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--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_TX is
Generic (
CLK_DIV_VAL : integer := 16;
PARITY_BIT : string := "none" -- type of parity: "none", "even", "odd", "mark", "space"
);
Port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- UART INTERFACE
UART_CLK_EN : in std_logic; -- oversampling (16x) UART clock enable
UART_TXD : out std_logic; -- serial transmit data
-- USER DATA INPUT INTERFACE
DIN : in std_logic_vector(7 downto 0); -- input data to be transmitted over UART
DIN_VLD : in std_logic; -- when DIN_VLD = 1, input data (DIN) are valid
DIN_RDY : out std_logic -- when DIN_RDY = 1, transmitter is ready and valid input data will be accepted for transmiting
);
end entity;
architecture RTL of UART_TX is
signal tx_clk_en : std_logic;
signal tx_clk_div_clr : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
signal tx_bit_count : unsigned(2 downto 0);
signal tx_bit_count_en : std_logic;
signal tx_ready : std_logic;
signal tx_parity_bit : std_logic;
signal tx_data_out_sel : std_logic_vector(1 downto 0);
type state is (idle, txsync, startbit, databits, paritybit, stopbit);
signal tx_pstate : state;
signal tx_nstate : state;
begin
DIN_RDY <= tx_ready;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER CLOCK DIVIDER AND CLOCK ENABLE FLAG
-- -------------------------------------------------------------------------
tx_clk_divider_i : entity work.UART_CLK_DIV
generic map(
DIV_MAX_VAL => CLK_DIV_VAL,
DIV_MARK_POS => 1
)
port map (
CLK => CLK,
RST => RST,
CLEAR => tx_clk_div_clr,
ENABLE => UART_CLK_EN,
DIV_MARK => tx_clk_en
);
-- -------------------------------------------------------------------------
-- UART TRANSMITTER INPUT DATA REGISTER
-- -------------------------------------------------------------------------
uart_tx_input_data_reg_p : process (CLK)
begin
if (rising_edge(CLK)) then
if (DIN_VLD = '1' AND tx_ready = '1') then
tx_data <= DIN;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER BIT COUNTER
-- -------------------------------------------------------------------------
uart_tx_bit_counter_p : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_bit_count <= (others => '0');
elsif (tx_bit_count_en = '1' AND tx_clk_en = '1') then
if (tx_bit_count = "111") then
tx_bit_count <= (others => '0');
else
tx_bit_count <= tx_bit_count + 1;
end if;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER PARITY GENERATOR
-- -------------------------------------------------------------------------
uart_tx_parity_g : if (PARITY_BIT /= "none") generate
uart_tx_parity_gen_i: entity work.UART_PARITY
generic map (
DATA_WIDTH => 8,
PARITY_TYPE => PARITY_BIT
)
port map (
DATA_IN => tx_data,
PARITY_OUT => tx_parity_bit
);
end generate;
uart_tx_noparity_g : if (PARITY_BIT = "none") generate
tx_parity_bit <= '0';
end generate;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER OUTPUT DATA REGISTER
-- -------------------------------------------------------------------------
uart_tx_output_data_reg_p : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
UART_TXD <= '1';
else
case tx_data_out_sel is
when "01" => -- START BIT
UART_TXD <= '0';
when "10" => -- DATA BITS
UART_TXD <= tx_data(to_integer(tx_bit_count));
when "11" => -- PARITY BIT
UART_TXD <= tx_parity_bit;
when others => -- STOP BIT OR IDLE
UART_TXD <= '1';
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER FSM
-- -------------------------------------------------------------------------
-- PRESENT STATE REGISTER
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_pstate <= idle;
else
tx_pstate <= tx_nstate;
end if;
end if;
end process;
-- NEXT STATE AND OUTPUTS LOGIC
process (tx_pstate, DIN_VLD, tx_clk_en, tx_bit_count)
begin
case tx_pstate is
when idle =>
tx_ready <= '1';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '1';
if (DIN_VLD = '1') then
tx_nstate <= txsync;
else
tx_nstate <= idle;
end if;
when txsync =>
tx_ready <= '0';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '0';
if (tx_clk_en = '1') then
tx_nstate <= startbit;
else
tx_nstate <= txsync;
end if;
when startbit =>
tx_ready <= '0';
tx_data_out_sel <= "01";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '0';
if (tx_clk_en = '1') then
tx_nstate <= databits;
else
tx_nstate <= startbit;
end if;
when databits =>
tx_ready <= '0';
tx_data_out_sel <= "10";
tx_bit_count_en <= '1';
tx_clk_div_clr <= '0';
if ((tx_clk_en = '1') AND (tx_bit_count = "111")) then
if (PARITY_BIT = "none") then
tx_nstate <= stopbit;
else
tx_nstate <= paritybit;
end if ;
else
tx_nstate <= databits;
end if;
when paritybit =>
tx_ready <= '0';
tx_data_out_sel <= "11";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '0';
if (tx_clk_en = '1') then
tx_nstate <= stopbit;
else
tx_nstate <= paritybit;
end if;
when stopbit =>
tx_ready <= '1';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '0';
if (DIN_VLD = '1') then
tx_nstate <= txsync;
elsif (tx_clk_en = '1') then
tx_nstate <= idle;
else
tx_nstate <= stopbit;
end if;
when others =>
tx_ready <= '0';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '0';
tx_nstate <= idle;
end case;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- PROJECT: SIMPLE UART FOR FPGA
--------------------------------------------------------------------------------
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_TX is
Generic (
CLK_DIV_VAL : integer := 16;
PARITY_BIT : string := "none" -- type of parity: "none", "even", "odd", "mark", "space"
);
Port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- UART INTERFACE
UART_CLK_EN : in std_logic; -- oversampling (16x) UART clock enable
UART_TXD : out std_logic; -- serial transmit data
-- USER DATA INPUT INTERFACE
DIN : in std_logic_vector(7 downto 0); -- input data to be transmitted over UART
DIN_VLD : in std_logic; -- when DIN_VLD = 1, input data (DIN) are valid
DIN_RDY : out std_logic -- when DIN_RDY = 1, transmitter is ready and valid input data will be accepted for transmiting
);
end entity;
architecture RTL of UART_TX is
signal tx_clk_en : std_logic;
signal tx_clk_div_clr : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
signal tx_bit_count : unsigned(2 downto 0);
signal tx_bit_count_en : std_logic;
signal tx_ready : std_logic;
signal tx_parity_bit : std_logic;
signal tx_data_out_sel : std_logic_vector(1 downto 0);
type state is (idle, txsync, startbit, databits, paritybit, stopbit);
signal tx_pstate : state;
signal tx_nstate : state;
begin
DIN_RDY <= tx_ready;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER CLOCK DIVIDER AND CLOCK ENABLE FLAG
-- -------------------------------------------------------------------------
tx_clk_divider_i : entity work.UART_CLK_DIV
generic map(
DIV_MAX_VAL => CLK_DIV_VAL,
DIV_MARK_POS => 1
)
port map (
CLK => CLK,
RST => RST,
CLEAR => tx_clk_div_clr,
ENABLE => UART_CLK_EN,
DIV_MARK => tx_clk_en
);
-- -------------------------------------------------------------------------
-- UART TRANSMITTER INPUT DATA REGISTER
-- -------------------------------------------------------------------------
uart_tx_input_data_reg_p : process (CLK)
begin
if (rising_edge(CLK)) then
if (DIN_VLD = '1' AND tx_ready = '1') then
tx_data <= DIN;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER BIT COUNTER
-- -------------------------------------------------------------------------
uart_tx_bit_counter_p : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_bit_count <= (others => '0');
elsif (tx_bit_count_en = '1' AND tx_clk_en = '1') then
if (tx_bit_count = "111") then
tx_bit_count <= (others => '0');
else
tx_bit_count <= tx_bit_count + 1;
end if;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER PARITY GENERATOR
-- -------------------------------------------------------------------------
uart_tx_parity_g : if (PARITY_BIT /= "none") generate
uart_tx_parity_gen_i: entity work.UART_PARITY
generic map (
DATA_WIDTH => 8,
PARITY_TYPE => PARITY_BIT
)
port map (
DATA_IN => tx_data,
PARITY_OUT => tx_parity_bit
);
end generate;
uart_tx_noparity_g : if (PARITY_BIT = "none") generate
tx_parity_bit <= '0';
end generate;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER OUTPUT DATA REGISTER
-- -------------------------------------------------------------------------
uart_tx_output_data_reg_p : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
UART_TXD <= '1';
else
case tx_data_out_sel is
when "01" => -- START BIT
UART_TXD <= '0';
when "10" => -- DATA BITS
UART_TXD <= tx_data(to_integer(tx_bit_count));
when "11" => -- PARITY BIT
UART_TXD <= tx_parity_bit;
when others => -- STOP BIT OR IDLE
UART_TXD <= '1';
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- UART TRANSMITTER FSM
-- -------------------------------------------------------------------------
-- PRESENT STATE REGISTER
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
tx_pstate <= idle;
else
tx_pstate <= tx_nstate;
end if;
end if;
end process;
-- NEXT STATE AND OUTPUTS LOGIC
process (tx_pstate, DIN_VLD, tx_clk_en, tx_bit_count)
begin
case tx_pstate is
when idle =>
tx_ready <= '1';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '1';
if (DIN_VLD = '1') then
tx_nstate <= txsync;
else
tx_nstate <= idle;
end if;
when txsync =>
tx_ready <= '0';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '0';
if (tx_clk_en = '1') then
tx_nstate <= startbit;
else
tx_nstate <= txsync;
end if;
when startbit =>
tx_ready <= '0';
tx_data_out_sel <= "01";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '0';
if (tx_clk_en = '1') then
tx_nstate <= databits;
else
tx_nstate <= startbit;
end if;
when databits =>
tx_ready <= '0';
tx_data_out_sel <= "10";
tx_bit_count_en <= '1';
tx_clk_div_clr <= '0';
if ((tx_clk_en = '1') AND (tx_bit_count = "111")) then
if (PARITY_BIT = "none") then
tx_nstate <= stopbit;
else
tx_nstate <= paritybit;
end if ;
else
tx_nstate <= databits;
end if;
when paritybit =>
tx_ready <= '0';
tx_data_out_sel <= "11";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '0';
if (tx_clk_en = '1') then
tx_nstate <= stopbit;
else
tx_nstate <= paritybit;
end if;
when stopbit =>
tx_ready <= '1';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '0';
if (DIN_VLD = '1') then
tx_nstate <= txsync;
elsif (tx_clk_en = '1') then
tx_nstate <= idle;
else
tx_nstate <= stopbit;
end if;
when others =>
tx_ready <= '0';
tx_data_out_sel <= "00";
tx_bit_count_en <= '0';
tx_clk_div_clr <= '0';
tx_nstate <= idle;
end case;
end process;
end architecture;
|
component wasca is
port (
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
altpll_0_locked_conduit_export : out std_logic; -- export
altpll_0_phasedone_conduit_export : out std_logic; -- export
clk_clk : in std_logic := 'X'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- ba
external_sdram_controller_wire_cas_n : out std_logic; -- cas_n
external_sdram_controller_wire_cke : out std_logic; -- cke
external_sdram_controller_wire_cs_n : out std_logic; -- cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
external_sdram_controller_wire_ras_n : out std_logic; -- ras_n
external_sdram_controller_wire_we_n : out std_logic; -- we_n
pio_0_external_connection_export : inout std_logic_vector(3 downto 0) := (others => 'X'); -- export
sd_mmc_controller_0_sd_card_io_sd_clk_o_pad : out std_logic; -- sd_clk_o_pad
sd_mmc_controller_0_sd_card_io_sd_cmd_dat_i : in std_logic := 'X'; -- sd_cmd_dat_i
sd_mmc_controller_0_sd_card_io_sd_cmd_oe_o : out std_logic; -- sd_cmd_oe_o
sd_mmc_controller_0_sd_card_io_sd_cmd_out_o : out std_logic; -- sd_cmd_out_o
sd_mmc_controller_0_sd_card_io_sd_dat_dat_i : in std_logic_vector(3 downto 0) := (others => 'X'); -- sd_dat_dat_i
sd_mmc_controller_0_sd_card_io_sd_dat_oe_o : out std_logic; -- sd_dat_oe_o
sd_mmc_controller_0_sd_card_io_sd_dat_out_o : out std_logic_vector(3 downto 0); -- sd_dat_out_o
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := 'X'; -- read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write
sega_saturn_abus_slave_0_abus_functioncode : in std_logic_vector(1 downto 0) := (others => 'X'); -- functioncode
sega_saturn_abus_slave_0_abus_timing : in std_logic_vector(2 downto 0) := (others => 'X'); -- timing
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- waitrequest
sega_saturn_abus_slave_0_abus_addressstrobe : in std_logic := 'X'; -- addressstrobe
sega_saturn_abus_slave_0_abus_interrupt : out std_logic; -- interrupt
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
sega_saturn_abus_slave_0_abus_direction : out std_logic; -- direction
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
sega_saturn_abus_slave_0_abus_disableout : out std_logic; -- disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := 'X'; -- saturn_reset
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic -- txd
);
end component wasca;
u0 : component wasca
port map (
altpll_0_areset_conduit_export => CONNECTED_TO_altpll_0_areset_conduit_export, -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export => CONNECTED_TO_altpll_0_locked_conduit_export, -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export => CONNECTED_TO_altpll_0_phasedone_conduit_export, -- altpll_0_phasedone_conduit.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clock_116_mhz_clk => CONNECTED_TO_clock_116_mhz_clk, -- clock_116_mhz.clk
external_sdram_controller_wire_addr => CONNECTED_TO_external_sdram_controller_wire_addr, -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba => CONNECTED_TO_external_sdram_controller_wire_ba, -- .ba
external_sdram_controller_wire_cas_n => CONNECTED_TO_external_sdram_controller_wire_cas_n, -- .cas_n
external_sdram_controller_wire_cke => CONNECTED_TO_external_sdram_controller_wire_cke, -- .cke
external_sdram_controller_wire_cs_n => CONNECTED_TO_external_sdram_controller_wire_cs_n, -- .cs_n
external_sdram_controller_wire_dq => CONNECTED_TO_external_sdram_controller_wire_dq, -- .dq
external_sdram_controller_wire_dqm => CONNECTED_TO_external_sdram_controller_wire_dqm, -- .dqm
external_sdram_controller_wire_ras_n => CONNECTED_TO_external_sdram_controller_wire_ras_n, -- .ras_n
external_sdram_controller_wire_we_n => CONNECTED_TO_external_sdram_controller_wire_we_n, -- .we_n
pio_0_external_connection_export => CONNECTED_TO_pio_0_external_connection_export, -- pio_0_external_connection.export
sd_mmc_controller_0_sd_card_io_sd_clk_o_pad => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_clk_o_pad, -- sd_mmc_controller_0_sd_card_io.sd_clk_o_pad
sd_mmc_controller_0_sd_card_io_sd_cmd_dat_i => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_cmd_dat_i, -- .sd_cmd_dat_i
sd_mmc_controller_0_sd_card_io_sd_cmd_oe_o => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_cmd_oe_o, -- .sd_cmd_oe_o
sd_mmc_controller_0_sd_card_io_sd_cmd_out_o => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_cmd_out_o, -- .sd_cmd_out_o
sd_mmc_controller_0_sd_card_io_sd_dat_dat_i => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_dat_dat_i, -- .sd_dat_dat_i
sd_mmc_controller_0_sd_card_io_sd_dat_oe_o => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_dat_oe_o, -- .sd_dat_oe_o
sd_mmc_controller_0_sd_card_io_sd_dat_out_o => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_dat_out_o, -- .sd_dat_out_o
sega_saturn_abus_slave_0_abus_address => CONNECTED_TO_sega_saturn_abus_slave_0_abus_address, -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_chipselect => CONNECTED_TO_sega_saturn_abus_slave_0_abus_chipselect, -- .chipselect
sega_saturn_abus_slave_0_abus_read => CONNECTED_TO_sega_saturn_abus_slave_0_abus_read, -- .read
sega_saturn_abus_slave_0_abus_write => CONNECTED_TO_sega_saturn_abus_slave_0_abus_write, -- .write
sega_saturn_abus_slave_0_abus_functioncode => CONNECTED_TO_sega_saturn_abus_slave_0_abus_functioncode, -- .functioncode
sega_saturn_abus_slave_0_abus_timing => CONNECTED_TO_sega_saturn_abus_slave_0_abus_timing, -- .timing
sega_saturn_abus_slave_0_abus_waitrequest => CONNECTED_TO_sega_saturn_abus_slave_0_abus_waitrequest, -- .waitrequest
sega_saturn_abus_slave_0_abus_addressstrobe => CONNECTED_TO_sega_saturn_abus_slave_0_abus_addressstrobe, -- .addressstrobe
sega_saturn_abus_slave_0_abus_interrupt => CONNECTED_TO_sega_saturn_abus_slave_0_abus_interrupt, -- .interrupt
sega_saturn_abus_slave_0_abus_addressdata => CONNECTED_TO_sega_saturn_abus_slave_0_abus_addressdata, -- .addressdata
sega_saturn_abus_slave_0_abus_direction => CONNECTED_TO_sega_saturn_abus_slave_0_abus_direction, -- .direction
sega_saturn_abus_slave_0_abus_muxing => CONNECTED_TO_sega_saturn_abus_slave_0_abus_muxing, -- .muxing
sega_saturn_abus_slave_0_abus_disableout => CONNECTED_TO_sega_saturn_abus_slave_0_abus_disableout, -- .disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset => CONNECTED_TO_sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset, -- sega_saturn_abus_slave_0_conduit_saturn_reset.saturn_reset
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd -- .txd
);
|
-- Vhdl test bench created from schematic /home/emmanuel/current_projects/Xilinx/Workspace/cpu_mips32/ALU_control.sch - Mon May 14 15:21:40 2012
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY ALU_control_ALU_control_sch_tb IS
END ALU_control_ALU_control_sch_tb;
ARCHITECTURE behavioral OF ALU_control_ALU_control_sch_tb IS
COMPONENT ALU_control
PORT( Instruction : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
Operation : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
ALUOp : IN STD_LOGIC_VECTOR (2 DOWNTO 0));
END COMPONENT;
SIGNAL Instruction : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL Operation : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL ALUOp : STD_LOGIC_VECTOR (2 DOWNTO 0);
BEGIN
UUT: ALU_control PORT MAP(
Instruction => Instruction,
Operation => Operation,
ALUOp => ALUOp
);
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
Instruction <= "000000";
-- Test lw/sw => 0010
ALUOp <= "000";
wait for 1ms;
-- Test beq => 0110
ALUOp <= "001";
wait for 1ms;
-- Test andi => 0000
ALUOp <= "100";
wait for 1ms;
-- Test ori => 0001
ALUOp <= "101";
wait for 1ms;
-- Test R instruction
ALUOp <= "010";
-- Test or => 0001
Instruction <= "100101";
wait for 1ms;
-- Test slt => 0111
Instruction <= "101010";
wait for 1ms;
-- Test xor => 0011
Instruction <= "100111";
wait for 1ms;
-- Test add => 0010
Instruction <= "100000";
wait for 1ms;
-- Test sub => 0110
Instruction <= "100010";
wait for 1ms;
-- Test and => 0000
Instruction <= "100100";
wait for 1ms;
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
|
library ieee;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity spi_reader is
port (
clock : in std_logic ;
sclk : out std_logic ;
miso : in std_logic ;
mosi : out std_logic ;
enx : out std_logic ;
reset_out : out std_logic
) ;
end entity ;
architecture arch of spi_reader is
constant RESET_CYCLES : natural := 1000 ;
constant ENX_WAIT_CYCLES : natural := 10 ;
constant WRITE_BIT_COUNT : natural := 7 ;
constant READ_BIT_COUNT : natural := 8 ;
constant TOTAL_BIT_COUNT : natural := WRITE_BIT_COUNT + READ_BIT_COUNT ;
type command_t is (COMMAND_READ, COMMAND_WRITE) ;
type fsm_t is (RESET, WAITING, FALLING_SCLK, RISING_SCLK) ;
signal fsm : fsm_t ;
constant command : command_t := COMMAND_READ ;
signal spi_address : unsigned(6 downto 0) := (others =>'0') ;
begin
reader : process(all)
variable count : natural range 0 to 1000 := 0 ;
variable address : unsigned(6 downto 0) := (others =>'0') ;
variable wdata : unsigned(7 downto 0) ;
variable rdata : unsigned(7 downto 0) ;
begin
if( rising_edge(clock) ) then
enx <= '0' ;
reset_out <= '1' ;
case fsm is
when RESET =>
reset_out <= '0' ;
spi_address <= (others =>'0') ;
if( count = 0 ) then
fsm <= WAITING ;
count := ENX_WAIT_CYCLES ;
else
count := count - 1 ;
end if ;
when WAITING =>
sclk <= '1' ;
enx <= '1' ;
if( spi_address = 127 ) then
spi_address <= (others =>'0') ;
fsm <= RESET ;
count := RESET_CYCLES ;
end if ;
if( count = 0 ) then
count := TOTAL_BIT_COUNT ;
fsm <= FALLING_SCLK ;
address := spi_address ;
spi_address <= spi_address + 1;
else
count := count - 1 ;
end if ;
when FALLING_SCLK =>
sclk <= '0' ;
fsm <= RISING_SCLK ;
if( command = COMMAND_READ ) then
if( count = TOTAL_BIT_COUNT ) then
mosi <= '0' ;
elsif( count < TOTAL_BIT_COUNT - WRITE_BIT_COUNT ) then
mosi <= '0' ;
else
mosi <= address(address'high) ;
address := shift_left(address,1) ;
end if ;
else
if( count = TOTAL_BIT_COUNT ) then
mosi <= '1' ;
elsif( count < TOTAL_BIT_COUNT - WRITE_BIT_COUNT ) then
mosi <= wdata(wdata'high) ;
wdata := shift_left(wdata,1) ;
else
mosi <= address(address'high) ;
address := shift_left(address,1) ;
end if ;
end if ;
when RISING_SCLK =>
sclk <= '1' ;
if( command = COMMAND_READ ) then
if( count < TOTAL_BIT_COUNT - WRITE_BIT_COUNT ) then
rdata := rdata(rdata'high-1 downto 0) & miso ;
end if ;
end if ;
if( count = 0 ) then
fsm <= WAITING ;
count := ENX_WAIT_CYCLES ;
else
count := count - 1 ;
fsm <= FALLING_SCLK ;
end if ;
end case ;
end if ;
end process ;
end architecture ;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter is
port (
INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
INPUT_STREAM_TVALID : IN STD_LOGIC;
INPUT_STREAM_TREADY : OUT STD_LOGIC;
OUTPUT_STREAM_TVALID : OUT STD_LOGIC;
OUTPUT_STREAM_TREADY : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC );
end;
architecture behav of image_filter is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"image_filter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=6.666670,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=5.681000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=6,HLS_SYN_DSP=4,HLS_SYN_FF=1026,HLS_SYN_LUT=1358}";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_true : BOOLEAN := true;
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_logic_1 : STD_LOGIC := '1';
signal ap_rst_n_inv : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_start : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_done : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_continue : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_idle : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_ready : STD_LOGIC;
signal image_filter_Block_proc_U0_rows : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Block_proc_U0_cols : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Block_proc_U0_ap_return_0 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_1 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_2 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_3 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel : STD_LOGIC;
signal img_0_rows_V_channel_full_n : STD_LOGIC;
signal ap_reg_ready_img_0_rows_V_channel_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_0_rows_V_channel_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V : STD_LOGIC;
signal img_1_rows_V_full_n : STD_LOGIC;
signal ap_reg_ready_img_1_rows_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_1_rows_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V : STD_LOGIC;
signal img_1_cols_V_full_n : STD_LOGIC;
signal ap_reg_ready_img_1_cols_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_1_cols_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel : STD_LOGIC;
signal img_0_cols_V_channel_full_n : STD_LOGIC;
signal ap_reg_ready_img_0_cols_V_channel_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_0_cols_V_channel_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_start : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_done : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_continue : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_idle : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_ready : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_start : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_done : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_continue : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_idle : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_ready : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_rows : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Loop_1_proc_U0_cols : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_empty_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_read : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_empty_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_read : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_empty_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_read : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_full_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_write : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_full_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_write : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_full_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_write : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_start : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_done : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_continue : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_idle : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_ready : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_hs_continue : STD_LOGIC;
signal img_0_rows_V_channel_U_ap_dummy_ce : STD_LOGIC;
signal img_0_rows_V_channel_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_rows_V_channel_write : STD_LOGIC;
signal img_0_rows_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_rows_V_channel_empty_n : STD_LOGIC;
signal img_0_rows_V_channel_read : STD_LOGIC;
signal img_0_cols_V_channel_U_ap_dummy_ce : STD_LOGIC;
signal img_0_cols_V_channel_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_cols_V_channel_write : STD_LOGIC;
signal img_0_cols_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_cols_V_channel_empty_n : STD_LOGIC;
signal img_0_cols_V_channel_read : STD_LOGIC;
signal img_1_rows_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_rows_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_rows_V_write : STD_LOGIC;
signal img_1_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_rows_V_empty_n : STD_LOGIC;
signal img_1_rows_V_read : STD_LOGIC;
signal img_1_cols_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_cols_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_cols_V_write : STD_LOGIC;
signal img_1_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_cols_V_empty_n : STD_LOGIC;
signal img_1_cols_V_read : STD_LOGIC;
signal img_0_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC;
signal img_0_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_0_V_full_n : STD_LOGIC;
signal img_0_data_stream_0_V_write : STD_LOGIC;
signal img_0_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_0_V_empty_n : STD_LOGIC;
signal img_0_data_stream_0_V_read : STD_LOGIC;
signal img_0_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC;
signal img_0_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_1_V_full_n : STD_LOGIC;
signal img_0_data_stream_1_V_write : STD_LOGIC;
signal img_0_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_1_V_empty_n : STD_LOGIC;
signal img_0_data_stream_1_V_read : STD_LOGIC;
signal img_0_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC;
signal img_0_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_2_V_full_n : STD_LOGIC;
signal img_0_data_stream_2_V_write : STD_LOGIC;
signal img_0_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_2_V_empty_n : STD_LOGIC;
signal img_0_data_stream_2_V_read : STD_LOGIC;
signal img_1_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_0_V_full_n : STD_LOGIC;
signal img_1_data_stream_0_V_write : STD_LOGIC;
signal img_1_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_0_V_empty_n : STD_LOGIC;
signal img_1_data_stream_0_V_read : STD_LOGIC;
signal img_1_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_1_V_full_n : STD_LOGIC;
signal img_1_data_stream_1_V_write : STD_LOGIC;
signal img_1_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_1_V_empty_n : STD_LOGIC;
signal img_1_data_stream_1_V_read : STD_LOGIC;
signal img_1_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_2_V_full_n : STD_LOGIC;
signal img_1_data_stream_2_V_write : STD_LOGIC;
signal img_1_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_2_V_empty_n : STD_LOGIC;
signal img_1_data_stream_2_V_read : STD_LOGIC;
signal ap_reg_procdone_image_filter_Block_proc_U0 : STD_LOGIC := '0';
signal ap_sig_hs_done : STD_LOGIC;
signal ap_reg_procdone_image_filter_AXIvideo2Mat_U0 : STD_LOGIC := '0';
signal ap_reg_procdone_image_filter_Loop_1_proc_U0 : STD_LOGIC := '0';
signal ap_reg_procdone_image_filter_Mat2AXIvideo_U0 : STD_LOGIC := '0';
signal ap_CS : STD_LOGIC;
signal ap_sig_top_allready : STD_LOGIC;
component image_filter_Block_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0) );
end component;
component image_filter_AXIvideo2Mat IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
INPUT_STREAM_TVALID : IN STD_LOGIC;
INPUT_STREAM_TREADY : OUT STD_LOGIC;
INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC );
end component;
component image_filter_Loop_1_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
img_0_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_0_data_stream_0_V_empty_n : IN STD_LOGIC;
img_0_data_stream_0_V_read : OUT STD_LOGIC;
img_0_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_0_data_stream_1_V_empty_n : IN STD_LOGIC;
img_0_data_stream_1_V_read : OUT STD_LOGIC;
img_0_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_0_data_stream_2_V_empty_n : IN STD_LOGIC;
img_0_data_stream_2_V_read : OUT STD_LOGIC;
img_1_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_1_data_stream_0_V_full_n : IN STD_LOGIC;
img_1_data_stream_0_V_write : OUT STD_LOGIC;
img_1_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_1_data_stream_1_V_full_n : IN STD_LOGIC;
img_1_data_stream_1_V_write : OUT STD_LOGIC;
img_1_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_1_data_stream_2_V_full_n : IN STD_LOGIC;
img_1_data_stream_2_V_write : OUT STD_LOGIC );
end component;
component image_filter_Mat2AXIvideo IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_empty_n : IN STD_LOGIC;
img_data_stream_0_V_read : OUT STD_LOGIC;
img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_empty_n : IN STD_LOGIC;
img_data_stream_1_V_read : OUT STD_LOGIC;
img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_empty_n : IN STD_LOGIC;
img_data_stream_2_V_read : OUT STD_LOGIC;
OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
OUTPUT_STREAM_TVALID : OUT STD_LOGIC;
OUTPUT_STREAM_TREADY : IN STD_LOGIC;
OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component FIFO_image_filter_img_0_rows_V_channel IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_cols_V_channel IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_rows_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_cols_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_data_stream_0_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_data_stream_1_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_data_stream_2_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_data_stream_0_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_data_stream_1_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_data_stream_2_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
begin
image_filter_Block_proc_U0 : component image_filter_Block_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Block_proc_U0_ap_start,
ap_done => image_filter_Block_proc_U0_ap_done,
ap_continue => image_filter_Block_proc_U0_ap_continue,
ap_idle => image_filter_Block_proc_U0_ap_idle,
ap_ready => image_filter_Block_proc_U0_ap_ready,
rows => image_filter_Block_proc_U0_rows,
cols => image_filter_Block_proc_U0_cols,
ap_return_0 => image_filter_Block_proc_U0_ap_return_0,
ap_return_1 => image_filter_Block_proc_U0_ap_return_1,
ap_return_2 => image_filter_Block_proc_U0_ap_return_2,
ap_return_3 => image_filter_Block_proc_U0_ap_return_3);
image_filter_AXIvideo2Mat_U0 : component image_filter_AXIvideo2Mat
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_AXIvideo2Mat_U0_ap_start,
ap_done => image_filter_AXIvideo2Mat_U0_ap_done,
ap_continue => image_filter_AXIvideo2Mat_U0_ap_continue,
ap_idle => image_filter_AXIvideo2Mat_U0_ap_idle,
ap_ready => image_filter_AXIvideo2Mat_U0_ap_ready,
INPUT_STREAM_TDATA => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA,
INPUT_STREAM_TVALID => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY,
INPUT_STREAM_TKEEP => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB,
INPUT_STREAM_TUSER => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER,
INPUT_STREAM_TLAST => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST,
INPUT_STREAM_TID => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID,
INPUT_STREAM_TDEST => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST,
img_rows_V_read => image_filter_AXIvideo2Mat_U0_img_rows_V_read,
img_cols_V_read => image_filter_AXIvideo2Mat_U0_img_cols_V_read,
img_data_stream_0_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din,
img_data_stream_0_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n,
img_data_stream_0_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write,
img_data_stream_1_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din,
img_data_stream_1_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n,
img_data_stream_1_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write,
img_data_stream_2_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din,
img_data_stream_2_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n,
img_data_stream_2_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write);
image_filter_Loop_1_proc_U0 : component image_filter_Loop_1_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Loop_1_proc_U0_ap_start,
ap_done => image_filter_Loop_1_proc_U0_ap_done,
ap_continue => image_filter_Loop_1_proc_U0_ap_continue,
ap_idle => image_filter_Loop_1_proc_U0_ap_idle,
ap_ready => image_filter_Loop_1_proc_U0_ap_ready,
rows => image_filter_Loop_1_proc_U0_rows,
cols => image_filter_Loop_1_proc_U0_cols,
img_0_data_stream_0_V_dout => image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_dout,
img_0_data_stream_0_V_empty_n => image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_empty_n,
img_0_data_stream_0_V_read => image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_read,
img_0_data_stream_1_V_dout => image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_dout,
img_0_data_stream_1_V_empty_n => image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_empty_n,
img_0_data_stream_1_V_read => image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_read,
img_0_data_stream_2_V_dout => image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_dout,
img_0_data_stream_2_V_empty_n => image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_empty_n,
img_0_data_stream_2_V_read => image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_read,
img_1_data_stream_0_V_din => image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_din,
img_1_data_stream_0_V_full_n => image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_full_n,
img_1_data_stream_0_V_write => image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_write,
img_1_data_stream_1_V_din => image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_din,
img_1_data_stream_1_V_full_n => image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_full_n,
img_1_data_stream_1_V_write => image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_write,
img_1_data_stream_2_V_din => image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_din,
img_1_data_stream_2_V_full_n => image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_full_n,
img_1_data_stream_2_V_write => image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_write);
image_filter_Mat2AXIvideo_U0 : component image_filter_Mat2AXIvideo
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Mat2AXIvideo_U0_ap_start,
ap_done => image_filter_Mat2AXIvideo_U0_ap_done,
ap_continue => image_filter_Mat2AXIvideo_U0_ap_continue,
ap_idle => image_filter_Mat2AXIvideo_U0_ap_idle,
ap_ready => image_filter_Mat2AXIvideo_U0_ap_ready,
img_rows_V_read => image_filter_Mat2AXIvideo_U0_img_rows_V_read,
img_cols_V_read => image_filter_Mat2AXIvideo_U0_img_cols_V_read,
img_data_stream_0_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout,
img_data_stream_0_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n,
img_data_stream_0_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read,
img_data_stream_1_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout,
img_data_stream_1_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n,
img_data_stream_1_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read,
img_data_stream_2_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout,
img_data_stream_2_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n,
img_data_stream_2_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read,
OUTPUT_STREAM_TDATA => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TVALID => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY,
OUTPUT_STREAM_TKEEP => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID,
OUTPUT_STREAM_TDEST => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST);
img_0_rows_V_channel_U : component FIFO_image_filter_img_0_rows_V_channel
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_rows_V_channel_U_ap_dummy_ce,
if_write_ce => img_0_rows_V_channel_U_ap_dummy_ce,
if_din => img_0_rows_V_channel_din,
if_full_n => img_0_rows_V_channel_full_n,
if_write => img_0_rows_V_channel_write,
if_dout => img_0_rows_V_channel_dout,
if_empty_n => img_0_rows_V_channel_empty_n,
if_read => img_0_rows_V_channel_read);
img_0_cols_V_channel_U : component FIFO_image_filter_img_0_cols_V_channel
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_cols_V_channel_U_ap_dummy_ce,
if_write_ce => img_0_cols_V_channel_U_ap_dummy_ce,
if_din => img_0_cols_V_channel_din,
if_full_n => img_0_cols_V_channel_full_n,
if_write => img_0_cols_V_channel_write,
if_dout => img_0_cols_V_channel_dout,
if_empty_n => img_0_cols_V_channel_empty_n,
if_read => img_0_cols_V_channel_read);
img_1_rows_V_U : component FIFO_image_filter_img_1_rows_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_rows_V_U_ap_dummy_ce,
if_write_ce => img_1_rows_V_U_ap_dummy_ce,
if_din => img_1_rows_V_din,
if_full_n => img_1_rows_V_full_n,
if_write => img_1_rows_V_write,
if_dout => img_1_rows_V_dout,
if_empty_n => img_1_rows_V_empty_n,
if_read => img_1_rows_V_read);
img_1_cols_V_U : component FIFO_image_filter_img_1_cols_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_cols_V_U_ap_dummy_ce,
if_write_ce => img_1_cols_V_U_ap_dummy_ce,
if_din => img_1_cols_V_din,
if_full_n => img_1_cols_V_full_n,
if_write => img_1_cols_V_write,
if_dout => img_1_cols_V_dout,
if_empty_n => img_1_cols_V_empty_n,
if_read => img_1_cols_V_read);
img_0_data_stream_0_V_U : component FIFO_image_filter_img_0_data_stream_0_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_data_stream_0_V_U_ap_dummy_ce,
if_write_ce => img_0_data_stream_0_V_U_ap_dummy_ce,
if_din => img_0_data_stream_0_V_din,
if_full_n => img_0_data_stream_0_V_full_n,
if_write => img_0_data_stream_0_V_write,
if_dout => img_0_data_stream_0_V_dout,
if_empty_n => img_0_data_stream_0_V_empty_n,
if_read => img_0_data_stream_0_V_read);
img_0_data_stream_1_V_U : component FIFO_image_filter_img_0_data_stream_1_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_data_stream_1_V_U_ap_dummy_ce,
if_write_ce => img_0_data_stream_1_V_U_ap_dummy_ce,
if_din => img_0_data_stream_1_V_din,
if_full_n => img_0_data_stream_1_V_full_n,
if_write => img_0_data_stream_1_V_write,
if_dout => img_0_data_stream_1_V_dout,
if_empty_n => img_0_data_stream_1_V_empty_n,
if_read => img_0_data_stream_1_V_read);
img_0_data_stream_2_V_U : component FIFO_image_filter_img_0_data_stream_2_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_data_stream_2_V_U_ap_dummy_ce,
if_write_ce => img_0_data_stream_2_V_U_ap_dummy_ce,
if_din => img_0_data_stream_2_V_din,
if_full_n => img_0_data_stream_2_V_full_n,
if_write => img_0_data_stream_2_V_write,
if_dout => img_0_data_stream_2_V_dout,
if_empty_n => img_0_data_stream_2_V_empty_n,
if_read => img_0_data_stream_2_V_read);
img_1_data_stream_0_V_U : component FIFO_image_filter_img_1_data_stream_0_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_data_stream_0_V_U_ap_dummy_ce,
if_write_ce => img_1_data_stream_0_V_U_ap_dummy_ce,
if_din => img_1_data_stream_0_V_din,
if_full_n => img_1_data_stream_0_V_full_n,
if_write => img_1_data_stream_0_V_write,
if_dout => img_1_data_stream_0_V_dout,
if_empty_n => img_1_data_stream_0_V_empty_n,
if_read => img_1_data_stream_0_V_read);
img_1_data_stream_1_V_U : component FIFO_image_filter_img_1_data_stream_1_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_data_stream_1_V_U_ap_dummy_ce,
if_write_ce => img_1_data_stream_1_V_U_ap_dummy_ce,
if_din => img_1_data_stream_1_V_din,
if_full_n => img_1_data_stream_1_V_full_n,
if_write => img_1_data_stream_1_V_write,
if_dout => img_1_data_stream_1_V_dout,
if_empty_n => img_1_data_stream_1_V_empty_n,
if_read => img_1_data_stream_1_V_read);
img_1_data_stream_2_V_U : component FIFO_image_filter_img_1_data_stream_2_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_data_stream_2_V_U_ap_dummy_ce,
if_write_ce => img_1_data_stream_2_V_U_ap_dummy_ce,
if_din => img_1_data_stream_2_V_din,
if_full_n => img_1_data_stream_2_V_full_n,
if_write => img_1_data_stream_2_V_write,
if_dout => img_1_data_stream_2_V_dout,
if_empty_n => img_1_data_stream_2_V_empty_n,
if_read => img_1_data_stream_2_V_read);
-- ap_reg_procdone_image_filter_AXIvideo2Mat_U0 assign process. --
ap_reg_procdone_image_filter_AXIvideo2Mat_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_AXIvideo2Mat_U0_ap_done)) then
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Block_proc_U0 assign process. --
ap_reg_procdone_image_filter_Block_proc_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0;
elsif ((image_filter_Block_proc_U0_ap_done = ap_const_logic_1)) then
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Loop_1_proc_U0 assign process. --
ap_reg_procdone_image_filter_Loop_1_proc_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Loop_1_proc_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Loop_1_proc_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_Loop_1_proc_U0_ap_done)) then
ap_reg_procdone_image_filter_Loop_1_proc_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Mat2AXIvideo_U0 assign process. --
ap_reg_procdone_image_filter_Mat2AXIvideo_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_done)) then
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_0_cols_V_channel_full_n assign process. --
ap_reg_ready_img_0_cols_V_channel_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = img_0_cols_V_channel_full_n))) then
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_0_rows_V_channel_full_n assign process. --
ap_reg_ready_img_0_rows_V_channel_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (img_0_rows_V_channel_full_n = ap_const_logic_1))) then
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_1_cols_V_full_n assign process. --
ap_reg_ready_img_1_cols_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = img_1_cols_V_full_n))) then
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_1_rows_V_full_n assign process. --
ap_reg_ready_img_1_rows_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = img_1_rows_V_full_n))) then
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_CS assign process. --
ap_CS_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
ap_CS <= ap_const_logic_0;
end if;
end process;
INPUT_STREAM_TREADY <= image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY;
OUTPUT_STREAM_TDATA <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA;
OUTPUT_STREAM_TDEST <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST;
OUTPUT_STREAM_TID <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID;
OUTPUT_STREAM_TKEEP <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP;
OUTPUT_STREAM_TLAST <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST;
OUTPUT_STREAM_TSTRB <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB;
OUTPUT_STREAM_TUSER <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER;
OUTPUT_STREAM_TVALID <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID;
-- ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_0_cols_V_channel_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_img_0_cols_V_channel_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_0_rows_V_channel_full_n)
begin
if ((ap_reg_ready_img_0_rows_V_channel_full_n = ap_const_logic_1)) then
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_1_cols_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_img_1_cols_V_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_1_rows_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_img_1_rows_V_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
ap_done <= ap_sig_hs_done;
-- ap_idle assign process. --
ap_idle_assign_proc : process(image_filter_Block_proc_U0_ap_idle, image_filter_AXIvideo2Mat_U0_ap_idle, image_filter_Loop_1_proc_U0_ap_idle, image_filter_Mat2AXIvideo_U0_ap_idle, img_0_rows_V_channel_empty_n, img_0_cols_V_channel_empty_n, img_1_rows_V_empty_n, img_1_cols_V_empty_n)
begin
if (((image_filter_Block_proc_U0_ap_idle = ap_const_logic_1) and (ap_const_logic_1 = image_filter_AXIvideo2Mat_U0_ap_idle) and (ap_const_logic_1 = image_filter_Loop_1_proc_U0_ap_idle) and (ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_idle) and (ap_const_logic_0 = img_0_rows_V_channel_empty_n) and (ap_const_logic_0 = img_0_cols_V_channel_empty_n) and (ap_const_logic_0 = img_1_rows_V_empty_n) and (ap_const_logic_0 = img_1_cols_V_empty_n))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready <= ap_sig_top_allready;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sig_hs_continue <= ap_const_logic_1;
-- ap_sig_hs_done assign process. --
ap_sig_hs_done_assign_proc : process(image_filter_Mat2AXIvideo_U0_ap_done)
begin
if ((ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_done)) then
ap_sig_hs_done <= ap_const_logic_1;
else
ap_sig_hs_done <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ready_img_0_cols_V_channel_full_n assign process. --
ap_sig_ready_img_0_cols_V_channel_full_n_assign_proc : process(img_0_cols_V_channel_full_n, ap_reg_ready_img_0_cols_V_channel_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_img_0_cols_V_channel_full_n)) then
ap_sig_ready_img_0_cols_V_channel_full_n <= img_0_cols_V_channel_full_n;
else
ap_sig_ready_img_0_cols_V_channel_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_img_0_rows_V_channel_full_n assign process. --
ap_sig_ready_img_0_rows_V_channel_full_n_assign_proc : process(img_0_rows_V_channel_full_n, ap_reg_ready_img_0_rows_V_channel_full_n)
begin
if ((ap_reg_ready_img_0_rows_V_channel_full_n = ap_const_logic_0)) then
ap_sig_ready_img_0_rows_V_channel_full_n <= img_0_rows_V_channel_full_n;
else
ap_sig_ready_img_0_rows_V_channel_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_img_1_cols_V_full_n assign process. --
ap_sig_ready_img_1_cols_V_full_n_assign_proc : process(img_1_cols_V_full_n, ap_reg_ready_img_1_cols_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_img_1_cols_V_full_n)) then
ap_sig_ready_img_1_cols_V_full_n <= img_1_cols_V_full_n;
else
ap_sig_ready_img_1_cols_V_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_img_1_rows_V_full_n assign process. --
ap_sig_ready_img_1_rows_V_full_n_assign_proc : process(img_1_rows_V_full_n, ap_reg_ready_img_1_rows_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_img_1_rows_V_full_n)) then
ap_sig_ready_img_1_rows_V_full_n <= img_1_rows_V_full_n;
else
ap_sig_ready_img_1_rows_V_full_n <= ap_const_logic_1;
end if;
end process;
ap_sig_top_allready <= image_filter_AXIvideo2Mat_U0_ap_ready;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA <= INPUT_STREAM_TDATA;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST <= INPUT_STREAM_TDEST;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID <= INPUT_STREAM_TID;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP <= INPUT_STREAM_TKEEP;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST <= INPUT_STREAM_TLAST;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB <= INPUT_STREAM_TSTRB;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER <= INPUT_STREAM_TUSER;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID <= INPUT_STREAM_TVALID;
image_filter_AXIvideo2Mat_U0_ap_continue <= ap_const_logic_1;
image_filter_AXIvideo2Mat_U0_ap_start <= (ap_start and img_0_rows_V_channel_empty_n and img_0_cols_V_channel_empty_n);
image_filter_AXIvideo2Mat_U0_img_cols_V_read <= img_0_cols_V_channel_dout;
image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n <= img_0_data_stream_0_V_full_n;
image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n <= img_0_data_stream_1_V_full_n;
image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n <= img_0_data_stream_2_V_full_n;
image_filter_AXIvideo2Mat_U0_img_rows_V_read <= img_0_rows_V_channel_dout;
-- image_filter_Block_proc_U0_ap_continue assign process. --
image_filter_Block_proc_U0_ap_continue_assign_proc : process(ap_sig_ready_img_0_rows_V_channel_full_n, ap_sig_ready_img_1_rows_V_full_n, ap_sig_ready_img_1_cols_V_full_n, ap_sig_ready_img_0_cols_V_channel_full_n)
begin
if (((ap_sig_ready_img_0_rows_V_channel_full_n = ap_const_logic_1) and (ap_const_logic_1 = ap_sig_ready_img_1_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_img_1_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_img_0_cols_V_channel_full_n))) then
image_filter_Block_proc_U0_ap_continue <= ap_const_logic_1;
else
image_filter_Block_proc_U0_ap_continue <= ap_const_logic_0;
end if;
end process;
image_filter_Block_proc_U0_ap_start <= ap_start;
image_filter_Block_proc_U0_cols <= cols;
image_filter_Block_proc_U0_rows <= rows;
image_filter_Loop_1_proc_U0_ap_continue <= ap_const_logic_1;
image_filter_Loop_1_proc_U0_ap_start <= ap_start;
image_filter_Loop_1_proc_U0_cols <= cols;
image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_dout <= img_0_data_stream_0_V_dout;
image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_empty_n <= img_0_data_stream_0_V_empty_n;
image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_dout <= img_0_data_stream_1_V_dout;
image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_empty_n <= img_0_data_stream_1_V_empty_n;
image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_dout <= img_0_data_stream_2_V_dout;
image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_empty_n <= img_0_data_stream_2_V_empty_n;
image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_full_n <= img_1_data_stream_0_V_full_n;
image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_full_n <= img_1_data_stream_1_V_full_n;
image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_full_n <= img_1_data_stream_2_V_full_n;
image_filter_Loop_1_proc_U0_rows <= rows;
image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY <= OUTPUT_STREAM_TREADY;
image_filter_Mat2AXIvideo_U0_ap_continue <= ap_sig_hs_continue;
image_filter_Mat2AXIvideo_U0_ap_start <= (img_1_rows_V_empty_n and img_1_cols_V_empty_n);
image_filter_Mat2AXIvideo_U0_img_cols_V_read <= img_1_cols_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout <= img_1_data_stream_0_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n <= img_1_data_stream_0_V_empty_n;
image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout <= img_1_data_stream_1_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n <= img_1_data_stream_1_V_empty_n;
image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout <= img_1_data_stream_2_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n <= img_1_data_stream_2_V_empty_n;
image_filter_Mat2AXIvideo_U0_img_rows_V_read <= img_1_rows_V_dout;
img_0_cols_V_channel_U_ap_dummy_ce <= ap_const_logic_1;
img_0_cols_V_channel_din <= image_filter_Block_proc_U0_ap_return_1;
img_0_cols_V_channel_read <= image_filter_AXIvideo2Mat_U0_ap_ready;
img_0_cols_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel;
img_0_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1;
img_0_data_stream_0_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din;
img_0_data_stream_0_V_read <= image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_read;
img_0_data_stream_0_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write;
img_0_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1;
img_0_data_stream_1_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din;
img_0_data_stream_1_V_read <= image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_read;
img_0_data_stream_1_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write;
img_0_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1;
img_0_data_stream_2_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din;
img_0_data_stream_2_V_read <= image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_read;
img_0_data_stream_2_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write;
img_0_rows_V_channel_U_ap_dummy_ce <= ap_const_logic_1;
img_0_rows_V_channel_din <= image_filter_Block_proc_U0_ap_return_0;
img_0_rows_V_channel_read <= image_filter_AXIvideo2Mat_U0_ap_ready;
img_0_rows_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel;
img_1_cols_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_cols_V_din <= image_filter_Block_proc_U0_ap_return_3;
img_1_cols_V_read <= image_filter_Mat2AXIvideo_U0_ap_ready;
img_1_cols_V_write <= ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V;
img_1_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_data_stream_0_V_din <= image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_din;
img_1_data_stream_0_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read;
img_1_data_stream_0_V_write <= image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_write;
img_1_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_data_stream_1_V_din <= image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_din;
img_1_data_stream_1_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read;
img_1_data_stream_1_V_write <= image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_write;
img_1_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_data_stream_2_V_din <= image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_din;
img_1_data_stream_2_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read;
img_1_data_stream_2_V_write <= image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_write;
img_1_rows_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_rows_V_din <= image_filter_Block_proc_U0_ap_return_2;
img_1_rows_V_read <= image_filter_Mat2AXIvideo_U0_ap_ready;
img_1_rows_V_write <= ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter is
port (
INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
INPUT_STREAM_TVALID : IN STD_LOGIC;
INPUT_STREAM_TREADY : OUT STD_LOGIC;
OUTPUT_STREAM_TVALID : OUT STD_LOGIC;
OUTPUT_STREAM_TREADY : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC );
end;
architecture behav of image_filter is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"image_filter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=6.666670,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=5.681000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=6,HLS_SYN_DSP=4,HLS_SYN_FF=1026,HLS_SYN_LUT=1358}";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_true : BOOLEAN := true;
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_logic_1 : STD_LOGIC := '1';
signal ap_rst_n_inv : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_start : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_done : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_continue : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_idle : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_ready : STD_LOGIC;
signal image_filter_Block_proc_U0_rows : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Block_proc_U0_cols : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Block_proc_U0_ap_return_0 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_1 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_2 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_3 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel : STD_LOGIC;
signal img_0_rows_V_channel_full_n : STD_LOGIC;
signal ap_reg_ready_img_0_rows_V_channel_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_0_rows_V_channel_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V : STD_LOGIC;
signal img_1_rows_V_full_n : STD_LOGIC;
signal ap_reg_ready_img_1_rows_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_1_rows_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V : STD_LOGIC;
signal img_1_cols_V_full_n : STD_LOGIC;
signal ap_reg_ready_img_1_cols_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_1_cols_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel : STD_LOGIC;
signal img_0_cols_V_channel_full_n : STD_LOGIC;
signal ap_reg_ready_img_0_cols_V_channel_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_0_cols_V_channel_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_start : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_done : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_continue : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_idle : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_ready : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_start : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_done : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_continue : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_idle : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_ready : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_rows : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Loop_1_proc_U0_cols : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_empty_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_read : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_empty_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_read : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_empty_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_read : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_full_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_write : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_full_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_write : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_full_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_write : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_start : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_done : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_continue : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_idle : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_ready : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_hs_continue : STD_LOGIC;
signal img_0_rows_V_channel_U_ap_dummy_ce : STD_LOGIC;
signal img_0_rows_V_channel_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_rows_V_channel_write : STD_LOGIC;
signal img_0_rows_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_rows_V_channel_empty_n : STD_LOGIC;
signal img_0_rows_V_channel_read : STD_LOGIC;
signal img_0_cols_V_channel_U_ap_dummy_ce : STD_LOGIC;
signal img_0_cols_V_channel_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_cols_V_channel_write : STD_LOGIC;
signal img_0_cols_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_cols_V_channel_empty_n : STD_LOGIC;
signal img_0_cols_V_channel_read : STD_LOGIC;
signal img_1_rows_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_rows_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_rows_V_write : STD_LOGIC;
signal img_1_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_rows_V_empty_n : STD_LOGIC;
signal img_1_rows_V_read : STD_LOGIC;
signal img_1_cols_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_cols_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_cols_V_write : STD_LOGIC;
signal img_1_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_cols_V_empty_n : STD_LOGIC;
signal img_1_cols_V_read : STD_LOGIC;
signal img_0_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC;
signal img_0_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_0_V_full_n : STD_LOGIC;
signal img_0_data_stream_0_V_write : STD_LOGIC;
signal img_0_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_0_V_empty_n : STD_LOGIC;
signal img_0_data_stream_0_V_read : STD_LOGIC;
signal img_0_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC;
signal img_0_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_1_V_full_n : STD_LOGIC;
signal img_0_data_stream_1_V_write : STD_LOGIC;
signal img_0_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_1_V_empty_n : STD_LOGIC;
signal img_0_data_stream_1_V_read : STD_LOGIC;
signal img_0_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC;
signal img_0_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_2_V_full_n : STD_LOGIC;
signal img_0_data_stream_2_V_write : STD_LOGIC;
signal img_0_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_2_V_empty_n : STD_LOGIC;
signal img_0_data_stream_2_V_read : STD_LOGIC;
signal img_1_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_0_V_full_n : STD_LOGIC;
signal img_1_data_stream_0_V_write : STD_LOGIC;
signal img_1_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_0_V_empty_n : STD_LOGIC;
signal img_1_data_stream_0_V_read : STD_LOGIC;
signal img_1_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_1_V_full_n : STD_LOGIC;
signal img_1_data_stream_1_V_write : STD_LOGIC;
signal img_1_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_1_V_empty_n : STD_LOGIC;
signal img_1_data_stream_1_V_read : STD_LOGIC;
signal img_1_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_2_V_full_n : STD_LOGIC;
signal img_1_data_stream_2_V_write : STD_LOGIC;
signal img_1_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_2_V_empty_n : STD_LOGIC;
signal img_1_data_stream_2_V_read : STD_LOGIC;
signal ap_reg_procdone_image_filter_Block_proc_U0 : STD_LOGIC := '0';
signal ap_sig_hs_done : STD_LOGIC;
signal ap_reg_procdone_image_filter_AXIvideo2Mat_U0 : STD_LOGIC := '0';
signal ap_reg_procdone_image_filter_Loop_1_proc_U0 : STD_LOGIC := '0';
signal ap_reg_procdone_image_filter_Mat2AXIvideo_U0 : STD_LOGIC := '0';
signal ap_CS : STD_LOGIC;
signal ap_sig_top_allready : STD_LOGIC;
component image_filter_Block_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0) );
end component;
component image_filter_AXIvideo2Mat IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
INPUT_STREAM_TVALID : IN STD_LOGIC;
INPUT_STREAM_TREADY : OUT STD_LOGIC;
INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC );
end component;
component image_filter_Loop_1_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
img_0_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_0_data_stream_0_V_empty_n : IN STD_LOGIC;
img_0_data_stream_0_V_read : OUT STD_LOGIC;
img_0_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_0_data_stream_1_V_empty_n : IN STD_LOGIC;
img_0_data_stream_1_V_read : OUT STD_LOGIC;
img_0_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_0_data_stream_2_V_empty_n : IN STD_LOGIC;
img_0_data_stream_2_V_read : OUT STD_LOGIC;
img_1_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_1_data_stream_0_V_full_n : IN STD_LOGIC;
img_1_data_stream_0_V_write : OUT STD_LOGIC;
img_1_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_1_data_stream_1_V_full_n : IN STD_LOGIC;
img_1_data_stream_1_V_write : OUT STD_LOGIC;
img_1_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_1_data_stream_2_V_full_n : IN STD_LOGIC;
img_1_data_stream_2_V_write : OUT STD_LOGIC );
end component;
component image_filter_Mat2AXIvideo IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_empty_n : IN STD_LOGIC;
img_data_stream_0_V_read : OUT STD_LOGIC;
img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_empty_n : IN STD_LOGIC;
img_data_stream_1_V_read : OUT STD_LOGIC;
img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_empty_n : IN STD_LOGIC;
img_data_stream_2_V_read : OUT STD_LOGIC;
OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
OUTPUT_STREAM_TVALID : OUT STD_LOGIC;
OUTPUT_STREAM_TREADY : IN STD_LOGIC;
OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component FIFO_image_filter_img_0_rows_V_channel IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_cols_V_channel IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_rows_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_cols_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_data_stream_0_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_data_stream_1_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_data_stream_2_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_data_stream_0_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_data_stream_1_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_data_stream_2_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
begin
image_filter_Block_proc_U0 : component image_filter_Block_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Block_proc_U0_ap_start,
ap_done => image_filter_Block_proc_U0_ap_done,
ap_continue => image_filter_Block_proc_U0_ap_continue,
ap_idle => image_filter_Block_proc_U0_ap_idle,
ap_ready => image_filter_Block_proc_U0_ap_ready,
rows => image_filter_Block_proc_U0_rows,
cols => image_filter_Block_proc_U0_cols,
ap_return_0 => image_filter_Block_proc_U0_ap_return_0,
ap_return_1 => image_filter_Block_proc_U0_ap_return_1,
ap_return_2 => image_filter_Block_proc_U0_ap_return_2,
ap_return_3 => image_filter_Block_proc_U0_ap_return_3);
image_filter_AXIvideo2Mat_U0 : component image_filter_AXIvideo2Mat
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_AXIvideo2Mat_U0_ap_start,
ap_done => image_filter_AXIvideo2Mat_U0_ap_done,
ap_continue => image_filter_AXIvideo2Mat_U0_ap_continue,
ap_idle => image_filter_AXIvideo2Mat_U0_ap_idle,
ap_ready => image_filter_AXIvideo2Mat_U0_ap_ready,
INPUT_STREAM_TDATA => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA,
INPUT_STREAM_TVALID => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY,
INPUT_STREAM_TKEEP => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB,
INPUT_STREAM_TUSER => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER,
INPUT_STREAM_TLAST => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST,
INPUT_STREAM_TID => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID,
INPUT_STREAM_TDEST => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST,
img_rows_V_read => image_filter_AXIvideo2Mat_U0_img_rows_V_read,
img_cols_V_read => image_filter_AXIvideo2Mat_U0_img_cols_V_read,
img_data_stream_0_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din,
img_data_stream_0_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n,
img_data_stream_0_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write,
img_data_stream_1_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din,
img_data_stream_1_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n,
img_data_stream_1_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write,
img_data_stream_2_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din,
img_data_stream_2_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n,
img_data_stream_2_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write);
image_filter_Loop_1_proc_U0 : component image_filter_Loop_1_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Loop_1_proc_U0_ap_start,
ap_done => image_filter_Loop_1_proc_U0_ap_done,
ap_continue => image_filter_Loop_1_proc_U0_ap_continue,
ap_idle => image_filter_Loop_1_proc_U0_ap_idle,
ap_ready => image_filter_Loop_1_proc_U0_ap_ready,
rows => image_filter_Loop_1_proc_U0_rows,
cols => image_filter_Loop_1_proc_U0_cols,
img_0_data_stream_0_V_dout => image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_dout,
img_0_data_stream_0_V_empty_n => image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_empty_n,
img_0_data_stream_0_V_read => image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_read,
img_0_data_stream_1_V_dout => image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_dout,
img_0_data_stream_1_V_empty_n => image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_empty_n,
img_0_data_stream_1_V_read => image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_read,
img_0_data_stream_2_V_dout => image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_dout,
img_0_data_stream_2_V_empty_n => image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_empty_n,
img_0_data_stream_2_V_read => image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_read,
img_1_data_stream_0_V_din => image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_din,
img_1_data_stream_0_V_full_n => image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_full_n,
img_1_data_stream_0_V_write => image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_write,
img_1_data_stream_1_V_din => image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_din,
img_1_data_stream_1_V_full_n => image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_full_n,
img_1_data_stream_1_V_write => image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_write,
img_1_data_stream_2_V_din => image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_din,
img_1_data_stream_2_V_full_n => image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_full_n,
img_1_data_stream_2_V_write => image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_write);
image_filter_Mat2AXIvideo_U0 : component image_filter_Mat2AXIvideo
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Mat2AXIvideo_U0_ap_start,
ap_done => image_filter_Mat2AXIvideo_U0_ap_done,
ap_continue => image_filter_Mat2AXIvideo_U0_ap_continue,
ap_idle => image_filter_Mat2AXIvideo_U0_ap_idle,
ap_ready => image_filter_Mat2AXIvideo_U0_ap_ready,
img_rows_V_read => image_filter_Mat2AXIvideo_U0_img_rows_V_read,
img_cols_V_read => image_filter_Mat2AXIvideo_U0_img_cols_V_read,
img_data_stream_0_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout,
img_data_stream_0_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n,
img_data_stream_0_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read,
img_data_stream_1_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout,
img_data_stream_1_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n,
img_data_stream_1_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read,
img_data_stream_2_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout,
img_data_stream_2_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n,
img_data_stream_2_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read,
OUTPUT_STREAM_TDATA => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TVALID => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY,
OUTPUT_STREAM_TKEEP => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID,
OUTPUT_STREAM_TDEST => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST);
img_0_rows_V_channel_U : component FIFO_image_filter_img_0_rows_V_channel
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_rows_V_channel_U_ap_dummy_ce,
if_write_ce => img_0_rows_V_channel_U_ap_dummy_ce,
if_din => img_0_rows_V_channel_din,
if_full_n => img_0_rows_V_channel_full_n,
if_write => img_0_rows_V_channel_write,
if_dout => img_0_rows_V_channel_dout,
if_empty_n => img_0_rows_V_channel_empty_n,
if_read => img_0_rows_V_channel_read);
img_0_cols_V_channel_U : component FIFO_image_filter_img_0_cols_V_channel
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_cols_V_channel_U_ap_dummy_ce,
if_write_ce => img_0_cols_V_channel_U_ap_dummy_ce,
if_din => img_0_cols_V_channel_din,
if_full_n => img_0_cols_V_channel_full_n,
if_write => img_0_cols_V_channel_write,
if_dout => img_0_cols_V_channel_dout,
if_empty_n => img_0_cols_V_channel_empty_n,
if_read => img_0_cols_V_channel_read);
img_1_rows_V_U : component FIFO_image_filter_img_1_rows_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_rows_V_U_ap_dummy_ce,
if_write_ce => img_1_rows_V_U_ap_dummy_ce,
if_din => img_1_rows_V_din,
if_full_n => img_1_rows_V_full_n,
if_write => img_1_rows_V_write,
if_dout => img_1_rows_V_dout,
if_empty_n => img_1_rows_V_empty_n,
if_read => img_1_rows_V_read);
img_1_cols_V_U : component FIFO_image_filter_img_1_cols_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_cols_V_U_ap_dummy_ce,
if_write_ce => img_1_cols_V_U_ap_dummy_ce,
if_din => img_1_cols_V_din,
if_full_n => img_1_cols_V_full_n,
if_write => img_1_cols_V_write,
if_dout => img_1_cols_V_dout,
if_empty_n => img_1_cols_V_empty_n,
if_read => img_1_cols_V_read);
img_0_data_stream_0_V_U : component FIFO_image_filter_img_0_data_stream_0_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_data_stream_0_V_U_ap_dummy_ce,
if_write_ce => img_0_data_stream_0_V_U_ap_dummy_ce,
if_din => img_0_data_stream_0_V_din,
if_full_n => img_0_data_stream_0_V_full_n,
if_write => img_0_data_stream_0_V_write,
if_dout => img_0_data_stream_0_V_dout,
if_empty_n => img_0_data_stream_0_V_empty_n,
if_read => img_0_data_stream_0_V_read);
img_0_data_stream_1_V_U : component FIFO_image_filter_img_0_data_stream_1_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_data_stream_1_V_U_ap_dummy_ce,
if_write_ce => img_0_data_stream_1_V_U_ap_dummy_ce,
if_din => img_0_data_stream_1_V_din,
if_full_n => img_0_data_stream_1_V_full_n,
if_write => img_0_data_stream_1_V_write,
if_dout => img_0_data_stream_1_V_dout,
if_empty_n => img_0_data_stream_1_V_empty_n,
if_read => img_0_data_stream_1_V_read);
img_0_data_stream_2_V_U : component FIFO_image_filter_img_0_data_stream_2_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_data_stream_2_V_U_ap_dummy_ce,
if_write_ce => img_0_data_stream_2_V_U_ap_dummy_ce,
if_din => img_0_data_stream_2_V_din,
if_full_n => img_0_data_stream_2_V_full_n,
if_write => img_0_data_stream_2_V_write,
if_dout => img_0_data_stream_2_V_dout,
if_empty_n => img_0_data_stream_2_V_empty_n,
if_read => img_0_data_stream_2_V_read);
img_1_data_stream_0_V_U : component FIFO_image_filter_img_1_data_stream_0_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_data_stream_0_V_U_ap_dummy_ce,
if_write_ce => img_1_data_stream_0_V_U_ap_dummy_ce,
if_din => img_1_data_stream_0_V_din,
if_full_n => img_1_data_stream_0_V_full_n,
if_write => img_1_data_stream_0_V_write,
if_dout => img_1_data_stream_0_V_dout,
if_empty_n => img_1_data_stream_0_V_empty_n,
if_read => img_1_data_stream_0_V_read);
img_1_data_stream_1_V_U : component FIFO_image_filter_img_1_data_stream_1_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_data_stream_1_V_U_ap_dummy_ce,
if_write_ce => img_1_data_stream_1_V_U_ap_dummy_ce,
if_din => img_1_data_stream_1_V_din,
if_full_n => img_1_data_stream_1_V_full_n,
if_write => img_1_data_stream_1_V_write,
if_dout => img_1_data_stream_1_V_dout,
if_empty_n => img_1_data_stream_1_V_empty_n,
if_read => img_1_data_stream_1_V_read);
img_1_data_stream_2_V_U : component FIFO_image_filter_img_1_data_stream_2_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_data_stream_2_V_U_ap_dummy_ce,
if_write_ce => img_1_data_stream_2_V_U_ap_dummy_ce,
if_din => img_1_data_stream_2_V_din,
if_full_n => img_1_data_stream_2_V_full_n,
if_write => img_1_data_stream_2_V_write,
if_dout => img_1_data_stream_2_V_dout,
if_empty_n => img_1_data_stream_2_V_empty_n,
if_read => img_1_data_stream_2_V_read);
-- ap_reg_procdone_image_filter_AXIvideo2Mat_U0 assign process. --
ap_reg_procdone_image_filter_AXIvideo2Mat_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_AXIvideo2Mat_U0_ap_done)) then
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Block_proc_U0 assign process. --
ap_reg_procdone_image_filter_Block_proc_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0;
elsif ((image_filter_Block_proc_U0_ap_done = ap_const_logic_1)) then
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Loop_1_proc_U0 assign process. --
ap_reg_procdone_image_filter_Loop_1_proc_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Loop_1_proc_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Loop_1_proc_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_Loop_1_proc_U0_ap_done)) then
ap_reg_procdone_image_filter_Loop_1_proc_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Mat2AXIvideo_U0 assign process. --
ap_reg_procdone_image_filter_Mat2AXIvideo_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_done)) then
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_0_cols_V_channel_full_n assign process. --
ap_reg_ready_img_0_cols_V_channel_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = img_0_cols_V_channel_full_n))) then
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_0_rows_V_channel_full_n assign process. --
ap_reg_ready_img_0_rows_V_channel_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (img_0_rows_V_channel_full_n = ap_const_logic_1))) then
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_1_cols_V_full_n assign process. --
ap_reg_ready_img_1_cols_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = img_1_cols_V_full_n))) then
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_1_rows_V_full_n assign process. --
ap_reg_ready_img_1_rows_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = img_1_rows_V_full_n))) then
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_CS assign process. --
ap_CS_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
ap_CS <= ap_const_logic_0;
end if;
end process;
INPUT_STREAM_TREADY <= image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY;
OUTPUT_STREAM_TDATA <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA;
OUTPUT_STREAM_TDEST <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST;
OUTPUT_STREAM_TID <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID;
OUTPUT_STREAM_TKEEP <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP;
OUTPUT_STREAM_TLAST <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST;
OUTPUT_STREAM_TSTRB <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB;
OUTPUT_STREAM_TUSER <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER;
OUTPUT_STREAM_TVALID <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID;
-- ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_0_cols_V_channel_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_img_0_cols_V_channel_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_0_rows_V_channel_full_n)
begin
if ((ap_reg_ready_img_0_rows_V_channel_full_n = ap_const_logic_1)) then
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_1_cols_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_img_1_cols_V_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_1_rows_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_img_1_rows_V_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
ap_done <= ap_sig_hs_done;
-- ap_idle assign process. --
ap_idle_assign_proc : process(image_filter_Block_proc_U0_ap_idle, image_filter_AXIvideo2Mat_U0_ap_idle, image_filter_Loop_1_proc_U0_ap_idle, image_filter_Mat2AXIvideo_U0_ap_idle, img_0_rows_V_channel_empty_n, img_0_cols_V_channel_empty_n, img_1_rows_V_empty_n, img_1_cols_V_empty_n)
begin
if (((image_filter_Block_proc_U0_ap_idle = ap_const_logic_1) and (ap_const_logic_1 = image_filter_AXIvideo2Mat_U0_ap_idle) and (ap_const_logic_1 = image_filter_Loop_1_proc_U0_ap_idle) and (ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_idle) and (ap_const_logic_0 = img_0_rows_V_channel_empty_n) and (ap_const_logic_0 = img_0_cols_V_channel_empty_n) and (ap_const_logic_0 = img_1_rows_V_empty_n) and (ap_const_logic_0 = img_1_cols_V_empty_n))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready <= ap_sig_top_allready;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sig_hs_continue <= ap_const_logic_1;
-- ap_sig_hs_done assign process. --
ap_sig_hs_done_assign_proc : process(image_filter_Mat2AXIvideo_U0_ap_done)
begin
if ((ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_done)) then
ap_sig_hs_done <= ap_const_logic_1;
else
ap_sig_hs_done <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ready_img_0_cols_V_channel_full_n assign process. --
ap_sig_ready_img_0_cols_V_channel_full_n_assign_proc : process(img_0_cols_V_channel_full_n, ap_reg_ready_img_0_cols_V_channel_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_img_0_cols_V_channel_full_n)) then
ap_sig_ready_img_0_cols_V_channel_full_n <= img_0_cols_V_channel_full_n;
else
ap_sig_ready_img_0_cols_V_channel_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_img_0_rows_V_channel_full_n assign process. --
ap_sig_ready_img_0_rows_V_channel_full_n_assign_proc : process(img_0_rows_V_channel_full_n, ap_reg_ready_img_0_rows_V_channel_full_n)
begin
if ((ap_reg_ready_img_0_rows_V_channel_full_n = ap_const_logic_0)) then
ap_sig_ready_img_0_rows_V_channel_full_n <= img_0_rows_V_channel_full_n;
else
ap_sig_ready_img_0_rows_V_channel_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_img_1_cols_V_full_n assign process. --
ap_sig_ready_img_1_cols_V_full_n_assign_proc : process(img_1_cols_V_full_n, ap_reg_ready_img_1_cols_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_img_1_cols_V_full_n)) then
ap_sig_ready_img_1_cols_V_full_n <= img_1_cols_V_full_n;
else
ap_sig_ready_img_1_cols_V_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_img_1_rows_V_full_n assign process. --
ap_sig_ready_img_1_rows_V_full_n_assign_proc : process(img_1_rows_V_full_n, ap_reg_ready_img_1_rows_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_img_1_rows_V_full_n)) then
ap_sig_ready_img_1_rows_V_full_n <= img_1_rows_V_full_n;
else
ap_sig_ready_img_1_rows_V_full_n <= ap_const_logic_1;
end if;
end process;
ap_sig_top_allready <= image_filter_AXIvideo2Mat_U0_ap_ready;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA <= INPUT_STREAM_TDATA;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST <= INPUT_STREAM_TDEST;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID <= INPUT_STREAM_TID;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP <= INPUT_STREAM_TKEEP;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST <= INPUT_STREAM_TLAST;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB <= INPUT_STREAM_TSTRB;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER <= INPUT_STREAM_TUSER;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID <= INPUT_STREAM_TVALID;
image_filter_AXIvideo2Mat_U0_ap_continue <= ap_const_logic_1;
image_filter_AXIvideo2Mat_U0_ap_start <= (ap_start and img_0_rows_V_channel_empty_n and img_0_cols_V_channel_empty_n);
image_filter_AXIvideo2Mat_U0_img_cols_V_read <= img_0_cols_V_channel_dout;
image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n <= img_0_data_stream_0_V_full_n;
image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n <= img_0_data_stream_1_V_full_n;
image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n <= img_0_data_stream_2_V_full_n;
image_filter_AXIvideo2Mat_U0_img_rows_V_read <= img_0_rows_V_channel_dout;
-- image_filter_Block_proc_U0_ap_continue assign process. --
image_filter_Block_proc_U0_ap_continue_assign_proc : process(ap_sig_ready_img_0_rows_V_channel_full_n, ap_sig_ready_img_1_rows_V_full_n, ap_sig_ready_img_1_cols_V_full_n, ap_sig_ready_img_0_cols_V_channel_full_n)
begin
if (((ap_sig_ready_img_0_rows_V_channel_full_n = ap_const_logic_1) and (ap_const_logic_1 = ap_sig_ready_img_1_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_img_1_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_img_0_cols_V_channel_full_n))) then
image_filter_Block_proc_U0_ap_continue <= ap_const_logic_1;
else
image_filter_Block_proc_U0_ap_continue <= ap_const_logic_0;
end if;
end process;
image_filter_Block_proc_U0_ap_start <= ap_start;
image_filter_Block_proc_U0_cols <= cols;
image_filter_Block_proc_U0_rows <= rows;
image_filter_Loop_1_proc_U0_ap_continue <= ap_const_logic_1;
image_filter_Loop_1_proc_U0_ap_start <= ap_start;
image_filter_Loop_1_proc_U0_cols <= cols;
image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_dout <= img_0_data_stream_0_V_dout;
image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_empty_n <= img_0_data_stream_0_V_empty_n;
image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_dout <= img_0_data_stream_1_V_dout;
image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_empty_n <= img_0_data_stream_1_V_empty_n;
image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_dout <= img_0_data_stream_2_V_dout;
image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_empty_n <= img_0_data_stream_2_V_empty_n;
image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_full_n <= img_1_data_stream_0_V_full_n;
image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_full_n <= img_1_data_stream_1_V_full_n;
image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_full_n <= img_1_data_stream_2_V_full_n;
image_filter_Loop_1_proc_U0_rows <= rows;
image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY <= OUTPUT_STREAM_TREADY;
image_filter_Mat2AXIvideo_U0_ap_continue <= ap_sig_hs_continue;
image_filter_Mat2AXIvideo_U0_ap_start <= (img_1_rows_V_empty_n and img_1_cols_V_empty_n);
image_filter_Mat2AXIvideo_U0_img_cols_V_read <= img_1_cols_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout <= img_1_data_stream_0_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n <= img_1_data_stream_0_V_empty_n;
image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout <= img_1_data_stream_1_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n <= img_1_data_stream_1_V_empty_n;
image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout <= img_1_data_stream_2_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n <= img_1_data_stream_2_V_empty_n;
image_filter_Mat2AXIvideo_U0_img_rows_V_read <= img_1_rows_V_dout;
img_0_cols_V_channel_U_ap_dummy_ce <= ap_const_logic_1;
img_0_cols_V_channel_din <= image_filter_Block_proc_U0_ap_return_1;
img_0_cols_V_channel_read <= image_filter_AXIvideo2Mat_U0_ap_ready;
img_0_cols_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel;
img_0_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1;
img_0_data_stream_0_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din;
img_0_data_stream_0_V_read <= image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_read;
img_0_data_stream_0_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write;
img_0_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1;
img_0_data_stream_1_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din;
img_0_data_stream_1_V_read <= image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_read;
img_0_data_stream_1_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write;
img_0_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1;
img_0_data_stream_2_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din;
img_0_data_stream_2_V_read <= image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_read;
img_0_data_stream_2_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write;
img_0_rows_V_channel_U_ap_dummy_ce <= ap_const_logic_1;
img_0_rows_V_channel_din <= image_filter_Block_proc_U0_ap_return_0;
img_0_rows_V_channel_read <= image_filter_AXIvideo2Mat_U0_ap_ready;
img_0_rows_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel;
img_1_cols_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_cols_V_din <= image_filter_Block_proc_U0_ap_return_3;
img_1_cols_V_read <= image_filter_Mat2AXIvideo_U0_ap_ready;
img_1_cols_V_write <= ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V;
img_1_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_data_stream_0_V_din <= image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_din;
img_1_data_stream_0_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read;
img_1_data_stream_0_V_write <= image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_write;
img_1_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_data_stream_1_V_din <= image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_din;
img_1_data_stream_1_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read;
img_1_data_stream_1_V_write <= image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_write;
img_1_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_data_stream_2_V_din <= image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_din;
img_1_data_stream_2_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read;
img_1_data_stream_2_V_write <= image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_write;
img_1_rows_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_rows_V_din <= image_filter_Block_proc_U0_ap_return_2;
img_1_rows_V_read <= image_filter_Mat2AXIvideo_U0_ap_ready;
img_1_rows_V_write <= ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V;
end behav;
|
-- ======================================================================
-- CBC-DES encryption/decryption
-- algorithm according to FIPS 46-3 specification
-- Copyright (C) 2007 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.des_pkg.all;
entity cbctdes is
port (
reset_i : in std_logic; -- low active async reset
clk_i : in std_logic; -- clock
start_i : in std_logic; -- start cbc
mode_i : in std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
key1_i : in std_logic_vector(0 TO 63); -- key input
key2_i : in std_logic_vector(0 TO 63); -- key input
key3_i : in std_logic_vector(0 TO 63); -- key input
iv_i : in std_logic_vector(0 to 63); -- iv input
data_i : in std_logic_vector(0 TO 63); -- data input
valid_i : in std_logic; -- input key/data valid flag
ready_o : out std_logic; -- ready to encrypt/decrypt
data_o : out std_logic_vector(0 TO 63); -- data output
valid_o : out std_logic -- output data valid flag
);
end entity cbctdes;
architecture rtl of cbctdes is
component tdes is
port (
reset_i : in std_logic; -- async reset
clk_i : in std_logic; -- clock
mode_i : in std_logic; -- tdes-modus: 0 = encrypt, 1 = decrypt
key1_i : in std_logic_vector(0 TO 63); -- key input
key2_i : in std_logic_vector(0 TO 63); -- key input
key3_i : in std_logic_vector(0 TO 63); -- key input
data_i : in std_logic_vector(0 TO 63); -- data input
valid_i : in std_logic; -- input key/data valid flag
data_o : out std_logic_vector(0 TO 63); -- data output
valid_o : out std_logic; -- output data valid flag
ready_o : out std_logic
);
end component tdes;
signal s_mode : std_logic;
signal s_des_mode : std_logic;
signal s_start : std_logic;
signal s_key1 : std_logic_vector(0 to 63);
signal s_key2 : std_logic_vector(0 to 63);
signal s_key3 : std_logic_vector(0 to 63);
signal s_tdes_key1 : std_logic_vector(0 to 63);
signal s_tdes_key2 : std_logic_vector(0 to 63);
signal s_tdes_key3 : std_logic_vector(0 to 63);
signal s_iv : std_logic_vector(0 to 63);
signal s_datain : std_logic_vector(0 to 63);
signal s_datain_d : std_logic_vector(0 to 63);
signal s_des_datain : std_logic_vector(0 to 63);
signal s_validin : std_logic;
signal s_des_dataout : std_logic_vector(0 to 63);
signal s_dataout : std_logic_vector(0 to 63);
signal s_validout : std_logic;
signal s_ready : std_logic;
signal s_readyout : std_logic;
begin
s_des_datain <= iv_i xor data_i when mode_i = '0' and start_i = '1' else
s_dataout xor data_i when s_mode = '0' and start_i = '0' else
data_i;
data_o <= s_iv xor s_des_dataout when s_mode = '1' and s_start = '1' else
s_datain_d xor s_des_dataout when s_mode = '1' and s_start = '0' else
s_des_dataout;
s_tdes_key1 <= key1_i when start_i = '1' else s_key1;
s_tdes_key2 <= key2_i when start_i = '1' else s_key2;
s_tdes_key3 <= key3_i when start_i = '1' else s_key3;
s_des_mode <= mode_i when start_i = '1' else s_mode;
ready_o <= s_ready;
s_validin <= valid_i and s_ready;
valid_o <= s_validout;
inputregister : process(clk_i, reset_i) is
begin
if(reset_i = '0') then
s_mode <= '0';
s_start <= '0';
s_key1 <= (others => '0');
s_key2 <= (others => '0');
s_key3 <= (others => '0');
s_iv <= (others => '0');
s_datain <= (others => '0');
s_datain_d <= (others => '0');
elsif(rising_edge(clk_i)) then
if(valid_i = '1' and s_ready = '1') then
s_start <= start_i;
s_datain <= data_i;
s_datain_d <= s_datain;
end if;
if(valid_i = '1' and s_ready = '1' and start_i = '1') then
s_mode <= mode_i;
s_key1 <= key1_i;
s_key2 <= key2_i;
s_key3 <= key3_i;
s_iv <= iv_i;
end if;
end if;
end process inputregister;
outputregister : process(clk_i, reset_i) is
begin
if(reset_i = '0') then
s_ready <= '1';
s_dataout <= (others => '0');
elsif(rising_edge(clk_i)) then
if(valid_i = '1' and s_ready = '1' and s_readyout = '1') then
s_ready <= '0';
end if;
if(s_validout = '1') then
s_ready <= '1';
s_dataout <= s_des_dataout;
end if;
end if;
end process outputregister;
i_tdes : tdes
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => s_des_mode,
key1_i => s_tdes_key1,
key2_i => s_tdes_key2,
key3_i => s_tdes_key3,
data_i => s_des_datain,
valid_i => s_validin,
data_o => s_des_dataout,
valid_o => s_validout,
ready_o => s_readyout
);
end architecture rtl;
|
-------------------------------------------------------------------------------
-- Title : Entity for simulation model of MAX6682 temperature sensor
-- Project :
-------------------------------------------------------------------------------
-- File : max6682-e.vhd
-- Author : Johann Glaser
-- Company :
-- Created : 2011-04-14
-- Last update: 2011-04-14
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-04-14 1.0 glasejoh Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity MAX6682_Model is
port (
ChipSelect_n_i : in std_logic;
SCLK_i : in std_logic;
SO_o : out std_logic;
Value_i : in std_logic_vector(10 downto 0));
end MAX6682_Model;
architecture behavior of MAX6682_Model is
begin -- behavior
SPIProc: process (ChipSelect_n_i,SCLK_i,Value_i)
variable Value : std_logic_vector(10 downto 0);
begin -- process SPIProc
if ChipSelect_n_i = '1' then
Value := Value_i;
SO_o <= 'Z';
else
--falling_edge(ChipSelect_n_i) then
--wait for 30 ns; -- t_DV <= 35 ns : CS Fall to Output Data Valid
if falling_edge(SCLK_i) then
--wait for 30 ns; -- t_DO <= 35 ns : SCK Fall to Output Data Valid
Value := Value(Value'high-1 downto 0) & 'Z';
end if;
SO_o <= Value(Value'high);
end if;
end process SPIProc;
end behavior;
|
-------------------------------------------------------------------------------
-- Title : Entity for simulation model of MAX6682 temperature sensor
-- Project :
-------------------------------------------------------------------------------
-- File : max6682-e.vhd
-- Author : Johann Glaser
-- Company :
-- Created : 2011-04-14
-- Last update: 2011-04-14
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-04-14 1.0 glasejoh Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity MAX6682_Model is
port (
ChipSelect_n_i : in std_logic;
SCLK_i : in std_logic;
SO_o : out std_logic;
Value_i : in std_logic_vector(10 downto 0));
end MAX6682_Model;
architecture behavior of MAX6682_Model is
begin -- behavior
SPIProc: process (ChipSelect_n_i,SCLK_i,Value_i)
variable Value : std_logic_vector(10 downto 0);
begin -- process SPIProc
if ChipSelect_n_i = '1' then
Value := Value_i;
SO_o <= 'Z';
else
--falling_edge(ChipSelect_n_i) then
--wait for 30 ns; -- t_DV <= 35 ns : CS Fall to Output Data Valid
if falling_edge(SCLK_i) then
--wait for 30 ns; -- t_DO <= 35 ns : SCK Fall to Output Data Valid
Value := Value(Value'high-1 downto 0) & 'Z';
end if;
SO_o <= Value(Value'high);
end if;
end process SPIProc;
end behavior;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.TB_Package.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
-- Declaring network component
component network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
component flit_tracker is
generic (
DATA_WIDTH: integer := 32;
tracker_file: string :="track.txt"
);
port (
clk: in std_logic;
RX: in std_logic_vector (DATA_WIDTH-1 downto 0);
valid_in : in std_logic
);
end component;
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal credit_counter_out_0: std_logic_vector (1 downto 0);
signal credit_out_L_0, credit_in_L_0, valid_in_L_0, valid_out_L_0: std_logic;
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal credit_counter_out_1: std_logic_vector (1 downto 0);
signal credit_out_L_1, credit_in_L_1, valid_in_L_1, valid_out_L_1: std_logic;
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal credit_counter_out_2: std_logic_vector (1 downto 0);
signal credit_out_L_2, credit_in_L_2, valid_in_L_2, valid_out_L_2: std_logic;
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal credit_counter_out_3: std_logic_vector (1 downto 0);
signal credit_out_L_3, credit_in_L_3, valid_in_L_3, valid_out_L_3: std_logic;
--------------
signal Rxy_reconf: std_logic_vector (7 downto 0) := "01111101";
signal Reconfig: std_logic := '0';
constant clk_period : time := 1 ns;
signal reset, not_reset, clk: std_logic :='0';
begin
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset <= '1' after 1 ns;
-- instantiating the network
-- instantiating the flit trackers
F_T_0_T: flit_tracker generic map (
DATA_WIDTH => 32,
tracker_file =>"traces/track0_T.txt"
)
port map (
clk => clk, RX => TX_L_0,
valid_in => valid_out_L_0
);
F_T_1_T: flit_tracker generic map (
DATA_WIDTH => 32,
tracker_file =>"traces/track1_T.txt"
)
port map (
clk => clk, RX => TX_L_1,
valid_in => valid_out_L_1
);
F_T_2_T: flit_tracker generic map (
DATA_WIDTH => 32,
tracker_file =>"traces/track2_T.txt"
)
port map (
clk => clk, RX => TX_L_2,
valid_in => valid_out_L_2
);
F_T_3_T: flit_tracker generic map (
DATA_WIDTH => 32,
tracker_file =>"traces/track3_T.txt"
)
port map (
clk => clk, RX => TX_L_3,
valid_in => valid_out_L_3
);
NoC: network_2x2 generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk, Rxy_reconf, Reconfig,
RX_L_0, credit_out_L_0, valid_out_L_0, credit_in_L_0, valid_in_L_0, TX_L_0,
RX_L_1, credit_out_L_1, valid_out_L_1, credit_in_L_1, valid_in_L_1, TX_L_1,
RX_L_2, credit_out_L_2, valid_out_L_2, credit_in_L_2, valid_in_L_2, TX_L_2,
RX_L_3, credit_out_L_3, valid_out_L_3, credit_in_L_3, valid_in_L_3, TX_L_3
);
not_reset <= not reset;
-- connecting the packet generators
credit_counter_control(clk, credit_out_L_0, valid_in_L_0, credit_counter_out_0);
gen_random_packet(2, 100, 0, 33, 8, 8, 2000 ns, clk, credit_counter_out_0, valid_in_L_0, RX_L_0);
credit_counter_control(clk, credit_out_L_1, valid_in_L_1, credit_counter_out_1);
gen_random_packet(2, 100, 1, 15, 8, 8, 2000 ns, clk, credit_counter_out_1, valid_in_L_1, RX_L_1);
credit_counter_control(clk, credit_out_L_2, valid_in_L_2, credit_counter_out_2);
gen_random_packet(2, 100, 2, 6, 8, 8, 2000 ns, clk, credit_counter_out_2, valid_in_L_2, RX_L_2);
credit_counter_control(clk, credit_out_L_3, valid_in_L_3, credit_counter_out_3);
gen_random_packet(2, 100, 3, 30, 8, 8, 2000 ns, clk, credit_counter_out_3, valid_in_L_3, RX_L_3);
-- connecting the packet receivers
get_packet(32, 5, 0, clk, credit_in_L_0, valid_out_L_0, TX_L_0);
get_packet(32, 5, 1, clk, credit_in_L_1, valid_out_L_1, TX_L_1);
get_packet(32, 5, 2, clk, credit_in_L_2, valid_out_L_2, TX_L_2);
get_packet(32, 5, 3, clk, credit_in_L_3, valid_out_L_3, TX_L_3);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.TB_Package.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
-- Declaring network component
component network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
component flit_tracker is
generic (
DATA_WIDTH: integer := 32;
tracker_file: string :="track.txt"
);
port (
clk: in std_logic;
RX: in std_logic_vector (DATA_WIDTH-1 downto 0);
valid_in : in std_logic
);
end component;
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal credit_counter_out_0: std_logic_vector (1 downto 0);
signal credit_out_L_0, credit_in_L_0, valid_in_L_0, valid_out_L_0: std_logic;
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal credit_counter_out_1: std_logic_vector (1 downto 0);
signal credit_out_L_1, credit_in_L_1, valid_in_L_1, valid_out_L_1: std_logic;
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal credit_counter_out_2: std_logic_vector (1 downto 0);
signal credit_out_L_2, credit_in_L_2, valid_in_L_2, valid_out_L_2: std_logic;
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal credit_counter_out_3: std_logic_vector (1 downto 0);
signal credit_out_L_3, credit_in_L_3, valid_in_L_3, valid_out_L_3: std_logic;
--------------
signal Rxy_reconf: std_logic_vector (7 downto 0) := "01111101";
signal Reconfig: std_logic := '0';
constant clk_period : time := 1 ns;
signal reset, not_reset, clk: std_logic :='0';
begin
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset <= '1' after 1 ns;
-- instantiating the network
-- instantiating the flit trackers
F_T_0_T: flit_tracker generic map (
DATA_WIDTH => 32,
tracker_file =>"traces/track0_T.txt"
)
port map (
clk => clk, RX => TX_L_0,
valid_in => valid_out_L_0
);
F_T_1_T: flit_tracker generic map (
DATA_WIDTH => 32,
tracker_file =>"traces/track1_T.txt"
)
port map (
clk => clk, RX => TX_L_1,
valid_in => valid_out_L_1
);
F_T_2_T: flit_tracker generic map (
DATA_WIDTH => 32,
tracker_file =>"traces/track2_T.txt"
)
port map (
clk => clk, RX => TX_L_2,
valid_in => valid_out_L_2
);
F_T_3_T: flit_tracker generic map (
DATA_WIDTH => 32,
tracker_file =>"traces/track3_T.txt"
)
port map (
clk => clk, RX => TX_L_3,
valid_in => valid_out_L_3
);
NoC: network_2x2 generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk, Rxy_reconf, Reconfig,
RX_L_0, credit_out_L_0, valid_out_L_0, credit_in_L_0, valid_in_L_0, TX_L_0,
RX_L_1, credit_out_L_1, valid_out_L_1, credit_in_L_1, valid_in_L_1, TX_L_1,
RX_L_2, credit_out_L_2, valid_out_L_2, credit_in_L_2, valid_in_L_2, TX_L_2,
RX_L_3, credit_out_L_3, valid_out_L_3, credit_in_L_3, valid_in_L_3, TX_L_3
);
not_reset <= not reset;
-- connecting the packet generators
credit_counter_control(clk, credit_out_L_0, valid_in_L_0, credit_counter_out_0);
gen_random_packet(2, 100, 0, 33, 8, 8, 2000 ns, clk, credit_counter_out_0, valid_in_L_0, RX_L_0);
credit_counter_control(clk, credit_out_L_1, valid_in_L_1, credit_counter_out_1);
gen_random_packet(2, 100, 1, 15, 8, 8, 2000 ns, clk, credit_counter_out_1, valid_in_L_1, RX_L_1);
credit_counter_control(clk, credit_out_L_2, valid_in_L_2, credit_counter_out_2);
gen_random_packet(2, 100, 2, 6, 8, 8, 2000 ns, clk, credit_counter_out_2, valid_in_L_2, RX_L_2);
credit_counter_control(clk, credit_out_L_3, valid_in_L_3, credit_counter_out_3);
gen_random_packet(2, 100, 3, 30, 8, 8, 2000 ns, clk, credit_counter_out_3, valid_in_L_3, RX_L_3);
-- connecting the packet receivers
get_packet(32, 5, 0, clk, credit_in_L_0, valid_out_L_0, TX_L_0);
get_packet(32, 5, 1, clk, credit_in_L_1, valid_out_L_1, TX_L_1);
get_packet(32, 5, 2, clk, credit_in_L_2, valid_out_L_2, TX_L_2);
get_packet(32, 5, 3, clk, credit_in_L_3, valid_out_L_3, TX_L_3);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.TB_Package.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
-- Declaring network component
component network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV: integer := 11);
port (reset: in std_logic;
clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH-1 downto 0)
);
end component;
component flit_tracker is
generic (
DATA_WIDTH: integer := 32;
tracker_file: string :="track.txt"
);
port (
clk: in std_logic;
RX: in std_logic_vector (DATA_WIDTH-1 downto 0);
valid_in : in std_logic
);
end component;
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal credit_counter_out_0: std_logic_vector (1 downto 0);
signal credit_out_L_0, credit_in_L_0, valid_in_L_0, valid_out_L_0: std_logic;
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal credit_counter_out_1: std_logic_vector (1 downto 0);
signal credit_out_L_1, credit_in_L_1, valid_in_L_1, valid_out_L_1: std_logic;
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal credit_counter_out_2: std_logic_vector (1 downto 0);
signal credit_out_L_2, credit_in_L_2, valid_in_L_2, valid_out_L_2: std_logic;
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal credit_counter_out_3: std_logic_vector (1 downto 0);
signal credit_out_L_3, credit_in_L_3, valid_in_L_3, valid_out_L_3: std_logic;
--------------
signal Rxy_reconf: std_logic_vector (7 downto 0) := "01111101";
signal Reconfig: std_logic := '0';
constant clk_period : time := 1 ns;
signal reset, not_reset, clk: std_logic :='0';
begin
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset <= '1' after 1 ns;
-- instantiating the network
-- instantiating the flit trackers
F_T_0_T: flit_tracker generic map (
DATA_WIDTH => 32,
tracker_file =>"traces/track0_T.txt"
)
port map (
clk => clk, RX => TX_L_0,
valid_in => valid_out_L_0
);
F_T_1_T: flit_tracker generic map (
DATA_WIDTH => 32,
tracker_file =>"traces/track1_T.txt"
)
port map (
clk => clk, RX => TX_L_1,
valid_in => valid_out_L_1
);
F_T_2_T: flit_tracker generic map (
DATA_WIDTH => 32,
tracker_file =>"traces/track2_T.txt"
)
port map (
clk => clk, RX => TX_L_2,
valid_in => valid_out_L_2
);
F_T_3_T: flit_tracker generic map (
DATA_WIDTH => 32,
tracker_file =>"traces/track3_T.txt"
)
port map (
clk => clk, RX => TX_L_3,
valid_in => valid_out_L_3
);
NoC: network_2x2 generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
port map (reset, clk, Rxy_reconf, Reconfig,
RX_L_0, credit_out_L_0, valid_out_L_0, credit_in_L_0, valid_in_L_0, TX_L_0,
RX_L_1, credit_out_L_1, valid_out_L_1, credit_in_L_1, valid_in_L_1, TX_L_1,
RX_L_2, credit_out_L_2, valid_out_L_2, credit_in_L_2, valid_in_L_2, TX_L_2,
RX_L_3, credit_out_L_3, valid_out_L_3, credit_in_L_3, valid_in_L_3, TX_L_3
);
not_reset <= not reset;
-- connecting the packet generators
credit_counter_control(clk, credit_out_L_0, valid_in_L_0, credit_counter_out_0);
gen_random_packet(2, 100, 0, 33, 8, 8, 2000 ns, clk, credit_counter_out_0, valid_in_L_0, RX_L_0);
credit_counter_control(clk, credit_out_L_1, valid_in_L_1, credit_counter_out_1);
gen_random_packet(2, 100, 1, 15, 8, 8, 2000 ns, clk, credit_counter_out_1, valid_in_L_1, RX_L_1);
credit_counter_control(clk, credit_out_L_2, valid_in_L_2, credit_counter_out_2);
gen_random_packet(2, 100, 2, 6, 8, 8, 2000 ns, clk, credit_counter_out_2, valid_in_L_2, RX_L_2);
credit_counter_control(clk, credit_out_L_3, valid_in_L_3, credit_counter_out_3);
gen_random_packet(2, 100, 3, 30, 8, 8, 2000 ns, clk, credit_counter_out_3, valid_in_L_3, RX_L_3);
-- connecting the packet receivers
get_packet(32, 5, 0, clk, credit_in_L_0, valid_out_L_0, TX_L_0);
get_packet(32, 5, 1, clk, credit_in_L_1, valid_out_L_1, TX_L_1);
get_packet(32, 5, 2, clk, credit_in_L_2, valid_out_L_2, TX_L_2);
get_packet(32, 5, 3, clk, credit_in_L_3, valid_out_L_3, TX_L_3);
end;
|
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare15.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare15 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare15;
ARCHITECTURE SYN OF lpm_compare15 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(8 DOWNTO 0) <= "111100000";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 9
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "480"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
-- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
-- Retrieval info: CONNECT: @datab 0 0 9 0 480 0 0 9 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare15.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare15.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare15.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare15.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare15_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
--
-- LinearTableMul.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki ([email protected])
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
--
-- modified by t.hara
--
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity LinearTableMul is
port (
i0 : in std_logic_vector( 5 downto 0 ); -- ³µ 6bit (¬ 6bit)
i1 : in std_logic_vector( 9 downto 0 ); -- t«10bit (® 10bit)
o : out std_logic_vector( 9 downto 0 ) -- t«10bit (® 10bit)
);
end entity;
architecture rtl of LinearTableMul is
signal w_mul : std_logic_vector( 16 downto 0 ); -- t«17bit (®16bit)
begin
w_mul <= ('0' & i0) * i1;
o <= w_mul( 15 downto 6 ); -- MSBJbg, ¬ºÊ 6bitJbg
end architecture;
|
entity file1 is
end entity;
architecture test of file1 is
type char_file is file of character;
file f1 : char_file;
type string_file is file of string;
file f2 : string_file;
file f3 : string_file open WRITE_MODE is "test2.txt";
begin
process is
variable c : character;
variable s : string(1 to 3);
variable len : natural;
variable status : file_open_status;
begin
file_open(f1, "test.txt", WRITE_MODE);
write(f1, 'x');
write(f1, 'y');
write(f1, LF);
file_close(f1);
file_open(f1, "test.txt");
read(f1, c);
assert c = 'x';
read(f1, c);
assert c = 'y';
read(f1, c);
assert c = LF;
assert endfile(f1);
file_close(f1);
file_open(f2, "test.txt", READ_MODE);
read(f2, s, len);
assert s = "xy" & LF;
assert len = 3;
file_close(f2);
write(f3, "hello");
file_close(f3);
file_open(status, f3, "test2.txt", READ_MODE);
assert status = OPEN_OK;
read(f3, s, len);
assert len = 3;
assert s = "hel";
file_close(f3);
file_open(status, f3, "not_here", READ_MODE);
assert status = NAME_ERROR;
wait;
end process;
end architecture;
|
entity file1 is
end entity;
architecture test of file1 is
type char_file is file of character;
file f1 : char_file;
type string_file is file of string;
file f2 : string_file;
file f3 : string_file open WRITE_MODE is "test2.txt";
begin
process is
variable c : character;
variable s : string(1 to 3);
variable len : natural;
variable status : file_open_status;
begin
file_open(f1, "test.txt", WRITE_MODE);
write(f1, 'x');
write(f1, 'y');
write(f1, LF);
file_close(f1);
file_open(f1, "test.txt");
read(f1, c);
assert c = 'x';
read(f1, c);
assert c = 'y';
read(f1, c);
assert c = LF;
assert endfile(f1);
file_close(f1);
file_open(f2, "test.txt", READ_MODE);
read(f2, s, len);
assert s = "xy" & LF;
assert len = 3;
file_close(f2);
write(f3, "hello");
file_close(f3);
file_open(status, f3, "test2.txt", READ_MODE);
assert status = OPEN_OK;
read(f3, s, len);
assert len = 3;
assert s = "hel";
file_close(f3);
file_open(status, f3, "not_here", READ_MODE);
assert status = NAME_ERROR;
wait;
end process;
end architecture;
|
entity file1 is
end entity;
architecture test of file1 is
type char_file is file of character;
file f1 : char_file;
type string_file is file of string;
file f2 : string_file;
file f3 : string_file open WRITE_MODE is "test2.txt";
begin
process is
variable c : character;
variable s : string(1 to 3);
variable len : natural;
variable status : file_open_status;
begin
file_open(f1, "test.txt", WRITE_MODE);
write(f1, 'x');
write(f1, 'y');
write(f1, LF);
file_close(f1);
file_open(f1, "test.txt");
read(f1, c);
assert c = 'x';
read(f1, c);
assert c = 'y';
read(f1, c);
assert c = LF;
assert endfile(f1);
file_close(f1);
file_open(f2, "test.txt", READ_MODE);
read(f2, s, len);
assert s = "xy" & LF;
assert len = 3;
file_close(f2);
write(f3, "hello");
file_close(f3);
file_open(status, f3, "test2.txt", READ_MODE);
assert status = OPEN_OK;
read(f3, s, len);
assert len = 3;
assert s = "hel";
file_close(f3);
file_open(status, f3, "not_here", READ_MODE);
assert status = NAME_ERROR;
wait;
end process;
end architecture;
|
entity file1 is
end entity;
architecture test of file1 is
type char_file is file of character;
file f1 : char_file;
type string_file is file of string;
file f2 : string_file;
file f3 : string_file open WRITE_MODE is "test2.txt";
begin
process is
variable c : character;
variable s : string(1 to 3);
variable len : natural;
variable status : file_open_status;
begin
file_open(f1, "test.txt", WRITE_MODE);
write(f1, 'x');
write(f1, 'y');
write(f1, LF);
file_close(f1);
file_open(f1, "test.txt");
read(f1, c);
assert c = 'x';
read(f1, c);
assert c = 'y';
read(f1, c);
assert c = LF;
assert endfile(f1);
file_close(f1);
file_open(f2, "test.txt", READ_MODE);
read(f2, s, len);
assert s = "xy" & LF;
assert len = 3;
file_close(f2);
write(f3, "hello");
file_close(f3);
file_open(status, f3, "test2.txt", READ_MODE);
assert status = OPEN_OK;
read(f3, s, len);
assert len = 3;
assert s = "hel";
file_close(f3);
file_open(status, f3, "not_here", READ_MODE);
assert status = NAME_ERROR;
wait;
end process;
end architecture;
|
entity file1 is
end entity;
architecture test of file1 is
type char_file is file of character;
file f1 : char_file;
type string_file is file of string;
file f2 : string_file;
file f3 : string_file open WRITE_MODE is "test2.txt";
begin
process is
variable c : character;
variable s : string(1 to 3);
variable len : natural;
variable status : file_open_status;
begin
file_open(f1, "test.txt", WRITE_MODE);
write(f1, 'x');
write(f1, 'y');
write(f1, LF);
file_close(f1);
file_open(f1, "test.txt");
read(f1, c);
assert c = 'x';
read(f1, c);
assert c = 'y';
read(f1, c);
assert c = LF;
assert endfile(f1);
file_close(f1);
file_open(f2, "test.txt", READ_MODE);
read(f2, s, len);
assert s = "xy" & LF;
assert len = 3;
file_close(f2);
write(f3, "hello");
file_close(f3);
file_open(status, f3, "test2.txt", READ_MODE);
assert status = OPEN_OK;
read(f3, s, len);
assert len = 3;
assert s = "hel";
file_close(f3);
file_open(status, f3, "not_here", READ_MODE);
assert status = NAME_ERROR;
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1660.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p02n01i01660ent IS
END c09s01b00x00p02n01i01660ent;
ARCHITECTURE c09s01b00x00p02n01i01660arch OF c09s01b00x00p02n01i01660ent IS
BEGIN
B:block
signal D: BIT;
begin
D <= '1';
end; -- Failure_here
-- The reserved word block expected.
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p02n01i01660 - The reserved word block expected."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p02n01i01660arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1660.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p02n01i01660ent IS
END c09s01b00x00p02n01i01660ent;
ARCHITECTURE c09s01b00x00p02n01i01660arch OF c09s01b00x00p02n01i01660ent IS
BEGIN
B:block
signal D: BIT;
begin
D <= '1';
end; -- Failure_here
-- The reserved word block expected.
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p02n01i01660 - The reserved word block expected."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p02n01i01660arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1660.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p02n01i01660ent IS
END c09s01b00x00p02n01i01660ent;
ARCHITECTURE c09s01b00x00p02n01i01660arch OF c09s01b00x00p02n01i01660ent IS
BEGIN
B:block
signal D: BIT;
begin
D <= '1';
end; -- Failure_here
-- The reserved word block expected.
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p02n01i01660 - The reserved word block expected."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p02n01i01660arch;
|
library ieee;
use ieee.std_logic_1164.all;
-- for LHI instr. which loads the 16 bit immediate values imm16 into the most significant
-- half of an integer register and clears the least significant half (i.e. imm16 ## 0^16)
entity concat16 is
port(
-- inputs
string16 : in std_logic_vector(15 downto 0);
-- outputs
string32 : out std_logic_vector(31 downto 0) -- this goes to lhi_mux21
);
end concat16;
architecture rtl of concat16 is
begin
string32 <= string16 & X"0000";
end rtl;
|
-- NEED RESULT: ARCH00422: Dynamic elaboration passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00422
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 12.5 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00422)
-- ENT00422_Test_Bench(ARCH00422_Test_Bench)
--
-- REVISION HISTORY:
--
-- 31-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00422 of E00000 is
function f ( x,y : integer ) return integer is
constant cx : integer := x+2 ;
constant cy : integer := 2*y ;
begin
return cx + cy ;
end f ;
begin
P :
process
begin
test_report ( "ARCH00422" ,
"Dynamic elaboration" ,
f(10, 4) = (10+2) + (2*4)
) ;
wait ;
end process P ;
end ARCH00422 ;
entity ENT00422_Test_Bench is
end ENT00422_Test_Bench ;
architecture ARCH00422_Test_Bench of ENT00422_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00422 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00422_Test_Bench ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc557.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:29 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:26 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:02 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00557ent IS
END c03s04b01x00p01n01i00557ent;
ARCHITECTURE c03s04b01x00p01n01i00557arch OF c03s04b01x00p01n01i00557ent IS
type bit_file is file of bit;
BEGIN
TESTING: PROCESS
file filein : bit_file open write_mode is "iofile.08";
BEGIN
for i in 1 to 100 loop
write(filein,'1');
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00557 - The output file will be verified by test s010204.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00557arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc557.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:29 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:26 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:02 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00557ent IS
END c03s04b01x00p01n01i00557ent;
ARCHITECTURE c03s04b01x00p01n01i00557arch OF c03s04b01x00p01n01i00557ent IS
type bit_file is file of bit;
BEGIN
TESTING: PROCESS
file filein : bit_file open write_mode is "iofile.08";
BEGIN
for i in 1 to 100 loop
write(filein,'1');
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00557 - The output file will be verified by test s010204.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00557arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc557.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:29 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:26 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:02 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00557ent IS
END c03s04b01x00p01n01i00557ent;
ARCHITECTURE c03s04b01x00p01n01i00557arch OF c03s04b01x00p01n01i00557ent IS
type bit_file is file of bit;
BEGIN
TESTING: PROCESS
file filein : bit_file open write_mode is "iofile.08";
BEGIN
for i in 1 to 100 loop
write(filein,'1');
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00557 - The output file will be verified by test s010204.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00557arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gen_multiplexer is
generic(
PORT_SIZE: natural := 1;
PORT_QUANT: natural := 2); --Port quantity, la cantidad de puertos de entrada
port (
data_in: in
data_out: out std_logic_vector(PORT_SIZE-1 downto 0);
);
end;
architecture contBCD_arq of contBCD is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk,rst)
variable count: integer range 0 to 10;
begin
if rst = '1' then
s <= (others => '0');
co <= '0';
elsif rising_edge(clk) then
if ena = '1' then
count:=count + 1;
if count = 9 then
co <= '1';
elsif count = 10 then
count := 0;
co <= '0';
else
co <= '0';
end if;
end if;
end if;
s <= std_logic_vector(TO_UNSIGNED(count,4));
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memmux04 is
port (ad : std_logic_vector (1 downto 0);
val : std_logic;
dat : std_logic_vector (3 downto 0);
res : out std_logic_vector (3 downto 0));
end memmux04;
architecture behav of memmux04 is
begin
process (ad, val)
variable hi, lo : natural;
variable t : std_logic_vector(3 downto 0);
begin
lo := to_integer(unsigned(ad));
t := dat;
t (lo) := val;
res <= t;
end process;
end behav;
|
library IEEE;
use ieee.std_logic_1164.all;
entity registers is
port(
readRegister1, readRegister2, writeRegister : in std_logic_vector(4 downto 0);
writeData : in std_logic_vector(31 downto 0);
clk, rst, pre, regWrite : in std_logic;
readData1, readData2 : out std_logic_vector(31 downto 0)
);
end registers;
architecture behav of registers is
signal in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15, in16, in17, in18, in19, in20, in21, in22, in23, in24, in25, in26, in27, in28, in29, in30, in31 : std_logic_vector(31 downto 0);
signal out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10, out11, out12, out13, out14, out15, out16, out17, out18, out19, out20, out21, out22, out23, out24, out25, out26, out27, out28, out29, out30, out31 : std_logic_vector(31 downto 0);
signal ce0, ce1, ce2, ce3, ce4, ce5, ce6, ce7, ce8, ce9, ce10, ce11, ce12, ce13, ce14, ce15, ce16, ce17, ce18, ce19, ce20, ce21, ce22, ce23, ce24, ce25, ce26, ce27, ce28, ce29, ce30, ce31 : std_logic;
begin
DEMUX : entity work.one_to_thirty_two_demux(behav) port map(writeData, writeRegister, out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10, out11, out12, out13, out14, out15, out16, out17, out18, out19, out20, out21, out22, out23, out24, out25, out26, out27, out28, out29, out30, out31, ce0, ce1, ce2, ce3, ce4, ce5, ce6, ce7, ce8, ce9, ce10, ce11, ce12, ce13, ce14, ce15, ce16, ce17, ce18, ce19, ce20, ce21, ce22, ce23, ce24, ce25, ce26, ce27, ce28, ce29, ce30, ce31);
MUXA : entity work.thirty_two_to_one_mux(behav) port map(in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15, in16, in17, in18, in19, in20, in21, in22, in23, in24, in25, in26, in27, in28, in29, in30, in31, readRegister1, readData1);
MUXB : entity work.thirty_two_to_one_mux(behav) port map(in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15, in16, in17, in18, in19, in20, in21, in22, in23, in24, in25, in26, in27, in28, in29, in30, in31, readRegister2, readData2);
REG0 : entity work.thirty_two_bit_register(behav) port map(out0, clk, rst, pre, ce0, in0);
REG1 : entity work.thirty_two_bit_register(behav) port map(out1, clk, rst, pre, ce1, in1);
REG2 : entity work.thirty_two_bit_register(behav) port map(out2, clk, rst, pre, ce2, in2);
REG3 : entity work.thirty_two_bit_register(behav) port map(out3, clk, rst, pre, ce3, in3);
REG4 : entity work.thirty_two_bit_register(behav) port map(out4, clk, rst, pre, ce4, in4);
REG5 : entity work.thirty_two_bit_register(behav) port map(out5, clk, rst, pre, ce5, in5);
REG6 : entity work.thirty_two_bit_register(behav) port map(out6, clk, rst, pre, ce6, in6);
REG7 : entity work.thirty_two_bit_register(behav) port map(out7, clk, rst, pre, ce7, in7);
REG8 : entity work.thirty_two_bit_register(behav) port map(out8, clk, rst, pre, ce8, in8);
REG9 : entity work.thirty_two_bit_register(behav) port map(out9, clk, rst, pre, ce9, in9);
REG10 : entity work.thirty_two_bit_register(behav) port map(out10, clk, rst, pre, ce10, in10);
REG11 : entity work.thirty_two_bit_register(behav) port map(out11, clk, rst, pre, ce11, in11);
REG12 : entity work.thirty_two_bit_register(behav) port map(out12, clk, rst, pre, ce12, in12);
REG13 : entity work.thirty_two_bit_register(behav) port map(out13, clk, rst, pre, ce13, in13);
REG14 : entity work.thirty_two_bit_register(behav) port map(out14, clk, rst, pre, ce14, in14);
REG15 : entity work.thirty_two_bit_register(behav) port map(out15, clk, rst, pre, ce15, in15);
REG16 : entity work.thirty_two_bit_register(behav) port map(out16, clk, rst, pre, ce16, in16);
REG17 : entity work.thirty_two_bit_register(behav) port map(out17, clk, rst, pre, ce17, in17);
REG18 : entity work.thirty_two_bit_register(behav) port map(out18, clk, rst, pre, ce18, in18);
REG19 : entity work.thirty_two_bit_register(behav) port map(out19, clk, rst, pre, ce19, in19);
REG20 : entity work.thirty_two_bit_register(behav) port map(out20, clk, rst, pre, ce20, in20);
REG21 : entity work.thirty_two_bit_register(behav) port map(out21, clk, rst, pre, ce21, in21);
REG22 : entity work.thirty_two_bit_register(behav) port map(out22, clk, rst, pre, ce22, in22);
REG23 : entity work.thirty_two_bit_register(behav) port map(out23, clk, rst, pre, ce23, in23);
REG24 : entity work.thirty_two_bit_register(behav) port map(out24, clk, rst, pre, ce24, in24);
REG25 : entity work.thirty_two_bit_register(behav) port map(out25, clk, rst, pre, ce25, in25);
REG26 : entity work.thirty_two_bit_register(behav) port map(out26, clk, rst, pre, ce26, in26);
REG27 : entity work.thirty_two_bit_register(behav) port map(out27, clk, rst, pre, ce27, in27);
REG28 : entity work.thirty_two_bit_register(behav) port map(out28, clk, rst, pre, ce28, in28);
REG29 : entity work.thirty_two_bit_register(behav) port map(out29, clk, rst, pre, ce29, in29);
REG30 : entity work.thirty_two_bit_register(behav) port map(out30, clk, rst, pre, ce30, in30);
REG31 : entity work.thirty_two_bit_register(behav) port map(out31, clk, rst, pre, ce31, in31);
end behav; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3cg
-- File: leon3cg.vhd
-- Author: Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3 component with clock gating
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity leon3cg is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic; -- AHB clock (free-running)
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
gclk : in std_ulogic -- gated clock
);
end;
architecture rtl of leon3cg is
signal gnd, vcc : std_logic;
signal fpuo : grfpu_out_type;
begin
gnd <= '0'; vcc <= '1';
fpuo <= grfpu_out_none;
leon3x0 : leon3x
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => 0,
fpft => 0,
cmft => 0,
iuinj => 0,
ceinj => 0,
cached => cached,
clk2x => 0,
netlist => 0,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp,
npasi => npasi,
pwrpsr => pwrpsr,
rex => rex,
altwin => altwin)
port map (
clk => gnd,
gclk2 => gclk,
gfclk2 => clk,
clk2 => clk,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi,
irqo => irqo,
dbgi => dbgi,
dbgo => dbgo,
fpui => open,
fpuo => fpuo,
clken => vcc
);
end;
|
--------------------------------------------------------------------------------
-- file name : glb_stellar_cmd.vhd
--
-- author : e. barhorst
--
-- company : 4dsp
--
-- item : number
--
-- units : entity
-- arch_itecture
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
-- from
-- ver pcb mod date changes
-- === ======= ======== =======
--
-- 0.0 0 19-01-2009 new version
-- 31-08-2009 added the mailbox input port
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Specify libraries
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- Entity declaration
--------------------------------------------------------------------------------
entity stellar_cmd is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"0000010"
);
port (
reset : in std_logic;
-- Command interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
cmd_always_ack : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_val_ack : out std_logic; --the out_reg has valid data and expects and acknowledge back (pulse)
out_reg_addr : out std_logic_vector(27 downto 0);--out register address
in_reg : in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0);--requested address
--write acknowledge interface
wr_ack : in std_logic := '0'; --pulse to indicate write is done
-- Mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end entity stellar_cmd;
--------------------------------------------------------------------------------
-- Architecture declaration
--------------------------------------------------------------------------------
architecture arch_stellar_cmd of stellar_cmd is
-----------------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------------
constant CMD_WR : std_logic_vector(3 downto 0) := x"1";
constant CMD_RD : std_logic_vector(3 downto 0) := x"2";
constant CMD_RD_ACK : std_logic_vector(3 downto 0) := x"4";
constant CMD_WR_ACK : std_logic_vector(3 downto 0) := x"5";
constant CMD_WR_EXPECTS_ACK : std_logic_vector(3 downto 0) := x"6";
-----------------------------------------------------------------------------------
-- Dignal declarations
-----------------------------------------------------------------------------------
signal register_wr : std_logic;
signal register_wr_ack : std_logic;
signal register_rd : std_logic;
signal out_cmd_val_sig : std_logic;
signal in_reg_addr_sig : std_logic_vector(27 downto 0);
signal out_reg_addr_sig : std_logic_vector(27 downto 0);
signal mbx_in_val_sig : std_logic;
signal mbx_received : std_logic;
signal wr_ack_sig : std_logic;
-----------------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------------
component pulse2pulse
port (
in_clk : in std_logic;
out_clk : in std_logic;
rst : in std_logic;
pulsein : in std_logic;
inbusy : out std_logic;
pulseout : out std_logic
);
end component;
-----------------------------------------------------------------------------------
-- Begin
-----------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------------
p2p0: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_wr,
inbusy => open,
pulseout => out_reg_val
);
p2p1: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_rd,
inbusy => open,
pulseout => in_reg_req
);
p2p2: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd,
rst => reset,
pulsein => in_reg_val,
inbusy => open,
pulseout => out_cmd_val_sig
);
p2p3: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd ,
rst => reset,
pulsein => mbx_in_val,
inbusy => open,
pulseout => mbx_in_val_sig
);
p2p4: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd ,
rst => reset,
pulsein => wr_ack,
inbusy => open,
pulseout => wr_ack_sig
);
p2p5: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_wr_ack,
inbusy => open,
pulseout => out_reg_val_ack
);
-----------------------------------------------------------------------------------
-- Synchronous processes
-----------------------------------------------------------------------------------
in_reg_proc: process (reset, clk_cmd)
begin
if (reset = '1') then
in_reg_addr_sig <= (others => '0');
register_rd <= '0';
mbx_received <= '0';
out_cmd <= (others => '0');
out_cmd_val <= '0';
elsif (clk_cmd'event and clk_cmd = '1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_RD and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
in_reg_addr_sig <= in_cmd(59 downto 32)-start_addr;
end if;
--generate the read req pulse when the address is in the modules range
if ((in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_RD and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) or cmd_always_ack = '1') then
register_rd <= '1';
else
register_rd <= '0';
end if;
--mailbox has less priority then command acknowledge
--create the output packet
if (out_cmd_val_sig = '1' and mbx_in_val_sig = '1') then
mbx_received <= '1';
elsif( mbx_received = '1' and out_cmd_val_sig = '0') then
mbx_received <= '0';
end if;
if (out_cmd_val_sig = '1') then
out_cmd(31 downto 0) <= in_reg;
out_cmd(59 downto 32) <= in_reg_addr_sig+start_addr;
out_cmd(63 downto 60) <= CMD_RD_ACK;
elsif (mbx_in_val_sig = '1' or mbx_received = '1') then
out_cmd(31 downto 0) <= mbx_in_reg;
out_cmd(59 downto 32) <= start_addr;
out_cmd(63 downto 60) <= (others=>'0');
elsif (wr_ack_sig = '1' ) then
out_cmd(31 downto 0) <= mbx_in_reg;
out_cmd(59 downto 32) <= out_reg_addr_sig+start_addr;
out_cmd(63 downto 60) <= CMD_WR_ACK;
else
out_cmd(63 downto 0) <= (others=>'0');
end if;
if (out_cmd_val_sig = '1') then
out_cmd_val <= '1';
elsif (mbx_in_val_sig = '1' or mbx_received = '1') then
out_cmd_val <= '1';
elsif (wr_ack_sig = '1') then
out_cmd_val <= '1';
else
out_cmd_val <= '0';
end if;
end if;
end process;
out_reg_proc: process(reset, clk_cmd)
begin
if (reset = '1') then
out_reg_addr_sig <= (others => '0');
out_reg <= (others => '0');
register_wr <= '0';
register_wr_ack <= '0';
elsif(clk_cmd'event and clk_cmd = '1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and (in_cmd(63 downto 60) = CMD_WR or in_cmd(63 downto 60) = CMD_WR_EXPECTS_ACK)
and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
out_reg_addr_sig <= in_cmd(59 downto 32) - start_addr;
out_reg <= in_cmd(31 downto 0);
end if;
--generate the write req pulse when the address is in the modules range
if (in_cmd_val = '1' and (in_cmd(63 downto 60) = CMD_WR or in_cmd(63 downto 60) = CMD_WR_EXPECTS_ACK)
and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
register_wr <= '1';
else
register_wr <= '0';
end if;
--generate the write requests ack pulse when the address is in the modules range and command is write that expects an ack
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_WR_EXPECTS_ACK and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
register_wr_ack <= '1';
else
register_wr_ack <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
-- Asynchronous mapping
-----------------------------------------------------------------------------------
in_reg_addr <= in_reg_addr_sig;
out_reg_addr <= out_reg_addr_sig;
-----------------------------------------------------------------------------------
-- End
-----------------------------------------------------------------------------------
end architecture arch_stellar_cmd;
|
--------------------------------------------------------------------------------
-- Generated from template tb_template.vhdl by hexconv.pl
--------------------------------------------------------------------------------
-- Light8080 simulation test bench.
--------------------------------------------------------------------------------
-- Source for the 8080 program is in asm\tb0.asm
--------------------------------------------------------------------------------
--
-- This test bench provides a simulated CPU system to test programs. This test
-- bench does not do any assertions or checks, all assertions are left to the
-- software.
--
-- The simulated environment has 2KB of RAM, mirror-mapped to all the memory
-- map of the 8080, initialized with the test program object code. See the perl
-- script 'util\hexconv.pl' and BAT files in the asm directory.
--
-- Besides, it provides some means to trigger hardware irq from software,
-- including the specification of the instructions fed to the CPU as interrupt
-- vectors during inta cycles.
--
-- We will simulate 8 possible irq sources. The software can trigger any one of
-- them by writing at registers 0x010 and 0x011. Register 0x010 holds the irq
-- source to be triggered (0 to 7) and register 0x011 holds the number of clock
-- cycles that will elapse from the end of the instruction that writes to the
-- register to the assertion of intr.
--
-- When the interrupt is acknowledged and inta is asserted, the test bench reads
-- the value at register 0x010 as the irq source, and feeds an instruction to
-- the CPU starting from the RAM address 0040h+source*4.
-- That is, address range 0040h-005fh is reserved for the simulated 'interrupt
-- vectors', a total of 4 bytes for each of the 8 sources. This allows the
-- software to easily test different interrupt vectors without any hand
-- assembly. All of this is strictly simulation-only stuff.
--
--
-- Upon completion, the software must write a value to register 0x020. Writing
-- a 0x055 means 'success', writing a 0x0aa means 'failure'. Success and
-- failure conditions are defined by the software.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity light8080_tb0 is
end entity light8080_tb0;
architecture behavior of light8080_tb0 is
--------------------------------------------------------------------------------
-- Simulation parameters
-- T: simulated clock period
constant T : time := 100 ns;
-- MAX_SIM_LENGTH: maximum simulation time
constant MAX_SIM_LENGTH : time := T*7000; -- enough for the tb0
--------------------------------------------------------------------------------
-- Component Declaration for the Unit Under Test (UUT)
component light8080
port (
addr_out : out std_logic_vector(15 downto 0);
inta : out std_logic;
inte : out std_logic;
halt : out std_logic;
intr : in std_logic;
vma : out std_logic;
io : out std_logic;
rd : out std_logic;
wr : out std_logic;
fetch : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
clk : in std_logic;
reset : in std_logic );
end component;
signal data_i : std_logic_vector(7 downto 0) := (others=>'0');
signal vma_o : std_logic;
signal rd_o : std_logic;
signal wr_o : std_logic;
signal io_o : std_logic;
signal data_o : std_logic_vector(7 downto 0);
signal data_mem : std_logic_vector(7 downto 0);
signal addr_o : std_logic_vector(15 downto 0);
signal fetch_o : std_logic;
signal inta_o : std_logic;
signal inte_o : std_logic;
signal intr_i : std_logic := '0';
signal halt_o : std_logic;
signal reset : std_logic := '0';
signal clk : std_logic := '1';
signal done : std_logic := '0';
type t_rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom : t_rom := (
X"31",X"f3",X"05",X"3e",X"77",X"e6",X"00",X"ca",
X"0d",X"00",X"cd",X"e0",X"04",X"d2",X"13",X"00",
X"cd",X"e0",X"04",X"ea",X"19",X"00",X"cd",X"e0",
X"04",X"f2",X"1f",X"00",X"cd",X"e0",X"04",X"c2",
X"2e",X"00",X"da",X"2e",X"00",X"e2",X"2e",X"00",
X"fa",X"2e",X"00",X"c3",X"31",X"00",X"cd",X"e0",
X"04",X"c6",X"06",X"c2",X"39",X"00",X"cd",X"e0",
X"04",X"da",X"42",X"00",X"e2",X"42",X"00",X"f2",
X"45",X"00",X"cd",X"e0",X"04",X"c6",X"70",X"e2",
X"4d",X"00",X"cd",X"e0",X"04",X"fa",X"56",X"00",
X"ca",X"56",X"00",X"d2",X"59",X"00",X"cd",X"e0",
X"04",X"c6",X"81",X"fa",X"61",X"00",X"cd",X"e0",
X"04",X"ca",X"6a",X"00",X"da",X"6a",X"00",X"e2",
X"6d",X"00",X"cd",X"e0",X"04",X"c6",X"fe",X"da",
X"75",X"00",X"cd",X"e0",X"04",X"ca",X"7e",X"00",
X"e2",X"7e",X"00",X"fa",X"81",X"00",X"cd",X"e0",
X"04",X"fe",X"00",X"da",X"99",X"00",X"ca",X"99",
X"00",X"fe",X"f5",X"da",X"99",X"00",X"c2",X"99",
X"00",X"fe",X"ff",X"ca",X"99",X"00",X"da",X"9c",
X"00",X"cd",X"e0",X"04",X"ce",X"0a",X"ce",X"0a",
X"fe",X"0b",X"ca",X"a8",X"00",X"cd",X"e0",X"04",
X"d6",X"0c",X"d6",X"0f",X"fe",X"f0",X"ca",X"b4",
X"00",X"cd",X"e0",X"04",X"de",X"f1",X"de",X"0e",
X"fe",X"f0",X"ca",X"c0",X"00",X"cd",X"e0",X"04",
X"e6",X"55",X"fe",X"50",X"ca",X"ca",X"00",X"cd",
X"e0",X"04",X"f6",X"3a",X"fe",X"7a",X"ca",X"d4",
X"00",X"cd",X"e0",X"04",X"ee",X"0f",X"fe",X"75",
X"ca",X"de",X"00",X"cd",X"e0",X"04",X"e6",X"00",
X"dc",X"e0",X"04",X"e4",X"e0",X"04",X"fc",X"e0",
X"04",X"c4",X"e0",X"04",X"fe",X"00",X"ca",X"f4",
X"00",X"cd",X"e0",X"04",X"d6",X"77",X"d4",X"e0",
X"04",X"ec",X"e0",X"04",X"f4",X"e0",X"04",X"cc",
X"e0",X"04",X"fe",X"89",X"ca",X"0a",X"01",X"cd",
X"e0",X"04",X"e6",X"ff",X"e4",X"17",X"01",X"fe",
X"d9",X"ca",X"74",X"01",X"cd",X"e0",X"04",X"e8",
X"c6",X"10",X"ec",X"23",X"01",X"c6",X"02",X"e0",
X"cd",X"e0",X"04",X"e0",X"c6",X"20",X"fc",X"2f",
X"01",X"c6",X"04",X"e8",X"cd",X"e0",X"04",X"f0",
X"c6",X"80",X"f4",X"3b",X"01",X"c6",X"80",X"f8",
X"cd",X"e0",X"04",X"f8",X"c6",X"40",X"d4",X"47",
X"01",X"c6",X"40",X"f0",X"cd",X"e0",X"04",X"d8",
X"c6",X"8f",X"dc",X"53",X"01",X"d6",X"02",X"d0",
X"cd",X"e0",X"04",X"d0",X"c6",X"f7",X"c4",X"5f",
X"01",X"c6",X"fe",X"d8",X"cd",X"e0",X"04",X"c8",
X"c6",X"01",X"cc",X"6b",X"01",X"c6",X"d0",X"c0",
X"cd",X"e0",X"04",X"c0",X"c6",X"47",X"fe",X"47",
X"c8",X"cd",X"e0",X"04",X"3e",X"77",X"3c",X"47",
X"04",X"48",X"0d",X"51",X"5a",X"63",X"6c",X"7d",
X"3d",X"4f",X"59",X"6b",X"45",X"50",X"62",X"7c",
X"57",X"14",X"6a",X"4d",X"0c",X"61",X"44",X"05",
X"58",X"7b",X"5f",X"1c",X"43",X"60",X"24",X"4c",
X"69",X"55",X"15",X"7a",X"67",X"25",X"54",X"42",
X"68",X"2c",X"5d",X"1d",X"4b",X"79",X"6f",X"2d",
X"65",X"5c",X"53",X"4a",X"41",X"78",X"fe",X"77",
X"c4",X"e0",X"04",X"af",X"06",X"01",X"0e",X"03",
X"16",X"07",X"1e",X"0f",X"26",X"1f",X"2e",X"3f",
X"80",X"81",X"82",X"83",X"84",X"85",X"87",X"fe",
X"f0",X"c4",X"e0",X"04",X"90",X"91",X"92",X"93",
X"94",X"95",X"fe",X"78",X"c4",X"e0",X"04",X"97",
X"c4",X"e0",X"04",X"3e",X"80",X"87",X"06",X"01",
X"0e",X"02",X"16",X"03",X"1e",X"04",X"26",X"05",
X"2e",X"06",X"88",X"06",X"80",X"80",X"80",X"89",
X"80",X"80",X"8a",X"80",X"80",X"8b",X"80",X"80",
X"8c",X"80",X"80",X"8d",X"80",X"80",X"8f",X"fe",
X"37",X"c4",X"e0",X"04",X"3e",X"80",X"87",X"06",
X"01",X"98",X"06",X"ff",X"80",X"99",X"80",X"9a",
X"80",X"9b",X"80",X"9c",X"80",X"9d",X"fe",X"e0",
X"c4",X"e0",X"04",X"3e",X"80",X"87",X"9f",X"fe",
X"ff",X"c4",X"e0",X"04",X"3e",X"ff",X"06",X"fe",
X"0e",X"fc",X"16",X"ef",X"1e",X"7f",X"26",X"f4",
X"2e",X"bf",X"a7",X"a1",X"a2",X"a3",X"a4",X"a5",
X"a7",X"fe",X"24",X"c4",X"e0",X"04",X"af",X"06",
X"01",X"0e",X"02",X"16",X"04",X"1e",X"08",X"26",
X"10",X"2e",X"20",X"b0",X"b1",X"b2",X"b3",X"b4",
X"b5",X"b7",X"fe",X"3f",X"c4",X"e0",X"04",X"3e",
X"00",X"26",X"8f",X"2e",X"4f",X"a8",X"a9",X"aa",
X"ab",X"ac",X"ad",X"fe",X"cf",X"c4",X"e0",X"04",
X"af",X"c4",X"e0",X"04",X"06",X"44",X"0e",X"45",
X"16",X"46",X"1e",X"47",X"26",X"04",X"2e",X"ec",
X"70",X"06",X"00",X"46",X"3e",X"44",X"b8",X"c4",
X"e0",X"04",X"72",X"16",X"00",X"56",X"3e",X"46",
X"ba",X"c4",X"e0",X"04",X"73",X"1e",X"00",X"5e",
X"3e",X"47",X"bb",X"c4",X"e0",X"04",X"74",X"26",
X"04",X"2e",X"ec",X"66",X"3e",X"04",X"bc",X"c4",
X"e0",X"04",X"75",X"26",X"04",X"2e",X"ec",X"6e",
X"3e",X"ec",X"bd",X"c4",X"e0",X"04",X"26",X"04",
X"2e",X"ec",X"3e",X"32",X"77",X"be",X"c4",X"e0",
X"04",X"86",X"fe",X"64",X"c4",X"e0",X"04",X"af",
X"7e",X"fe",X"32",X"c4",X"e0",X"04",X"26",X"04",
X"2e",X"ec",X"7e",X"96",X"c4",X"e0",X"04",X"3e",
X"80",X"87",X"8e",X"fe",X"33",X"c4",X"e0",X"04",
X"3e",X"80",X"87",X"9e",X"fe",X"cd",X"c4",X"e0",
X"04",X"a6",X"c4",X"e0",X"04",X"3e",X"25",X"b6",
X"fe",X"37",X"c4",X"e0",X"04",X"ae",X"fe",X"05",
X"c4",X"e0",X"04",X"36",X"55",X"34",X"35",X"86",
X"fe",X"5a",X"c4",X"e0",X"04",X"01",X"ff",X"12",
X"11",X"ff",X"12",X"21",X"ff",X"12",X"03",X"13",
X"23",X"3e",X"13",X"b8",X"c4",X"e0",X"04",X"ba",
X"c4",X"e0",X"04",X"bc",X"c4",X"e0",X"04",X"3e",
X"00",X"b9",X"c4",X"e0",X"04",X"bb",X"c4",X"e0",
X"04",X"bd",X"c4",X"e0",X"04",X"0b",X"1b",X"2b",
X"3e",X"12",X"b8",X"c4",X"e0",X"04",X"ba",X"c4",
X"e0",X"04",X"bc",X"c4",X"e0",X"04",X"3e",X"ff",
X"b9",X"c4",X"e0",X"04",X"bb",X"c4",X"e0",X"04",
X"bd",X"c4",X"e0",X"04",X"32",X"ec",X"04",X"af",
X"3a",X"ec",X"04",X"fe",X"ff",X"c4",X"e0",X"04",
X"2a",X"ea",X"04",X"22",X"ec",X"04",X"3a",X"ea",
X"04",X"47",X"3a",X"ec",X"04",X"b8",X"c4",X"e0",
X"04",X"3a",X"eb",X"04",X"47",X"3a",X"ed",X"04",
X"b8",X"c4",X"e0",X"04",X"3e",X"aa",X"32",X"ec",
X"04",X"44",X"4d",X"af",X"0a",X"fe",X"aa",X"c4",
X"e0",X"04",X"3c",X"02",X"3a",X"ec",X"04",X"fe",
X"ab",X"c4",X"e0",X"04",X"3e",X"77",X"32",X"ec",
X"04",X"2a",X"ea",X"04",X"11",X"00",X"00",X"eb",
X"af",X"1a",X"fe",X"77",X"c4",X"e0",X"04",X"af",
X"84",X"85",X"c4",X"e0",X"04",X"3e",X"cc",X"12",
X"3a",X"ec",X"04",X"fe",X"cc",X"12",X"3a",X"ec",
X"04",X"fe",X"cc",X"c4",X"e0",X"04",X"21",X"77",
X"77",X"29",X"3e",X"ee",X"bc",X"c4",X"e0",X"04",
X"bd",X"c4",X"e0",X"04",X"21",X"55",X"55",X"01",
X"ff",X"ff",X"09",X"3e",X"55",X"d4",X"e0",X"04",
X"bc",X"c4",X"e0",X"04",X"3e",X"54",X"bd",X"c4",
X"e0",X"04",X"21",X"aa",X"aa",X"11",X"33",X"33",
X"19",X"3e",X"dd",X"bc",X"c4",X"e0",X"04",X"bd",
X"c4",X"e0",X"04",X"37",X"d4",X"e0",X"04",X"3f",
X"dc",X"e0",X"04",X"3e",X"aa",X"2f",X"fe",X"55",
X"c4",X"e0",X"04",X"b7",X"27",X"fe",X"55",X"c4",
X"e0",X"04",X"3e",X"88",X"87",X"27",X"fe",X"76",
X"c4",X"e0",X"04",X"af",X"3e",X"aa",X"27",X"d4",
X"e0",X"04",X"fe",X"10",X"c4",X"e0",X"04",X"af",
X"3e",X"9a",X"27",X"d4",X"e0",X"04",X"c4",X"e0",
X"04",X"37",X"3e",X"42",X"07",X"dc",X"e0",X"04",
X"07",X"d4",X"e0",X"04",X"fe",X"09",X"c4",X"e0",
X"04",X"0f",X"d4",X"e0",X"04",X"0f",X"fe",X"42",
X"c4",X"e0",X"04",X"17",X"17",X"d4",X"e0",X"04",
X"fe",X"08",X"c4",X"e0",X"04",X"1f",X"1f",X"dc",
X"e0",X"04",X"fe",X"02",X"c4",X"e0",X"04",X"01",
X"34",X"12",X"11",X"aa",X"aa",X"21",X"55",X"55",
X"af",X"c5",X"d5",X"e5",X"f5",X"01",X"00",X"00",
X"11",X"00",X"00",X"21",X"00",X"00",X"3e",X"c0",
X"c6",X"f0",X"f1",X"e1",X"d1",X"c1",X"dc",X"e0",
X"04",X"c4",X"e0",X"04",X"e4",X"e0",X"04",X"fc",
X"e0",X"04",X"3e",X"12",X"b8",X"c4",X"e0",X"04",
X"3e",X"34",X"b9",X"c4",X"e0",X"04",X"3e",X"aa",
X"ba",X"c4",X"e0",X"04",X"bb",X"c4",X"e0",X"04",
X"3e",X"55",X"bc",X"c4",X"e0",X"04",X"bd",X"c4",
X"e0",X"04",X"21",X"00",X"00",X"39",X"22",X"f1",
X"04",X"31",X"f0",X"04",X"3b",X"3b",X"33",X"3b",
X"3e",X"55",X"32",X"ee",X"04",X"2f",X"32",X"ef",
X"04",X"c1",X"b8",X"c4",X"e0",X"04",X"2f",X"b9",
X"c4",X"e0",X"04",X"21",X"f0",X"04",X"f9",X"21",
X"33",X"77",X"3b",X"3b",X"e3",X"3a",X"ef",X"04",
X"fe",X"77",X"c4",X"e0",X"04",X"3a",X"ee",X"04",
X"fe",X"33",X"c4",X"e0",X"04",X"3e",X"55",X"bd",
X"c4",X"e0",X"04",X"2f",X"bc",X"c4",X"e0",X"04",
X"2a",X"f1",X"04",X"f9",X"21",X"e5",X"04",X"e9",
X"3e",X"aa",X"d3",X"20",X"76",X"3e",X"55",X"d3",
X"20",X"76",X"ec",X"04",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"
);
signal irq_vector_byte: std_logic_vector(7 downto 0);
signal irq_source : integer range 0 to 7;
signal cycles_to_intr : integer range -10 to 255;
signal int_vector_index : integer range 0 to 3;
signal addr_vector_table: integer range 0 to 65535;
begin
-- Instantiate the Unit Under Test (UUT)
uut: light8080 PORT MAP(
clk => clk,
reset => reset,
vma => vma_o,
rd => rd_o,
wr => wr_o,
io => io_o,
fetch => fetch_o,
addr_out => addr_o,
data_in => data_i,
data_out => data_o,
intr => intr_i,
inte => inte_o,
inta => inta_o,
halt => halt_o
);
-- clock: run clock until test is done
clock:
process(done, clk)
begin
if done = '0' then
clk <= not clk after T/2;
end if;
end process clock;
-- Drive reset and done
main_test:
process
begin
-- Assert reset for at least one full clk period
reset <= '1';
wait until clk = '1';
wait for T/2;
reset <= '0';
-- Remember to 'cut away' the preceding 3 clk semiperiods from
-- the wait statement...
wait for (MAX_SIM_LENGTH - T*1.5);
-- Maximum sim time elapsed, assume the program ran away and
-- stop the clk process asserting 'done' (which will stop the simulation)
done <= '1';
assert (done = '1')
report "Test timed out."
severity failure;
wait;
end process main_test;
-- Synchronous RAM; 2KB mirrored everywhere
synchronous_ram:
process(clk)
begin
if (clk'event and clk='1') then
data_mem <= rom(conv_integer(addr_o(10 downto 0)));
if wr_o = '1' and addr_o(15 downto 11)="00000" then
rom(conv_integer(addr_o(10 downto 0))) <= data_o;
end if;
end if;
end process synchronous_ram;
irq_trigger_register:
process(clk)
begin
if (clk'event and clk='1') then
if reset='1' then
cycles_to_intr <= -10; -- meaning no interrupt pending
intr_i <= '0';
else
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"11" then
cycles_to_intr <= conv_integer(data_o) + 1;
else
if cycles_to_intr >= 0 then
cycles_to_intr <= cycles_to_intr - 1;
end if;
if cycles_to_intr = 0 then
intr_i <= '1';
else
intr_i <= '0';
end if;
end if;
end if;
end if;
end process irq_trigger_register;
irq_source_register:
process(clk)
begin
if (clk'event and clk='1') then
if reset='1' then
irq_source <= 0;
else
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"10" then
irq_source <= conv_integer(data_o(2 downto 0));
end if;
end if;
end if;
end process irq_source_register;
-- 'interrupt vector' logic.
irq_vector_table:
process(clk)
begin
if (clk'event and clk='1') then
if vma_o = '1' and rd_o='1' then
if inta_o = '1' then
int_vector_index <= int_vector_index + 1;
else
int_vector_index <= 0;
end if;
end if;
-- this is the address of the byte we'll feed to the CPU
addr_vector_table <= 64+irq_source*4+int_vector_index;
end if;
end process irq_vector_table;
irq_vector_byte <= rom(addr_vector_table);
data_i <= data_mem when inta_o='0' else irq_vector_byte;
test_outcome_register:
process(clk)
variable outcome : std_logic_vector(7 downto 0);
begin
if (clk'event and clk='1') then
if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"20" then
assert (data_o /= X"55") report "Software reports SUCCESS" severity failure;
assert (data_o /= X"aa") report "Software reports FAILURE" severity failure;
assert ((data_o = X"aa") or (data_o = X"55"))
report "Software reports unexpected outcome value."
severity failure;
end if;
end if;
end process test_outcome_register;
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux IS
GENERIC (N : POSITIVE := 8);
PORT(
a, b, c, d, e, f : IN std_logic_vector(N-1 DOWNTO 0);
sel : IN std_logic_vector(3 DOWNTO 0);
S : OUT std_logic_vector(N-1 DOWNTO 0)
);
END ENTITY mux;
ARCHITECTURE Behavior OF mux IS
SIGNAL Qs : STD_LOGIC_VECTOR(N-1 DOWNTO 0);
BEGIN
mux : PROCESS(sel)
BEGIN
CASE sel IS
when "0011" =>
Qs <= a;
when "0100" =>
Qs <= b;
when "0101" =>
Qs <= c;
when "0110" =>
Qs <= d;
when "0111" =>
Qs <= e;
when "1000" =>
Qs <= f;
when others =>
NULL;
END CASE;
END PROCESS mux;
S <= Qs;
END ARCHITECTURE Behavior;
|
-- NEED RESULT: ARCH00690: Allocators with generic scalar qualified expression passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00690
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.6 (3)
-- 7.3.6 (6)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00690)
-- ENT00690_Test_Bench(ARCH00690_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00690 of GENERIC_STANDARD_TYPES is
begin
process
variable correct : boolean := true ;
type a_boolean is access boolean ;
variable va_boolean_1, va_boolean_2 : a_boolean
:= new boolean ;
type a_bit is access bit ;
variable va_bit_1, va_bit_2 : a_bit
:= new bit ;
type a_severity_level is access severity_level ;
variable va_severity_level_1, va_severity_level_2 : a_severity_level
:= new severity_level ;
type a_character is access character ;
variable va_character_1, va_character_2 : a_character
:= new character ;
type a_t_enum1 is access t_enum1 ;
variable va_t_enum1_1, va_t_enum1_2 : a_t_enum1
:= new t_enum1 ;
type a_st_enum1 is access st_enum1 ;
variable va_st_enum1_1, va_st_enum1_2 : a_st_enum1
:= new st_enum1 ;
type a_integer is access integer ;
variable va_integer_1, va_integer_2 : a_integer
:= new integer ;
type a_t_int1 is access t_int1 ;
variable va_t_int1_1, va_t_int1_2 : a_t_int1
:= new t_int1 ;
type a_st_int1 is access st_int1 ;
variable va_st_int1_1, va_st_int1_2 : a_st_int1
:= new st_int1 ;
type a_time is access time ;
variable va_time_1, va_time_2 : a_time
:= new time ;
type a_t_phys1 is access t_phys1 ;
variable va_t_phys1_1, va_t_phys1_2 : a_t_phys1
:= new t_phys1 ;
type a_st_phys1 is access st_phys1 ;
variable va_st_phys1_1, va_st_phys1_2 : a_st_phys1
:= new st_phys1 ;
type a_real is access real ;
variable va_real_1, va_real_2 : a_real
:= new real ;
type a_t_real1 is access t_real1 ;
variable va_t_real1_1, va_t_real1_2 : a_t_real1
:= new t_real1 ;
type a_st_real1 is access st_real1 ;
variable va_st_real1_1, va_st_real1_2 : a_st_real1
:= new st_real1 ;
begin
va_boolean_1 := new boolean ' (c_boolean_1) ;
va_bit_1 := new bit ' (c_bit_1) ;
va_severity_level_1 := new severity_level ' (c_severity_level_1) ;
va_character_1 := new character ' (c_character_1) ;
va_t_enum1_1 := new t_enum1 ' (c_t_enum1_1) ;
va_st_enum1_1 := new st_enum1 ' (c_st_enum1_1) ;
va_integer_1 := new integer ' (c_integer_1) ;
va_t_int1_1 := new t_int1 ' (c_t_int1_1) ;
va_st_int1_1 := new st_int1 ' (c_st_int1_1) ;
va_time_1 := new time ' (c_time_1) ;
va_t_phys1_1 := new t_phys1 ' (c_t_phys1_1) ;
va_st_phys1_1 := new st_phys1 ' (c_st_phys1_1) ;
va_real_1 := new real ' (c_real_1) ;
va_t_real1_1 := new t_real1 ' (c_t_real1_1) ;
va_st_real1_1 := new st_real1 ' (c_st_real1_1) ;
correct := correct and
va_boolean_1.all = c_boolean_1 ;
correct := correct and
va_bit_1.all = c_bit_1 ;
correct := correct and
va_severity_level_1.all = c_severity_level_1 ;
correct := correct and
va_character_1.all = c_character_1 ;
correct := correct and
va_t_enum1_1.all = c_t_enum1_1 ;
correct := correct and
va_st_enum1_1.all = c_st_enum1_1 ;
correct := correct and
va_integer_1.all = c_integer_1 ;
correct := correct and
va_t_int1_1.all = c_t_int1_1 ;
correct := correct and
va_st_int1_1.all = c_st_int1_1 ;
correct := correct and
va_time_1.all = c_time_1 ;
correct := correct and
va_t_phys1_1.all = c_t_phys1_1 ;
correct := correct and
va_st_phys1_1.all = c_st_phys1_1 ;
correct := correct and
va_real_1.all = c_real_1 ;
correct := correct and
va_t_real1_1.all = c_t_real1_1 ;
correct := correct and
va_st_real1_1.all = c_st_real1_1 ;
test_report ( "ARCH00690" ,
"Allocators with generic scalar qualified expression" ,
correct) ;
wait ;
end process ;
end ARCH00690 ;
--
entity ENT00690_Test_Bench is
end ENT00690_Test_Bench ;
--
architecture ARCH00690_Test_Bench of ENT00690_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00690 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00690_Test_Bench ;
|
library ieee;
use ieee.std_logic_1164.all;
entity slice03 is
port (di : std_logic_vector(7 downto 0);
do : out std_logic_vector (3 downto 0));
end slice03;
architecture behav of slice03 is
begin
do <= di (7 downto 4)(7 downto 4);
end behav;
|
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2; --double sync by default
kResetPolarity : std_logic := '1'); --aReset active-high by default
Port (
aReset : in STD_LOGIC; -- active-high/active-low asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aReset)
begin
if (aReset = kResetPolarity) then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2; --double sync by default
kResetPolarity : std_logic := '1'); --aReset active-high by default
Port (
aReset : in STD_LOGIC; -- active-high/active-low asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aReset)
begin
if (aReset = kResetPolarity) then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid !
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0);
-- Checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic
);
end allocator_credit_counter_logic_pseudo_checkers;
architecture behavior of allocator_credit_counter_logic_pseudo_checkers is
begin
-- The combionational part
----------------------------------------------------------------
-- Checkers for the process handling the credit counters
-- North credit counter
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_in /= credit_counter_N_out) then
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out < 3 and credit_counter_N_in /= credit_counter_N_out + 1) then
err_credit_in_N_credit_counter_N_out_increment <= '1';
else
err_credit_in_N_credit_counter_N_out_increment <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out = 3 and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '1';
else
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out > 0 and credit_counter_N_in /= credit_counter_N_out - 1) then
err_grant_N_credit_counter_N_out_decrement <= '1';
else
err_grant_N_credit_counter_N_out_decrement <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out = 0 and credit_counter_N_in /= credit_counter_N_out) then
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '1';
else
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '0' and valid_N = '0' and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
-- East credit counter
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '1' and credit_counter_E_in /= credit_counter_E_out) then
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out < 3 and credit_counter_E_in /= credit_counter_E_out + 1) then
err_credit_in_E_credit_counter_E_out_increment <= '1';
else
err_credit_in_E_credit_counter_E_out_increment <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out = 3 and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '1';
else
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out > 0 and credit_counter_E_in /= credit_counter_E_out - 1) then
err_grant_E_credit_counter_E_out_decrement <= '1';
else
err_grant_E_credit_counter_E_out_decrement <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out = 0 and credit_counter_E_in /= credit_counter_E_out) then
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '1';
else
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '0' and valid_E = '0' and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
-- West credit counter
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '1' and credit_counter_W_in /= credit_counter_W_out) then
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out < 3 and credit_counter_W_in /= credit_counter_W_out + 1) then
err_credit_in_W_credit_counter_W_out_increment <= '1';
else
err_credit_in_W_credit_counter_W_out_increment <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out = 3) and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '1';
else
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if (valid_W = '1' and credit_in_W = '0' and credit_counter_W_out > 0 and credit_counter_W_in /= credit_counter_W_out - 1) then
err_grant_W_credit_counter_W_out_decrement <= '1';
else
err_grant_W_credit_counter_W_out_decrement <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( valid_W = '1' and credit_in_W = '0' and credit_counter_W_out = 0 and credit_counter_W_in /= credit_counter_W_out) then
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '1';
else
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '0' and valid_W = '0' and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
-- South credit counter
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '1' and credit_counter_S_in /= credit_counter_S_out) then
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '0' and credit_counter_S_out < 3 and credit_counter_S_in /= credit_counter_S_out + 1) then
err_credit_in_S_credit_counter_S_out_increment <= '1';
else
err_credit_in_S_credit_counter_S_out_increment <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if ( credit_in_S = '1' and valid_S = '0' and credit_counter_S_out = 3 and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '1';
else
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out > 0 and credit_counter_S_in /= credit_counter_S_out - 1) then
err_grant_S_credit_counter_S_out_decrement <= '1';
else
err_grant_S_credit_counter_S_out_decrement <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out = 0 and credit_counter_S_in /= credit_counter_S_out) then
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '1';
else
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '0' and valid_S = '0' and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
-- Local credit counter
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '1' and credit_counter_L_in /= credit_counter_L_out) then
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out < 3 and credit_counter_L_in /= credit_counter_L_out + 1) then
err_credit_in_L_credit_counter_L_out_increment <= '1';
else
err_credit_in_L_credit_counter_L_out_increment <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out = 3 and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '1';
else
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out > 0 and credit_counter_L_in /= credit_counter_L_out - 1) then
err_grant_L_credit_counter_L_out_decrement <= '1';
else
err_grant_L_credit_counter_L_out_decrement <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out = 0 and credit_counter_L_in /= credit_counter_L_out) then
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '1';
else
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '0' and valid_L = '0' and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
END;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid !
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0);
-- Checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic
);
end allocator_credit_counter_logic_pseudo_checkers;
architecture behavior of allocator_credit_counter_logic_pseudo_checkers is
begin
-- The combionational part
----------------------------------------------------------------
-- Checkers for the process handling the credit counters
-- North credit counter
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_in /= credit_counter_N_out) then
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out < 3 and credit_counter_N_in /= credit_counter_N_out + 1) then
err_credit_in_N_credit_counter_N_out_increment <= '1';
else
err_credit_in_N_credit_counter_N_out_increment <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out = 3 and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '1';
else
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out > 0 and credit_counter_N_in /= credit_counter_N_out - 1) then
err_grant_N_credit_counter_N_out_decrement <= '1';
else
err_grant_N_credit_counter_N_out_decrement <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out = 0 and credit_counter_N_in /= credit_counter_N_out) then
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '1';
else
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '0' and valid_N = '0' and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
-- East credit counter
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '1' and credit_counter_E_in /= credit_counter_E_out) then
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out < 3 and credit_counter_E_in /= credit_counter_E_out + 1) then
err_credit_in_E_credit_counter_E_out_increment <= '1';
else
err_credit_in_E_credit_counter_E_out_increment <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out = 3 and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '1';
else
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out > 0 and credit_counter_E_in /= credit_counter_E_out - 1) then
err_grant_E_credit_counter_E_out_decrement <= '1';
else
err_grant_E_credit_counter_E_out_decrement <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out = 0 and credit_counter_E_in /= credit_counter_E_out) then
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '1';
else
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '0' and valid_E = '0' and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
-- West credit counter
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '1' and credit_counter_W_in /= credit_counter_W_out) then
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out < 3 and credit_counter_W_in /= credit_counter_W_out + 1) then
err_credit_in_W_credit_counter_W_out_increment <= '1';
else
err_credit_in_W_credit_counter_W_out_increment <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out = 3) and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '1';
else
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if (valid_W = '1' and credit_in_W = '0' and credit_counter_W_out > 0 and credit_counter_W_in /= credit_counter_W_out - 1) then
err_grant_W_credit_counter_W_out_decrement <= '1';
else
err_grant_W_credit_counter_W_out_decrement <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( valid_W = '1' and credit_in_W = '0' and credit_counter_W_out = 0 and credit_counter_W_in /= credit_counter_W_out) then
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '1';
else
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '0' and valid_W = '0' and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
-- South credit counter
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '1' and credit_counter_S_in /= credit_counter_S_out) then
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '0' and credit_counter_S_out < 3 and credit_counter_S_in /= credit_counter_S_out + 1) then
err_credit_in_S_credit_counter_S_out_increment <= '1';
else
err_credit_in_S_credit_counter_S_out_increment <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if ( credit_in_S = '1' and valid_S = '0' and credit_counter_S_out = 3 and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '1';
else
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out > 0 and credit_counter_S_in /= credit_counter_S_out - 1) then
err_grant_S_credit_counter_S_out_decrement <= '1';
else
err_grant_S_credit_counter_S_out_decrement <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out = 0 and credit_counter_S_in /= credit_counter_S_out) then
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '1';
else
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '0' and valid_S = '0' and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
-- Local credit counter
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '1' and credit_counter_L_in /= credit_counter_L_out) then
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out < 3 and credit_counter_L_in /= credit_counter_L_out + 1) then
err_credit_in_L_credit_counter_L_out_increment <= '1';
else
err_credit_in_L_credit_counter_L_out_increment <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out = 3 and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '1';
else
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out > 0 and credit_counter_L_in /= credit_counter_L_out - 1) then
err_grant_L_credit_counter_L_out_decrement <= '1';
else
err_grant_L_credit_counter_L_out_decrement <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out = 0 and credit_counter_L_in /= credit_counter_L_out) then
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '1';
else
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '0' and valid_L = '0' and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
END;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid !
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0);
-- Checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic
);
end allocator_credit_counter_logic_pseudo_checkers;
architecture behavior of allocator_credit_counter_logic_pseudo_checkers is
begin
-- The combionational part
----------------------------------------------------------------
-- Checkers for the process handling the credit counters
-- North credit counter
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_in /= credit_counter_N_out) then
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out < 3 and credit_counter_N_in /= credit_counter_N_out + 1) then
err_credit_in_N_credit_counter_N_out_increment <= '1';
else
err_credit_in_N_credit_counter_N_out_increment <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out = 3 and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '1';
else
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out > 0 and credit_counter_N_in /= credit_counter_N_out - 1) then
err_grant_N_credit_counter_N_out_decrement <= '1';
else
err_grant_N_credit_counter_N_out_decrement <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out = 0 and credit_counter_N_in /= credit_counter_N_out) then
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '1';
else
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '0' and valid_N = '0' and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
-- East credit counter
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '1' and credit_counter_E_in /= credit_counter_E_out) then
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out < 3 and credit_counter_E_in /= credit_counter_E_out + 1) then
err_credit_in_E_credit_counter_E_out_increment <= '1';
else
err_credit_in_E_credit_counter_E_out_increment <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out = 3 and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '1';
else
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out > 0 and credit_counter_E_in /= credit_counter_E_out - 1) then
err_grant_E_credit_counter_E_out_decrement <= '1';
else
err_grant_E_credit_counter_E_out_decrement <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out = 0 and credit_counter_E_in /= credit_counter_E_out) then
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '1';
else
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '0' and valid_E = '0' and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
-- West credit counter
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '1' and credit_counter_W_in /= credit_counter_W_out) then
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out < 3 and credit_counter_W_in /= credit_counter_W_out + 1) then
err_credit_in_W_credit_counter_W_out_increment <= '1';
else
err_credit_in_W_credit_counter_W_out_increment <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out = 3) and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '1';
else
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if (valid_W = '1' and credit_in_W = '0' and credit_counter_W_out > 0 and credit_counter_W_in /= credit_counter_W_out - 1) then
err_grant_W_credit_counter_W_out_decrement <= '1';
else
err_grant_W_credit_counter_W_out_decrement <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( valid_W = '1' and credit_in_W = '0' and credit_counter_W_out = 0 and credit_counter_W_in /= credit_counter_W_out) then
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '1';
else
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '0' and valid_W = '0' and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
-- South credit counter
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '1' and credit_counter_S_in /= credit_counter_S_out) then
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '0' and credit_counter_S_out < 3 and credit_counter_S_in /= credit_counter_S_out + 1) then
err_credit_in_S_credit_counter_S_out_increment <= '1';
else
err_credit_in_S_credit_counter_S_out_increment <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if ( credit_in_S = '1' and valid_S = '0' and credit_counter_S_out = 3 and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '1';
else
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out > 0 and credit_counter_S_in /= credit_counter_S_out - 1) then
err_grant_S_credit_counter_S_out_decrement <= '1';
else
err_grant_S_credit_counter_S_out_decrement <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out = 0 and credit_counter_S_in /= credit_counter_S_out) then
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '1';
else
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '0' and valid_S = '0' and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
-- Local credit counter
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '1' and credit_counter_L_in /= credit_counter_L_out) then
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out < 3 and credit_counter_L_in /= credit_counter_L_out + 1) then
err_credit_in_L_credit_counter_L_out_increment <= '1';
else
err_credit_in_L_credit_counter_L_out_increment <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out = 3 and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '1';
else
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out > 0 and credit_counter_L_in /= credit_counter_L_out - 1) then
err_grant_L_credit_counter_L_out_decrement <= '1';
else
err_grant_L_credit_counter_L_out_decrement <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out = 0 and credit_counter_L_in /= credit_counter_L_out) then
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '1';
else
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '0' and valid_L = '0' and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
END;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nco_sine_lut_V_rom is
generic(
dwidth : integer := 16;
awidth : integer := 12;
mem_size : integer := 4096
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of nco_sine_lut_V_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "0000000000000000", 1 => "0000000000011001", 2 => "0000000000110010",
3 => "0000000001001011", 4 => "0000000001100100", 5 => "0000000001111101",
6 => "0000000010010110", 7 => "0000000010101111", 8 => "0000000011001001",
9 => "0000000011100010", 10 => "0000000011111011", 11 => "0000000100010100",
12 => "0000000100101101", 13 => "0000000101000110", 14 => "0000000101011111",
15 => "0000000101111000", 16 => "0000000110010010", 17 => "0000000110101011",
18 => "0000000111000100", 19 => "0000000111011101", 20 => "0000000111110110",
21 => "0000001000001111", 22 => "0000001000101000", 23 => "0000001001000001",
24 => "0000001001011011", 25 => "0000001001110100", 26 => "0000001010001101",
27 => "0000001010100110", 28 => "0000001010111111", 29 => "0000001011011000",
30 => "0000001011110001", 31 => "0000001100001010", 32 => "0000001100100011",
33 => "0000001100111101", 34 => "0000001101010110", 35 => "0000001101101111",
36 => "0000001110001000", 37 => "0000001110100001", 38 => "0000001110111010",
39 => "0000001111010011", 40 => "0000001111101100", 41 => "0000010000000101",
42 => "0000010000011110", 43 => "0000010000110111", 44 => "0000010001010001",
45 => "0000010001101010", 46 => "0000010010000011", 47 => "0000010010011100",
48 => "0000010010110101", 49 => "0000010011001110", 50 => "0000010011100111",
51 => "0000010100000000", 52 => "0000010100011001", 53 => "0000010100110010",
54 => "0000010101001011", 55 => "0000010101100100", 56 => "0000010101111101",
57 => "0000010110010110", 58 => "0000010110101111", 59 => "0000010111001000",
60 => "0000010111100001", 61 => "0000010111111010", 62 => "0000011000010011",
63 => "0000011000101100", 64 => "0000011001000101", 65 => "0000011001011110",
66 => "0000011001110111", 67 => "0000011010010000", 68 => "0000011010101001",
69 => "0000011011000010", 70 => "0000011011011011", 71 => "0000011011110100",
72 => "0000011100001101", 73 => "0000011100100110", 74 => "0000011100111111",
75 => "0000011101011000", 76 => "0000011101110001", 77 => "0000011110001010",
78 => "0000011110100011", 79 => "0000011110111100", 80 => "0000011111010101",
81 => "0000011111101110", 82 => "0000100000000111", 83 => "0000100000100000",
84 => "0000100000111001", 85 => "0000100001010010", 86 => "0000100001101011",
87 => "0000100010000100", 88 => "0000100010011100", 89 => "0000100010110101",
90 => "0000100011001110", 91 => "0000100011100111", 92 => "0000100100000000",
93 => "0000100100011001", 94 => "0000100100110010", 95 => "0000100101001011",
96 => "0000100101100100", 97 => "0000100101111100", 98 => "0000100110010101",
99 => "0000100110101110", 100 => "0000100111000111", 101 => "0000100111100000",
102 => "0000100111111001", 103 => "0000101000010001", 104 => "0000101000101010",
105 => "0000101001000011", 106 => "0000101001011100", 107 => "0000101001110101",
108 => "0000101010001101", 109 => "0000101010100110", 110 => "0000101010111111",
111 => "0000101011011000", 112 => "0000101011110001", 113 => "0000101100001001",
114 => "0000101100100010", 115 => "0000101100111011", 116 => "0000101101010100",
117 => "0000101101101100", 118 => "0000101110000101", 119 => "0000101110011110",
120 => "0000101110110110", 121 => "0000101111001111", 122 => "0000101111101000",
123 => "0000110000000001", 124 => "0000110000011001", 125 => "0000110000110010",
126 => "0000110001001011", 127 => "0000110001100011", 128 => "0000110001111100",
129 => "0000110010010101", 130 => "0000110010101101", 131 => "0000110011000110",
132 => "0000110011011110", 133 => "0000110011110111", 134 => "0000110100010000",
135 => "0000110100101000", 136 => "0000110101000001", 137 => "0000110101011001",
138 => "0000110101110010", 139 => "0000110110001011", 140 => "0000110110100011",
141 => "0000110110111100", 142 => "0000110111010100", 143 => "0000110111101101",
144 => "0000111000000101", 145 => "0000111000011110", 146 => "0000111000110110",
147 => "0000111001001111", 148 => "0000111001100111", 149 => "0000111010000000",
150 => "0000111010011000", 151 => "0000111010110001", 152 => "0000111011001001",
153 => "0000111011100010", 154 => "0000111011111010", 155 => "0000111100010010",
156 => "0000111100101011", 157 => "0000111101000011", 158 => "0000111101011100",
159 => "0000111101110100", 160 => "0000111110001100", 161 => "0000111110100101",
162 => "0000111110111101", 163 => "0000111111010110", 164 => "0000111111101110",
165 => "0001000000000110", 166 => "0001000000011111", 167 => "0001000000110111",
168 => "0001000001001111", 169 => "0001000001101000", 170 => "0001000010000000",
171 => "0001000010011000", 172 => "0001000010110000", 173 => "0001000011001001",
174 => "0001000011100001", 175 => "0001000011111001", 176 => "0001000100010001",
177 => "0001000100101010", 178 => "0001000101000010", 179 => "0001000101011010",
180 => "0001000101110010", 181 => "0001000110001010", 182 => "0001000110100010",
183 => "0001000110111011", 184 => "0001000111010011", 185 => "0001000111101011",
186 => "0001001000000011", 187 => "0001001000011011", 188 => "0001001000110011",
189 => "0001001001001011", 190 => "0001001001100011", 191 => "0001001001111011",
192 => "0001001010010100", 193 => "0001001010101100", 194 => "0001001011000100",
195 => "0001001011011100", 196 => "0001001011110100", 197 => "0001001100001100",
198 => "0001001100100100", 199 => "0001001100111100", 200 => "0001001101010100",
201 => "0001001101101100", 202 => "0001001110000011", 203 => "0001001110011011",
204 => "0001001110110011", 205 => "0001001111001011", 206 => "0001001111100011",
207 => "0001001111111011", 208 => "0001010000010011", 209 => "0001010000101011",
210 => "0001010001000011", 211 => "0001010001011010", 212 => "0001010001110010",
213 => "0001010010001010", 214 => "0001010010100010", 215 => "0001010010111010",
216 => "0001010011010001", 217 => "0001010011101001", 218 => "0001010100000001",
219 => "0001010100011001", 220 => "0001010100110000", 221 => "0001010101001000",
222 => "0001010101100000", 223 => "0001010101110111", 224 => "0001010110001111",
225 => "0001010110100111", 226 => "0001010110111110", 227 => "0001010111010110",
228 => "0001010111101110", 229 => "0001011000000101", 230 => "0001011000011101",
231 => "0001011000110100", 232 => "0001011001001100", 233 => "0001011001100100",
234 => "0001011001111011", 235 => "0001011010010011", 236 => "0001011010101010",
237 => "0001011011000010", 238 => "0001011011011001", 239 => "0001011011110001",
240 => "0001011100001000", 241 => "0001011100011111", 242 => "0001011100110111",
243 => "0001011101001110", 244 => "0001011101100110", 245 => "0001011101111101",
246 => "0001011110010100", 247 => "0001011110101100", 248 => "0001011111000011",
249 => "0001011111011010", 250 => "0001011111110010", 251 => "0001100000001001",
252 => "0001100000100000", 253 => "0001100000111000", 254 => "0001100001001111",
255 => "0001100001100110", 256 => "0001100001111101", 257 => "0001100010010101",
258 => "0001100010101100", 259 => "0001100011000011", 260 => "0001100011011010",
261 => "0001100011110001", 262 => "0001100100001000", 263 => "0001100100100000",
264 => "0001100100110111", 265 => "0001100101001110", 266 => "0001100101100101",
267 => "0001100101111100", 268 => "0001100110010011", 269 => "0001100110101010",
270 => "0001100111000001", 271 => "0001100111011000", 272 => "0001100111101111",
273 => "0001101000000110", 274 => "0001101000011101", 275 => "0001101000110100",
276 => "0001101001001011", 277 => "0001101001100010", 278 => "0001101001111001",
279 => "0001101010001111", 280 => "0001101010100110", 281 => "0001101010111101",
282 => "0001101011010100", 283 => "0001101011101011", 284 => "0001101100000010",
285 => "0001101100011000", 286 => "0001101100101111", 287 => "0001101101000110",
288 => "0001101101011101", 289 => "0001101101110011", 290 => "0001101110001010",
291 => "0001101110100001", 292 => "0001101110110111", 293 => "0001101111001110",
294 => "0001101111100101", 295 => "0001101111111011", 296 => "0001110000010010",
297 => "0001110000101000", 298 => "0001110000111111", 299 => "0001110001010101",
300 => "0001110001101100", 301 => "0001110010000011", 302 => "0001110010011001",
303 => "0001110010101111", 304 => "0001110011000110", 305 => "0001110011011100",
306 => "0001110011110011", 307 => "0001110100001001", 308 => "0001110100100000",
309 => "0001110100110110", 310 => "0001110101001100", 311 => "0001110101100011",
312 => "0001110101111001", 313 => "0001110110001111", 314 => "0001110110100110",
315 => "0001110110111100", 316 => "0001110111010010", 317 => "0001110111101000",
318 => "0001110111111110", 319 => "0001111000010101", 320 => "0001111000101011",
321 => "0001111001000001", 322 => "0001111001010111", 323 => "0001111001101101",
324 => "0001111010000011", 325 => "0001111010011001", 326 => "0001111010110000",
327 => "0001111011000110", 328 => "0001111011011100", 329 => "0001111011110010",
330 => "0001111100001000", 331 => "0001111100011110", 332 => "0001111100110100",
333 => "0001111101001001", 334 => "0001111101011111", 335 => "0001111101110101",
336 => "0001111110001011", 337 => "0001111110100001", 338 => "0001111110110111",
339 => "0001111111001101", 340 => "0001111111100010", 341 => "0001111111111000",
342 => "0010000000001110", 343 => "0010000000100100", 344 => "0010000000111001",
345 => "0010000001001111", 346 => "0010000001100101", 347 => "0010000001111011",
348 => "0010000010010000", 349 => "0010000010100110", 350 => "0010000010111011",
351 => "0010000011010001", 352 => "0010000011100111", 353 => "0010000011111100",
354 => "0010000100010010", 355 => "0010000100100111", 356 => "0010000100111101",
357 => "0010000101010010", 358 => "0010000101101000", 359 => "0010000101111101",
360 => "0010000110010010", 361 => "0010000110101000", 362 => "0010000110111101",
363 => "0010000111010010", 364 => "0010000111101000", 365 => "0010000111111101",
366 => "0010001000010010", 367 => "0010001000101000", 368 => "0010001000111101",
369 => "0010001001010010", 370 => "0010001001100111", 371 => "0010001001111101",
372 => "0010001010010010", 373 => "0010001010100111", 374 => "0010001010111100",
375 => "0010001011010001", 376 => "0010001011100110", 377 => "0010001011111011",
378 => "0010001100010000", 379 => "0010001100100101", 380 => "0010001100111010",
381 => "0010001101001111", 382 => "0010001101100100", 383 => "0010001101111001",
384 => "0010001110001110", 385 => "0010001110100011", 386 => "0010001110111000",
387 => "0010001111001101", 388 => "0010001111100001", 389 => "0010001111110110",
390 => "0010010000001011", 391 => "0010010000100000", 392 => "0010010000110100",
393 => "0010010001001001", 394 => "0010010001011110", 395 => "0010010001110011",
396 => "0010010010000111", 397 => "0010010010011100", 398 => "0010010010110000",
399 => "0010010011000101", 400 => "0010010011011010", 401 => "0010010011101110",
402 => "0010010100000011", 403 => "0010010100010111", 404 => "0010010100101100",
405 => "0010010101000000", 406 => "0010010101010100", 407 => "0010010101101001",
408 => "0010010101111101", 409 => "0010010110010010", 410 => "0010010110100110",
411 => "0010010110111010", 412 => "0010010111001111", 413 => "0010010111100011",
414 => "0010010111110111", 415 => "0010011000001011", 416 => "0010011000011111",
417 => "0010011000110100", 418 => "0010011001001000", 419 => "0010011001011100",
420 => "0010011001110000", 421 => "0010011010000100", 422 => "0010011010011000",
423 => "0010011010101100", 424 => "0010011011000000", 425 => "0010011011010100",
426 => "0010011011101000", 427 => "0010011011111100", 428 => "0010011100010000",
429 => "0010011100100100", 430 => "0010011100111000", 431 => "0010011101001100",
432 => "0010011101011111", 433 => "0010011101110011", 434 => "0010011110000111",
435 => "0010011110011011", 436 => "0010011110101111", 437 => "0010011111000010",
438 => "0010011111010110", 439 => "0010011111101010", 440 => "0010011111111101",
441 => "0010100000010001", 442 => "0010100000100100", 443 => "0010100000111000",
444 => "0010100001001011", 445 => "0010100001011111", 446 => "0010100001110010",
447 => "0010100010000110", 448 => "0010100010011001", 449 => "0010100010101101",
450 => "0010100011000000", 451 => "0010100011010100", 452 => "0010100011100111",
453 => "0010100011111010", 454 => "0010100100001110", 455 => "0010100100100001",
456 => "0010100100110100", 457 => "0010100101000111", 458 => "0010100101011010",
459 => "0010100101101110", 460 => "0010100110000001", 461 => "0010100110010100",
462 => "0010100110100111", 463 => "0010100110111010", 464 => "0010100111001101",
465 => "0010100111100000", 466 => "0010100111110011", 467 => "0010101000000110",
468 => "0010101000011001", 469 => "0010101000101100", 470 => "0010101000111111",
471 => "0010101001010010", 472 => "0010101001100101", 473 => "0010101001110111",
474 => "0010101010001010", 475 => "0010101010011101", 476 => "0010101010110000",
477 => "0010101011000010", 478 => "0010101011010101", 479 => "0010101011101000",
480 => "0010101011111010", 481 => "0010101100001101", 482 => "0010101100100000",
483 => "0010101100110010", 484 => "0010101101000101", 485 => "0010101101010111",
486 => "0010101101101010", 487 => "0010101101111100", 488 => "0010101110001110",
489 => "0010101110100001", 490 => "0010101110110011", 491 => "0010101111000110",
492 => "0010101111011000", 493 => "0010101111101010", 494 => "0010101111111100",
495 => "0010110000001111", 496 => "0010110000100001", 497 => "0010110000110011",
498 => "0010110001000101", 499 => "0010110001010111", 500 => "0010110001101010",
501 => "0010110001111100", 502 => "0010110010001110", 503 => "0010110010100000",
504 => "0010110010110010", 505 => "0010110011000100", 506 => "0010110011010110",
507 => "0010110011101000", 508 => "0010110011111001", 509 => "0010110100001011",
510 => "0010110100011101", 511 => "0010110100101111", 512 => "0010110101000001",
513 => "0010110101010010", 514 => "0010110101100100", 515 => "0010110101110110",
516 => "0010110110001000", 517 => "0010110110011001", 518 => "0010110110101011",
519 => "0010110110111100", 520 => "0010110111001110", 521 => "0010110111100000",
522 => "0010110111110001", 523 => "0010111000000011", 524 => "0010111000010100",
525 => "0010111000100101", 526 => "0010111000110111", 527 => "0010111001001000",
528 => "0010111001011010", 529 => "0010111001101011", 530 => "0010111001111100",
531 => "0010111010001101", 532 => "0010111010011111", 533 => "0010111010110000",
534 => "0010111011000001", 535 => "0010111011010010", 536 => "0010111011100011",
537 => "0010111011110100", 538 => "0010111100000101", 539 => "0010111100010110",
540 => "0010111100101000", 541 => "0010111100111000", 542 => "0010111101001001",
543 => "0010111101011010", 544 => "0010111101101011", 545 => "0010111101111100",
546 => "0010111110001101", 547 => "0010111110011110", 548 => "0010111110101111",
549 => "0010111110111111", 550 => "0010111111010000", 551 => "0010111111100001",
552 => "0010111111110001", 553 => "0011000000000010", 554 => "0011000000010011",
555 => "0011000000100011", 556 => "0011000000110100", 557 => "0011000001000100",
558 => "0011000001010101", 559 => "0011000001100101", 560 => "0011000001110110",
561 => "0011000010000110", 562 => "0011000010010110", 563 => "0011000010100111",
564 => "0011000010110111", 565 => "0011000011000111", 566 => "0011000011011000",
567 => "0011000011101000", 568 => "0011000011111000", 569 => "0011000100001000",
570 => "0011000100011000", 571 => "0011000100101000", 572 => "0011000100111000",
573 => "0011000101001001", 574 => "0011000101011001", 575 => "0011000101101001",
576 => "0011000101111001", 577 => "0011000110001000", 578 => "0011000110011000",
579 => "0011000110101000", 580 => "0011000110111000", 581 => "0011000111001000",
582 => "0011000111011000", 583 => "0011000111100111", 584 => "0011000111110111",
585 => "0011001000000111", 586 => "0011001000010110", 587 => "0011001000100110",
588 => "0011001000110110", 589 => "0011001001000101", 590 => "0011001001010101",
591 => "0011001001100100", 592 => "0011001001110100", 593 => "0011001010000011",
594 => "0011001010010011", 595 => "0011001010100010", 596 => "0011001010110001",
597 => "0011001011000001", 598 => "0011001011010000", 599 => "0011001011011111",
600 => "0011001011101110", 601 => "0011001011111110", 602 => "0011001100001101",
603 => "0011001100011100", 604 => "0011001100101011", 605 => "0011001100111010",
606 => "0011001101001001", 607 => "0011001101011000", 608 => "0011001101100111",
609 => "0011001101110110", 610 => "0011001110000101", 611 => "0011001110010100",
612 => "0011001110100011", 613 => "0011001110110010", 614 => "0011001111000001",
615 => "0011001111001111", 616 => "0011001111011110", 617 => "0011001111101101",
618 => "0011001111111011", 619 => "0011010000001010", 620 => "0011010000011001",
621 => "0011010000100111", 622 => "0011010000110110", 623 => "0011010001000100",
624 => "0011010001010011", 625 => "0011010001100001", 626 => "0011010001110000",
627 => "0011010001111110", 628 => "0011010010001100", 629 => "0011010010011011",
630 => "0011010010101001", 631 => "0011010010110111", 632 => "0011010011000110",
633 => "0011010011010100", 634 => "0011010011100010", 635 => "0011010011110000",
636 => "0011010011111110", 637 => "0011010100001100", 638 => "0011010100011010",
639 => "0011010100101000", 640 => "0011010100110110", 641 => "0011010101000100",
642 => "0011010101010010", 643 => "0011010101100000", 644 => "0011010101101110",
645 => "0011010101111100", 646 => "0011010110001001", 647 => "0011010110010111",
648 => "0011010110100101", 649 => "0011010110110011", 650 => "0011010111000000",
651 => "0011010111001110", 652 => "0011010111011100", 653 => "0011010111101001",
654 => "0011010111110111", 655 => "0011011000000100", 656 => "0011011000010010",
657 => "0011011000011111", 658 => "0011011000101100", 659 => "0011011000111010",
660 => "0011011001000111", 661 => "0011011001010100", 662 => "0011011001100010",
663 => "0011011001101111", 664 => "0011011001111100", 665 => "0011011010001001",
666 => "0011011010010110", 667 => "0011011010100100", 668 => "0011011010110001",
669 => "0011011010111110", 670 => "0011011011001011", 671 => "0011011011011000",
672 => "0011011011100101", 673 => "0011011011110001", 674 => "0011011011111110",
675 => "0011011100001011", 676 => "0011011100011000", 677 => "0011011100100101",
678 => "0011011100110001", 679 => "0011011100111110", 680 => "0011011101001011",
681 => "0011011101010111", 682 => "0011011101100100", 683 => "0011011101110001",
684 => "0011011101111101", 685 => "0011011110001010", 686 => "0011011110010110",
687 => "0011011110100011", 688 => "0011011110101111", 689 => "0011011110111011",
690 => "0011011111001000", 691 => "0011011111010100", 692 => "0011011111100000",
693 => "0011011111101101", 694 => "0011011111111001", 695 => "0011100000000101",
696 => "0011100000010001", 697 => "0011100000011101", 698 => "0011100000101001",
699 => "0011100000110101", 700 => "0011100001000001", 701 => "0011100001001101",
702 => "0011100001011001", 703 => "0011100001100101", 704 => "0011100001110001",
705 => "0011100001111101", 706 => "0011100010001001", 707 => "0011100010010100",
708 => "0011100010100000", 709 => "0011100010101100", 710 => "0011100010110111",
711 => "0011100011000011", 712 => "0011100011001111", 713 => "0011100011011010",
714 => "0011100011100110", 715 => "0011100011110001", 716 => "0011100011111101",
717 => "0011100100001000", 718 => "0011100100010011", 719 => "0011100100011111",
720 => "0011100100101010", 721 => "0011100100110101", 722 => "0011100101000001",
723 => "0011100101001100", 724 => "0011100101010111", 725 => "0011100101100010",
726 => "0011100101101101", 727 => "0011100101111000", 728 => "0011100110000011",
729 => "0011100110001110", 730 => "0011100110011001", 731 => "0011100110100100",
732 => "0011100110101111", 733 => "0011100110111010", 734 => "0011100111000101",
735 => "0011100111010000", 736 => "0011100111011010", 737 => "0011100111100101",
738 => "0011100111110000", 739 => "0011100111111011", 740 => "0011101000000101",
741 => "0011101000010000", 742 => "0011101000011010", 743 => "0011101000100101",
744 => "0011101000101111", 745 => "0011101000111010", 746 => "0011101001000100",
747 => "0011101001001111", 748 => "0011101001011001", 749 => "0011101001100011",
750 => "0011101001101101", 751 => "0011101001111000", 752 => "0011101010000010",
753 => "0011101010001100", 754 => "0011101010010110", 755 => "0011101010100000",
756 => "0011101010101010", 757 => "0011101010110100", 758 => "0011101010111110",
759 => "0011101011001000", 760 => "0011101011010010", 761 => "0011101011011100",
762 => "0011101011100110", 763 => "0011101011110000", 764 => "0011101011111010",
765 => "0011101100000011", 766 => "0011101100001101", 767 => "0011101100010111",
768 => "0011101100100000", 769 => "0011101100101010", 770 => "0011101100110100",
771 => "0011101100111101", 772 => "0011101101000111", 773 => "0011101101010000",
774 => "0011101101011001", 775 => "0011101101100011", 776 => "0011101101101100",
777 => "0011101101110101", 778 => "0011101101111111", 779 => "0011101110001000",
780 => "0011101110010001", 781 => "0011101110011010", 782 => "0011101110100011",
783 => "0011101110101101", 784 => "0011101110110110", 785 => "0011101110111111",
786 => "0011101111001000", 787 => "0011101111010001", 788 => "0011101111011010",
789 => "0011101111100010", 790 => "0011101111101011", 791 => "0011101111110100",
792 => "0011101111111101", 793 => "0011110000000110", 794 => "0011110000001110",
795 => "0011110000010111", 796 => "0011110000100000", 797 => "0011110000101000",
798 => "0011110000110001", 799 => "0011110000111001", 800 => "0011110001000010",
801 => "0011110001001010", 802 => "0011110001010011", 803 => "0011110001011011",
804 => "0011110001100011", 805 => "0011110001101100", 806 => "0011110001110100",
807 => "0011110001111100", 808 => "0011110010000100", 809 => "0011110010001100",
810 => "0011110010010101", 811 => "0011110010011101", 812 => "0011110010100101",
813 => "0011110010101101", 814 => "0011110010110101", 815 => "0011110010111101",
816 => "0011110011000101", 817 => "0011110011001100", 818 => "0011110011010100",
819 => "0011110011011100", 820 => "0011110011100100", 821 => "0011110011101100",
822 => "0011110011110011", 823 => "0011110011111011", 824 => "0011110100000010",
825 => "0011110100001010", 826 => "0011110100010010", 827 => "0011110100011001",
828 => "0011110100100001", 829 => "0011110100101000", 830 => "0011110100101111",
831 => "0011110100110111", 832 => "0011110100111110", 833 => "0011110101000101",
834 => "0011110101001101", 835 => "0011110101010100", 836 => "0011110101011011",
837 => "0011110101100010", 838 => "0011110101101001", 839 => "0011110101110000",
840 => "0011110101110111", 841 => "0011110101111110", 842 => "0011110110000101",
843 => "0011110110001100", 844 => "0011110110010011", 845 => "0011110110011010",
846 => "0011110110100001", 847 => "0011110110100111", 848 => "0011110110101110",
849 => "0011110110110101", 850 => "0011110110111011", 851 => "0011110111000010",
852 => "0011110111001001", 853 => "0011110111001111", 854 => "0011110111010110",
855 => "0011110111011100", 856 => "0011110111100010", 857 => "0011110111101001",
858 => "0011110111101111", 859 => "0011110111110101", 860 => "0011110111111100",
861 => "0011111000000010", 862 => "0011111000001000", 863 => "0011111000001110",
864 => "0011111000010100", 865 => "0011111000011011", 866 => "0011111000100001",
867 => "0011111000100111", 868 => "0011111000101101", 869 => "0011111000110011",
870 => "0011111000111000", 871 => "0011111000111110", 872 => "0011111001000100",
873 => "0011111001001010", 874 => "0011111001010000", 875 => "0011111001010101",
876 => "0011111001011011", 877 => "0011111001100001", 878 => "0011111001100110",
879 => "0011111001101100", 880 => "0011111001110001", 881 => "0011111001110111",
882 => "0011111001111100", 883 => "0011111010000010", 884 => "0011111010000111",
885 => "0011111010001100", 886 => "0011111010010010", 887 => "0011111010010111",
888 => "0011111010011100", 889 => "0011111010100001", 890 => "0011111010100111",
891 => "0011111010101100", 892 => "0011111010110001", 893 => "0011111010110110",
894 => "0011111010111011", 895 => "0011111011000000", 896 => "0011111011000101",
897 => "0011111011001010", 898 => "0011111011001110", 899 => "0011111011010011",
900 => "0011111011011000", 901 => "0011111011011101", 902 => "0011111011100001",
903 => "0011111011100110", 904 => "0011111011101011", 905 => "0011111011101111",
906 => "0011111011110100", 907 => "0011111011111000", 908 => "0011111011111101",
909 => "0011111100000001", 910 => "0011111100000110", 911 => "0011111100001010",
912 => "0011111100001110", 913 => "0011111100010011", 914 => "0011111100010111",
915 => "0011111100011011", 916 => "0011111100011111", 917 => "0011111100100011",
918 => "0011111100100111", 919 => "0011111100101011", 920 => "0011111100101111",
921 => "0011111100110011", 922 => "0011111100110111", 923 => "0011111100111011",
924 => "0011111100111111", 925 => "0011111101000011", 926 => "0011111101000111",
927 => "0011111101001010", 928 => "0011111101001110", 929 => "0011111101010010",
930 => "0011111101010101", 931 => "0011111101011001", 932 => "0011111101011101",
933 => "0011111101100000", 934 => "0011111101100100", 935 => "0011111101100111",
936 => "0011111101101010", 937 => "0011111101101110", 938 => "0011111101110001",
939 => "0011111101110100", 940 => "0011111101111000", 941 => "0011111101111011",
942 => "0011111101111110", 943 => "0011111110000001", 944 => "0011111110000100",
945 => "0011111110000111", 946 => "0011111110001010", 947 => "0011111110001101",
948 => "0011111110010000", 949 => "0011111110010011", 950 => "0011111110010110",
951 => "0011111110011001", 952 => "0011111110011100", 953 => "0011111110011110",
954 => "0011111110100001", 955 => "0011111110100100", 956 => "0011111110100110",
957 => "0011111110101001", 958 => "0011111110101100", 959 => "0011111110101110",
960 => "0011111110110001", 961 => "0011111110110011", 962 => "0011111110110101",
963 => "0011111110111000", 964 => "0011111110111010", 965 => "0011111110111100",
966 => "0011111110111111", 967 => "0011111111000001", 968 => "0011111111000011",
969 => "0011111111000101", 970 => "0011111111000111", 971 => "0011111111001001",
972 => "0011111111001011", 973 => "0011111111001101", 974 => "0011111111001111",
975 => "0011111111010001", 976 => "0011111111010011", 977 => "0011111111010101",
978 => "0011111111010111", 979 => "0011111111011000", 980 => "0011111111011010",
981 => "0011111111011100", 982 => "0011111111011110", 983 => "0011111111011111",
984 => "0011111111100001", 985 => "0011111111100010", 986 => "0011111111100100",
987 => "0011111111100101", 988 => "0011111111100111", 989 => "0011111111101000",
990 => "0011111111101001", 991 => "0011111111101011", 992 => "0011111111101100",
993 => "0011111111101101", 994 => "0011111111101110", 995 => "0011111111101111",
996 => "0011111111110000", 997 => "0011111111110001", 998 => "0011111111110010",
999 => "0011111111110011", 1000 => "0011111111110100", 1001 => "0011111111110101",
1002 => "0011111111110110", 1003 => "0011111111110111", 1004 => "0011111111111000",
1005 to 1006=> "0011111111111001", 1007 => "0011111111111010", 1008 to 1009=> "0011111111111011",
1010 to 1011=> "0011111111111100", 1012 to 1013=> "0011111111111101", 1014 to 1016=> "0011111111111110",
1017 to 1023=> "0011111111111111", 1024 => "0100000000000000", 1025 to 1031=> "0011111111111111",
1032 to 1034=> "0011111111111110", 1035 to 1036=> "0011111111111101", 1037 to 1038=> "0011111111111100",
1039 to 1040=> "0011111111111011", 1041 => "0011111111111010", 1042 to 1043=> "0011111111111001",
1044 => "0011111111111000", 1045 => "0011111111110111", 1046 => "0011111111110110",
1047 => "0011111111110101", 1048 => "0011111111110100", 1049 => "0011111111110011",
1050 => "0011111111110010", 1051 => "0011111111110001", 1052 => "0011111111110000",
1053 => "0011111111101111", 1054 => "0011111111101110", 1055 => "0011111111101101",
1056 => "0011111111101100", 1057 => "0011111111101011", 1058 => "0011111111101001",
1059 => "0011111111101000", 1060 => "0011111111100111", 1061 => "0011111111100101",
1062 => "0011111111100100", 1063 => "0011111111100010", 1064 => "0011111111100001",
1065 => "0011111111011111", 1066 => "0011111111011110", 1067 => "0011111111011100",
1068 => "0011111111011010", 1069 => "0011111111011000", 1070 => "0011111111010111",
1071 => "0011111111010101", 1072 => "0011111111010011", 1073 => "0011111111010001",
1074 => "0011111111001111", 1075 => "0011111111001101", 1076 => "0011111111001011",
1077 => "0011111111001001", 1078 => "0011111111000111", 1079 => "0011111111000101",
1080 => "0011111111000011", 1081 => "0011111111000001", 1082 => "0011111110111111",
1083 => "0011111110111100", 1084 => "0011111110111010", 1085 => "0011111110111000",
1086 => "0011111110110101", 1087 => "0011111110110011", 1088 => "0011111110110001",
1089 => "0011111110101110", 1090 => "0011111110101100", 1091 => "0011111110101001",
1092 => "0011111110100110", 1093 => "0011111110100100", 1094 => "0011111110100001",
1095 => "0011111110011110", 1096 => "0011111110011100", 1097 => "0011111110011001",
1098 => "0011111110010110", 1099 => "0011111110010011", 1100 => "0011111110010000",
1101 => "0011111110001101", 1102 => "0011111110001010", 1103 => "0011111110000111",
1104 => "0011111110000100", 1105 => "0011111110000001", 1106 => "0011111101111110",
1107 => "0011111101111011", 1108 => "0011111101111000", 1109 => "0011111101110100",
1110 => "0011111101110001", 1111 => "0011111101101110", 1112 => "0011111101101010",
1113 => "0011111101100111", 1114 => "0011111101100100", 1115 => "0011111101100000",
1116 => "0011111101011101", 1117 => "0011111101011001", 1118 => "0011111101010101",
1119 => "0011111101010010", 1120 => "0011111101001110", 1121 => "0011111101001010",
1122 => "0011111101000111", 1123 => "0011111101000011", 1124 => "0011111100111111",
1125 => "0011111100111011", 1126 => "0011111100110111", 1127 => "0011111100110011",
1128 => "0011111100101111", 1129 => "0011111100101011", 1130 => "0011111100100111",
1131 => "0011111100100011", 1132 => "0011111100011111", 1133 => "0011111100011011",
1134 => "0011111100010111", 1135 => "0011111100010011", 1136 => "0011111100001110",
1137 => "0011111100001010", 1138 => "0011111100000110", 1139 => "0011111100000001",
1140 => "0011111011111101", 1141 => "0011111011111000", 1142 => "0011111011110100",
1143 => "0011111011101111", 1144 => "0011111011101011", 1145 => "0011111011100110",
1146 => "0011111011100001", 1147 => "0011111011011101", 1148 => "0011111011011000",
1149 => "0011111011010011", 1150 => "0011111011001110", 1151 => "0011111011001010",
1152 => "0011111011000101", 1153 => "0011111011000000", 1154 => "0011111010111011",
1155 => "0011111010110110", 1156 => "0011111010110001", 1157 => "0011111010101100",
1158 => "0011111010100111", 1159 => "0011111010100001", 1160 => "0011111010011100",
1161 => "0011111010010111", 1162 => "0011111010010010", 1163 => "0011111010001100",
1164 => "0011111010000111", 1165 => "0011111010000010", 1166 => "0011111001111100",
1167 => "0011111001110111", 1168 => "0011111001110001", 1169 => "0011111001101100",
1170 => "0011111001100110", 1171 => "0011111001100001", 1172 => "0011111001011011",
1173 => "0011111001010101", 1174 => "0011111001010000", 1175 => "0011111001001010",
1176 => "0011111001000100", 1177 => "0011111000111110", 1178 => "0011111000111000",
1179 => "0011111000110011", 1180 => "0011111000101101", 1181 => "0011111000100111",
1182 => "0011111000100001", 1183 => "0011111000011011", 1184 => "0011111000010100",
1185 => "0011111000001110", 1186 => "0011111000001000", 1187 => "0011111000000010",
1188 => "0011110111111100", 1189 => "0011110111110101", 1190 => "0011110111101111",
1191 => "0011110111101001", 1192 => "0011110111100010", 1193 => "0011110111011100",
1194 => "0011110111010110", 1195 => "0011110111001111", 1196 => "0011110111001001",
1197 => "0011110111000010", 1198 => "0011110110111011", 1199 => "0011110110110101",
1200 => "0011110110101110", 1201 => "0011110110100111", 1202 => "0011110110100001",
1203 => "0011110110011010", 1204 => "0011110110010011", 1205 => "0011110110001100",
1206 => "0011110110000101", 1207 => "0011110101111110", 1208 => "0011110101110111",
1209 => "0011110101110000", 1210 => "0011110101101001", 1211 => "0011110101100010",
1212 => "0011110101011011", 1213 => "0011110101010100", 1214 => "0011110101001101",
1215 => "0011110101000101", 1216 => "0011110100111110", 1217 => "0011110100110111",
1218 => "0011110100101111", 1219 => "0011110100101000", 1220 => "0011110100100001",
1221 => "0011110100011001", 1222 => "0011110100010010", 1223 => "0011110100001010",
1224 => "0011110100000010", 1225 => "0011110011111011", 1226 => "0011110011110011",
1227 => "0011110011101100", 1228 => "0011110011100100", 1229 => "0011110011011100",
1230 => "0011110011010100", 1231 => "0011110011001100", 1232 => "0011110011000101",
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1944 => "0000101000101010", 1945 => "0000101000010001", 1946 => "0000100111111001",
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1950 => "0000100110010101", 1951 => "0000100101111100", 1952 => "0000100101100100",
1953 => "0000100101001011", 1954 => "0000100100110010", 1955 => "0000100100011001",
1956 => "0000100100000000", 1957 => "0000100011100111", 1958 => "0000100011001110",
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2760 => "1100011100110000", 2761 => "1100011100100101", 2762 => "1100011100011001",
2763 => "1100011100001110", 2764 => "1100011100000010", 2765 => "1100011011110111",
2766 => "1100011011101100", 2767 => "1100011011100000", 2768 => "1100011011010101",
2769 => "1100011011001010", 2770 => "1100011010111110", 2771 => "1100011010110011",
2772 => "1100011010101000", 2773 => "1100011010011101", 2774 => "1100011010010010",
2775 => "1100011010000111", 2776 => "1100011001111100", 2777 => "1100011001110001",
2778 => "1100011001100110", 2779 => "1100011001011011", 2780 => "1100011001010000",
2781 => "1100011001000101", 2782 => "1100011000111010", 2783 => "1100011000101111",
2784 => "1100011000100101", 2785 => "1100011000011010", 2786 => "1100011000001111",
2787 => "1100011000000100", 2788 => "1100010111111010", 2789 => "1100010111101111",
2790 => "1100010111100101", 2791 => "1100010111011010", 2792 => "1100010111010000",
2793 => "1100010111000101", 2794 => "1100010110111011", 2795 => "1100010110110000",
2796 => "1100010110100110", 2797 => "1100010110011100", 2798 => "1100010110010010",
2799 => "1100010110000111", 2800 => "1100010101111101", 2801 => "1100010101110011",
2802 => "1100010101101001", 2803 => "1100010101011111", 2804 => "1100010101010101",
2805 => "1100010101001011", 2806 => "1100010101000001", 2807 => "1100010100110111",
2808 => "1100010100101101", 2809 => "1100010100100011", 2810 => "1100010100011001",
2811 => "1100010100001111", 2812 => "1100010100000101", 2813 => "1100010011111100",
2814 => "1100010011110010", 2815 => "1100010011101000", 2816 => "1100010011011111",
2817 => "1100010011010101", 2818 => "1100010011001011", 2819 => "1100010011000010",
2820 => "1100010010111000", 2821 => "1100010010101111", 2822 => "1100010010100110",
2823 => "1100010010011100", 2824 => "1100010010010011", 2825 => "1100010010001010",
2826 => "1100010010000000", 2827 => "1100010001110111", 2828 => "1100010001101110",
2829 => "1100010001100101", 2830 => "1100010001011100", 2831 => "1100010001010010",
2832 => "1100010001001001", 2833 => "1100010001000000", 2834 => "1100010000110111",
2835 => "1100010000101110", 2836 => "1100010000100101", 2837 => "1100010000011101",
2838 => "1100010000010100", 2839 => "1100010000001011", 2840 => "1100010000000010",
2841 => "1100001111111001", 2842 => "1100001111110001", 2843 => "1100001111101000",
2844 => "1100001111011111", 2845 => "1100001111010111", 2846 => "1100001111001110",
2847 => "1100001111000110", 2848 => "1100001110111101", 2849 => "1100001110110101",
2850 => "1100001110101100", 2851 => "1100001110100100", 2852 => "1100001110011100",
2853 => "1100001110010011", 2854 => "1100001110001011", 2855 => "1100001110000011",
2856 => "1100001101111011", 2857 => "1100001101110011", 2858 => "1100001101101010",
2859 => "1100001101100010", 2860 => "1100001101011010", 2861 => "1100001101010010",
2862 => "1100001101001010", 2863 => "1100001101000010", 2864 => "1100001100111010",
2865 => "1100001100110011", 2866 => "1100001100101011", 2867 => "1100001100100011",
2868 => "1100001100011011", 2869 => "1100001100010011", 2870 => "1100001100001100",
2871 => "1100001100000100", 2872 => "1100001011111101", 2873 => "1100001011110101",
2874 => "1100001011101101", 2875 => "1100001011100110", 2876 => "1100001011011110",
2877 => "1100001011010111", 2878 => "1100001011010000", 2879 => "1100001011001000",
2880 => "1100001011000001", 2881 => "1100001010111010", 2882 => "1100001010110010",
2883 => "1100001010101011", 2884 => "1100001010100100", 2885 => "1100001010011101",
2886 => "1100001010010110", 2887 => "1100001010001111", 2888 => "1100001010001000",
2889 => "1100001010000001", 2890 => "1100001001111010", 2891 => "1100001001110011",
2892 => "1100001001101100", 2893 => "1100001001100101", 2894 => "1100001001011110",
2895 => "1100001001011000", 2896 => "1100001001010001", 2897 => "1100001001001010",
2898 => "1100001001000100", 2899 => "1100001000111101", 2900 => "1100001000110110",
2901 => "1100001000110000", 2902 => "1100001000101001", 2903 => "1100001000100011",
2904 => "1100001000011101", 2905 => "1100001000010110", 2906 => "1100001000010000",
2907 => "1100001000001010", 2908 => "1100001000000011", 2909 => "1100000111111101",
2910 => "1100000111110111", 2911 => "1100000111110001", 2912 => "1100000111101011",
2913 => "1100000111100100", 2914 => "1100000111011110", 2915 => "1100000111011000",
2916 => "1100000111010010", 2917 => "1100000111001100", 2918 => "1100000111000111",
2919 => "1100000111000001", 2920 => "1100000110111011", 2921 => "1100000110110101",
2922 => "1100000110101111", 2923 => "1100000110101010", 2924 => "1100000110100100",
2925 => "1100000110011110", 2926 => "1100000110011001", 2927 => "1100000110010011",
2928 => "1100000110001110", 2929 => "1100000110001000", 2930 => "1100000110000011",
2931 => "1100000101111101", 2932 => "1100000101111000", 2933 => "1100000101110011",
2934 => "1100000101101101", 2935 => "1100000101101000", 2936 => "1100000101100011",
2937 => "1100000101011110", 2938 => "1100000101011000", 2939 => "1100000101010011",
2940 => "1100000101001110", 2941 => "1100000101001001", 2942 => "1100000101000100",
2943 => "1100000100111111", 2944 => "1100000100111010", 2945 => "1100000100110101",
2946 => "1100000100110001", 2947 => "1100000100101100", 2948 => "1100000100100111",
2949 => "1100000100100010", 2950 => "1100000100011110", 2951 => "1100000100011001",
2952 => "1100000100010100", 2953 => "1100000100010000", 2954 => "1100000100001011",
2955 => "1100000100000111", 2956 => "1100000100000010", 2957 => "1100000011111110",
2958 => "1100000011111001", 2959 => "1100000011110101", 2960 => "1100000011110001",
2961 => "1100000011101100", 2962 => "1100000011101000", 2963 => "1100000011100100",
2964 => "1100000011100000", 2965 => "1100000011011100", 2966 => "1100000011011000",
2967 => "1100000011010100", 2968 => "1100000011010000", 2969 => "1100000011001100",
2970 => "1100000011001000", 2971 => "1100000011000100", 2972 => "1100000011000000",
2973 => "1100000010111100", 2974 => "1100000010111000", 2975 => "1100000010110101",
2976 => "1100000010110001", 2977 => "1100000010101101", 2978 => "1100000010101010",
2979 => "1100000010100110", 2980 => "1100000010100010", 2981 => "1100000010011111",
2982 => "1100000010011011", 2983 => "1100000010011000", 2984 => "1100000010010101",
2985 => "1100000010010001", 2986 => "1100000010001110", 2987 => "1100000010001011",
2988 => "1100000010000111", 2989 => "1100000010000100", 2990 => "1100000010000001",
2991 => "1100000001111110", 2992 => "1100000001111011", 2993 => "1100000001111000",
2994 => "1100000001110101", 2995 => "1100000001110010", 2996 => "1100000001101111",
2997 => "1100000001101100", 2998 => "1100000001101001", 2999 => "1100000001100110",
3000 => "1100000001100011", 3001 => "1100000001100001", 3002 => "1100000001011110",
3003 => "1100000001011011", 3004 => "1100000001011001", 3005 => "1100000001010110",
3006 => "1100000001010011", 3007 => "1100000001010001", 3008 => "1100000001001110",
3009 => "1100000001001100", 3010 => "1100000001001010", 3011 => "1100000001000111",
3012 => "1100000001000101", 3013 => "1100000001000011", 3014 => "1100000001000000",
3015 => "1100000000111110", 3016 => "1100000000111100", 3017 => "1100000000111010",
3018 => "1100000000111000", 3019 => "1100000000110110", 3020 => "1100000000110100",
3021 => "1100000000110010", 3022 => "1100000000110000", 3023 => "1100000000101110",
3024 => "1100000000101100", 3025 => "1100000000101010", 3026 => "1100000000101000",
3027 => "1100000000100111", 3028 => "1100000000100101", 3029 => "1100000000100011",
3030 => "1100000000100001", 3031 => "1100000000100000", 3032 => "1100000000011110",
3033 => "1100000000011101", 3034 => "1100000000011011", 3035 => "1100000000011010",
3036 => "1100000000011000", 3037 => "1100000000010111", 3038 => "1100000000010110",
3039 => "1100000000010100", 3040 => "1100000000010011", 3041 => "1100000000010010",
3042 => "1100000000010001", 3043 => "1100000000010000", 3044 => "1100000000001111",
3045 => "1100000000001110", 3046 => "1100000000001101", 3047 => "1100000000001100",
3048 => "1100000000001011", 3049 => "1100000000001010", 3050 => "1100000000001001",
3051 => "1100000000001000", 3052 => "1100000000000111", 3053 to 3054=> "1100000000000110",
3055 => "1100000000000101", 3056 to 3057=> "1100000000000100", 3058 to 3059=> "1100000000000011",
3060 to 3061=> "1100000000000010", 3062 to 3064=> "1100000000000001", 3065 to 3079=> "1100000000000000",
3080 to 3082=> "1100000000000001", 3083 to 3084=> "1100000000000010", 3085 to 3086=> "1100000000000011",
3087 to 3088=> "1100000000000100", 3089 => "1100000000000101", 3090 to 3091=> "1100000000000110",
3092 => "1100000000000111", 3093 => "1100000000001000", 3094 => "1100000000001001",
3095 => "1100000000001010", 3096 => "1100000000001011", 3097 => "1100000000001100",
3098 => "1100000000001101", 3099 => "1100000000001110", 3100 => "1100000000001111",
3101 => "1100000000010000", 3102 => "1100000000010001", 3103 => "1100000000010010",
3104 => "1100000000010011", 3105 => "1100000000010100", 3106 => "1100000000010110",
3107 => "1100000000010111", 3108 => "1100000000011000", 3109 => "1100000000011010",
3110 => "1100000000011011", 3111 => "1100000000011101", 3112 => "1100000000011110",
3113 => "1100000000100000", 3114 => "1100000000100001", 3115 => "1100000000100011",
3116 => "1100000000100101", 3117 => "1100000000100111", 3118 => "1100000000101000",
3119 => "1100000000101010", 3120 => "1100000000101100", 3121 => "1100000000101110",
3122 => "1100000000110000", 3123 => "1100000000110010", 3124 => "1100000000110100",
3125 => "1100000000110110", 3126 => "1100000000111000", 3127 => "1100000000111010",
3128 => "1100000000111100", 3129 => "1100000000111110", 3130 => "1100000001000000",
3131 => "1100000001000011", 3132 => "1100000001000101", 3133 => "1100000001000111",
3134 => "1100000001001010", 3135 => "1100000001001100", 3136 => "1100000001001110",
3137 => "1100000001010001", 3138 => "1100000001010011", 3139 => "1100000001010110",
3140 => "1100000001011001", 3141 => "1100000001011011", 3142 => "1100000001011110",
3143 => "1100000001100001", 3144 => "1100000001100011", 3145 => "1100000001100110",
3146 => "1100000001101001", 3147 => "1100000001101100", 3148 => "1100000001101111",
3149 => "1100000001110010", 3150 => "1100000001110101", 3151 => "1100000001111000",
3152 => "1100000001111011", 3153 => "1100000001111110", 3154 => "1100000010000001",
3155 => "1100000010000100", 3156 => "1100000010000111", 3157 => "1100000010001011",
3158 => "1100000010001110", 3159 => "1100000010010001", 3160 => "1100000010010101",
3161 => "1100000010011000", 3162 => "1100000010011011", 3163 => "1100000010011111",
3164 => "1100000010100010", 3165 => "1100000010100110", 3166 => "1100000010101010",
3167 => "1100000010101101", 3168 => "1100000010110001", 3169 => "1100000010110101",
3170 => "1100000010111000", 3171 => "1100000010111100", 3172 => "1100000011000000",
3173 => "1100000011000100", 3174 => "1100000011001000", 3175 => "1100000011001100",
3176 => "1100000011010000", 3177 => "1100000011010100", 3178 => "1100000011011000",
3179 => "1100000011011100", 3180 => "1100000011100000", 3181 => "1100000011100100",
3182 => "1100000011101000", 3183 => "1100000011101100", 3184 => "1100000011110001",
3185 => "1100000011110101", 3186 => "1100000011111001", 3187 => "1100000011111110",
3188 => "1100000100000010", 3189 => "1100000100000111", 3190 => "1100000100001011",
3191 => "1100000100010000", 3192 => "1100000100010100", 3193 => "1100000100011001",
3194 => "1100000100011110", 3195 => "1100000100100010", 3196 => "1100000100100111",
3197 => "1100000100101100", 3198 => "1100000100110001", 3199 => "1100000100110101",
3200 => "1100000100111010", 3201 => "1100000100111111", 3202 => "1100000101000100",
3203 => "1100000101001001", 3204 => "1100000101001110", 3205 => "1100000101010011",
3206 => "1100000101011000", 3207 => "1100000101011110", 3208 => "1100000101100011",
3209 => "1100000101101000", 3210 => "1100000101101101", 3211 => "1100000101110011",
3212 => "1100000101111000", 3213 => "1100000101111101", 3214 => "1100000110000011",
3215 => "1100000110001000", 3216 => "1100000110001110", 3217 => "1100000110010011",
3218 => "1100000110011001", 3219 => "1100000110011110", 3220 => "1100000110100100",
3221 => "1100000110101010", 3222 => "1100000110101111", 3223 => "1100000110110101",
3224 => "1100000110111011", 3225 => "1100000111000001", 3226 => "1100000111000111",
3227 => "1100000111001100", 3228 => "1100000111010010", 3229 => "1100000111011000",
3230 => "1100000111011110", 3231 => "1100000111100100", 3232 => "1100000111101011",
3233 => "1100000111110001", 3234 => "1100000111110111", 3235 => "1100000111111101",
3236 => "1100001000000011", 3237 => "1100001000001010", 3238 => "1100001000010000",
3239 => "1100001000010110", 3240 => "1100001000011101", 3241 => "1100001000100011",
3242 => "1100001000101001", 3243 => "1100001000110000", 3244 => "1100001000110110",
3245 => "1100001000111101", 3246 => "1100001001000100", 3247 => "1100001001001010",
3248 => "1100001001010001", 3249 => "1100001001011000", 3250 => "1100001001011110",
3251 => "1100001001100101", 3252 => "1100001001101100", 3253 => "1100001001110011",
3254 => "1100001001111010", 3255 => "1100001010000001", 3256 => "1100001010001000",
3257 => "1100001010001111", 3258 => "1100001010010110", 3259 => "1100001010011101",
3260 => "1100001010100100", 3261 => "1100001010101011", 3262 => "1100001010110010",
3263 => "1100001010111010", 3264 => "1100001011000001", 3265 => "1100001011001000",
3266 => "1100001011010000", 3267 => "1100001011010111", 3268 => "1100001011011110",
3269 => "1100001011100110", 3270 => "1100001011101101", 3271 => "1100001011110101",
3272 => "1100001011111101", 3273 => "1100001100000100", 3274 => "1100001100001100",
3275 => "1100001100010011", 3276 => "1100001100011011", 3277 => "1100001100100011",
3278 => "1100001100101011", 3279 => "1100001100110011", 3280 => "1100001100111010",
3281 => "1100001101000010", 3282 => "1100001101001010", 3283 => "1100001101010010",
3284 => "1100001101011010", 3285 => "1100001101100010", 3286 => "1100001101101010",
3287 => "1100001101110011", 3288 => "1100001101111011", 3289 => "1100001110000011",
3290 => "1100001110001011", 3291 => "1100001110010011", 3292 => "1100001110011100",
3293 => "1100001110100100", 3294 => "1100001110101100", 3295 => "1100001110110101",
3296 => "1100001110111101", 3297 => "1100001111000110", 3298 => "1100001111001110",
3299 => "1100001111010111", 3300 => "1100001111011111", 3301 => "1100001111101000",
3302 => "1100001111110001", 3303 => "1100001111111001", 3304 => "1100010000000010",
3305 => "1100010000001011", 3306 => "1100010000010100", 3307 => "1100010000011101",
3308 => "1100010000100101", 3309 => "1100010000101110", 3310 => "1100010000110111",
3311 => "1100010001000000", 3312 => "1100010001001001", 3313 => "1100010001010010",
3314 => "1100010001011100", 3315 => "1100010001100101", 3316 => "1100010001101110",
3317 => "1100010001110111", 3318 => "1100010010000000", 3319 => "1100010010001010",
3320 => "1100010010010011", 3321 => "1100010010011100", 3322 => "1100010010100110",
3323 => "1100010010101111", 3324 => "1100010010111000", 3325 => "1100010011000010",
3326 => "1100010011001011", 3327 => "1100010011010101", 3328 => "1100010011011111",
3329 => "1100010011101000", 3330 => "1100010011110010", 3331 => "1100010011111100",
3332 => "1100010100000101", 3333 => "1100010100001111", 3334 => "1100010100011001",
3335 => "1100010100100011", 3336 => "1100010100101101", 3337 => "1100010100110111",
3338 => "1100010101000001", 3339 => "1100010101001011", 3340 => "1100010101010101",
3341 => "1100010101011111", 3342 => "1100010101101001", 3343 => "1100010101110011",
3344 => "1100010101111101", 3345 => "1100010110000111", 3346 => "1100010110010010",
3347 => "1100010110011100", 3348 => "1100010110100110", 3349 => "1100010110110000",
3350 => "1100010110111011", 3351 => "1100010111000101", 3352 => "1100010111010000",
3353 => "1100010111011010", 3354 => "1100010111100101", 3355 => "1100010111101111",
3356 => "1100010111111010", 3357 => "1100011000000100", 3358 => "1100011000001111",
3359 => "1100011000011010", 3360 => "1100011000100101", 3361 => "1100011000101111",
3362 => "1100011000111010", 3363 => "1100011001000101", 3364 => "1100011001010000",
3365 => "1100011001011011", 3366 => "1100011001100110", 3367 => "1100011001110001",
3368 => "1100011001111100", 3369 => "1100011010000111", 3370 => "1100011010010010",
3371 => "1100011010011101", 3372 => "1100011010101000", 3373 => "1100011010110011",
3374 => "1100011010111110", 3375 => "1100011011001010", 3376 => "1100011011010101",
3377 => "1100011011100000", 3378 => "1100011011101100", 3379 => "1100011011110111",
3380 => "1100011100000010", 3381 => "1100011100001110", 3382 => "1100011100011001",
3383 => "1100011100100101", 3384 => "1100011100110000", 3385 => "1100011100111100",
3386 => "1100011101001000", 3387 => "1100011101010011", 3388 => "1100011101011111",
3389 => "1100011101101011", 3390 => "1100011101110110", 3391 => "1100011110000010",
3392 => "1100011110001110", 3393 => "1100011110011010", 3394 => "1100011110100110",
3395 => "1100011110110010", 3396 => "1100011110111110", 3397 => "1100011111001010",
3398 => "1100011111010110", 3399 => "1100011111100010", 3400 => "1100011111101110",
3401 => "1100011111111010", 3402 => "1100100000000110", 3403 => "1100100000010010",
3404 => "1100100000011111", 3405 => "1100100000101011", 3406 => "1100100000110111",
3407 => "1100100001000100", 3408 => "1100100001010000", 3409 => "1100100001011100",
3410 => "1100100001101001", 3411 => "1100100001110101", 3412 => "1100100010000010",
3413 => "1100100010001110", 3414 => "1100100010011011", 3415 => "1100100010101000",
3416 => "1100100010110100", 3417 => "1100100011000001", 3418 => "1100100011001110",
3419 => "1100100011011010", 3420 => "1100100011100111", 3421 => "1100100011110100",
3422 => "1100100100000001", 3423 => "1100100100001110", 3424 => "1100100100011010",
3425 => "1100100100100111", 3426 => "1100100100110100", 3427 => "1100100101000001",
3428 => "1100100101001110", 3429 => "1100100101011011", 3430 => "1100100101101001",
3431 => "1100100101110110", 3432 => "1100100110000011", 3433 => "1100100110010000",
3434 => "1100100110011101", 3435 => "1100100110101011", 3436 => "1100100110111000",
3437 => "1100100111000101", 3438 => "1100100111010011", 3439 => "1100100111100000",
3440 => "1100100111101101", 3441 => "1100100111111011", 3442 => "1100101000001000",
3443 => "1100101000010110", 3444 => "1100101000100011", 3445 => "1100101000110001",
3446 => "1100101000111111", 3447 => "1100101001001100", 3448 => "1100101001011010",
3449 => "1100101001101000", 3450 => "1100101001110110", 3451 => "1100101010000011",
3452 => "1100101010010001", 3453 => "1100101010011111", 3454 => "1100101010101101",
3455 => "1100101010111011", 3456 => "1100101011001001", 3457 => "1100101011010111",
3458 => "1100101011100101", 3459 => "1100101011110011", 3460 => "1100101100000001",
3461 => "1100101100001111", 3462 => "1100101100011101", 3463 => "1100101100101011",
3464 => "1100101100111001", 3465 => "1100101101001000", 3466 => "1100101101010110",
3467 => "1100101101100100", 3468 => "1100101101110011", 3469 => "1100101110000001",
3470 => "1100101110001111", 3471 => "1100101110011110", 3472 => "1100101110101100",
3473 => "1100101110111011", 3474 => "1100101111001001", 3475 => "1100101111011000",
3476 => "1100101111100110", 3477 => "1100101111110101", 3478 => "1100110000000100",
3479 => "1100110000010010", 3480 => "1100110000100001", 3481 => "1100110000110000",
3482 => "1100110000111110", 3483 => "1100110001001101", 3484 => "1100110001011100",
3485 => "1100110001101011", 3486 => "1100110001111010", 3487 => "1100110010001001",
3488 => "1100110010011000", 3489 => "1100110010100111", 3490 => "1100110010110110",
3491 => "1100110011000101", 3492 => "1100110011010100", 3493 => "1100110011100011",
3494 => "1100110011110010", 3495 => "1100110100000001", 3496 => "1100110100010001",
3497 => "1100110100100000", 3498 => "1100110100101111", 3499 => "1100110100111110",
3500 => "1100110101001110", 3501 => "1100110101011101", 3502 => "1100110101101100",
3503 => "1100110101111100", 3504 => "1100110110001011", 3505 => "1100110110011011",
3506 => "1100110110101010", 3507 => "1100110110111010", 3508 => "1100110111001001",
3509 => "1100110111011001", 3510 => "1100110111101001", 3511 => "1100110111111000",
3512 => "1100111000001000", 3513 => "1100111000011000", 3514 => "1100111000100111",
3515 => "1100111000110111", 3516 => "1100111001000111", 3517 => "1100111001010111",
3518 => "1100111001100111", 3519 => "1100111001110111", 3520 => "1100111010000110",
3521 => "1100111010010110", 3522 => "1100111010100110", 3523 => "1100111010110110",
3524 => "1100111011000111", 3525 => "1100111011010111", 3526 => "1100111011100111",
3527 => "1100111011110111", 3528 => "1100111100000111", 3529 => "1100111100010111",
3530 => "1100111100100111", 3531 => "1100111100111000", 3532 => "1100111101001000",
3533 => "1100111101011000", 3534 => "1100111101101001", 3535 => "1100111101111001",
3536 => "1100111110001001", 3537 => "1100111110011010", 3538 => "1100111110101010",
3539 => "1100111110111011", 3540 => "1100111111001011", 3541 => "1100111111011100",
3542 => "1100111111101100", 3543 => "1100111111111101", 3544 => "1101000000001110",
3545 => "1101000000011110", 3546 => "1101000000101111", 3547 => "1101000001000000",
3548 => "1101000001010000", 3549 => "1101000001100001", 3550 => "1101000001110010",
3551 => "1101000010000011", 3552 => "1101000010010100", 3553 => "1101000010100101",
3554 => "1101000010110110", 3555 => "1101000011000111", 3556 => "1101000011010111",
3557 => "1101000011101001", 3558 => "1101000011111010", 3559 => "1101000100001011",
3560 => "1101000100011100", 3561 => "1101000100101101", 3562 => "1101000100111110",
3563 => "1101000101001111", 3564 => "1101000101100000", 3565 => "1101000101110010",
3566 => "1101000110000011", 3567 => "1101000110010100", 3568 => "1101000110100101",
3569 => "1101000110110111", 3570 => "1101000111001000", 3571 => "1101000111011010",
3572 => "1101000111101011", 3573 => "1101000111111100", 3574 => "1101001000001110",
3575 => "1101001000011111", 3576 => "1101001000110001", 3577 => "1101001001000011",
3578 => "1101001001010100", 3579 => "1101001001100110", 3580 => "1101001001110111",
3581 => "1101001010001001", 3582 => "1101001010011011", 3583 => "1101001010101101",
3584 => "1101001010111110", 3585 => "1101001011010000", 3586 => "1101001011100010",
3587 => "1101001011110100", 3588 => "1101001100000110", 3589 => "1101001100010111",
3590 => "1101001100101001", 3591 => "1101001100111011", 3592 => "1101001101001101",
3593 => "1101001101011111", 3594 => "1101001101110001", 3595 => "1101001110000011",
3596 => "1101001110010101", 3597 => "1101001110101000", 3598 => "1101001110111010",
3599 => "1101001111001100", 3600 => "1101001111011110", 3601 => "1101001111110000",
3602 => "1101010000000011", 3603 => "1101010000010101", 3604 => "1101010000100111",
3605 => "1101010000111001", 3606 => "1101010001001100", 3607 => "1101010001011110",
3608 => "1101010001110001", 3609 => "1101010010000011", 3610 => "1101010010010101",
3611 => "1101010010101000", 3612 => "1101010010111010", 3613 => "1101010011001101",
3614 => "1101010011011111", 3615 => "1101010011110010", 3616 => "1101010100000101",
3617 => "1101010100010111", 3618 => "1101010100101010", 3619 => "1101010100111101",
3620 => "1101010101001111", 3621 => "1101010101100010", 3622 => "1101010101110101",
3623 => "1101010110001000", 3624 => "1101010110011010", 3625 => "1101010110101101",
3626 => "1101010111000000", 3627 => "1101010111010011", 3628 => "1101010111100110",
3629 => "1101010111111001", 3630 => "1101011000001100", 3631 => "1101011000011111",
3632 => "1101011000110010", 3633 => "1101011001000101", 3634 => "1101011001011000",
3635 => "1101011001101011", 3636 => "1101011001111110", 3637 => "1101011010010001",
3638 => "1101011010100101", 3639 => "1101011010111000", 3640 => "1101011011001011",
3641 => "1101011011011110", 3642 => "1101011011110001", 3643 => "1101011100000101",
3644 => "1101011100011000", 3645 => "1101011100101011", 3646 => "1101011100111111",
3647 => "1101011101010010", 3648 => "1101011101100110", 3649 => "1101011101111001",
3650 => "1101011110001101", 3651 => "1101011110100000", 3652 => "1101011110110100",
3653 => "1101011111000111", 3654 => "1101011111011011", 3655 => "1101011111101110",
3656 => "1101100000000010", 3657 => "1101100000010101", 3658 => "1101100000101001",
3659 => "1101100000111101", 3660 => "1101100001010000", 3661 => "1101100001100100",
3662 => "1101100001111000", 3663 => "1101100010001100", 3664 => "1101100010100000",
3665 => "1101100010110011", 3666 => "1101100011000111", 3667 => "1101100011011011",
3668 => "1101100011101111", 3669 => "1101100100000011", 3670 => "1101100100010111",
3671 => "1101100100101011", 3672 => "1101100100111111", 3673 => "1101100101010011",
3674 => "1101100101100111", 3675 => "1101100101111011", 3676 => "1101100110001111",
3677 => "1101100110100011", 3678 => "1101100110110111", 3679 => "1101100111001011",
3680 => "1101100111100000", 3681 => "1101100111110100", 3682 => "1101101000001000",
3683 => "1101101000011100", 3684 => "1101101000110000", 3685 => "1101101001000101",
3686 => "1101101001011001", 3687 => "1101101001101101", 3688 => "1101101010000010",
3689 => "1101101010010110", 3690 => "1101101010101011", 3691 => "1101101010111111",
3692 => "1101101011010011", 3693 => "1101101011101000", 3694 => "1101101011111100",
3695 => "1101101100010001", 3696 => "1101101100100101", 3697 => "1101101100111010",
3698 => "1101101101001111", 3699 => "1101101101100011", 3700 => "1101101101111000",
3701 => "1101101110001100", 3702 => "1101101110100001", 3703 => "1101101110110110",
3704 => "1101101111001011", 3705 => "1101101111011111", 3706 => "1101101111110100",
3707 => "1101110000001001", 3708 => "1101110000011110", 3709 => "1101110000110010",
3710 => "1101110001000111", 3711 => "1101110001011100", 3712 => "1101110001110001",
3713 => "1101110010000110", 3714 => "1101110010011011", 3715 => "1101110010110000",
3716 => "1101110011000101", 3717 => "1101110011011010", 3718 => "1101110011101111",
3719 => "1101110100000100", 3720 => "1101110100011001", 3721 => "1101110100101110",
3722 => "1101110101000011", 3723 => "1101110101011000", 3724 => "1101110101101101",
3725 => "1101110110000010", 3726 => "1101110110011000", 3727 => "1101110110101101",
3728 => "1101110111000010", 3729 => "1101110111010111", 3730 => "1101110111101101",
3731 => "1101111000000010", 3732 => "1101111000010111", 3733 => "1101111000101101",
3734 => "1101111001000010", 3735 => "1101111001010111", 3736 => "1101111001101101",
3737 => "1101111010000010", 3738 => "1101111010010111", 3739 => "1101111010101101",
3740 => "1101111011000010", 3741 => "1101111011011000", 3742 => "1101111011101101",
3743 => "1101111100000011", 3744 => "1101111100011000", 3745 => "1101111100101110",
3746 => "1101111101000100", 3747 => "1101111101011001", 3748 => "1101111101101111",
3749 => "1101111110000100", 3750 => "1101111110011010", 3751 => "1101111110110000",
3752 => "1101111111000110", 3753 => "1101111111011011", 3754 => "1101111111110001",
3755 => "1110000000000111", 3756 => "1110000000011101", 3757 => "1110000000110010",
3758 => "1110000001001000", 3759 => "1110000001011110", 3760 => "1110000001110100",
3761 => "1110000010001010", 3762 => "1110000010100000", 3763 => "1110000010110110",
3764 => "1110000011001011", 3765 => "1110000011100001", 3766 => "1110000011110111",
3767 => "1110000100001101", 3768 => "1110000100100011", 3769 => "1110000100111001",
3770 => "1110000101001111", 3771 => "1110000101100110", 3772 => "1110000101111100",
3773 => "1110000110010010", 3774 => "1110000110101000", 3775 => "1110000110111110",
3776 => "1110000111010100", 3777 => "1110000111101010", 3778 => "1110001000000001",
3779 => "1110001000010111", 3780 => "1110001000101101", 3781 => "1110001001000011",
3782 => "1110001001011001", 3783 => "1110001001110000", 3784 => "1110001010000110",
3785 => "1110001010011100", 3786 => "1110001010110011", 3787 => "1110001011001001",
3788 => "1110001011011111", 3789 => "1110001011110110", 3790 => "1110001100001100",
3791 => "1110001100100011", 3792 => "1110001100111001", 3793 => "1110001101010000",
3794 => "1110001101100110", 3795 => "1110001101111100", 3796 => "1110001110010011",
3797 => "1110001110101010", 3798 => "1110001111000000", 3799 => "1110001111010111",
3800 => "1110001111101101", 3801 => "1110010000000100", 3802 => "1110010000011010",
3803 => "1110010000110001", 3804 => "1110010001001000", 3805 => "1110010001011110",
3806 => "1110010001110101", 3807 => "1110010010001100", 3808 => "1110010010100010",
3809 => "1110010010111001", 3810 => "1110010011010000", 3811 => "1110010011100111",
3812 => "1110010011111101", 3813 => "1110010100010100", 3814 => "1110010100101011",
3815 => "1110010101000010", 3816 => "1110010101011001", 3817 => "1110010101110000",
3818 => "1110010110000110", 3819 => "1110010110011101", 3820 => "1110010110110100",
3821 => "1110010111001011", 3822 => "1110010111100010", 3823 => "1110010111111001",
3824 => "1110011000010000", 3825 => "1110011000100111", 3826 => "1110011000111110",
3827 => "1110011001010101", 3828 => "1110011001101100", 3829 => "1110011010000011",
3830 => "1110011010011010", 3831 => "1110011010110001", 3832 => "1110011011001000",
3833 => "1110011011011111", 3834 => "1110011011110111", 3835 => "1110011100001110",
3836 => "1110011100100101", 3837 => "1110011100111100", 3838 => "1110011101010011",
3839 => "1110011101101010", 3840 => "1110011110000010", 3841 => "1110011110011001",
3842 => "1110011110110000", 3843 => "1110011111000111", 3844 => "1110011111011111",
3845 => "1110011111110110", 3846 => "1110100000001101", 3847 => "1110100000100101",
3848 => "1110100000111100", 3849 => "1110100001010011", 3850 => "1110100001101011",
3851 => "1110100010000010", 3852 => "1110100010011001", 3853 => "1110100010110001",
3854 => "1110100011001000", 3855 => "1110100011100000", 3856 => "1110100011110111",
3857 => "1110100100001110", 3858 => "1110100100100110", 3859 => "1110100100111101",
3860 => "1110100101010101", 3861 => "1110100101101100", 3862 => "1110100110000100",
3863 => "1110100110011011", 3864 => "1110100110110011", 3865 => "1110100111001011",
3866 => "1110100111100010", 3867 => "1110100111111010", 3868 => "1110101000010001",
3869 => "1110101000101001", 3870 => "1110101001000001", 3871 => "1110101001011000",
3872 => "1110101001110000", 3873 => "1110101010001000", 3874 => "1110101010011111",
3875 => "1110101010110111", 3876 => "1110101011001111", 3877 => "1110101011100110",
3878 => "1110101011111110", 3879 => "1110101100010110", 3880 => "1110101100101110",
3881 => "1110101101000101", 3882 => "1110101101011101", 3883 => "1110101101110101",
3884 => "1110101110001101", 3885 => "1110101110100101", 3886 => "1110101110111100",
3887 => "1110101111010100", 3888 => "1110101111101100", 3889 => "1110110000000100",
3890 => "1110110000011100", 3891 => "1110110000110100", 3892 => "1110110001001100",
3893 => "1110110001100100", 3894 => "1110110001111100", 3895 => "1110110010010011",
3896 => "1110110010101011", 3897 => "1110110011000011", 3898 => "1110110011011011",
3899 => "1110110011110011", 3900 => "1110110100001011", 3901 => "1110110100100011",
3902 => "1110110100111011", 3903 => "1110110101010011", 3904 => "1110110101101011",
3905 => "1110110110000100", 3906 => "1110110110011100", 3907 => "1110110110110100",
3908 => "1110110111001100", 3909 => "1110110111100100", 3910 => "1110110111111100",
3911 => "1110111000010100", 3912 => "1110111000101100", 3913 => "1110111001000100",
3914 => "1110111001011101", 3915 => "1110111001110101", 3916 => "1110111010001101",
3917 => "1110111010100101", 3918 => "1110111010111101", 3919 => "1110111011010101",
3920 => "1110111011101110", 3921 => "1110111100000110", 3922 => "1110111100011110",
3923 => "1110111100110110", 3924 => "1110111101001111", 3925 => "1110111101100111",
3926 => "1110111101111111", 3927 => "1110111110010111", 3928 => "1110111110110000",
3929 => "1110111111001000", 3930 => "1110111111100000", 3931 => "1110111111111001",
3932 => "1111000000010001", 3933 => "1111000000101001", 3934 => "1111000001000010",
3935 => "1111000001011010", 3936 => "1111000001110011", 3937 => "1111000010001011",
3938 => "1111000010100011", 3939 => "1111000010111100", 3940 => "1111000011010100",
3941 => "1111000011101101", 3942 => "1111000100000101", 3943 => "1111000100011101",
3944 => "1111000100110110", 3945 => "1111000101001110", 3946 => "1111000101100111",
3947 => "1111000101111111", 3948 => "1111000110011000", 3949 => "1111000110110000",
3950 => "1111000111001001", 3951 => "1111000111100001", 3952 => "1111000111111010",
3953 => "1111001000010010", 3954 => "1111001000101011", 3955 => "1111001001000011",
3956 => "1111001001011100", 3957 => "1111001001110100", 3958 => "1111001010001101",
3959 => "1111001010100110", 3960 => "1111001010111110", 3961 => "1111001011010111",
3962 => "1111001011101111", 3963 => "1111001100001000", 3964 => "1111001100100001",
3965 => "1111001100111001", 3966 => "1111001101010010", 3967 => "1111001101101010",
3968 => "1111001110000011", 3969 => "1111001110011100", 3970 => "1111001110110100",
3971 => "1111001111001101", 3972 => "1111001111100110", 3973 => "1111001111111110",
3974 => "1111010000010111", 3975 => "1111010000110000", 3976 => "1111010001001001",
3977 => "1111010001100001", 3978 => "1111010001111010", 3979 => "1111010010010011",
3980 => "1111010010101011", 3981 => "1111010011000100", 3982 => "1111010011011101",
3983 => "1111010011110110", 3984 => "1111010100001110", 3985 => "1111010100100111",
3986 => "1111010101000000", 3987 => "1111010101011001", 3988 => "1111010101110010",
3989 => "1111010110001010", 3990 => "1111010110100011", 3991 => "1111010110111100",
3992 => "1111010111010101", 3993 => "1111010111101110", 3994 => "1111011000000110",
3995 => "1111011000011111", 3996 => "1111011000111000", 3997 => "1111011001010001",
3998 => "1111011001101010", 3999 => "1111011010000011", 4000 => "1111011010011011",
4001 => "1111011010110100", 4002 => "1111011011001101", 4003 => "1111011011100110",
4004 => "1111011011111111", 4005 => "1111011100011000", 4006 => "1111011100110001",
4007 => "1111011101001010", 4008 => "1111011101100011", 4009 => "1111011101111011",
4010 => "1111011110010100", 4011 => "1111011110101101", 4012 => "1111011111000110",
4013 => "1111011111011111", 4014 => "1111011111111000", 4015 => "1111100000010001",
4016 => "1111100000101010", 4017 => "1111100001000011", 4018 => "1111100001011100",
4019 => "1111100001110101", 4020 => "1111100010001110", 4021 => "1111100010100111",
4022 => "1111100011000000", 4023 => "1111100011011001", 4024 => "1111100011110010",
4025 => "1111100100001011", 4026 => "1111100100100100", 4027 => "1111100100111101",
4028 => "1111100101010110", 4029 => "1111100101101111", 4030 => "1111100110001000",
4031 => "1111100110100001", 4032 => "1111100110111010", 4033 => "1111100111010011",
4034 => "1111100111101100", 4035 => "1111101000000101", 4036 => "1111101000011110",
4037 => "1111101000110111", 4038 => "1111101001010000", 4039 => "1111101001101001",
4040 => "1111101010000010", 4041 => "1111101010011011", 4042 => "1111101010110100",
4043 => "1111101011001101", 4044 => "1111101011100110", 4045 => "1111101011111111",
4046 => "1111101100011000", 4047 => "1111101100110001", 4048 => "1111101101001010",
4049 => "1111101101100011", 4050 => "1111101101111100", 4051 => "1111101110010101",
4052 => "1111101110101110", 4053 => "1111101111001000", 4054 => "1111101111100001",
4055 => "1111101111111010", 4056 => "1111110000010011", 4057 => "1111110000101100",
4058 => "1111110001000101", 4059 => "1111110001011110", 4060 => "1111110001110111",
4061 => "1111110010010000", 4062 => "1111110010101001", 4063 => "1111110011000010",
4064 => "1111110011011100", 4065 => "1111110011110101", 4066 => "1111110100001110",
4067 => "1111110100100111", 4068 => "1111110101000000", 4069 => "1111110101011001",
4070 => "1111110101110010", 4071 => "1111110110001011", 4072 => "1111110110100100",
4073 => "1111110110111110", 4074 => "1111110111010111", 4075 => "1111110111110000",
4076 => "1111111000001001", 4077 => "1111111000100010", 4078 => "1111111000111011",
4079 => "1111111001010100", 4080 => "1111111001101101", 4081 => "1111111010000111",
4082 => "1111111010100000", 4083 => "1111111010111001", 4084 => "1111111011010010",
4085 => "1111111011101011", 4086 => "1111111100000100", 4087 => "1111111100011101",
4088 => "1111111100110110", 4089 => "1111111101010000", 4090 => "1111111101101001",
4091 => "1111111110000010", 4092 => "1111111110011011", 4093 => "1111111110110100",
4094 => "1111111111001101", 4095 => "1111111111100110" );
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nco_sine_lut_V is
generic (
DataWidth : INTEGER := 16;
AddressRange : INTEGER := 4096;
AddressWidth : INTEGER := 12);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of nco_sine_lut_V is
component nco_sine_lut_V_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
nco_sine_lut_V_rom_U : component nco_sine_lut_V_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nco_sine_lut_V_rom is
generic(
dwidth : integer := 16;
awidth : integer := 12;
mem_size : integer := 4096
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of nco_sine_lut_V_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "0000000000000000", 1 => "0000000000011001", 2 => "0000000000110010",
3 => "0000000001001011", 4 => "0000000001100100", 5 => "0000000001111101",
6 => "0000000010010110", 7 => "0000000010101111", 8 => "0000000011001001",
9 => "0000000011100010", 10 => "0000000011111011", 11 => "0000000100010100",
12 => "0000000100101101", 13 => "0000000101000110", 14 => "0000000101011111",
15 => "0000000101111000", 16 => "0000000110010010", 17 => "0000000110101011",
18 => "0000000111000100", 19 => "0000000111011101", 20 => "0000000111110110",
21 => "0000001000001111", 22 => "0000001000101000", 23 => "0000001001000001",
24 => "0000001001011011", 25 => "0000001001110100", 26 => "0000001010001101",
27 => "0000001010100110", 28 => "0000001010111111", 29 => "0000001011011000",
30 => "0000001011110001", 31 => "0000001100001010", 32 => "0000001100100011",
33 => "0000001100111101", 34 => "0000001101010110", 35 => "0000001101101111",
36 => "0000001110001000", 37 => "0000001110100001", 38 => "0000001110111010",
39 => "0000001111010011", 40 => "0000001111101100", 41 => "0000010000000101",
42 => "0000010000011110", 43 => "0000010000110111", 44 => "0000010001010001",
45 => "0000010001101010", 46 => "0000010010000011", 47 => "0000010010011100",
48 => "0000010010110101", 49 => "0000010011001110", 50 => "0000010011100111",
51 => "0000010100000000", 52 => "0000010100011001", 53 => "0000010100110010",
54 => "0000010101001011", 55 => "0000010101100100", 56 => "0000010101111101",
57 => "0000010110010110", 58 => "0000010110101111", 59 => "0000010111001000",
60 => "0000010111100001", 61 => "0000010111111010", 62 => "0000011000010011",
63 => "0000011000101100", 64 => "0000011001000101", 65 => "0000011001011110",
66 => "0000011001110111", 67 => "0000011010010000", 68 => "0000011010101001",
69 => "0000011011000010", 70 => "0000011011011011", 71 => "0000011011110100",
72 => "0000011100001101", 73 => "0000011100100110", 74 => "0000011100111111",
75 => "0000011101011000", 76 => "0000011101110001", 77 => "0000011110001010",
78 => "0000011110100011", 79 => "0000011110111100", 80 => "0000011111010101",
81 => "0000011111101110", 82 => "0000100000000111", 83 => "0000100000100000",
84 => "0000100000111001", 85 => "0000100001010010", 86 => "0000100001101011",
87 => "0000100010000100", 88 => "0000100010011100", 89 => "0000100010110101",
90 => "0000100011001110", 91 => "0000100011100111", 92 => "0000100100000000",
93 => "0000100100011001", 94 => "0000100100110010", 95 => "0000100101001011",
96 => "0000100101100100", 97 => "0000100101111100", 98 => "0000100110010101",
99 => "0000100110101110", 100 => "0000100111000111", 101 => "0000100111100000",
102 => "0000100111111001", 103 => "0000101000010001", 104 => "0000101000101010",
105 => "0000101001000011", 106 => "0000101001011100", 107 => "0000101001110101",
108 => "0000101010001101", 109 => "0000101010100110", 110 => "0000101010111111",
111 => "0000101011011000", 112 => "0000101011110001", 113 => "0000101100001001",
114 => "0000101100100010", 115 => "0000101100111011", 116 => "0000101101010100",
117 => "0000101101101100", 118 => "0000101110000101", 119 => "0000101110011110",
120 => "0000101110110110", 121 => "0000101111001111", 122 => "0000101111101000",
123 => "0000110000000001", 124 => "0000110000011001", 125 => "0000110000110010",
126 => "0000110001001011", 127 => "0000110001100011", 128 => "0000110001111100",
129 => "0000110010010101", 130 => "0000110010101101", 131 => "0000110011000110",
132 => "0000110011011110", 133 => "0000110011110111", 134 => "0000110100010000",
135 => "0000110100101000", 136 => "0000110101000001", 137 => "0000110101011001",
138 => "0000110101110010", 139 => "0000110110001011", 140 => "0000110110100011",
141 => "0000110110111100", 142 => "0000110111010100", 143 => "0000110111101101",
144 => "0000111000000101", 145 => "0000111000011110", 146 => "0000111000110110",
147 => "0000111001001111", 148 => "0000111001100111", 149 => "0000111010000000",
150 => "0000111010011000", 151 => "0000111010110001", 152 => "0000111011001001",
153 => "0000111011100010", 154 => "0000111011111010", 155 => "0000111100010010",
156 => "0000111100101011", 157 => "0000111101000011", 158 => "0000111101011100",
159 => "0000111101110100", 160 => "0000111110001100", 161 => "0000111110100101",
162 => "0000111110111101", 163 => "0000111111010110", 164 => "0000111111101110",
165 => "0001000000000110", 166 => "0001000000011111", 167 => "0001000000110111",
168 => "0001000001001111", 169 => "0001000001101000", 170 => "0001000010000000",
171 => "0001000010011000", 172 => "0001000010110000", 173 => "0001000011001001",
174 => "0001000011100001", 175 => "0001000011111001", 176 => "0001000100010001",
177 => "0001000100101010", 178 => "0001000101000010", 179 => "0001000101011010",
180 => "0001000101110010", 181 => "0001000110001010", 182 => "0001000110100010",
183 => "0001000110111011", 184 => "0001000111010011", 185 => "0001000111101011",
186 => "0001001000000011", 187 => "0001001000011011", 188 => "0001001000110011",
189 => "0001001001001011", 190 => "0001001001100011", 191 => "0001001001111011",
192 => "0001001010010100", 193 => "0001001010101100", 194 => "0001001011000100",
195 => "0001001011011100", 196 => "0001001011110100", 197 => "0001001100001100",
198 => "0001001100100100", 199 => "0001001100111100", 200 => "0001001101010100",
201 => "0001001101101100", 202 => "0001001110000011", 203 => "0001001110011011",
204 => "0001001110110011", 205 => "0001001111001011", 206 => "0001001111100011",
207 => "0001001111111011", 208 => "0001010000010011", 209 => "0001010000101011",
210 => "0001010001000011", 211 => "0001010001011010", 212 => "0001010001110010",
213 => "0001010010001010", 214 => "0001010010100010", 215 => "0001010010111010",
216 => "0001010011010001", 217 => "0001010011101001", 218 => "0001010100000001",
219 => "0001010100011001", 220 => "0001010100110000", 221 => "0001010101001000",
222 => "0001010101100000", 223 => "0001010101110111", 224 => "0001010110001111",
225 => "0001010110100111", 226 => "0001010110111110", 227 => "0001010111010110",
228 => "0001010111101110", 229 => "0001011000000101", 230 => "0001011000011101",
231 => "0001011000110100", 232 => "0001011001001100", 233 => "0001011001100100",
234 => "0001011001111011", 235 => "0001011010010011", 236 => "0001011010101010",
237 => "0001011011000010", 238 => "0001011011011001", 239 => "0001011011110001",
240 => "0001011100001000", 241 => "0001011100011111", 242 => "0001011100110111",
243 => "0001011101001110", 244 => "0001011101100110", 245 => "0001011101111101",
246 => "0001011110010100", 247 => "0001011110101100", 248 => "0001011111000011",
249 => "0001011111011010", 250 => "0001011111110010", 251 => "0001100000001001",
252 => "0001100000100000", 253 => "0001100000111000", 254 => "0001100001001111",
255 => "0001100001100110", 256 => "0001100001111101", 257 => "0001100010010101",
258 => "0001100010101100", 259 => "0001100011000011", 260 => "0001100011011010",
261 => "0001100011110001", 262 => "0001100100001000", 263 => "0001100100100000",
264 => "0001100100110111", 265 => "0001100101001110", 266 => "0001100101100101",
267 => "0001100101111100", 268 => "0001100110010011", 269 => "0001100110101010",
270 => "0001100111000001", 271 => "0001100111011000", 272 => "0001100111101111",
273 => "0001101000000110", 274 => "0001101000011101", 275 => "0001101000110100",
276 => "0001101001001011", 277 => "0001101001100010", 278 => "0001101001111001",
279 => "0001101010001111", 280 => "0001101010100110", 281 => "0001101010111101",
282 => "0001101011010100", 283 => "0001101011101011", 284 => "0001101100000010",
285 => "0001101100011000", 286 => "0001101100101111", 287 => "0001101101000110",
288 => "0001101101011101", 289 => "0001101101110011", 290 => "0001101110001010",
291 => "0001101110100001", 292 => "0001101110110111", 293 => "0001101111001110",
294 => "0001101111100101", 295 => "0001101111111011", 296 => "0001110000010010",
297 => "0001110000101000", 298 => "0001110000111111", 299 => "0001110001010101",
300 => "0001110001101100", 301 => "0001110010000011", 302 => "0001110010011001",
303 => "0001110010101111", 304 => "0001110011000110", 305 => "0001110011011100",
306 => "0001110011110011", 307 => "0001110100001001", 308 => "0001110100100000",
309 => "0001110100110110", 310 => "0001110101001100", 311 => "0001110101100011",
312 => "0001110101111001", 313 => "0001110110001111", 314 => "0001110110100110",
315 => "0001110110111100", 316 => "0001110111010010", 317 => "0001110111101000",
318 => "0001110111111110", 319 => "0001111000010101", 320 => "0001111000101011",
321 => "0001111001000001", 322 => "0001111001010111", 323 => "0001111001101101",
324 => "0001111010000011", 325 => "0001111010011001", 326 => "0001111010110000",
327 => "0001111011000110", 328 => "0001111011011100", 329 => "0001111011110010",
330 => "0001111100001000", 331 => "0001111100011110", 332 => "0001111100110100",
333 => "0001111101001001", 334 => "0001111101011111", 335 => "0001111101110101",
336 => "0001111110001011", 337 => "0001111110100001", 338 => "0001111110110111",
339 => "0001111111001101", 340 => "0001111111100010", 341 => "0001111111111000",
342 => "0010000000001110", 343 => "0010000000100100", 344 => "0010000000111001",
345 => "0010000001001111", 346 => "0010000001100101", 347 => "0010000001111011",
348 => "0010000010010000", 349 => "0010000010100110", 350 => "0010000010111011",
351 => "0010000011010001", 352 => "0010000011100111", 353 => "0010000011111100",
354 => "0010000100010010", 355 => "0010000100100111", 356 => "0010000100111101",
357 => "0010000101010010", 358 => "0010000101101000", 359 => "0010000101111101",
360 => "0010000110010010", 361 => "0010000110101000", 362 => "0010000110111101",
363 => "0010000111010010", 364 => "0010000111101000", 365 => "0010000111111101",
366 => "0010001000010010", 367 => "0010001000101000", 368 => "0010001000111101",
369 => "0010001001010010", 370 => "0010001001100111", 371 => "0010001001111101",
372 => "0010001010010010", 373 => "0010001010100111", 374 => "0010001010111100",
375 => "0010001011010001", 376 => "0010001011100110", 377 => "0010001011111011",
378 => "0010001100010000", 379 => "0010001100100101", 380 => "0010001100111010",
381 => "0010001101001111", 382 => "0010001101100100", 383 => "0010001101111001",
384 => "0010001110001110", 385 => "0010001110100011", 386 => "0010001110111000",
387 => "0010001111001101", 388 => "0010001111100001", 389 => "0010001111110110",
390 => "0010010000001011", 391 => "0010010000100000", 392 => "0010010000110100",
393 => "0010010001001001", 394 => "0010010001011110", 395 => "0010010001110011",
396 => "0010010010000111", 397 => "0010010010011100", 398 => "0010010010110000",
399 => "0010010011000101", 400 => "0010010011011010", 401 => "0010010011101110",
402 => "0010010100000011", 403 => "0010010100010111", 404 => "0010010100101100",
405 => "0010010101000000", 406 => "0010010101010100", 407 => "0010010101101001",
408 => "0010010101111101", 409 => "0010010110010010", 410 => "0010010110100110",
411 => "0010010110111010", 412 => "0010010111001111", 413 => "0010010111100011",
414 => "0010010111110111", 415 => "0010011000001011", 416 => "0010011000011111",
417 => "0010011000110100", 418 => "0010011001001000", 419 => "0010011001011100",
420 => "0010011001110000", 421 => "0010011010000100", 422 => "0010011010011000",
423 => "0010011010101100", 424 => "0010011011000000", 425 => "0010011011010100",
426 => "0010011011101000", 427 => "0010011011111100", 428 => "0010011100010000",
429 => "0010011100100100", 430 => "0010011100111000", 431 => "0010011101001100",
432 => "0010011101011111", 433 => "0010011101110011", 434 => "0010011110000111",
435 => "0010011110011011", 436 => "0010011110101111", 437 => "0010011111000010",
438 => "0010011111010110", 439 => "0010011111101010", 440 => "0010011111111101",
441 => "0010100000010001", 442 => "0010100000100100", 443 => "0010100000111000",
444 => "0010100001001011", 445 => "0010100001011111", 446 => "0010100001110010",
447 => "0010100010000110", 448 => "0010100010011001", 449 => "0010100010101101",
450 => "0010100011000000", 451 => "0010100011010100", 452 => "0010100011100111",
453 => "0010100011111010", 454 => "0010100100001110", 455 => "0010100100100001",
456 => "0010100100110100", 457 => "0010100101000111", 458 => "0010100101011010",
459 => "0010100101101110", 460 => "0010100110000001", 461 => "0010100110010100",
462 => "0010100110100111", 463 => "0010100110111010", 464 => "0010100111001101",
465 => "0010100111100000", 466 => "0010100111110011", 467 => "0010101000000110",
468 => "0010101000011001", 469 => "0010101000101100", 470 => "0010101000111111",
471 => "0010101001010010", 472 => "0010101001100101", 473 => "0010101001110111",
474 => "0010101010001010", 475 => "0010101010011101", 476 => "0010101010110000",
477 => "0010101011000010", 478 => "0010101011010101", 479 => "0010101011101000",
480 => "0010101011111010", 481 => "0010101100001101", 482 => "0010101100100000",
483 => "0010101100110010", 484 => "0010101101000101", 485 => "0010101101010111",
486 => "0010101101101010", 487 => "0010101101111100", 488 => "0010101110001110",
489 => "0010101110100001", 490 => "0010101110110011", 491 => "0010101111000110",
492 => "0010101111011000", 493 => "0010101111101010", 494 => "0010101111111100",
495 => "0010110000001111", 496 => "0010110000100001", 497 => "0010110000110011",
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501 => "0010110001111100", 502 => "0010110010001110", 503 => "0010110010100000",
504 => "0010110010110010", 505 => "0010110011000100", 506 => "0010110011010110",
507 => "0010110011101000", 508 => "0010110011111001", 509 => "0010110100001011",
510 => "0010110100011101", 511 => "0010110100101111", 512 => "0010110101000001",
513 => "0010110101010010", 514 => "0010110101100100", 515 => "0010110101110110",
516 => "0010110110001000", 517 => "0010110110011001", 518 => "0010110110101011",
519 => "0010110110111100", 520 => "0010110111001110", 521 => "0010110111100000",
522 => "0010110111110001", 523 => "0010111000000011", 524 => "0010111000010100",
525 => "0010111000100101", 526 => "0010111000110111", 527 => "0010111001001000",
528 => "0010111001011010", 529 => "0010111001101011", 530 => "0010111001111100",
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534 => "0010111011000001", 535 => "0010111011010010", 536 => "0010111011100011",
537 => "0010111011110100", 538 => "0010111100000101", 539 => "0010111100010110",
540 => "0010111100101000", 541 => "0010111100111000", 542 => "0010111101001001",
543 => "0010111101011010", 544 => "0010111101101011", 545 => "0010111101111100",
546 => "0010111110001101", 547 => "0010111110011110", 548 => "0010111110101111",
549 => "0010111110111111", 550 => "0010111111010000", 551 => "0010111111100001",
552 => "0010111111110001", 553 => "0011000000000010", 554 => "0011000000010011",
555 => "0011000000100011", 556 => "0011000000110100", 557 => "0011000001000100",
558 => "0011000001010101", 559 => "0011000001100101", 560 => "0011000001110110",
561 => "0011000010000110", 562 => "0011000010010110", 563 => "0011000010100111",
564 => "0011000010110111", 565 => "0011000011000111", 566 => "0011000011011000",
567 => "0011000011101000", 568 => "0011000011111000", 569 => "0011000100001000",
570 => "0011000100011000", 571 => "0011000100101000", 572 => "0011000100111000",
573 => "0011000101001001", 574 => "0011000101011001", 575 => "0011000101101001",
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585 => "0011001000000111", 586 => "0011001000010110", 587 => "0011001000100110",
588 => "0011001000110110", 589 => "0011001001000101", 590 => "0011001001010101",
591 => "0011001001100100", 592 => "0011001001110100", 593 => "0011001010000011",
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600 => "0011001011101110", 601 => "0011001011111110", 602 => "0011001100001101",
603 => "0011001100011100", 604 => "0011001100101011", 605 => "0011001100111010",
606 => "0011001101001001", 607 => "0011001101011000", 608 => "0011001101100111",
609 => "0011001101110110", 610 => "0011001110000101", 611 => "0011001110010100",
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615 => "0011001111001111", 616 => "0011001111011110", 617 => "0011001111101101",
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945 => "0011111110000111", 946 => "0011111110001010", 947 => "0011111110001101",
948 => "0011111110010000", 949 => "0011111110010011", 950 => "0011111110010110",
951 => "0011111110011001", 952 => "0011111110011100", 953 => "0011111110011110",
954 => "0011111110100001", 955 => "0011111110100100", 956 => "0011111110100110",
957 => "0011111110101001", 958 => "0011111110101100", 959 => "0011111110101110",
960 => "0011111110110001", 961 => "0011111110110011", 962 => "0011111110110101",
963 => "0011111110111000", 964 => "0011111110111010", 965 => "0011111110111100",
966 => "0011111110111111", 967 => "0011111111000001", 968 => "0011111111000011",
969 => "0011111111000101", 970 => "0011111111000111", 971 => "0011111111001001",
972 => "0011111111001011", 973 => "0011111111001101", 974 => "0011111111001111",
975 => "0011111111010001", 976 => "0011111111010011", 977 => "0011111111010101",
978 => "0011111111010111", 979 => "0011111111011000", 980 => "0011111111011010",
981 => "0011111111011100", 982 => "0011111111011110", 983 => "0011111111011111",
984 => "0011111111100001", 985 => "0011111111100010", 986 => "0011111111100100",
987 => "0011111111100101", 988 => "0011111111100111", 989 => "0011111111101000",
990 => "0011111111101001", 991 => "0011111111101011", 992 => "0011111111101100",
993 => "0011111111101101", 994 => "0011111111101110", 995 => "0011111111101111",
996 => "0011111111110000", 997 => "0011111111110001", 998 => "0011111111110010",
999 => "0011111111110011", 1000 => "0011111111110100", 1001 => "0011111111110101",
1002 => "0011111111110110", 1003 => "0011111111110111", 1004 => "0011111111111000",
1005 to 1006=> "0011111111111001", 1007 => "0011111111111010", 1008 to 1009=> "0011111111111011",
1010 to 1011=> "0011111111111100", 1012 to 1013=> "0011111111111101", 1014 to 1016=> "0011111111111110",
1017 to 1023=> "0011111111111111", 1024 => "0100000000000000", 1025 to 1031=> "0011111111111111",
1032 to 1034=> "0011111111111110", 1035 to 1036=> "0011111111111101", 1037 to 1038=> "0011111111111100",
1039 to 1040=> "0011111111111011", 1041 => "0011111111111010", 1042 to 1043=> "0011111111111001",
1044 => "0011111111111000", 1045 => "0011111111110111", 1046 => "0011111111110110",
1047 => "0011111111110101", 1048 => "0011111111110100", 1049 => "0011111111110011",
1050 => "0011111111110010", 1051 => "0011111111110001", 1052 => "0011111111110000",
1053 => "0011111111101111", 1054 => "0011111111101110", 1055 => "0011111111101101",
1056 => "0011111111101100", 1057 => "0011111111101011", 1058 => "0011111111101001",
1059 => "0011111111101000", 1060 => "0011111111100111", 1061 => "0011111111100101",
1062 => "0011111111100100", 1063 => "0011111111100010", 1064 => "0011111111100001",
1065 => "0011111111011111", 1066 => "0011111111011110", 1067 => "0011111111011100",
1068 => "0011111111011010", 1069 => "0011111111011000", 1070 => "0011111111010111",
1071 => "0011111111010101", 1072 => "0011111111010011", 1073 => "0011111111010001",
1074 => "0011111111001111", 1075 => "0011111111001101", 1076 => "0011111111001011",
1077 => "0011111111001001", 1078 => "0011111111000111", 1079 => "0011111111000101",
1080 => "0011111111000011", 1081 => "0011111111000001", 1082 => "0011111110111111",
1083 => "0011111110111100", 1084 => "0011111110111010", 1085 => "0011111110111000",
1086 => "0011111110110101", 1087 => "0011111110110011", 1088 => "0011111110110001",
1089 => "0011111110101110", 1090 => "0011111110101100", 1091 => "0011111110101001",
1092 => "0011111110100110", 1093 => "0011111110100100", 1094 => "0011111110100001",
1095 => "0011111110011110", 1096 => "0011111110011100", 1097 => "0011111110011001",
1098 => "0011111110010110", 1099 => "0011111110010011", 1100 => "0011111110010000",
1101 => "0011111110001101", 1102 => "0011111110001010", 1103 => "0011111110000111",
1104 => "0011111110000100", 1105 => "0011111110000001", 1106 => "0011111101111110",
1107 => "0011111101111011", 1108 => "0011111101111000", 1109 => "0011111101110100",
1110 => "0011111101110001", 1111 => "0011111101101110", 1112 => "0011111101101010",
1113 => "0011111101100111", 1114 => "0011111101100100", 1115 => "0011111101100000",
1116 => "0011111101011101", 1117 => "0011111101011001", 1118 => "0011111101010101",
1119 => "0011111101010010", 1120 => "0011111101001110", 1121 => "0011111101001010",
1122 => "0011111101000111", 1123 => "0011111101000011", 1124 => "0011111100111111",
1125 => "0011111100111011", 1126 => "0011111100110111", 1127 => "0011111100110011",
1128 => "0011111100101111", 1129 => "0011111100101011", 1130 => "0011111100100111",
1131 => "0011111100100011", 1132 => "0011111100011111", 1133 => "0011111100011011",
1134 => "0011111100010111", 1135 => "0011111100010011", 1136 => "0011111100001110",
1137 => "0011111100001010", 1138 => "0011111100000110", 1139 => "0011111100000001",
1140 => "0011111011111101", 1141 => "0011111011111000", 1142 => "0011111011110100",
1143 => "0011111011101111", 1144 => "0011111011101011", 1145 => "0011111011100110",
1146 => "0011111011100001", 1147 => "0011111011011101", 1148 => "0011111011011000",
1149 => "0011111011010011", 1150 => "0011111011001110", 1151 => "0011111011001010",
1152 => "0011111011000101", 1153 => "0011111011000000", 1154 => "0011111010111011",
1155 => "0011111010110110", 1156 => "0011111010110001", 1157 => "0011111010101100",
1158 => "0011111010100111", 1159 => "0011111010100001", 1160 => "0011111010011100",
1161 => "0011111010010111", 1162 => "0011111010010010", 1163 => "0011111010001100",
1164 => "0011111010000111", 1165 => "0011111010000010", 1166 => "0011111001111100",
1167 => "0011111001110111", 1168 => "0011111001110001", 1169 => "0011111001101100",
1170 => "0011111001100110", 1171 => "0011111001100001", 1172 => "0011111001011011",
1173 => "0011111001010101", 1174 => "0011111001010000", 1175 => "0011111001001010",
1176 => "0011111001000100", 1177 => "0011111000111110", 1178 => "0011111000111000",
1179 => "0011111000110011", 1180 => "0011111000101101", 1181 => "0011111000100111",
1182 => "0011111000100001", 1183 => "0011111000011011", 1184 => "0011111000010100",
1185 => "0011111000001110", 1186 => "0011111000001000", 1187 => "0011111000000010",
1188 => "0011110111111100", 1189 => "0011110111110101", 1190 => "0011110111101111",
1191 => "0011110111101001", 1192 => "0011110111100010", 1193 => "0011110111011100",
1194 => "0011110111010110", 1195 => "0011110111001111", 1196 => "0011110111001001",
1197 => "0011110111000010", 1198 => "0011110110111011", 1199 => "0011110110110101",
1200 => "0011110110101110", 1201 => "0011110110100111", 1202 => "0011110110100001",
1203 => "0011110110011010", 1204 => "0011110110010011", 1205 => "0011110110001100",
1206 => "0011110110000101", 1207 => "0011110101111110", 1208 => "0011110101110111",
1209 => "0011110101110000", 1210 => "0011110101101001", 1211 => "0011110101100010",
1212 => "0011110101011011", 1213 => "0011110101010100", 1214 => "0011110101001101",
1215 => "0011110101000101", 1216 => "0011110100111110", 1217 => "0011110100110111",
1218 => "0011110100101111", 1219 => "0011110100101000", 1220 => "0011110100100001",
1221 => "0011110100011001", 1222 => "0011110100010010", 1223 => "0011110100001010",
1224 => "0011110100000010", 1225 => "0011110011111011", 1226 => "0011110011110011",
1227 => "0011110011101100", 1228 => "0011110011100100", 1229 => "0011110011011100",
1230 => "0011110011010100", 1231 => "0011110011001100", 1232 => "0011110011000101",
1233 => "0011110010111101", 1234 => "0011110010110101", 1235 => "0011110010101101",
1236 => "0011110010100101", 1237 => "0011110010011101", 1238 => "0011110010010101",
1239 => "0011110010001100", 1240 => "0011110010000100", 1241 => "0011110001111100",
1242 => "0011110001110100", 1243 => "0011110001101100", 1244 => "0011110001100011",
1245 => "0011110001011011", 1246 => "0011110001010011", 1247 => "0011110001001010",
1248 => "0011110001000010", 1249 => "0011110000111001", 1250 => "0011110000110001",
1251 => "0011110000101000", 1252 => "0011110000100000", 1253 => "0011110000010111",
1254 => "0011110000001110", 1255 => "0011110000000110", 1256 => "0011101111111101",
1257 => "0011101111110100", 1258 => "0011101111101011", 1259 => "0011101111100010",
1260 => "0011101111011010", 1261 => "0011101111010001", 1262 => "0011101111001000",
1263 => "0011101110111111", 1264 => "0011101110110110", 1265 => "0011101110101101",
1266 => "0011101110100011", 1267 => "0011101110011010", 1268 => "0011101110010001",
1269 => "0011101110001000", 1270 => "0011101101111111", 1271 => "0011101101110101",
1272 => "0011101101101100", 1273 => "0011101101100011", 1274 => "0011101101011001",
1275 => "0011101101010000", 1276 => "0011101101000111", 1277 => "0011101100111101",
1278 => "0011101100110100", 1279 => "0011101100101010", 1280 => "0011101100100000",
1281 => "0011101100010111", 1282 => "0011101100001101", 1283 => "0011101100000011",
1284 => "0011101011111010", 1285 => "0011101011110000", 1286 => "0011101011100110",
1287 => "0011101011011100", 1288 => "0011101011010010", 1289 => "0011101011001000",
1290 => "0011101010111110", 1291 => "0011101010110100", 1292 => "0011101010101010",
1293 => "0011101010100000", 1294 => "0011101010010110", 1295 => "0011101010001100",
1296 => "0011101010000010", 1297 => "0011101001111000", 1298 => "0011101001101101",
1299 => "0011101001100011", 1300 => "0011101001011001", 1301 => "0011101001001111",
1302 => "0011101001000100", 1303 => "0011101000111010", 1304 => "0011101000101111",
1305 => "0011101000100101", 1306 => "0011101000011010", 1307 => "0011101000010000",
1308 => "0011101000000101", 1309 => "0011100111111011", 1310 => "0011100111110000",
1311 => "0011100111100101", 1312 => "0011100111011010", 1313 => "0011100111010000",
1314 => "0011100111000101", 1315 => "0011100110111010", 1316 => "0011100110101111",
1317 => "0011100110100100", 1318 => "0011100110011001", 1319 => "0011100110001110",
1320 => "0011100110000011", 1321 => "0011100101111000", 1322 => "0011100101101101",
1323 => "0011100101100010", 1324 => "0011100101010111", 1325 => "0011100101001100",
1326 => "0011100101000001", 1327 => "0011100100110101", 1328 => "0011100100101010",
1329 => "0011100100011111", 1330 => "0011100100010011", 1331 => "0011100100001000",
1332 => "0011100011111101", 1333 => "0011100011110001", 1334 => "0011100011100110",
1335 => "0011100011011010", 1336 => "0011100011001111", 1337 => "0011100011000011",
1338 => "0011100010110111", 1339 => "0011100010101100", 1340 => "0011100010100000",
1341 => "0011100010010100", 1342 => "0011100010001001", 1343 => "0011100001111101",
1344 => "0011100001110001", 1345 => "0011100001100101", 1346 => "0011100001011001",
1347 => "0011100001001101", 1348 => "0011100001000001", 1349 => "0011100000110101",
1350 => "0011100000101001", 1351 => "0011100000011101", 1352 => "0011100000010001",
1353 => "0011100000000101", 1354 => "0011011111111001", 1355 => "0011011111101101",
1356 => "0011011111100000", 1357 => "0011011111010100", 1358 => "0011011111001000",
1359 => "0011011110111011", 1360 => "0011011110101111", 1361 => "0011011110100011",
1362 => "0011011110010110", 1363 => "0011011110001010", 1364 => "0011011101111101",
1365 => "0011011101110001", 1366 => "0011011101100100", 1367 => "0011011101010111",
1368 => "0011011101001011", 1369 => "0011011100111110", 1370 => "0011011100110001",
1371 => "0011011100100101", 1372 => "0011011100011000", 1373 => "0011011100001011",
1374 => "0011011011111110", 1375 => "0011011011110001", 1376 => "0011011011100101",
1377 => "0011011011011000", 1378 => "0011011011001011", 1379 => "0011011010111110",
1380 => "0011011010110001", 1381 => "0011011010100100", 1382 => "0011011010010110",
1383 => "0011011010001001", 1384 => "0011011001111100", 1385 => "0011011001101111",
1386 => "0011011001100010", 1387 => "0011011001010100", 1388 => "0011011001000111",
1389 => "0011011000111010", 1390 => "0011011000101100", 1391 => "0011011000011111",
1392 => "0011011000010010", 1393 => "0011011000000100", 1394 => "0011010111110111",
1395 => "0011010111101001", 1396 => "0011010111011100", 1397 => "0011010111001110",
1398 => "0011010111000000", 1399 => "0011010110110011", 1400 => "0011010110100101",
1401 => "0011010110010111", 1402 => "0011010110001001", 1403 => "0011010101111100",
1404 => "0011010101101110", 1405 => "0011010101100000", 1406 => "0011010101010010",
1407 => "0011010101000100", 1408 => "0011010100110110", 1409 => "0011010100101000",
1410 => "0011010100011010", 1411 => "0011010100001100", 1412 => "0011010011111110",
1413 => "0011010011110000", 1414 => "0011010011100010", 1415 => "0011010011010100",
1416 => "0011010011000110", 1417 => "0011010010110111", 1418 => "0011010010101001",
1419 => "0011010010011011", 1420 => "0011010010001100", 1421 => "0011010001111110",
1422 => "0011010001110000", 1423 => "0011010001100001", 1424 => "0011010001010011",
1425 => "0011010001000100", 1426 => "0011010000110110", 1427 => "0011010000100111",
1428 => "0011010000011001", 1429 => "0011010000001010", 1430 => "0011001111111011",
1431 => "0011001111101101", 1432 => "0011001111011110", 1433 => "0011001111001111",
1434 => "0011001111000001", 1435 => "0011001110110010", 1436 => "0011001110100011",
1437 => "0011001110010100", 1438 => "0011001110000101", 1439 => "0011001101110110",
1440 => "0011001101100111", 1441 => "0011001101011000", 1442 => "0011001101001001",
1443 => "0011001100111010", 1444 => "0011001100101011", 1445 => "0011001100011100",
1446 => "0011001100001101", 1447 => "0011001011111110", 1448 => "0011001011101110",
1449 => "0011001011011111", 1450 => "0011001011010000", 1451 => "0011001011000001",
1452 => "0011001010110001", 1453 => "0011001010100010", 1454 => "0011001010010011",
1455 => "0011001010000011", 1456 => "0011001001110100", 1457 => "0011001001100100",
1458 => "0011001001010101", 1459 => "0011001001000101", 1460 => "0011001000110110",
1461 => "0011001000100110", 1462 => "0011001000010110", 1463 => "0011001000000111",
1464 => "0011000111110111", 1465 => "0011000111100111", 1466 => "0011000111011000",
1467 => "0011000111001000", 1468 => "0011000110111000", 1469 => "0011000110101000",
1470 => "0011000110011000", 1471 => "0011000110001000", 1472 => "0011000101111001",
1473 => "0011000101101001", 1474 => "0011000101011001", 1475 => "0011000101001001",
1476 => "0011000100111000", 1477 => "0011000100101000", 1478 => "0011000100011000",
1479 => "0011000100001000", 1480 => "0011000011111000", 1481 => "0011000011101000",
1482 => "0011000011011000", 1483 => "0011000011000111", 1484 => "0011000010110111",
1485 => "0011000010100111", 1486 => "0011000010010110", 1487 => "0011000010000110",
1488 => "0011000001110110", 1489 => "0011000001100101", 1490 => "0011000001010101",
1491 => "0011000001000100", 1492 => "0011000000110100", 1493 => "0011000000100011",
1494 => "0011000000010011", 1495 => "0011000000000010", 1496 => "0010111111110001",
1497 => "0010111111100001", 1498 => "0010111111010000", 1499 => "0010111110111111",
1500 => "0010111110101111", 1501 => "0010111110011110", 1502 => "0010111110001101",
1503 => "0010111101111100", 1504 => "0010111101101011", 1505 => "0010111101011010",
1506 => "0010111101001001", 1507 => "0010111100111000", 1508 => "0010111100101000",
1509 => "0010111100010110", 1510 => "0010111100000101", 1511 => "0010111011110100",
1512 => "0010111011100011", 1513 => "0010111011010010", 1514 => "0010111011000001",
1515 => "0010111010110000", 1516 => "0010111010011111", 1517 => "0010111010001101",
1518 => "0010111001111100", 1519 => "0010111001101011", 1520 => "0010111001011010",
1521 => "0010111001001000", 1522 => "0010111000110111", 1523 => "0010111000100101",
1524 => "0010111000010100", 1525 => "0010111000000011", 1526 => "0010110111110001",
1527 => "0010110111100000", 1528 => "0010110111001110", 1529 => "0010110110111100",
1530 => "0010110110101011", 1531 => "0010110110011001", 1532 => "0010110110001000",
1533 => "0010110101110110", 1534 => "0010110101100100", 1535 => "0010110101010010",
1536 => "0010110101000001", 1537 => "0010110100101111", 1538 => "0010110100011101",
1539 => "0010110100001011", 1540 => "0010110011111001", 1541 => "0010110011101000",
1542 => "0010110011010110", 1543 => "0010110011000100", 1544 => "0010110010110010",
1545 => "0010110010100000", 1546 => "0010110010001110", 1547 => "0010110001111100",
1548 => "0010110001101010", 1549 => "0010110001010111", 1550 => "0010110001000101",
1551 => "0010110000110011", 1552 => "0010110000100001", 1553 => "0010110000001111",
1554 => "0010101111111100", 1555 => "0010101111101010", 1556 => "0010101111011000",
1557 => "0010101111000110", 1558 => "0010101110110011", 1559 => "0010101110100001",
1560 => "0010101110001110", 1561 => "0010101101111100", 1562 => "0010101101101010",
1563 => "0010101101010111", 1564 => "0010101101000101", 1565 => "0010101100110010",
1566 => "0010101100100000", 1567 => "0010101100001101", 1568 => "0010101011111010",
1569 => "0010101011101000", 1570 => "0010101011010101", 1571 => "0010101011000010",
1572 => "0010101010110000", 1573 => "0010101010011101", 1574 => "0010101010001010",
1575 => "0010101001110111", 1576 => "0010101001100101", 1577 => "0010101001010010",
1578 => "0010101000111111", 1579 => "0010101000101100", 1580 => "0010101000011001",
1581 => "0010101000000110", 1582 => "0010100111110011", 1583 => "0010100111100000",
1584 => "0010100111001101", 1585 => "0010100110111010", 1586 => "0010100110100111",
1587 => "0010100110010100", 1588 => "0010100110000001", 1589 => "0010100101101110",
1590 => "0010100101011010", 1591 => "0010100101000111", 1592 => "0010100100110100",
1593 => "0010100100100001", 1594 => "0010100100001110", 1595 => "0010100011111010",
1596 => "0010100011100111", 1597 => "0010100011010100", 1598 => "0010100011000000",
1599 => "0010100010101101", 1600 => "0010100010011001", 1601 => "0010100010000110",
1602 => "0010100001110010", 1603 => "0010100001011111", 1604 => "0010100001001011",
1605 => "0010100000111000", 1606 => "0010100000100100", 1607 => "0010100000010001",
1608 => "0010011111111101", 1609 => "0010011111101010", 1610 => "0010011111010110",
1611 => "0010011111000010", 1612 => "0010011110101111", 1613 => "0010011110011011",
1614 => "0010011110000111", 1615 => "0010011101110011", 1616 => "0010011101011111",
1617 => "0010011101001100", 1618 => "0010011100111000", 1619 => "0010011100100100",
1620 => "0010011100010000", 1621 => "0010011011111100", 1622 => "0010011011101000",
1623 => "0010011011010100", 1624 => "0010011011000000", 1625 => "0010011010101100",
1626 => "0010011010011000", 1627 => "0010011010000100", 1628 => "0010011001110000",
1629 => "0010011001011100", 1630 => "0010011001001000", 1631 => "0010011000110100",
1632 => "0010011000011111", 1633 => "0010011000001011", 1634 => "0010010111110111",
1635 => "0010010111100011", 1636 => "0010010111001111", 1637 => "0010010110111010",
1638 => "0010010110100110", 1639 => "0010010110010010", 1640 => "0010010101111101",
1641 => "0010010101101001", 1642 => "0010010101010100", 1643 => "0010010101000000",
1644 => "0010010100101100", 1645 => "0010010100010111", 1646 => "0010010100000011",
1647 => "0010010011101110", 1648 => "0010010011011010", 1649 => "0010010011000101",
1650 => "0010010010110000", 1651 => "0010010010011100", 1652 => "0010010010000111",
1653 => "0010010001110011", 1654 => "0010010001011110", 1655 => "0010010001001001",
1656 => "0010010000110100", 1657 => "0010010000100000", 1658 => "0010010000001011",
1659 => "0010001111110110", 1660 => "0010001111100001", 1661 => "0010001111001101",
1662 => "0010001110111000", 1663 => "0010001110100011", 1664 => "0010001110001110",
1665 => "0010001101111001", 1666 => "0010001101100100", 1667 => "0010001101001111",
1668 => "0010001100111010", 1669 => "0010001100100101", 1670 => "0010001100010000",
1671 => "0010001011111011", 1672 => "0010001011100110", 1673 => "0010001011010001",
1674 => "0010001010111100", 1675 => "0010001010100111", 1676 => "0010001010010010",
1677 => "0010001001111101", 1678 => "0010001001100111", 1679 => "0010001001010010",
1680 => "0010001000111101", 1681 => "0010001000101000", 1682 => "0010001000010010",
1683 => "0010000111111101", 1684 => "0010000111101000", 1685 => "0010000111010010",
1686 => "0010000110111101", 1687 => "0010000110101000", 1688 => "0010000110010010",
1689 => "0010000101111101", 1690 => "0010000101101000", 1691 => "0010000101010010",
1692 => "0010000100111101", 1693 => "0010000100100111", 1694 => "0010000100010010",
1695 => "0010000011111100", 1696 => "0010000011100111", 1697 => "0010000011010001",
1698 => "0010000010111011", 1699 => "0010000010100110", 1700 => "0010000010010000",
1701 => "0010000001111011", 1702 => "0010000001100101", 1703 => "0010000001001111",
1704 => "0010000000111001", 1705 => "0010000000100100", 1706 => "0010000000001110",
1707 => "0001111111111000", 1708 => "0001111111100010", 1709 => "0001111111001101",
1710 => "0001111110110111", 1711 => "0001111110100001", 1712 => "0001111110001011",
1713 => "0001111101110101", 1714 => "0001111101011111", 1715 => "0001111101001001",
1716 => "0001111100110100", 1717 => "0001111100011110", 1718 => "0001111100001000",
1719 => "0001111011110010", 1720 => "0001111011011100", 1721 => "0001111011000110",
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2505 => "1101011010111000", 2506 => "1101011010100101", 2507 => "1101011010010001",
2508 => "1101011001111110", 2509 => "1101011001101011", 2510 => "1101011001011000",
2511 => "1101011001000101", 2512 => "1101011000110010", 2513 => "1101011000011111",
2514 => "1101011000001100", 2515 => "1101010111111001", 2516 => "1101010111100110",
2517 => "1101010111010011", 2518 => "1101010111000000", 2519 => "1101010110101101",
2520 => "1101010110011010", 2521 => "1101010110001000", 2522 => "1101010101110101",
2523 => "1101010101100010", 2524 => "1101010101001111", 2525 => "1101010100111101",
2526 => "1101010100101010", 2527 => "1101010100010111", 2528 => "1101010100000101",
2529 => "1101010011110010", 2530 => "1101010011011111", 2531 => "1101010011001101",
2532 => "1101010010111010", 2533 => "1101010010101000", 2534 => "1101010010010101",
2535 => "1101010010000011", 2536 => "1101010001110001", 2537 => "1101010001011110",
2538 => "1101010001001100", 2539 => "1101010000111001", 2540 => "1101010000100111",
2541 => "1101010000010101", 2542 => "1101010000000011", 2543 => "1101001111110000",
2544 => "1101001111011110", 2545 => "1101001111001100", 2546 => "1101001110111010",
2547 => "1101001110101000", 2548 => "1101001110010101", 2549 => "1101001110000011",
2550 => "1101001101110001", 2551 => "1101001101011111", 2552 => "1101001101001101",
2553 => "1101001100111011", 2554 => "1101001100101001", 2555 => "1101001100010111",
2556 => "1101001100000110", 2557 => "1101001011110100", 2558 => "1101001011100010",
2559 => "1101001011010000", 2560 => "1101001010111110", 2561 => "1101001010101101",
2562 => "1101001010011011", 2563 => "1101001010001001", 2564 => "1101001001110111",
2565 => "1101001001100110", 2566 => "1101001001010100", 2567 => "1101001001000011",
2568 => "1101001000110001", 2569 => "1101001000011111", 2570 => "1101001000001110",
2571 => "1101000111111100", 2572 => "1101000111101011", 2573 => "1101000111011010",
2574 => "1101000111001000", 2575 => "1101000110110111", 2576 => "1101000110100101",
2577 => "1101000110010100", 2578 => "1101000110000011", 2579 => "1101000101110010",
2580 => "1101000101100000", 2581 => "1101000101001111", 2582 => "1101000100111110",
2583 => "1101000100101101", 2584 => "1101000100011100", 2585 => "1101000100001011",
2586 => "1101000011111010", 2587 => "1101000011101001", 2588 => "1101000011010111",
2589 => "1101000011000111", 2590 => "1101000010110110", 2591 => "1101000010100101",
2592 => "1101000010010100", 2593 => "1101000010000011", 2594 => "1101000001110010",
2595 => "1101000001100001", 2596 => "1101000001010000", 2597 => "1101000001000000",
2598 => "1101000000101111", 2599 => "1101000000011110", 2600 => "1101000000001110",
2601 => "1100111111111101", 2602 => "1100111111101100", 2603 => "1100111111011100",
2604 => "1100111111001011", 2605 => "1100111110111011", 2606 => "1100111110101010",
2607 => "1100111110011010", 2608 => "1100111110001001", 2609 => "1100111101111001",
2610 => "1100111101101001", 2611 => "1100111101011000", 2612 => "1100111101001000",
2613 => "1100111100111000", 2614 => "1100111100100111", 2615 => "1100111100010111",
2616 => "1100111100000111", 2617 => "1100111011110111", 2618 => "1100111011100111",
2619 => "1100111011010111", 2620 => "1100111011000111", 2621 => "1100111010110110",
2622 => "1100111010100110", 2623 => "1100111010010110", 2624 => "1100111010000110",
2625 => "1100111001110111", 2626 => "1100111001100111", 2627 => "1100111001010111",
2628 => "1100111001000111", 2629 => "1100111000110111", 2630 => "1100111000100111",
2631 => "1100111000011000", 2632 => "1100111000001000", 2633 => "1100110111111000",
2634 => "1100110111101001", 2635 => "1100110111011001", 2636 => "1100110111001001",
2637 => "1100110110111010", 2638 => "1100110110101010", 2639 => "1100110110011011",
2640 => "1100110110001011", 2641 => "1100110101111100", 2642 => "1100110101101100",
2643 => "1100110101011101", 2644 => "1100110101001110", 2645 => "1100110100111110",
2646 => "1100110100101111", 2647 => "1100110100100000", 2648 => "1100110100010001",
2649 => "1100110100000001", 2650 => "1100110011110010", 2651 => "1100110011100011",
2652 => "1100110011010100", 2653 => "1100110011000101", 2654 => "1100110010110110",
2655 => "1100110010100111", 2656 => "1100110010011000", 2657 => "1100110010001001",
2658 => "1100110001111010", 2659 => "1100110001101011", 2660 => "1100110001011100",
2661 => "1100110001001101", 2662 => "1100110000111110", 2663 => "1100110000110000",
2664 => "1100110000100001", 2665 => "1100110000010010", 2666 => "1100110000000100",
2667 => "1100101111110101", 2668 => "1100101111100110", 2669 => "1100101111011000",
2670 => "1100101111001001", 2671 => "1100101110111011", 2672 => "1100101110101100",
2673 => "1100101110011110", 2674 => "1100101110001111", 2675 => "1100101110000001",
2676 => "1100101101110011", 2677 => "1100101101100100", 2678 => "1100101101010110",
2679 => "1100101101001000", 2680 => "1100101100111001", 2681 => "1100101100101011",
2682 => "1100101100011101", 2683 => "1100101100001111", 2684 => "1100101100000001",
2685 => "1100101011110011", 2686 => "1100101011100101", 2687 => "1100101011010111",
2688 => "1100101011001001", 2689 => "1100101010111011", 2690 => "1100101010101101",
2691 => "1100101010011111", 2692 => "1100101010010001", 2693 => "1100101010000011",
2694 => "1100101001110110", 2695 => "1100101001101000", 2696 => "1100101001011010",
2697 => "1100101001001100", 2698 => "1100101000111111", 2699 => "1100101000110001",
2700 => "1100101000100011", 2701 => "1100101000010110", 2702 => "1100101000001000",
2703 => "1100100111111011", 2704 => "1100100111101101", 2705 => "1100100111100000",
2706 => "1100100111010011", 2707 => "1100100111000101", 2708 => "1100100110111000",
2709 => "1100100110101011", 2710 => "1100100110011101", 2711 => "1100100110010000",
2712 => "1100100110000011", 2713 => "1100100101110110", 2714 => "1100100101101001",
2715 => "1100100101011011", 2716 => "1100100101001110", 2717 => "1100100101000001",
2718 => "1100100100110100", 2719 => "1100100100100111", 2720 => "1100100100011010",
2721 => "1100100100001110", 2722 => "1100100100000001", 2723 => "1100100011110100",
2724 => "1100100011100111", 2725 => "1100100011011010", 2726 => "1100100011001110",
2727 => "1100100011000001", 2728 => "1100100010110100", 2729 => "1100100010101000",
2730 => "1100100010011011", 2731 => "1100100010001110", 2732 => "1100100010000010",
2733 => "1100100001110101", 2734 => "1100100001101001", 2735 => "1100100001011100",
2736 => "1100100001010000", 2737 => "1100100001000100", 2738 => "1100100000110111",
2739 => "1100100000101011", 2740 => "1100100000011111", 2741 => "1100100000010010",
2742 => "1100100000000110", 2743 => "1100011111111010", 2744 => "1100011111101110",
2745 => "1100011111100010", 2746 => "1100011111010110", 2747 => "1100011111001010",
2748 => "1100011110111110", 2749 => "1100011110110010", 2750 => "1100011110100110",
2751 => "1100011110011010", 2752 => "1100011110001110", 2753 => "1100011110000010",
2754 => "1100011101110110", 2755 => "1100011101101011", 2756 => "1100011101011111",
2757 => "1100011101010011", 2758 => "1100011101001000", 2759 => "1100011100111100",
2760 => "1100011100110000", 2761 => "1100011100100101", 2762 => "1100011100011001",
2763 => "1100011100001110", 2764 => "1100011100000010", 2765 => "1100011011110111",
2766 => "1100011011101100", 2767 => "1100011011100000", 2768 => "1100011011010101",
2769 => "1100011011001010", 2770 => "1100011010111110", 2771 => "1100011010110011",
2772 => "1100011010101000", 2773 => "1100011010011101", 2774 => "1100011010010010",
2775 => "1100011010000111", 2776 => "1100011001111100", 2777 => "1100011001110001",
2778 => "1100011001100110", 2779 => "1100011001011011", 2780 => "1100011001010000",
2781 => "1100011001000101", 2782 => "1100011000111010", 2783 => "1100011000101111",
2784 => "1100011000100101", 2785 => "1100011000011010", 2786 => "1100011000001111",
2787 => "1100011000000100", 2788 => "1100010111111010", 2789 => "1100010111101111",
2790 => "1100010111100101", 2791 => "1100010111011010", 2792 => "1100010111010000",
2793 => "1100010111000101", 2794 => "1100010110111011", 2795 => "1100010110110000",
2796 => "1100010110100110", 2797 => "1100010110011100", 2798 => "1100010110010010",
2799 => "1100010110000111", 2800 => "1100010101111101", 2801 => "1100010101110011",
2802 => "1100010101101001", 2803 => "1100010101011111", 2804 => "1100010101010101",
2805 => "1100010101001011", 2806 => "1100010101000001", 2807 => "1100010100110111",
2808 => "1100010100101101", 2809 => "1100010100100011", 2810 => "1100010100011001",
2811 => "1100010100001111", 2812 => "1100010100000101", 2813 => "1100010011111100",
2814 => "1100010011110010", 2815 => "1100010011101000", 2816 => "1100010011011111",
2817 => "1100010011010101", 2818 => "1100010011001011", 2819 => "1100010011000010",
2820 => "1100010010111000", 2821 => "1100010010101111", 2822 => "1100010010100110",
2823 => "1100010010011100", 2824 => "1100010010010011", 2825 => "1100010010001010",
2826 => "1100010010000000", 2827 => "1100010001110111", 2828 => "1100010001101110",
2829 => "1100010001100101", 2830 => "1100010001011100", 2831 => "1100010001010010",
2832 => "1100010001001001", 2833 => "1100010001000000", 2834 => "1100010000110111",
2835 => "1100010000101110", 2836 => "1100010000100101", 2837 => "1100010000011101",
2838 => "1100010000010100", 2839 => "1100010000001011", 2840 => "1100010000000010",
2841 => "1100001111111001", 2842 => "1100001111110001", 2843 => "1100001111101000",
2844 => "1100001111011111", 2845 => "1100001111010111", 2846 => "1100001111001110",
2847 => "1100001111000110", 2848 => "1100001110111101", 2849 => "1100001110110101",
2850 => "1100001110101100", 2851 => "1100001110100100", 2852 => "1100001110011100",
2853 => "1100001110010011", 2854 => "1100001110001011", 2855 => "1100001110000011",
2856 => "1100001101111011", 2857 => "1100001101110011", 2858 => "1100001101101010",
2859 => "1100001101100010", 2860 => "1100001101011010", 2861 => "1100001101010010",
2862 => "1100001101001010", 2863 => "1100001101000010", 2864 => "1100001100111010",
2865 => "1100001100110011", 2866 => "1100001100101011", 2867 => "1100001100100011",
2868 => "1100001100011011", 2869 => "1100001100010011", 2870 => "1100001100001100",
2871 => "1100001100000100", 2872 => "1100001011111101", 2873 => "1100001011110101",
2874 => "1100001011101101", 2875 => "1100001011100110", 2876 => "1100001011011110",
2877 => "1100001011010111", 2878 => "1100001011010000", 2879 => "1100001011001000",
2880 => "1100001011000001", 2881 => "1100001010111010", 2882 => "1100001010110010",
2883 => "1100001010101011", 2884 => "1100001010100100", 2885 => "1100001010011101",
2886 => "1100001010010110", 2887 => "1100001010001111", 2888 => "1100001010001000",
2889 => "1100001010000001", 2890 => "1100001001111010", 2891 => "1100001001110011",
2892 => "1100001001101100", 2893 => "1100001001100101", 2894 => "1100001001011110",
2895 => "1100001001011000", 2896 => "1100001001010001", 2897 => "1100001001001010",
2898 => "1100001001000100", 2899 => "1100001000111101", 2900 => "1100001000110110",
2901 => "1100001000110000", 2902 => "1100001000101001", 2903 => "1100001000100011",
2904 => "1100001000011101", 2905 => "1100001000010110", 2906 => "1100001000010000",
2907 => "1100001000001010", 2908 => "1100001000000011", 2909 => "1100000111111101",
2910 => "1100000111110111", 2911 => "1100000111110001", 2912 => "1100000111101011",
2913 => "1100000111100100", 2914 => "1100000111011110", 2915 => "1100000111011000",
2916 => "1100000111010010", 2917 => "1100000111001100", 2918 => "1100000111000111",
2919 => "1100000111000001", 2920 => "1100000110111011", 2921 => "1100000110110101",
2922 => "1100000110101111", 2923 => "1100000110101010", 2924 => "1100000110100100",
2925 => "1100000110011110", 2926 => "1100000110011001", 2927 => "1100000110010011",
2928 => "1100000110001110", 2929 => "1100000110001000", 2930 => "1100000110000011",
2931 => "1100000101111101", 2932 => "1100000101111000", 2933 => "1100000101110011",
2934 => "1100000101101101", 2935 => "1100000101101000", 2936 => "1100000101100011",
2937 => "1100000101011110", 2938 => "1100000101011000", 2939 => "1100000101010011",
2940 => "1100000101001110", 2941 => "1100000101001001", 2942 => "1100000101000100",
2943 => "1100000100111111", 2944 => "1100000100111010", 2945 => "1100000100110101",
2946 => "1100000100110001", 2947 => "1100000100101100", 2948 => "1100000100100111",
2949 => "1100000100100010", 2950 => "1100000100011110", 2951 => "1100000100011001",
2952 => "1100000100010100", 2953 => "1100000100010000", 2954 => "1100000100001011",
2955 => "1100000100000111", 2956 => "1100000100000010", 2957 => "1100000011111110",
2958 => "1100000011111001", 2959 => "1100000011110101", 2960 => "1100000011110001",
2961 => "1100000011101100", 2962 => "1100000011101000", 2963 => "1100000011100100",
2964 => "1100000011100000", 2965 => "1100000011011100", 2966 => "1100000011011000",
2967 => "1100000011010100", 2968 => "1100000011010000", 2969 => "1100000011001100",
2970 => "1100000011001000", 2971 => "1100000011000100", 2972 => "1100000011000000",
2973 => "1100000010111100", 2974 => "1100000010111000", 2975 => "1100000010110101",
2976 => "1100000010110001", 2977 => "1100000010101101", 2978 => "1100000010101010",
2979 => "1100000010100110", 2980 => "1100000010100010", 2981 => "1100000010011111",
2982 => "1100000010011011", 2983 => "1100000010011000", 2984 => "1100000010010101",
2985 => "1100000010010001", 2986 => "1100000010001110", 2987 => "1100000010001011",
2988 => "1100000010000111", 2989 => "1100000010000100", 2990 => "1100000010000001",
2991 => "1100000001111110", 2992 => "1100000001111011", 2993 => "1100000001111000",
2994 => "1100000001110101", 2995 => "1100000001110010", 2996 => "1100000001101111",
2997 => "1100000001101100", 2998 => "1100000001101001", 2999 => "1100000001100110",
3000 => "1100000001100011", 3001 => "1100000001100001", 3002 => "1100000001011110",
3003 => "1100000001011011", 3004 => "1100000001011001", 3005 => "1100000001010110",
3006 => "1100000001010011", 3007 => "1100000001010001", 3008 => "1100000001001110",
3009 => "1100000001001100", 3010 => "1100000001001010", 3011 => "1100000001000111",
3012 => "1100000001000101", 3013 => "1100000001000011", 3014 => "1100000001000000",
3015 => "1100000000111110", 3016 => "1100000000111100", 3017 => "1100000000111010",
3018 => "1100000000111000", 3019 => "1100000000110110", 3020 => "1100000000110100",
3021 => "1100000000110010", 3022 => "1100000000110000", 3023 => "1100000000101110",
3024 => "1100000000101100", 3025 => "1100000000101010", 3026 => "1100000000101000",
3027 => "1100000000100111", 3028 => "1100000000100101", 3029 => "1100000000100011",
3030 => "1100000000100001", 3031 => "1100000000100000", 3032 => "1100000000011110",
3033 => "1100000000011101", 3034 => "1100000000011011", 3035 => "1100000000011010",
3036 => "1100000000011000", 3037 => "1100000000010111", 3038 => "1100000000010110",
3039 => "1100000000010100", 3040 => "1100000000010011", 3041 => "1100000000010010",
3042 => "1100000000010001", 3043 => "1100000000010000", 3044 => "1100000000001111",
3045 => "1100000000001110", 3046 => "1100000000001101", 3047 => "1100000000001100",
3048 => "1100000000001011", 3049 => "1100000000001010", 3050 => "1100000000001001",
3051 => "1100000000001000", 3052 => "1100000000000111", 3053 to 3054=> "1100000000000110",
3055 => "1100000000000101", 3056 to 3057=> "1100000000000100", 3058 to 3059=> "1100000000000011",
3060 to 3061=> "1100000000000010", 3062 to 3064=> "1100000000000001", 3065 to 3079=> "1100000000000000",
3080 to 3082=> "1100000000000001", 3083 to 3084=> "1100000000000010", 3085 to 3086=> "1100000000000011",
3087 to 3088=> "1100000000000100", 3089 => "1100000000000101", 3090 to 3091=> "1100000000000110",
3092 => "1100000000000111", 3093 => "1100000000001000", 3094 => "1100000000001001",
3095 => "1100000000001010", 3096 => "1100000000001011", 3097 => "1100000000001100",
3098 => "1100000000001101", 3099 => "1100000000001110", 3100 => "1100000000001111",
3101 => "1100000000010000", 3102 => "1100000000010001", 3103 => "1100000000010010",
3104 => "1100000000010011", 3105 => "1100000000010100", 3106 => "1100000000010110",
3107 => "1100000000010111", 3108 => "1100000000011000", 3109 => "1100000000011010",
3110 => "1100000000011011", 3111 => "1100000000011101", 3112 => "1100000000011110",
3113 => "1100000000100000", 3114 => "1100000000100001", 3115 => "1100000000100011",
3116 => "1100000000100101", 3117 => "1100000000100111", 3118 => "1100000000101000",
3119 => "1100000000101010", 3120 => "1100000000101100", 3121 => "1100000000101110",
3122 => "1100000000110000", 3123 => "1100000000110010", 3124 => "1100000000110100",
3125 => "1100000000110110", 3126 => "1100000000111000", 3127 => "1100000000111010",
3128 => "1100000000111100", 3129 => "1100000000111110", 3130 => "1100000001000000",
3131 => "1100000001000011", 3132 => "1100000001000101", 3133 => "1100000001000111",
3134 => "1100000001001010", 3135 => "1100000001001100", 3136 => "1100000001001110",
3137 => "1100000001010001", 3138 => "1100000001010011", 3139 => "1100000001010110",
3140 => "1100000001011001", 3141 => "1100000001011011", 3142 => "1100000001011110",
3143 => "1100000001100001", 3144 => "1100000001100011", 3145 => "1100000001100110",
3146 => "1100000001101001", 3147 => "1100000001101100", 3148 => "1100000001101111",
3149 => "1100000001110010", 3150 => "1100000001110101", 3151 => "1100000001111000",
3152 => "1100000001111011", 3153 => "1100000001111110", 3154 => "1100000010000001",
3155 => "1100000010000100", 3156 => "1100000010000111", 3157 => "1100000010001011",
3158 => "1100000010001110", 3159 => "1100000010010001", 3160 => "1100000010010101",
3161 => "1100000010011000", 3162 => "1100000010011011", 3163 => "1100000010011111",
3164 => "1100000010100010", 3165 => "1100000010100110", 3166 => "1100000010101010",
3167 => "1100000010101101", 3168 => "1100000010110001", 3169 => "1100000010110101",
3170 => "1100000010111000", 3171 => "1100000010111100", 3172 => "1100000011000000",
3173 => "1100000011000100", 3174 => "1100000011001000", 3175 => "1100000011001100",
3176 => "1100000011010000", 3177 => "1100000011010100", 3178 => "1100000011011000",
3179 => "1100000011011100", 3180 => "1100000011100000", 3181 => "1100000011100100",
3182 => "1100000011101000", 3183 => "1100000011101100", 3184 => "1100000011110001",
3185 => "1100000011110101", 3186 => "1100000011111001", 3187 => "1100000011111110",
3188 => "1100000100000010", 3189 => "1100000100000111", 3190 => "1100000100001011",
3191 => "1100000100010000", 3192 => "1100000100010100", 3193 => "1100000100011001",
3194 => "1100000100011110", 3195 => "1100000100100010", 3196 => "1100000100100111",
3197 => "1100000100101100", 3198 => "1100000100110001", 3199 => "1100000100110101",
3200 => "1100000100111010", 3201 => "1100000100111111", 3202 => "1100000101000100",
3203 => "1100000101001001", 3204 => "1100000101001110", 3205 => "1100000101010011",
3206 => "1100000101011000", 3207 => "1100000101011110", 3208 => "1100000101100011",
3209 => "1100000101101000", 3210 => "1100000101101101", 3211 => "1100000101110011",
3212 => "1100000101111000", 3213 => "1100000101111101", 3214 => "1100000110000011",
3215 => "1100000110001000", 3216 => "1100000110001110", 3217 => "1100000110010011",
3218 => "1100000110011001", 3219 => "1100000110011110", 3220 => "1100000110100100",
3221 => "1100000110101010", 3222 => "1100000110101111", 3223 => "1100000110110101",
3224 => "1100000110111011", 3225 => "1100000111000001", 3226 => "1100000111000111",
3227 => "1100000111001100", 3228 => "1100000111010010", 3229 => "1100000111011000",
3230 => "1100000111011110", 3231 => "1100000111100100", 3232 => "1100000111101011",
3233 => "1100000111110001", 3234 => "1100000111110111", 3235 => "1100000111111101",
3236 => "1100001000000011", 3237 => "1100001000001010", 3238 => "1100001000010000",
3239 => "1100001000010110", 3240 => "1100001000011101", 3241 => "1100001000100011",
3242 => "1100001000101001", 3243 => "1100001000110000", 3244 => "1100001000110110",
3245 => "1100001000111101", 3246 => "1100001001000100", 3247 => "1100001001001010",
3248 => "1100001001010001", 3249 => "1100001001011000", 3250 => "1100001001011110",
3251 => "1100001001100101", 3252 => "1100001001101100", 3253 => "1100001001110011",
3254 => "1100001001111010", 3255 => "1100001010000001", 3256 => "1100001010001000",
3257 => "1100001010001111", 3258 => "1100001010010110", 3259 => "1100001010011101",
3260 => "1100001010100100", 3261 => "1100001010101011", 3262 => "1100001010110010",
3263 => "1100001010111010", 3264 => "1100001011000001", 3265 => "1100001011001000",
3266 => "1100001011010000", 3267 => "1100001011010111", 3268 => "1100001011011110",
3269 => "1100001011100110", 3270 => "1100001011101101", 3271 => "1100001011110101",
3272 => "1100001011111101", 3273 => "1100001100000100", 3274 => "1100001100001100",
3275 => "1100001100010011", 3276 => "1100001100011011", 3277 => "1100001100100011",
3278 => "1100001100101011", 3279 => "1100001100110011", 3280 => "1100001100111010",
3281 => "1100001101000010", 3282 => "1100001101001010", 3283 => "1100001101010010",
3284 => "1100001101011010", 3285 => "1100001101100010", 3286 => "1100001101101010",
3287 => "1100001101110011", 3288 => "1100001101111011", 3289 => "1100001110000011",
3290 => "1100001110001011", 3291 => "1100001110010011", 3292 => "1100001110011100",
3293 => "1100001110100100", 3294 => "1100001110101100", 3295 => "1100001110110101",
3296 => "1100001110111101", 3297 => "1100001111000110", 3298 => "1100001111001110",
3299 => "1100001111010111", 3300 => "1100001111011111", 3301 => "1100001111101000",
3302 => "1100001111110001", 3303 => "1100001111111001", 3304 => "1100010000000010",
3305 => "1100010000001011", 3306 => "1100010000010100", 3307 => "1100010000011101",
3308 => "1100010000100101", 3309 => "1100010000101110", 3310 => "1100010000110111",
3311 => "1100010001000000", 3312 => "1100010001001001", 3313 => "1100010001010010",
3314 => "1100010001011100", 3315 => "1100010001100101", 3316 => "1100010001101110",
3317 => "1100010001110111", 3318 => "1100010010000000", 3319 => "1100010010001010",
3320 => "1100010010010011", 3321 => "1100010010011100", 3322 => "1100010010100110",
3323 => "1100010010101111", 3324 => "1100010010111000", 3325 => "1100010011000010",
3326 => "1100010011001011", 3327 => "1100010011010101", 3328 => "1100010011011111",
3329 => "1100010011101000", 3330 => "1100010011110010", 3331 => "1100010011111100",
3332 => "1100010100000101", 3333 => "1100010100001111", 3334 => "1100010100011001",
3335 => "1100010100100011", 3336 => "1100010100101101", 3337 => "1100010100110111",
3338 => "1100010101000001", 3339 => "1100010101001011", 3340 => "1100010101010101",
3341 => "1100010101011111", 3342 => "1100010101101001", 3343 => "1100010101110011",
3344 => "1100010101111101", 3345 => "1100010110000111", 3346 => "1100010110010010",
3347 => "1100010110011100", 3348 => "1100010110100110", 3349 => "1100010110110000",
3350 => "1100010110111011", 3351 => "1100010111000101", 3352 => "1100010111010000",
3353 => "1100010111011010", 3354 => "1100010111100101", 3355 => "1100010111101111",
3356 => "1100010111111010", 3357 => "1100011000000100", 3358 => "1100011000001111",
3359 => "1100011000011010", 3360 => "1100011000100101", 3361 => "1100011000101111",
3362 => "1100011000111010", 3363 => "1100011001000101", 3364 => "1100011001010000",
3365 => "1100011001011011", 3366 => "1100011001100110", 3367 => "1100011001110001",
3368 => "1100011001111100", 3369 => "1100011010000111", 3370 => "1100011010010010",
3371 => "1100011010011101", 3372 => "1100011010101000", 3373 => "1100011010110011",
3374 => "1100011010111110", 3375 => "1100011011001010", 3376 => "1100011011010101",
3377 => "1100011011100000", 3378 => "1100011011101100", 3379 => "1100011011110111",
3380 => "1100011100000010", 3381 => "1100011100001110", 3382 => "1100011100011001",
3383 => "1100011100100101", 3384 => "1100011100110000", 3385 => "1100011100111100",
3386 => "1100011101001000", 3387 => "1100011101010011", 3388 => "1100011101011111",
3389 => "1100011101101011", 3390 => "1100011101110110", 3391 => "1100011110000010",
3392 => "1100011110001110", 3393 => "1100011110011010", 3394 => "1100011110100110",
3395 => "1100011110110010", 3396 => "1100011110111110", 3397 => "1100011111001010",
3398 => "1100011111010110", 3399 => "1100011111100010", 3400 => "1100011111101110",
3401 => "1100011111111010", 3402 => "1100100000000110", 3403 => "1100100000010010",
3404 => "1100100000011111", 3405 => "1100100000101011", 3406 => "1100100000110111",
3407 => "1100100001000100", 3408 => "1100100001010000", 3409 => "1100100001011100",
3410 => "1100100001101001", 3411 => "1100100001110101", 3412 => "1100100010000010",
3413 => "1100100010001110", 3414 => "1100100010011011", 3415 => "1100100010101000",
3416 => "1100100010110100", 3417 => "1100100011000001", 3418 => "1100100011001110",
3419 => "1100100011011010", 3420 => "1100100011100111", 3421 => "1100100011110100",
3422 => "1100100100000001", 3423 => "1100100100001110", 3424 => "1100100100011010",
3425 => "1100100100100111", 3426 => "1100100100110100", 3427 => "1100100101000001",
3428 => "1100100101001110", 3429 => "1100100101011011", 3430 => "1100100101101001",
3431 => "1100100101110110", 3432 => "1100100110000011", 3433 => "1100100110010000",
3434 => "1100100110011101", 3435 => "1100100110101011", 3436 => "1100100110111000",
3437 => "1100100111000101", 3438 => "1100100111010011", 3439 => "1100100111100000",
3440 => "1100100111101101", 3441 => "1100100111111011", 3442 => "1100101000001000",
3443 => "1100101000010110", 3444 => "1100101000100011", 3445 => "1100101000110001",
3446 => "1100101000111111", 3447 => "1100101001001100", 3448 => "1100101001011010",
3449 => "1100101001101000", 3450 => "1100101001110110", 3451 => "1100101010000011",
3452 => "1100101010010001", 3453 => "1100101010011111", 3454 => "1100101010101101",
3455 => "1100101010111011", 3456 => "1100101011001001", 3457 => "1100101011010111",
3458 => "1100101011100101", 3459 => "1100101011110011", 3460 => "1100101100000001",
3461 => "1100101100001111", 3462 => "1100101100011101", 3463 => "1100101100101011",
3464 => "1100101100111001", 3465 => "1100101101001000", 3466 => "1100101101010110",
3467 => "1100101101100100", 3468 => "1100101101110011", 3469 => "1100101110000001",
3470 => "1100101110001111", 3471 => "1100101110011110", 3472 => "1100101110101100",
3473 => "1100101110111011", 3474 => "1100101111001001", 3475 => "1100101111011000",
3476 => "1100101111100110", 3477 => "1100101111110101", 3478 => "1100110000000100",
3479 => "1100110000010010", 3480 => "1100110000100001", 3481 => "1100110000110000",
3482 => "1100110000111110", 3483 => "1100110001001101", 3484 => "1100110001011100",
3485 => "1100110001101011", 3486 => "1100110001111010", 3487 => "1100110010001001",
3488 => "1100110010011000", 3489 => "1100110010100111", 3490 => "1100110010110110",
3491 => "1100110011000101", 3492 => "1100110011010100", 3493 => "1100110011100011",
3494 => "1100110011110010", 3495 => "1100110100000001", 3496 => "1100110100010001",
3497 => "1100110100100000", 3498 => "1100110100101111", 3499 => "1100110100111110",
3500 => "1100110101001110", 3501 => "1100110101011101", 3502 => "1100110101101100",
3503 => "1100110101111100", 3504 => "1100110110001011", 3505 => "1100110110011011",
3506 => "1100110110101010", 3507 => "1100110110111010", 3508 => "1100110111001001",
3509 => "1100110111011001", 3510 => "1100110111101001", 3511 => "1100110111111000",
3512 => "1100111000001000", 3513 => "1100111000011000", 3514 => "1100111000100111",
3515 => "1100111000110111", 3516 => "1100111001000111", 3517 => "1100111001010111",
3518 => "1100111001100111", 3519 => "1100111001110111", 3520 => "1100111010000110",
3521 => "1100111010010110", 3522 => "1100111010100110", 3523 => "1100111010110110",
3524 => "1100111011000111", 3525 => "1100111011010111", 3526 => "1100111011100111",
3527 => "1100111011110111", 3528 => "1100111100000111", 3529 => "1100111100010111",
3530 => "1100111100100111", 3531 => "1100111100111000", 3532 => "1100111101001000",
3533 => "1100111101011000", 3534 => "1100111101101001", 3535 => "1100111101111001",
3536 => "1100111110001001", 3537 => "1100111110011010", 3538 => "1100111110101010",
3539 => "1100111110111011", 3540 => "1100111111001011", 3541 => "1100111111011100",
3542 => "1100111111101100", 3543 => "1100111111111101", 3544 => "1101000000001110",
3545 => "1101000000011110", 3546 => "1101000000101111", 3547 => "1101000001000000",
3548 => "1101000001010000", 3549 => "1101000001100001", 3550 => "1101000001110010",
3551 => "1101000010000011", 3552 => "1101000010010100", 3553 => "1101000010100101",
3554 => "1101000010110110", 3555 => "1101000011000111", 3556 => "1101000011010111",
3557 => "1101000011101001", 3558 => "1101000011111010", 3559 => "1101000100001011",
3560 => "1101000100011100", 3561 => "1101000100101101", 3562 => "1101000100111110",
3563 => "1101000101001111", 3564 => "1101000101100000", 3565 => "1101000101110010",
3566 => "1101000110000011", 3567 => "1101000110010100", 3568 => "1101000110100101",
3569 => "1101000110110111", 3570 => "1101000111001000", 3571 => "1101000111011010",
3572 => "1101000111101011", 3573 => "1101000111111100", 3574 => "1101001000001110",
3575 => "1101001000011111", 3576 => "1101001000110001", 3577 => "1101001001000011",
3578 => "1101001001010100", 3579 => "1101001001100110", 3580 => "1101001001110111",
3581 => "1101001010001001", 3582 => "1101001010011011", 3583 => "1101001010101101",
3584 => "1101001010111110", 3585 => "1101001011010000", 3586 => "1101001011100010",
3587 => "1101001011110100", 3588 => "1101001100000110", 3589 => "1101001100010111",
3590 => "1101001100101001", 3591 => "1101001100111011", 3592 => "1101001101001101",
3593 => "1101001101011111", 3594 => "1101001101110001", 3595 => "1101001110000011",
3596 => "1101001110010101", 3597 => "1101001110101000", 3598 => "1101001110111010",
3599 => "1101001111001100", 3600 => "1101001111011110", 3601 => "1101001111110000",
3602 => "1101010000000011", 3603 => "1101010000010101", 3604 => "1101010000100111",
3605 => "1101010000111001", 3606 => "1101010001001100", 3607 => "1101010001011110",
3608 => "1101010001110001", 3609 => "1101010010000011", 3610 => "1101010010010101",
3611 => "1101010010101000", 3612 => "1101010010111010", 3613 => "1101010011001101",
3614 => "1101010011011111", 3615 => "1101010011110010", 3616 => "1101010100000101",
3617 => "1101010100010111", 3618 => "1101010100101010", 3619 => "1101010100111101",
3620 => "1101010101001111", 3621 => "1101010101100010", 3622 => "1101010101110101",
3623 => "1101010110001000", 3624 => "1101010110011010", 3625 => "1101010110101101",
3626 => "1101010111000000", 3627 => "1101010111010011", 3628 => "1101010111100110",
3629 => "1101010111111001", 3630 => "1101011000001100", 3631 => "1101011000011111",
3632 => "1101011000110010", 3633 => "1101011001000101", 3634 => "1101011001011000",
3635 => "1101011001101011", 3636 => "1101011001111110", 3637 => "1101011010010001",
3638 => "1101011010100101", 3639 => "1101011010111000", 3640 => "1101011011001011",
3641 => "1101011011011110", 3642 => "1101011011110001", 3643 => "1101011100000101",
3644 => "1101011100011000", 3645 => "1101011100101011", 3646 => "1101011100111111",
3647 => "1101011101010010", 3648 => "1101011101100110", 3649 => "1101011101111001",
3650 => "1101011110001101", 3651 => "1101011110100000", 3652 => "1101011110110100",
3653 => "1101011111000111", 3654 => "1101011111011011", 3655 => "1101011111101110",
3656 => "1101100000000010", 3657 => "1101100000010101", 3658 => "1101100000101001",
3659 => "1101100000111101", 3660 => "1101100001010000", 3661 => "1101100001100100",
3662 => "1101100001111000", 3663 => "1101100010001100", 3664 => "1101100010100000",
3665 => "1101100010110011", 3666 => "1101100011000111", 3667 => "1101100011011011",
3668 => "1101100011101111", 3669 => "1101100100000011", 3670 => "1101100100010111",
3671 => "1101100100101011", 3672 => "1101100100111111", 3673 => "1101100101010011",
3674 => "1101100101100111", 3675 => "1101100101111011", 3676 => "1101100110001111",
3677 => "1101100110100011", 3678 => "1101100110110111", 3679 => "1101100111001011",
3680 => "1101100111100000", 3681 => "1101100111110100", 3682 => "1101101000001000",
3683 => "1101101000011100", 3684 => "1101101000110000", 3685 => "1101101001000101",
3686 => "1101101001011001", 3687 => "1101101001101101", 3688 => "1101101010000010",
3689 => "1101101010010110", 3690 => "1101101010101011", 3691 => "1101101010111111",
3692 => "1101101011010011", 3693 => "1101101011101000", 3694 => "1101101011111100",
3695 => "1101101100010001", 3696 => "1101101100100101", 3697 => "1101101100111010",
3698 => "1101101101001111", 3699 => "1101101101100011", 3700 => "1101101101111000",
3701 => "1101101110001100", 3702 => "1101101110100001", 3703 => "1101101110110110",
3704 => "1101101111001011", 3705 => "1101101111011111", 3706 => "1101101111110100",
3707 => "1101110000001001", 3708 => "1101110000011110", 3709 => "1101110000110010",
3710 => "1101110001000111", 3711 => "1101110001011100", 3712 => "1101110001110001",
3713 => "1101110010000110", 3714 => "1101110010011011", 3715 => "1101110010110000",
3716 => "1101110011000101", 3717 => "1101110011011010", 3718 => "1101110011101111",
3719 => "1101110100000100", 3720 => "1101110100011001", 3721 => "1101110100101110",
3722 => "1101110101000011", 3723 => "1101110101011000", 3724 => "1101110101101101",
3725 => "1101110110000010", 3726 => "1101110110011000", 3727 => "1101110110101101",
3728 => "1101110111000010", 3729 => "1101110111010111", 3730 => "1101110111101101",
3731 => "1101111000000010", 3732 => "1101111000010111", 3733 => "1101111000101101",
3734 => "1101111001000010", 3735 => "1101111001010111", 3736 => "1101111001101101",
3737 => "1101111010000010", 3738 => "1101111010010111", 3739 => "1101111010101101",
3740 => "1101111011000010", 3741 => "1101111011011000", 3742 => "1101111011101101",
3743 => "1101111100000011", 3744 => "1101111100011000", 3745 => "1101111100101110",
3746 => "1101111101000100", 3747 => "1101111101011001", 3748 => "1101111101101111",
3749 => "1101111110000100", 3750 => "1101111110011010", 3751 => "1101111110110000",
3752 => "1101111111000110", 3753 => "1101111111011011", 3754 => "1101111111110001",
3755 => "1110000000000111", 3756 => "1110000000011101", 3757 => "1110000000110010",
3758 => "1110000001001000", 3759 => "1110000001011110", 3760 => "1110000001110100",
3761 => "1110000010001010", 3762 => "1110000010100000", 3763 => "1110000010110110",
3764 => "1110000011001011", 3765 => "1110000011100001", 3766 => "1110000011110111",
3767 => "1110000100001101", 3768 => "1110000100100011", 3769 => "1110000100111001",
3770 => "1110000101001111", 3771 => "1110000101100110", 3772 => "1110000101111100",
3773 => "1110000110010010", 3774 => "1110000110101000", 3775 => "1110000110111110",
3776 => "1110000111010100", 3777 => "1110000111101010", 3778 => "1110001000000001",
3779 => "1110001000010111", 3780 => "1110001000101101", 3781 => "1110001001000011",
3782 => "1110001001011001", 3783 => "1110001001110000", 3784 => "1110001010000110",
3785 => "1110001010011100", 3786 => "1110001010110011", 3787 => "1110001011001001",
3788 => "1110001011011111", 3789 => "1110001011110110", 3790 => "1110001100001100",
3791 => "1110001100100011", 3792 => "1110001100111001", 3793 => "1110001101010000",
3794 => "1110001101100110", 3795 => "1110001101111100", 3796 => "1110001110010011",
3797 => "1110001110101010", 3798 => "1110001111000000", 3799 => "1110001111010111",
3800 => "1110001111101101", 3801 => "1110010000000100", 3802 => "1110010000011010",
3803 => "1110010000110001", 3804 => "1110010001001000", 3805 => "1110010001011110",
3806 => "1110010001110101", 3807 => "1110010010001100", 3808 => "1110010010100010",
3809 => "1110010010111001", 3810 => "1110010011010000", 3811 => "1110010011100111",
3812 => "1110010011111101", 3813 => "1110010100010100", 3814 => "1110010100101011",
3815 => "1110010101000010", 3816 => "1110010101011001", 3817 => "1110010101110000",
3818 => "1110010110000110", 3819 => "1110010110011101", 3820 => "1110010110110100",
3821 => "1110010111001011", 3822 => "1110010111100010", 3823 => "1110010111111001",
3824 => "1110011000010000", 3825 => "1110011000100111", 3826 => "1110011000111110",
3827 => "1110011001010101", 3828 => "1110011001101100", 3829 => "1110011010000011",
3830 => "1110011010011010", 3831 => "1110011010110001", 3832 => "1110011011001000",
3833 => "1110011011011111", 3834 => "1110011011110111", 3835 => "1110011100001110",
3836 => "1110011100100101", 3837 => "1110011100111100", 3838 => "1110011101010011",
3839 => "1110011101101010", 3840 => "1110011110000010", 3841 => "1110011110011001",
3842 => "1110011110110000", 3843 => "1110011111000111", 3844 => "1110011111011111",
3845 => "1110011111110110", 3846 => "1110100000001101", 3847 => "1110100000100101",
3848 => "1110100000111100", 3849 => "1110100001010011", 3850 => "1110100001101011",
3851 => "1110100010000010", 3852 => "1110100010011001", 3853 => "1110100010110001",
3854 => "1110100011001000", 3855 => "1110100011100000", 3856 => "1110100011110111",
3857 => "1110100100001110", 3858 => "1110100100100110", 3859 => "1110100100111101",
3860 => "1110100101010101", 3861 => "1110100101101100", 3862 => "1110100110000100",
3863 => "1110100110011011", 3864 => "1110100110110011", 3865 => "1110100111001011",
3866 => "1110100111100010", 3867 => "1110100111111010", 3868 => "1110101000010001",
3869 => "1110101000101001", 3870 => "1110101001000001", 3871 => "1110101001011000",
3872 => "1110101001110000", 3873 => "1110101010001000", 3874 => "1110101010011111",
3875 => "1110101010110111", 3876 => "1110101011001111", 3877 => "1110101011100110",
3878 => "1110101011111110", 3879 => "1110101100010110", 3880 => "1110101100101110",
3881 => "1110101101000101", 3882 => "1110101101011101", 3883 => "1110101101110101",
3884 => "1110101110001101", 3885 => "1110101110100101", 3886 => "1110101110111100",
3887 => "1110101111010100", 3888 => "1110101111101100", 3889 => "1110110000000100",
3890 => "1110110000011100", 3891 => "1110110000110100", 3892 => "1110110001001100",
3893 => "1110110001100100", 3894 => "1110110001111100", 3895 => "1110110010010011",
3896 => "1110110010101011", 3897 => "1110110011000011", 3898 => "1110110011011011",
3899 => "1110110011110011", 3900 => "1110110100001011", 3901 => "1110110100100011",
3902 => "1110110100111011", 3903 => "1110110101010011", 3904 => "1110110101101011",
3905 => "1110110110000100", 3906 => "1110110110011100", 3907 => "1110110110110100",
3908 => "1110110111001100", 3909 => "1110110111100100", 3910 => "1110110111111100",
3911 => "1110111000010100", 3912 => "1110111000101100", 3913 => "1110111001000100",
3914 => "1110111001011101", 3915 => "1110111001110101", 3916 => "1110111010001101",
3917 => "1110111010100101", 3918 => "1110111010111101", 3919 => "1110111011010101",
3920 => "1110111011101110", 3921 => "1110111100000110", 3922 => "1110111100011110",
3923 => "1110111100110110", 3924 => "1110111101001111", 3925 => "1110111101100111",
3926 => "1110111101111111", 3927 => "1110111110010111", 3928 => "1110111110110000",
3929 => "1110111111001000", 3930 => "1110111111100000", 3931 => "1110111111111001",
3932 => "1111000000010001", 3933 => "1111000000101001", 3934 => "1111000001000010",
3935 => "1111000001011010", 3936 => "1111000001110011", 3937 => "1111000010001011",
3938 => "1111000010100011", 3939 => "1111000010111100", 3940 => "1111000011010100",
3941 => "1111000011101101", 3942 => "1111000100000101", 3943 => "1111000100011101",
3944 => "1111000100110110", 3945 => "1111000101001110", 3946 => "1111000101100111",
3947 => "1111000101111111", 3948 => "1111000110011000", 3949 => "1111000110110000",
3950 => "1111000111001001", 3951 => "1111000111100001", 3952 => "1111000111111010",
3953 => "1111001000010010", 3954 => "1111001000101011", 3955 => "1111001001000011",
3956 => "1111001001011100", 3957 => "1111001001110100", 3958 => "1111001010001101",
3959 => "1111001010100110", 3960 => "1111001010111110", 3961 => "1111001011010111",
3962 => "1111001011101111", 3963 => "1111001100001000", 3964 => "1111001100100001",
3965 => "1111001100111001", 3966 => "1111001101010010", 3967 => "1111001101101010",
3968 => "1111001110000011", 3969 => "1111001110011100", 3970 => "1111001110110100",
3971 => "1111001111001101", 3972 => "1111001111100110", 3973 => "1111001111111110",
3974 => "1111010000010111", 3975 => "1111010000110000", 3976 => "1111010001001001",
3977 => "1111010001100001", 3978 => "1111010001111010", 3979 => "1111010010010011",
3980 => "1111010010101011", 3981 => "1111010011000100", 3982 => "1111010011011101",
3983 => "1111010011110110", 3984 => "1111010100001110", 3985 => "1111010100100111",
3986 => "1111010101000000", 3987 => "1111010101011001", 3988 => "1111010101110010",
3989 => "1111010110001010", 3990 => "1111010110100011", 3991 => "1111010110111100",
3992 => "1111010111010101", 3993 => "1111010111101110", 3994 => "1111011000000110",
3995 => "1111011000011111", 3996 => "1111011000111000", 3997 => "1111011001010001",
3998 => "1111011001101010", 3999 => "1111011010000011", 4000 => "1111011010011011",
4001 => "1111011010110100", 4002 => "1111011011001101", 4003 => "1111011011100110",
4004 => "1111011011111111", 4005 => "1111011100011000", 4006 => "1111011100110001",
4007 => "1111011101001010", 4008 => "1111011101100011", 4009 => "1111011101111011",
4010 => "1111011110010100", 4011 => "1111011110101101", 4012 => "1111011111000110",
4013 => "1111011111011111", 4014 => "1111011111111000", 4015 => "1111100000010001",
4016 => "1111100000101010", 4017 => "1111100001000011", 4018 => "1111100001011100",
4019 => "1111100001110101", 4020 => "1111100010001110", 4021 => "1111100010100111",
4022 => "1111100011000000", 4023 => "1111100011011001", 4024 => "1111100011110010",
4025 => "1111100100001011", 4026 => "1111100100100100", 4027 => "1111100100111101",
4028 => "1111100101010110", 4029 => "1111100101101111", 4030 => "1111100110001000",
4031 => "1111100110100001", 4032 => "1111100110111010", 4033 => "1111100111010011",
4034 => "1111100111101100", 4035 => "1111101000000101", 4036 => "1111101000011110",
4037 => "1111101000110111", 4038 => "1111101001010000", 4039 => "1111101001101001",
4040 => "1111101010000010", 4041 => "1111101010011011", 4042 => "1111101010110100",
4043 => "1111101011001101", 4044 => "1111101011100110", 4045 => "1111101011111111",
4046 => "1111101100011000", 4047 => "1111101100110001", 4048 => "1111101101001010",
4049 => "1111101101100011", 4050 => "1111101101111100", 4051 => "1111101110010101",
4052 => "1111101110101110", 4053 => "1111101111001000", 4054 => "1111101111100001",
4055 => "1111101111111010", 4056 => "1111110000010011", 4057 => "1111110000101100",
4058 => "1111110001000101", 4059 => "1111110001011110", 4060 => "1111110001110111",
4061 => "1111110010010000", 4062 => "1111110010101001", 4063 => "1111110011000010",
4064 => "1111110011011100", 4065 => "1111110011110101", 4066 => "1111110100001110",
4067 => "1111110100100111", 4068 => "1111110101000000", 4069 => "1111110101011001",
4070 => "1111110101110010", 4071 => "1111110110001011", 4072 => "1111110110100100",
4073 => "1111110110111110", 4074 => "1111110111010111", 4075 => "1111110111110000",
4076 => "1111111000001001", 4077 => "1111111000100010", 4078 => "1111111000111011",
4079 => "1111111001010100", 4080 => "1111111001101101", 4081 => "1111111010000111",
4082 => "1111111010100000", 4083 => "1111111010111001", 4084 => "1111111011010010",
4085 => "1111111011101011", 4086 => "1111111100000100", 4087 => "1111111100011101",
4088 => "1111111100110110", 4089 => "1111111101010000", 4090 => "1111111101101001",
4091 => "1111111110000010", 4092 => "1111111110011011", 4093 => "1111111110110100",
4094 => "1111111111001101", 4095 => "1111111111100110" );
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nco_sine_lut_V is
generic (
DataWidth : INTEGER := 16;
AddressRange : INTEGER := 4096;
AddressWidth : INTEGER := 12);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of nco_sine_lut_V is
component nco_sine_lut_V_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
nco_sine_lut_V_rom_U : component nco_sine_lut_V_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
|
-------------------------------------------------------------
-- MSS copyright 2011-2014
-- Filename: COM5402.VHD
-- Author: Alain Zarembowitch / MSS
-- Version: 6
-- Date last modified: 1/31/14
-- Inheritance: N/A
--
-- description: Internet IP stack: IP/TCP/UDP/ARP/PING.
-- The IP stack relies on the lower layers: MAC (COM5401) and PHY (Integrated circuit)
-- Interfaces directly with COM-5401SOFT MAC protocol layer or equivalent.
--
-- Rev 2 8/21/11 AZ
-- Change tx strategy. Transmission is triggered when MAC_TX_CTS = '1' without any
-- flow control breaks within a frame. Reason: the MAC tx elastic buffer is now 4KB,
-- large enough for 2 maximum size frames.
--
-- Rev 3 11/10/13 AZ
-- Progressively replacing ASYNC_RESET with SYNC_RESET
--
-- Rev 4 11/10/13 AZ
-- Added MAC_TX_SOF flag for an easier interface with Xilinx tri-mode MAC
-- Corrected IP header bug in UDP_TX.vhd
--
-- Rev 5 1/28/14 AZ
-- Increased EFF_RX_WINDOW_SIZE_PARTIAL precision to 17 bits to detect abnormal negative window size reports
--
-- Rev 6 1/31/14 AZ
-- moved TX_IDLE_TIMEOUT up to a generic parameter.
---------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.com5402pkg.all; -- defines global types, number of TCP streams, etc
library UNISIM;
use UNISIM.VComponents.all;
entity COM5402 is
generic (
CLK_FREQUENCY: integer := 56;
-- CLK frequency in MHz. Needed to compute actual delays.
TX_IDLE_TIMEOUT: integer range 0 to 50:= 50;
-- inactive input timeout, expressed in 4us units. -- 50*4us = 200us
-- Controls the transmit stream segmentation: data in the elastic buffer will be transmitted if
-- no input is received within TX_IDLE_TIMEOUT, without waiting for the transmit frame to be filled with MSS data bytes.
SIMULATION: std_logic := '0'
-- 1 during simulation with Wireshark .cap file, '0' otherwise
-- Wireshark many not be able to collect offloaded checksum computations.
-- when SIMULATION = '1': (a) IP header checksum is valid if 0000,
-- (b) TCP checksum computation is forced to a valid 00001 irrespective of the 16-bit checksum
-- captured by Wireshark.
);
Port (
--//-- CLK, RESET
CLK: in std_logic;
-- All signals are synchronous with CLK
-- CLK must be a global clock 125 MHz or faster to match the Gbps MAC speed.
ASYNC_RESET: in std_logic; -- to be phased out. replace with SYNC_RESET
SYNC_RESET: in std_logic;
--//-- CONFIGURATION
-- configuration signals are synchonous with CLK
-- Synchronous with CLK clock.
MAC_ADDR : IN std_logic_vector(47 downto 0);
IPv4_ADDR: in std_logic_vector(31 downto 0);
IPv6_ADDR: in std_logic_vector(127 downto 0);
SUBNET_MASK: in std_logic_vector(31 downto 0);
GATEWAY_IP_ADDR: in std_logic_vector(31 downto 0);
-- local IP address. 4 bytes for IPv4, 16 bytes for IPv6
-- Natural order (MSB) 172.16.1.128 (LSB) as transmitted in the IP frame.
--// User-initiated connection reset for stream I
CONNECTION_RESET: in std_logic_vector((NTCPSTREAMS-1) downto 0);
--//-- Protocol -> Transmit MAC Interface
-- 32-bit CRC is automatically appended by the MAC layer. User should not supply it.
-- Synchonous with the user-side CLK
MAC_TX_DATA: out std_logic_vector(7 downto 0);
-- MAC reads the data at the rising edge of CLK when MAC_TX_DATA_VALID = '1'
MAC_TX_DATA_VALID: out std_logic;
-- data valid
MAC_TX_SOF: out std_logic;
-- start of frame: '1' when sending the first byte.
-- Aligned with MAC_TX_DATA_VALID
MAC_TX_EOF: out std_logic;
-- End of frame: '1' when sending the last byte in a packet to be transmitted.
-- Aligned with MAC_TX_DATA_VALID
MAC_TX_CTS: in std_logic;
-- MAC-generated Clear To Send flow control signal, indicating room in the
-- MAC tx elastic buffer for a complete maximum size frame 1518B.
-- The user should check that this signal is high before deciding to send
-- sending the next frame.
-- Note: MAC_TX_CTS may go low while the frame is transfered in. Ignore it as space is guaranteed
-- at the start of frame.
--//-- Receive MAC -> Protocol
-- Valid rx packets only: packets with bad CRC or invalid address are discarded.
-- The 32-bit CRC is always removed by the MAC layer.
-- Synchonous with the user-side CLK
MAC_RX_DATA: in std_logic_vector(7 downto 0);
-- USER reads the data at the rising edge of CLK when MAC_RX_DATA_VALID = '1'
MAC_RX_DATA_VALID: in std_logic;
-- data valid
MAC_RX_SOF: in std_logic;
-- '1' when sending the first byte in a received packet.
-- Aligned with MAC_RX_DATA_VALID
MAC_RX_EOF: in std_logic;
-- '1' when sending the last byte in a received packet.
-- Aligned with MAC_RX_DATA_VALID
--//-- Application <- UDP rx
UDP_RX_DATA: out std_logic_vector(7 downto 0);
UDP_RX_DATA_VALID: out std_logic;
UDP_RX_SOF: out std_logic;
UDP_RX_EOF: out std_logic;
-- 1 CLK pulse indicating that UDP_RX_DATA is the last byte in the UDP data field.
-- ALWAYS CHECK UDP_RX_DATA_VALID at the end of packet (UDP_RX_EOF = '1') to confirm
-- that the UDP packet is valid. External buffer may have to backtrack to the the last
-- valid pointer to discard an invalid UDP packet.
-- Reason: we only knows about bad UDP packets at the end.
UDP_RX_DEST_PORT_NO: in std_logic_vector(15 downto 0);
--//-- Application -> UDP tx
UDP_TX_DATA: in std_logic_vector(7 downto 0);
UDP_TX_DATA_VALID: in std_logic;
UDP_TX_SOF: in std_logic; -- 1 CLK-wide pulse to mark the first byte in the tx UDP frame
UDP_TX_EOF: in std_logic; -- 1 CLK-wide pulse to mark the last byte in the tx UDP frame
UDP_TX_CTS: out std_logic;
UDP_TX_ACK: out std_logic; -- 1 CLK-wide pulse indicating that the previous UDP frame is being sent
UDP_TX_NAK: out std_logic; -- 1 CLK-wide pulse indicating that the previous UDP frame could not be sent
UDP_TX_DEST_IP_ADDR: in std_logic_vector(127 downto 0);
UDP_TX_DEST_PORT_NO: in std_logic_vector(15 downto 0);
UDP_TX_SOURCE_PORT_NO: in std_logic_vector(15 downto 0);
--//-- Application <- TCP rx
-- NTCPSTREAMS can operate independently and concurrently. No scheduling arbitration needed here.
TCP_RX_DATA: out SLV8xNTCPSTREAMStype;
TCP_RX_DATA_VALID: out std_logic_vector((NTCPSTREAMS-1) downto 0);
TCP_RX_RTS: out std_logic_vector((NTCPSTREAMS-1) downto 0); -- Ready To Send
TCP_RX_CTS: in std_logic_vector((NTCPSTREAMS-1) downto 0); -- Clear To Send
--//-- Application -> TCP tx
-- NTCPSTREAMS can operate independently and concurrently. No scheduling arbitration needed here.
TCP_TX_DATA: in SLV8xNTCPSTREAMStype;
TCP_TX_DATA_VALID: in std_logic_vector((NTCPSTREAMS-1) downto 0);
TCP_TX_CTS: out std_logic_vector((NTCPSTREAMS-1) downto 0);
-- Clear To Send = transmit flow control.
-- App is responsible for checking the CTS signal before sending APP_DATA
--//-- TEST POINTS, COMSCOPE TRACES
CS1: out std_logic_vector(7 downto 0);
CS1_CLK: out std_logic;
CS2: out std_logic_vector(7 downto 0);
CS2_CLK: out std_logic;
TP: out std_logic_vector(10 downto 1)
);
end entity;
architecture Behavioral of COM5402 is
--------------------------------------------------------
-- COMPONENTS
--------------------------------------------------------
COMPONENT TIMER_4US
GENERIC (
CLK_FREQUENCY: integer
);
PORT(
ASYNC_RESET : IN std_logic;
CLK : IN std_logic;
TICK_4US : OUT std_logic;
TICK_100MS: out std_logic
);
END COMPONENT;
COMPONENT PACKET_PARSING
GENERIC (
IPv6_ENABLED: std_logic;
SIMULATION: std_logic
);
PORT(
ASYNC_RESET : IN std_logic;
CLK : IN std_logic;
TICK_4US : IN std_logic;
MAC_RX_DATA : IN std_logic_vector(7 downto 0);
MAC_RX_DATA_VALID : IN std_logic;
MAC_RX_SOF : IN std_logic;
MAC_RX_EOF : IN std_logic;
IPv4_ADDR: in std_logic_vector(31 downto 0);
IPv6_ADDR: in std_logic_vector(127 downto 0);
IP_RX_DATA: out std_logic_vector(7 downto 0);
IP_RX_DATA_VALID: out std_logic;
IP_RX_SOF: out std_logic;
IP_RX_EOF: out std_logic;
IP_BYTE_COUNT: out std_logic_vector(15 downto 0);
IP_HEADER_FLAG: out std_logic;
RX_TYPE : OUT std_logic_vector(3 downto 0);
RX_TYPE_RDY : OUT std_logic;
RX_IPv4_6n: out std_logic;
RX_IP_PROTOCOL : OUT std_logic_vector(7 downto 0);
RX_IP_PROTOCOL_RDY : OUT std_logic;
VALID_DEST_IP : OUT std_logic;
VALID_DEST_IP_RDY : OUT std_logic;
IP_HEADER_CHECKSUM_VALID: out std_logic;
IP_HEADER_CHECKSUM_VALID_RDY: out std_logic;
RX_SOURCE_MAC_ADDR: out std_logic_vector(47 downto 0);
RX_SOURCE_IP_ADDR: out std_logic_vector(127 downto 0);
RX_SOURCE_TCP_PORT_NO: out std_logic_vector(15 downto 0);
RX_DEST_IP_ADDR: out std_logic_vector(127 downto 0);
RX_DEST_TCP_PORT_NO: out std_logic_vector(15 downto 0);
RX_UDP_CKSUM: out std_logic_vector(16 downto 0);
RX_UDP_CKSUM_RDY: out std_logic;
RX_TCP_HEADER_FLAG: out std_logic;
RX_TCP_FLAGS: out std_logic_vector(7 downto 0);
RX_TCP_CKSUM: out std_logic_vector(16 downto 0);
RX_TCP_SEQ_NO: out std_logic_vector(31 downto 0);
RX_TCP_ACK_NO: out std_logic_vector(31 downto 0);
RX_TCP_WINDOW_SIZE: out std_logic_vector(15 downto 0);
CS1 : OUT std_logic_vector(7 downto 0);
CS1_CLK : OUT std_logic;
CS2 : OUT std_logic_vector(7 downto 0);
CS2_CLK : OUT std_logic;
TP : OUT std_logic_vector(10 downto 1)
);
END COMPONENT;
COMPONENT PING
GENERIC (
IPv6_ENABLED: std_logic;
MAX_PING_SIZE: std_logic_vector(15 downto 0)
);
PORT(
ASYNC_RESET : IN std_logic;
CLK : IN std_logic;
MAC_RX_DATA : IN std_logic_vector(7 downto 0);
MAC_RX_DATA_VALID : IN std_logic;
MAC_RX_SOF : IN std_logic;
MAC_RX_EOF : IN std_logic;
MAC_ADDR : IN std_logic_vector(47 downto 0);
IPv4_ADDR: in std_logic_vector(31 downto 0);
IPv6_ADDR: in std_logic_vector(127 downto 0);
RX_IPv4_6n: in std_logic;
RX_IP_PROTOCOL : IN std_logic_vector(7 downto 0);
RX_IP_PROTOCOL_RDY : IN std_logic;
IP_RX_DATA_VALID: in std_logic;
IP_RX_EOF : IN std_logic;
MAC_TX_CTS : IN std_logic;
MAC_TX_DATA : OUT std_logic_vector(7 downto 0);
MAC_TX_DATA_VALID : OUT std_logic;
MAC_TX_EOF : OUT std_logic;
RTS : OUT std_logic;
TP : OUT std_logic_vector(10 downto 1)
);
END COMPONENT;
COMPONENT ARP
PORT(
ASYNC_RESET : IN std_logic;
CLK : IN std_logic;
MAC_RX_DATA : IN std_logic_vector(7 downto 0);
MAC_RX_DATA_VALID : IN std_logic;
MAC_RX_SOF : IN std_logic;
MAC_RX_EOF : IN std_logic;
MAC_ADDR : IN std_logic_vector(47 downto 0);
IPv4_ADDR: in std_logic_vector(31 downto 0);
RX_TYPE : IN std_logic_vector(3 downto 0);
RX_TYPE_RDY : IN std_logic;
RX_SOURCE_MAC_ADDR: in std_logic_vector(47 downto 0);
RX_SOURCE_IP_ADDR: in std_logic_vector(31 downto 0);
MAC_TX_CTS : IN std_logic;
MAC_TX_DATA : OUT std_logic_vector(7 downto 0);
MAC_TX_DATA_VALID : OUT std_logic;
MAC_TX_EOF : OUT std_logic;
RTS : OUT std_logic;
TP : OUT std_logic_vector(10 downto 1)
);
END COMPONENT;
COMPONENT WHOIS2
PORT(
CLK : IN std_logic;
SYNC_RESET : IN std_logic;
WHOIS_IP_ADDR : IN std_logic_vector(31 downto 0);
WHOIS_START : IN std_logic;
MAC_ADDR : IN std_logic_vector(47 downto 0);
IPv4_ADDR : IN std_logic_vector(31 downto 0);
MAC_TX_CTS : IN std_logic;
WHOIS_RDY : OUT std_logic;
MAC_TX_DATA : OUT std_logic_vector(7 downto 0);
MAC_TX_DATA_VALID : OUT std_logic;
MAX_TX_EOF : OUT std_logic;
RTS : OUT std_logic;
TP : OUT std_logic_vector(10 downto 1)
);
END COMPONENT;
COMPONENT ARP_CACHE2
PORT(
SYNC_RESET: in std_logic;
CLK : IN std_logic;
TICK_100MS : IN std_logic;
RT_IP_ADDR : IN std_logic_vector(31 downto 0);
RT_REQ_RTS : IN std_logic;
RT_CTS: out std_logic;
RT_MAC_REPLY : OUT std_logic_vector(47 downto 0);
RT_MAC_RDY : OUT std_logic;
RT_NAK: out std_logic;
MAC_ADDR : IN std_logic_vector(47 downto 0);
IPv4_ADDR : IN std_logic_vector(31 downto 0);
SUBNET_MASK : IN std_logic_vector(31 downto 0);
GATEWAY_IP_ADDR: in std_logic_vector(31 downto 0);
RX_SOURCE_ADDR_RDY: in std_logic;
RX_SOURCE_MAC_ADDR: in std_logic_vector(47 downto 0);
RX_SOURCE_IP_ADDR: in std_logic_vector(31 downto 0);
WHOIS_IP_ADDR : OUT std_logic_vector(31 downto 0);
WHOIS_START : OUT std_logic;
SREG1 : OUT std_logic_vector(7 downto 0);
SREG2 : OUT std_logic_vector(7 downto 0);
SREG3 : OUT std_logic_vector(7 downto 0);
SREG4 : OUT std_logic_vector(7 downto 0);
SREG5 : OUT std_logic_vector(7 downto 0);
SREG6 : OUT std_logic_vector(7 downto 0);
TP : OUT std_logic_vector(10 downto 1)
);
END COMPONENT;
COMPONENT UDP2SERIAL
GENERIC (
PORT_NO: std_logic_vector(15 downto 0);
CLK_FREQUENCY: integer
);
PORT(
ASYNC_RESET : IN std_logic;
CLK : IN std_logic;
IP_RX_DATA : IN std_logic_vector(7 downto 0);
IP_RX_DATA_VALID : IN std_logic;
IP_RX_SOF : IN std_logic;
IP_RX_EOF : IN std_logic;
IP_HEADER_FLAG : IN std_logic;
RX_IP_PROTOCOL : IN std_logic_vector(7 downto 0);
RX_IP_PROTOCOL_RDY : IN std_logic;
SERIAL_OUT : OUT std_logic;
TP : OUT std_logic_vector(10 downto 1)
);
END COMPONENT;
COMPONENT UDP_RX
PORT(
ASYNC_RESET : IN std_logic;
CLK : IN std_logic;
IP_RX_DATA : IN std_logic_vector(7 downto 0);
IP_RX_DATA_VALID : IN std_logic;
IP_RX_SOF : IN std_logic;
IP_RX_EOF : IN std_logic;
IP_BYTE_COUNT: in std_logic_vector(15 downto 0);
IP_HEADER_FLAG : IN std_logic;
RX_IP_PROTOCOL : IN std_logic_vector(7 downto 0);
RX_IP_PROTOCOL_RDY : IN std_logic;
RX_UDP_CKSUM: in std_logic_vector(16 downto 0);
RX_UDP_CKSUM_RDY: in std_logic;
PORT_NO: in std_logic_vector(15 downto 0);
APP_DATA : OUT std_logic_vector(7 downto 0);
APP_DATA_VALID : OUT std_logic;
APP_SOF : OUT std_logic;
APP_EOF : OUT std_logic;
APP_SRC_UDP_PORT: OUT std_logic_vector(15 downto 0);
TP : OUT std_logic_vector(10 downto 1)
);
END COMPONENT;
COMPONENT UDP_TX
generic (
NBUFS: integer ;
IPv6_ENABLED: std_logic
);
PORT(
CLK : IN std_logic;
SYNC_RESET : IN std_logic;
TICK_4US: in std_logic;
APP_DATA : IN std_logic_vector(7 downto 0);
APP_DATA_VALID : IN std_logic;
APP_SOF : IN std_logic;
APP_EOF : IN std_logic;
APP_CTS : OUT std_logic;
DEST_IP_ADDR: in std_logic_vector(127 downto 0);
DEST_PORT_NO : IN std_logic_vector(15 downto 0);
SOURCE_PORT_NO : IN std_logic_vector(15 downto 0);
IPv4_6n: in std_logic;
MAC_ADDR: in std_logic_vector(47 downto 0);
IPv4_ADDR: in std_logic_vector(31 downto 0);
IPv6_ADDR: in std_logic_vector(127 downto 0);
IP_ID: in std_logic_vector(15 downto 0);
ACK : OUT std_logic;
NAK : OUT std_logic;
RT_IP_ADDR : OUT std_logic_vector(31 downto 0);
RT_REQ_RTS: out std_logic;
RT_REQ_CTS: in std_logic;
RT_MAC_REPLY : IN std_logic_vector(47 downto 0);
RT_MAC_RDY : IN std_logic;
RT_NAK: in std_logic;
MAC_TX_DATA : OUT std_logic_vector(7 downto 0);
MAC_TX_DATA_VALID : OUT std_logic;
MAC_TX_EOF : OUT std_logic;
MAC_TX_CTS : IN std_logic;
RTS: out std_logic := '0';
TP : OUT std_logic_vector(10 downto 1)
);
END COMPONENT;
COMPONENT TCP_SERVER
GENERIC (
MSS: std_logic_vector(15 downto 0);
IPv6_ENABLED: std_logic;
SIMULATION: std_logic
);
PORT(
CLK : IN std_logic;
SYNC_RESET: in std_logic;
TICK_4US: in std_logic;
TICK_100MS: in std_logic;
MAC_ADDR: in std_logic_vector(47 downto 0);
TCP_LOCAL_PORTS: in SLV16xNTCPSTREAMStype;
CONNECTION_RESET: in std_logic_vector((NTCPSTREAMS-1) downto 0);
IP_RX_DATA: in std_logic_vector(7 downto 0);
IP_RX_DATA_VALID: in std_logic;
IP_RX_SOF: in std_logic;
IP_RX_EOF: in std_logic;
IP_BYTE_COUNT: in std_logic_vector(15 downto 0);
IP_HEADER_FLAG: in std_logic;
RX_IPv4_6n: in std_logic;
RX_IP_PROTOCOL: in std_logic_vector(7 downto 0);
RX_IP_PROTOCOL_RDY: in std_logic;
RX_SOURCE_MAC_ADDR: in std_logic_vector(47 downto 0);
RX_SOURCE_IP_ADDR: in std_logic_vector(127 downto 0);
RX_SOURCE_TCP_PORT_NO: in std_logic_vector(15 downto 0);
RX_TCP_HEADER_FLAG: in std_logic;
RX_TCP_FLAGS: in std_logic_vector(7 downto 0);
RX_TCP_CKSUM: in std_logic_vector(16 downto 0);
RX_TCP_SEQ_NO: in std_logic_vector(31 downto 0);
RX_TCP_ACK_NO: in std_logic_vector(31 downto 0);
RX_TCP_WINDOW_SIZE: in std_logic_vector(15 downto 0);
RX_DEST_TCP_PORT_NO: in std_logic_vector(15 downto 0);
RX_DATA: out std_logic_vector(7 downto 0);
RX_DATA_VALID: out std_logic;
RX_SOF: out std_logic;
RX_STREAM_NO: out integer range 0 to (NTCPSTREAMS-1);
RX_EOF: out std_logic;
RX_FREE_SPACE: in SLV16xNTCPSTREAMStype;
TX_PACKET_SEQUENCE_START_OUT: out std_logic;
TX_DEST_MAC_ADDR_OUT: out std_logic_vector(47 downto 0);
TX_DEST_IP_ADDR_OUT: out std_logic_vector(127 downto 0);
TX_DEST_PORT_NO_OUT: out std_logic_vector(15 downto 0);
TX_SOURCE_PORT_NO_OUT: out std_logic_vector(15 downto 0);
TX_IPv4_6n_OUT: out std_logic;
TX_SEQ_NO_OUT: out std_logic_vector(31 downto 0);
TX_ACK_NO_OUT: out std_logic_vector(31 downto 0);
TX_ACK_WINDOW_LENGTH_OUT: out std_logic_vector(15 downto 0);
TX_FLAGS_OUT: out std_logic_vector(7 downto 0);
TX_PACKET_TYPE_OUT : out std_logic_vector(1 downto 0);
MAC_TX_EOF: in std_logic; -- need to know when packet tx is complete
RTS: out std_logic := '0';
EFF_RX_WINDOW_SIZE_PARTIAL: out std_logic_vector(16 downto 0);
EFF_RX_WINDOW_SIZE_PARTIAL_STREAM: out integer range 0 to (NTCPSTREAMS-1) := 0;
EFF_RX_WINDOW_SIZE_PARTIAL_VALID: out std_logic; -- 1 CLK-wide pulse to indicate that the above information is valid
TX_SEQ_NO: out SLV17xNTCPSTREAMStype;
RX_TCP_ACK_NO_D: out SLV17xNTCPSTREAMStype;
CONNECTED_FLAG: out std_logic_vector((NTCPSTREAMS-1) downto 0);
TX_STREAM_SEL: in integer range 0 to (NTCPSTREAMS-1) := 0;
TX_PAYLOAD_RTS: in std_logic;
TX_PAYLOAD_SIZE: in std_logic_vector(10 downto 0);
TP: out std_logic_vector(10 downto 1)
);
END COMPONENT;
COMPONENT TCP_TXBUF is
generic (
NBUFS: integer;
TX_IDLE_TIMEOUT: integer range 0 to 50;
MSS: std_logic_vector(15 downto 0)
);
Port (
--//-- CLK, RESET
CLK: in std_logic;
SYNC_RESET: in std_logic;
TICK_4US: in std_logic;
APP_DATA: in SLV8xNTCPSTREAMStype;
APP_DATA_VALID: in std_logic_vector((NTCPSTREAMS-1) downto 0);
APP_CTS: out std_logic_vector((NTCPSTREAMS-1) downto 0);
EFF_RX_WINDOW_SIZE_PARTIAL_IN: in std_logic_vector(16 downto 0);
EFF_RX_WINDOW_SIZE_PARTIAL_STREAM: in integer range 0 to (NTCPSTREAMS-1) := 0;
EFF_RX_WINDOW_SIZE_PARTIAL_VALID: in std_logic; -- 1 CLK-wide pulse to indicate that the above information is valid
TX_SEQ_NO_IN: in SLV17xNTCPSTREAMStype;
RX_TCP_ACK_NO_D: in SLV17xNTCPSTREAMStype;
CONNECTED_FLAG: in std_logic_vector((NTCPSTREAMS-1) downto 0);
TX_STREAM_SEL: out integer range 0 to (NTCPSTREAMS-1) := 0;
TX_PAYLOAD_RTS: out std_logic;
TX_PAYLOAD_CHECKSUM: out std_logic_vector(16 downto 0);
TX_PAYLOAD_SIZE: out std_logic_vector(10 downto 0);
TX_PAYLOAD_CTS: in std_logic;
TX_PAYLOAD_DATA: out std_logic_vector(7 downto 0);
TX_PAYLOAD_DATA_VALID: out std_logic;
MAC_TX_EOF: in std_logic; -- need to know when packet tx is complete
TP: out std_logic_vector(10 downto 1)
);
end COMPONENT;
COMPONENT TCP_TX
GENERIC (
MSS: std_logic_vector(15 downto 0);
IPv6_ENABLED: std_logic
);
PORT(
ASYNC_RESET : IN std_logic;
CLK : IN std_logic;
MAC_ADDR : IN std_logic_vector(47 downto 0);
IPv4_ADDR : IN std_logic_vector(31 downto 0);
IPv6_ADDR : IN std_logic_vector(127 downto 0);
TX_PACKET_SEQUENCE_START : IN std_logic;
TX_DEST_MAC_ADDR_IN : IN std_logic_vector(47 downto 0);
TX_DEST_IP_ADDR_IN : IN std_logic_vector(127 downto 0);
TX_DEST_PORT_NO_IN : IN std_logic_vector(15 downto 0);
TX_SOURCE_PORT_NO_IN : IN std_logic_vector(15 downto 0);
TX_IPv4_6n_IN : IN std_logic;
TX_SEQ_NO_IN : IN std_logic_vector(31 downto 0);
TX_ACK_NO_IN : IN std_logic_vector(31 downto 0);
TX_ACK_WINDOW_LENGTH_IN : IN std_logic_vector(15 downto 0);
IP_ID_IN : IN std_logic_vector(15 downto 0);
TX_FLAGS_IN : IN std_logic_vector(7 downto 0);
TX_PACKET_TYPE_IN : IN std_logic_vector(1 downto 0);
TX_PAYLOAD_DATA : IN std_logic_vector(7 downto 0);
TX_PAYLOAD_DATA_VALID : IN std_logic;
TX_PAYLOAD_RTS : IN std_logic;
TX_PAYLOAD_CTS : OUT std_logic;
TX_PAYLOAD_SIZE : IN std_logic_vector(10 downto 0);
TX_PAYLOAD_CHECKSUM: in std_logic_vector(16 downto 0);
MAC_TX_CTS : IN std_logic;
MAC_TX_DATA : OUT std_logic_vector(7 downto 0);
MAC_TX_DATA_VALID : OUT std_logic;
MAC_TX_EOF : OUT std_logic;
TP : OUT std_logic_vector(10 downto 1)
);
END COMPONENT;
COMPONENT TCP_RXBUFNDEMUX2
GENERIC (
NBUFS: integer
);
PORT(
SYNC_RESET : IN std_logic;
CLK : IN std_logic;
RX_DATA : IN std_logic_vector(7 downto 0);
RX_DATA_VALID : IN std_logic;
RX_SOF : IN std_logic;
RX_STREAM_NO: in integer range 0 to (NTCPSTREAMS-1);
RX_EOF : IN std_logic;
RX_FREE_SPACE: OUT SLV16xNTCPSTREAMStype;
RX_APP_DATA: out SLV8xNTCPSTREAMStype;
RX_APP_DATA_VALID: out std_logic_vector((NTCPSTREAMS-1) downto 0);
RX_APP_SOF: out std_logic_vector((NTCPSTREAMS-1) downto 0);
RX_APP_EOF: out std_logic_vector((NTCPSTREAMS-1) downto 0);
RX_APP_RTS: out std_logic_vector((NTCPSTREAMS-1) downto 0);
RX_APP_CTS: in std_logic_vector((NTCPSTREAMS-1) downto 0);
TP : OUT std_logic_vector(10 downto 1)
);
END COMPONENT;
--------------------------------------------------------
-- SIGNALS
--------------------------------------------------------
-- NOTATIONS:
-- _E as one-CLK early sample
-- _D as one-CLK delayed sample
-- _D2 as two-CLKs delayed sample
--//-- TIMERS -----------------------------
signal TICK_4US: std_logic := '0';
signal TICK_100MS_rt: std_logic := '0';
signal TICK_100MS: std_logic := '0';
--//-- MAC INTERFACE --------------
signal MAC_TX_DATA_VALID_local : std_logic := '0';
signal MAC_TX_EOF_FLAG : std_logic := '0';
signal MAC_TX_EOF_local : std_logic := '0';
--//-- PARSE INCOMING PACKET --------------
signal RX_TYPE: std_logic_vector(3 downto 0) := (others => '0');
signal RX_TYPE_RDY : std_logic := '0';
signal RX_IPv4_6n : std_logic := '0';
signal RX_IP_PROTOCOL : std_logic_vector(7 downto 0) := (others => '0');
signal RX_IP_PROTOCOL_RDY : std_logic := '0';
signal IP_RX_DATA : std_logic_vector(7 downto 0) := (others => '0');
signal IP_RX_DATA_VALID : std_logic := '0';
signal IP_RX_SOF : std_logic := '0';
signal IP_RX_EOF : std_logic := '0';
signal IP_BYTE_COUNT : std_logic_vector(15 downto 0) := (others => '0');
signal IP_HEADER_FLAG : std_logic := '0';
signal RX_UDP_CKSUM: std_logic_vector(16 downto 0) := (others => '0');
signal RX_UDP_CKSUM_RDY: std_logic := '0';
signal RX_TCP_HEADER_FLAG: std_logic := '0';
signal RX_TCP_FLAGS: std_logic_vector(7 downto 0) := (others => '0');
signal RX_TCP_CKSUM: std_logic_vector(16 downto 0) := (others => '0');
signal RX_TCP_SEQ_NO: std_logic_vector(31 downto 0) := (others => '0');
signal RX_TCP_ACK_NO: std_logic_vector(31 downto 0) := (others => '0');
signal RX_TCP_WINDOW_SIZE: std_logic_vector(15 downto 0) := (others => '0');
signal RX_DEST_TCP_PORT_NO: std_logic_vector(15 downto 0) := (others => '0');
signal TP_PARSING: std_logic_vector(10 downto 1);
signal RX_SOURCE_MAC_ADDR: std_logic_vector(47 downto 0) := (others => '0');
signal RX_SOURCE_IP_ADDR: std_logic_vector(127 downto 0) := (others => '0');
signal RX_SOURCE_TCP_PORT_NO: std_logic_vector(15 downto 0) := (others => '0');
signal RX_DEST_IP_ADDR: std_logic_vector(127 downto 0) := (others => '0');
signal IP_HEADER_CHECKSUM_VALID: std_logic := '0';
signal IP_HEADER_CHECKSUM_VALID_RDY: std_logic := '0';
--//-- ARP REPLY --------------
signal ARP_MAC_TX_DATA: std_logic_vector(7 downto 0) := x"00";
signal ARP_MAC_TX_DATA_VALID: std_logic := '0';
signal ARP_MAC_TX_EOF: std_logic := '0';
signal ARP_MAC_TX_CTS: std_logic := '0';
signal ARP_RTS: std_logic := '0';
signal TP_ARP: std_logic_vector(10 downto 1);
--//-- PING REPLY --------------
signal PING_MAC_TX_DATA: std_logic_vector(7 downto 0) := x"00";
signal PING_MAC_TX_DATA_VALID: std_logic := '0';
signal PING_MAC_TX_EOF: std_logic := '0';
signal PING_MAC_TX_CTS: std_logic := '0';
signal PING_RTS: std_logic := '0';
signal TP_PING: std_logic_vector(10 downto 1);
--//-- WHOIS ---------------------------------------------
signal WHOIS_IP_ADDR: std_logic_vector(31 downto 0) := (others => '0');
signal WHOIS_START: std_logic := '0';
signal WHOIS_RDY: std_logic := '0';
signal WHOIS_MAC_TX_DATA: std_logic_vector(7 downto 0) := x"00";
signal WHOIS_MAC_TX_DATA_VALID: std_logic := '0';
signal WHOIS_MAC_TX_EOF: std_logic := '0';
signal WHOIS_MAC_TX_CTS: std_logic := '0';
signal WHOIS_RTS: std_logic := '0';
signal TP_WHOIS: std_logic_vector(10 downto 1) := (others => '0');
--//-- ARP CACHE -----------------------------------------
signal RT_IP_ADDR: std_logic_vector(31 downto 0) := (others => '0');
signal RT_REQ_RTS: std_logic := '0';
signal RT_CTS: std_logic := '0';
signal RT_MAC_REPLY: std_logic_vector(47 downto 0) := (others => '0');
signal RT_MAC_RDY: std_logic := '0';
signal RT_NAK: std_logic := '0';
signal TP_ARP_CACHE2: std_logic_vector(10 downto 1) := (others => '0');
--//-- UDP RX ------------------------------------
signal TP_UDP_RX: std_logic_vector(10 downto 1) := (others => '0');
--//-- UDP TX ------------------------------------
signal UDP001_RT_REQ_RTS: std_logic := '0';
signal UDP001_RT_REQ_CTS: std_logic := '0';
signal UDP001_RT_IP_ADDR: std_logic_vector(31 downto 0) := (others => '0');
signal UDP001_RT_MAC_RDY: std_logic := '0';
signal UDP001_RT_NAK: std_logic := '0';
signal UDP001_MAC_TX_DATA: std_logic_vector(7 downto 0) := x"00";
signal UDP001_MAC_TX_DATA_VALID: std_logic := '0';
signal UDP001_MAC_TX_EOF: std_logic := '0';
signal UDP001_MAC_TX_CTS: std_logic := '0';
signal UDP001_RTS: std_logic := '0';
signal TP_UDP_TX: std_logic_vector(10 downto 1) := (others => '0');
signal UDP_TX_ACK_local: std_logic := '0';
signal UDP_TX_NAK_local: std_logic := '0';
--//-- TCP RX ------------------------------------
-- TCP server 001
signal TCP_LOCAL_PORTS: SLV16xNTCPSTREAMStype;
signal TCP001_MAC_TX_DATA: std_logic_vector(7 downto 0) := x"00";
signal TCP001_MAC_TX_DATA_VALID: std_logic := '0';
signal TCP001_MAC_TX_EOF: std_logic := '0';
signal TCP001_MAC_TX_CTS: std_logic := '0';
signal TCP001_RTS: std_logic := '0';
signal TCP001_RX_DATA: std_logic_vector(7 downto 0) := x"00";
signal TCP001_RX_DATA_VALID: std_logic := '0';
signal TCP001_RX_SOF: std_logic := '0';
signal TCP001_RX_STREAM_NO: integer range 0 to (NTCPSTREAMS-1);
signal TCP001_RX_EOF: std_logic := '0';
signal TCP001_RX_FREE_SPACE: SLV16xNTCPSTREAMStype;
signal TCP001_TX_PACKET_SEQUENCE_START: std_logic := '0';
signal TCP001_TX_DEST_MAC_ADDR: std_logic_vector(47 downto 0) := (others => '0');
signal TCP001_TX_DEST_IP_ADDR: std_logic_vector(127 downto 0) := (others => '0');
signal TCP001_TX_DEST_PORT_NO: std_logic_vector(15 downto 0) := (others => '0');
signal TCP001_TX_SOURCE_PORT_NO: std_logic_vector(15 downto 0) := (others => '0');
signal TCP001_TX_IPv4_6n: std_logic := '0';
signal TCP001_TX_SEQ_NO: std_logic_vector(31 downto 0) := (others => '0');
signal TCP001_TX_ACK_NO: std_logic_vector(31 downto 0) := (others => '0');
signal TCP001_TX_ACK_WINDOW_LENGTH: std_logic_vector(15 downto 0) := (others => '0');
signal TCP001_TX_FLAGS: std_logic_vector(7 downto 0) := (others => '0');
signal TCP001_TX_PACKET_TYPE: std_logic_vector(1 downto 0) := (others => '0');
signal TCP001_EFF_RX_WINDOW_SIZE_PARTIAL: std_logic_vector(16 downto 0) := (others => '0');
signal TCP001_EFF_RX_WINDOW_SIZE_PARTIAL_STREAM: integer range 0 to (NTCPSTREAMS-1);
signal TCP001_EFF_RX_WINDOW_SIZE_PARTIAL_VALID: std_logic := '0'; -- 1 CLK-wide pulse to indicate that the above information is valid
signal TCP001_TX_SEQ_NOxNTCPSTREAMS: SLV17xNTCPSTREAMStype;
signal TCP001_RX_ACK_NOxNTCPSTREAMS: SLV17xNTCPSTREAMStype;
signal TCP001_CONNECTED_FLAG: std_logic_vector((NTCPSTREAMS-1) downto 0) := (others => '0');
signal TCP001_TX_PAYLOAD_DATA: std_logic_vector(7 downto 0) := x"00";
signal TCP001_TX_PAYLOAD_DATA_VALID: std_logic := '0';
signal TCP001_TX_PAYLOAD_RTS: std_logic := '0';
signal TCP001_TX_PAYLOAD_CTS: std_logic := '0';
signal TCP001_TX_PAYLOAD_SIZE: std_logic_vector(10 downto 0) := (others => '0');
signal TCP001_TX_PAYLOAD_CHECKSUM: std_logic_vector(16 downto 0) := "0" & x"0000";
signal TCP001_TX_STREAM_SEL: integer range 0 to (NTCPSTREAMS-1);
signal TCP001_TCP_TX_CTS: std_logic_vector((NTCPSTREAMS-1) downto 0) := (others => '0');
signal TP_TCP_SERVER: std_logic_vector(10 downto 1);
signal TP_TCP_TXBUF: std_logic_vector(10 downto 1);
-- TCP server 002
--signal TCP_LOCAL_PORTS: SLV16xNTCPSTREAMStype;
--signal TCP002_MAC_TX_DATA: std_logic_vector(7 downto 0) := x"00";
--signal TCP002_MAC_TX_DATA_VALID: std_logic := '0';
--signal TCP002_MAC_TX_EOF: std_logic := '0';
--signal TCP002_MAC_TX_CTS: std_logic := '0';
--signal TCP002_RTS: std_logic := '0';
--signal TCP002_RX_DATA: std_logic_vector(7 downto 0) := x"00";
--signal TCP002_RX_DATA_VALID: std_logic := '0';
--signal TCP002_RX_SOF: std_logic := '0';
--signal TCP002_RX_STREAM_NO: integer range 0 to (NTCPSTREAMS-1);
--signal TCP002_RX_EOF: std_logic := '0';
--signal TCP002_RX_FREE_SPACE: std_logic_vector(15 downto 0) := x"0400";
--signal TCP002_TX_PACKET_SEQUENCE_START: std_logic := '0';
--signal TCP002_TX_DEST_MAC_ADDR: std_logic_vector(47 downto 0) := (others => '0');
--signal TCP002_TX_DEST_IP_ADDR: std_logic_vector(127 downto 0) := (others => '0');
--signal TCP002_TX_DEST_PORT_NO: std_logic_vector(15 downto 0) := (others => '0');
--signal TCP002_TX_SOURCE_PORT_NO: std_logic_vector(15 downto 0) := (others => '0');
--signal TCP002_TX_IPv4_6n: std_logic := '0';
--signal TCP002_TX_SEQ_NO: std_logic_vector(31 downto 0) := (others => '0');
--signal TCP002_TX_ACK_NO: std_logic_vector(31 downto 0) := (others => '0');
--signal TCP002_TX_ACK_WINDOW_LENGTH: std_logic_vector(15 downto 0) := (others => '0');
--signal TCP002_TX_FLAGS: std_logic_vector(7 downto 0) := (others => '0');
--signal TCP002_TX_PACKET_TYPE: std_logic_vector(1 downto 0) := (others => '0');
--signal TCP002_EFF_RX_WINDOW_SIZE_PARTIAL: std_logic_vector(15 downto 0) := (others => '0');
--signal TCP002_EFF_RX_WINDOW_SIZE_PARTIAL_STREAM: integer range 0 to (NTCPSTREAMS-1);
--signal TCP002_EFF_RX_WINDOW_SIZE_PARTIAL_VALID: std_logic := '0'; -- 1 CLK-wide pulse to indicate that the above information is valid
--signal TCP002_TX_SEQ_NOxNTCPSTREAMS: SLV16xNTCPSTREAMStype;
--signal TCP002_RX_ACK_NOxNTCPSTREAMS: SLV16xNTCPSTREAMStype;
--signal TCP002_CONNECTED_FLAG: std_logic_vector((NTCPSTREAMS-1) downto 0) := (others => '0');
--signal TCP002_TX_PAYLOAD_DATA: std_logic_vector(7 downto 0) := x"00";
--signal TCP002_TX_PAYLOAD_DATA_VALID: std_logic := '0';
--signal TCP002_TX_PAYLOAD_RTS: std_logic := '0';
--signal TCP002_TX_PAYLOAD_CTS: std_logic := '0';
--signal TCP002_TX_PAYLOAD_SIZE: std_logic_vector(10 downto 0) := (others => '0');
--signal TCP002_TX_PAYLOAD_CHECKSUM: std_logic_vector(16 downto 0) := "0" & x"0000";
--signal TCP002_TX_STREAM_SEL: integer range 0 to (NTCPSTREAMS-1);
--signal TCP002_TCP_TX_CTS: std_logic_vector((NTCPSTREAMS-1) downto 0) := (others => '0');
--//-- APP -> TCP TX BUFFER
signal TCP_TXBUF_DATA: std_logic_vector(7 downto 0) := x"00";
signal TCP_TXBUF_DATA_VALID: std_logic := '0';
signal TCP_TXBUF_SOF: std_logic := '0';
signal TCP_TXBUF_EOF: std_logic := '0';
signal TCP_TXBUF_RTS: std_logic := '0';
signal TCP_TXBUF_CTS: std_logic := '0';
--???signal TCP_TXBUF_PAYLOAD_SIZE: std_logic_vector(15 downto 0) := x"0000";
signal TCP_TXBUF_PARTIAL_CKSUM: std_logic_vector(15 downto 0) := x"0000";
signal TCP_TXBUF_RPTR: std_logic_vector(31 downto 0) := x"00000000";
signal TCP_TXBUF_RPTR_CONFIRMED: std_logic_vector(31 downto 0) := x"00000000";
--//-- TRANSMISSION ARBITER --------------
signal IP_ID: std_logic_vector(15 downto 0) := x"0000";
signal TX_MUX_STATE: integer range 0 to 10; -- up to 6 protocol engines. Increase size if more.
--//-- ROUTING TABLE ARBITER --------------
signal RT_MUX_STATE: integer range 0 to 10;
-- 1 + number of transmit components vying for access to the routing table. Adjust as needed.
--//-- TEST POINTS
------------------------------------------------------
-- IMPLEMENTATION
--------------------------------------------------------
begin
--//-- TIMERS -----------------------------
Inst_TIMER_4US: TIMER_4US
GENERIC MAP(
CLK_FREQUENCY => CLK_FREQUENCY
)
PORT MAP(
ASYNC_RESET => ASYNC_RESET,
CLK => CLK,
TICK_4US => TICK_4US,
TICK_100MS => TICK_100MS_rt
);
TICK_100MS <= TICK_4US when (SIMULATION = '1') else TICK_100MS_rt; -- to accelerate simulations
--//-- PARSE INCOMING PACKET --------------
-- Code is common to all protocols. Extracts key information from incoming packets.
Inst_PACKET_PARSING: PACKET_PARSING
GENERIC MAP(
IPv6_ENABLED => IPv6_ENABLED,
SIMULATION => SIMULATION
)
PORT MAP(
ASYNC_RESET => ASYNC_RESET,
CLK => CLK,
TICK_4US => TICK_4US,
MAC_RX_DATA => MAC_RX_DATA,
MAC_RX_DATA_VALID => MAC_RX_DATA_VALID,
MAC_RX_SOF => MAC_RX_SOF,
MAC_RX_EOF => MAC_RX_EOF,
IPv4_ADDR => IPv4_ADDR,
IPv6_ADDR => IPv6_ADDR,
IP_RX_DATA => IP_RX_DATA,
IP_RX_DATA_VALID => IP_RX_DATA_VALID,
IP_RX_SOF => IP_RX_SOF,
IP_RX_EOF => IP_RX_EOF,
IP_BYTE_COUNT => IP_BYTE_COUNT,
IP_HEADER_FLAG => IP_HEADER_FLAG,
RX_TYPE => RX_TYPE,
RX_TYPE_RDY => RX_TYPE_RDY,
RX_IPv4_6n => RX_IPv4_6n,
RX_IP_PROTOCOL => RX_IP_PROTOCOL,
RX_IP_PROTOCOL_RDY => RX_IP_PROTOCOL_RDY,
VALID_DEST_IP => open,
VALID_DEST_IP_RDY => open,
IP_HEADER_CHECKSUM_VALID => IP_HEADER_CHECKSUM_VALID,
IP_HEADER_CHECKSUM_VALID_RDY => IP_HEADER_CHECKSUM_VALID_RDY,
RX_SOURCE_MAC_ADDR => RX_SOURCE_MAC_ADDR,
RX_SOURCE_IP_ADDR => RX_SOURCE_IP_ADDR,
RX_SOURCE_TCP_PORT_NO => RX_SOURCE_TCP_PORT_NO,
RX_DEST_IP_ADDR => RX_DEST_IP_ADDR,
RX_DEST_TCP_PORT_NO => RX_DEST_TCP_PORT_NO,
RX_UDP_CKSUM => RX_UDP_CKSUM,
RX_UDP_CKSUM_RDY => RX_UDP_CKSUM_RDY,
-- RX_TCP_BYTE_COUNT => RX_TCP_BYTE_COUNT,
RX_TCP_HEADER_FLAG => RX_TCP_HEADER_FLAG,
RX_TCP_FLAGS => RX_TCP_FLAGS,
RX_TCP_CKSUM => RX_TCP_CKSUM,
RX_TCP_SEQ_NO => RX_TCP_SEQ_NO,
RX_TCP_ACK_NO => RX_TCP_ACK_NO,
RX_TCP_WINDOW_SIZE => RX_TCP_WINDOW_SIZE,
CS1 => open,
CS1_CLK => open,
CS2 => open,
CS2_CLK => open,
TP => TP_PARSING
);
--//-- ARP REPLY --------------
-- Instantiated once per PHY. IPv4-only. Use NDP for IPv6.
Inst_ARP: ARP
PORT MAP(
ASYNC_RESET => ASYNC_RESET,
CLK => CLK,
MAC_RX_DATA => MAC_RX_DATA,
MAC_RX_DATA_VALID => MAC_RX_DATA_VALID,
MAC_RX_SOF => MAC_RX_SOF,
MAC_RX_EOF => MAC_RX_EOF,
MAC_ADDR => MAC_ADDR,
IPv4_ADDR => IPv4_ADDR,
RX_TYPE => RX_TYPE,
RX_TYPE_RDY => RX_TYPE_RDY,
RX_SOURCE_MAC_ADDR => RX_SOURCE_MAC_ADDR,
RX_SOURCE_IP_ADDR => RX_SOURCE_IP_ADDR(31 downto 0),
MAC_TX_DATA => ARP_MAC_TX_DATA,
MAC_TX_DATA_VALID => ARP_MAC_TX_DATA_VALID,
MAC_TX_EOF => ARP_MAC_TX_EOF,
MAC_TX_CTS => ARP_MAC_TX_CTS,
RTS => ARP_RTS,
TP => TP_ARP
);
--//-- PING REPLY --------------
-- Instantiated once per PHY.
Inst_PING: PING
GENERIC MAP(
IPv6_ENABLED => IPv6_ENABLED,
MAX_PING_SIZE => x"0200" -- 512 byte threshold for ping requests
)
PORT MAP(
ASYNC_RESET => ASYNC_RESET,
CLK => CLK,
MAC_RX_DATA => MAC_RX_DATA,
MAC_RX_DATA_VALID => MAC_RX_DATA_VALID,
MAC_RX_SOF => MAC_RX_SOF,
MAC_RX_EOF => MAC_RX_EOF,
MAC_ADDR => MAC_ADDR,
IPv4_ADDR => IPv4_ADDR,
IPv6_ADDR => IPv6_ADDR,
RX_IPv4_6n => RX_IPv4_6n,
RX_IP_PROTOCOL => RX_IP_PROTOCOL,
RX_IP_PROTOCOL_RDY => RX_IP_PROTOCOL_RDY,
IP_RX_DATA_VALID => IP_RX_DATA_VALID,
IP_RX_EOF => IP_RX_EOF,
MAC_TX_DATA => PING_MAC_TX_DATA,
MAC_TX_DATA_VALID => PING_MAC_TX_DATA_VALID,
MAC_TX_EOF => PING_MAC_TX_EOF,
MAC_TX_CTS => PING_MAC_TX_CTS,
RTS => PING_RTS,
TP => TP_PING
);
--//-- WHOIS ---------------------------------------------
-- Sends ARP requests
-- Currently only used by UDP tx
WHOIS2_X: if(NUDPTX /= 0) generate
WHOIS2_001: WHOIS2 PORT MAP(
SYNC_RESET => SYNC_RESET,
CLK => CLK,
WHOIS_IP_ADDR => WHOIS_IP_ADDR,
WHOIS_START => WHOIS_START,
WHOIS_RDY => WHOIS_RDY, -- unused
MAC_ADDR => MAC_ADDR,
IPv4_ADDR => IPv4_ADDR,
MAC_TX_DATA => WHOIS_MAC_TX_DATA,
MAC_TX_DATA_VALID => WHOIS_MAC_TX_DATA_VALID,
MAX_TX_EOF => WHOIS_MAC_TX_EOF,
MAC_TX_CTS => WHOIS_MAC_TX_CTS,
RTS => WHOIS_RTS,
TP => TP_WHOIS
);
end generate;
--//-- ARP CACHE (ROUTING TABLE) -----------------------------------------
-- Routing table mapping destination IP addresses and associated MAC addresses.
-- Currently only used by UDP tx
ARP_CACHE2_X: if(NUDPTX /= 0) generate
ARP_CACHE2_001: ARP_CACHE2 PORT MAP(
SYNC_RESET => SYNC_RESET,
CLK => CLK,
TICK_100MS => TICK_100MS,
RT_IP_ADDR => RT_IP_ADDR,
RT_REQ_RTS => RT_REQ_RTS,
RT_CTS => RT_CTS,
RT_MAC_REPLY => RT_MAC_REPLY,
RT_MAC_RDY => RT_MAC_RDY,
RT_NAK => RT_NAK,
MAC_ADDR => MAC_ADDR,
IPv4_ADDR => IPv4_ADDR,
SUBNET_MASK => SUBNET_MASK,
GATEWAY_IP_ADDR => GATEWAY_IP_ADDR,
WHOIS_IP_ADDR => WHOIS_IP_ADDR,
WHOIS_START => WHOIS_START,
RX_SOURCE_ADDR_RDY => MAC_RX_EOF,
RX_SOURCE_MAC_ADDR => RX_SOURCE_MAC_ADDR,
RX_SOURCE_IP_ADDR => RX_SOURCE_IP_ADDR(31 downto 0), -- IPv4 only
SREG1 => open,
SREG2 => open,
SREG3 => open,
SREG4 => open,
SREG5 => open,
SREG6 => open,
TP => TP_ARP_CACHE2
);
end generate;
--//-- UDP RX to Serial (Monitoring and control) ---------
Inst_UDP2SERIAL: UDP2SERIAL
GENERIC MAP(
PORT_NO => x"0405", --1029
CLK_FREQUENCY => CLK_FREQUENCY
)
PORT MAP(
ASYNC_RESET => ASYNC_RESET,
CLK => CLK,
IP_RX_DATA => IP_RX_DATA,
IP_RX_DATA_VALID => IP_RX_DATA_VALID,
IP_RX_SOF => IP_RX_SOF,
IP_RX_EOF => IP_RX_EOF,
IP_HEADER_FLAG => IP_HEADER_FLAG,
RX_IP_PROTOCOL => RX_IP_PROTOCOL,
RX_IP_PROTOCOL_RDY => RX_IP_PROTOCOL_RDY,
SERIAL_OUT => open,
TP => open
);
--//-- UDP RX ------------------------------------
UDP_RX_X: if(NUDPRX /= 0) generate
UDP_RX_001: UDP_RX
PORT MAP(
ASYNC_RESET => ASYNC_RESET,
CLK => CLK,
IP_RX_DATA => IP_RX_DATA,
IP_RX_DATA_VALID => IP_RX_DATA_VALID,
IP_RX_SOF => IP_RX_SOF,
IP_RX_EOF => IP_RX_EOF,
IP_BYTE_COUNT => IP_BYTE_COUNT,
IP_HEADER_FLAG => IP_HEADER_FLAG,
RX_IP_PROTOCOL => RX_IP_PROTOCOL,
RX_IP_PROTOCOL_RDY => RX_IP_PROTOCOL_RDY,
RX_UDP_CKSUM => RX_UDP_CKSUM,
RX_UDP_CKSUM_RDY => RX_UDP_CKSUM_RDY,
-- configuration
PORT_NO => UDP_RX_DEST_PORT_NO,
-- Application interface
APP_DATA => UDP_RX_DATA,
APP_DATA_VALID => UDP_RX_DATA_VALID,
APP_SOF => UDP_RX_SOF,
APP_EOF => UDP_RX_EOF,
APP_SRC_UDP_PORT => open,
TP => TP_UDP_RX
);
end generate;
--//-- UDP TX ------------------------------------
UDP_TX_NZ: if(NUDPTX /= 0) generate
UDP_TX_001: UDP_TX
GENERIC MAP(
NBUFS => 1,
IPv6_ENABLED => '0'
)
PORT MAP(
CLK => CLK,
SYNC_RESET => SYNC_RESET,
TICK_4US => TICK_4US,
-- Application interface
APP_DATA => UDP_TX_DATA,
APP_DATA_VALID => UDP_TX_DATA_VALID,
APP_SOF => UDP_TX_SOF,
APP_EOF => UDP_TX_EOF,
APP_CTS => UDP_TX_CTS,
ACK => UDP_TX_ACK_local,
NAK => UDP_TX_NAK_local,
DEST_IP_ADDR => UDP_TX_DEST_IP_ADDR,
DEST_PORT_NO => UDP_TX_DEST_PORT_NO,
SOURCE_PORT_NO => UDP_TX_SOURCE_PORT_NO,
IPv4_6n => '1',
-- Configuration
MAC_ADDR => MAC_ADDR,
IPv4_ADDR => IPv4_ADDR,
IPv6_ADDR => IPv6_ADDR,
IP_ID => IP_ID,
-- Routing
RT_IP_ADDR => UDP001_RT_IP_ADDR,
RT_REQ_RTS => UDP001_RT_REQ_RTS,
RT_REQ_CTS => UDP001_RT_REQ_CTS,
RT_MAC_REPLY => RT_MAC_REPLY,
RT_MAC_RDY => UDP001_RT_MAC_RDY,
RT_NAK => UDP001_RT_NAK,
-- MAC interface
MAC_TX_DATA => UDP001_MAC_TX_DATA,
MAC_TX_DATA_VALID => UDP001_MAC_TX_DATA_VALID,
MAC_TX_EOF => UDP001_MAC_TX_EOF,
MAC_TX_CTS => UDP001_MAC_TX_CTS,
RTS => UDP001_RTS,
TP => TP_UDP_TX
);
end generate;
UDP_TX_ACK <= UDP_TX_ACK_local;
UDP_TX_NAK <= UDP_TX_NAK_local;
--//-- TCP SERVER 001 ------------------------------------
-- declare the port number for each TCP stream (NTCPSTREAMS streams, declared in com5402pkg)
TCP_SERVER_X: if (NTCPSTREAMS /= 0) generate
-- TCP_SERVER does the conversion between TCP port number and stream number (and vice versa)
TCP_LOCAL_PORTS(0) <= x"0400"; -- port 1024
TCP_LOCAL_PORTS(1) <= x"0401"; -- port 1025
--TCP_LOCAL_PORTS(2) <= x"0402"; -- port 1026
TCP_SERVER_001: TCP_SERVER
GENERIC MAP(
MSS => x"05B4", -- 1460 bytes
IPv6_ENABLED => IPv6_ENABLED,
SIMULATION => SIMULATION
)
PORT MAP(
CLK => CLK,
SYNC_RESET => SYNC_RESET,
TICK_4US => TICK_4US,
TICK_100MS => TICK_100MS,
MAC_ADDR => MAC_ADDR,
TCP_LOCAL_PORTS => TCP_LOCAL_PORTS,
CONNECTION_RESET => CONNECTION_RESET,
IP_RX_DATA => IP_RX_DATA,
IP_RX_DATA_VALID => IP_RX_DATA_VALID,
IP_RX_SOF => IP_RX_SOF,
IP_RX_EOF => IP_RX_EOF,
IP_BYTE_COUNT => IP_BYTE_COUNT,
IP_HEADER_FLAG => IP_HEADER_FLAG,
RX_IPv4_6n => RX_IPv4_6n,
RX_IP_PROTOCOL => RX_IP_PROTOCOL,
RX_IP_PROTOCOL_RDY => RX_IP_PROTOCOL_RDY,
RX_SOURCE_MAC_ADDR => RX_SOURCE_MAC_ADDR,
RX_SOURCE_IP_ADDR => RX_SOURCE_IP_ADDR,
RX_SOURCE_TCP_PORT_NO => RX_SOURCE_TCP_PORT_NO,
-- RX_TCP_BYTE_COUNT => RX_TCP_BYTE_COUNT,
RX_TCP_HEADER_FLAG => RX_TCP_HEADER_FLAG,
RX_TCP_FLAGS => RX_TCP_FLAGS,
RX_TCP_CKSUM => RX_TCP_CKSUM,
RX_TCP_SEQ_NO => RX_TCP_SEQ_NO,
RX_TCP_ACK_NO => RX_TCP_ACK_NO,
RX_TCP_WINDOW_SIZE => RX_TCP_WINDOW_SIZE,
RX_DEST_TCP_PORT_NO => RX_DEST_TCP_PORT_NO,
RX_DATA => TCP001_RX_DATA,
RX_DATA_VALID => TCP001_RX_DATA_VALID,
RX_SOF => TCP001_RX_SOF,
RX_STREAM_NO => TCP001_RX_STREAM_NO,
RX_EOF => TCP001_RX_EOF,
RX_FREE_SPACE => TCP001_RX_FREE_SPACE,
TX_PACKET_SEQUENCE_START_OUT => TCP001_TX_PACKET_SEQUENCE_START,
TX_DEST_MAC_ADDR_OUT => TCP001_TX_DEST_MAC_ADDR,
TX_DEST_IP_ADDR_OUT => TCP001_TX_DEST_IP_ADDR,
TX_DEST_PORT_NO_OUT => TCP001_TX_DEST_PORT_NO,
TX_SOURCE_PORT_NO_OUT => TCP001_TX_SOURCE_PORT_NO,
TX_IPv4_6n_OUT => TCP001_TX_IPv4_6n,
TX_SEQ_NO_OUT => TCP001_TX_SEQ_NO,
TX_ACK_NO_OUT => TCP001_TX_ACK_NO,
TX_ACK_WINDOW_LENGTH_OUT => TCP001_TX_ACK_WINDOW_LENGTH,
TX_FLAGS_OUT => TCP001_TX_FLAGS,
TX_PACKET_TYPE_OUT => TCP001_TX_PACKET_TYPE,
MAC_TX_EOF => TCP001_MAC_TX_EOF,
RTS => TCP001_RTS,
EFF_RX_WINDOW_SIZE_PARTIAL => TCP001_EFF_RX_WINDOW_SIZE_PARTIAL,
EFF_RX_WINDOW_SIZE_PARTIAL_STREAM => TCP001_EFF_RX_WINDOW_SIZE_PARTIAL_STREAM,
EFF_RX_WINDOW_SIZE_PARTIAL_VALID => TCP001_EFF_RX_WINDOW_SIZE_PARTIAL_VALID,
TX_SEQ_NO => TCP001_TX_SEQ_NOxNTCPSTREAMS,
RX_TCP_ACK_NO_D => TCP001_RX_ACK_NOxNTCPSTREAMS,
TX_STREAM_SEL => TCP001_TX_STREAM_SEL,
TX_PAYLOAD_RTS => TCP001_TX_PAYLOAD_RTS,
TX_PAYLOAD_SIZE => TCP001_TX_PAYLOAD_SIZE,
CONNECTED_FLAG => TCP001_CONNECTED_FLAG,
TP => TP_TCP_SERVER
);
-- assemble tx packet (MAC/IP/TCP)
Inst_TCP_TX: TCP_TX
GENERIC MAP(
MSS => x"05B4", -- 1460 bytes
IPv6_ENABLED => IPv6_ENABLED
)
PORT MAP(
ASYNC_RESET => ASYNC_RESET,
CLK => CLK,
MAC_ADDR => MAC_ADDR,
IPv4_ADDR => IPv4_ADDR,
IPv6_ADDR => IPv6_ADDR,
TX_PACKET_SEQUENCE_START => TCP001_TX_PACKET_SEQUENCE_START,
TX_DEST_MAC_ADDR_IN => TCP001_TX_DEST_MAC_ADDR,
TX_DEST_IP_ADDR_IN => TCP001_TX_DEST_IP_ADDR,
TX_DEST_PORT_NO_IN => TCP001_TX_DEST_PORT_NO,
TX_SOURCE_PORT_NO_IN => TCP001_TX_SOURCE_PORT_NO,
TX_IPv4_6n_IN => TCP001_TX_IPv4_6n,
TX_SEQ_NO_IN => TCP001_TX_SEQ_NO,
TX_ACK_NO_IN => TCP001_TX_ACK_NO,
TX_ACK_WINDOW_LENGTH_IN => TCP001_TX_ACK_WINDOW_LENGTH,
IP_ID_IN => IP_ID,
TX_FLAGS_IN => TCP001_TX_FLAGS,
TX_PACKET_TYPE_IN => TCP001_TX_PACKET_TYPE,
TX_PAYLOAD_DATA => TCP001_TX_PAYLOAD_DATA,
TX_PAYLOAD_DATA_VALID => TCP001_TX_PAYLOAD_DATA_VALID,
TX_PAYLOAD_RTS => TCP001_TX_PAYLOAD_RTS,
TX_PAYLOAD_CTS => TCP001_TX_PAYLOAD_CTS,
TX_PAYLOAD_SIZE => TCP001_TX_PAYLOAD_SIZE,
TX_PAYLOAD_CHECKSUM => TCP001_TX_PAYLOAD_CHECKSUM,
MAC_TX_DATA => TCP001_MAC_TX_DATA,
MAC_TX_DATA_VALID => TCP001_MAC_TX_DATA_VALID,
MAC_TX_EOF => TCP001_MAC_TX_EOF,
MAC_TX_CTS => TCP001_MAC_TX_CTS,
TP => open
);
Inst_TCP_RXBUFNDEMUX2: TCP_RXBUFNDEMUX2
GENERIC MAP(
NBUFS => 8 -- must be large enough to include 2 MSS per enabled TCP stream. Min = 2. Recommended 4 or 8.
)
PORT MAP(
SYNC_RESET => SYNC_RESET,
CLK => CLK,
RX_DATA => TCP001_RX_DATA,
RX_DATA_VALID => TCP001_RX_DATA_VALID,
RX_SOF => TCP001_RX_SOF,
RX_STREAM_NO => TCP001_RX_STREAM_NO,
RX_EOF => TCP001_RX_EOF,
RX_FREE_SPACE => TCP001_RX_FREE_SPACE,
RX_APP_DATA => TCP_RX_DATA,
RX_APP_DATA_VALID => TCP_RX_DATA_VALID,
RX_APP_SOF => open,
RX_APP_EOF => open,
RX_APP_CTS => TCP_RX_CTS,
RX_APP_RTS => TCP_RX_RTS,
TP => open
);
Inst_TCP_TXBUF: TCP_TXBUF
GENERIC MAP(
NBUFS => 8,
TX_IDLE_TIMEOUT => TX_IDLE_TIMEOUT,
MSS => x"05B4" -- 1460 bytes, consistent with Ethernet MTU of 1500 bytes.
)
PORT MAP(
CLK => CLK,
SYNC_RESET => SYNC_RESET,
TICK_4US => TICK_4US,
-- application interface -------
APP_DATA => TCP_TX_DATA,
APP_DATA_VALID => TCP_TX_DATA_VALID,
APP_CTS => TCP001_TCP_TX_CTS,
-- TCP_SERVER interface -------
EFF_RX_WINDOW_SIZE_PARTIAL_IN => TCP001_EFF_RX_WINDOW_SIZE_PARTIAL,
EFF_RX_WINDOW_SIZE_PARTIAL_STREAM => TCP001_EFF_RX_WINDOW_SIZE_PARTIAL_STREAM,
EFF_RX_WINDOW_SIZE_PARTIAL_VALID => TCP001_EFF_RX_WINDOW_SIZE_PARTIAL_VALID,
TX_SEQ_NO_IN => TCP001_TX_SEQ_NOxNTCPSTREAMS,
RX_TCP_ACK_NO_D => TCP001_RX_ACK_NOxNTCPSTREAMS,
CONNECTED_FLAG => TCP001_CONNECTED_FLAG,
TX_STREAM_SEL => TCP001_TX_STREAM_SEL,
-- TCP_TX interface -------
TX_PAYLOAD_DATA => TCP001_TX_PAYLOAD_DATA,
TX_PAYLOAD_DATA_VALID => TCP001_TX_PAYLOAD_DATA_VALID,
TX_PAYLOAD_RTS => TCP001_TX_PAYLOAD_RTS,
TX_PAYLOAD_CTS => TCP001_TX_PAYLOAD_CTS,
TX_PAYLOAD_SIZE => TCP001_TX_PAYLOAD_SIZE,
TX_PAYLOAD_CHECKSUM => TCP001_TX_PAYLOAD_CHECKSUM,
MAC_TX_EOF => TCP001_MAC_TX_EOF,
TP => TP_TCP_TXBUF
);
TCP_TX_CTS <= TCP001_TCP_TX_CTS;
end generate;
--//-- IP ID generation
-- Increment IP ID every time an IP datagram is sent
IP_ID_GEN_001: process(ASYNC_RESET, CLK)
begin
if(ASYNC_RESET = '1') then
IP_ID <= (others => '0');
elsif rising_edge(CLK) then
if(TCP001_MAC_TX_EOF = '1') or (UDP001_MAC_TX_EOF = '1') then
-- if(TCP001_MAC_TX_EOF = '1') or (TCP002_MAC_TX_EOF = '1') or (UDP001_MAC_TX_EOF = '1') then
-- increment every time an IP packet is send.
-- Adjust as needed when other IP/UDP/TCP components are instantiated
IP_ID <= IP_ID + 1;
end if;
end if;
end process;
--//-- TRANSMISSION ARBITER --------------
-- determines the source for the next packet to be transmitted.
-- State machine to prevent overlapping between two packets ready...
-- For example, one has to wait until a UDP packet has completed transmission
-- before starting to send a TCP packet.
TX_MUX_001: process(CLK)
begin
if rising_edge(CLK) then
if(SYNC_RESET = '1') then
TX_MUX_STATE <= 0; -- idle
elsif(TX_MUX_STATE = 0) and (MAC_TX_CTS = '1') then
-- from idle to ...
if(ARP_RTS = '1') then
TX_MUX_STATE <= 1; -- enable ARP response
elsif(PING_RTS = '1') then
TX_MUX_STATE <= 2; -- enable PING response
elsif(TCP001_RTS = '1') and (NTCPSTREAMS /= 0) then
TX_MUX_STATE <= 3; -- enable TCP001 transmission
elsif(WHOIS_RTS = '1') and (NUDPTX /= 0) then
TX_MUX_STATE <= 4; -- enable WHOIS transmission
elsif(UDP001_RTS = '1') and (NUDPTX /= 0) then
TX_MUX_STATE <= 5; -- enable UDP001 transmission (duplicate as needed)
-- elsif(TCP002_RTS = '1') and (NTCPSTREAMS /= 0) then
-- TX_MUX_STATE <= 6; -- enable TCP002 transmission
end if;
-- Done transmitting. go from ... to idle
elsif(TX_MUX_STATE = 1) and (ARP_MAC_TX_EOF = '1') then
TX_MUX_STATE <= 0; -- idle
elsif(TX_MUX_STATE = 2) and (PING_MAC_TX_EOF = '1') then
TX_MUX_STATE <= 0; -- idle
elsif(TX_MUX_STATE = 3) and (TCP001_MAC_TX_EOF = '1') and (NTCPSTREAMS /= 0) then
TX_MUX_STATE <= 0; -- idle
elsif(TX_MUX_STATE = 4) and (WHOIS_MAC_TX_EOF = '1') and (NUDPTX /= 0) then
TX_MUX_STATE <= 0; -- idle
elsif(TX_MUX_STATE = 5) and (UDP001_MAC_TX_EOF = '1') and (NUDPTX /= 0) then -- (duplicate as needed)
TX_MUX_STATE <= 0; -- idle
-- elsif(TX_MUX_STATE = 6) and (TCP002_MAC_TX_EOF = '1') and (NTCPSTREAMS /= 0) then
-- TX_MUX_STATE <= 0; -- idle
end if;
end if;
end process;
TX_MUX_002: process(TX_MUX_STATE, ARP_MAC_TX_EOF, ARP_MAC_TX_DATA_VALID, ARP_MAC_TX_DATA,
PING_MAC_TX_EOF, PING_MAC_TX_DATA_VALID, PING_MAC_TX_DATA,
TCP001_MAC_TX_EOF, TCP001_MAC_TX_DATA_VALID, TCP001_MAC_TX_DATA,
WHOIS_MAC_TX_DATA, WHOIS_MAC_TX_DATA_VALID, WHOIS_MAC_TX_EOF,
UDP001_MAC_TX_DATA, UDP001_MAC_TX_DATA_VALID, UDP001_MAC_TX_EOF)
begin
case(TX_MUX_STATE) is
when (1) =>
MAC_TX_DATA <= ARP_MAC_TX_DATA;
MAC_TX_DATA_VALID_local <= ARP_MAC_TX_DATA_VALID;
MAC_TX_EOF_local <= ARP_MAC_TX_EOF;
when (2) =>
MAC_TX_DATA <= PING_MAC_TX_DATA;
MAC_TX_DATA_VALID_local <= PING_MAC_TX_DATA_VALID;
MAC_TX_EOF_local <= PING_MAC_TX_EOF;
when (3) =>
MAC_TX_DATA <= TCP001_MAC_TX_DATA;
MAC_TX_DATA_VALID_local <= TCP001_MAC_TX_DATA_VALID;
MAC_TX_EOF_local <= TCP001_MAC_TX_EOF;
when (4) =>
MAC_TX_DATA <= WHOIS_MAC_TX_DATA;
MAC_TX_DATA_VALID_local <= WHOIS_MAC_TX_DATA_VALID;
MAC_TX_EOF_local <= WHOIS_MAC_TX_EOF;
when (5) =>
MAC_TX_DATA <= UDP001_MAC_TX_DATA;
MAC_TX_DATA_VALID_local <= UDP001_MAC_TX_DATA_VALID;
MAC_TX_EOF_local <= UDP001_MAC_TX_EOF;
-- when (6) =>
-- MAC_TX_DATA <= TCP002_MAC_TX_DATA;
-- MAC_TX_DATA_VALID_local <= TCP002_MAC_TX_DATA_VALID;
-- MAC_TX_EOF_local <= TCP002_MAC_TX_EOF;
when others =>
MAC_TX_DATA <= (others => '0');
MAC_TX_DATA_VALID_local <= '0';
MAC_TX_EOF_local <= '0';
end case;
end process;
MAC_TX_DATA_VALID <= MAC_TX_DATA_VALID_local;
MAC_TX_EOF <= MAC_TX_EOF_local;
-- reconstruct a SOF pulse for local loopback
SOF_GEN: process(CLK)
begin
if rising_edge(CLK) then
if(SYNC_RESET = '1') then
MAC_TX_EOF_FLAG <= '1';
elsif(MAC_TX_EOF_local = '1') then
MAC_TX_EOF_FLAG <= '1';
elsif(MAC_TX_DATA_VALID_local = '1') then
MAC_TX_EOF_FLAG <= '0';
end if;
end if;
end process;
MAC_TX_SOF <= '1' when (MAC_TX_DATA_VALID_local = '1') and (MAC_TX_EOF_FLAG = '1') else '0';
-- Route "Clear To Send" signal from the MAC to the proper protocol component
ARP_MAC_TX_CTS <= '1' when (TX_MUX_STATE = 1) else '0';
PING_MAC_TX_CTS <= '1' when (TX_MUX_STATE = 2) else '0';
TCP001_MAC_TX_CTS <= '1' when (TX_MUX_STATE = 3) else '0';
WHOIS_MAC_TX_CTS <= '1' when (TX_MUX_STATE = 4) else '0';
UDP001_MAC_TX_CTS <= '1' when (TX_MUX_STATE = 5) else '0';
--TCP002_MAC_TX_CTS <= '1' when (TX_MUX_STATE = 6) else '0';
--//-- ROUTING TABLE ARBITER --------------
-- Since several components could send simultaneous routing (RT) requests, one must
-- determine who can access the routing table next
RT_MUX_001: process(ASYNC_RESET, CLK)
begin
if(ASYNC_RESET = '1') then
RT_MUX_STATE <= 0; -- idle
elsif rising_edge(CLK) then
if(RT_MUX_STATE = 0) then
-- from idle to ...
if(UDP001_RT_REQ_RTS = '1') then
RT_MUX_STATE <= 1; -- gives UDP001 access to the routing table
-- elsif(UDP002_RT_REQ_RTS = '1') then
-- RT_MUX_STATE <= 2; -- gives UDP002 access to the routing table
-- elsif(UDP003_RT_REQ_RTS = '1') then
-- RT_MUX_STATE <= 3; -- gives UDP003 access to the routing table
end if;
-- Routing table transaction complete. go back to idle
elsif (RT_MAC_RDY = '1') or (RT_NAK = '1') then
RT_MUX_STATE <= 0; -- idle
end if;
end if;
end process;
RT_MUX_002: process(RT_MUX_STATE, UDP001_RT_IP_ADDR, UDP001_RT_REQ_RTS)
begin
case(RT_MUX_STATE) is
when (1) =>
RT_IP_ADDR <= UDP001_RT_IP_ADDR;
RT_REQ_RTS <= UDP001_RT_REQ_RTS;
-- when (2) =>
-- RT_IP_ADDR <= UDP002_RT_IP_ADDR;
-- --when (3) =>
-- RT_IP_ADDR <= UDP003_RT_IP_ADDR;
-- etc...
when others =>
RT_IP_ADDR <= (others => '0');
RT_REQ_RTS <= '0';
end case;
end process;
UDP001_RT_REQ_CTS <= RT_CTS when (RT_MUX_STATE = 1) else '0';
--UDP002_RT_REQ_CTS <= RT_CTS when (RT_MUX_STATE = 2) else '0';
--UDP003_RT_REQ_CTS <= RT_CTS when (RT_MUX_STATE = 3) else '0';
-- etc...
UDP001_RT_MAC_RDY <= RT_MAC_RDY when (RT_MUX_STATE = 1) else '0';
--UDP002_RT_MAC_RDY <= RT_MAC_RDY when (RT_MUX_STATE = 2) else '0';
--UDP003_RT_MAC_RDY <= RT_MAC_RDY when (RT_MUX_STATE = 3) else '0';
-- etc...
UDP001_RT_NAK <= RT_NAK when (RT_MUX_STATE = 1) else '0';
--UDP002_RT_NAK <= RT_NAK when (RT_MUX_STATE = 2) else '0';
--UDP003_RT_NAK <= RT_NAK when (RT_MUX_STATE = 3) else '0';
-- etc...
--//-- TEST POINTS
TP <= TP_TCP_SERVER;
--TP(1) <= '1' when (TX_MUX_STATE=1) else '0'; -- arp
--TP(2) <= '1' when (TX_MUX_STATE=2) else '0'; -- ping
--TP(3) <= '1' when (TX_MUX_STATE=4) else '0'; -- whois
--TP(4) <= '1' when (TX_MUX_STATE=5) else '0'; -- udp tx
--TP(5) <= UDP_TX_DATA_VALID;
--TP(6) <= UDP_TX_ACK_local;
--TP(7) <= UDP_TX_NAK_local;
--TP(8) <= WHOIS_START;
--TP(9) <= RT_REQ_RTS;
--TP(10) <= RT_MAC_RDY;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shiftr00 is
port(
clkcshr: in std_logic ;
codopcshr: in std_logic_vector ( 3 downto 0 );
portAcshr: in std_logic_vector ( 7 downto 0 );
inFlagcshr: in std_logic;
outcshr: out std_logic_vector ( 7 downto 0 );
outFlagcshr: out std_logic );
end;
architecture shiftr0 of shiftr00 is
begin
pshr: process(codopcshr, portAcshr)
begin
if(codopcshr = "1010") then
outcshr(7) <= '0';
outcshr(6 downto 0) <= portAcshr(7 downto 1);
outFlagcshr <= '1';
else
outcshr <= (others => 'Z');
outFlagcshr <= 'Z';
end if;
end process pshr;
-- pnand: process(clknd, codopnd, inFlagnd)
-- --variable auxnd: bit:='0';
-- begin
-- if (clknd = '1') then
----clknd'event and
-- if (codopnd = "0100") then
-- if (inFlagnd = '1') then
-- --if (auxnd = '0') then
-- --auxnd:= '1';
-- outnd <= portAnd nand portBnd;
-- outFlagnd <= '1';
-- --end if;
-- else
-- outFlagnd <= '0';
-- end if;
-- else
-- outnd <= (others => 'Z');
-- outFlagnd <= 'Z';
-- --auxnd:='0';
-- end if;
-- end if;
-- end process pnand;
end shiftr0;
|
library verilog;
use verilog.vl_types.all;
entity MeioSomador4Bits_vlg_vec_tst is
end MeioSomador4Bits_vlg_vec_tst;
|
-- $Id: bp_rs232_2l4l_iob.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_2l4l_iob - syn
-- Description: iob's for internal(2line) + external(4line) rs232, with select
--
-- Dependencies: bp_rs232_2line_iob
-- bp_rs232_4line_iob
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 12.1-14,7; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.2.2 fix mistake in tx and rts relay
-- 2011-08-07 404 1.2.1 add RELAY generic and a relay stage towards IOB's
-- 2011-08-06 403 1.2 add pipeline flops; add RESET signal
-- 2011-07-09 391 1.1 moved and renamed to bpgen
-- 2011-07-02 387 1.0.1 use bp_rs232_[24]line_iob now
-- 2010-04-17 278 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity bp_rs232_2l4l_iob is -- iob's for dual 2l+4l rs232, w/ select
generic (
RELAY : boolean := false); -- add a relay stage towards IOB's
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
SEL : in slbit; -- select, '0' for port 0
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
);
end bp_rs232_2l4l_iob;
architecture syn of bp_rs232_2l4l_iob is
signal RXD0 : slbit := '0';
signal RXD1 : slbit := '0';
signal CTS1_N : slbit := '0';
signal R_RXD : slbit := '1';
signal R_CTS_N : slbit := '0';
signal R_TXD0 : slbit := '1';
signal R_TXD1 : slbit := '1';
signal R_RTS1_N : slbit := '0';
signal RR_RXD0 : slbit := '1';
signal RR_TXD0 : slbit := '1';
signal RR_RXD1 : slbit := '1';
signal RR_TXD1 : slbit := '1';
signal RR_CTS1_N : slbit := '0';
signal RR_RTS1_N : slbit := '0';
begin
-- On Digilent Atlys bords the IOBs for P0 and P1 are on diagonally opposide
-- corners of the die, which causes very long (7-8ns) routing delays to a LUT
-- in the middle. The RELAY generic allows to add 'relay flops' between IOB
-- flops and the mux implented in proc_regs_mux.
--
-- The data flow is
-- iob-flop relay-flop if-flop port
-- RXD0 -> RR_RXD0 -> R_RXD -> RXD
-- TXD0 <- RR_TXD0 <- R_TXD0 <- TXD
-- RXD1 -> RR_RXD1 -> R_RXD -> RXD
-- TXD1 <- RR_TXD1 <- R_TXD1 <- TXD
-- CTS1_N -> RR_CTS1_N -> R_CTS_N -> CTS
-- RTS1_N <- RR_RTS1_N <- R_RTS1_N <- RTS
P0 : bp_rs232_2line_iob
port map (
CLK => CLK,
RXD => RXD0,
TXD => RR_TXD0,
I_RXD => I_RXD0,
O_TXD => O_TXD0
);
P1 : bp_rs232_4line_iob
port map (
CLK => CLK,
RXD => RXD1,
TXD => RR_TXD1,
CTS_N => CTS1_N,
RTS_N => RR_RTS1_N,
I_RXD => I_RXD1,
O_TXD => O_TXD1,
I_CTS_N => I_CTS1_N,
O_RTS_N => O_RTS1_N
);
DORELAY : if RELAY generate
proc_regs_pipe: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
RR_RXD0 <= '1';
RR_TXD0 <= '1';
RR_RXD1 <= '1';
RR_TXD1 <= '1';
RR_CTS1_N <= '0';
RR_RTS1_N <= '0';
else
RR_RXD0 <= RXD0;
RR_TXD0 <= R_TXD0;
RR_RXD1 <= RXD1;
RR_TXD1 <= R_TXD1;
RR_CTS1_N <= CTS1_N;
RR_RTS1_N <= R_RTS1_N;
end if;
end if;
end process proc_regs_pipe;
end generate DORELAY;
NORELAY : if not RELAY generate
RR_RXD0 <= RXD0;
RR_TXD0 <= R_TXD0;
RR_RXD1 <= RXD1;
RR_TXD1 <= R_TXD1;
RR_CTS1_N <= CTS1_N;
RR_RTS1_N <= R_RTS1_N;
end generate NORELAY;
proc_regs_mux: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_RXD <= '1';
R_CTS_N <= '0';
R_TXD0 <= '1';
R_TXD1 <= '1';
R_RTS1_N <= '0';
else
if SEL = '0' then -- use 2-line rs232, no flow cntl
R_RXD <= RR_RXD0; -- get port 0 inputs
R_CTS_N <= '0';
R_TXD0 <= TXD; -- set port 0 output
R_TXD1 <= '1'; -- port 1 outputs to idle state
R_RTS1_N <= '0';
else -- otherwise use 4-line rs232
R_RXD <= RR_RXD1; -- get port 1 inputs
R_CTS_N <= RR_CTS1_N;
R_TXD0 <= '1'; -- port 0 output to idle state
R_TXD1 <= TXD; -- set port 1 outputs
R_RTS1_N <= RTS_N;
end if;
end if;
end if;
end process proc_regs_mux;
RXD <= R_RXD;
CTS_N <= R_CTS_N;
end syn;
|
--------------------------------------------------------------------------
-- package com tipos basicos
--------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
package PhoenixPackage is
-----------------------------------------------------------------------
-- OCP PARAMETERS
-----------------------------------------------------------------------
------------------ command Enconding - p. 13 ---------------------------
constant IDLE: Std_Logic_Vector(2 downto 0) :="000";
constant WR: Std_Logic_Vector(2 downto 0) :="001";
constant RD: Std_Logic_Vector(2 downto 0) :="010";
constant RDEX: Std_Logic_Vector(2 downto 0) :="011";
constant BCST: Std_Logic_Vector(2 downto 0) :="111";
-----------------------Response Enconding------------------------------
constant DVA: Std_Logic_Vector(1 downto 0) :="01";
constant ERR: Std_Logic_Vector(1 downto 0) :="11";
constant NULO: Std_Logic_Vector(1 downto 0) :="00";
constant ALVO: Std_Logic_Vector(7 downto 0) :="00000000";
---------------------------------------------------------
-- CONSTANTS INDEPENDENTES
---------------------------------------------------------
constant NPORT: integer := 5;
constant EAST : integer := 0;
constant WEST : integer := 1;
constant NORTH : integer := 2;
constant SOUTH : integer := 3;
constant LOCAL : integer := 4;
---------------------------------------------------------
-- CONSTANT DEPENDENTE DA LARGURA DE BANDA DA REDE
---------------------------------------------------------
constant TAM_FLIT : integer range 1 to 64 := 16;
constant METADEFLIT : integer range 1 to 32 := (TAM_FLIT/2);
constant QUARTOFLIT : integer range 1 to 16 := (TAM_FLIT/4);
---------------------------------------------------------
-- CONSTANTS DEPENDENTES DA PROFUNDIDADE DA FILA
---------------------------------------------------------
constant TAM_BUFFER: integer := 16;
constant TAM_POINTER : integer range 1 to 32 := 5;
---------------------------------------------------------
-- CONSTANTS DEPENDENTES DO NUMERO DE ROTEADORES
---------------------------------------------------------
constant NUM_X : integer := 5;
constant NUM_Y : integer := 5;
constant NROT: integer := NUM_X*NUM_Y;
constant MIN_X : integer := 0;
constant MIN_Y : integer := 0;
constant MAX_X : integer := NUM_X-1;
constant MAX_Y : integer := NUM_Y-1;
---------------------------------------------------------
-- CONSTANT TB
---------------------------------------------------------
constant TAM_LINHA : integer := 500;
---------------------------------------------------------
-- VARIAVEIS DO NOVO HARDWARE
---------------------------------------------------------
subtype reg21 is std_logic_vector(20 downto 0);
type buffControl is array(0 to 4) of std_logic_vector((TAM_FLIT-1) downto 0);
type RouterControl is (invalidRegion, validRegion, faultPort, portError);
type ArrayRouterControl is array(NPORT downto 0) of RouterControl;
constant c_WR_ROUT_TAB : integer := 1;
constant c_WR_FAULT_TAB : integer := 2;
constant c_RD_FAULT_TAB_STEP1 : integer := 3;
constant c_RD_FAULT_TAB_STEP2 : integer := 4;
constant c_TEST_LINKS : integer := 5;
---------------------------------------------------------
-- SUBTIPOS, TIPOS E FUNCOES
---------------------------------------------------------
subtype reg3 is std_logic_vector(2 downto 0);
subtype reg8 is std_logic_vector(7 downto 0);
subtype reg32 is std_logic_vector(31 downto 0);
subtype regNrot is std_logic_vector((NROT-1) downto 0);
subtype regNport is std_logic_vector((NPORT-1) downto 0);
subtype regflit is std_logic_vector((TAM_FLIT-1) downto 0);
subtype regmetadeflit is std_logic_vector(((TAM_FLIT/2)-1) downto 0);
subtype regquartoflit is std_logic_vector((QUARTOFLIT-1) downto 0);
subtype pointer is std_logic_vector((TAM_POINTER-1) downto 0);
type buff is array(0 to TAM_BUFFER-1) of regflit;
type arrayNport_reg3 is array((NPORT-1) downto 0) of reg3;
type arrayNport_reg8 is array((NPORT-1) downto 0) of reg8;
type arrayNport_regflit is array((NPORT-1) downto 0) of regflit;
type arrayNrot_reg3 is array((NROT-1) downto 0) of reg3;
type arrayNrot_regflit is array((NROT-1) downto 0) of regflit;
type arrayNrot_regmetadeflit is array((NROT-1) downto 0) of regmetadeflit;
type arrayNrot_regNport is array((NROT-1) downto 0) of regNport;
function CONV_VECTOR( int: integer ) return std_logic_vector;
type arrayRegNport is array ((NPORT-1) downto 0) of regNport;
type routingTable is array(0 to MAX_X, 0 to MAX_Y) of std_logic_vector(NPORT-1 downto 0);
---------------------------------------------------------
-- FUNCOES TB
---------------------------------------------------------
function CONV_VECTOR( letra : string(1 to TAM_LINHA); pos: integer ) return std_logic_vector;
function CONV_HEX( int : integer ) return string;
function CONV_STRING_4BITS( dado : std_logic_vector(3 downto 0)) return string;
function CONV_STRING_8BITS( dado : std_logic_vector(7 downto 0)) return string;
function CONV_STRING_16BITS( dado : std_logic_vector(15 downto 0)) return string;
function CONV_STRING_32BITS( dado : std_logic_vector(31 downto 0)) return string;
function NUMBER_TO_ADDRESS(number: integer) return regflit;
function ADDRESS_TO_NUMBER (address: std_logic_vector) return integer;
function ADDRESS_TO_NUMBER_NOIA (address: std_logic_vector) return integer;
function to_hstring(value: std_logic_vector) return string;
function PORT_NAME(value: integer) return string;
function GET_ADDR(index : integer) return regflit;
end PhoenixPackage;
package body PhoenixPackage is
--
-- dado o index do roteador retorna o endereço correspondente
--
function GET_ADDR( index: integer) return regflit is
variable addrX, addrY: regmetadeflit;
variable addr: regflit;
begin
addrX := CONV_STD_LOGIC_VECTOR(index/NUM_X,METADEFLIT);
addrY := CONV_STD_LOGIC_VECTOR(index mod NUM_Y, METADEFLIT);
addr := addrX & addrY;
return addr;
end GET_ADDR;
--
-- converte um inteiro em um std_logic_vector(2 downto 0)
--
function CONV_VECTOR( int: integer ) return std_logic_vector is
variable bin: reg3;
begin
case(int) is
when 0 => bin := "000";
when 1 => bin := "001";
when 2 => bin := "010";
when 3 => bin := "011";
when 4 => bin := "100";
when 5 => bin := "101";
when 6 => bin := "110";
when 7 => bin := "111";
when others => bin := "000";
end case;
return bin;
end CONV_VECTOR;
---------------------------------------------------------
-- FUNCOES TB
---------------------------------------------------------
--
-- converte um caracter de uma dada linha em um std_logic_vector
--
function CONV_VECTOR( letra:string(1 to TAM_LINHA); pos: integer ) return std_logic_vector is
variable bin: std_logic_vector(3 downto 0);
begin
case (letra(pos)) is
when '0' => bin := "0000";
when '1' => bin := "0001";
when '2' => bin := "0010";
when '3' => bin := "0011";
when '4' => bin := "0100";
when '5' => bin := "0101";
when '6' => bin := "0110";
when '7' => bin := "0111";
when '8' => bin := "1000";
when '9' => bin := "1001";
when 'A' => bin := "1010";
when 'B' => bin := "1011";
when 'C' => bin := "1100";
when 'D' => bin := "1101";
when 'E' => bin := "1110";
when 'F' => bin := "1111";
when others => bin := "0000";
end case;
return bin;
end CONV_VECTOR;
-- converte um inteiro em um string
function CONV_HEX( int: integer ) return string is
variable str: string(1 to 1);
begin
case(int) is
when 0 => str := "0";
when 1 => str := "1";
when 2 => str := "2";
when 3 => str := "3";
when 4 => str := "4";
when 5 => str := "5";
when 6 => str := "6";
when 7 => str := "7";
when 8 => str := "8";
when 9 => str := "9";
when 10 => str := "A";
when 11 => str := "B";
when 12 => str := "C";
when 13 => str := "D";
when 14 => str := "E";
when 15 => str := "F";
when others => str := "U";
end case;
return str;
end CONV_HEX;
function CONV_STRING_4BITS(dado : std_logic_vector(3 downto 0)) return string is
variable str: string(1 to 1);
begin
str := CONV_HEX(CONV_INTEGER(dado));
return str;
end CONV_STRING_4BITS;
function CONV_STRING_8BITS(dado : std_logic_vector(7 downto 0)) return string is
variable str1,str2: string(1 to 1);
variable str: string(1 to 2);
begin
str1 := CONV_STRING_4BITS(dado(7 downto 4));
str2 := CONV_STRING_4BITS(dado(3 downto 0));
str := str1 & str2;
return str;
end CONV_STRING_8BITS;
function CONV_STRING_16BITS(dado : std_logic_vector(15 downto 0)) return string is
variable str1,str2: string(1 to 2);
variable str: string(1 to 4);
begin
str1 := CONV_STRING_8BITS(dado(15 downto 8));
str2 := CONV_STRING_8BITS(dado(7 downto 0));
str := str1 & str2;
return str;
end CONV_STRING_16BITS;
function CONV_STRING_32BITS(dado : std_logic_vector(31 downto 0)) return string is
variable str1,str2: string(1 to 4);
variable str: string(1 to 8);
begin
str1 := CONV_STRING_16BITS(dado(31 downto 16));
str2 := CONV_STRING_16BITS(dado(15 downto 0));
str := str1 & str2;
return str;
end CONV_STRING_32BITS;
function NUMBER_TO_ADDRESS( number: integer ) return regflit is
variable address: regflit := (others => '0');
begin
address(TAM_FLIT-1 downto METADEFLIT) := (others=>'0');
address(METADEFLIT-1 downto QUARTOFLIT) := CONV_STD_LOGIC_VECTOR(number/NUM_X, QUARTOFLIT);
address(QUARTOFLIT-1 downto 0) := CONV_STD_LOGIC_VECTOR(number mod NUM_Y, QUARTOFLIT);
return address;
end NUMBER_TO_ADDRESS;
function ADDRESS_TO_NUMBER (address: std_logic_vector) return integer is
variable number: integer := 0;
alias addrX is address(METADEFLIT-1 downto QUARTOFLIT);
alias addrY is address(QUARTOFLIT-1 downto 0);
variable X : integer := CONV_INTEGER(addrX);
variable Y : integer := CONV_INTEGER(addrY);
begin
number := Y*(MAX_X+1) + X;
return number;
end ADDRESS_TO_NUMBER;
function ADDRESS_TO_NUMBER_NOIA (address: std_logic_vector) return integer is
variable number: integer := 0;
alias addrX is address(METADEFLIT-1 downto QUARTOFLIT);
alias addrY is address(QUARTOFLIT-1 downto 0);
variable X : integer := CONV_INTEGER(addrX);
variable Y : integer := CONV_INTEGER(addrY);
begin
number := X*(MAX_Y+1) + Y;
return number;
end ADDRESS_TO_NUMBER_NOIA;
-- converte hexa para string
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4; -- numero minimo de blocos de 4 bits (truncado)
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1); -- valores finais, no caso do value nao ser multiplo de 4
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1); -- o valor em si.
variable result : STRING(1 to ne); -- blocos de 4 bits
variable quad : STD_LOGIC_VECTOR(0 to 3); -- um bloco.
begin
if value'length < 1 then
return result;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
function PORT_NAME(value: integer) return string is
variable str: string (1 to 8);
begin
case value is
when EAST => str(1 to 4) := "EAST";
when WEST => str(1 to 4) := "WEST";
when NORTH => str(1 to 5) := "NORTH";
when SOUTH => str(1 to 5) := "SOUTH";
when LOCAL => str(1 to 5) := "LOCAL";
when others => str(1 to 7) := "INVALID";
end case;
return str;
end function PORT_NAME;
end PhoenixPackage; |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_STICKYFLAG24 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
SET : in vl_logic_vector(23 downto 0);
CLR : in vl_logic_vector(23 downto 0);
FLAG : out vl_logic_vector(23 downto 0)
);
end F2DSS_ACE_MISC_STICKYFLAG24;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_STICKYFLAG24 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
SET : in vl_logic_vector(23 downto 0);
CLR : in vl_logic_vector(23 downto 0);
FLAG : out vl_logic_vector(23 downto 0)
);
end F2DSS_ACE_MISC_STICKYFLAG24;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_STICKYFLAG24 is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
SET : in vl_logic_vector(23 downto 0);
CLR : in vl_logic_vector(23 downto 0);
FLAG : out vl_logic_vector(23 downto 0)
);
end F2DSS_ACE_MISC_STICKYFLAG24;
|
library ieee;
use ieee.std_logic_1164.all;
entity foo_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end entity;
architecture rtl of foo_m is
begin
process (clock) begin
if (rising_edge(clock)) then
x <= a and b;
y <= a or b;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity foo_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end entity;
architecture rtl of foo_m is
begin
process (clock) begin
if (rising_edge(clock)) then
x <= a and b;
y <= a or b;
end if;
end process;
end architecture;
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/27/2016 04:46:45 PM
-- Design Name:
-- Module Name: top_level - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_level is
Port ( ---------------------------------------------------------------------------
-- Xilinx Hard IP Interface
-- . Clock and Resets
pcie_clk_p : in std_logic;
pcie_clk_n : in std_logic;
clk200_n : in STD_LOGIC;
clk200_p : in STD_LOGIC;
rst_n_i : in STD_LOGIC;
sys_rst_n_i : in STD_LOGIC;
-- . Serial I/F
pci_exp_txn : out std_logic_vector(4-1 downto 0);--output wire [4 -1:0] pci_exp_txn ,
pci_exp_txp : out std_logic_vector(4-1 downto 0);--output wire [4 -1:0] pci_exp_txp ,
pci_exp_rxn : in std_logic_vector(4-1 downto 0);--input wire [4 -1:0] pci_exp_rxn ,
pci_exp_rxp : in std_logic_vector(4-1 downto 0);
-- . IO
usr_sw_i : in STD_LOGIC_VECTOR (2 downto 0);
usr_led_o : out STD_LOGIC_VECTOR (2 downto 0);
--front_led_o : out STD_LOGIC_VECTOR (3 downto 0);
-- . DDR3
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
--init_calib_complete : out std_logic;
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0)
);
end top_level;
architecture Behavioral of top_level is
constant AXI_BUS_WIDTH : integer := 64;
component simple_counter is
Port (
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
count_o : out STD_LOGIC_VECTOR (28 downto 0)
);
end component;
COMPONENT pcie_7x_0
PORT (
pci_exp_txp : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pci_exp_txn : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pci_exp_rxp : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
pci_exp_rxn : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
user_clk_out : OUT STD_LOGIC;
user_reset_out : OUT STD_LOGIC;
user_lnk_up : OUT STD_LOGIC;
user_app_rdy : OUT STD_LOGIC;
tx_buf_av : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
tx_cfg_req : OUT STD_LOGIC;
tx_err_drop : OUT STD_LOGIC;
s_axis_tx_tready : OUT STD_LOGIC;
s_axis_tx_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_tx_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tx_tlast : IN STD_LOGIC;
s_axis_tx_tvalid : IN STD_LOGIC;
s_axis_tx_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_rx_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_rx_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_rx_tlast : OUT STD_LOGIC;
m_axis_rx_tvalid : OUT STD_LOGIC;
m_axis_rx_tready : IN STD_LOGIC;
m_axis_rx_tuser : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
cfg_status : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_command : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dstatus : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dcommand : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_lstatus : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_lcommand : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dcommand2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_pcie_link_state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_pmcsr_pme_en : OUT STD_LOGIC;
cfg_pmcsr_powerstate : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_pmcsr_pme_status : OUT STD_LOGIC;
cfg_received_func_lvl_rst : OUT STD_LOGIC;
cfg_interrupt : IN STD_LOGIC;
cfg_interrupt_rdy : OUT STD_LOGIC;
cfg_interrupt_assert : IN STD_LOGIC;
cfg_interrupt_di : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_do : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_mmenable : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_interrupt_msienable : OUT STD_LOGIC;
cfg_interrupt_msixenable : OUT STD_LOGIC;
cfg_interrupt_msixfm : OUT STD_LOGIC;
cfg_interrupt_stat : IN STD_LOGIC;
cfg_pciecap_interrupt_msgnum : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_to_turnoff : OUT STD_LOGIC;
cfg_bus_number : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_device_number : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_function_number : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_msg_received : OUT STD_LOGIC;
cfg_msg_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_bridge_serr_en : OUT STD_LOGIC;
cfg_slot_control_electromech_il_ctl_pulse : OUT STD_LOGIC;
cfg_root_control_syserr_corr_err_en : OUT STD_LOGIC;
cfg_root_control_syserr_non_fatal_err_en : OUT STD_LOGIC;
cfg_root_control_syserr_fatal_err_en : OUT STD_LOGIC;
cfg_root_control_pme_int_en : OUT STD_LOGIC;
cfg_aer_rooterr_corr_err_reporting_en : OUT STD_LOGIC;
cfg_aer_rooterr_non_fatal_err_reporting_en : OUT STD_LOGIC;
cfg_aer_rooterr_fatal_err_reporting_en : OUT STD_LOGIC;
cfg_aer_rooterr_corr_err_received : OUT STD_LOGIC;
cfg_aer_rooterr_non_fatal_err_received : OUT STD_LOGIC;
cfg_aer_rooterr_fatal_err_received : OUT STD_LOGIC;
cfg_msg_received_err_cor : OUT STD_LOGIC;
cfg_msg_received_err_non_fatal : OUT STD_LOGIC;
cfg_msg_received_err_fatal : OUT STD_LOGIC;
cfg_msg_received_pm_as_nak : OUT STD_LOGIC;
cfg_msg_received_pm_pme : OUT STD_LOGIC;
cfg_msg_received_pme_to_ack : OUT STD_LOGIC;
cfg_msg_received_assert_int_a : OUT STD_LOGIC;
cfg_msg_received_assert_int_b : OUT STD_LOGIC;
cfg_msg_received_assert_int_c : OUT STD_LOGIC;
cfg_msg_received_assert_int_d : OUT STD_LOGIC;
cfg_msg_received_deassert_int_a : OUT STD_LOGIC;
cfg_msg_received_deassert_int_b : OUT STD_LOGIC;
cfg_msg_received_deassert_int_c : OUT STD_LOGIC;
cfg_msg_received_deassert_int_d : OUT STD_LOGIC;
cfg_msg_received_setslotpowerlimit : OUT STD_LOGIC;
cfg_vc_tcvc_map : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
sys_clk : IN STD_LOGIC;
sys_rst_n : IN STD_LOGIC
);
END COMPONENT;
component app is
Generic(
AXI_BUS_WIDTH : integer := 64;
DMA_MEMORY_SELECTED : string := "DDR3"
);
Port ( clk_i : in STD_LOGIC;
sys_clk_n_i : IN STD_LOGIC;
sys_clk_p_i : IN STD_LOGIC;
rst_i : in STD_LOGIC;
user_lnk_up_i : in STD_LOGIC;
user_app_rdy_i : in STD_LOGIC;
-- AXI-Stream bus
m_axis_tx_tready_i : in STD_LOGIC;
m_axis_tx_tdata_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
m_axis_tx_tkeep_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
m_axis_tx_tlast_o : out STD_LOGIC;
m_axis_tx_tvalid_o : out STD_LOGIC;
m_axis_tx_tuser_o : out STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_rx_tdata_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
s_axis_rx_tkeep_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
s_axis_rx_tlast_i : in STD_LOGIC;
s_axis_rx_tvalid_i : in STD_LOGIC;
s_axis_rx_tready_o : out STD_LOGIC;
s_axis_rx_tuser_i : in STD_LOGIC_VECTOR(21 DOWNTO 0);
-- PCIe interrupt config
cfg_interrupt_o : out STD_LOGIC;
cfg_interrupt_rdy_i : in STD_LOGIC;
cfg_interrupt_assert_o : out STD_LOGIC;
cfg_interrupt_di_o : out STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_do_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_mmenable_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_interrupt_msienable_i : in STD_LOGIC;
cfg_interrupt_msixenable_i : in STD_LOGIC;
cfg_interrupt_msixfm_i : in STD_LOGIC;
cfg_interrupt_stat_o : out STD_LOGIC;
cfg_pciecap_interrupt_msgnum_o : out STD_LOGIC_VECTOR(4 DOWNTO 0);
-- PCIe ID
cfg_bus_number_i : in STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_device_number_i : in STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_function_number_i : in STD_LOGIC_VECTOR(2 DOWNTO 0);
-- PCIe debug
tx_err_drop_i : in STD_LOGIC;
cfg_dstatus_i : in STD_LOGIC_VECTOR(15 DOWNTO 0);
--DDR3
ddr3_dq_io : inout std_logic_vector(63 downto 0);
ddr3_dqs_p_io : inout std_logic_vector(7 downto 0);
ddr3_dqs_n_io : inout std_logic_vector(7 downto 0);
--init_calib_complete_o : out std_logic;
ddr3_addr_o : out std_logic_vector(14 downto 0);
ddr3_ba_o : out std_logic_vector(2 downto 0);
ddr3_ras_n_o : out std_logic;
ddr3_cas_n_o : out std_logic;
ddr3_we_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_ck_p_o : out std_logic_vector(0 downto 0);
ddr3_ck_n_o : out std_logic_vector(0 downto 0);
ddr3_cke_o : out std_logic_vector(0 downto 0);
ddr3_cs_n_o : out std_logic_vector(0 downto 0);
ddr3_dm_o : out std_logic_vector(7 downto 0);
ddr3_odt_o : out std_logic_vector(0 downto 0);
--I/O
usr_sw_i : in STD_LOGIC_VECTOR (2 downto 0);
usr_led_o : out STD_LOGIC_VECTOR (3 downto 0);
front_led_o : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
--Clocks
signal sys_clk : STD_LOGIC;
--signal clk200 : STD_LOGIC;
signal aclk : STD_LOGIC;
signal arstn_s : STD_LOGIC;
signal rst_s : STD_LOGIC;
--Wishbone bus
signal usr_led_s : std_logic_vector(3 downto 0);
--signal count_s : STD_LOGIC_VECTOR (28 downto 0);
-- AXI-stream bus to PCIE
signal s_axis_tx_tready_s : STD_LOGIC;
signal s_axis_tx_tdata_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
signal s_axis_tx_tkeep_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
signal s_axis_tx_tlast_s : STD_LOGIC;
signal s_axis_tx_tvalid_s : STD_LOGIC;
signal s_axis_tx_tuser_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal m_axis_rx_tdata_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0);
signal m_axis_rx_tkeep_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0);
signal m_axis_rx_tlast_s : STD_LOGIC;
signal m_axis_rx_tvalid_s : STD_LOGIC;
signal m_axis_rx_tready_s : STD_LOGIC;
signal m_axis_rx_tuser_s : STD_LOGIC_VECTOR(21 DOWNTO 0);
-- PCIE signals
signal user_lnk_up_s : STD_LOGIC;
signal user_app_rdy_s : STD_LOGIC;
signal tx_err_drop_s : STD_LOGIC;
signal cfg_interrupt_s : STD_LOGIC;
signal cfg_interrupt_rdy_s : STD_LOGIC;
signal cfg_interrupt_assert_s : STD_LOGIC;
signal cfg_interrupt_di_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal cfg_interrupt_do_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal cfg_interrupt_mmenable_s : STD_LOGIC_VECTOR(2 DOWNTO 0);
signal cfg_interrupt_msienable_s : STD_LOGIC;
signal cfg_interrupt_msixenable_s : STD_LOGIC;
signal cfg_interrupt_msixfm_s : STD_LOGIC;
signal cfg_interrupt_stat_s : STD_LOGIC;
signal cfg_pciecap_interrupt_msgnum_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
-- PCIE ID
signal cfg_bus_number_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal cfg_device_number_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal cfg_function_number_s : STD_LOGIC_VECTOR(2 DOWNTO 0);
--PCIE debug
signal cfg_dstatus_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
begin
-- LVDS input to internal single
-- CLK_IBUFDS : IBUFDS
-- generic map(
-- IOSTANDARD => "DEFAULT"
-- )
-- port map(
-- I => clk200_p,
-- IB => clk200_n,
-- O => clk200
-- );
-- design_1_0: component design_1
-- port map (
-- CLK_IN_D_clk_n(0) => pcie_clk_n,
-- CLK_IN_D_clk_p(0) => pcie_clk_p,
-- IBUF_OUT(0) => sys_clk
-- );
refclk_ibuf : IBUFDS_GTE2
port map(
O => sys_clk,
ODIV2 => open,
I => pcie_clk_p,
IB => pcie_clk_n,
CEB => '0');
rst_s <= not rst_n_i;
arstn_s <= sys_rst_n_i or rst_n_i;
pcie_0 : pcie_7x_0
PORT MAP (
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
user_clk_out => aclk,
user_reset_out => open, -- TODO
user_lnk_up => user_lnk_up_s,
user_app_rdy => user_app_rdy_s,
tx_err_drop => tx_err_drop_s,
s_axis_tx_tready => s_axis_tx_tready_s,
s_axis_tx_tdata => s_axis_tx_tdata_s,
s_axis_tx_tkeep => s_axis_tx_tkeep_s,
s_axis_tx_tlast => s_axis_tx_tlast_s,
s_axis_tx_tvalid => s_axis_tx_tvalid_s,
s_axis_tx_tuser => s_axis_tx_tuser_s,
m_axis_rx_tdata => m_axis_rx_tdata_s,
m_axis_rx_tkeep => m_axis_rx_tkeep_s,
m_axis_rx_tlast => m_axis_rx_tlast_s,
m_axis_rx_tvalid => m_axis_rx_tvalid_s,
m_axis_rx_tready => m_axis_rx_tready_s,
m_axis_rx_tuser => m_axis_rx_tuser_s,
cfg_interrupt => cfg_interrupt_s,
cfg_interrupt_rdy => cfg_interrupt_rdy_s,
cfg_interrupt_assert => cfg_interrupt_assert_s,
cfg_interrupt_di => cfg_interrupt_di_s,
cfg_interrupt_do => cfg_interrupt_do_s,
cfg_interrupt_mmenable => cfg_interrupt_mmenable_s,
cfg_interrupt_msienable => cfg_interrupt_msienable_s,
cfg_interrupt_msixenable => cfg_interrupt_msixenable_s,
cfg_interrupt_msixfm => cfg_interrupt_msixfm_s,
cfg_interrupt_stat => cfg_interrupt_stat_s,
cfg_pciecap_interrupt_msgnum => cfg_pciecap_interrupt_msgnum_s,
cfg_dstatus => cfg_dstatus_s,
cfg_bus_number => cfg_bus_number_s,
cfg_device_number => cfg_device_number_s,
cfg_function_number => cfg_function_number_s,
sys_clk => sys_clk,
sys_rst_n => sys_rst_n_i
);
app_0:app
generic map(
AXI_BUS_WIDTH => 64,
DMA_MEMORY_SELECTED => "BRAM"
)
port map(
clk_i => aclk,
sys_clk_n_i => clk200_n,
sys_clk_p_i => clk200_p,
rst_i => rst_s,
user_lnk_up_i => user_lnk_up_s,
user_app_rdy_i => user_app_rdy_s,
-- AXI-Stream bus
m_axis_tx_tready_i => s_axis_tx_tready_s,
m_axis_tx_tdata_o => s_axis_tx_tdata_s,
m_axis_tx_tkeep_o => s_axis_tx_tkeep_s,
m_axis_tx_tlast_o => s_axis_tx_tlast_s,
m_axis_tx_tvalid_o => s_axis_tx_tvalid_s,
m_axis_tx_tuser_o => s_axis_tx_tuser_s,
s_axis_rx_tdata_i => m_axis_rx_tdata_s,
s_axis_rx_tkeep_i => m_axis_rx_tkeep_s,
s_axis_rx_tlast_i => m_axis_rx_tlast_s,
s_axis_rx_tvalid_i => m_axis_rx_tvalid_s,
s_axis_rx_tready_o => m_axis_rx_tready_s,
s_axis_rx_tuser_i => m_axis_rx_tuser_s,
-- PCIe interrupt config
cfg_interrupt_o => cfg_interrupt_s,
cfg_interrupt_rdy_i => cfg_interrupt_rdy_s,
cfg_interrupt_assert_o => cfg_interrupt_assert_s,
cfg_interrupt_di_o => cfg_interrupt_di_s,
cfg_interrupt_do_i => cfg_interrupt_do_s,
cfg_interrupt_mmenable_i => cfg_interrupt_mmenable_s,
cfg_interrupt_msienable_i => cfg_interrupt_msienable_s,
cfg_interrupt_msixenable_i => cfg_interrupt_msixenable_s,
cfg_interrupt_msixfm_i => cfg_interrupt_msixfm_s,
cfg_interrupt_stat_o => cfg_interrupt_stat_s,
cfg_pciecap_interrupt_msgnum_o => cfg_pciecap_interrupt_msgnum_s,
-- PCIe ID
cfg_bus_number_i => cfg_bus_number_s,
cfg_device_number_i => cfg_device_number_s,
cfg_function_number_i => cfg_function_number_s,
-- PCIe debug
tx_err_drop_i => tx_err_drop_s,
cfg_dstatus_i => cfg_dstatus_s,
--DDR3
ddr3_dq_io => ddr3_dq,
ddr3_dqs_p_io => ddr3_dqs_p,
ddr3_dqs_n_io => ddr3_dqs_n,
--init_calib_complete_o => init_calib_complete,
ddr3_addr_o => ddr3_addr,
ddr3_ba_o => ddr3_ba,
ddr3_ras_n_o => ddr3_ras_n,
ddr3_cas_n_o => ddr3_cas_n,
ddr3_we_n_o => ddr3_we_n,
ddr3_reset_n_o => ddr3_reset_n,
ddr3_ck_p_o => ddr3_ck_p,
ddr3_ck_n_o => ddr3_ck_n,
ddr3_cke_o => ddr3_cke,
ddr3_cs_n_o => ddr3_cs_n,
ddr3_dm_o => ddr3_dm,
ddr3_odt_o => ddr3_odt,
--I/O
usr_sw_i => usr_sw_i,
usr_led_o => usr_led_s,
front_led_o => open--front_led_o
);
usr_led_o <= usr_led_s(2 downto 0);
--m_axis_rx_tready_s <= '1';
end Behavioral;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity dvb_dma is
port (
rst : in std_logic;
clk : in std_logic;
-- control port
address : in std_logic_vector(3 downto 0);
byteenable : in std_logic_vector(3 downto 0);
writedata : in std_logic_vector(31 downto 0);
write : in std_logic;
readdata : out std_logic_vector(31 downto 0);
interrupt : out std_logic;
-- DVB port
dvb_sop : in std_logic;
dvb_data : in std_logic_vector(7 downto 0);
dvb_dval : in std_logic;
-- memory port
mem_size : out std_logic_vector(6 downto 0);
mem_addr : out std_logic_vector(63 downto 3);
mem_byteen : out std_logic_vector(7 downto 0);
mem_wrdata : out std_logic_vector(63 downto 0);
mem_write : out std_logic;
mem_waitreq : in std_logic
);
end;
architecture rtl of dvb_dma is
constant REG_DMA_CTRLSTAT : natural := 0;
constant REG_DMA_CTRLSTAT_SET : natural := 0;
constant REG_DMA_CTRLSTAT_CLR : natural := 1;
constant REG_DMA_START_ADDR_L : natural := 2; -- first address of the ring buffer
constant REG_DMA_START_ADDR_H : natural := 3;
constant REG_DMA_SIZE : natural := 4; -- packet size, number of packets per interrupt block and number of blocks per buffer
constant REG_DMA_TIMEOUT : natural := 5; -- force interrupt when timer expires
constant REG_DMA_CURR_ADDR_L : natural := 6;
constant REG_DMA_CURR_ADDR_H : natural := 7;
constant REG_STAT_PKT_RECEIVED : natural := 8;
constant REG_STAT_PKT_ACCEPTED : natural := 9;
constant REG_STAT_PKT_OVERRUNS : natural := 10;
constant REG_STAT_PKT_UNDERRUNS : natural := 11;
constant REG_STAT_FIFO_OVERRUNS : natural := 12;
constant BIT_DMA_RUN : natural := 0;
constant BIT_DMA_IRQ : natural := 9;
signal dma_ctrlstat_reg : std_logic_vector(31 downto 0);
signal dma_start_addr : std_logic_vector(63 downto 0);
signal dma_timeout : std_logic_vector(31 downto 0);
alias dma_start_addr_l : std_logic_vector(31 downto 0) is dma_start_addr(31 downto 0);
alias dma_start_addr_h : std_logic_vector(31 downto 0) is dma_start_addr(63 downto 32);
signal dma_packet_size : std_logic_vector(7 downto 0);
signal dma_block_size : std_logic_vector(23 downto 8);
signal dma_length : std_logic_vector(31 downto 24);
-- control stat register fields
signal dma_run : std_logic;
signal dma_irq : std_logic;
signal dma_curr_addr : unsigned(63 downto 0);
alias dma_curr_addr_l : unsigned(31 downto 0) is dma_curr_addr(31 downto 0);
alias dma_curr_addr_h : unsigned(31 downto 0) is dma_curr_addr(63 downto 32);
signal dma_irq_reset : std_logic;
signal pkt_size : unsigned(dma_packet_size'length downto 0);
signal block_size : unsigned(dma_block_size'length downto 0);
signal blocks_num : unsigned(dma_length'length downto 0);
signal dvb_latch_data : std_logic_vector(dvb_data'range);
signal dvb_latch_dval : std_logic;
signal dvb_overrun_n : std_logic;
signal fifo_overflow : std_logic;
signal dvb_cnt : unsigned(pkt_size'range);
signal write_page : unsigned(2 downto 0);
signal write_addr_l : unsigned(dma_packet_size'range);
alias write_addr_h is write_page(write_page'left - 1 downto write_page'right);
signal stat_pkts_received : unsigned(31 downto 0);
signal stat_pkts_accepted : unsigned(31 downto 0);
signal stat_pkt_overruns : unsigned(31 downto 0);
signal stat_pkt_underruns : unsigned(31 downto 0);
signal stat_fifo_overruns : unsigned(31 downto 0);
signal dma_cnt : unsigned(pkt_size'range);
signal read_page : unsigned(2 downto 0);
alias read_addr_l is dma_cnt(dma_cnt'left - 1 downto dma_cnt'right + 3);
alias read_addr_h is read_page(read_page'left - 1 downto read_page'right);
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_rdclken : std_logic;
signal fifo_rdaddr : std_logic_vector(6 downto 0);
signal fifo_rddata : std_logic_vector(63 downto 0);
signal fifo_wraddr : std_logic_vector(9 downto 0);
signal fifo_wrdata : std_logic_vector(7 downto 0);
signal fifo_wren : std_logic;
signal fifo_latch_valid : std_logic;
signal fifo_rddata_valid : std_logic;
signal dma_reg : std_logic_vector(63 downto 0);
signal dma_reg_be : std_logic_vector(7 downto 0);
signal dma_reg_pad : std_logic_vector(63 downto 8);
signal dma_reg_pad_be : std_logic_vector(7 downto 1);
signal dma_reg_pad_wren : std_logic;
signal mem_write_i : std_logic;
signal burst_addr : unsigned(63 downto 0);
signal burst : std_logic;
signal burst_end : std_logic;
signal dma_pkt_cnt : unsigned(dma_block_size'length downto 0);
signal dma_blk_cnt : unsigned(dma_length'length downto 0);
signal dma_irq_pend : std_logic;
signal dma_reload_n : std_logic;
signal dma_timer : signed(dma_timeout'length downto 0);
signal dma_timer_d : std_logic;
begin
process (rst, clk)
begin
if rising_edge(clk) then
if write then
write_sr_flag(dma_run, REG_DMA_CTRLSTAT_SET, BIT_DMA_RUN, address, writedata, byteenable);
if not dma_run then
write_reg(dma_start_addr_l, REG_DMA_START_ADDR_L, address, writedata, byteenable);
write_reg(dma_start_addr_h, REG_DMA_START_ADDR_H, address, writedata, byteenable);
write_reg(dma_packet_size, REG_DMA_SIZE, address, writedata, byteenable);
write_reg(dma_block_size, REG_DMA_SIZE, address, writedata, byteenable);
write_reg(dma_length, REG_DMA_SIZE, address, writedata, byteenable);
write_reg(dma_timeout, REG_DMA_TIMEOUT, address, writedata, byteenable);
end if;
end if;
if unsigned(address) = REG_DMA_CTRLSTAT_CLR then
dma_irq_reset <= write and byteenable(BIT_DMA_IRQ / 8) and writedata(BIT_DMA_IRQ);
else
dma_irq_reset <= '0';
end if;
end if;
if rst then
dma_run <= '0';
dma_irq_reset <= '0';
--
dma_start_addr_l <= (others => '0');
dma_start_addr_h <= (others => '0');
dma_packet_size <= (others => '0');
dma_block_size <= (others => '0');
dma_length <= (others => '0');
dma_timeout <= (others => '0');
end if;
end process;
dma_ctrlstat_reg <= (
BIT_DMA_RUN => dma_run,
BIT_DMA_IRQ => dma_irq,
--
others => '0'
);
with to_integer(unsigned(address)) select
readdata <= dma_ctrlstat_reg when REG_DMA_CTRLSTAT_SET | REG_DMA_CTRLSTAT_CLR,
dma_start_addr_l when REG_DMA_START_ADDR_L,
dma_start_addr_h when REG_DMA_START_ADDR_H,
dma_length & dma_block_size & dma_packet_size when REG_DMA_SIZE,
dma_timeout when REG_DMA_TIMEOUT,
std_logic_vector(dma_curr_addr_l) when REG_DMA_CURR_ADDR_L,
std_logic_vector(dma_curr_addr_h) when REG_DMA_CURR_ADDR_H,
std_logic_vector(stat_pkts_received) when REG_STAT_PKT_RECEIVED,
std_logic_vector(stat_pkts_accepted) when REG_STAT_PKT_ACCEPTED,
std_logic_vector(stat_pkt_overruns) when REG_STAT_PKT_OVERRUNS,
std_logic_vector(stat_pkt_underruns) when REG_STAT_PKT_UNDERRUNS,
std_logic_vector(stat_fifo_overruns) when REG_STAT_FIFO_OVERRUNS,
(others => 'X') when others;
FIFO_0 : entity work.dvb_dma_fifo_ram
port map (
wrclock => clk,
wraddress => fifo_wraddr,
data => fifo_wrdata,
wren => fifo_wren,
--
rdclock => clk,
rdclocken => fifo_rdclken,
rdaddress => fifo_rdaddr,
q => fifo_rddata
);
fifo_wraddr <= std_logic_vector(write_addr_h & write_addr_l);
fifo_wrdata <= dvb_latch_data;
fifo_wren <= dvb_latch_dval;
fifo_rdaddr <= std_logic_vector(read_addr_h & read_addr_l);
fifo_rdclken <= mem_write_i nand mem_waitreq;
fifo_full <= write_page(write_page'left) xor read_page(read_page'left) when write_addr_h = read_addr_h else '0';
fifo_empty <= '1' when write_page = read_page else '0';
pkt_size(pkt_size'left) <= '1' when unsigned(dma_packet_size) = 0 else '0';
pkt_size(pkt_size'left - 1 downto 0) <= unsigned(dma_packet_size);
block_size(block_size'left) <= '1' when unsigned(dma_block_size) = 0 else '0';
block_size(block_size'left - 1 downto 0) <= unsigned(dma_block_size);
blocks_num(blocks_num'left) <= '1' when unsigned(dma_length) = 0 else '0';
blocks_num(blocks_num'left - 1 downto 0) <= unsigned(dma_length);
process (rst, dma_run, clk)
variable sop : std_logic;
variable burst_size : unsigned(8 downto 0);
begin
if rising_edge(clk) then
-- FIFO primary side
sop := dvb_sop and dvb_dval;
--
dvb_latch_data <= dvb_data;
dvb_latch_dval <= dvb_dval and ((dvb_sop and not fifo_full) or (dvb_cnt(dvb_cnt'left) and not fifo_overflow));
if dvb_dval then
if dvb_sop then
fifo_overflow <= fifo_full;
end if;
if dvb_sop then
dvb_cnt <= unsigned('1' & (-signed(dma_packet_size))) + 1;
elsif dvb_cnt(dvb_cnt'left) then
dvb_cnt <= dvb_cnt + 1;
end if;
if dvb_sop then
dvb_overrun_n <= '1';
else
dvb_overrun_n <= dvb_cnt(dvb_cnt'left);
end if;
end if;
if sop then
write_addr_l <= (others => '0');
elsif dvb_latch_dval then
write_addr_l <= write_addr_l + 1;
end if;
if not dvb_cnt(dvb_cnt'left) and dvb_latch_dval then
write_page <= write_page + 1;
end if;
-- statistic counters
if sop then
stat_pkts_received <= stat_pkts_received + 1;
end if;
if not dvb_cnt(dvb_cnt'left) and dvb_latch_dval then
stat_pkts_accepted <= stat_pkts_accepted + 1;
end if;
if not dvb_cnt(dvb_cnt'left) and dvb_dval and not dvb_sop and dvb_overrun_n then
stat_pkt_overruns <= stat_pkt_overruns + 1;
end if;
if sop and dvb_cnt(dvb_cnt'left) then
stat_pkt_underruns <= stat_pkt_underruns + 1;
end if;
if sop and fifo_full then
stat_fifo_overruns <= stat_fifo_overruns + 1;
end if;
-- FIFO secondary side
if fifo_rdclken then
if burst_end then
burst <= '0';
elsif not fifo_empty then
burst <= '1';
end if;
if not burst then
dma_cnt <= (others => '0');
else
dma_cnt <= dma_cnt + 8;
end if;
if dma_cnt < pkt_size then
fifo_latch_valid <= burst;
else
fifo_latch_valid <= '0';
end if;
fifo_rddata_valid <= fifo_latch_valid;
if not fifo_latch_valid and fifo_rddata_valid then
read_page <= read_page + 1;
end if;
-- bus alignment
dma_reg <= fifo_rddata;
case std_logic_vector(fifo_latch_valid & pkt_size(2 downto 0)) is
when "0111" =>
dma_reg_be <= (7 => '0', others => fifo_rddata_valid);
when "0110" =>
dma_reg_be <= (7 downto 6 => '0', others => fifo_rddata_valid);
when "0101" =>
dma_reg_be <= (7 downto 5 => '0', others => fifo_rddata_valid);
when "0100" =>
dma_reg_be <= (7 downto 4 => '0', others => fifo_rddata_valid);
when "0011" =>
dma_reg_be <= (7 downto 3 => '0', others => fifo_rddata_valid);
when "0010" =>
dma_reg_be <= (7 downto 2 => '0', others => fifo_rddata_valid);
when "0001" =>
dma_reg_be <= (7 downto 1 => '0', others => fifo_rddata_valid);
when others =>
dma_reg_be <= (others => fifo_rddata_valid);
end case;
dma_reg_pad <= dma_reg(63 downto 8);
dma_reg_pad_be <= dma_reg_be(7 downto 1);
case burst_addr(2 downto 0) is
when "111" =>
mem_wrdata <= dma_reg(7 downto 0) & dma_reg_pad;
mem_byteen <= dma_reg_be(0) & dma_reg_pad_be;
dma_reg_pad_wren <= dma_reg_be(1);
when "110" =>
mem_wrdata <= dma_reg(15 downto 0) & dma_reg_pad(63 downto 16);
mem_byteen <= dma_reg_be(1 downto 0) & dma_reg_pad_be(7 downto 2);
dma_reg_pad_wren <= dma_reg_be(2);
when "101" =>
mem_wrdata <= dma_reg(23 downto 0) & dma_reg_pad(63 downto 24);
mem_byteen <= dma_reg_be(2 downto 0) & dma_reg_pad_be(7 downto 3);
dma_reg_pad_wren <= dma_reg_be(3);
when "100" =>
mem_wrdata <= dma_reg(31 downto 0) & dma_reg_pad(63 downto 32);
mem_byteen <= dma_reg_be(3 downto 0) & dma_reg_pad_be(7 downto 4);
dma_reg_pad_wren <= dma_reg_be(4);
when "011" =>
mem_wrdata <= dma_reg(39 downto 0) & dma_reg_pad(63 downto 40);
mem_byteen <= dma_reg_be(4 downto 0) & dma_reg_pad_be(7 downto 5);
dma_reg_pad_wren <= dma_reg_be(5);
when "010" =>
mem_wrdata <= dma_reg(47 downto 0) & dma_reg_pad(63 downto 48);
mem_byteen <= dma_reg_be(5 downto 0) & dma_reg_pad_be(7 downto 6);
dma_reg_pad_wren <= dma_reg_be(6);
when "001" =>
mem_wrdata <= dma_reg(55 downto 0) & dma_reg_pad(63 downto 56);
mem_byteen <= dma_reg_be(6 downto 0) & dma_reg_pad_be(7);
dma_reg_pad_wren <= dma_reg_be(7);
when others =>
mem_wrdata <= dma_reg;
mem_byteen <= dma_reg_be;
dma_reg_pad_wren <= '0';
end case;
mem_write_i <= dma_reg_be(0) or dma_reg_pad_wren;
end if;
if not mem_write_i and dma_reg_be(0) then
burst_size := pkt_size + burst_addr(2 downto 0) + 7;
mem_size <= '0' & std_logic_vector(burst_size(8 downto 3));
end if;
burst_end <= (mem_write_i and not mem_waitreq) and (dma_reg_be(0) nor dma_reg_pad_wren);
-- process memory pointers
if dma_pkt_cnt = block_size then
dma_irq_pend <= not dma_irq_pend;
else
dma_irq_pend <= '0';
end if;
if dma_blk_cnt = blocks_num then
dma_reload_n <= not dma_reload_n;
else
dma_reload_n <= '1';
end if;
if dma_irq_pend then
dma_pkt_cnt <= (others => '0');
elsif burst_end then
dma_pkt_cnt <= dma_pkt_cnt + 1;
end if;
if not dma_reload_n then
dma_blk_cnt <= (others => '0');
elsif dma_irq_pend then
dma_blk_cnt <= dma_blk_cnt + 1;
end if;
if not dma_reload_n then
burst_addr <= unsigned(dma_start_addr);
elsif burst_end then
burst_addr <= burst_addr + pkt_size;
end if;
-- interrupts and status
if not dma_irq then
dma_curr_addr <= burst_addr;
end if;
if dma_irq_reset then
dma_irq <= '0';
elsif dma_irq_pend or (not dma_timer(dma_timer'left) and dma_timer_d) then
dma_irq <= '1';
end if;
-- DMA timeout timer
if burst_end or not dma_timer(dma_timer'left) then
dma_timer <= -signed('0' & dma_timeout);
else
dma_timer <= dma_timer + 1;
end if;
dma_timer_d <= dma_timer(dma_timer'left);
end if;
if not dma_run then
dvb_latch_data <= (others => '0');
dvb_latch_dval <= '0';
dvb_cnt <= (others => '0');
write_addr_l <= (others => '0');
write_page <= (others => '0');
dvb_overrun_n <= '0';
fifo_overflow <= '0';
-- statistic counters
stat_pkts_received <= (others => '0');
stat_pkts_accepted <= (others => '0');
stat_pkt_overruns <= (others => '0');
stat_pkt_underruns <= (others => '0');
stat_fifo_overruns <= (others => '0');
--
read_page <= (others => '0');
--
dma_pkt_cnt <= (others => '0');
dma_blk_cnt <= (others => '0');
dma_irq_pend <= '0';
dma_reload_n <= '0';
--
dma_curr_addr <= (others => '0');
dma_irq <= '0';
--
dma_timer <= (others => '0');
dma_timer_d <= '0';
end if;
if rst then
dma_cnt <= (others => '0');
fifo_latch_valid <= '0';
fifo_rddata_valid <= '0';
dma_reg <= (others => '0');
dma_reg_be <= (others => '0');
dma_reg_pad <= (others => '0');
dma_reg_pad_be <= (others => '0');
dma_reg_pad_wren <= '0';
--
burst <= '0';
burst_end <= '0';
burst_addr <= (others => '0');
--
mem_byteen <= (others => '0');
mem_wrdata <= (others => '0');
mem_write_i <= '0';
end if;
end process;
mem_addr <= std_logic_vector(burst_addr(63 downto 3));
mem_write <= mem_write_i;
interrupt <= dma_irq;
end;
|
------------------------------------------------------------------------------
-- File name: top_cpu.vhd
-- Function : Top file for the Tomasulo CPU project with file i/o
-- Modified by : Prasanjeet Das
-- Date : 7/20/09, 7/24/09, 7/25/09
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all; -- Xilinx primitive BUFGP
entity top_cpu is
port (
CLK_PORT : in std_logic;
sw0, sw1, sw2, sw3, sw4, sw5, sw6, sw7 : in std_logic; --changed by PRASANJEET
btn3 : in std_logic;
btn2 : in std_logic;
btn1, btn0 : in std_logic;
St_ce_bar, St_rp_bar, Mt_ce_bar, Mt_St_we_bar, Mt_St_oe_bar : out std_logic;
LD7, LD6, LD5, LD4, LD3, LD2, LD1, LD0 : out std_logic;
ca, cb, cc, cd, ce, cf, cg, dp : out std_logic;
AN0, AN1, AN2, AN3 : out std_logic;
------------------------------------------------------------------------
-- Epp-like bus signals (ports to connect to the Cypress USB intrerface)
EppAstb: in std_logic; -- Address strobe --changed by PRASANJEET
EppDstb: in std_logic; -- Data strobe --changed by PRASANJEET
EppWr : in std_logic; -- Port write signal --changed by PRASANJEET
EppDB : inout std_logic_vector(7 downto 0); -- port data bus --changed by PRASANJEET
EppWait: out std_logic; -- Port wait signal --changed by PRASANJEET
------------------------------------------------------------------------
-- user extended signals
Led : in std_logic_vector(7 downto 0); -- 0x01 8 virtual LEDs on the PC I/O Ex GUI --changed by PRASANJEET
LBar : in std_logic_vector(23 downto 0); -- 0x02..4 24 lights on the PC I/O Ex GUI light bar --changed by PRASANJEET
Sw : out std_logic_vector(15 downto 0); -- 0x05..6 16 switches, bottom row on the PC I/O Ex GUI --changed by PRASANJEET
dwOut: out std_logic_vector(31 downto 0); -- 0x09..b 32 Bits user output --changed by PRASANJEET
dwIn : in std_logic_vector(31 downto 0) -- 0x0d..10 32 Bits user input --changed by PRASANJEET
);
end top_cpu ;
------------------------------------------------------------------------------
architecture top_cpu_arc of top_cpu is
SIGNAL clock_half : std_logic ;
signal Resetb : std_logic;
signal BCLK : std_logic;
signal BCLK_TEMP : std_logic;
-- signals to go into the logic under test
signal clk_top, resetb_top : std_logic;
-- component declarations
component tomasulo_top
port (
Reset : in std_logic;
--digi_address : in std_logic_vector(5 downto 0); -- input ID for the register we want to see
--digi_data : out std_logic_vector(31 downto 0); -- output data given by the register
Clk : in std_logic;
--modified by Prasanjeet
-- signals corresponding to Instruction memory
fio_icache_addr_IM : in std_logic_vector(5 downto 0); --changed by PRASANJEET
fio_icache_data_in_IM : in std_logic_vector(127 downto 0); --changed by PRASANJEET
fio_icache_wea_IM : in std_logic; --changed by PRASANJEET
fio_icache_data_out_IM : out std_logic_vector(127 downto 0); --changed by PRASANJEET
fio_icache_ena_IM : in std_logic; -- changed by PRASANJEET
fio_dmem_addr_DM : in std_logic_vector(5 downto 0); --changed by PRASANJEET
fio_dmem_data_out_DM : out std_logic_vector(31 downto 0); --changed by PRASANJEET
fio_dmem_data_in_DM : in std_logic_vector(31 downto 0); --changed by PRASANJEET
fio_dmem_wea_DM : in std_logic; --changed by PRASANJEET
Test_mode : in std_logic; -- for using the test mode
walking_led_start : out std_logic
-- end modified by Prasanjeet
);
end component ;
-- debouncer
component ee560_debounce is
generic (N_dc: positive := 23);
port (CLK, RESETB_DEBOUNCE :in std_logic; -- CLK = 50 MHz
PB :in std_logic; -- push button
DPB, SCEN, MCEN, CCEN :out std_logic );
end component ee560_debounce ;
--bufgp for clock
component BUFGP
port (I: in std_logic; O: out std_logic);
end component;
component BUFG
port (I: in std_logic; O: out std_logic);
end component;
--signals for file i/o
signal Addr_Mem_IM, Addr_Mem_DM, Addr_Mem : std_logic_vector(5 downto 0); -- address going to user memory -- here it is 4 bits
signal WE_Mem_IM, WE_Mem_DM: std_logic; -- Write Enable, Read Enable control signals to user memory
signal Data_to_Mem_IM, Data_to_Mem: std_logic_vector(127 downto 0); -- data to be written to memory
signal Data_to_Mem_DM : std_logic_vector(31 downto 0);
signal Data_from_Mem_IM, Data_from_Mem: std_logic_vector(127 downto 0); -- data to be read from memory
signal Data_from_Mem_DM : std_logic_vector(31 downto 0);
signal test_in: std_logic;
------------
signal regEppAdr: std_logic_vector (7 downto 0); -- Epp address register
signal regVer: std_logic_vector(7 downto 0); -- 0x00 I/O returns the complement of written value -- for I/O Ex Tab
signal busEppInternal: std_logic_vector(7 downto 0); -- internal bus (before tristate)
-- added by Sabya --
signal Mem_Select_Reg: std_logic_vector (7 downto 0); -- 0x2A; we get Sel_IM_Bar_Slash_DM from this
signal Control_Reg: std_logic_vector (7 downto 0); -- 0x2B; We get test mode from this. Not needed in the current design.
-- Type declaration
type state_type is (IDLE, -- idle state(1)
A_RD_FINISH, -- finish reading from address register (2)
A_WR_START, -- start writing to address register(3)
A_WR_FINISH, -- finish writing from address register (4)
OTHER_RD_FINISH, -- finish reading from other than pointer and data memory (5)
OTHER_WR_FINISH, -- finish writing to other than pointer and data memory (6)
OTHER_WR_START, -- start writing to other than pointer and data memory (7)
PNTR_RD_START, -- start reading the memory pointer (8)
PNTR_RD_FINISH, -- finish reading the memory pointer(9)
PNTR_WR_START, -- start writing the memory pointer(10)
PNTR_WR_FINISH, -- finish writing the memory pointer(11)
M_RD_START_1_8, -- start reading data memory (12)
M_RD_FINISH_1_8, -- finish reading data memory(13)
M_RD_START_9_10, -- deals with carriage return and line feed (14)
M_RD_FINISH_9_10, -- deals with carriage return and line feed (15)
M_WR_START_1_8, -- start writing data memory (16)
M_WR_FINISH_1_8, -- finish writing data memory(17)
M_WR_START_9_10, -- deals with carriage return and line feed (18)
M_WR_FINISH_9_10, -- deals with carriage return and line feed (19)
INC_NIB_COUNT, -- increment the nibble counter (20)
INC_MEM_PNTR -- increment the mem_pointer (21)
);
-- Intermediate signal declarations
signal current_state : state_type;
--intermediate signals of the state machine
signal EN_A_RD, EN_M_RD, EN_A_WR, EN_M_WR, EN_PNTR_RD, EN_PNTR_WR, EN_OTHER_RD: std_logic; -- all the read and write enable signals
signal EN_REG_WR, EN_REG_RD: std_logic; -- read and write signals for register file
signal ASTB_S, DSTB_S, ASTB_SS, DSTB_SS : std_logic; -- signals used for double synchronizing address and data strobe
signal D_int1, D_int2, D_int3: std_logic_vector(7 downto 0); -- signals used for registering the Eppdata
signal A_int1, A_int2, A_int3: std_logic_vector(7 downto 0); -- signals used for registering the EppAddress
signal wait_Epp: std_logic; -- internal signal used for EppWait;
signal pointer: std_logic_vector(7 downto 0); -- pointer to memory
signal i: std_logic_vector(1 downto 0); --internal counter
--signal clk, resetb: std_logic; -- clk and Resetb signals
signal nib_count: std_logic_vector(5 downto 0); -- to count the nibbles
signal nib_on_file: std_logic_vector(7 downto 0); -- show the nibbles on the file
signal Sel_IM_Bar_Slash_DM: std_logic; -- A Flip-Flop Resetb or set by SW0 to select between IM/DM; -- FF output = '0' => IM, '1' => DM
-- *****************************************************************************************
-- constant declarations
-- 40, 41 for instruction memory
-- *****************************************************************************************
constant addr_mem_pointer: std_logic_vector(7 downto 0) := X"28"; --40 dec - 28 hex
constant addr_memory: std_logic_vector(7 downto 0) := X"29"; --41 dec - 29 hex
-- added by sabya
constant addr_Mem_Select_Reg: std_logic_vector(7 downto 0) := X"2A";
constant addr_Control_Reg: std_logic_vector(7 downto 0) := X"2B";
--******************************************************************************************
-- intermediate signals for data conversion
signal BINARY, binary_in : std_logic_vector(3 downto 0); -- - BINARY for FPGA ==> File and binary_in for File ==> FPGA
signal ASCII, ascii_out: std_logic_vector(7 downto 0); -- ASCII for ,File ==> FPGA and ascii_out for FPGA ==> File
signal extended_zero : std_logic_vector(95 downto 0);
-- signals used for the array of registers to store the nibbles
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
subtype reg_mem is std_logic_vector(3 downto 0); --register array declaration
type reg_type is array (0 to 31) of reg_mem;
signal reg_array : reg_type;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
signal divclk: std_logic_vector(1 downto 0); -- the divided clock
--***************************************************************
signal reset_fileio, reset_tomasulo: std_logic;
--signal r_sw2, r_sw3: std_logic; -- Resetb signals
--++++++++++++++++++++++++++++++++++++++++++++
signal walking_led: std_logic_vector(7 downto 0); -- walking led counter.
signal walking_led_en: std_logic;
signal walking_led_clk: std_logic_vector(22 downto 0);
signal w_led: std_logic_vector(2 downto 0); -- encoded walking led pattern
--++++++++++++++++++++++++++++++++++++++++++++++++
-- signals from debouncers
signal db_btn0,db_btn1: std_logic;
--++++++++++++++++++++++++++++++++++++++++++++++++++
begin
cpu_2_inst : tomasulo_top
port map (
Reset => reset_tomasulo,
Clk => clk_top,
fio_icache_addr_IM => Addr_Mem_IM, --changed by PRASANJEET
fio_icache_data_in_IM => Data_to_Mem_IM, --changed by PRASANJEET
fio_icache_wea_IM => WE_Mem_IM, --changed by PRASANJEET
fio_icache_data_out_IM => Data_from_Mem_IM,--changed by PRASANJEET
fio_icache_ena_IM => '1', -- changed by PRASANJEET
fio_dmem_addr_DM => Addr_Mem_DM,--changed by PRASANJEET
fio_dmem_data_out_DM => Data_from_Mem_DM, --changed by PRASANJEET
fio_dmem_data_in_DM => Data_to_Mem_DM, --changed by PRASANJEET
fio_dmem_wea_DM => WE_Mem_DM, --changed by PRASANJEET
Test_mode => test_in, -- changed by PRASANJEET
walking_led_start => walking_led_en --changed by PRASANJEET
);
BUF_GP_1: BUFGP port map (I => CLK_PORT, O => BCLK_TEMP);
------------
--concurrent assignments
-- send address and data to both the memories, it's the control signal WE which will determine which memory to write
Data_to_mem_IM <= Data_to_mem;
Data_to_mem_DM <= Data_to_mem(127 downto 96);
Addr_mem_IM <= Addr_mem;
Addr_mem_DM <= Addr_mem;
Data_from_mem <= Data_from_mem_IM when Sel_IM_Bar_Slash_DM = '0' else Data_from_mem_DM&extended_zero; --Data to be read from memory is sent to the file on the control of swith sw0
WE_Mem_IM <= EN_M_WR when Sel_IM_Bar_Slash_DM = '0' else '0'; -- the Sel_IM_Bar_Slash_DM is controlled by sw0
WE_Mem_DM <= EN_M_WR when Sel_IM_Bar_Slash_DM = '1' else '0';
extended_zero <= (others =>'0');
------------------------------------------------------------------------------
--Clock Divider derives slower clocks from the 50 MHz clock on s2 board
CLOCK_DIVIDER1: process (BCLK_TEMP, resetb_top)
begin
if (resetb_top = '0') then
divclk <= (others => '0');
elsif (BCLK_TEMP'event and BCLK_TEMP = '1') then
divclk <= divclk + '1';
end if;
end process CLOCK_DIVIDER1;
--da cheng july17 2011
clock_half <= divclk(1); -- this is 25MHz clock
BUF_G_3: BUFG port map (I => clock_half, O => BCLK);
---------------------------------------------------------------------
walking_led_pro: process(clk_top, resetb_top)
begin
if(resetb_top = '0')then
walking_led_clk <= (others =>'0');
elsif(clk_top'event and clk_top = '1')then
if(walking_led_en = '1')then
walking_led_clk <= walking_led_clk + '1';
end if;
end if;
end process walking_led_pro;
-- ---------------------------------------------------------
--w_led <= walking_led_clk(20 downto 18);
--Da Cheng modified at July 17 2011
w_led <= walking_led_clk(22 downto 20);
-- -- decoder to produce one hot signals
walking_led <= "00000001" when w_led = "000" else
"00000010" when w_led = "001" else
"00000100" when w_led = "010" else
"00001000" when w_led = "011" else
"00010000" when w_led = "100" else
"00100000" when w_led = "101" else
"01000000" when w_led = "110" else
"10000000" when w_led = "111" else
"11111111";
-- ----------------------------------------------------------
--
---------------------------
--concurrent assignments
Resetb <= btn3;--this is active high system Resetb
--added by PRASANJEET
-------------------------------------------------------
resetb_top <= not(btn3); --the Resetb to the debouncer (this is system reset)
-------------------------------------------------------
clk_top <= BCLK;
--process to store the nibbles into the register file
write_reg: process(clk_top)
begin
if(clk_top'event and clk_top = '1')then
if(EN_REG_WR = '1')then
reg_array(CONV_INTEGER(UNSIGNED(nib_count(4 downto 0)))) <= binary_in;
end if;
end if;
end process write_reg;
-------------------------------------------------------------------------------
-- disabling the seven segment display
ca <= '1' ;
cb <= '1' ;
cc <= '1' ;
cd <= '1' ;
ce <= '1' ;
cf <= '1' ;
cg <= '1' ;
dp <= sw3 and sw4 and sw5 and sw6 and sw7 and btn0 and btn2 ; -- just to remove the synthesis warnings let all the unused switches and buttons drive something
AN0 <= '1' ;
AN1 <= '1' ;
AN2 <= '1' ;
AN3 <= '1' ;
-- disabling the flash / memory
St_ce_bar <= '1';
Mt_ce_bar <= '1';
St_rp_bar <= '1';
Mt_St_we_bar <= '1';
Mt_St_oe_bar <= '1';
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
LD6 <= walking_led(6);
LD7 <= walking_led(7);-- just to check for wait signal
LD5 <= walking_led(5); LD4 <= walking_led(4);
LD3 <= walking_led(3); LD2 <= walking_led(2) ; LD1 <= walking_led(1); LD0 <= walking_led(0);
-- --****************************************************************************************************
--++++++++++++++++++++++++++++++++
Addr_mem <= pointer(5 downto 0); -- 6 bit address
--++++++++++++++++++++++++++++++++
-- Epp signals
-- Port signals
EppWait <= wait_Epp;
EppDB <= busEppInternal when (EppWr = '1') else "ZZZZZZZZ";
busEppInternal <=
regEppAdr when (EN_A_RD = '1') else
nib_on_file when (EN_M_RD = '1')else --this is the nibble being sent to the file
pointer when (EN_PNTR_RD = '1')else
--@Sabya:- add Mem_Select_Reg and Control_Reg here
Mem_Select_Reg when (EN_OTHER_RD = '1') and (regEppAdr = addr_Mem_Select_Reg) else
Control_Reg when (EN_OTHER_RD = '1') and (regEppAdr = addr_Control_Reg) else
regVer when (EN_OTHER_RD = '1') else --later on to be expanded and qualified with address (regEppAdr = x00)
Led when (regEppAdr = x"01") else
LBar(7 downto 0) when (regEppAdr = x"02") else
LBar(15 downto 8) when (regEppAdr = x"03") else
LBar(23 downto 16) when (regEppAdr = x"04") else
dwIn(7 downto 0) when (regEppAdr = x"0d") else
dwIn(15 downto 8) when (regEppAdr = x"0e") else
dwIn(23 downto 16) when (regEppAdr = x"0f") else
dwIn(31 downto 24) ;
--output function logic
EN_A_RD <= '1' when (current_state = A_RD_FINISH) else '0';
EN_OTHER_RD <= '1' when (current_state = OTHER_RD_FINISH) else '0';
EN_REG_RD <= '1'; --always read the register file
EN_REG_WR <= '1' when (current_state = M_WR_START_1_8 or current_state = M_WR_FINISH_1_8) else '0';
EN_M_RD <= '1' when (current_state = M_RD_START_1_8 or current_state = M_RD_FINISH_1_8 or current_state = M_RD_START_9_10 or current_state = M_RD_FINISH_9_10) else '0';
EN_PNTR_RD <= '1' when (current_state = PNTR_RD_START or current_state = PNTR_RD_FINISH) else '0';
EN_A_WR <= '1' when (current_state = A_WR_START or current_state = A_WR_FINISH) else '0';
EN_M_WR <= '1' when (current_state = M_WR_START_9_10 or current_state = M_WR_FINISH_9_10) else '0';
EN_PNTR_WR <= '1' when (current_state = PNTR_WR_START or current_state = PNTR_WR_FINISH) else '0';
wait_Epp <= '1' when (current_state = A_WR_FINISH or current_state = A_RD_FINISH or current_state = M_WR_FINISH_9_10 or current_state = M_RD_FINISH_9_10
or current_state = PNTR_WR_FINISH or current_state = PNTR_RD_FINISH or current_state = OTHER_WR_FINISH or current_state = OTHER_RD_FINISH
or current_state = M_WR_FINISH_1_8 or current_state = M_RD_FINISH_1_8 or current_state = INC_NIB_COUNT or current_state = INC_MEM_PNTR)
else '0';
nib_on_file <= X"0D" when ((nib_count = "001000" and Sel_IM_Bar_Slash_DM = '1') or (nib_count = "100000" and Sel_IM_Bar_Slash_DM = '0') )else -- carriage return --0D
X"0A" when ((nib_count = "001001" and Sel_IM_Bar_Slash_DM = '1') or (nib_count = "100001" and Sel_IM_Bar_Slash_DM = '0') )else --line feed --0A
ascii_out; -- the nibble being read from memory
--***********************************************************
ascii_out <= X"30" when (BINARY = "0000") else --hex 0
X"31" when (BINARY = "0001") else --hex 1
X"32" when (BINARY = "0010") else --hex 2
X"33" when (BINARY = "0011") else --hex 3
X"34" when (BINARY = "0100") else --hex 4
X"35" when (BINARY = "0101") else --hex 5
X"36" when (BINARY = "0110") else --hex 6
X"37" when (BINARY = "0111") else --hex 7
X"38" when (BINARY = "1000") else --hex 8
X"39" when (BINARY = "1001") else --hex 9
X"41" when (BINARY = "1010") else --hex A
X"42" when (BINARY = "1011") else --hex B
X"43" when (BINARY = "1100") else --hex C
X"44" when (BINARY = "1101") else --hex D
X"45" when (BINARY = "1110") else --hex E
X"46" when (BINARY = "1111") else --hex F
X"37";
binary_in <= "0000" when (ASCII = X"30") else
"0001" when (ASCII = X"31") else
"0010" when (ASCII = X"32") else
"0011" when (ASCII = X"33") else
"0100" when (ASCII = X"34") else
"0101" when (ASCII = X"35") else
"0110" when (ASCII = X"36") else
"0111" when (ASCII = X"37") else
"1000" when (ASCII = X"38") else
"1001" when (ASCII = X"39") else
"1010" when (ASCII = X"41") else
"1011" when (ASCII = X"42") else
"1100" when (ASCII = X"43") else
"1101" when (ASCII = X"44") else
"1110" when (ASCII = X"45") else
"1111" when (ASCII = X"46") else
"0110";
--************************************************************
BINARY <= Data_from_mem(3 downto 0) when (nib_count = "011111")else
Data_from_mem(7 downto 4) when (nib_count = "011110")else
Data_from_mem(11 downto 8) when (nib_count = "011101")else
Data_from_mem(15 downto 12) when (nib_count = "011100")else
Data_from_mem(19 downto 16) when (nib_count = "011011")else
Data_from_mem(23 downto 20) when (nib_count = "011010")else
Data_from_mem(27 downto 24) when (nib_count = "011001")else
Data_from_mem(31 downto 28) when (nib_count = "011000")else
Data_from_mem(35 downto 32) when (nib_count = "010111")else
Data_from_mem(39 downto 36) when (nib_count = "010110")else
Data_from_mem(43 downto 40) when (nib_count = "010101")else
Data_from_mem(47 downto 44) when (nib_count = "010100")else
Data_from_mem(51 downto 48) when (nib_count = "010011")else
Data_from_mem(55 downto 52) when (nib_count = "010010")else
Data_from_mem(59 downto 56) when (nib_count = "010001")else
Data_from_mem(63 downto 60) when (nib_count = "010000")else
Data_from_mem(67 downto 64) when (nib_count = "001111")else
Data_from_mem(71 downto 68) when (nib_count = "001110")else
Data_from_mem(75 downto 72) when (nib_count = "001101")else
Data_from_mem(79 downto 76) when (nib_count = "001100")else
Data_from_mem(83 downto 80) when (nib_count = "001011")else
Data_from_mem(87 downto 84) when (nib_count = "001010")else
Data_from_mem(91 downto 88) when (nib_count = "001001")else
Data_from_mem(95 downto 92) when (nib_count = "001000")else
Data_from_mem(99 downto 96) when (nib_count = "000111")else
Data_from_mem(103 downto 100) when (nib_count = "000110")else
Data_from_mem(107 downto 104) when (nib_count = "000101")else
Data_from_mem(111 downto 108) when (nib_count = "000100")else
Data_from_mem(115 downto 112) when (nib_count = "000011")else
Data_from_mem(119 downto 116) when (nib_count = "000010")else
Data_from_mem(123 downto 120) when (nib_count = "000001")else
Data_from_mem(127 downto 124) when (nib_count = "000000")else
"1010";
-- notice that we start with most significant nibble and end with the least significant nibble
--clocked process with asynchronous active low Resetb for double synchronization
double_sync: process (clk_top, reset_fileio) --double synchronizing to safeguard against metastability
begin
if (reset_fileio = '0') then
ASTB_S <= '1';
DSTB_S <= '1';
ASTB_SS <= '1';
DSTB_SS <= '1';
elsif (clk_top'event and clk_top = '1') then
ASTB_S <= EppAstb;
ASTB_SS <= ASTB_S;
DSTB_S <= EppDstb;
DSTB_SS <= DSTB_S;
end if;
end process double_sync;
-- clocked process with asynchronous active low Resetb for combined CU and DPU
CU_DPU: process (clk_top, reset_fileio)
begin
if (reset_fileio = '0') then
current_state <= IDLE;
i <= (others => 'X');
pointer <= (others => '0');
nib_count <= (others=> '0');
D_int1 <= (others => 'X');
D_int2 <= (others => 'X');
D_int3 <= (others => 'X');
A_int1 <= (others => 'X');
A_int2 <= (others => 'X');
A_int3 <= (others => 'X');
ASCII <= (others =>'X');
regver <=(others =>'X');
--added by sabya
Mem_Select_Reg <= (others =>'X');
Control_Reg <= (others =>'X');
regEppAdr <= (others =>'X');
elsif (clk_top'event and clk_top = '1') then
case (current_state) is
when IDLE => --(1)
-- CU state transitions
if(ASTB_SS = '0')then -- if adress strobe asserted and intent to write
if(EppWr = '0')then
current_state <= A_WR_START;
else
current_state <= A_RD_FINISH;
end if;
elsif(DSTB_SS = '0')then -- if data strobe asserted and intent to write
if(EppWr = '0')then
if(regEppAdr = addr_memory)then
if(((nib_count = "001001" and Sel_IM_Bar_Slash_DM = '1')or (nib_count = "100001" and Sel_IM_Bar_Slash_DM = '0')) or ((nib_count = "001000" and Sel_IM_Bar_Slash_DM = '1' )or(nib_count = "100000" and Sel_IM_Bar_Slash_DM = '0')))then -- for nibble count >= 8(DM) or >= 32(IM)
current_state <= M_WR_START_9_10;
else
current_state <= M_WR_START_1_8;
end if;
elsif(regeppadr = addr_mem_pointer)then
current_state <= PNTR_WR_START;
else
current_state <= OTHER_WR_START;
end if;
else -- if data strobe asserted and intent to read
if(regeppadr = addr_memory)then
if(((nib_count = "001001" and Sel_IM_Bar_Slash_DM = '1')or (nib_count = "100001" and Sel_IM_Bar_Slash_DM = '0')) or ((nib_count = "001000" and Sel_IM_Bar_Slash_DM = '1' )or(nib_count = "100000" and Sel_IM_Bar_Slash_DM = '0')))then -- for nibble count >= 8(DM) or >= 32(IM)
current_state <= M_RD_START_9_10;
else
current_state <= M_RD_START_1_8;
end if;
elsif(regeppadr = addr_mem_pointer)then
current_state <= PNTR_RD_START;
else
current_state <= OTHER_RD_FINISH;
end if;
end if;
elsif (ASTB_SS = '1' and DSTB_SS = '1') then
current_state <= IDLE;
end if;
-- DPU RTL
i <= (others => '0');
when A_RD_FINISH => --(2)
-- CU state transitions
if (ASTB_SS = '1') then
current_state <= IDLE;
end if;
-- DPU RTL
i <= (others => '0');
when A_WR_START => --(3)
-- CU state transitions
if ( i = "11") then
current_state <= A_WR_FINISH;
end if;
-- DPU RTL
i <= i + "01";
A_int1 <= EppDB;
A_int2 <= A_int1;
A_int3 <= A_int2;
regeppadr <= A_int3;
when A_WR_FINISH => --(4)
-- CU state transitions
if (ASTB_SS = '1') then
current_state <= IDLE;
end if;
-- DPU RTL
A_int1 <= EppDB;
A_int2 <= A_int1;
A_int3 <= A_int2;
regeppadr <= A_int3;
when OTHER_RD_FINISH => --(5)
-- CU state transitions
if ( DSTB_SS = '1') then
current_state <= IDLE;
end if;
-- DPU RTL
-- NO DPU RTL
when OTHER_WR_START => --(6)
-- CU state transitions
if ( i = "11") then
current_state <= OTHER_WR_FINISH;
end if;
-- DPU RTL
i <= i + "01";
D_int1 <= EppDB; --applicable only for regeppaddr = x00
D_int2 <= D_int1;
D_int3 <= D_int2;
--@Sabya:- qualify this with regEppadr
-- default - regver
-- 0x2A - Mem_select_reg
-- 0x2B - Control_register
case regEppAdr is
when addr_Mem_Select_Reg => Mem_Select_Reg <= D_int3;
when addr_Control_Reg => Control_Reg <= D_int3;
when others => regver <= not(D_int3);
end case;
when OTHER_WR_FINISH => --(7)
-- CU state transitions
if (DSTB_SS = '1') then
current_state <= IDLE;
end if;
-- DPU RTL
D_int1 <= EppDB; --applicable only for regeppaddr = x00
D_int2 <= D_int1;
D_int3 <= D_int2;
--@Sabya:- qualify this with regEppadr
-- default - regver
-- 0x2A - Mem_select_reg
-- 0x2B - Control_register
case regEppAdr is
when addr_Mem_Select_Reg => Mem_Select_Reg <= D_int3;
when addr_Control_Reg => Control_Reg <= D_int3;
when others => regver <= not(D_int3);
end case;
when PNTR_RD_START => --(8)
-- CU state transitions
if ( i = "11") then
current_state <= PNTR_RD_FINISH;
end if;
-- DPU RTL
i <= i + "01";
when PNTR_RD_FINISH => --(9)
-- CU state transitions
if ( DSTB_SS = '1') then
current_state <= IDLE;
end if;
-- DPU RTL
--NO DPU RTL
when PNTR_WR_START => --(10)
-- CU state transitions
if ( i = "11") then
current_state <= PNTR_WR_FINISH;
end if;
-- DPU RTL
i <= i + "01";
D_int1 <= EppDB;
D_int2 <= D_int1;
D_int3 <= D_int2;
Pointer <= D_int3;
when PNTR_WR_FINISH => --(11)
-- CU state transitions
if ( DSTB_SS = '1') then
current_state <= IDLE;
end if;
-- DPU RTL
D_int1 <= EppDB;
D_int2 <= D_int1;
D_int3 <= D_int2;
Pointer <= D_int3;
when M_RD_START_1_8 => --(12)
-- CU state transitions
if ( i = "11") then
current_state <= M_RD_FINISH_1_8;
end if;
-- DPU RTL
i <= i + "01";
when M_RD_FINISH_1_8 => --(13)
-- CU state transitions
if ( DSTB_SS = '1') then
current_state <= INC_NIB_COUNT;
end if;
-- DPU RTL
--NO DPU RTL
when M_RD_START_9_10 => --(14)
-- CU state transitions
if ( i = "11") then
current_state <= M_RD_FINISH_9_10;
end if;
-- DPU RTL
i <= i + "01";
when M_RD_FINISH_9_10 => --(15)
-- CU state transitions
if ( DSTB_SS = '1') then
current_state <= INC_NIB_COUNT;
end if;
-- DPU RTL
--NO DPU RTL
when M_WR_START_1_8 => --(16)
-- CU state transitions
if ( i = "11") then
current_state <= M_WR_FINISH_1_8;
end if;
-- DPU RTL
i <= i + "01";
D_int1 <= EppDB;
D_int2 <= D_int1;
D_int3 <= D_int2;
ASCII <= D_int3; -- the data read from the file
when M_WR_FINISH_1_8 => --(17)
-- CU state transitions
if(DSTB_SS = '1')then
current_state <= INC_NIB_COUNT;
end if;
-- DPU RTL
D_int1 <= EppDB;
D_int2 <= D_int1;
D_int3 <= D_int2;
ASCII <= D_int3; -- the data read from the file
when M_WR_START_9_10 => --(18)
-- CU state transitions
if ( i = "11") then
current_state <= M_WR_FINISH_9_10;
end if;
-- DPU RTL
i <= i + "01";
Data_to_mem <= reg_array(0)®_array(1)®_array(2)®_array(3)®_array(4)®_array(5)®_array(6)®_array(7)
& reg_array(8)®_array(9)®_array(10)®_array(11)®_array(12)®_array(13)®_array(14)®_array(15)
& reg_array(16)®_array(17)®_array(18)®_array(19)®_array(20)®_array(21)®_array(22)®_array(23)
& reg_array(24)®_array(25)®_array(26)®_array(27)®_array(28)®_array(29)®_array(30)®_array(31);
when M_WR_FINISH_9_10 => --(19)
-- CU state transitions
if(DSTB_SS = '1')then
current_state <= INC_NIB_COUNT;
end if;
-- DPU RTL
Data_to_mem <= reg_array(0)®_array(1)®_array(2)®_array(3)®_array(4)®_array(5)®_array(6)®_array(7)
& reg_array(8)®_array(9)®_array(10)®_array(11)®_array(12)®_array(13)®_array(14)®_array(15)
& reg_array(16)®_array(17)®_array(18)®_array(19)®_array(20)®_array(21)®_array(22)®_array(23)
& reg_array(24)®_array(25)®_array(26)®_array(27)®_array(28)®_array(29)®_array(30)®_array(31);
when INC_NIB_COUNT => --(20)
-- CU state transitions
if((nib_count < "001001" and Sel_IM_Bar_Slash_DM = '1') or (nib_count < "100001" and Sel_IM_Bar_Slash_DM = '0'))then
current_state <= IDLE;
else
current_state <= INC_MEM_PNTR;
end if;
-- DPU RTL
nib_count <= nib_count + "000001";
when INC_MEM_PNTR => --(21)
-- CU state transitions
current_state <= IDLE;
-- DPU RTL
pointer <= pointer + "00000001";
nib_count <= "000000";
when others =>
current_state <= IDLE;
end case;
end if;
end process CU_DPU;
--@Sabya: Changed this so that it comes from the PC
Sel_IM_Bar_Slash_DM <= Mem_Select_Reg(0);
test_in<= Control_Reg(0);
reset_tomasulo<=Control_Reg(1);
--process to store the data sent by sw0 into a register sel_IM_Slash_DM
-- Sel_IM_Bar_Slash_DM_process: process (clk_top)
-- begin
-- if (clk_top'event and clk_top = '1') then
-- Sel_IM_Bar_Slash_DM <= sw0;
-- test_in <= sw1; -- NOTE test mode is set by switch 1.
-- reset_tomasulo <= sw2; --reset_tomasulo
--r_sw2 <= sw2;
--r_sw3 <= sw3;
-- end if;
-- end process Sel_IM_Bar_Slash_DM_process;
btn1_debouncer: ee560_debounce --btn1 used as Resetb for fileio
generic map (N_dc => 25)
port map (clk => clk_top, RESETB_DEBOUNCE => reset_fileio, -- CLK = 50 MHz
PB => btn1,
DPB => db_btn1, SCEN => open, MCEN => open, CCEN => open );
reset_fileio <= not(db_btn1);
end top_cpu_arc ;
------------------------------------------------------------------------------
|
--
-- FeedbackMemory.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
--
-- This module represents a store for feedback data of all OPLL channels. The feedback
-- data is written by the OutputGenerator module. Then the value written is
-- read from the Operator module.
--
entity FeedbackMemory is port (
clk : in std_logic;
reset : in std_logic;
wr : in std_logic;
waddr : in CH_TYPE;
wdata : in SIGNED_LI_TYPE;
raddr : in CH_TYPE;
rdata : out SIGNED_LI_TYPE
);
end FeedbackMemory;
architecture RTL of FeedbackMemory is
type SIGNED_LI_ARRAY_TYPE is array (0 to MAXCH-1) of SIGNED_LI_VECTOR_TYPE;
signal data_array : SIGNED_LI_ARRAY_TYPE;
begin
process(clk, reset)
variable init_ch : integer range 0 to MAXCH;
begin
if reset = '1' then
init_ch := 0;
elsif clk'event and clk='1' then
if init_ch /= MAXCH then
data_array(init_ch) <= (others=>'0');
init_ch := init_ch + 1;
elsif wr='1' then
data_array(waddr) <= CONV_SIGNED_LI_VECTOR(wdata);
end if;
rdata <= CONV_SIGNED_LI(data_array(raddr));
end if;
end process;
end RTL; |
--
-- FeedbackMemory.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
--
-- This module represents a store for feedback data of all OPLL channels. The feedback
-- data is written by the OutputGenerator module. Then the value written is
-- read from the Operator module.
--
entity FeedbackMemory is port (
clk : in std_logic;
reset : in std_logic;
wr : in std_logic;
waddr : in CH_TYPE;
wdata : in SIGNED_LI_TYPE;
raddr : in CH_TYPE;
rdata : out SIGNED_LI_TYPE
);
end FeedbackMemory;
architecture RTL of FeedbackMemory is
type SIGNED_LI_ARRAY_TYPE is array (0 to MAXCH-1) of SIGNED_LI_VECTOR_TYPE;
signal data_array : SIGNED_LI_ARRAY_TYPE;
begin
process(clk, reset)
variable init_ch : integer range 0 to MAXCH;
begin
if reset = '1' then
init_ch := 0;
elsif clk'event and clk='1' then
if init_ch /= MAXCH then
data_array(init_ch) <= (others=>'0');
init_ch := init_ch + 1;
elsif wr='1' then
data_array(waddr) <= CONV_SIGNED_LI_VECTOR(wdata);
end if;
rdata <= CONV_SIGNED_LI(data_array(raddr));
end if;
end process;
end RTL; |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:51:15 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_auto_pc_0_sim_netlist.vhdl
-- Design : ip_design_auto_pc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[0]_0\ : out STD_LOGIC;
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\m_axi_awaddr[11]\ : out STD_LOGIC;
\m_axi_awaddr[3]\ : out STD_LOGIC;
\m_axi_awaddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd is
signal \axaddr_incr[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \axaddr_incr_reg[11]_i_4_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_incr_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal next_pending_r_i_5_n_0 : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_axi_awaddr[11]_INST_0_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_axi_awaddr[3]_INST_0_i_1\ : label is "soft_lutpair118";
begin
\axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\;
\axaddr_incr_reg[11]_0\(9 downto 0) <= \^axaddr_incr_reg[11]_0\(9 downto 0);
\axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\;
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_7\,
O => p_1_in(0)
);
\axaddr_incr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(10),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_5\,
O => p_1_in(10)
);
\axaddr_incr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \state_reg[1]_rep\,
O => \axaddr_incr[11]_i_1_n_0\
);
\axaddr_incr[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(11),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_4\,
O => p_1_in(11)
);
\axaddr_incr[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_6\,
O => p_1_in(1)
);
\axaddr_incr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_5\,
O => p_1_in(2)
);
\axaddr_incr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3_n_4\,
O => p_1_in(3)
);
\axaddr_incr[3]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"0009"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \state_reg[1]_rep\,
I2 => \m_payload_i_reg[46]\(4),
I3 => \m_payload_i_reg[46]\(5),
O => S(0)
);
\axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_incr_reg_n_0_[3]\,
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_11_n_0\
);
\axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_incr_reg_n_0_[2]\,
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
O => \axaddr_incr[3]_i_12_n_0\
);
\axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(1),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_13_n_0\
);
\axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\(0),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \state_reg[1]_rep\,
I2 => \m_payload_i_reg[46]\(4),
I3 => \m_payload_i_reg[46]\(5),
O => S(3)
);
\axaddr_incr[3]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A9A"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \state_reg[1]_rep\,
I2 => \m_payload_i_reg[46]\(5),
I3 => \m_payload_i_reg[46]\(4),
O => S(2)
);
\axaddr_incr[3]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"009A"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \state_reg[1]_rep\,
I2 => \m_payload_i_reg[46]\(4),
I3 => \m_payload_i_reg[46]\(5),
O => S(1)
);
\axaddr_incr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(4),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_7\,
O => p_1_in(4)
);
\axaddr_incr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(5),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_6\,
O => p_1_in(5)
);
\axaddr_incr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(6),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_5\,
O => p_1_in(6)
);
\axaddr_incr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(7),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3_n_4\,
O => p_1_in(7)
);
\axaddr_incr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(8),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_7\,
O => p_1_in(8)
);
\axaddr_incr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axaddr_incr(9),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4_n_6\,
O => p_1_in(9)
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(0),
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(10),
Q => \^axaddr_incr_reg[11]_0\(8),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(11),
Q => \^axaddr_incr_reg[11]_0\(9),
R => '0'
);
\axaddr_incr_reg[11]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_3_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_4_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_4_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[11]_i_4_n_4\,
O(2) => \axaddr_incr_reg[11]_i_4_n_5\,
O(1) => \axaddr_incr_reg[11]_i_4_n_6\,
O(0) => \axaddr_incr_reg[11]_i_4_n_7\,
S(3 downto 0) => \^axaddr_incr_reg[11]_0\(9 downto 6)
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(1),
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(2),
Q => \axaddr_incr_reg_n_0_[2]\,
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(3),
Q => \axaddr_incr_reg_n_0_[3]\,
R => '0'
);
\axaddr_incr_reg[3]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_3_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_3_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_3_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_3_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr_reg_n_0_[3]\,
DI(2) => \axaddr_incr_reg_n_0_[2]\,
DI(1 downto 0) => \^axaddr_incr_reg[11]_0\(1 downto 0),
O(3) => \axaddr_incr_reg[3]_i_3_n_4\,
O(2) => \axaddr_incr_reg[3]_i_3_n_5\,
O(1) => \axaddr_incr_reg[3]_i_3_n_6\,
O(0) => \axaddr_incr_reg[3]_i_3_n_7\,
S(3) => \axaddr_incr[3]_i_11_n_0\,
S(2) => \axaddr_incr[3]_i_12_n_0\,
S(1) => \axaddr_incr[3]_i_13_n_0\,
S(0) => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(4),
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(5),
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(6),
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(7),
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_3_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_3_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_3_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_3_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[7]_i_3_n_4\,
O(2) => \axaddr_incr_reg[7]_i_3_n_5\,
O(1) => \axaddr_incr_reg[7]_i_3_n_6\,
O(0) => \axaddr_incr_reg[7]_i_3_n_7\,
S(3 downto 0) => \^axaddr_incr_reg[11]_0\(5 downto 2)
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(8),
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[11]_i_1_n_0\,
D => p_1_in(9),
Q => \^axaddr_incr_reg[11]_0\(7),
R => '0'
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44444F4444444444"
)
port map (
I0 => \axlen_cnt_reg_n_0_[0]\,
I1 => \^axlen_cnt_reg[0]_0\,
I2 => Q(1),
I3 => si_rs_awvalid,
I4 => Q(0),
I5 => \m_payload_i_reg[46]\(7),
O => \axlen_cnt[0]_i_1__1_n_0\
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(8),
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[1]_i_1_n_0\
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(9),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
I5 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[2]_i_1_n_0\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^axlen_cnt_reg[0]_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_2__0_n_0\
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_1_n_0\
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[4]\,
I5 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_1_n_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt[7]_i_3_n_0\,
O => \axlen_cnt[6]_i_1_n_0\
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A9AA"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt[7]_i_3_n_0\,
O => \axlen_cnt[7]_i_2_n_0\
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
O => \axlen_cnt[7]_i_3_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[0]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[1]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[2]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[4]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => \state_reg[0]_rep\
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[5]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => \state_reg[0]_rep\
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[6]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => \state_reg[0]_rep\
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[7]_i_2_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => \state_reg[0]_rep\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \m_payload_i_reg[46]\(6),
O => \m_axi_awaddr[11]\
);
\m_axi_awaddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[2]\,
I2 => \m_payload_i_reg[46]\(6),
I3 => \m_payload_i_reg[46]\(2),
O => \m_axi_awaddr[2]\
);
\m_axi_awaddr[3]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \axaddr_incr_reg_n_0_[3]\,
I2 => \m_payload_i_reg[46]\(6),
I3 => \m_payload_i_reg[46]\(3),
O => \m_axi_awaddr[3]\
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55545555"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[6]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
I4 => next_pending_r_i_5_n_0,
O => \^axlen_cnt_reg[0]_0\
);
next_pending_r_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_i_5_n_0
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_0,
Q => \^axaddr_incr_reg[0]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 is
port (
incr_next_pending : out STD_LOGIC;
\axaddr_incr_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[0]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\m_axi_araddr[11]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC;
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_14_b2s_incr_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_incr[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_4__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_3__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_2__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \next_pending_r_i_2__1_n_0\ : STD_LOGIC;
signal next_pending_r_i_4_n_0 : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_3__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1__2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \next_pending_r_i_2__1\ : label is "soft_lutpair6";
begin
Q(11 downto 0) <= \^q\(11 downto 0);
\axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\;
\axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\;
incr_next_pending <= \^incr_next_pending\;
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_7\,
O => \axaddr_incr[0]_i_1__0_n_0\
);
\axaddr_incr[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_5\,
O => \axaddr_incr[10]_i_1__0_n_0\
);
\axaddr_incr[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_4\,
O => \axaddr_incr[11]_i_2__0_n_0\
);
\axaddr_incr[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_6\,
O => \axaddr_incr[1]_i_1__0_n_0\
);
\axaddr_incr[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_5\,
O => \axaddr_incr[2]_i_1__0_n_0\
);
\axaddr_incr[3]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"0202010202020202"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(0)
);
\axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(3),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_11_n_0\
);
\axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^q\(2),
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
O => \axaddr_incr[3]_i_12_n_0\
);
\axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^q\(1),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_13_n_0\
);
\axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \^q\(0),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
O => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[3]_i_3__0_n_4\,
O => \axaddr_incr[3]_i_1__0_n_0\
);
\axaddr_incr[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(3)
);
\axaddr_incr[3]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A2A262A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \m_payload_i_reg[46]\(5),
I2 => \m_payload_i_reg[46]\(4),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(2)
);
\axaddr_incr[3]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0A060A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \m_payload_i_reg[46]\(4),
I2 => \m_payload_i_reg[46]\(5),
I3 => m_axi_arready,
I4 => \state_reg[1]_0\(1),
I5 => \state_reg[1]_0\(0),
O => S(1)
);
\axaddr_incr[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_7\,
O => \axaddr_incr[4]_i_1__0_n_0\
);
\axaddr_incr[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_6\,
O => \axaddr_incr[5]_i_1__0_n_0\
);
\axaddr_incr[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(2),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_5\,
O => \axaddr_incr[6]_i_1__0_n_0\
);
\axaddr_incr[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[7]\(3),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[7]_i_3__0_n_4\,
O => \axaddr_incr[7]_i_1__0_n_0\
);
\axaddr_incr[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(0),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_7\,
O => \axaddr_incr[8]_i_1__0_n_0\
);
\axaddr_incr[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => O(1),
I1 => \^axaddr_incr_reg[0]_0\,
I2 => \axaddr_incr_reg[11]_i_4__0_n_6\,
O => \axaddr_incr[9]_i_1__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[11]_i_2__0_n_0\,
Q => \^q\(11),
R => '0'
);
\axaddr_incr_reg[11]_i_4__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_3__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_4__0_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_4__0_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_4__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[11]_i_4__0_n_4\,
O(2) => \axaddr_incr_reg[11]_i_4__0_n_5\,
O(1) => \axaddr_incr_reg[11]_i_4__0_n_6\,
O(0) => \axaddr_incr_reg[11]_i_4__0_n_7\,
S(3 downto 0) => \^q\(11 downto 8)
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\axaddr_incr_reg[3]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_3__0_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_3__0_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_3__0_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(3 downto 0),
O(3) => \axaddr_incr_reg[3]_i_3__0_n_4\,
O(2) => \axaddr_incr_reg[3]_i_3__0_n_5\,
O(1) => \axaddr_incr_reg[3]_i_3__0_n_6\,
O(0) => \axaddr_incr_reg[3]_i_3__0_n_7\,
S(3) => \axaddr_incr[3]_i_11_n_0\,
S(2) => \axaddr_incr[3]_i_12_n_0\,
S(1) => \axaddr_incr[3]_i_13_n_0\,
S(0) => \axaddr_incr[3]_i_14_n_0\
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\axaddr_incr_reg[7]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_3__0_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_3__0_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_3__0_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_3__0_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[7]_i_3__0_n_4\,
O(2) => \axaddr_incr_reg[7]_i_3__0_n_5\,
O(1) => \axaddr_incr_reg[7]_i_3__0_n_6\,
O(0) => \axaddr_incr_reg[7]_i_3__0_n_7\,
S(3 downto 0) => \^q\(7 downto 4)
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_1(0),
D => \axaddr_incr[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20FF2020"
)
port map (
I0 => si_rs_arvalid,
I1 => \state_reg[0]_rep\,
I2 => \m_payload_i_reg[46]\(7),
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[0]_i_1_n_0\
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(8),
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[1]_i_1__1_n_0\
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(9),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
I5 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[0]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \^axlen_cnt_reg[0]_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_2__1_n_0\
);
\axlen_cnt[3]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55545555"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[6]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
I4 => next_pending_r_i_4_n_0,
O => \^axlen_cnt_reg[0]_0\
);
\axlen_cnt[4]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[4]_i_1__2_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[4]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"A6"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \axlen_cnt_reg_n_0_[5]\,
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A9AA"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[0]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_2__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => \state_reg[1]\
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => \state_reg[1]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^axaddr_incr_reg[0]_0\,
I1 => \m_payload_i_reg[46]\(6),
O => \m_axi_araddr[11]\
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF505C"
)
port map (
I0 => \next_pending_r_i_2__1_n_0\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep\,
I3 => E(0),
I4 => \m_payload_i_reg[44]\,
O => \^incr_next_pending\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => next_pending_r_i_4_n_0,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt_reg_n_0_[6]\,
O => \next_pending_r_i_2__1_n_0\
);
next_pending_r_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
O => next_pending_r_i_4_n_0
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^incr_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_0,
Q => \^axaddr_incr_reg[0]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[7]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axaddr_incr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_valid_i0 : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[6]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC;
incr_next_pending : in STD_LOGIC;
\m_payload_i_reg[44]_0\ : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[0]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[11]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \state[1]_i_1__0\ : label is "soft_lutpair1";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[0]\(0) <= \^axaddr_offset_r_reg[0]\(0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
\wrap_cnt_r_reg[0]\ <= \^wrap_cnt_r_reg[0]\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[3]\(1 downto 0) <= \^wrap_second_len_r_reg[3]\(1 downto 0);
\axaddr_incr[11]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => sel_first,
I1 => \^m_payload_i_reg[0]_0\,
I2 => \^m_payload_i_reg[0]\,
I3 => m_axi_arready,
O => \axaddr_incr_reg[0]\(0)
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]\(0),
I1 => \m_payload_i_reg[44]\(1),
I2 => \^q\(0),
I3 => si_rs_arvalid,
I4 => \^q\(1),
I5 => \m_payload_i_reg[3]\,
O => \^axaddr_offset_r_reg[0]\(0)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0E02"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(0),
I2 => \^q\(1),
I3 => m_axi_arready,
O => \axlen_cnt_reg[4]\(0)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002320"
)
port map (
I0 => m_axi_arready,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => si_rs_arvalid,
I4 => \axlen_cnt_reg[6]\,
O => \axlen_cnt_reg[7]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => si_rs_arvalid,
O => \m_payload_i_reg[0]_1\(0)
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF70FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => si_rs_arvalid,
I3 => s_axi_arvalid,
I4 => s_ready_i_reg,
O => m_valid_i0
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFABEEAA"
)
port map (
I0 => \m_payload_i_reg[44]_0\,
I1 => \^r_push_r_reg\,
I2 => \^e\(0),
I3 => \axlen_cnt_reg[3]\,
I4 => next_pending_r_reg,
O => \^wrap_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => m_axi_arready,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[44]\(0),
I2 => \^sel_first_i\,
I3 => incr_next_pending,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[44]\(0),
I2 => \^sel_first_i\,
I3 => incr_next_pending,
O => s_axburst_eq1_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_1,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^m_payload_i_reg[0]\,
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => \^sel_first_i\
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000770000FFFFF0"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => m_axi_arready,
I2 => si_rs_arvalid,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \cnt_read_reg[1]_rep__0\,
O => next_state(0)
);
\state[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FC00040"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
I4 => \cnt_read_reg[1]_rep__0\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8A5575AA8A5545"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \^wrap_cnt_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[0]\(0),
O => D(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6AA56AAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[2]\(1),
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \^e\(0),
I3 => \^wrap_cnt_r_reg[0]\,
I4 => \^axaddr_offset_r_reg[0]\(0),
I5 => \wrap_second_len_r_reg[2]\(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \wrap_second_len_r_reg[2]\(0),
I2 => \wrap_cnt_r[3]_i_2__0_n_0\,
I3 => \wrap_second_len_r_reg[2]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D1D1D1D1D1D1DFD1"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^e\(0),
I2 => \^axaddr_offset_r_reg[0]\(0),
I3 => \m_payload_i_reg[35]\,
I4 => \m_payload_i_reg[47]\(1),
I5 => \m_payload_i_reg[47]\(0),
O => \wrap_cnt_r[3]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8AAA8AAA8AAABA"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \^wrap_cnt_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[0]\(0),
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000404"
)
port map (
I0 => \^axaddr_offset_r_reg[0]\(0),
I1 => \m_payload_i_reg[35]\,
I2 => \m_payload_i_reg[35]_0\,
I3 => \^e\(0),
I4 => \axaddr_offset_r_reg[3]\(1),
I5 => \m_payload_i_reg[47]\(0),
O => \^wrap_cnt_r_reg[0]\
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB00FFFFFB00FB00"
)
port map (
I0 => \^axaddr_offset_r_reg[0]\(0),
I1 => \m_payload_i_reg[35]\,
I2 => \m_payload_i_reg[47]\(0),
I3 => \m_payload_i_reg[35]_0\,
I4 => \^e\(0),
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
bvalid_i_reg : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
bresp_push : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo is
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \bresp_cnt[7]_i_5_n_0\ : STD_LOGIC;
signal \bresp_cnt[7]_i_6_n_0\ : STD_LOGIC;
signal \^bresp_push\ : STD_LOGIC;
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_5\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair128";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_3\ : label is "soft_lutpair127";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
bresp_push <= \^bresp_push\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__0_0\ <= \^cnt_read_reg[1]_rep__0_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAABAAAA"
)
port map (
I0 => areset_d1,
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt[7]_i_4_n_0\,
I3 => \bresp_cnt[7]_i_5_n_0\,
I4 => \bresp_cnt[7]_i_6_n_0\,
O => SR(0)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFF22F222F2"
)
port map (
I0 => \memory_reg[3][1]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(1),
I2 => \bresp_cnt_reg[7]\(3),
I3 => \memory_reg[3][3]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAEFFAE"
)
port map (
I0 => \bresp_cnt_reg[7]\(4),
I1 => \bresp_cnt_reg[7]\(1),
I2 => \memory_reg[3][1]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(0),
I4 => \memory_reg[3][0]_srl4_n_0\,
O => \bresp_cnt[7]_i_4_n_0\
);
\bresp_cnt[7]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAFFEAEA"
)
port map (
I0 => \bresp_cnt_reg[7]\(6),
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => \^cnt_read_reg[1]_rep__0_0\,
I3 => \bresp_cnt_reg[7]\(3),
I4 => \memory_reg[3][3]_srl4_n_0\,
O => \bresp_cnt[7]_i_5_n_0\
);
\bresp_cnt[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004004"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => mhandshake_r,
I2 => \bresp_cnt_reg[7]\(2),
I3 => \memory_reg[3][2]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(7),
O => \bresp_cnt[7]_i_6_n_0\
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0444"
)
port map (
I0 => areset_d1,
I1 => bvalid_i_i_2_n_0,
I2 => si_rs_bvalid,
I3 => si_rs_bready,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => \^cnt_read_reg[1]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(0),
I4 => Q(1),
I5 => si_rs_bvalid,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^bresp_push\,
I1 => Q(0),
I2 => shandshake_r,
O => D(0)
);
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__0_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__0_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000004100"
)
port map (
I0 => \bresp_cnt_reg[7]\(7),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \bresp_cnt_reg[7]\(2),
I3 => mhandshake_r,
I4 => \bresp_cnt_reg[7]\(5),
I5 => \memory_reg[3][0]_srl4_i_2__0_n_0\,
O => \^bresp_push\
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFEFFFE"
)
port map (
I0 => \bresp_cnt[7]_i_3_n_0\,
I1 => \bresp_cnt[7]_i_4_n_0\,
I2 => \bresp_cnt_reg[7]\(6),
I3 => \memory_reg[3][0]_srl4_i_3_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_2__0_n_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => \^cnt_read_reg[1]_rep__0_0\,
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \out\(1)
);
\state[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^cnt_read_reg[1]_rep__0_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
O => \state_reg[0]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_14_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair129";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair129";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AA6"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => sel,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(1),
I3 => \^q\(0),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[3]_rep__0_0\ : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_14_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair18";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair15";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair15";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \^wr_en0\,
I2 => s_ready_i_reg,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[0]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AA6A6AAA6AAA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[3]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \^cnt_read_reg[3]_rep__2_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[1]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
I3 => \^cnt_read_reg[3]_rep__2_0\,
I4 => \^cnt_read_reg[4]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\ is
port (
m_valid_i_reg : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
si_rs_rready : in STD_LOGIC;
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[2]_rep__2\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_14_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal m_valid_i_i_3_n_0 : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair19";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__1_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \cnt_read_reg[0]_rep__1_n_0\,
I1 => r_push_r,
I2 => s_ready_i_reg,
I3 => \cnt_read_reg[1]_rep__0_n_0\,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE7F0180"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFFFFFB20000004"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[2]_rep__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAA9AAA9AAA9AA6"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read_reg[2]_rep__0_n_0\,
I3 => \cnt_read_reg[3]_rep__0_n_0\,
I4 => \cnt_read[4]_i_3__0_n_0\,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"5DFFFFFF"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
I4 => \cnt_read_reg[0]_rep__1_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
I3 => r_push_r,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF08080808080808"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[4]_rep__0_n_0\,
I2 => m_valid_i_i_3_n_0,
I3 => \cnt_read_reg[3]_rep__2\,
I4 => \cnt_read_reg[4]_rep__2_0\,
I5 => \cnt_read_reg[2]_rep__2\,
O => \^m_valid_i_reg\
);
m_valid_i_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \cnt_read_reg[0]_rep__1_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
O => m_valid_i_i_3_n_0
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEAAAAAAFEAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[2]_rep__0_n_0\,
I3 => \cnt_read_reg[4]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axlen_cnt_reg[0]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axlen_cnt_reg[1]\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_0 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axlen_cnt_reg[0]\ : STD_LOGIC;
signal \^b_push\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state_reg[0]_rep_n_0\ : STD_LOGIC;
signal \state_reg[1]_rep_n_0\ : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^wrap_next_pending\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__0\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair115";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair114";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axlen_cnt_reg[0]\ <= \^axlen_cnt_reg[0]\;
b_push <= \^b_push\;
incr_next_pending <= \^incr_next_pending\;
sel_first_i <= \^sel_first_i\;
\wrap_boundary_axaddr_r_reg[0]\(0) <= \^wrap_boundary_axaddr_r_reg[0]\(0);
wrap_next_pending <= \^wrap_next_pending\;
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"04FF"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \^axlen_cnt_reg[0]\,
O => E(0)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"000004FF"
)
port map (
I0 => \state_reg[0]_rep_n_0\,
I1 => si_rs_awvalid,
I2 => \state_reg[1]_rep_n_0\,
I3 => \^axlen_cnt_reg[0]\,
I4 => \axlen_cnt_reg[6]\,
O => \axlen_cnt_reg[7]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \state_reg[0]_rep_n_0\,
I1 => \state_reg[1]_rep_n_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^b_push\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCF000045000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[0]_rep__0\,
I2 => \cnt_read_reg[1]_rep__0_0\,
I3 => m_axi_awready,
I4 => \state_reg[0]_rep_n_0\,
I5 => \state_reg[1]_rep_n_0\,
O => \^b_push\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^wrap_boundary_axaddr_r_reg[0]\(0),
I2 => next_pending_r_reg,
I3 => \^axlen_cnt_reg[0]\,
I4 => \axlen_cnt_reg[6]\,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B888B8BB"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^wrap_boundary_axaddr_r_reg[0]\(0),
I2 => next_pending_r_reg_0,
I3 => \^axlen_cnt_reg[0]\,
I4 => \axlen_cnt_reg[1]\,
O => \^wrap_next_pending\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"5555DD551515DD15"
)
port map (
I0 => \state_reg[1]_rep_n_0\,
I1 => \state_reg[0]_rep_n_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[1]_rep__0_0\,
I4 => \cnt_read_reg[0]_rep__0\,
I5 => s_axburst_eq1_reg_0,
O => \^axlen_cnt_reg[0]\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[39]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[39]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF88888F88"
)
port map (
I0 => \^axlen_cnt_reg[0]\,
I1 => sel_first,
I2 => \state_reg[1]_rep_n_0\,
I3 => si_rs_awvalid,
I4 => \state_reg[0]_rep_n_0\,
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF88888F88"
)
port map (
I0 => \^axlen_cnt_reg[0]\,
I1 => sel_first_0,
I2 => \state_reg[1]_rep_n_0\,
I3 => si_rs_awvalid,
I4 => \state_reg[0]_rep_n_0\,
I5 => areset_d1,
O => sel_first_reg_0
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF88888F88"
)
port map (
I0 => \^axlen_cnt_reg[0]\,
I1 => sel_first_reg_1,
I2 => \state_reg[1]_rep_n_0\,
I3 => si_rs_awvalid,
I4 => \state_reg[0]_rep_n_0\,
I5 => areset_d1,
O => \^sel_first_i\
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AEFE0E0EFEFE5E5E"
)
port map (
I0 => \state_reg[1]_rep_n_0\,
I1 => si_rs_awvalid,
I2 => \state_reg[0]_rep_n_0\,
I3 => s_axburst_eq1_reg_0,
I4 => \cnt_read_reg[1]_rep__0\,
I5 => m_axi_awready,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2E220E0000000000"
)
port map (
I0 => m_axi_awready,
I1 => \state_reg[1]_rep_n_0\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => \cnt_read_reg[1]_rep__0_0\,
I4 => s_axburst_eq1_reg_0,
I5 => \state_reg[0]_rep_n_0\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \state_reg[0]_rep_n_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \state_reg[1]_rep_n_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \state_reg[1]_rep_n_0\,
I1 => si_rs_awvalid,
I2 => \state_reg[0]_rep_n_0\,
O => \^wrap_boundary_axaddr_r_reg[0]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \next_pending_r_i_2__0\ : label is "soft_lutpair126";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(0),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(10),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(10),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(11),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(11),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF6"
)
port map (
I0 => wrap_cnt_r(3),
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axaddr_wrap[11]_i_4_n_0\,
I3 => \axlen_cnt_reg_n_0_[4]\,
O => \axaddr_wrap[11]_i_3_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => wrap_cnt_r(1),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => wrap_cnt_r(2),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(1),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(2),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(3),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[46]\(13),
I2 => \m_payload_i_reg[46]\(12),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[46]\(12),
I2 => \m_payload_i_reg[46]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[46]\(13),
I2 => \m_payload_i_reg[46]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[46]\(13),
I2 => \m_payload_i_reg[46]\(12),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(4),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(4),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(5),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(5),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(6),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(6),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(7),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(7),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(8),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(8),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[46]\(9),
I1 => \state_reg[1]_rep\,
I2 => axaddr_wrap0(9),
I3 => \axaddr_wrap[11]_i_3_n_0\,
I4 => wrap_boundary_axaddr_r(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3 downto 0) => axaddr_wrap(11 downto 8)
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3 downto 0) => axaddr_wrap(7 downto 4)
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44444F4444444444"
)
port map (
I0 => \axlen_cnt_reg_n_0_[0]\,
I1 => \axlen_cnt[3]_i_2_n_0\,
I2 => Q(1),
I3 => si_rs_awvalid,
I4 => Q(0),
I5 => \m_payload_i_reg[46]\(15),
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(16),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt[3]_i_2_n_0\,
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[46]\(17),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt[3]_i_2_n_0\,
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt[3]_i_2_n_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[3]_i_2_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444440"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(0),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(10),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(8),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(11),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(9),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(1),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(1),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(1),
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(2),
I3 => \m_payload_i_reg[46]\(14),
I4 => sel_first_reg_4,
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(3),
I3 => \m_payload_i_reg[46]\(14),
I4 => sel_first_reg_3,
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(4),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(2),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(5),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(3),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(6),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(4),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(7),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(5),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(8),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(6),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[46]\(14),
I3 => \m_payload_i_reg[46]\(9),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(7),
O => m_axi_awaddr(9)
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[46]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[46]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[46]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[46]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[46]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axlen_cnt_reg[0]_0\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 17 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_14_b2s_wrap_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__1_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\;
sel_first_reg_0 <= \^sel_first_reg_0\;
\wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0);
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I3 => \state_reg[1]_rep\,
I4 => Q(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_5\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I3 => \state_reg[1]_rep\,
I4 => Q(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_4\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I3 => \state_reg[1]_rep\,
I4 => Q(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axaddr_wrap[11]_i_4__0_n_0\,
I3 => \axlen_cnt_reg_n_0_[4]\,
O => \axaddr_wrap[11]_i_3__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \wrap_cnt_r_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \wrap_cnt_r_reg_n_0_[1]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I3 => \state_reg[1]_rep\,
I4 => Q(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I3 => \state_reg[1]_rep\,
I4 => Q(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I3 => \state_reg[1]_rep\,
I4 => Q(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => Q(13),
I2 => Q(12),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => Q(12),
I2 => Q(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => Q(13),
I2 => Q(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => Q(13),
I2 => Q(12),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I3 => \state_reg[1]_rep\,
I4 => Q(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I3 => \state_reg[1]_rep\,
I4 => Q(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I3 => \state_reg[1]_rep\,
I4 => Q(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I3 => \state_reg[1]_rep\,
I4 => Q(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_7\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I3 => \state_reg[1]_rep\,
I4 => Q(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \axaddr_wrap_reg[11]_i_2__0_n_6\,
I1 => \axaddr_wrap[11]_i_3__0_n_0\,
I2 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I3 => \state_reg[1]_rep\,
I4 => Q(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_2__0_n_7\,
S(3) => \axaddr_wrap_reg_n_0_[11]\,
S(2) => \axaddr_wrap_reg_n_0_[10]\,
S(1) => \axaddr_wrap_reg_n_0_[9]\,
S(0) => \axaddr_wrap_reg_n_0_[8]\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap_reg_n_0_[7]\,
S(2) => \axaddr_wrap_reg_n_0_[6]\,
S(1) => \axaddr_wrap_reg_n_0_[5]\,
S(0) => \axaddr_wrap_reg_n_0_[4]\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"20FF2020"
)
port map (
I0 => si_rs_arvalid,
I1 => \state_reg[0]_rep\,
I2 => Q(15),
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => Q(16),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => Q(17),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \^axlen_cnt_reg[0]_0\,
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \^axlen_cnt_reg[0]_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt[3]_i_2__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
O => \^axlen_cnt_reg[0]_0\
);
\axlen_cnt[4]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444440"
)
port map (
I0 => E(0),
I1 => \axlen_cnt_reg_n_0_[4]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_1__1_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => Q(14),
I3 => Q(0),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => Q(14),
I3 => Q(10),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => Q(14),
I3 => Q(11),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => Q(14),
I3 => Q(1),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[2]\,
I2 => Q(14),
I3 => Q(2),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(2),
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => Q(14),
I3 => Q(3),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => Q(14),
I3 => Q(4),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[5]\,
I2 => Q(14),
I3 => Q(5),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(5),
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => Q(14),
I3 => Q(6),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => Q(14),
I3 => Q(7),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => Q(14),
I3 => Q(8),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EF40EF4FEF40E040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => Q(14),
I3 => Q(9),
I4 => sel_first_reg_2,
I5 => \axaddr_incr_reg[11]\(9),
O => m_axi_araddr(9)
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"313D020E"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(0),
I1 => E(0),
I2 => \axaddr_offset_r_reg[3]_1\,
I3 => \m_payload_i_reg[35]\,
I4 => \^wrap_second_len_r_reg[3]_0\(1),
O => \wrap_cnt_r[1]_i_1_n_0\
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_cnt_r[1]_i_1_n_0\,
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \^wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \^wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \^wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \^wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 53 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
m_valid_i0 : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_offset_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 53 downto 0 );
signal \axaddr_incr[3]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[52]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 to 3 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_3\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair21";
begin
Q(53 downto 0) <= \^q\(53 downto 0);
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0);
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[3]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[3]_i_4__0_n_0\
);
\axaddr_incr[3]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[3]_i_5__0_n_0\
);
\axaddr_incr[3]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[3]_i_6__0_n_0\
);
\axaddr_incr_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => O(3 downto 0),
S(3 downto 0) => \^q\(11 downto 8)
);
\axaddr_incr_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[3]_i_4__0_n_0\,
DI(1) => \axaddr_incr[3]_i_5__0_n_0\,
DI(0) => \axaddr_incr[3]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3 downto 0) => \^q\(7 downto 4)
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1FDF00001FDFFFFF"
)
port map (
I0 => \axaddr_offset_r[1]_i_3_n_0\,
I1 => \^q\(35),
I2 => \^q\(40),
I3 => \axaddr_offset_r[2]_i_3__0_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_0\(0),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_3_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_0\(1),
O => \^axaddr_offset_r_reg[3]\(1)
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => si_rs_arlen(3),
I1 => \axaddr_offset_r[3]_i_2__0_n_0\,
I2 => \state_reg[1]_rep_0\,
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[0]_rep\,
I5 => \axaddr_offset_r_reg[3]_0\(2),
O => \^axaddr_offset_r_reg[3]\(2)
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r[3]_i_2__0_n_0\
);
\axlen_cnt[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => si_rs_arlen(3),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[52]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => \m_payload_i[52]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => si_rs_arlen(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[52]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[1]_rep_1\(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \^q\(39),
I2 => si_rs_arlen(3),
I3 => \^q\(40),
I4 => \^q\(41),
O => next_pending_r_reg
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[1]_rep_0\,
I3 => \state_reg[0]_rep\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888082AAAAA082A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(40),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => si_rs_arlen(3),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002AA02A0A2AAA2A"
)
port map (
I0 => \^q\(4),
I1 => si_rs_arlen(3),
I2 => \^q\(35),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => si_rs_arlen(3),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(35),
I3 => si_rs_arlen(3),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0EF0FFFF0EF00000"
)
port map (
I0 => \^axaddr_offset_r_reg[3]\(1),
I1 => \^axaddr_offset_r_reg[3]\(2),
I2 => axaddr_offset_0(0),
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[2]_0\(0),
O => \wrap_second_len_r_reg[2]\(0)
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA4AFFFFAA4A0000"
)
port map (
I0 => \^axaddr_offset_r_reg[3]\(1),
I1 => \^axaddr_offset_r_reg[3]\(2),
I2 => \^axaddr_offset_r_reg[1]\,
I3 => axaddr_offset_0(0),
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[2]_0\(1),
O => \wrap_second_len_r_reg[2]\(1)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r_reg[3]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC;
axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 54 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice_0 : entity is "axi_register_slice_v2_1_14_axic_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice_0 is
signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 61 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_5_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[0]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_4\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_3\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_2\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_5\ : label is "soft_lutpair53";
begin
Q(54 downto 0) <= \^q\(54 downto 0);
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[3]\ <= \^axaddr_offset_r_reg[3]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
wrap_second_len(2 downto 0) <= \^wrap_second_len\(2 downto 0);
\wrap_second_len_r_reg[1]\ <= \^wrap_second_len_r_reg[1]\;
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[3]_i_4_n_0\
);
\axaddr_incr[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[3]_i_5_n_0\
);
\axaddr_incr[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(35),
O => \axaddr_incr[3]_i_6_n_0\
);
\axaddr_incr_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[11]_i_3_n_1\,
CO(1) => \axaddr_incr_reg[11]_i_3_n_2\,
CO(0) => \axaddr_incr_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_incr(11 downto 8),
S(3 downto 0) => \^q\(11 downto 8)
);
\axaddr_incr_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[3]_i_2_n_0\,
CO(2) => \axaddr_incr_reg[3]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[3]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[3]_i_4_n_0\,
DI(1) => \axaddr_incr[3]_i_5_n_0\,
DI(0) => \axaddr_incr[3]_i_6_n_0\,
O(3 downto 0) => axaddr_incr(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[3]_i_2_n_0\,
CO(3) => \axaddr_incr_reg[7]_i_2_n_0\,
CO(2) => \axaddr_incr_reg[7]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[7]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_incr(7 downto 4),
S(3 downto 0) => \^q\(7 downto 4)
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
O => axaddr_offset(0)
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000700FFFFF7FF"
)
port map (
I0 => \^q\(39),
I1 => \axaddr_offset_r[0]_i_3_n_0\,
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]_0\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_3_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \^q\(40),
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]_0\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(35),
I3 => \^q\(3),
I4 => \^q\(36),
I5 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
O => axaddr_offset(1)
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"03FFF3FF55555555"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(2),
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \axaddr_offset_r[2]_i_4_n_0\,
I5 => \state_reg[1]_rep\,
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[2]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_4_n_0\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FF00000800"
)
port map (
I0 => \^q\(42),
I1 => \axaddr_offset_r[3]_i_2_n_0\,
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \axaddr_offset_r_reg[3]_0\(3),
O => \^axaddr_offset_r_reg[3]\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r[3]_i_2_n_0\
);
\axlen_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[1]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \^axlen_cnt_reg[3]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => skid_buffer(52)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(52),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(40),
I2 => \^q\(42),
I3 => \^q\(39),
O => next_pending_r_reg
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_awvalid,
I1 => \^s_axi_awready\,
I2 => b_push,
I3 => \^m_valid_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A002A2AAAA02A2"
)
port map (
I0 => \^q\(2),
I1 => \^q\(41),
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A0A2AA02AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(42),
I2 => \^q\(35),
I3 => \^q\(36),
I4 => \^q\(41),
I5 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(35),
I3 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDD8DDAAAAA8AA"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r[0]_i_3_n_0\,
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \wrap_second_len_r_reg[3]\(0),
O => D(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\,
I1 => \wrap_cnt_r[3]_i_2_n_0\,
O => D(1)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len\(1),
I1 => \wrap_cnt_r[3]_i_2_n_0\,
I2 => \^wrap_second_len_r_reg[1]\,
O => D(2)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len\(2),
I1 => \^wrap_second_len_r_reg[1]\,
I2 => \wrap_cnt_r[3]_i_2_n_0\,
I3 => \^wrap_second_len\(1),
O => D(3)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABAAA"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \axaddr_offset_r[0]_i_2_n_0\,
I3 => \axaddr_offset_r[2]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[3]\,
O => \wrap_cnt_r[3]_i_2_n_0\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800FFFFF8FF"
)
port map (
I0 => \^q\(39),
I1 => \axaddr_offset_r[0]_i_3_n_0\,
I2 => \state_reg[1]\(1),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(0),
I5 => \wrap_second_len_r_reg[3]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000CCCCCACC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF2FFFFFF"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(3),
I1 => \state_reg[1]_rep\,
I2 => \wrap_second_len_r[3]_i_2_n_0\,
I3 => \axaddr_offset_r[2]_i_2_n_0\,
I4 => \axaddr_offset_r[0]_i_2_n_0\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFE200E2"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(2),
I3 => \^q\(35),
I4 => \wrap_second_len_r[0]_i_4_n_0\,
I5 => \wrap_second_len_r[0]_i_5_n_0\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_5_n_0\
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2EE22E222EE22EE2"
)
port map (
I0 => \wrap_second_len_r_reg[3]\(1),
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r[0]_i_2_n_0\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[3]\,
I5 => \axaddr_offset_r[2]_i_2_n_0\,
O => \^wrap_second_len_r_reg[1]\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08F3FFFF08F30000"
)
port map (
I0 => \^axaddr_offset_r_reg[3]\,
I1 => \axaddr_offset_r[0]_i_2_n_0\,
I2 => \^axaddr_offset_r_reg[1]\,
I3 => \axaddr_offset_r[2]_i_2_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]\(2),
O => \^wrap_second_len\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00FFFFBF00BF00"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \axaddr_offset_r[0]_i_2_n_0\,
I2 => \axaddr_offset_r[2]_i_2_n_0\,
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]\(3),
O => \^wrap_second_len\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_4_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
shandshake : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_14_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair82";
attribute SOFT_HLUTNM of shandshake_r_i_1 : label is "soft_lutpair82";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => si_rs_bvalid,
O => shandshake
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[0]_rep__1\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_14_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_valid_i_i_1__2\ : label is "soft_lutpair90";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[3]_rep__0\,
O => \cnt_read_reg[0]_rep__1\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \^skid_buffer_reg[0]_0\,
I3 => \cnt_read_reg[3]_rep__0\,
O => \m_valid_i_i_1__2_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__2_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[3]_rep__0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
shandshake : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_b_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_b_channel is
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_5 : STD_LOGIC;
signal \bresp_cnt[7]_i_7_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair131";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_5,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bresp_push => bresp_push,
bvalid_i_reg => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0\,
\in\(15 downto 0) => \in\(15 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready,
si_rs_bvalid => \^si_rs_bvalid\,
\state_reg[0]_rep\ => \state_reg[0]_rep\
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
I1 => \bresp_cnt_reg__0\(1),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_7_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_7_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_7_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_5,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_3,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACECCCC"
)
port map (
I0 => m_axi_bresp(0),
I1 => \s_bresp_acc_reg_n_0_[0]\,
I2 => \s_bresp_acc_reg_n_0_[1]\,
I3 => m_axi_bresp(1),
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[1]\,
I1 => m_axi_bresp(1),
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
sel_first_0 : out STD_LOGIC;
sel_first : out STD_LOGIC;
\axlen_cnt_reg[0]\ : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator is
signal incr_cmd_0_n_10 : STD_LOGIC;
signal incr_cmd_0_n_11 : STD_LOGIC;
signal incr_cmd_0_n_12 : STD_LOGIC;
signal incr_cmd_0_n_13 : STD_LOGIC;
signal incr_cmd_0_n_14 : STD_LOGIC;
signal incr_cmd_0_n_15 : STD_LOGIC;
signal incr_cmd_0_n_3 : STD_LOGIC;
signal incr_cmd_0_n_4 : STD_LOGIC;
signal incr_cmd_0_n_5 : STD_LOGIC;
signal incr_cmd_0_n_6 : STD_LOGIC;
signal incr_cmd_0_n_7 : STD_LOGIC;
signal incr_cmd_0_n_8 : STD_LOGIC;
signal incr_cmd_0_n_9 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd
port map (
E(0) => E(0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_incr_reg[0]_0\ => sel_first_0,
\axaddr_incr_reg[11]_0\(9) => incr_cmd_0_n_3,
\axaddr_incr_reg[11]_0\(8) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_10,
\axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_11,
\axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_12,
\axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[11]\ => incr_cmd_0_n_13,
\m_axi_awaddr[2]\ => incr_cmd_0_n_15,
\m_axi_awaddr[3]\ => incr_cmd_0_n_14,
\m_payload_i_reg[46]\(9 downto 7) => \m_payload_i_reg[46]\(18 downto 16),
\m_payload_i_reg[46]\(6 downto 4) => \m_payload_i_reg[46]\(14 downto 12),
\m_payload_i_reg[46]\(3 downto 0) => \m_payload_i_reg[46]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
next_pending_r_reg_0 => next_pending_r_reg,
sel_first_reg_0 => sel_first_reg_1,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]\(0) => \state_reg[0]\(0),
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[46]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
Q(1 downto 0) => Q(1 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\(9) => incr_cmd_0_n_3,
\axaddr_incr_reg[11]\(8) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]\(7) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]\(6) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]\(5) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]\(4) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]\(3) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]\(2) => incr_cmd_0_n_10,
\axaddr_incr_reg[11]\(1) => incr_cmd_0_n_11,
\axaddr_incr_reg[11]\(0) => incr_cmd_0_n_12,
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[46]\(17 downto 14) => \m_payload_i_reg[46]\(18 downto 15),
\m_payload_i_reg[46]\(13 downto 0) => \m_payload_i_reg[46]\(13 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first,
sel_first_reg_1 => sel_first_reg_2,
sel_first_reg_2 => incr_cmd_0_n_13,
sel_first_reg_3 => incr_cmd_0_n_14,
sel_first_reg_4 => incr_cmd_0_n_15,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]\(0) => \state_reg[0]\(0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 is
port (
incr_next_pending : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
sel_first : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[0]\ : out STD_LOGIC;
\axlen_cnt_reg[0]_0\ : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
si_rs_arvalid : in STD_LOGIC;
\state_reg[0]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
sel_first_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC;
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_14_b2s_cmd_translator";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 is
signal incr_cmd_0_n_10 : STD_LOGIC;
signal incr_cmd_0_n_11 : STD_LOGIC;
signal incr_cmd_0_n_12 : STD_LOGIC;
signal incr_cmd_0_n_13 : STD_LOGIC;
signal incr_cmd_0_n_14 : STD_LOGIC;
signal incr_cmd_0_n_15 : STD_LOGIC;
signal incr_cmd_0_n_3 : STD_LOGIC;
signal incr_cmd_0_n_4 : STD_LOGIC;
signal incr_cmd_0_n_5 : STD_LOGIC;
signal incr_cmd_0_n_6 : STD_LOGIC;
signal incr_cmd_0_n_7 : STD_LOGIC;
signal incr_cmd_0_n_8 : STD_LOGIC;
signal incr_cmd_0_n_9 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \state[1]_i_2\ : label is "soft_lutpair14";
begin
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2
port map (
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(11) => incr_cmd_0_n_3,
Q(10) => incr_cmd_0_n_4,
Q(9) => incr_cmd_0_n_5,
Q(8) => incr_cmd_0_n_6,
Q(7) => incr_cmd_0_n_7,
Q(6) => incr_cmd_0_n_8,
Q(5) => incr_cmd_0_n_9,
Q(4) => incr_cmd_0_n_10,
Q(3) => incr_cmd_0_n_11,
Q(2) => incr_cmd_0_n_12,
Q(1) => incr_cmd_0_n_13,
Q(0) => incr_cmd_0_n_14,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[0]_0\ => sel_first,
\axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\,
incr_next_pending => incr_next_pending,
\m_axi_araddr[11]\ => incr_cmd_0_n_15,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\(9 downto 7) => Q(18 downto 16),
\m_payload_i_reg[46]\(6 downto 4) => Q(14 downto 12),
\m_payload_i_reg[46]\(3 downto 0) => Q(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1(0) => sel_first_reg_4(0),
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\ => \state_reg[1]\,
\state_reg[1]_0\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => Q(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => Q(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
Q(17 downto 14) => Q(18 downto 15),
Q(13 downto 0) => Q(13 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\(11) => incr_cmd_0_n_3,
\axaddr_incr_reg[11]\(10) => incr_cmd_0_n_4,
\axaddr_incr_reg[11]\(9) => incr_cmd_0_n_5,
\axaddr_incr_reg[11]\(8) => incr_cmd_0_n_6,
\axaddr_incr_reg[11]\(7) => incr_cmd_0_n_7,
\axaddr_incr_reg[11]\(6) => incr_cmd_0_n_8,
\axaddr_incr_reg[11]\(5) => incr_cmd_0_n_9,
\axaddr_incr_reg[11]\(4) => incr_cmd_0_n_10,
\axaddr_incr_reg[11]\(3) => incr_cmd_0_n_11,
\axaddr_incr_reg[11]\(2) => incr_cmd_0_n_12,
\axaddr_incr_reg[11]\(1) => incr_cmd_0_n_13,
\axaddr_incr_reg[11]\(0) => incr_cmd_0_n_14,
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
\axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_15,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_r_channel is
port (
m_valid_i_reg : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_r_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_2 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_push,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_2,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[2]_rep__2\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 54 downto 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 53 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_offset : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
shandshake : out STD_LOGIC;
\wrap_second_len_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC;
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
\cnt_read_reg[0]_rep__1\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
m_valid_i0 : in STD_LOGIC;
aresetn : in STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
axaddr_offset_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_2\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axi_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axi_register_slice is
signal \gen_simple_ar.ar_pipe_n_2\ : STD_LOGIC;
signal \gen_simple_aw.aw_pipe_n_1\ : STD_LOGIC;
signal \gen_simple_aw.aw_pipe_n_91\ : STD_LOGIC;
begin
\gen_simple_ar.ar_pipe\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice
port map (
O(3 downto 0) => O(3 downto 0),
Q(53 downto 0) => \s_arid_r_reg[11]\(53 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_simple_aw.aw_pipe_n_1\,
\aresetn_d_reg[0]_0\ => \gen_simple_aw.aw_pipe_n_91\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
axaddr_offset_0(0) => axaddr_offset_0(0),
\axaddr_offset_r_reg[0]\ => \axaddr_offset_r_reg[0]\,
\axaddr_offset_r_reg[1]\ => \axaddr_offset_r_reg[1]\,
\axaddr_offset_r_reg[3]\(2 downto 0) => \axaddr_offset_r_reg[3]\(2 downto 0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \axaddr_offset_r_reg[3]_1\(2 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i0 => m_valid_i0,
m_valid_i_reg_0 => \gen_simple_ar.ar_pipe_n_2\,
next_pending_r_reg => next_pending_r_reg_0,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]_rep\ => \state_reg[1]_rep_0\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_1\(0) => \state_reg[1]_rep_2\(0),
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_second_len_r_reg[2]\(1 downto 0) => \wrap_second_len_r_reg[2]\(1 downto 0),
\wrap_second_len_r_reg[2]_0\(1 downto 0) => \wrap_second_len_r_reg[2]_0\(1 downto 0),
\wrap_second_len_r_reg[3]\ => \wrap_second_len_r_reg[3]\
);
\gen_simple_aw.aw_pipe\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice_0
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
Q(54 downto 0) => Q(54 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => \gen_simple_aw.aw_pipe_n_91\,
\aresetn_d_reg[1]_inv_0\ => \gen_simple_ar.ar_pipe_n_2\,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
axaddr_offset(1) => axaddr_offset(2),
axaddr_offset(0) => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[3]\ => axaddr_offset(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => \gen_simple_aw.aw_pipe_n_1\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
wrap_second_len(2 downto 1) => wrap_second_len(3 downto 2),
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[1]\ => wrap_second_len(1),
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0)
);
\gen_simple_b.b_pipe\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_simple_aw.aw_pipe_n_1\,
\aresetn_d_reg[1]_inv\ => \gen_simple_ar.ar_pipe_n_2\,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
shandshake => shandshake,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
\gen_simple_r.r_pipe\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_simple_aw.aw_pipe_n_1\,
\aresetn_d_reg[1]_inv\ => \gen_simple_ar.ar_pipe_n_2\,
\cnt_read_reg[0]_rep__1\ => \cnt_read_reg[0]_rep__1\,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_ar_channel is
port (
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\wrap_second_len_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
axaddr_offset : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
r_push : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
m_valid_i0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 30 downto 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_ar_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_ar_channel is
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_11 : STD_LOGIC;
signal ar_cmd_fsm_0_n_14 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_18 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_4 : STD_LOGIC;
signal ar_cmd_fsm_0_n_5 : STD_LOGIC;
signal ar_cmd_fsm_0_n_6 : STD_LOGIC;
signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_4 : STD_LOGIC;
signal cmd_translator_0_n_5 : STD_LOGIC;
signal cmd_translator_0_n_6 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal \incr_cmd_0/sel_first\ : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wrap_next_pending : STD_LOGIC;
begin
axaddr_offset(0) <= \^axaddr_offset\(0);
\axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push <= \^r_push\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
ar_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm
port map (
D(2) => ar_cmd_fsm_0_n_3,
D(1) => ar_cmd_fsm_0_n_4,
D(0) => ar_cmd_fsm_0_n_5,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => state(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[0]\(0) => ar_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[0]\(0) => \^axaddr_offset\(0),
\axaddr_offset_r_reg[3]\(1) => \^axaddr_offset_r_reg[3]\(2),
\axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axlen_cnt_reg[3]\ => cmd_translator_0_n_6,
\axlen_cnt_reg[4]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[6]\ => cmd_translator_0_n_5,
\axlen_cnt_reg[7]\ => ar_cmd_fsm_0_n_0,
\cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \m_payload_i_reg[0]\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[35]_0\ => \m_payload_i_reg[35]_0\,
\m_payload_i_reg[3]\ => \m_payload_i_reg[3]\,
\m_payload_i_reg[44]\(1 downto 0) => Q(16 downto 15),
\m_payload_i_reg[44]_0\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(1 downto 0) => \m_payload_i_reg[47]_0\(2 downto 1),
m_valid_i0 => m_valid_i0,
next_pending_r_reg => cmd_translator_0_n_1,
r_push_r_reg => \^r_push\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_11,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_14,
s_axburst_eq1_reg_0 => cmd_translator_0_n_8,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg => s_ready_i_reg,
sel_first => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_17,
sel_first_reg_0 => ar_cmd_fsm_0_n_18,
sel_first_reg_1 => cmd_translator_0_n_4,
sel_first_reg_2 => cmd_translator_0_n_2,
si_rs_arvalid => si_rs_arvalid,
\wrap_cnt_r_reg[0]\ => ar_cmd_fsm_0_n_6,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[2]\(1 downto 0) => D(1 downto 0),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len\(3),
\wrap_second_len_r_reg[3]\(0) => \wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(1) => \wrap_cmd_0/wrap_second_len_r\(3),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(0)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1
port map (
D(3 downto 1) => \m_payload_i_reg[47]_0\(2 downto 0),
D(0) => \^axaddr_offset\(0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(18 downto 0) => Q(18 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_offset_r_reg[3]\(3 downto 1) => \^axaddr_offset_r_reg[3]\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axaddr_offset_r_reg[3]_0\ => ar_cmd_fsm_0_n_6,
\axlen_cnt_reg[0]\ => cmd_translator_0_n_5,
\axlen_cnt_reg[0]_0\ => cmd_translator_0_n_6,
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_11,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_14,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
\m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_1,
r_rlast => r_rlast,
sel_first => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_4,
sel_first_reg_2 => ar_cmd_fsm_0_n_18,
sel_first_reg_3 => ar_cmd_fsm_0_n_17,
sel_first_reg_4(0) => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => cmd_translator_0_n_8,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]\ => ar_cmd_fsm_0_n_0,
\state_reg[1]_0\(1 downto 0) => state(1 downto 0),
\state_reg[1]_rep\ => \^r_push\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3) => \wrap_cmd_0/wrap_second_len_r\(3),
\wrap_second_len_r_reg[3]\(2 downto 1) => \wrap_second_len_r_reg[2]\(1 downto 0),
\wrap_second_len_r_reg[3]\(0) => \wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(3) => \wrap_cmd_0/wrap_second_len\(3),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => D(1 downto 0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_4,
\wrap_second_len_r_reg[3]_1\(0) => ar_cmd_fsm_0_n_5
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(19),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(29),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(30),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(20),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(21),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(22),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(23),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(24),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(25),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(26),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(27),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(28),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_aw_channel is
port (
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[0]\ : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
\m_payload_i_reg[61]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_aw_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_aw_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_10 : STD_LOGIC;
signal aw_cmd_fsm_0_n_11 : STD_LOGIC;
signal aw_cmd_fsm_0_n_12 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal aw_cmd_fsm_0_n_5 : STD_LOGIC;
signal aw_cmd_fsm_0_n_6 : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_5 : STD_LOGIC;
signal cmd_translator_0_n_6 : STD_LOGIC;
signal cmd_translator_0_n_7 : STD_LOGIC;
signal \incr_cmd_0/sel_first\ : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal sel_first : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[0]\ : STD_LOGIC;
signal wrap_next_pending : STD_LOGIC;
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\wrap_boundary_axaddr_r_reg[0]\ <= \^wrap_boundary_axaddr_r_reg[0]\;
aw_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm
port map (
E(0) => aw_cmd_fsm_0_n_0,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axlen_cnt_reg[0]\ => aw_cmd_fsm_0_n_3,
\axlen_cnt_reg[1]\ => cmd_translator_0_n_7,
\axlen_cnt_reg[6]\ => cmd_translator_0_n_5,
\axlen_cnt_reg[7]\ => aw_cmd_fsm_0_n_5,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\,
\cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0_0\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\(0) => E(0),
\m_payload_i_reg[39]\(0) => \m_payload_i_reg[61]\(15),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_6,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_10,
s_axburst_eq1_reg_0 => cmd_translator_0_n_6,
sel_first => sel_first,
sel_first_0 => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_11,
sel_first_reg_0 => aw_cmd_fsm_0_n_12,
sel_first_reg_1 => cmd_translator_0_n_2,
si_rs_awvalid => si_rs_awvalid,
\wrap_boundary_axaddr_r_reg[0]\(0) => \^wrap_boundary_axaddr_r_reg[0]\,
wrap_next_pending => wrap_next_pending
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[0]\,
Q(1 downto 0) => \^q\(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axlen_cnt_reg[0]\ => cmd_translator_0_n_5,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_6,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_10,
\m_payload_i_reg[46]\(18 downto 0) => \m_payload_i_reg[61]\(18 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_7,
sel_first => sel_first,
sel_first_0 => \incr_cmd_0/sel_first\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_12,
sel_first_reg_2 => aw_cmd_fsm_0_n_11,
si_rs_awvalid => si_rs_awvalid,
\state_reg[0]\(0) => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_6,
\state_reg[0]_rep_0\ => aw_cmd_fsm_0_n_5,
\state_reg[1]_rep\ => aw_cmd_fsm_0_n_3,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(20),
Q => \in\(4),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(21),
Q => \in\(5),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(22),
Q => \in\(6),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(23),
Q => \in\(7),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(29),
Q => \in\(13),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[61]\(19),
Q => \in\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s is
signal \RD.ar_channel_0_n_0\ : STD_LOGIC;
signal \RD.ar_channel_0_n_38\ : STD_LOGIC;
signal \RD.ar_channel_0_n_39\ : STD_LOGIC;
signal \RD.ar_channel_0_n_40\ : STD_LOGIC;
signal \RD.ar_channel_0_n_41\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_1\ : STD_LOGIC;
signal SI_REG_n_10 : STD_LOGIC;
signal SI_REG_n_103 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_153 : STD_LOGIC;
signal SI_REG_n_154 : STD_LOGIC;
signal SI_REG_n_161 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_168 : STD_LOGIC;
signal SI_REG_n_169 : STD_LOGIC;
signal SI_REG_n_170 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_172 : STD_LOGIC;
signal SI_REG_n_173 : STD_LOGIC;
signal SI_REG_n_174 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_45 : STD_LOGIC;
signal SI_REG_n_83 : STD_LOGIC;
signal SI_REG_n_84 : STD_LOGIC;
signal SI_REG_n_85 : STD_LOGIC;
signal SI_REG_n_86 : STD_LOGIC;
signal \WR.aw_channel_0_n_2\ : STD_LOGIC;
signal \WR.aw_channel_0_n_42\ : STD_LOGIC;
signal \WR.aw_channel_0_n_43\ : STD_LOGIC;
signal \WR.aw_channel_0_n_44\ : STD_LOGIC;
signal \WR.aw_channel_0_n_45\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \WR.b_channel_0_n_3\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axaddr_incr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_simple_ar.ar_pipe/m_valid_i0\ : STD_LOGIC;
signal \gen_simple_ar.ar_pipe/p_1_in\ : STD_LOGIC;
signal \gen_simple_aw.aw_pipe/p_1_in\ : STD_LOGIC;
signal r_push : STD_LOGIC;
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 2 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
s_axi_arready <= \^s_axi_arready\;
\RD.ar_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_ar_channel
port map (
D(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(2 downto 1),
E(0) => \gen_simple_ar.ar_pipe/p_1_in\,
O(3) => SI_REG_n_145,
O(2) => SI_REG_n_146,
O(1) => SI_REG_n_147,
O(0) => SI_REG_n_148,
Q(30 downto 19) => s_arid(11 downto 0),
Q(18 downto 16) => si_rs_arlen(2 downto 0),
Q(15) => si_rs_arburst(1),
Q(14) => SI_REG_n_103,
Q(13 downto 12) => si_rs_arsize(1 downto 0),
Q(11 downto 0) => si_rs_araddr(11 downto 0),
S(3) => \RD.ar_channel_0_n_38\,
S(2) => \RD.ar_channel_0_n_39\,
S(1) => \RD.ar_channel_0_n_40\,
S(0) => \RD.ar_channel_0_n_41\,
aclk => aclk,
areset_d1 => areset_d1,
axaddr_offset(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(0),
\axaddr_offset_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 1),
\cnt_read_reg[1]_rep__0\ => \RD.r_channel_0_n_1\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_8\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[35]\ => SI_REG_n_161,
\m_payload_i_reg[35]_0\ => SI_REG_n_163,
\m_payload_i_reg[3]\ => SI_REG_n_173,
\m_payload_i_reg[3]_0\(3) => SI_REG_n_83,
\m_payload_i_reg[3]_0\(2) => SI_REG_n_84,
\m_payload_i_reg[3]_0\(1) => SI_REG_n_85,
\m_payload_i_reg[3]_0\(0) => SI_REG_n_86,
\m_payload_i_reg[44]\ => SI_REG_n_162,
\m_payload_i_reg[47]\ => SI_REG_n_164,
\m_payload_i_reg[47]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3 downto 1),
\m_payload_i_reg[6]\(6) => SI_REG_n_166,
\m_payload_i_reg[6]\(5) => SI_REG_n_167,
\m_payload_i_reg[6]\(4) => SI_REG_n_168,
\m_payload_i_reg[6]\(3) => SI_REG_n_169,
\m_payload_i_reg[6]\(2) => SI_REG_n_170,
\m_payload_i_reg[6]\(1) => SI_REG_n_171,
\m_payload_i_reg[6]\(0) => SI_REG_n_172,
\m_payload_i_reg[7]\(3) => SI_REG_n_141,
\m_payload_i_reg[7]\(2) => SI_REG_n_142,
\m_payload_i_reg[7]\(1) => SI_REG_n_143,
\m_payload_i_reg[7]\(0) => SI_REG_n_144,
m_valid_i0 => \gen_simple_ar.ar_pipe/m_valid_i0\,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push => r_push,
r_rlast => r_rlast,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg => \^s_axi_arready\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_0\,
\wrap_second_len_r_reg[2]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(2 downto 1)
);
\RD.r_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_0\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_push => r_push,
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_165,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_1\
);
SI_REG: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axi_register_slice
port map (
D(3 downto 2) => wrap_cnt(3 downto 2),
D(1) => SI_REG_n_10,
D(0) => wrap_cnt(0),
E(0) => \gen_simple_aw.aw_pipe/p_1_in\,
O(3) => SI_REG_n_145,
O(2) => SI_REG_n_146,
O(1) => SI_REG_n_147,
O(0) => SI_REG_n_148,
Q(54 downto 43) => s_awid(11 downto 0),
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_45,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_42\,
S(2) => \WR.aw_channel_0_n_43\,
S(1) => \WR.aw_channel_0_n_44\,
S(0) => \WR.aw_channel_0_n_45\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_incr_reg[3]\(3) => SI_REG_n_83,
\axaddr_incr_reg[3]\(2) => SI_REG_n_84,
\axaddr_incr_reg[3]\(1) => SI_REG_n_85,
\axaddr_incr_reg[3]\(0) => SI_REG_n_86,
\axaddr_incr_reg[7]\(3) => SI_REG_n_141,
\axaddr_incr_reg[7]\(2) => SI_REG_n_142,
\axaddr_incr_reg[7]\(1) => SI_REG_n_143,
\axaddr_incr_reg[7]\(0) => SI_REG_n_144,
axaddr_offset(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3 downto 0),
axaddr_offset_0(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(0),
\axaddr_offset_r_reg[0]\ => SI_REG_n_173,
\axaddr_offset_r_reg[1]\ => SI_REG_n_161,
\axaddr_offset_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3 downto 1),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 1),
\axlen_cnt_reg[3]\ => SI_REG_n_153,
\axlen_cnt_reg[3]_0\ => SI_REG_n_164,
b_push => b_push,
\cnt_read_reg[0]_rep__1\ => SI_REG_n_165,
\cnt_read_reg[3]_rep__0\ => \RD.r_channel_0_n_0\,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_38\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_39\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_40\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_41\,
m_valid_i0 => \gen_simple_ar.ar_pipe/m_valid_i0\,
next_pending_r_reg => SI_REG_n_154,
next_pending_r_reg_0 => SI_REG_n_162,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(53 downto 42) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(41 downto 39) => si_rs_arlen(2 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_103,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => \^s_axi_arready\,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
shandshake => shandshake,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_2\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_0\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\(0) => \gen_simple_ar.ar_pipe/p_1_in\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_166,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_167,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_168,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_169,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_170,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_171,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_172,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_174,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_175,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_176,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_177,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_178,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_179,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_180,
wrap_second_len(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 0),
\wrap_second_len_r_reg[2]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(2 downto 1),
\wrap_second_len_r_reg[2]_0\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(2 downto 1),
\wrap_second_len_r_reg[3]\ => SI_REG_n_163,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\(3 downto 0)
);
\WR.aw_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_aw_channel
port map (
D(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3 downto 0),
E(0) => \gen_simple_aw.aw_pipe/p_1_in\,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_42\,
S(2) => \WR.aw_channel_0_n_43\,
S(1) => \WR.aw_channel_0_n_44\,
S(0) => \WR.aw_channel_0_n_45\,
aclk => aclk,
areset_d1 => areset_d1,
axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_3\,
\cnt_read_reg[1]_rep__0_0\ => \WR.b_channel_0_n_2\,
\in\(15 downto 4) => b_awid(11 downto 0),
\in\(3 downto 0) => b_awlen(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[46]\ => SI_REG_n_154,
\m_payload_i_reg[47]\ => SI_REG_n_153,
\m_payload_i_reg[61]\(31 downto 20) => s_awid(11 downto 0),
\m_payload_i_reg[61]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[61]\(15) => si_rs_awburst(1),
\m_payload_i_reg[61]\(14) => SI_REG_n_45,
\m_payload_i_reg[61]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[61]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\(6) => SI_REG_n_174,
\m_payload_i_reg[6]\(5) => SI_REG_n_175,
\m_payload_i_reg[6]\(4) => SI_REG_n_176,
\m_payload_i_reg[6]\(3) => SI_REG_n_177,
\m_payload_i_reg[6]\(2) => SI_REG_n_178,
\m_payload_i_reg[6]\(1) => SI_REG_n_179,
\m_payload_i_reg[6]\(0) => SI_REG_n_180,
si_rs_awvalid => si_rs_awvalid,
\wrap_boundary_axaddr_r_reg[0]\ => \WR.aw_channel_0_n_2\,
\wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(1) => SI_REG_n_10,
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\,
\in\(15 downto 4) => b_awid(11 downto 0),
\in\(3 downto 0) => b_awlen(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
shandshake => shandshake,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
\state_reg[0]_rep\ => \WR.b_channel_0_n_3\
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter : entity is "2'b10";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_auto_pc_0,axi_protocol_converter_v2_1_14_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
attribute X_INTERFACE_INFO of s_axi_arid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARID";
attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARQOS";
attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
attribute X_INTERFACE_INFO of s_axi_awid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWID";
attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWQOS";
attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
attribute X_INTERFACE_INFO of s_axi_bid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BID";
attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute X_INTERFACE_INFO of s_axi_rid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RID";
attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute X_INTERFACE_INFO of s_axi_wid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WID";
attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
begin
END;
end generate;
IF_LABEL : if a = '1' generate
begin
END;
end generate;
CASE_LABEL : case data generate
when choice =>
begin
END;
end generate;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
begin
END;
end generate;
IF_LABEL : if a = '1' generate
begin
END;
end generate;
CASE_LABEL : case data generate
when choice =>
begin
END;
end generate;
end;
|
--------------------------------------------------------------------------------
--
-- Title : fp23_mult
-- Design : fpfftk
-- Author : Kapitanov
-- Company :
--
-------------------------------------------------------------------------------
--
-- Description : floating point multiplier
--
-------------------------------------------------------------------------------
--
-- Version 1.0 22.02.2013
-- Description:
-- Multiplier for FP - 2DSP48E1 slices
-- 4 clock cycles delay
--
--
-- Version 1.2 15.01.2014
-- Description:
-- 5 clock cycles delay, improved logic
--
-- Version 1.3 24.03.2015
-- Description:
-- Deleted din_en signal
-- This version is fully pipelined with 1 DSP48E1!
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- The MIT License (MIT)
-- Copyright (c) 2016 Kapitanov Alexander
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library unisim;
use unisim.vcomponents.DSP48E1;
use unisim.vcomponents.DSP48E2;
library work;
use work.reduce_pack.all;
use work.fp_m1_pkg.fp23_data;
entity fp23_mult is
generic(
EXP_DIF : std_logic_vector(5 downto 0):="011111"; -- DIFF_EXP
XSERIES : string:="7SERIES" --! Xilinx series
);
port(
aa : in fp23_data; --! Multiplicand A
bb : in fp23_data; --! Multiplier B
cc : out fp23_data; --! Product C
enable : in std_logic; --! Input data enable
valid : out std_logic; --! Output data valid
reset : in std_logic; --! Reset
clk : in std_logic --! Clock
);
end fp23_mult;
architecture fp23_mult of fp23_mult is
type std_logic_array_4x6 is array(3 downto 0) of std_logic_vector(5 downto 0);
signal man_aa : std_logic_vector(29 downto 0);
signal man_bb : std_logic_vector(17 downto 0);
type std_logic_array_2x5 is array(1 downto 0) of std_logic_vector(5 downto 0);
signal exp_az : std_logic_array_2x5;
signal exp_bz : std_logic_array_2x5;
signal exp_cc : std_logic_vector(5 downto 0);
signal exp_df : std_logic_vector(6 downto 0);
signal sig_cc : std_logic;
signal man_cc : std_logic_vector(15 downto 0);
signal prod : std_logic_vector(47 downto 0);
signal sig_ccz : std_logic_vector(2 downto 0);
signal exp_underflow : std_logic;
signal exp_underflowz : std_logic;
---------------------------------------
signal expa_or : std_logic;
signal expb_or : std_logic;
signal exp_zero : std_logic;
signal exp_zeroz : std_logic;
signal enaz : std_logic_vector(3 downto 0);
begin
---- finding zero exponents for multipliers ----
expa_or <= or_reduce(aa.exp) when rising_edge(clk);
expb_or <= or_reduce(bb.exp) when rising_edge(clk);
exp_zero <= (expa_or and expb_or) when rising_edge(clk);
exp_zeroz <= exp_zero when rising_edge(clk);
-- forming fractions for mulptiplier
man_aa(29 downto 18) <= x"000";
man_aa(17 downto 0) <= "01" & aa.man;
man_bb <= "01" & bb.man;
x7SERIES: if (XSERIES = "7SERIES") generate
NORMALIZE: DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT",
B_INPUT => "DIRECT",
USE_DPORT => FALSE,
USE_MULT => "MULTIPLY",
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 1,
AREG => 1,
BCASCREG => 1,
BREG => 1,
CARRYINREG => 1,
CARRYINSELREG => 1,
CREG => 1,
DREG => 1,
INMODEREG => 1,
MREG => 1,
OPMODEREG => 1,
PREG => 1
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open,
BCOUT => open,
CARRYCASCOUT => open,
MULTSIGNOUT => open,
PCOUT => open,
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open,
PATTERNBDETECT => open,
PATTERNDETECT => open,
UNDERFLOW => open,
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open,
P => prod,
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others=>'0'),
BCIN => (others=>'0'),
CARRYCASCIN => '0',
MULTSIGNIN => '0',
PCIN => (others=>'0'),
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => (others=>'0'),
CARRYINSEL => (others=>'0'),
CLK => clk,
INMODE => (others=>'0'),
OPMODE => "0000101",
-- Data: 30-bit (each) input: Data Ports
A => man_aa,
B => man_bb,
C => (others=>'0'),
CARRYIN => '0',
D => (others=>'0'),
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => enable,
CEA2 => '1',
CEAD => '0',
CEALUMODE => '1',
CEB1 => enable,
CEB2 => '1',
CEC => '1',
CECARRYIN => '1',
CECTRL => '1',
CED => '1',
CEINMODE => '1',
CEM => '1',
CEP => '1',
RSTA => reset,
RSTALLCARRYIN => reset,
RSTALUMODE => reset,
RSTB => reset,
RSTC => reset,
RSTCTRL => reset,
RSTD => reset,
RSTINMODE => reset,
RSTM => reset,
RSTP => reset
);
end generate;
xULTRA: if (XSERIES = "ULTRA") generate
NORMALIZE : DSP48E2
generic map (
-- Feature Control Attributes: Data Path Selection
AMULTSEL => "A",
A_INPUT => "DIRECT",
BMULTSEL => "B",
B_INPUT => "DIRECT",
PREADDINSEL => "A",
USE_MULT => "MULTIPLY",
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 1,
AREG => 1,
BCASCREG => 1,
BREG => 1,
CARRYINREG => 1,
CARRYINSELREG => 1,
CREG => 1,
DREG => 1,
INMODEREG => 1,
MREG => 1,
OPMODEREG => 1,
PREG => 1
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open,
BCOUT => open,
CARRYCASCOUT => open,
MULTSIGNOUT => open,
PCOUT => open,
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open,
PATTERNBDETECT => open,
PATTERNDETECT => open,
UNDERFLOW => open,
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open,
P => prod,
XOROUT => open,
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others=>'0'),
BCIN => (others=>'0'),
CARRYCASCIN => '0',
MULTSIGNIN => '0',
PCIN => (others=>'0'),
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => (others=>'0'),
CARRYINSEL => (others=>'0'),
CLK => clk,
INMODE => (others=>'0'),
OPMODE => "000000101",
-- Data inputs: Data Ports
A => man_aa,
B => man_bb,
C => (others=>'0'),
CARRYIN => '0',
D => (others=>'0'),
-- Reset/Clock Enable inputs: Reset/Clock Enable Inputs
CEA1 => enable,
CEA2 => '1',
CEAD => '0',
CEALUMODE => '1',
CEB1 => enable,
CEB2 => '1',
CEC => '1',
CECARRYIN => '1',
CECTRL => '1',
CED => '1',
CEINMODE => '1',
CEM => '1',
CEP => '1',
RSTA => reset,
RSTALLCARRYIN => reset,
RSTALUMODE => reset,
RSTB => reset,
RSTC => reset,
RSTCTRL => reset,
RSTD => reset,
RSTINMODE => reset,
RSTM => reset,
RSTP => reset
);
end generate;
---- exp difference ----
pr_exp: process(clk) is
begin
if rising_edge(clk) then
exp_az <= exp_az(0) & aa.exp;
exp_bz <= exp_bz(0) & bb.exp;
exp_df <= ('0' & exp_az(1)) + ('0' & exp_bz(1)) - ('0' & EXP_DIF);
if (exp_df(exp_df'left) = '0') then
exp_cc <= exp_df(exp_df'left-1 downto 0) + prod(33);
else
exp_cc <= (others=>'0');
end if;
end if;
end process;
-- find sign as xor of signs --
pr_sign: process(clk) is
begin
if rising_edge(clk) then
sig_cc <= aa.sig xor bb.sig;
sig_ccz <= sig_ccz(1 downto 0) & sig_cc;
end if;
end process;
-- find fraction --
pr_frac: process(clk) is
begin
if rising_edge(clk) then
if (prod(33) = '0') then
man_cc <= prod(31 downto 16);
else
man_cc <= prod(32 downto 17);
end if;
end if;
end process;
-- data out and result --
--exp_underflowz <= (exp_underflow and exp_zeroz) when rising_edge(clk);
exp_underflowz <= (exp_zeroz) when rising_edge(clk);
pr_dout: process(clk) is
begin
if rising_edge(clk) then
if (exp_underflowz = '0') then
cc <= ("000000", '0', x"0000");
else
cc <= (exp_cc, sig_ccz(2), man_cc);
end if;
end if;
end process;
enaz <= enaz(2 downto 0) & enable when rising_edge(clk);
valid <= enaz(3) when rising_edge(clk);
end fp23_mult;
|
-------------------------------------------------------------------------------
-- Title : Rotation-mode cordic, slv version
-- Project :
-------------------------------------------------------------------------------
-- File : cordic_rotate_slv.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-05-13
-- Last update: 2014-05-14
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This is a top-block for rotation mode using concordic,
-- constrained standard_logic_vector version.
-------------------------------------------------------------------------------
-- This file is part of Concordic.
--
-- Concordic is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Concordic is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- Copyright (c) 2014 Aylons Hazzud
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-05-13 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity cordic_rotate_slv is
generic (
g_stages : natural := 20;
g_width : natural := 32
);
port (
x_i : in std_logic_vector(g_width-1 downto 0) := "11000000";
y_i : in std_logic_vector(g_width-1 downto 0) := "11000000";
clk_i : in std_logic;
ce_i : in std_logic;
mag_o : out std_logic_vector(g_width-1 downto 0);
phase_o : out std_logic_vector(g_width-1 downto 0)
);
end entity cordic_rotate_slv;
-------------------------------------------------------------------------------
architecture str of cordic_rotate_slv is
signal adjusted_x : signed(g_width-1 downto 0);
signal adjusted_y : signed(g_width-1 downto 0);
signal adjusted_z : signed(g_width-1 downto 0);
signal mag_temp : signed(g_width-1 downto 0);
signal phase_temp : signed(g_width-1 downto 0);
signal y_temp : signed(g_width-1 downto 0);
component inversion_stage is
generic (
g_mode : string);
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed);
end component inversion_stage;
component cordic_core is
generic (
g_stages : natural;
g_mode : string);
port (
x_i : in signed;
y_i : in signed;
z_i : in signed;
clk_i : in std_logic;
ce_i : in std_logic;
x_o : out signed;
y_o : out signed;
z_o : out signed);
end component cordic_core;
begin -- architecture str
cmp_inversion : inversion_stage
generic map (
g_mode => "rect_to_polar")
port map (
x_i => signed(x_i),
y_i => signed(y_i),
z_i => (g_width-1 downto 0 => '0'),
clk_i => clk_i,
ce_i => ce_i,
x_o => adjusted_x,
y_o => adjusted_y,
z_o => adjusted_z);
cmp_core : cordic_core
generic map (
g_stages => g_stages,
g_mode => "rect_to_polar")
port map (
x_i => adjusted_x,
y_i => adjusted_y,
z_i => adjusted_z,
clk_i => clk_i,
ce_i => ce_i,
x_o => mag_temp,
y_o => y_temp,
z_o => phase_temp);
mag_o <= std_logic_vector(mag_temp);
phase_o <= std_logic_vector(phase_temp);
end architecture str;
-------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: zybo_vga - Structural
-- Description: Breakout for the vga output on the Zybo
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zybo_vga is
port(
clk : in std_logic;
active : in std_logic;
rgb : in std_logic_vector(15 downto 0);
vga_r : out std_logic_vector(4 downto 0);
vga_g : out std_logic_vector(5 downto 0);
vga_b : out std_logic_vector(4 downto 0)
);
end zybo_vga;
architecture Structural of zybo_vga is
signal r : std_logic_vector(4 downto 0) := "00000";
signal g : std_logic_vector(5 downto 0) := "000000";
signal b : std_logic_vector(4 downto 0) := "00000";
begin
process(clk)
begin
if falling_edge(clk) then
if active = '1' then
r <= rgb(15 downto 11);
g <= rgb(10 downto 5);
b <= rgb(4 downto 0);
end if;
end if;
end process;
vga_r <= r;
vga_g <= g;
vga_b <= b;
end Structural;
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: zybo_vga - Structural
-- Description: Breakout for the vga output on the Zybo
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zybo_vga is
port(
clk : in std_logic;
active : in std_logic;
rgb : in std_logic_vector(15 downto 0);
vga_r : out std_logic_vector(4 downto 0);
vga_g : out std_logic_vector(5 downto 0);
vga_b : out std_logic_vector(4 downto 0)
);
end zybo_vga;
architecture Structural of zybo_vga is
signal r : std_logic_vector(4 downto 0) := "00000";
signal g : std_logic_vector(5 downto 0) := "000000";
signal b : std_logic_vector(4 downto 0) := "00000";
begin
process(clk)
begin
if falling_edge(clk) then
if active = '1' then
r <= rgb(15 downto 11);
g <= rgb(10 downto 5);
b <= rgb(4 downto 0);
end if;
end if;
end process;
vga_r <= r;
vga_g <= g;
vga_b <= b;
end Structural;
|
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: VGA_SYNC
-- AUTHORS: Vojtěch Jeřábek <[email protected]>
-- Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity VGA_SYNC is
Port (
CLK : in std_logic; -- clock, must be 50 MHz
RST : in std_logic; -- reset
PIXEL_X : out std_logic_vector(9 downto 0); -- cislo pixelu na radku
PIXEL_Y : out std_logic_vector(9 downto 0); -- cislo pixelu ve sloupci
HSYNC : out std_logic; -- synchronizacni pulzy pro VGA vystup
VSYNC : out std_logic
);
end VGA_SYNC;
architecture Behavioral of VGA_SYNC is
signal pixel_tick : std_logic; -- doba vykreslovani pixelu - 25 MHz
signal position_x : unsigned(9 downto 0); -- udava cislo pixelu na radku
signal position_y : unsigned(9 downto 0); -- udava cislo pixelu ve sloupci
begin
----------------------------------------------------------------------------
-- pixel_tick o potrebne frekvenci 25MHz, vyzaduje CLK o frekvenci 50MHZ
pixel_tick_p : process (CLK, RST)
begin
if (RST = '1') then
pixel_tick <= '0';
elsif (rising_edge(CLK)) then
pixel_tick <= not pixel_tick;
end if;
end process;
----------------------------------------------------------------------------
-- pocitani na jakem pixelu na radku se nachazime
position_x_p : process (CLK, RST)
begin
if (RST = '1') then
position_x <= (others => '0');
elsif (rising_edge(CLK)) then
if (pixel_tick = '1') then
if (position_x = 799) then
position_x <= (others => '0');
else
position_x <= position_x + 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- pocitani na jakem pixelu ve sloupci se nachazime
position_y_p : process (CLK, RST)
begin
if (RST = '1') then
position_y <= (others => '0');
elsif (rising_edge(CLK)) then
if (pixel_tick = '1' and position_x = 799) then
if (position_y = 524) then
position_y <= (others => '0');
else
position_y <= position_y + 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- synchronizacni pulzy pro VGA
hsync_reg_p : process (CLK, RST)
begin
if (RST = '1') then
HSYNC <= '0';
elsif (rising_edge(CLK)) then
if (position_x > 655 and position_x < 752) then
HSYNC <= '0';
else
HSYNC <= '1';
end if;
end if;
end process;
vsync_reg_p : process (CLK, RST)
begin
if (RST = '1') then
VSYNC <= '0';
elsif (rising_edge(CLK)) then
if (position_y > 489 and position_y < 492) then
VSYNC <= '0';
else
VSYNC <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------------
-- prirazeni vystupnich signalu
PIXEL_X <= std_logic_vector(position_x);
PIXEL_Y <= std_logic_vector(position_y);
end Behavioral;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:06:11 01/04/2014
-- Design Name:
-- Module Name: C:/Users/Ruy/Desktop/LCSE_lab/dma/tb_dma_bus_controller.vhd
-- Project Name: dma
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dma_bus_controller
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_dma_bus_controller IS
END tb_dma_bus_controller;
ARCHITECTURE behavior OF tb_dma_bus_controller IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dma_bus_controller
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
Databus : INOUT std_logic_vector(7 downto 0);
Address : OUT std_logic_vector(7 downto 0);
ChipSelect : OUT std_logic;
WriteEnable : OUT std_logic;
OutputEnable : OUT std_logic;
Send : IN std_logic;
Ready : OUT std_logic;
DMA_RQ : OUT std_logic;
DMA_ACK : IN std_logic;
RX_empty : IN std_logic;
-- pragma synthesis_off
BC_state_ns : out integer;
-- pragma synthesis_on
RX_Databus : IN std_logic_vector(7 downto 0);
RX_Address : IN std_logic_vector(7 downto 0);
RX_ChipSelect : IN std_logic;
RX_WriteEnable : IN std_logic;
RX_OutputEnable : IN std_logic;
RX_start : OUT std_logic;
RX_end : IN std_logic;
TX_Databus : OUT std_logic_vector(7 downto 0);
TX_Address : IN std_logic_vector(7 downto 0);
TX_ChipSelect : IN std_logic;
TX_WriteEnable : IN std_logic;
TX_OutputEnable : IN std_logic;
TX_start : OUT std_logic;
TX_ready : IN std_logic;
TX_end : IN std_logic
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal Send : std_logic := '0';
signal DMA_ACK : std_logic := '0';
signal RX_empty : std_logic := '1';
signal RX_Databus : std_logic_vector(7 downto 0) := X"AA";
signal RX_Address : std_logic_vector(7 downto 0) := X"AA";
signal RX_ChipSelect : std_logic := '1';
signal RX_WriteEnable : std_logic := '0';
signal RX_OutputEnable : std_logic := '1';
signal RX_end : std_logic := '0';
signal TX_Address : std_logic_vector(7 downto 0) := X"55";
signal TX_ChipSelect : std_logic := '1';
signal TX_WriteEnable : std_logic := '1';
signal TX_OutputEnable : std_logic := '0';
signal TX_ready : std_logic := '1';
signal TX_end : std_logic := '0';
--BiDirs
signal Databus : std_logic_vector(7 downto 0) := X"55";
--Outputs
signal Address : std_logic_vector(7 downto 0);
signal ChipSelect : std_logic;
signal WriteEnable : std_logic;
signal OutputEnable : std_logic;
signal Ready : std_logic;
signal DMA_RQ : std_logic;
signal RX_start : std_logic;
signal TX_Databus : std_logic_vector(7 downto 0);
signal TX_start : std_logic;
-- pragma synthesis_on
signal BC_state_ns : integer;
-- pragma synthesis_on
-- Clock period definitions
constant Clk_period : time := 25ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dma_bus_controller PORT MAP (
Clk => Clk,
Reset => Reset,
Databus => Databus,
Address => Address,
ChipSelect => ChipSelect,
WriteEnable => WriteEnable,
OutputEnable => OutputEnable,
Send => Send,
Ready => Ready,
DMA_RQ => DMA_RQ,
DMA_ACK => DMA_ACK,
RX_empty => RX_empty,
-- pragma synthesis_off
BC_state_ns => BC_state_ns,
-- pragma synthesis_on
RX_Databus => RX_Databus,
RX_Address => RX_Address,
RX_ChipSelect => RX_ChipSelect,
RX_WriteEnable => RX_WriteEnable,
RX_OutputEnable => RX_OutputEnable,
RX_start => RX_start,
RX_end => RX_end,
TX_Databus => TX_Databus,
TX_Address => TX_Address,
TX_ChipSelect => TX_ChipSelect,
TX_WriteEnable => TX_WriteEnable,
TX_OutputEnable => TX_OutputEnable,
TX_start => TX_start,
TX_ready => TX_ready,
TX_end => TX_end
);
Clk <= not Clk after Clk_period;
-- Stimulus process
process
begin
wait for 50 ns;
Reset <= '1';
wait for 100 ns;
RX_Empty <= '0';
wait until BC_state_ns = 2;
Databus <= (others => 'Z');
wait for 325 ns;
DMA_ACK <= '1';
wait for 175 ns;
RX_empty <= '1';
wait until DMA_RQ = '0';
DMA_ACK <= '0' after 2 ns;
wait until BC_state_ns = 0;
Databus <= X"22";
wait;
end process;
process
begin
wait until BC_state_ns = 1;
TX_ready <= '0';
wait for 325 ns;
TX_end <= '1';
wait for 50 ns;
TX_end <= '0';
wait for 500 ns;
TX_ready <= '1';
wait;
end process;
process
begin
wait until BC_state_ns = 4;
wait for 325 ns;
RX_end <= '1';
wait for 50 ns;
RX_end <= '0';
wait;
end process;
process
begin
wait for 300 ns;
Send <= '1';
wait until Ready = '1';
Send <= '0' after 10 ns;
wait;
end process;
END;
|
-----------------------------------------------------------------------------------
-- Odsek za racunarsku tehniku i medjuracunarske komunikacije --
-- Copyright © 2009 All Rights Reserved --
-- --
-- Projekat: LabVezba2 --
-- Ime modula: char_rom.vhd --
-- Autori: LPRS2 TIM 2009/2010 <[email protected]> --
-- --
-- Opis: --
-- Char_rom generise tekst na ekranu. --
-- Znak se predstavlja matricom 8x8 tacaka. --
-- Oblici znakova se nalaze u datoteci char_rom_def_mem.coe --
-- --
-----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY char_rom IS PORT (
clk_i : IN STD_LOGIC; -- takt SIGNAL
character_address_i : IN STD_LOGIC_VECTOR (5 DOWNTO 0); -- adresa karaktera
font_row_i : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- ispis reda
font_col_i : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- ispis kolone
rom_mux_output_o : OUT STD_LOGIC -- izlazni SIGNAL iz char_rom-a
);
END char_rom;
ARCHITECTURE Behavioral OF char_rom IS
SIGNAL rom_data : STD_LOGIC_VECTOR( 7 DOWNTO 0 ); -- prosledjuje izlaz iz char_rom-a na ulaz u VGA
SIGNAL rom_address : STD_LOGIC_VECTOR( 8 DOWNTO 0 ); -- preuzima character_address_i i font_row_i
COMPONENT char_rom_def IS PORT (
clk : IN STD_LOGIC; -- takt
addr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); -- adresa znaka
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- izlaz
);
END COMPONENT;
BEGIN
-- Oblici znakova se nalaze u datoteci char_rom_def_mem.coe
BRAM_MEM_I: char_rom_def PORT MAP (
clk => clk_i ,
addr => rom_address,
dout => rom_data
);
------------------|----------
-- ADDRESS | OFFSET |
------------------|----------
rom_address <= character_address_i & font_row_i;
PROCESS(font_col_i, rom_data) BEGIN
CASE(font_col_i) IS
WHEN "000" => rom_mux_output_o <= rom_data(7);
WHEN "001" => rom_mux_output_o <= rom_data(6);
WHEN "010" => rom_mux_output_o <= rom_data(5);
WHEN "011" => rom_mux_output_o <= rom_data(4);
WHEN "100" => rom_mux_output_o <= rom_data(3);
WHEN "101" => rom_mux_output_o <= rom_data(2);
WHEN "110" => rom_mux_output_o <= rom_data(1);
WHEN "111" => rom_mux_output_o <= rom_data(0);
WHEN OTHERS => rom_mux_output_o <= '0';
END CASE;
END PROCESS;
END Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Altera Stratix-III LEON3 Demonstration design test bench
-- Copyright (C) 2007 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
library hynix;
use hynix.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1; -- number of ram banks
dbits : integer := CFG_DDR2SP_DATAWIDTH
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
constant lresp : boolean := false;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal Rst : std_logic := '0'; -- Reset
signal clk : std_logic := '0';
signal clk125 : std_logic := '0';
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal txd1, rxd1 : std_ulogic;
-- PSRAM and FLASH control
signal sram_advn : std_logic;
signal sram_csn : std_logic;
signal sram_wen : std_logic;
signal sram_ben : std_logic_vector (0 to 3);
signal sram_oen : std_ulogic;
signal sram_clk : std_ulogic;
signal sram_adscn : std_ulogic;
signal sram_psn : std_ulogic;
signal sram_adv_n : std_ulogic;
signal sram_wait : std_logic_vector(1 downto 0);
signal flash_clk, flash_cen, max_csn : std_logic;
signal flash_advn, flash_oen, flash_resetn, flash_wen : std_logic;
-- DDR2 memory
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_odt : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (8 downto 0); -- ddr dm
signal ddr_dqsp : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_dqsn : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_rdqs : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (15 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (2 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (71 downto 0); -- ddr data
signal ddr_dq2 : std_logic_vector (71 downto 0); -- ddr data
--signal ddra_cke : std_logic;
--signal ddra_csb : std_logic;
--signal ddra_web : std_ulogic; -- ddr write enable
--signal ddra_rasb : std_ulogic; -- ddr ras
--signal ddra_casb : std_ulogic; -- ddr cas
--signal ddra_ad : std_logic_vector (15 downto 0); -- ddr address
--signal ddra_ba : std_logic_vector (2 downto 0); -- ddr bank address
--signal ddrb_cke : std_logic;
--signal ddrb_csb : std_logic;
--signal ddrb_web : std_ulogic; -- ddr write enable
--signal ddrb_rasb : std_ulogic; -- ddr ras
--signal ddrb_casb : std_ulogic; -- ddr cas
--signal ddrb_ad : std_logic_vector (15 downto 0); -- ddr address
--signal ddrb_ba : std_logic_vector (2 downto 0); -- ddr bank address
--signal ddrab_clk : std_logic_vector(1 downto 0);
--signal ddrab_clkb : std_logic_vector(1 downto 0);
--signal ddrab_odt : std_logic_vector(1 downto 0);
--signal ddrab_dqsp : std_logic_vector(1 downto 0); -- ddr dqs
--signal ddrab_dqsn : std_logic_vector(1 downto 0); -- ddr dqs
--signal ddrab_dm : std_logic_vector(1 downto 0); -- ddr dm
--signal ddrab_dq : std_logic_vector (15 downto 0);-- ddr data
-- Ethernet
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk125 <= not clk125 after 4 * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
address(0) <= '0';
ddr_dq(71 downto dbits) <= (others => 'H');
ddr_dq2(71 downto dbits) <= (others => 'H');
ddr_dqsp(8 downto dbits/8) <= (others => 'H');
ddr_dqsn(8 downto dbits/8) <= (others => 'H');
ddr_rdqs(8 downto dbits/8) <= (others => 'H');
ddr_dm(8 downto dbits/8) <= (others => 'H');
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow, 50000, dbits)
port map (rst, clk, clk125, error, dsubren, dsuact,
-- rxd1, txd1,
gpio, address(25 downto 1), data, open,
sram_advn, sram_csn, sram_wen, sram_ben, sram_oen, sram_clk, sram_psn, sram_wait,
flash_clk, flash_advn, flash_cen, flash_oen, flash_resetn, flash_wen,
max_csn, iosn,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_odt, ddr_web,
ddr_rasb, ddr_casb, ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq,
open, open,
-- ddra_cke, ddra_csb, ddra_web, ddra_rasb, ddra_casb, ddra_ad(14 downto 0), ddra_ba, ddrb_cke,
-- ddrb_csb, ddrb_web, ddrb_rasb, ddrb_casb, ddrb_ad(14 downto 0), ddrb_ba, ddrab_clk, ddrab_clkb,
-- ddrab_odt, ddrab_dqsp, ddrab_dqsn, ddrab_dm, ddrab_dq,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n
);
ddr2delay : delay_wire
generic map(data_width => dbits, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => ddr_dq(dbits-1 downto 0), b => ddr_dq2(dbits-1 downto 0));
ddr2mem : for i in 0 to dbits/16-1 generate
u1 : HY5PS121621F
generic map (TimingCheckFlag => true, PUSCheckFlag => false,
index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i,
fname => sdramfile, bbits => CFG_DDR2SP_DATAWIDTH)
PORT MAP(
clk => ddr_clk(0), clkb => ddr_clkb(0), cke => ddr_cke(0),
csb => ddr_csb(0), rasb => ddr_rasb, casb => ddr_casb, web => ddr_web,
LDM => ddr_dm(i*2), UDM => ddr_dm(i*2+1), ba => ddr_ba(1 downto 0),
addr => ddr_ad(12 downto 0), dq => ddr_dq2(i*16+15 downto i*16),
LDQS => ddr_dqsp(i*2), LDQSB => ddr_dqsn(i*2), UDQS => ddr_dqsp(i*2+1),
UDQSB => ddr_dqsn(i*2+1));
end generate;
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31 downto 16),
gnd, gnd, flash_cen, flash_wen, flash_oen);
-- -- 32 bit prom
-- prom0 : for i in 0 to 3 generate
-- sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
-- port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), flash_cen,
-- flash_wen, flash_oen);
-- end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), sram_csn,
sram_wen, sram_oen);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, sram_oen, sram_wen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
-------------------------------------------------------------------------------
-- axi_vdma_mm2s_axis_dwidth_converter
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_mm2s_axis_dwidth_converter.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
entity axi_vdma_mm2s_axis_dwidth_converter is
generic ( C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED : integer := 32;
C_M_AXIS_MM2S_TDATA_WIDTH : integer := 32;
C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 : integer := 4;
C_MM2S_SOF_ENABLE : integer range 0 to 1 := 0;
ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ;
C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 : integer := 4;
-- C_AXIS_SIGNAL_SET : integer := 255;
C_AXIS_TID_WIDTH : integer := 1;
C_AXIS_TDEST_WIDTH : integer := 1;
C_FAMILY : string := "virtex7" );
port (
ACLK :in std_logic;
ARESETN :in std_logic;
ACLKEN :in std_logic;
mm2s_vsize_cntr_clr_flag : in std_logic ;
fsync_out : in std_logic ;
dwidth_fifo_pipe_empty : out std_logic ;
all_lines_xfred_s_dwidth : out std_logic ;
stop_reg : in std_logic ;
dm_halt_reg : in std_logic ;
crnt_vsize_d2 : in std_logic_vector(VSIZE_DWIDTH-1 downto 0) ;
S_AXIS_TVALID :in std_logic;
S_AXIS_TREADY :out std_logic;
S_AXIS_TDATA :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0);
S_AXIS_TSTRB :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0);
S_AXIS_TKEEP :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0);
S_AXIS_TLAST :in std_logic;
S_AXIS_TID :in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0);
S_AXIS_TDEST :in std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0);
S_AXIS_TUSER :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0);
M_AXIS_TVALID :out std_logic;
M_AXIS_TREADY :in std_logic;
M_AXIS_TDATA :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
M_AXIS_TSTRB :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0);
M_AXIS_TKEEP :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0);
M_AXIS_TLAST :out std_logic;
M_AXIS_TID :out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0);
M_AXIS_TDEST :out std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0);
M_AXIS_TUSER :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0)
);
end axi_vdma_mm2s_axis_dwidth_converter;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_mm2s_axis_dwidth_converter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant ZERO_VALUE : std_logic_vector(255 downto 0)
:= (others => '0');
-- Constants for line tracking logic
constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,VSIZE_DWIDTH));
constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Verilog module component declarations
-------------------------------------------------------------------------------
component axi_vdma_v6_2_axis_dwidth_converter_v1_0_axis_dwidth_converter is
generic ( C_S_AXIS_TDATA_WIDTH : integer := 32;
C_M_AXIS_TDATA_WIDTH : integer := 32;
C_AXIS_TID_WIDTH : integer := 1;
C_AXIS_TDEST_WIDTH : integer := 1;
C_S_AXIS_TUSER_WIDTH : integer := 4;
C_M_AXIS_TUSER_WIDTH : integer := 4;
--C_AXIS_SIGNAL_SET : integer := 255;
C_FAMILY : string := "virtex7" );
port (
ACLK :in std_logic;
ARESETN :in std_logic;
ACLKEN :in std_logic;
S_AXIS_TVALID :in std_logic;
S_AXIS_TREADY :out std_logic;
S_AXIS_TDATA :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0);
S_AXIS_TSTRB :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0);
S_AXIS_TKEEP :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0);
S_AXIS_TLAST :in std_logic;
S_AXIS_TID :in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0);
S_AXIS_TDEST :in std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0);
S_AXIS_TUSER :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0);
M_AXIS_TVALID :out std_logic;
M_AXIS_TREADY :in std_logic;
M_AXIS_TDATA :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
M_AXIS_TSTRB :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0);
M_AXIS_TKEEP :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0);
M_AXIS_TLAST :out std_logic;
M_AXIS_TID :out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0);
M_AXIS_TDEST :out std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0);
M_AXIS_TUSER :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0)
);
end component;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal M_AXIS_TREADY_D1 : std_logic := '0';
signal M_AXIS_TLAST_D1 : std_logic := '0';
signal M_AXIS_TVALID_D1 : std_logic := '0';
signal M_AXIS_TVALID_OUT : std_logic := '0';
signal M_AXIS_TLAST_OUT : std_logic := '0';
signal vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal all_lines_xfred : std_logic := '0';
--signal crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal decr_vcount : std_logic := '0';
--signal fifo_pipe_empty : std_logic := '0'
--signal stop_reg : std_logic := '0'
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
GEN_DWIDTH_NO_SOF : if ENABLE_FLUSH_ON_FSYNC = 0 or C_MM2S_SOF_ENABLE = 0 generate
begin
all_lines_xfred_s_dwidth <= all_lines_xfred;
-- Pass out of core
M_AXIS_TVALID <= M_AXIS_TVALID_OUT;
M_AXIS_TLAST <= M_AXIS_TLAST_OUT;
MM2S_AXIS_DWIDTH_CONVERTER_I : axi_vdma_v6_2_axis_dwidth_converter_v1_0_axis_dwidth_converter
generic map( C_S_AXIS_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED ,
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_AXIS_TID_WIDTH => C_AXIS_TID_WIDTH ,
C_S_AXIS_TUSER_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 ,
C_M_AXIS_TUSER_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 ,
C_AXIS_TDEST_WIDTH => C_AXIS_TDEST_WIDTH ,
--C_AXIS_SIGNAL_SET => C_AXIS_SIGNAL_SET ,
C_FAMILY => C_FAMILY )
port map(
ACLK => ACLK ,
ARESETN => ARESETN ,
ACLKEN => ACLKEN ,
S_AXIS_TVALID => S_AXIS_TVALID ,
S_AXIS_TREADY => S_AXIS_TREADY ,
S_AXIS_TDATA => S_AXIS_TDATA(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0) ,
S_AXIS_TSTRB => S_AXIS_TSTRB(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
S_AXIS_TKEEP => S_AXIS_TKEEP(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
S_AXIS_TLAST => S_AXIS_TLAST ,
S_AXIS_TID => S_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) ,
S_AXIS_TDEST => S_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) ,
S_AXIS_TUSER => S_AXIS_TUSER(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) ,
M_AXIS_TVALID => M_AXIS_TVALID_OUT ,
M_AXIS_TREADY => M_AXIS_TREADY ,
M_AXIS_TDATA => M_AXIS_TDATA(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0) ,
M_AXIS_TSTRB => M_AXIS_TSTRB(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0) ,
M_AXIS_TKEEP => M_AXIS_TKEEP(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0) ,
M_AXIS_TLAST => M_AXIS_TLAST_OUT ,
M_AXIS_TID => M_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) ,
M_AXIS_TDEST => M_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) ,
M_AXIS_TUSER => M_AXIS_TUSER(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0)
);
-- Register to break long timing paths for use in
-- transfer complete generation
DWIDTH_REG_STRM_SIGS : process(ACLK)
begin
if(ACLK'EVENT and ACLK = '1')then
if(ARESETN = '0')then
M_AXIS_TLAST_D1 <= '0';
M_AXIS_TVALID_D1 <= '0';
M_AXIS_TREADY_D1 <= '0';
else
M_AXIS_TLAST_D1 <= M_AXIS_TLAST_OUT;
M_AXIS_TVALID_D1 <= M_AXIS_TVALID_OUT;
M_AXIS_TREADY_D1 <= M_AXIS_TREADY;
end if;
end if;
end process DWIDTH_REG_STRM_SIGS;
--*****************************************************************************
--** Vertical Line Tracking
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when M_AXIS_TLAST_D1 = '1'
and M_AXIS_TVALID_D1 = '1'
and M_AXIS_TREADY_D1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
DWIDTH_VERT_COUNTER : process(ACLK)
begin
if(ACLK'EVENT and ACLK = '1')then
if(ARESETN = '0' and fsync_out = '0')then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred <= '0';
end if;
end if;
end process DWIDTH_VERT_COUNTER;
dwidth_fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and M_AXIS_TVALID_OUT = '0') -- All data for frame transmitted
or dm_halt_reg = '1' -- Commanded to Halt
else '0';
end generate GEN_DWIDTH_NO_SOF;
GEN_DWIDTH_SOF : if ENABLE_FLUSH_ON_FSYNC = 1 and C_MM2S_SOF_ENABLE = 1 generate
begin
-- Pass out of core
M_AXIS_TVALID <= M_AXIS_TVALID_OUT;
M_AXIS_TLAST <= M_AXIS_TLAST_OUT;
all_lines_xfred_s_dwidth <= all_lines_xfred;
MM2S_AXIS_DWIDTH_CONVERTER_I : axi_vdma_v6_2_axis_dwidth_converter_v1_0_axis_dwidth_converter
generic map( C_S_AXIS_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED ,
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_AXIS_TID_WIDTH => C_AXIS_TID_WIDTH ,
C_S_AXIS_TUSER_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 ,
C_M_AXIS_TUSER_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 ,
C_AXIS_TDEST_WIDTH => C_AXIS_TDEST_WIDTH ,
--C_AXIS_SIGNAL_SET => C_AXIS_SIGNAL_SET ,
C_FAMILY => C_FAMILY )
port map(
ACLK => ACLK ,
ARESETN => ARESETN ,
ACLKEN => ACLKEN ,
S_AXIS_TVALID => S_AXIS_TVALID ,
S_AXIS_TREADY => S_AXIS_TREADY ,
S_AXIS_TDATA => S_AXIS_TDATA(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0) ,
S_AXIS_TSTRB => S_AXIS_TSTRB(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
S_AXIS_TKEEP => S_AXIS_TKEEP(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
S_AXIS_TLAST => S_AXIS_TLAST ,
S_AXIS_TID => S_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) ,
S_AXIS_TDEST => S_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) ,
S_AXIS_TUSER => S_AXIS_TUSER(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) ,
M_AXIS_TVALID => M_AXIS_TVALID_OUT ,
M_AXIS_TREADY => M_AXIS_TREADY ,
M_AXIS_TDATA => M_AXIS_TDATA(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0) ,
M_AXIS_TSTRB => M_AXIS_TSTRB(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0) ,
M_AXIS_TKEEP => M_AXIS_TKEEP(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0) ,
M_AXIS_TLAST => M_AXIS_TLAST_OUT ,
M_AXIS_TID => M_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) ,
M_AXIS_TDEST => M_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) ,
M_AXIS_TUSER => M_AXIS_TUSER(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0)
);
-- Register to break long timing paths for use in
-- transfer complete generation
DWIDTH_REG_STRM_SIGS : process(ACLK)
begin
if(ACLK'EVENT and ACLK = '1')then
if(ARESETN = '0')then
M_AXIS_TLAST_D1 <= '0';
M_AXIS_TVALID_D1 <= '0';
M_AXIS_TREADY_D1 <= '0';
else
M_AXIS_TLAST_D1 <= M_AXIS_TLAST_OUT;
M_AXIS_TVALID_D1 <= M_AXIS_TVALID_OUT;
M_AXIS_TREADY_D1 <= M_AXIS_TREADY;
end if;
end if;
end process DWIDTH_REG_STRM_SIGS;
--*****************************************************************************
--** Vertical Line Tracking
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when M_AXIS_TLAST_D1 = '1'
and M_AXIS_TVALID_D1 = '1'
and M_AXIS_TREADY_D1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
DWIDTH_VERT_COUNTER : process(ACLK)
begin
if(ACLK'EVENT and ACLK = '1')then
if((ARESETN = '0' and fsync_out = '0') or mm2s_vsize_cntr_clr_flag = '1')then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred <= '0';
end if;
end if;
end process DWIDTH_VERT_COUNTER;
dwidth_fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and M_AXIS_TVALID_OUT = '0') -- All data for frame transmitted
or dm_halt_reg = '1' -- Commanded to Halt
else '0';
end generate GEN_DWIDTH_SOF;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_mm2s_axis_dwidth_converter
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_mm2s_axis_dwidth_converter.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
entity axi_vdma_mm2s_axis_dwidth_converter is
generic ( C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED : integer := 32;
C_M_AXIS_MM2S_TDATA_WIDTH : integer := 32;
C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 : integer := 4;
C_MM2S_SOF_ENABLE : integer range 0 to 1 := 0;
ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ;
C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 : integer := 4;
-- C_AXIS_SIGNAL_SET : integer := 255;
C_AXIS_TID_WIDTH : integer := 1;
C_AXIS_TDEST_WIDTH : integer := 1;
C_FAMILY : string := "virtex7" );
port (
ACLK :in std_logic;
ARESETN :in std_logic;
ACLKEN :in std_logic;
mm2s_vsize_cntr_clr_flag : in std_logic ;
fsync_out : in std_logic ;
dwidth_fifo_pipe_empty : out std_logic ;
all_lines_xfred_s_dwidth : out std_logic ;
stop_reg : in std_logic ;
dm_halt_reg : in std_logic ;
crnt_vsize_d2 : in std_logic_vector(VSIZE_DWIDTH-1 downto 0) ;
S_AXIS_TVALID :in std_logic;
S_AXIS_TREADY :out std_logic;
S_AXIS_TDATA :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0);
S_AXIS_TSTRB :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0);
S_AXIS_TKEEP :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0);
S_AXIS_TLAST :in std_logic;
S_AXIS_TID :in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0);
S_AXIS_TDEST :in std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0);
S_AXIS_TUSER :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0);
M_AXIS_TVALID :out std_logic;
M_AXIS_TREADY :in std_logic;
M_AXIS_TDATA :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
M_AXIS_TSTRB :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0);
M_AXIS_TKEEP :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0);
M_AXIS_TLAST :out std_logic;
M_AXIS_TID :out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0);
M_AXIS_TDEST :out std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0);
M_AXIS_TUSER :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0)
);
end axi_vdma_mm2s_axis_dwidth_converter;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_mm2s_axis_dwidth_converter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant ZERO_VALUE : std_logic_vector(255 downto 0)
:= (others => '0');
-- Constants for line tracking logic
constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,VSIZE_DWIDTH));
constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Verilog module component declarations
-------------------------------------------------------------------------------
component axi_vdma_v6_2_axis_dwidth_converter_v1_0_axis_dwidth_converter is
generic ( C_S_AXIS_TDATA_WIDTH : integer := 32;
C_M_AXIS_TDATA_WIDTH : integer := 32;
C_AXIS_TID_WIDTH : integer := 1;
C_AXIS_TDEST_WIDTH : integer := 1;
C_S_AXIS_TUSER_WIDTH : integer := 4;
C_M_AXIS_TUSER_WIDTH : integer := 4;
--C_AXIS_SIGNAL_SET : integer := 255;
C_FAMILY : string := "virtex7" );
port (
ACLK :in std_logic;
ARESETN :in std_logic;
ACLKEN :in std_logic;
S_AXIS_TVALID :in std_logic;
S_AXIS_TREADY :out std_logic;
S_AXIS_TDATA :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0);
S_AXIS_TSTRB :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0);
S_AXIS_TKEEP :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0);
S_AXIS_TLAST :in std_logic;
S_AXIS_TID :in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0);
S_AXIS_TDEST :in std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0);
S_AXIS_TUSER :in std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0);
M_AXIS_TVALID :out std_logic;
M_AXIS_TREADY :in std_logic;
M_AXIS_TDATA :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
M_AXIS_TSTRB :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0);
M_AXIS_TKEEP :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0);
M_AXIS_TLAST :out std_logic;
M_AXIS_TID :out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0);
M_AXIS_TDEST :out std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0);
M_AXIS_TUSER :out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0)
);
end component;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal M_AXIS_TREADY_D1 : std_logic := '0';
signal M_AXIS_TLAST_D1 : std_logic := '0';
signal M_AXIS_TVALID_D1 : std_logic := '0';
signal M_AXIS_TVALID_OUT : std_logic := '0';
signal M_AXIS_TLAST_OUT : std_logic := '0';
signal vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal all_lines_xfred : std_logic := '0';
--signal crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal decr_vcount : std_logic := '0';
--signal fifo_pipe_empty : std_logic := '0'
--signal stop_reg : std_logic := '0'
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
GEN_DWIDTH_NO_SOF : if ENABLE_FLUSH_ON_FSYNC = 0 or C_MM2S_SOF_ENABLE = 0 generate
begin
all_lines_xfred_s_dwidth <= all_lines_xfred;
-- Pass out of core
M_AXIS_TVALID <= M_AXIS_TVALID_OUT;
M_AXIS_TLAST <= M_AXIS_TLAST_OUT;
MM2S_AXIS_DWIDTH_CONVERTER_I : axi_vdma_v6_2_axis_dwidth_converter_v1_0_axis_dwidth_converter
generic map( C_S_AXIS_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED ,
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_AXIS_TID_WIDTH => C_AXIS_TID_WIDTH ,
C_S_AXIS_TUSER_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 ,
C_M_AXIS_TUSER_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 ,
C_AXIS_TDEST_WIDTH => C_AXIS_TDEST_WIDTH ,
--C_AXIS_SIGNAL_SET => C_AXIS_SIGNAL_SET ,
C_FAMILY => C_FAMILY )
port map(
ACLK => ACLK ,
ARESETN => ARESETN ,
ACLKEN => ACLKEN ,
S_AXIS_TVALID => S_AXIS_TVALID ,
S_AXIS_TREADY => S_AXIS_TREADY ,
S_AXIS_TDATA => S_AXIS_TDATA(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0) ,
S_AXIS_TSTRB => S_AXIS_TSTRB(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
S_AXIS_TKEEP => S_AXIS_TKEEP(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
S_AXIS_TLAST => S_AXIS_TLAST ,
S_AXIS_TID => S_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) ,
S_AXIS_TDEST => S_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) ,
S_AXIS_TUSER => S_AXIS_TUSER(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) ,
M_AXIS_TVALID => M_AXIS_TVALID_OUT ,
M_AXIS_TREADY => M_AXIS_TREADY ,
M_AXIS_TDATA => M_AXIS_TDATA(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0) ,
M_AXIS_TSTRB => M_AXIS_TSTRB(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0) ,
M_AXIS_TKEEP => M_AXIS_TKEEP(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0) ,
M_AXIS_TLAST => M_AXIS_TLAST_OUT ,
M_AXIS_TID => M_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) ,
M_AXIS_TDEST => M_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) ,
M_AXIS_TUSER => M_AXIS_TUSER(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0)
);
-- Register to break long timing paths for use in
-- transfer complete generation
DWIDTH_REG_STRM_SIGS : process(ACLK)
begin
if(ACLK'EVENT and ACLK = '1')then
if(ARESETN = '0')then
M_AXIS_TLAST_D1 <= '0';
M_AXIS_TVALID_D1 <= '0';
M_AXIS_TREADY_D1 <= '0';
else
M_AXIS_TLAST_D1 <= M_AXIS_TLAST_OUT;
M_AXIS_TVALID_D1 <= M_AXIS_TVALID_OUT;
M_AXIS_TREADY_D1 <= M_AXIS_TREADY;
end if;
end if;
end process DWIDTH_REG_STRM_SIGS;
--*****************************************************************************
--** Vertical Line Tracking
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when M_AXIS_TLAST_D1 = '1'
and M_AXIS_TVALID_D1 = '1'
and M_AXIS_TREADY_D1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
DWIDTH_VERT_COUNTER : process(ACLK)
begin
if(ACLK'EVENT and ACLK = '1')then
if(ARESETN = '0' and fsync_out = '0')then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred <= '0';
end if;
end if;
end process DWIDTH_VERT_COUNTER;
dwidth_fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and M_AXIS_TVALID_OUT = '0') -- All data for frame transmitted
or dm_halt_reg = '1' -- Commanded to Halt
else '0';
end generate GEN_DWIDTH_NO_SOF;
GEN_DWIDTH_SOF : if ENABLE_FLUSH_ON_FSYNC = 1 and C_MM2S_SOF_ENABLE = 1 generate
begin
-- Pass out of core
M_AXIS_TVALID <= M_AXIS_TVALID_OUT;
M_AXIS_TLAST <= M_AXIS_TLAST_OUT;
all_lines_xfred_s_dwidth <= all_lines_xfred;
MM2S_AXIS_DWIDTH_CONVERTER_I : axi_vdma_v6_2_axis_dwidth_converter_v1_0_axis_dwidth_converter
generic map( C_S_AXIS_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED ,
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_AXIS_TID_WIDTH => C_AXIS_TID_WIDTH ,
C_S_AXIS_TUSER_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 ,
C_M_AXIS_TUSER_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 ,
C_AXIS_TDEST_WIDTH => C_AXIS_TDEST_WIDTH ,
--C_AXIS_SIGNAL_SET => C_AXIS_SIGNAL_SET ,
C_FAMILY => C_FAMILY )
port map(
ACLK => ACLK ,
ARESETN => ARESETN ,
ACLKEN => ACLKEN ,
S_AXIS_TVALID => S_AXIS_TVALID ,
S_AXIS_TREADY => S_AXIS_TREADY ,
S_AXIS_TDATA => S_AXIS_TDATA(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0) ,
S_AXIS_TSTRB => S_AXIS_TSTRB(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
S_AXIS_TKEEP => S_AXIS_TKEEP(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
S_AXIS_TLAST => S_AXIS_TLAST ,
S_AXIS_TID => S_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) ,
S_AXIS_TDEST => S_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) ,
S_AXIS_TUSER => S_AXIS_TUSER(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) ,
M_AXIS_TVALID => M_AXIS_TVALID_OUT ,
M_AXIS_TREADY => M_AXIS_TREADY ,
M_AXIS_TDATA => M_AXIS_TDATA(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0) ,
M_AXIS_TSTRB => M_AXIS_TSTRB(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0) ,
M_AXIS_TKEEP => M_AXIS_TKEEP(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0) ,
M_AXIS_TLAST => M_AXIS_TLAST_OUT ,
M_AXIS_TID => M_AXIS_TID(C_AXIS_TID_WIDTH-1 downto 0) ,
M_AXIS_TDEST => M_AXIS_TDEST(C_AXIS_TDEST_WIDTH-1 downto 0) ,
M_AXIS_TUSER => M_AXIS_TUSER(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0)
);
-- Register to break long timing paths for use in
-- transfer complete generation
DWIDTH_REG_STRM_SIGS : process(ACLK)
begin
if(ACLK'EVENT and ACLK = '1')then
if(ARESETN = '0')then
M_AXIS_TLAST_D1 <= '0';
M_AXIS_TVALID_D1 <= '0';
M_AXIS_TREADY_D1 <= '0';
else
M_AXIS_TLAST_D1 <= M_AXIS_TLAST_OUT;
M_AXIS_TVALID_D1 <= M_AXIS_TVALID_OUT;
M_AXIS_TREADY_D1 <= M_AXIS_TREADY;
end if;
end if;
end process DWIDTH_REG_STRM_SIGS;
--*****************************************************************************
--** Vertical Line Tracking
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when M_AXIS_TLAST_D1 = '1'
and M_AXIS_TVALID_D1 = '1'
and M_AXIS_TREADY_D1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
DWIDTH_VERT_COUNTER : process(ACLK)
begin
if(ACLK'EVENT and ACLK = '1')then
if((ARESETN = '0' and fsync_out = '0') or mm2s_vsize_cntr_clr_flag = '1')then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred <= '0';
end if;
end if;
end process DWIDTH_VERT_COUNTER;
dwidth_fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and M_AXIS_TVALID_OUT = '0') -- All data for frame transmitted
or dm_halt_reg = '1' -- Commanded to Halt
else '0';
end generate GEN_DWIDTH_SOF;
end implementation;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-e.vhd,v 1.1 2007/03/05 08:58:59 wig Exp $
-- $Date: 2007/03/05 08:58:59 $
-- $Log: inst_t_e-e.vhd,v $
-- Revision 1.1 2007/03/05 08:58:59 wig
-- Upgraded testcases
-- case/force still not fully operational (internal names keep case).
--
-- Revision 1.2 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_t_e
--
entity inst_t_e is
-- Generics:
-- No Generated Generics for Entity inst_t_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_t_e
end inst_t_e;
--
-- End of Generated Entity inst_t_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.koc_lock_pack.all;
entity koc_lock_axi4_write_cntrl is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_control_default : std_logic_vector := X"00000001"
);
port (
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
reg_control : out std_logic_vector(axi_data_width-1 downto 0)
);
end koc_lock_axi4_write_cntrl;
architecture Behavioral of koc_lock_axi4_write_cntrl is
type state_type is (state_wait,state_write,state_response);
signal state : state_type := state_wait;
signal axi_awready_buff : std_logic := '0';
signal axi_awaddr_buff : std_logic_vector(axi_address_width-1 downto 0);
signal axi_wready_buff : std_logic := '0';
signal axi_bvalid_buff : std_logic := '0';
signal reg_control_buff : std_logic_vector(axi_data_width-1 downto 0) := reg_control_default;
begin
axi_awready <= axi_awready_buff;
axi_wready <= axi_wready_buff;
axi_bvalid <= axi_bvalid_buff;
axi_bresp <= axi_resp_okay;
reg_control <= reg_control_buff;
-- Drive the axi write interface.
process (aclk)
variable reg_control_var : std_logic_vector(axi_data_width-1 downto 0);
begin
-- Perform operations on the clock's positive edge.
if rising_edge(aclk) then
if aresetn='0' then
axi_awready_buff <= '0';
axi_wready_buff <= '0';
axi_bvalid_buff <= '0';
reg_control_buff <= reg_control_default;
state <= state_wait;
else
case state is
when state_wait=>
if axi_awvalid='1' and axi_awready_buff='1' then
axi_awready_buff <= '0';
axi_awaddr_buff <= axi_awaddr;
axi_wready_buff <= '1';
state <= state_write;
else
axi_awready_buff <= '1';
end if;
when state_write=>
if axi_wvalid='1' and axi_wready_buff='1' then
axi_wready_buff <= '0';
-- Determine control value from device requesting lock.
reg_control_var := (others=>'0');
for each_byte in 0 to axi_data_width/8-1 loop
if axi_awaddr_buff=reg_control_offset and axi_wstrb(each_byte)='1' then
reg_control_var(7+each_byte*8 downto each_byte*8) :=
axi_wdata(7+each_byte*8 downto each_byte*8);
end if;
end loop;
-- Perform lock if lock is available, or release it.
if reg_control_buff=reg_control_var then
reg_control_buff <= (others=>'0');
elsif reg_control_buff=std_logic_vector(to_unsigned(0,axi_data_width)) then
reg_control_buff <= reg_control_var;
end if;
state <= state_response;
axi_bvalid_buff <= '1';
end if;
when state_response=>
if axi_bvalid_buff='1' and axi_bready='1' then
axi_bvalid_buff <= '0';
state <= state_wait;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\CPU_Subsystem_8_bit_pkg.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE CPU_Subsystem_8_bit_pkg IS
TYPE vector_of_unsigned12 IS ARRAY (NATURAL RANGE <>) OF unsigned(11 DOWNTO 0);
END CPU_Subsystem_8_bit_pkg;
|
-------------------------------------------------------------------------------
-- sng_port_arb.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: sng_port_arb.vhd
--
-- Description: This file is the top level arbiter for full AXI4 mode
-- when configured in a single port mode to BRAM.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add input signal, AW2Arb_BVALID_Cnt, from wr_chnl. For configurations
-- when WREADY is to be a registered output. With a seperate FIFO for BID,
-- ensure arbitration does not get more than 8 ahead of BID responses. A
-- value of 8 is the max of the BVALID counter.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
------------------------------------------------------------------------------
entity sng_port_arb is
generic (
C_S_AXI_ADDR_WIDTH : integer := 32
-- Width of AXI address bus (in bits)
);
port (
-- *** AXI Clock and Reset ***
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic := '0';
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic := '0';
-- *** Write Channel Interface Signals ***
Arb2AW_Active : out std_logic := '0';
AW2Arb_Busy : in std_logic;
AW2Arb_Active_Clr : in std_logic;
AW2Arb_BVALID_Cnt : in std_logic_vector (2 downto 0);
-- *** Read Channel Interface Signals ***
Arb2AR_Active : out std_logic := '0';
AR2Arb_Active_Clr : in std_logic
);
end entity sng_port_arb;
-------------------------------------------------------------------------------
architecture implementation of sng_port_arb is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant ARB_WR : std_logic := '0';
constant ARB_RD : std_logic := '1';
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type ARB_SM_TYPE is ( IDLE,
RD_DATA,
WR_DATA
);
signal arb_sm_cs, arb_sm_ns : ARB_SM_TYPE;
signal axi_awready_cmb : std_logic := '0';
signal axi_awready_int : std_logic := '0';
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal last_arb_won_cmb : std_logic := '0';
signal last_arb_won : std_logic := '0';
signal aw_active_cmb : std_logic := '0';
signal aw_active : std_logic := '0';
signal ar_active_cmb : std_logic := '0';
signal ar_active : std_logic := '0';
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
AXI_AWREADY <= axi_awready_int;
-- AXI Read Address Channel Output Signals
AXI_ARREADY <= axi_arready_int;
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** Internal Arbitration Interface ***
---------------------------------------------------------------------------
Arb2AW_Active <= aw_active;
Arb2AR_Active <= ar_active;
---------------------------------------------------------------------------
-- Main Arb State Machine
--
-- Description: Main arbitration logic when AXI BRAM controller
-- configured in a single port BRAM mode.
-- Module is instantiated when C_SINGLE_PORT_BRAM = 1.
--
-- Outputs: last_arb_won Registered
-- aw_active Registered
-- ar_active Registered
-- axi_awready_int Registered
-- axi_arready_int Registered
--
--
-- ARB_SM_CMB_PROCESS: Combinational process to determine next state.
-- ARB_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
ARB_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_ARVALID,
AW2Arb_BVALID_Cnt,
AW2Arb_Busy,
AW2Arb_Active_Clr,
AR2Arb_Active_Clr,
last_arb_won,
aw_active,
ar_active,
arb_sm_cs )
begin
-- assign default values for state machine outputs
arb_sm_ns <= arb_sm_cs;
axi_awready_cmb <= '0';
axi_arready_cmb <= '0';
last_arb_won_cmb <= last_arb_won;
aw_active_cmb <= aw_active;
ar_active_cmb <= ar_active;
case arb_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Check for valid read operation
-- Reads take priority over AW traffic (if both asserted)
-- 4/11
-- if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or
-- ((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- 4/11
-- Add BVALID counter to AW arbitration.
-- Since this is arbitration to read, no need for BVALID counter.
if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or -- and
--(AW2Arb_BVALID_Cnt /= "111")) or
((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
-- 4/11 elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
end if;
------------------------- WR_DATA State -------------------------
when WR_DATA =>
-- Wait for write operation to complete
if (AW2Arb_Active_Clr = '1') then
aw_active_cmb <= '0';
-- Check early for pending read (to save clock cycle
-- in transitioning back to IDLE)
if (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Note: if timing paths occur b/w wr_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a read operation.
else
arb_sm_ns <= IDLE;
end if;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Wait for read operation to complete
if (AR2Arb_Active_Clr = '1') then
ar_active_cmb <= '0';
-- Check early for pending write operation (to save clock cycle
-- in transitioning back to IDLE)
-- 4/11 if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
-- Note: if timing paths occur b/w rd_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a write operation.
-- Check early for a pending back-to-back read operation
elsif (AXI_AWVALID = '0') and (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
else
arb_sm_ns <= IDLE;
end if;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
arb_sm_ns <= IDLE;
--coverage on
end case;
end process ARB_SM_CMB_PROCESS;
---------------------------------------------------------------------------
ARB_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
arb_sm_cs <= IDLE;
last_arb_won <= ARB_WR;
aw_active <= '0';
ar_active <= '0';
axi_awready_int <='0';
axi_arready_int <='0';
else
arb_sm_cs <= arb_sm_ns;
last_arb_won <= last_arb_won_cmb;
aw_active <= aw_active_cmb;
ar_active <= ar_active_cmb;
axi_awready_int <= axi_awready_cmb;
axi_arready_int <= axi_arready_cmb;
end if;
end if;
end process ARB_SM_REG_PROCESS;
---------------------------------------------------------------------------
end architecture implementation;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity SCIT4 is
port (
A, B : in std_logic_vector ( 3 downto 0 );
Cin : in std_logic;
S : out std_logic_vector ( 4 downto 0 )
);
end entity SCIT4;
architecture SCIT4_BODY of SCIT4 is
signal C : std_logic_vector ( 4 downto 0 );
begin
-- VSTUP : process (Cin)
-- begin
-- C(0) <= Cin;
-- end process VSTUP;
SCITANI : process ( C, A, B, Cin )
begin
C(0) <= Cin;
for I in 0 to 3 loop
S(I) <= A(I) xor B(I) xor C(I) after 2 ns;
C(I+1) <= ( A(I) and B(I) ) or ( A(I) and C(I) ) or ( B(I) and C(I) ) after 2 ns;
end loop;
S(4) <= C(4);
end process SCITANI;
-- VYSTUP : process (C(4))
-- begin
-- S(4) <= C(4);
-- end process VYSTUP;
end architecture SCIT4_BODY;
|
-- Project: VHDL to Verilog RTL translation
-- Revision: 1.0
-- Date of last Revision: February 27 2001
-- Designer: Vincenzo Liguori
-- vhd2vl test file
-- This VHDL file exercises vhd2vl
LIBRARY IEEE;
USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
entity test is port(
-- Inputs
clk, rstn : in std_logic;
en, start_dec : in std_logic;
addr : in std_logic_vector(2 downto 0);
din : in std_logic_vector(25 downto 0);
we : in std_logic;
pixel_in : in std_logic_vector(7 downto 0);
pix_req : in std_logic;
config, bip : in std_logic;
a, b : in std_logic_vector(7 downto 0);
c, load : in std_logic_vector(7 downto 0);
pack : in std_logic_vector(6 downto 0);
base : in std_logic_vector(2 downto 0);
qtd : in std_logic_vector(21 downto 0);
-- Outputs
dout : out std_logic_vector(25 downto 0);
pixel_out : out std_logic_vector(7 downto 0);
pixel_valid : out std_logic;
code : out std_logic_vector(9 downto 0);
code1 : out std_logic_vector(9 downto 0);
complex : out std_logic_vector(23 downto 0);
eno : out std_logic
);
end test;
architecture rtl of test is
-- Components declarations are ignored by vhd2vl
-- but they are still parsed
component dsp port(
-- Inputs
clk, rstn : in std_logic;
en, start : in std_logic;
param : in std_logic_vector(7 downto 0);
addr : in std_logic_vector(2 downto 0);
din : in std_logic_vector(25 downto 0);
we : in std_logic;
memdin : out std_logic_vector(13 downto 0);
-- Outputs
dout : out std_logic_vector(25 downto 0);
memaddr : out std_logic_vector(5 downto 0);
memdout : out std_logic_vector(13 downto 0)
);
end component;
component mem port(
-- Inputs
clk, rstn : in std_logic;
en : in std_logic;
cs : in std_logic;
addr : in std_logic_vector(5 downto 0);
din : in std_logic_vector(13 downto 0);
-- Outputs
dout : out std_logic_vector(13 downto 0)
);
end component;
type state is (red, green, blue, yellow);
signal status : state;
constant PARAM1 : std_logic_vector(7 downto 0):="01101101";
constant PARAM2 : std_logic_vector(7 downto 0):="11001101";
constant PARAM3 : std_logic_vector(7 downto 0):="00010111";
signal param : std_logic_vector(7 downto 0);
signal selection : std_logic;
signal start, enf : std_logic; -- Start and enable signals
signal memdin : std_logic_vector(13 downto 0);
signal memaddr : std_logic_vector(5 downto 0);
signal memdout : std_logic_vector(13 downto 0);
signal colour : std_logic_vector(1 downto 0);
begin
param <= PARAM1 when config = '1' else PARAM2 when status = green else PARAM3;
-- Synchronously process
process(clk) begin
if clk'event and clk = '1' then
pixel_out <= pixel_in xor "11001100";
end if;
end process;
-- Synchronous process
process(clk) begin
if rising_edge(clk) then
case status is
when red => colour <= "00";
when green => colour <= "01";
when blue => colour <= "10";
when others => colour <= "11";
end case;
end if;
end process;
-- Synchronous process with asynch reset
process(clk,rstn) begin
if rstn = '0' then
status <= red;
elsif rising_edge(clk) then
case status is
when red =>
if pix_req = '1' then
status <= green;
end if;
when green =>
if a(3) = '1' then
start <= start_dec;
status <= blue;
elsif (b(5) & a(3 downto 2)) = "001" then
status <= yellow;
end if;
when blue =>
status <= yellow;
when others =>
start <= '0';
status <= red;
end case;
end if;
end process;
-- Example of with statement
with memaddr(2 downto 0) select
code(9 downto 2) <= "110" & pack(6 downto 2) when "000" | "110",
"11100010" when "101",
(others => '1') when "010",
(others => '0') when "011",
a + b + '1' when others;
code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6));
-- Asynch process
decode : process(we, addr, config, bip) begin
if we = '1' then
if addr(2 downto 0) = "100" then
selection <= '1';
elsif (b & a) = a & b and bip = '0' then
selection <= config;
else
selection <= '1';
end if;
else
selection <= '0';
end if;
end process decode;
-- Components instantiation
dsp_inst : dsp port map(
-- Inputs
clk => clk,
rstn => rstn,
en => en,
start => start,
param => param,
addr => addr,
din => din,
we => we,
memdin => memdin,
-- Outputs
dout => dout,
memaddr => memaddr,
memdout => memdout
);
dsp_mem : mem port map(
-- Inputs
clk => clk,
rstn => rstn,
en => en,
cs => selection,
addr => memaddr,
din => memdout,
-- Outputs
dout => memdin
);
complex <= enf & ("110" * load) & qtd(3 downto 0) & base & "11001";
enf <= '1' when a = "1101111" + load and c < "1000111" else '0';
eno <= enf;
end rtl;
|
architecture rtl of fifo is
constant AVMM_SLAVE_NULL : t_avmm_slave :=
(
(others => '0'),
'0',
'0'
);
constant cons1 : t_type :=
(
(others => '0'),
(1 => '0', others => '1'),
(others => '0')
);
constant cons2 : t_type :=
(
(others => (valid => '0', data => (others => '0'))),
(others => (1 => '0', (others => '0')))
);
begin
end architecture rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: txreg_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity txreg_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end txreg_exdes;
architecture xilinx of txreg_exdes is
signal clk_i : std_logic;
component txreg is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : txreg
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity tb_05_03 is
end entity tb_05_03;
architecture test of tb_05_03 is
signal D, clk, clr, Q : bit := '0';
begin
dut : entity work.edge_triggered_Dff(behavioral)
port map ( D => D, clk => clk, clr => clr,
Q => Q );
stimulus : process is
begin
D <= '1'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
D <= '0'; wait for 10 ns;
clk <= '0'; wait for 10 ns;
D <= '1'; wait for 10 ns;
clr <= '1'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
clr <= '0'; wait for 10 ns;
clk <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity tb_05_03 is
end entity tb_05_03;
architecture test of tb_05_03 is
signal D, clk, clr, Q : bit := '0';
begin
dut : entity work.edge_triggered_Dff(behavioral)
port map ( D => D, clk => clk, clr => clr,
Q => Q );
stimulus : process is
begin
D <= '1'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
D <= '0'; wait for 10 ns;
clk <= '0'; wait for 10 ns;
D <= '1'; wait for 10 ns;
clr <= '1'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
clr <= '0'; wait for 10 ns;
clk <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity tb_05_03 is
end entity tb_05_03;
architecture test of tb_05_03 is
signal D, clk, clr, Q : bit := '0';
begin
dut : entity work.edge_triggered_Dff(behavioral)
port map ( D => D, clk => clk, clr => clr,
Q => Q );
stimulus : process is
begin
D <= '1'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
D <= '0'; wait for 10 ns;
clk <= '0'; wait for 10 ns;
D <= '1'; wait for 10 ns;
clr <= '1'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
clr <= '0'; wait for 10 ns;
clk <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
|
--
---- SPI Module - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: qspi_mode_0_module.vhd
---- Version: v3.0
---- Description: Serial Peripheral Interface (SPI) Module for interfacing
---- with a 32-bit AXI4 Bus.
----
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_spi.
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Author: SK
-- ~~~~~~
-- - First version of axi_quad_spi.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.proc_common_pkg.all;
library unisim;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------:
-- C_SCK_RATIO -- 2, 4, 16, 32, , , , 1024, 2048 SPI
-- clock ratio (16*N), where N=1,2,3...
-- C_SPI_NUM_BITS_REG -- Width of SPI Control register
-- in this module
-- C_NUM_SS_BITS -- Total number of SS-bits
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- OTHER INTERFACE
-- Slave_MODF_strobe -- Slave mode fault strobe
-- MODF_strobe -- Mode fault strobe
-- SR_3_MODF -- Mode fault error flag
-- SR_5_Tx_Empty -- Transmit Empty
-- Control_Reg -- Control Register
-- Slave_Select_Reg -- Slave Select Register
-- Transmit_Data -- Data Transmit Register Interface
-- Receive_Data -- Data Receive Register Interface
-- SPIXfer_done -- SPI transfer done flag
-- DTR_underrun -- DTR underrun generation signal
-- SPI INTERFACE
-- SCK_I -- SPI Bus Clock Input
-- SCK_O_reg -- SPI Bus Clock Output
-- SCK_T -- SPI Bus Clock 3-state Enable
-- (3-state when high)
-- MISO_I -- Master out,Slave in Input
-- MISO_O -- Master out,Slave in Output
-- MISO_T -- Master out,Slave in 3-state Enable
-- MOSI_I -- Master in,Slave out Input
-- MOSI_O -- Master in,Slave out Output
-- MOSI_T -- Master in,Slave out 3-state Enable
-- SPISEL -- Local SPI slave select active low input
-- has to be initialzed to VCC
-- SS_I -- Input of slave select vector
-- of length N input where there are
-- N SPI devices,but not connected
-- SS_O -- One-hot encoded,active low slave select
-- vector of length N ouput
-- SS_T -- Single 3-state control signal for
-- slave select vector of length N
-- (3-state when high)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_mode_0_module is
generic
(
--C_SPI_MODE : integer;
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_USE_STARTUP : integer;
C_SPICR_REG_WIDTH : integer;
C_SUB_FAMILY : string;
C_FIFO_EXIST : integer
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
----------------------
-- Control Reg is 10-bit wide
SPICR_0_LOOP : in std_logic;
SPICR_1_SPE : in std_logic;
SPICR_2_MASTER_N_SLV : in std_logic;
SPICR_3_CPOL : in std_logic;
SPICR_4_CPHA : in std_logic;
SPICR_5_TXFIFO_RST : in std_logic;
SPICR_6_RXFIFO_RST : in std_logic;
SPICR_7_SS : in std_logic;
SPICR_8_TR_INHIBIT : in std_logic;
SPICR_9_LSB : in std_logic;
----------------------
SR_3_MODF : in std_logic;
SR_5_Tx_Empty : in std_logic;
Slave_MODF_strobe : out std_logic;
MODF_strobe : out std_logic;
SPIXfer_done_rd_tx_en: out std_logic;
Slave_Select_Reg : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Receive_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
SPIXfer_done : out std_logic;
DTR_underrun : out std_logic;
SPISEL_pulse_op : out std_logic;
SPISEL_d1_reg : out std_logic;
--SPI Interface
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
MISO_I : in std_logic;
MISO_O : out std_logic;
MISO_T : out std_logic;
MOSI_I : in std_logic;
MOSI_O : out std_logic;
MOSI_T : out std_logic;
SPISEL : in std_logic;
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic;
control_bit_7_8 : in std_logic_vector(0 to 1);
Mst_N_Slv_mode : out std_logic;
Rx_FIFO_Full : in std_logic;
reset_RcFIFO_ptr_to_spi : in std_logic;
DRR_Overrun_reg : out std_logic;
tx_cntr_xfer_done : out std_logic
);
end qspi_mode_0_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of qspi_mode_0_module is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function Declarations
---------------------------------------------------------------------
------------------------
-- spcl_log2 : Performs log2(x) function for value of C_SCK_RATIO > 2
------------------------
function spcl_log2(x : natural) return integer is
variable j : integer := 0;
variable k : integer := 0;
begin
if(C_SCK_RATIO /= 2) then
for i in 0 to 11 loop
if(2**i >= x) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
else
-- coverage off
return 2;
-- coverage on
end if;
end spcl_log2;
-------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal Ratio_Count : std_logic_vector
(0 to (spcl_log2(C_SCK_RATIO))-2);
signal Count : std_logic_vector
(COUNT_WIDTH downto 0)
:= (others => '0');
signal LSB_first : std_logic;
signal Mst_Trans_inhibit : std_logic;
signal Manual_SS_mode : std_logic;
signal CPHA : std_logic;
signal CPOL : std_logic;
signal Mst_N_Slv : std_logic;
signal SPI_En : std_logic;
signal Loop_mode : std_logic;
signal transfer_start : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
signal sck_o_int : std_logic;
signal sck_o_in : std_logic;
signal Count_trigger : std_logic;
signal Count_trigger_d1 : std_logic;
signal Count_trigger_pulse : std_logic;
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal Serial_Dout : std_logic;
signal Serial_Din : std_logic;
signal Shift_Reg : std_logic_vector
(0 to C_NUM_TRANSFER_BITS-1);
signal SS_Asserted : std_logic;
signal SS_Asserted_1dly : std_logic;
signal Allow_Slave_MODF_Strobe : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal Loading_SR_Reg_int : std_logic;
signal sck_i_d1 : std_logic;
signal spisel_d1 : std_logic;
signal spisel_pulse : std_logic;
signal rising_edge_sck_i : std_logic;
signal falling_edge_sck_i : std_logic;
signal edge_sck_i : std_logic;
signal MODF_strobe_int : std_logic;
signal master_tri_state_en_control: std_logic;
signal slave_tri_state_en_control: std_logic;
-- following signals are added for use in variouos clock ratio modes.
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_rising_edge : std_logic;
signal rx_shft_reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
-- added synchronization signals for SPISEL and SCK_I
signal SPISEL_sync : std_logic;
signal SCK_I_sync : std_logic;
-- following register are declared for making data path clear in different modes
signal rx_shft_reg_s : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0110 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal sck_fe1 : std_logic;
signal sck_d21 : std_logic:='0';
signal sck_d11 : std_logic:='0';
signal SCK_O_1 : std_logic:='0';
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal mosi_i_sync : std_logic;
signal miso_i_sync : std_logic;
signal serial_dout_int : std_logic;
--
--attribute IOB : string;
--attribute IOB of SPI_TRISTATE_CONTROL_II : label is "true";
--attribute IOB of SPI_TRISTATE_CONTROL_III : label is "true";
--attribute IOB of SPI_TRISTATE_CONTROL_IV : label is "true";
--attribute IOB of SPI_TRISTATE_CONTROL_V : label is "true";
--attribute IOB of OTHER_RATIO_GENERATE : label is "true";
--attribute IOB of SCK_I_REG : label is "true";
--attribute IOB of SPISEL_REG : label is "true";
signal Mst_Trans_inhibit_d1, Mst_Trans_inhibit_pulse : std_logic;
signal no_slave_selected : std_logic;
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
TRANSFER_OKAY,
TEMP_TRANSFER_OKAY
);
signal spi_cntrl_ps: STATE_TYPE;
signal spi_cntrl_ns: STATE_TYPE;
signal stop_clock_reg : std_logic;
signal stop_clock : std_logic;
signal Rx_FIFO_Full_reg, DRR_Overrun_reg_int : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal SR_5_Tx_Empty_d1 : std_logic;
signal SR_5_Tx_Empty_pulse: std_logic;
signal SR_5_Tx_comeplete_Empty : std_logic;
signal falling_edge_sck_i_d1, rising_edge_sck_i_d1 : std_logic;
signal spisel_d2 : std_logic;
signal xfer_done_fifo_0 : std_logic;
signal rst_xfer_done_fifo_0 : std_logic;
-------------------------------------------------------------------------------
-- Architecture Starts
-------------------------------------------------------------------------------
begin
--------------------------------------------------
LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
-----------------------------------------
TX_EMPTY_MODE_0_P: process (Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) or
(transfer_start_pulse = '1') or
(rst_xfer_done_fifo_0 = '1')then
xfer_done_fifo_0 <= '0';
elsif(SPIXfer_done_int_pulse = '1')then
xfer_done_fifo_0 <= '1';
end if;
end if;
end process TX_EMPTY_MODE_0_P;
------------------------------
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') then
Rx_FIFO_Full_reg <= '0';
elsif(SPIXfer_done_int_pulse = '1')then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
-----------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv,
stop_clock_reg,
spi_cntrl_ps,
no_slave_selected,
SR_5_Tx_Empty,
SPIXfer_done_int_pulse,
transfer_start_pulse,
xfer_done_fifo_0
)
begin
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
stop_clock <= '0';
spi_cntrl_ns <= TRANSFER_OKAY;
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
if(no_slave_selected = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
stop_clock <= xfer_done_fifo_0;
if (no_slave_selected = '1')then
spi_cntrl_ns <= IDLE;
--code coverage -- elsif(SPIXfer_done_int_pulse='1')then
--code coverage -- stop_clock <= SR_5_Tx_Empty;
--code coverage -- spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
-----------------------------------------------
end generate LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN;
-------------------------------------------------------------------------------
LOCAL_TX_EMPTY_FIFO_12_GEN: if C_FIFO_EXIST /= 0 generate
-----
begin
-----
xfer_done_fifo_0 <= '0';
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
----------------------
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Rx_FIFO_Full_reg <= '0';
elsif(reset_RcFIFO_ptr_to_spi = '1') or (DRR_Overrun_reg_int = '1') then
Rx_FIFO_Full_reg <= '0';
elsif(SPIXfer_done_int_pulse = '1')and (Rx_FIFO_Full = '1') then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
----------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv ,
stop_clock_reg ,
spi_cntrl_ps ,
no_slave_selected ,
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse ,
transfer_start_pulse ,
SPIXfer_done_int_pulse_d2,
SR_5_Tx_comeplete_Empty,
Loop_mode
)is
-----
begin
-----
stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
spi_cntrl_ns <= TRANSFER_OKAY;
stop_clock <= '0';
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
--if(no_slave_selected = '1')then
if(SR_5_Tx_comeplete_Empty = '1' and
SPIXfer_done_int_pulse_d2 = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if(SR_5_Tx_comeplete_Empty='1')then
-- stop_clock <= xfer_done_fifo_0;
if (Loop_mode = '1' and
SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
elsif(no_slave_selected = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
--stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
----------------------------------------
----------------------------------------
end generate LOCAL_TX_EMPTY_FIFO_12_GEN;
-----------------------------------------
SR_5_TX_EMPTY_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SR_5_Tx_Empty_d1 <= '0';
else
SR_5_Tx_Empty_d1 <= SR_5_Tx_Empty;
end if;
end if;
end process SR_5_TX_EMPTY_PROCESS;
----------------------------------
SR_5_Tx_Empty_pulse <= SR_5_Tx_Empty_d1 and not (SR_5_Tx_Empty);
----------------------------------
-------------------------------------------------------------------------------
-- Combinatorial operations
-------------------------------------------------------------------------------
-----------------------------------------------------------
LSB_first <= SPICR_9_LSB; -- Control_Reg(0);
Mst_Trans_inhibit <= SPICR_8_TR_INHIBIT; -- Control_Reg(1);
Manual_SS_mode <= SPICR_7_SS; -- Control_Reg(2);
CPHA <= SPICR_4_CPHA; -- Control_Reg(5);
CPOL <= SPICR_3_CPOL; -- Control_Reg(6);
Mst_N_Slv <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
SPI_En <= SPICR_1_SPE; -- Control_Reg(8);
Loop_mode <= SPICR_0_LOOP; -- Control_Reg(9);
Mst_N_Slv_mode <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
-----------------------------------------------------------
MOSI_O <= Serial_Dout;
MISO_O <= Serial_Dout;
Receive_Data <= receive_Data_int;
DRR_Overrun_reg <= DRR_Overrun_reg_int;
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rx_FIFO_Full_reg and
SPIXfer_done_int_pulse; --_d2;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
MST_TRANS_INHIBIT_D1_I: component FD
generic map
(
INIT => '1'
)
port map
(
Q => Mst_Trans_inhibit_d1,
C => Bus2IP_Clk,
D => Mst_Trans_inhibit
);
Mst_Trans_inhibit_pulse <= Mst_Trans_inhibit and (not Mst_Trans_inhibit_d1);
-------------------------------------------------------------------------------
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
master_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0') and --no mode fault
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_II : Tri-state register for SCK_T, ideal state-deactive
SPI_TRISTATE_CONTROL_II: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_III: tri-state register for MOSI, ideal state-deactive
SPI_TRISTATE_CONTROL_III: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MOSI_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_IV: tri-state register for SS,ideal state-deactive
SPI_TRISTATE_CONTROL_IV: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--* -------------------------------------------------------------------------------
--* -- SLAVE_TRIST_EN_PROCESS : If slave mode, then make tristate enabled
--* ---------------------------
slave_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='0') and -- decides master/slave
(control_bit_7_8(1)='1') and -- decide the spi_en
(SPISEL_sync = '0') and
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_V: tri-state register for MISO, ideal state-deactive
SPI_TRISTATE_CONTROL_V: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MISO_T,
C => Bus2IP_Clk,
D => slave_tri_state_en_control
);
-------------------------------------------------------------------------------
DTR_COMPLETE_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if(SR_5_Tx_Empty = '1' and SPIXfer_done_int_pulse = '1')then
SR_5_Tx_comeplete_Empty <= '1';
elsif(SR_5_Tx_Empty = '0')then
SR_5_Tx_comeplete_Empty <= '0';
end if;
end if;
end process DTR_COMPLETE_EMPTY_P;
---------------------------------
DTR_UNDERRUN_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
--if(SPIXfer_done_int_pulse_d2 = '1') then
DTR_underrun <= '1';
--end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_0_GEN;
DTR_UNDERRUN_FIFO_EXIST_GEN: if C_FIFO_EXIST /= 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
if(SPIXfer_done_int_pulse = '1') then
DTR_underrun <= '1';
end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_EXIST_GEN;
-------------------------------------------------------------------------------
-- SPISEL_SYNC: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
SPISEL_REG: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => Bus2IP_Clk,
D => SPISEL
);
---- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-------------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spisel_d1 <= '1';
spisel_d2 <= '1';
else
spisel_d1 <= SPISEL_sync;
spisel_d2 <= spisel_d1;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
--SPISEL_DELAY_1CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d1,
-- C => Bus2IP_Clk,
-- D => SPISEL_sync
-- );
--SPISEL_DELAY_2CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d2,
-- C => Bus2IP_Clk,
-- D => spisel_d1
-- );
---- spisel pulse generating logic
---- this one clock cycle pulse will be available for data loading into
---- shift register
--spisel_pulse <= (not SPISEL_sync) and spisel_d1;
------------------------------------------------
-- spisel pulse generating logic
-- this one clock cycle pulse will be available for data loading into
-- shift register
spisel_pulse <= (not spisel_d1) and spisel_d2;
-- --------|__________ -- SPISEL
-- ----------|________ -- SPISEL_sync
-- -------------|_____ -- spisel_d1
-- ----------------|___-- spisel_d2
-- _____________|--|__ -- SPISEL_pulse_op
SPISEL_pulse_op <= spisel_pulse;
SPISEL_d1_reg <= spisel_d2;
-------------------------------------------------------------------------------
--SCK_I_SYNC: first synchronize incomming signal
-------------
SCK_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => SCK_I_sync,
C => Bus2IP_Clk,
D => SCK_I
);
------------------------------------------------------------------
-- SCK_I_DELAY_1CLK_PROCESS : Detect active SCK edge in slave mode on +ve edge
SCK_I_DELAY_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
sck_i_d1 <= '0';
else
sck_i_d1 <= SCK_I_sync;
end if;
end if;
end process SCK_I_DELAY_1CLK_PROCESS;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_4_GEN: to synchronise the incoming clock signal in
-- slave mode in SCK ratio = 4
RISING_EDGE_CLK_RATIO_4_GEN : if C_SCK_RATIO = 4 generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I and (not(SCK_I_sync)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I) and SCK_I_sync) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_4_GEN;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_OTHERS_GEN: Due to timing crunch, in SCK> 4 mode,
-- the incoming clock signal cant be synchro
-- -nized with internal AXI clock.
-- slave mode operation on SCK_RATIO=2 isn't
-- supported in the core.
RISING_EDGE_CLK_RATIO_OTHERS_GEN: if ((C_SCK_RATIO /= 2) and (C_SCK_RATIO /= 4))
generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I_sync and (not(sck_i_d1)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I_sync) and sck_i_d1) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_OTHERS_GEN;
-------------------------------------------------------------------------------
-- combine rising edge as well as falling edge as a single signal
edge_sck_i <= rising_edge_sck_i or falling_edge_sck_i;
no_slave_selected <= and_reduce(Slave_Select_Reg(0 to (C_NUM_SS_BITS-1)));
-------------------------------------------------------------------------------
-- TRANSFER_START_PROCESS : Generate transfer start signal. When the transfer
-- gets completed, SPI Transfer done strobe pulls
-- transfer_start back to zero.
---------------------------
TRANSFER_START_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
(
Mst_N_Slv = '1' and -- If Master Mode
(
SPI_En = '0' or -- enable not asserted or
(SPIXfer_done_int = '1' and SR_5_Tx_Empty = '1') or -- no data in Tx reg/FIFO or
SR_3_MODF = '1' or -- mode fault error
Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
stop_clock = '1'
)
) or
(
Mst_N_Slv = '0' and -- If Slave Mode
(
SPI_En = '0' -- enable not asserted or
)
)
)then
transfer_start <= '0';
else
-- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
-- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
--if((SPIXfer_done_int_pulse = '1') or
-- (SPIXfer_done_int_pulse_d1 = '1') or
-- (SPIXfer_done_int_pulse_d2='1')) then-- this is added to remove
-- -- glitch at the end of
-- -- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
end if;
end if;
end process TRANSFER_START_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
-- transfer start pulse generating logic
transfer_start_pulse <= transfer_start and (not(transfer_start_d1));
---------------------------------------------------------------------------------
---- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
----------------------------
--TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
--begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
-- SPIXfer_done_int <= '0';
-- --elsif (transfer_start_pulse = '1') then
-- -- SPIXfer_done_int <= '0';
-- elsif(and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) = '1') then --(Count(COUNT_WIDTH) = '1') then
-- SPIXfer_done_int <= '1';
-- end if;
-- end if;
--end process TRANSFER_DONE_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
begin
-----
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
--elsif (transfer_start_pulse = '1') then
-- SPIXfer_done_int <= '0';
-- elsif(and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) = '1') then --(Count(COUNT_WIDTH) = '1') then
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '0') then
SPIXfer_done_int <= '1';
--SPIXfer_done_int <= Count(COUNT_WIDTH-1) and
-- Count(COUNT_WIDTH-2) and
-- Count(COUNT_WIDTH-3) and
-- not Count(COUNT_WIDTH-4);
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
rx_shft_reg <= rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
RECEIVE_DATA_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if(Loop_mode = '1') then
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= Shift_Reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= Shift_Reg;
end if;
else
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
-- Done strobe delayed to match receive data
SPIXfer_done <= SPIXfer_done_int_pulse_d3;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d3; -- SPIXfer_done_int_pulse_d1;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d3;
-------------------------------------------------
end generate RX_DATA_SCK_RATIO_2_GEN1;
-------------------------------------------------------------------------------
-- RX_DATA_GEN_OTHER_RATIOS: This logic is for other SCK ratios than
---------------------------- C_SCK_RATIO =2
RX_DATA_GEN_OTHER_SCK_RATIOS : if C_SCK_RATIO /= 2 generate
begin
FIFO_PRESENT_GEN: if C_FIFO_EXIST = 1 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and
--and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
end generate FIFO_PRESENT_GEN;
--------------------------------------------------------------
FIFO_ABSENT_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and
((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
end generate FIFO_ABSENT_GEN;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
-- the below mux is applicable only for Master mode of SPI.
rx_shft_reg <=
rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else
rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: the below process if for other
-------------------------------------------- SPI ratios of C_SCK_RATIO >2
-- -- It multiplexes the data stored
-- -- in internal registers in LSB and
-- -- non-LSB modes, in master as well as
-- -- in slave mode.
RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if (Mst_N_Slv = '1') then -- in master mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
elsif(Mst_N_Slv = '0') then -- in slave mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg_s
(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg_s;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO;
SPIXfer_done <= SPIXfer_done_int_pulse_d2;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or
SPIXfer_done_int_pulse_d2 or
spisel_pulse;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
--------------------------------------------
end generate RX_DATA_GEN_OTHER_SCK_RATIOS;
-------------------------------------------------------------------------------
-- OTHER_RATIO_GENERATE : Logic to be used when C_SCK_RATIO is not equal to 2
-------------------------
OTHER_RATIO_GENERATE: if(C_SCK_RATIO /= 2) generate
--attribute IOB : string;
--attribute IOB of MOSI_I_REG : label is "true";
begin
-----
-------------------------------------------------------------------------------
-- OTHER_RATIO_MISO_I_REG_IOB_GEN: Push the IO1_I register in IOB
-- --------------
-- Only when the targeted family is 7-series or spartan 6
-- ir-respective of C_USE_STARTUP parameter
OTHER_RATIO_MISO_I_REG_IOB_GEN: if(C_SUB_FAMILY = "virtex7"
or
C_SUB_FAMILY = "kintex7"
or
C_SUB_FAMILY = "artix7"
--or
--C_SUB_FAMILY = "spartan6"
)
-- or
-- (
-- C_USE_STARTUP = 0
-- and
-- C_SUB_FAMILY = "virtex6"
-- )
generate
-- attribute IOB : string;
--attribute IOB of MISO_I_REG : label is "true";
-----
begin
-----
MISO_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => miso_i_sync,
C => Bus2IP_Clk,
D => MISO_I
);
end generate OTHER_RATIO_MISO_I_REG_IOB_GEN;
-----------------------------------------------------------------
-- OTHER_RATIO_MISO_I_REG_NO_IOB_GEN: If C_USE_STARTUP is used and family is virtex6, then
-- IO1_I is registered only, but it is not pushed in IOB.
-- this is due to STARTUP block in V6 is having DINSPI interface available for IO1_I.
-- OTHER_RATIO_MISO_I_REG_NO_IOB_GEN: if(C_USE_STARTUP = 1
-- and
-- C_SUB_FAMILY = "virtex6"
-- ) generate
-------
--begin
-------
--MISO_I_REG: component FD
--generic map
-- (
-- INIT => '0'
-- )
--port map
-- (
-- Q => miso_i_sync,
-- C => Bus2IP_Clk,
-- D => MISO_I
-- );
--end generate OTHER_RATIO_MISO_I_REG_NO_IOB_GEN;
-----------------------------------------------------------------
MOSI_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => mosi_i_sync,
C => Bus2IP_Clk,
D => MOSI_I
);
------------------------------
LOOP_BACK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Loop_mode = '0' or Soft_Reset_op = RESET_ACTIVE) then
serial_dout_int <= '0';
elsif(Loop_mode = '1') then
serial_dout_int <= Serial_Dout;
end if;
end if;
end process LOOP_BACK_PROCESS;
------------------------------
-- EXTERNAL_INPUT_OR_LOOP_PROCESS: The logic below provides MUXed input to
-- serial_din input.
EXTERNAL_INPUT_OR_LOOP_PROCESS: process(Loop_mode,
Mst_N_Slv,
mosi_i_sync,
miso_i_sync,
serial_dout_int
)is
-----
begin
-----
if(Mst_N_Slv = '1' )then
if(Loop_mode = '1')then
Serial_Din <= serial_dout_int;
else
Serial_Din <= miso_i_sync;
end if;
else
Serial_Din <= mosi_i_sync;
end if;
end process EXTERNAL_INPUT_OR_LOOP_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_COUNT_PROCESS : Counter which counts from (C_SCK_RATIO/2)-1 down to 0
-- Used for counting the time to control SCK_O_reg generation
-- depending on C_SCK_RATIO
------------------------
RATIO_COUNT_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
else
Ratio_Count <= Ratio_Count - 1;
if (Ratio_Count = 0) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
end if;
end if;
end if;
end process RATIO_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_GEN_PROCESS : Generate a trigger whenever Ratio_Count reaches
-- zero
------------------------------
COUNT_TRIGGER_GEN_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger <= '0';
elsif(Ratio_Count = 0) then
Count_trigger <= not Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_GEN_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_1CLK_PROCESS : Delay cnt_trigger signal by 1 clock cycle
-------------------------------
COUNT_TRIGGER_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger_d1 <= '0';
else
Count_trigger_d1 <= Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_1CLK_PROCESS;
-- generate a trigger pulse for rising edge as well as falling edge
Count_trigger_pulse <= (Count_trigger and (not(Count_trigger_d1))) or
((not(Count_trigger)) and Count_trigger_d1);
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Count <= (others => '0');
elsif (Mst_N_Slv = '1') then
if (SPIXfer_done_int = '1')or
(transfer_start = '0') or
(xfer_done_fifo_0 = '1') then
Count <= (others => '0');
elsif((Count_trigger_pulse = '1') and (Count(COUNT_WIDTH) = '0')) then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
elsif (Mst_N_Slv = '0') then
if ((transfer_start = '0') or (SPISEL_sync = '1')or
(spixfer_done_int = '1')) then
Count <= (others => '0');
elsif (edge_sck_i = '1') then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(Sync_Reset = '1') or
(Mst_N_Slv='0')
)then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= sck_o_int xor Count_trigger_pulse;
end if;
end if;
end process SCK_SET_RESET_PROCESS;
------------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
DELAY_CLK: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process DELAY_CLK;
------------------------------------
-- Rising egde pulse for CPHA-CPOL = 00/11 mode
sck_rising_edge <= not(sck_d2) and sck_d1;
-- CAPT_RX_FE_MODE_00_11: The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 00 and 11.
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_rising_edge = '1') and (transfer_start='1')) then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
--
sck_fe1 <= (not sck_d1) and sck_d2;
-- CAPT_RX_FE_MODE_01_10 : The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 01 and 10.
CAPT_RX_FE_MODE_01_10 : process(Bus2IP_Clk)
begin
--if rising_edge(Bus2IP_Clk) then
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0110 <= (others => '0');
elsif ((sck_fe1 = '1') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data
------------------------------
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif((Mst_N_Slv = '1')) then -- and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
-- Capture Data on even Count
elsif(--(transfer_start = '1') and
(Count(0) = '0') ) then
Serial_Dout <= Shift_Reg(0);
-- Shift Data on odd Count
elsif(--(transfer_start = '1') and
(Count(0) = '1') and
(Count_trigger_pulse = '1')) then
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & Serial_Din;
end if;
-- below mode is slave mode logic for SPI
elsif(Mst_N_Slv = '0') then
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
--if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(SR_5_Tx_Empty_pulse = '1' or SPIXfer_done_int = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif (transfer_start = '1') then
if((CPOL = '0' and CPHA = '0') or
(CPOL = '1' and CPHA = '1')) then
if(rising_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(falling_edge_sck_i = '1') then
--elsif(rising_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
elsif((CPOL = '0' and CPHA = '1') or
(CPOL = '1' and CPHA = '0')) then
--Serial_Dout <= Shift_Reg(0);
if(falling_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(rising_edge_sck_i = '1') then
--elsif(falling_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
end if;
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate OTHER_RATIO_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(transfer_start = '0') or
(SPIXfer_done_int = '1') or
(Mst_N_Slv = '0')) then
Count <= (others => '0');
--elsif (Count(COUNT_WIDTH) = '0') then
-- Count <= Count + 1;
elsif(Count(COUNT_WIDTH) = '0')then
if(CPHA = '0')then
if(CPOL = '0' and transfer_start_d1 = '1')then -- cpol = cpha = 00
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then -- cpol = cpha = 10
Count <= Count + 1;
end if;
else
if(CPOL = '1' and transfer_start_d1 = '1')then -- cpol = cpha = 11
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then-- cpol = cpha = 10
Count <= Count + 1;
end if;
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (Sync_Reset = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= (not sck_o_int);-- xor Count(COUNT_WIDTH);
end if;
end if;
end process SCK_SET_RESET_PROCESS;
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '0') then
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
-- if (sck_rising_edge = '1') then
if (sck_d1 = '1') then
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
-- Falling egde pulse
sck_rising_edge <= sck_d2 and not sck_d1;
--
-- CAPT_RX_FE_MODE_01_10: the below logic captures data in SPI 01 or 10 mode.
---------------------------
CAPT_RX_FE_MODE_01_10: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
sck_d11 <= sck_o_in;
sck_d21 <= sck_d11;
if(CPOL = '1' and CPHA = '0') then
if ((sck_d1 = '1') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
elsif((CPOL = '0') and (CPHA = '1')) then
if ((sck_fe1 = '0') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
sck_fe1 <= (not sck_d11) and sck_d21;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif(Mst_N_Slv = '1') then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif(--(transfer_start = '1') and
(Count(0) = '0') -- and
--(Count(COUNT_WIDTH) = '0')
) then -- Shift Data on even
Serial_Dout <= Shift_Reg(0);
elsif(--(transfer_start = '1') and
(Count(0) = '1')-- and
--(Count(COUNT_WIDTH) = '0')
) then -- Capture Data on odd
if(Loop_mode = '1') then -- Loop mode
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Dout;
else
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & MISO_I;
end if;
end if;
elsif(Mst_N_Slv = '0') then
-- Added to have consistent default value after reset
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
if(spisel_pulse = '1' or SPIXfer_done_int_d1 = '1') then
Shift_Reg <= (others => '0');
Serial_Dout <= '0';
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate RATIO_OF_2_GENERATE;
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL,CPHA,transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse
)
begin
-- if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Set <= (CPOL xor CPHA);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL,
CPHA,
transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse)
begin
--if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Reset <= not(CPOL xor CPHA);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_NOT_EQUAL_4_GENERATE : Logic to be used when C_SCK_RATIO is not equal
-- to 4
-------------------------------
RATIO_NOT_EQUAL_4_GENERATE: if(C_SCK_RATIO /= 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
--attribute IOB : string;
--attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_NOT_EQUAL_4_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_4_GENERATE : Logic to be used when C_SCK_RATIO is equal to 4
------------------------
RATIO_OF_4_GENERATE: if(C_SCK_RATIO = 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
------------------------
-- A work around to reduce one clock cycle for sck_o generation. This would
-- allow for proper shifting of data bits into the slave device.
-- Removing the final stage F/F. Disadvantage of not registering final output
-------------------------------------------------------------------------------
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv,
sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
-----
begin
-----
if((Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
SCK_O_EQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
--attribute IOB : string;
--attribute IOB of SCK_O_EQ_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_EQ_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => SCK_O_1 -- Data input
);
end generate SCK_O_EQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_EQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
----------------------------------------------------------------------------
-- SCK_RATIO_4_REG_PROCESS : The SCK is registered in SCK RATIO = 4 mode
----------------------------------------------------------------------------
SCK_O_EQ_4_REG_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- If Soft_Reset_op or slave Mode. Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= SCK_O_1;
end if;
end if;
end process SCK_O_EQ_4_REG_PROCESS;
-----------------------------------
end generate SCK_O_EQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_OF_4_GENERATE;
-------------------------------------------------------------------------------
-- LOADING_FIRST_ELEMENT_PROCESS : Combinatorial process to generate flag
-- when loading first data element in shift
-- register from transmit register/fifo
----------------------------------
LOADING_FIRST_ELEMENT_PROCESS: process(Soft_Reset_op,
SPI_En,Mst_N_Slv,
SS_Asserted,
SS_Asserted_1dly,
SR_3_MODF,
transfer_start_pulse)is
begin
if(Soft_Reset_op = RESET_ACTIVE) then
Loading_SR_Reg_int <= '0'; --Clear flag
elsif(SPI_En = '1' and --Enabled
(
((Mst_N_Slv = '1') and --Master configuration
(SS_Asserted = '1') and
(SS_Asserted_1dly = '0') and
(SR_3_MODF = '0')
) or
((Mst_N_Slv = '0') and --Slave configuration
((transfer_start_pulse = '1'))
)
)
)then
Loading_SR_Reg_int <= '1'; --Set flag
else
Loading_SR_Reg_int <= '0'; --Clear flag
end if;
end process LOADING_FIRST_ELEMENT_PROCESS;
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SS_O <= (others => '1');
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
elsif(transfer_start = '0') or (xfer_done_fifo_0 = '1') then -- Tranfer not in progress
if(Manual_SS_mode = '0') then -- Auto SS assert
SS_O <= (others => '1');
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
end if;
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '1';
SS_Asserted_1dly <= SS_Asserted;
end if;
end if;
end process SELECT_OUT_PROCESS;
-------------------------------------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif((Mst_N_Slv = '1') and --In Master mode
(SPISEL_sync = '0') and (Allow_MODF_Strobe = '1')) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
-------------------------------------------------------------------------------
-- SLAVE_MODF_STROBE_PROCESS : Strobe MODF signal when slave is addressed
-- but not enabled.
------------------------------
SLAVE_MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
Slave_MODF_strobe <= '0';
Allow_Slave_MODF_Strobe<= '1';
elsif((Mst_N_Slv = '0') and --In Slave mode
(SPI_En = '0') and --but not enabled
(SPISEL_sync = '0') and
(Allow_Slave_MODF_Strobe = '1')
) then
Slave_MODF_strobe <= '1';
Allow_Slave_MODF_Strobe <= '0';
else
Slave_MODF_strobe <= '0';
end if;
end if;
end process SLAVE_MODF_STROBE_PROCESS;
---------------------xxx------------------------------------------------------
end imp;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 11:16:06 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/dds/dds_funcsim.vhdl
-- Design : dds
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ddsdds_compiler_v6_0__parameterized0\ is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tready : out STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 39 downto 0 );
s_axis_phase_tlast : in STD_LOGIC;
s_axis_phase_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tvalid : in STD_LOGIC;
s_axis_config_tready : out STD_LOGIC;
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tlast : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tready : in STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_tlast : out STD_LOGIC;
m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tready : in STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 39 downto 0 );
m_axis_phase_tlast : out STD_LOGIC;
m_axis_phase_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
event_pinc_invalid : out STD_LOGIC;
event_poff_invalid : out STD_LOGIC;
event_phase_in_invalid : out STD_LOGIC;
event_s_phase_tlast_missing : out STD_LOGIC;
event_s_phase_tlast_unexpected : out STD_LOGIC;
event_s_phase_chanid_incorrect : out STD_LOGIC;
event_s_config_tlast_missing : out STD_LOGIC;
event_s_config_tlast_unexpected : out STD_LOGIC;
debug_axi_pinc_in : out STD_LOGIC_VECTOR ( 37 downto 0 );
debug_axi_poff_in : out STD_LOGIC_VECTOR ( 37 downto 0 );
debug_axi_resync_in : out STD_LOGIC;
debug_axi_chan_in : out STD_LOGIC_VECTOR ( 0 to 0 );
debug_core_nd : out STD_LOGIC;
debug_phase : out STD_LOGIC_VECTOR ( 37 downto 0 );
debug_phase_nd : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsdds_compiler_v6_0__parameterized0\ : entity is "dds_compiler_v6_0";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \ddsdds_compiler_v6_0__parameterized0\ : entity is "zynq";
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of \ddsdds_compiler_v6_0__parameterized0\ : entity is 9;
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 38;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_LATENCY : integer;
attribute C_LATENCY of \ddsdds_compiler_v6_0__parameterized0\ : entity is 7;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of \ddsdds_compiler_v6_0__parameterized0\ : entity is 2;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 16;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 16;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of \ddsdds_compiler_v6_0__parameterized0\ : entity is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of \ddsdds_compiler_v6_0__parameterized0\ : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_RESYNC : integer;
attribute C_RESYNC of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of \ddsdds_compiler_v6_0__parameterized0\ : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_POR_MODE : integer;
attribute C_POR_MODE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 40;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 32;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 40;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \ddsdds_compiler_v6_0__parameterized0\ : entity is "yes";
end \ddsdds_compiler_v6_0__parameterized0\;
architecture STRUCTURE of \ddsdds_compiler_v6_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_synth_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
attribute C_ACCUMULATOR_WIDTH of i_synth : label is 38;
attribute C_AMPLITUDE of i_synth : label is 0;
attribute C_CHANNELS of i_synth : label is 1;
attribute C_CHAN_WIDTH of i_synth : label is 1;
attribute C_DEBUG_INTERFACE of i_synth : label is 0;
attribute C_HAS_ACLKEN of i_synth : label is 0;
attribute C_HAS_ARESETN of i_synth : label is 0;
attribute C_HAS_M_DATA of i_synth : label is 1;
attribute C_HAS_M_PHASE of i_synth : label is 1;
attribute C_HAS_PHASEGEN of i_synth : label is 1;
attribute C_HAS_PHASE_OUT of i_synth : label is 1;
attribute C_HAS_SINCOS of i_synth : label is 1;
attribute C_HAS_S_CONFIG of i_synth : label is 0;
attribute C_HAS_S_PHASE of i_synth : label is 1;
attribute C_HAS_TLAST of i_synth : label is 0;
attribute C_HAS_TREADY of i_synth : label is 0;
attribute C_LATENCY of i_synth : label is 7;
attribute C_MEM_TYPE of i_synth : label is 1;
attribute C_MODE_OF_OPERATION of i_synth : label is 0;
attribute C_MODULUS of i_synth : label is 9;
attribute C_M_DATA_HAS_TUSER of i_synth : label is 0;
attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 32;
attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_M_PHASE_TDATA_WIDTH of i_synth : label is 40;
attribute C_M_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_NEGATIVE_COSINE of i_synth : label is 0;
attribute C_NEGATIVE_SINE of i_synth : label is 0;
attribute C_NOISE_SHAPING of i_synth : label is 0;
attribute C_OPTIMISE_GOAL of i_synth : label is 0;
attribute C_OUTPUTS_REQUIRED of i_synth : label is 2;
attribute C_OUTPUT_FORM of i_synth : label is 0;
attribute C_OUTPUT_WIDTH of i_synth : label is 16;
attribute C_PHASE_ANGLE_WIDTH of i_synth : label is 16;
attribute C_PHASE_INCREMENT of i_synth : label is 3;
attribute C_PHASE_INCREMENT_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET of i_synth : label is 0;
attribute C_PHASE_OFFSET_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE of i_synth : label is 0;
attribute C_RESYNC of i_synth : label is 0;
attribute C_S_CONFIG_SYNC_MODE of i_synth : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH of i_synth : label is 1;
attribute C_S_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_S_PHASE_TDATA_WIDTH of i_synth : label is 40;
attribute C_S_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_USE_DSP48 of i_synth : label is 0;
attribute C_XDEVICEFAMILY of i_synth : label is "zynq";
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
attribute secure_extras : string;
attribute secure_extras of i_synth : label is "A";
begin
debug_axi_resync_in <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_synth: entity work.\ddsdds_compiler_v6_0_viv__parameterized0\
port map (
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
debug_axi_chan_in(0) => debug_axi_chan_in(0),
debug_axi_pinc_in(37 downto 0) => debug_axi_pinc_in(37 downto 0),
debug_axi_poff_in(37 downto 0) => debug_axi_poff_in(37 downto 0),
debug_axi_resync_in => NLW_i_synth_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => debug_core_nd,
debug_phase(37 downto 0) => debug_phase(37 downto 0),
debug_phase_nd => debug_phase_nd,
event_phase_in_invalid => event_phase_in_invalid,
event_pinc_invalid => event_pinc_invalid,
event_poff_invalid => event_poff_invalid,
event_s_config_tlast_missing => event_s_config_tlast_missing,
event_s_config_tlast_unexpected => event_s_config_tlast_unexpected,
event_s_phase_chanid_incorrect => event_s_phase_chanid_incorrect,
event_s_phase_tlast_missing => event_s_phase_tlast_missing,
event_s_phase_tlast_unexpected => event_s_phase_tlast_unexpected,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
m_axis_data_tlast => m_axis_data_tlast,
m_axis_data_tready => m_axis_data_tready,
m_axis_data_tuser(0) => m_axis_data_tuser(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(39 downto 0) => m_axis_phase_tdata(39 downto 0),
m_axis_phase_tlast => m_axis_phase_tlast,
m_axis_phase_tready => m_axis_phase_tready,
m_axis_phase_tuser(0) => m_axis_phase_tuser(0),
m_axis_phase_tvalid => m_axis_phase_tvalid,
s_axis_config_tdata(0) => s_axis_config_tdata(0),
s_axis_config_tlast => s_axis_config_tlast,
s_axis_config_tready => s_axis_config_tready,
s_axis_config_tvalid => s_axis_config_tvalid,
s_axis_phase_tdata(39 downto 0) => s_axis_phase_tdata(39 downto 0),
s_axis_phase_tlast => s_axis_phase_tlast,
s_axis_phase_tready => s_axis_phase_tready,
s_axis_phase_tuser(0) => s_axis_phase_tuser(0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dds is
port (
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 39 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 39 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of dds : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dds : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of dds : entity is "dds_compiler_v6_0,Vivado 2014.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of dds : entity is "dds,dds_compiler_v6_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of dds : entity is "dds,dds_compiler_v6_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=38,C_CHANNELS=1,C_HAS_PHASE_OUT=1,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=7,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=2,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=16,C_PHASE_ANGLE_WIDTH=16,C_PHASE_INCREMENT=3,C_PHASE_INCREMENT_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=1,C_S_PHASE_TDATA_WIDTH=40,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=32,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=1,C_M_PHASE_TDATA_WIDTH=40,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}";
end dds;
architecture STRUCTURE of dds is
signal NLW_U0_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 37 downto 0 );
signal NLW_U0_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 37 downto 0 );
signal NLW_U0_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 37 downto 0 );
signal NLW_U0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of U0 : label is 38;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of U0 : label is 0;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of U0 : label is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of U0 : label is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of U0 : label is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of U0 : label is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of U0 : label is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of U0 : label is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of U0 : label is 1;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of U0 : label is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of U0 : label is 1;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of U0 : label is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of U0 : label is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of U0 : label is 1;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of U0 : label is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 7;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of U0 : label is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of U0 : label is 9;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of U0 : label is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of U0 : label is 32;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of U0 : label is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of U0 : label is 40;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of U0 : label is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of U0 : label is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of U0 : label is 0;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of U0 : label is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of U0 : label is 2;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of U0 : label is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of U0 : label is 16;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of U0 : label is 16;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of U0 : label is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of U0 : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of U0 : label is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of U0 : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of U0 : label is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of U0 : label is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of U0 : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of U0 : label is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of U0 : label is 40;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\ddsdds_compiler_v6_0__parameterized0\
port map (
aclk => aclk,
aclken => '1',
aresetn => '1',
debug_axi_chan_in(0) => NLW_U0_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(37 downto 0) => NLW_U0_debug_axi_pinc_in_UNCONNECTED(37 downto 0),
debug_axi_poff_in(37 downto 0) => NLW_U0_debug_axi_poff_in_UNCONNECTED(37 downto 0),
debug_axi_resync_in => NLW_U0_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_U0_debug_core_nd_UNCONNECTED,
debug_phase(37 downto 0) => NLW_U0_debug_phase_UNCONNECTED(37 downto 0),
debug_phase_nd => NLW_U0_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_U0_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_U0_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_U0_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_U0_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => NLW_U0_event_s_phase_tlast_missing_UNCONNECTED,
event_s_phase_tlast_unexpected => NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
m_axis_data_tlast => NLW_U0_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => '0',
m_axis_data_tuser(0) => NLW_U0_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(39 downto 0) => m_axis_phase_tdata(39 downto 0),
m_axis_phase_tlast => NLW_U0_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => '0',
m_axis_phase_tuser(0) => NLW_U0_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => m_axis_phase_tvalid,
s_axis_config_tdata(0) => '0',
s_axis_config_tlast => '0',
s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => '0',
s_axis_phase_tdata(39 downto 0) => s_axis_phase_tdata(39 downto 0),
s_axis_phase_tlast => '0',
s_axis_phase_tready => NLW_U0_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => '0',
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
|
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
entity TESTONE is
end TESTONE;
architecture beh of TESTONE is
component sedici_bit is
port (
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
res : out std_logic_vector(15 downto 0);
fine : out std_logic
);
end component;
signal start, clk, fine : std_logic;
signal din, res : std_logic_vector(15 downto 0);
begin
DUT: sedici_bit port map (din, start, clk, res, fine);
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
start <= '1' after 1 ns, '0' after 11 ns,
'1' after 51 ns, '0' after 61 ns,
'1' after 111 ns, '0' after 121 ns,
'1' after 181 ns, '0' after 191 ns;
din <= "00000000000000"&"00" after 11 ns, "0000000000000000" after 21 ns, -- NOT
"00000000000000"&"01" after 61 ns, "0000000000000001" after 71 ns, "0000000000000010" after 81 ns, -- OR
"00000000000000"&"10" after 121 ns, "0000000000000011" after 131 ns, "0000000000000101" after 141 ns, -- ADD
"00000000000000"&"11" after 191 ns, "0000000000000110" after 201 ns, "0000000000011111" after 211 ns; -- MAC
end beh;
|
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