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library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity csgc is
port(
clk : in std_logic;
mlang : in std_logic_vector(15 downto 0);
ba_ctl : out std_logic_vector(2 downto 0);
bb_ctl : out std_logic_vector(4 downto 0);
address : out std_logic_vector(7 downto 0);
gr_lat : out std_logic;
gra : out std_logic_vector(3 downto 0);
grb : out std_logic_vector(3 downto 0);
grc : out std_logic_vector(3 downto 0);
ir_lat : out std_logic;
fr_lat : out std_logic;
pr_lat : out std_logic;
pr_cnt : out std_logic;
mar_lat : out std_logic;
mdr_lat : out std_logic;
mdr_sel : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
func : out std_logic_vector(3 downto 0);
phaseView : out std_logic_vector(3 downto 0)
);
end csgc;
architecture BEHAVIOR of csgc is
-- Definitions --
signal mnemo : std_logic_vector(3 downto 0);
signal opeA : std_logic_vector(3 downto 0);
signal opeB_addr : std_logic_vector(7 downto 0);
signal opeB_gr : std_logic_vector(3 downto 0);
signal phase : std_logic_vector(3 downto 0);
signal serial : std_logic_vector(41 downto 0);
-- Main --
begin
phaseView <= phase;
mnemo <= mlang(15 downto 12);
opeA <= mlang(11 downto 8);
opeB_addr <= mlang( 7 downto 0);
opeB_gr <= mlang( 3 downto 0);
-- Process --
process(clk) begin
if(clk'event and (clk = '1')) then
-- do instruction --
case mnemo is
when "0000" => -- HALT --
phase <= "1000";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "00000" & "0000";
when "0001" => -- LD1 --
case phase is
when "0000" => -- GRB->GRA, PR=PR+1
phase <= "1000";
serial <= "010" & "00000" & "00000000" & "1" & opeB_gr & "0000" & opeA & "0001" & "00000" & "0000";
-- busA | busB | address |grlat| gra | grb | grc | i/f/pr |mem,mda/r| func
when others => null;
end case;
when "0010" => -- LD2 --
case phase is
when "0000" => -- address->MAR
phase <= "0001";
serial <= "000" & "00001" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0000" & "10000" & "0001";
when "0001" => -- change memory address
phase <= "0010";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "00010" & "0000";
when "0010" => -- mem(MAR)->MDR
phase <= "0011";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "01110" & "0000";
when "0011" => -- MDR->GRA, PR=PR+1
phase <= "1000";
serial <= "000" & "00010" & "00000000" & "1" & "0000" & "0000" & opeA & "0001" & "00000" & "0001";
when others => null;
end case;
when "0011" => -- LAD --
case phase is
when "0000" => -- address->GRA, PR=PR+1
phase <= "1000";
serial <= "000" & "00001" & opeB_addr & "1" & "0000" & "0000" & opeA & "0001" & "00000" & "0001";
when others => null;
end case;
when "0100" => -- STR --
case phase is
when "0000" => -- GRA->MDR
phase <= "0001";
serial <= "010" & "00000" & "00000000" & "0" & opeA & "0000" & "0000" & "0000" & "01000" & "0000";
when "0001" => -- address->MAR
phase <= "0010";
serial <= "000" & "00001" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0000" & "10000" & "0001";
when "0010" => -- MDR->mem(MAR), PR=PR+1
phase <= "1000";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0001" & "00001" & "0000";
when others => null;
end case;
when "0101" => -- ADD --
case phase is
when "0000" => -- GRA=GRA+GRB, PR=PR+1
phase <= "1000";
serial <= "010" & "10000" & "00000000" & "1" & opeA & opeB_gr & opeA & "0101" & "00000" & "0101";
when others => null;
end case;
when "0110" => -- SUB --
case phase is
when "0000" => -- GRA=GRA-GRB, PR=PR+1
phase <= "1000";
serial <= "010" & "10000" & "00000000" & "1" & opeA & opeB_gr & opeA & "0101" & "00000" & "0110";
when others => null;
end case;
when "0111" => -- SL --
case phase is
when "0000" => -- GRA=GRA<<GRB, PR=PR+1
phase <= "1000";
serial <= "010" & "10000" & "00000000" & "1" & opeA & opeB_gr & opeA & "0101" & "00000" & "0111";
when others => null;
end case;
when "1000" => -- SR --
case phase is
when "0000" => -- GRA=GRA>>GRB, PR=PR+1
phase <= "1000";
serial <= "010" & "10000" & "00000000" & "1" & opeA & opeB_gr & opeA & "0101" & "00000" & "1000";
when others => null;
end case;
when "1001" => -- NAND --
case phase is
when "0000" => -- GRA=GRAnandGRB, PR=PR+1
phase <= "1000";
serial <= "010" & "10000" & "00000000" & "1" & opeA & opeB_gr & opeA & "0101" & "00000" & "1001";
when others => null;
end case;
when "1010" => -- JMP --
if(opeA = "0000") then
case phase is
when "0000" => -- address->PR
phase <= "1000";
serial <= "000" & "00001" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "0001";
when others => null;
end case;
else
case phase is
when "0000" => -- PR->GRA
phase <= "0001";
serial <= "000" & "01000" & "00000000" & "1" & "0000" & "0000" & opeA & "0000" & "00000" & "0001";
when "0001" => -- address->PR
phase <= "1000";
serial <= "000" & "00001" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "0001";
when others => null;
end case;
end if;
when "1011" => -- JZE --
if(opeA = "0000") then
case phase is
when "0000" => -- if(ZF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1011";
when others => null;
end case;
else
case phase is
when "0000" => -- PR->GRA
phase <= "0001";
serial <= "000" & "01000" & "00000000" & "1" & "0000" & "0000" & opeA & "0000" & "00000" & "0001";
when "0001" => -- if(ZF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1011";
when others => null;
end case;
end if;
when "1100" => -- JMI --
if(opeA = "0000") then
case phase is
when "0000" => -- if(SF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1100";
when others => null;
end case;
else
case phase is
when "0000" => -- PR->GRA
phase <= "0001";
serial <= "000" & "01000" & "00000000" & "1" & "0000" & "0000" & opeA & "0000" & "00000" & "0001";
when "0001" => -- if(SF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1100";
when others => null;
end case;
end if;
when "1101" => -- JOV --
if(opeA = "0000") then
case phase is
when "0000" => -- if(OF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1101";
when others => null;
end case;
else
case phase is
when "0000" => -- PR->GRA
phase <= "0001";
serial <= "000" & "01000" & "00000000" & "1" & "0000" & "0000" & opeA & "0000" & "00000" & "0001";
when "0001" => -- if(OF=1) then address->PR else PR=PR+1
phase <= "1000";
serial <= "100" & "01000" & opeB_addr & "0" & "0000" & "0000" & "0000" & "0010" & "00000" & "1101";
when others => null;
end case;
end if;
when "1110" => -- RJMP --
case phase is
when "0000" => -- GRA->PR
phase <= "0001";
serial <= "000" & "10000" & "00000000" & "0" & "0000" & opeA & "0000" & "0010" & "00000" & "0001";
when "0001" => -- PR=PR+1
phase <= "1000";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0001" & "00000" & "0000";
when others => null;
end case;
when "1111" => -- DISP --
phase <= "1000"; -- PR=PR+1
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0001" & "00000" & "0000";
when others =>
phase <= "1000";
end case;
-- go next instruction --
case phase is
when "1000" => -- PR->MAR
phase <= "1001";
serial <= "000" & "01000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "10000" & "0001";
when "1001" => -- change memory address
phase <= "1010";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "00010" & "0000";
when "1010" => -- mem(MAR)->MDR
phase <= "1011";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "01110" & "0000";
when "1011" => -- MDR->IR
phase <= "1100";
serial <= "001" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "1000" & "00000" & "0000";
when "1100" => -- changing Mlang
phase <= "0000";
serial <= "000" & "00000" & "00000000" & "0" & "0000" & "0000" & "0000" & "0000" & "00000" & "0000";
when others => null;
end case;
else
null;
end if;
end process;
ba_ctl <= serial(41 downto 39);
bb_ctl <= serial(38 downto 34);
address <= serial(33 downto 26);
gr_lat <= serial(25);
gra <= serial(24 downto 21);
grb <= serial(20 downto 17);
grc <= serial(16 downto 13);
ir_lat <= serial(12);
fr_lat <= serial(11);
pr_lat <= serial(10);
pr_cnt <= serial(9);
mar_lat <= serial(8);
mdr_lat <= serial(7);
mdr_sel <= serial(6);
m_read <= serial(5);
m_write <= serial(4);
func <= serial(3 downto 0);
end BEHAVIOR;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/29/2017 12:10:39 PM
-- Design Name:
-- Module Name: Concat - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Concat is Port ( setZ : in STD_LOGIC;
DIN0 : in STD_LOGIC;
DIN1 : in STD_LOGIC;
DIN2 : in STD_LOGIC;
DIN3 : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (3 downto 0));
end Concat;
architecture Behavioral of Concat is begin
process (setZ, DIN0, DIN1, DIN2, DIN3) begin
if setZ = '1' then
DOUT <= (others => 'Z');
else
DOUT <= DIN0 & DIN1 & DIN2 & DIN3;
end if;
end process;
end Behavioral;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
entity lut_Sine is
generic (
REG_OUTPUT : BOOLEAN := TRUE;
MAX_AMPLITUDE : POSITIVE := 255;
POINTS : POSITIVE := 4096;
OFFSET_DEG : REAL := 0.0;
QUARTERS : POSITIVE := 4
);
port (
Clock : in STD_LOGIC;
Input : in STD_LOGIC_VECTOR(log2ceilnz(POINTS) - 1 downto 0);
Output : out STD_LOGIC_VECTOR(log2ceilnz(MAX_AMPLITUDE + ((QUARTERS - 1) / 2)) downto 0)
);
end entity;
architecture rtl of lut_Sine is
signal Output_nxt : STD_LOGIC_VECTOR(Output'range);
begin
-- ===========================================================================
-- 1 Qudrant LUT
-- ===========================================================================
genQ1 : if (QUARTERS = 1) generate
subtype T_RESULT is NATURAL range 0 to MAX_AMPLITUDE;
type T_LUT is array (NATURAL range <>) of T_RESULT;
function generateLUT return T_LUT is
variable Result : T_LUT(0 to POINTS - 1) := (others => 0);
constant STEP : REAL := (90.0 / real(Result'length)) * MATH_DEG_TO_RAD;
constant AMPLITUDE_I : REAL := real(MAX_AMPLITUDE);
variable x : REAL := 0.0;
variable y : REAL;
begin
for i in Result'range loop
Result(i) := integer(sin(x) * AMPLITUDE_I);
x := x + STEP;
end loop;
return Result;
end function;
constant LUT : T_LUT := generateLUT;
begin
assert (OFFSET_DEG = 0.0) report "Offset > 0.0° is only supported in 4 quadrant mode." severity FAILURE;
Output_nxt <= std_logic_vector(to_unsigned(LUT(to_index(Input, LUT'length)), Output_nxt'length));
end generate;
-- ===========================================================================
-- 2 Qudrant LUT
-- ===========================================================================
genQ12 : if (QUARTERS = 2) generate
subtype T_RESULT is NATURAL range 0 to MAX_AMPLITUDE;
type T_LUT is array (NATURAL range <>) of T_RESULT;
function generateLUT return T_LUT is
variable Result : T_LUT(0 to POINTS - 1) := (others => 0);
constant STEP : REAL := (180.0 / real(Result'length)) * MATH_DEG_TO_RAD;
constant AMPLITUDE_I : REAL := real(MAX_AMPLITUDE);
variable x : REAL := 0.0;
variable y : REAL;
begin
for i in Result'range loop
Result(i) := integer(sin(x) * AMPLITUDE_I);
x := x + STEP;
end loop;
return Result;
end function;
constant LUT : T_LUT := generateLUT;
begin
assert (OFFSET_DEG = 0.0) report "Offset > 0.0° is only supported in 4 quadrant mode." severity FAILURE;
Output_nxt <= std_logic_vector(to_unsigned(LUT(to_index(Input, LUT'length)), Output_nxt'length));
end generate;
-- ===========================================================================
-- 3 Qudrant LUT -> ERROR
-- ===========================================================================
genQ13 : if (QUARTERS = 3) generate
assert false report "QUARTERS=3 is not supported." severity FAILURE;
end generate;
-- ===========================================================================
-- 4 Qudrant LUT
-- ===========================================================================
genQ14 : if (QUARTERS = 4) generate
subtype T_RESULT is INTEGER range -MAX_AMPLITUDE to MAX_AMPLITUDE;
type T_LUT is array (NATURAL range <>) of T_RESULT;
function generateLUT return T_LUT is
variable Result : T_LUT(0 to POINTS - 1) := (others => 0);
constant STEP : REAL := (360.0 / real(Result'length)) * MATH_DEG_TO_RAD;
constant AMPLITUDE_I : REAL := real(MAX_AMPLITUDE);
variable x : REAL := OFFSET_DEG * MATH_DEG_TO_RAD;
variable y : REAL;
begin
for i in Result'range loop
report "x=" & str_format(x, 3) & " y=" & str_format((sin(x) * AMPLITUDE_I), 3) severity note;
Result(i) := integer(sin(x) * AMPLITUDE_I);
x := x + STEP;
end loop;
return Result;
end function;
constant LUT : T_LUT := generateLUT;
begin
Output_nxt <= std_logic_vector(to_signed(LUT(to_index(Input, LUT'length)), Output_nxt'length));
end generate;
-- ===========================================================================
-- No output registers
-- ===========================================================================
genNoReg : if (REG_OUTPUT = FALSE) generate
begin
Output <= Output_nxt;
end generate;
-- ===========================================================================
-- Output registers
-- ===========================================================================
genReg : if (REG_OUTPUT = TRUE) generate
signal Output_d : STD_LOGIC_VECTOR(Output'range) := (others => '0');
begin
Output_d <= Output_nxt when rising_edge(Clock);
Output <= Output_d;
end generate;
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
entity lut_Sine is
generic (
REG_OUTPUT : BOOLEAN := TRUE;
MAX_AMPLITUDE : POSITIVE := 255;
POINTS : POSITIVE := 4096;
OFFSET_DEG : REAL := 0.0;
QUARTERS : POSITIVE := 4
);
port (
Clock : in STD_LOGIC;
Input : in STD_LOGIC_VECTOR(log2ceilnz(POINTS) - 1 downto 0);
Output : out STD_LOGIC_VECTOR(log2ceilnz(MAX_AMPLITUDE + ((QUARTERS - 1) / 2)) downto 0)
);
end entity;
architecture rtl of lut_Sine is
signal Output_nxt : STD_LOGIC_VECTOR(Output'range);
begin
-- ===========================================================================
-- 1 Qudrant LUT
-- ===========================================================================
genQ1 : if (QUARTERS = 1) generate
subtype T_RESULT is NATURAL range 0 to MAX_AMPLITUDE;
type T_LUT is array (NATURAL range <>) of T_RESULT;
function generateLUT return T_LUT is
variable Result : T_LUT(0 to POINTS - 1) := (others => 0);
constant STEP : REAL := (90.0 / real(Result'length)) * MATH_DEG_TO_RAD;
constant AMPLITUDE_I : REAL := real(MAX_AMPLITUDE);
variable x : REAL := 0.0;
variable y : REAL;
begin
for i in Result'range loop
Result(i) := integer(sin(x) * AMPLITUDE_I);
x := x + STEP;
end loop;
return Result;
end function;
constant LUT : T_LUT := generateLUT;
begin
assert (OFFSET_DEG = 0.0) report "Offset > 0.0° is only supported in 4 quadrant mode." severity FAILURE;
Output_nxt <= std_logic_vector(to_unsigned(LUT(to_index(Input, LUT'length)), Output_nxt'length));
end generate;
-- ===========================================================================
-- 2 Qudrant LUT
-- ===========================================================================
genQ12 : if (QUARTERS = 2) generate
subtype T_RESULT is NATURAL range 0 to MAX_AMPLITUDE;
type T_LUT is array (NATURAL range <>) of T_RESULT;
function generateLUT return T_LUT is
variable Result : T_LUT(0 to POINTS - 1) := (others => 0);
constant STEP : REAL := (180.0 / real(Result'length)) * MATH_DEG_TO_RAD;
constant AMPLITUDE_I : REAL := real(MAX_AMPLITUDE);
variable x : REAL := 0.0;
variable y : REAL;
begin
for i in Result'range loop
Result(i) := integer(sin(x) * AMPLITUDE_I);
x := x + STEP;
end loop;
return Result;
end function;
constant LUT : T_LUT := generateLUT;
begin
assert (OFFSET_DEG = 0.0) report "Offset > 0.0° is only supported in 4 quadrant mode." severity FAILURE;
Output_nxt <= std_logic_vector(to_unsigned(LUT(to_index(Input, LUT'length)), Output_nxt'length));
end generate;
-- ===========================================================================
-- 3 Qudrant LUT -> ERROR
-- ===========================================================================
genQ13 : if (QUARTERS = 3) generate
assert false report "QUARTERS=3 is not supported." severity FAILURE;
end generate;
-- ===========================================================================
-- 4 Qudrant LUT
-- ===========================================================================
genQ14 : if (QUARTERS = 4) generate
subtype T_RESULT is INTEGER range -MAX_AMPLITUDE to MAX_AMPLITUDE;
type T_LUT is array (NATURAL range <>) of T_RESULT;
function generateLUT return T_LUT is
variable Result : T_LUT(0 to POINTS - 1) := (others => 0);
constant STEP : REAL := (360.0 / real(Result'length)) * MATH_DEG_TO_RAD;
constant AMPLITUDE_I : REAL := real(MAX_AMPLITUDE);
variable x : REAL := OFFSET_DEG * MATH_DEG_TO_RAD;
variable y : REAL;
begin
for i in Result'range loop
report "x=" & str_format(x, 3) & " y=" & str_format((sin(x) * AMPLITUDE_I), 3) severity note;
Result(i) := integer(sin(x) * AMPLITUDE_I);
x := x + STEP;
end loop;
return Result;
end function;
constant LUT : T_LUT := generateLUT;
begin
Output_nxt <= std_logic_vector(to_signed(LUT(to_index(Input, LUT'length)), Output_nxt'length));
end generate;
-- ===========================================================================
-- No output registers
-- ===========================================================================
genNoReg : if (REG_OUTPUT = FALSE) generate
begin
Output <= Output_nxt;
end generate;
-- ===========================================================================
-- Output registers
-- ===========================================================================
genReg : if (REG_OUTPUT = TRUE) generate
signal Output_d : STD_LOGIC_VECTOR(Output'range) := (others => '0');
begin
Output_d <= Output_nxt when rising_edge(Clock);
Output <= Output_d;
end generate;
end;
|
------------------------------
entity array_slices is
--generic declarations
port (
row: in integer range 0 to 3;
column: in integer range 0 to 4;
slice1: out bit ;
slice2: out bit_vector(1 to 2) ;
slice3: out bit_vector(1 to 4) ;
slice4: out bit_vector(1 to 3) ;);
end entity;
------------------------------
architecture circuit of array_slices is
type twod is array (1 to 3, 1 to 4) of bit;
constant table: twod := (('0', '0', '0', '1'),
('1', '0', '0', '1'),
('1', '1', '0', '1'));
begin
slice1 <= table(row)(column);
-- slice2 <= table(row, 1 to 2);
-- slice3 <= table(row, 1 to 4);
-- slice4 <= table(1, column) & table(2, column) & table(3, column);
gen: for i in 1 to 3 generate
slice4(i) <= table(i, column);
end generate;
end architecture;
------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1877.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01877ent IS
END c07s01b00x00p08n01i01877ent;
ARCHITECTURE c07s01b00x00p08n01i01877arch OF c07s01b00x00p08n01i01877ent IS
type small_int is range 0 to 7;
BEGIN
TESTING : PROCESS
variable car : small_int;
BEGIN
car := TESTING; --process labels illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01877 - Process labels are not permitted as primaries in a variable assignment expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01877arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1877.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01877ent IS
END c07s01b00x00p08n01i01877ent;
ARCHITECTURE c07s01b00x00p08n01i01877arch OF c07s01b00x00p08n01i01877ent IS
type small_int is range 0 to 7;
BEGIN
TESTING : PROCESS
variable car : small_int;
BEGIN
car := TESTING; --process labels illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01877 - Process labels are not permitted as primaries in a variable assignment expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01877arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1877.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01877ent IS
END c07s01b00x00p08n01i01877ent;
ARCHITECTURE c07s01b00x00p08n01i01877arch OF c07s01b00x00p08n01i01877ent IS
type small_int is range 0 to 7;
BEGIN
TESTING : PROCESS
variable car : small_int;
BEGIN
car := TESTING; --process labels illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01877 - Process labels are not permitted as primaries in a variable assignment expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01877arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psl.all;
use work.mmio_package.all;
entity mmio is
port (
i : in mmio_in;
o : out mmio_out
);
end entity mmio;
architecture logic of mmio is
signal q, r : mmio_int;
begin
comb : process(all)
variable v : mmio_int;
begin
----------------------------------------------------------------------------------------------------------------------- default assignments
v := r;
v.reg := i.ac.data;
----------------------------------------------------------------------------------------------------------------------- parse inputs
v.cfg_read := i.ha.val and i.ha.cfg and i.ha.rnw;
v.cfg_write := i.ha.val and i.ha.cfg and not i.ha.rnw;
v.mmio_dw := i.ha.dw;
v.mmio_write := i.ha.val and not i.ha.cfg and not i.ha.rnw;
v.mmio_read := i.ha.val and not i.ha.cfg and i.ha.rnw;
----------------------------------------------------------------------------------------------------------------------- afu descriptor
-- register offset x'0 : reg_prog_model and num_of_processes
if i.ha.ad(PSL_MMIO_ADDRESS_WIDTH - 1 downto 0) = 24x"0" then
v.cfg_data := AFUD_0;
-- register offset x'30' : per_process_psa_control
elsif i.ha.ad(PSL_MMIO_ADDRESS_WIDTH - 1 downto 0) = 24x"c" then
v.cfg_data := AFUD_30;
else
v.cfg_data := (others => '0');
end if;
----------------------------------------------------------------------------------------------------------------------- write
if v.mmio_write then
case i.ha.ad is
-- debug data
when MMIO_REG_ADDRESS =>
v.reg := i.ha.data;
when others => null;
end case;
end if;
----------------------------------------------------------------------------------------------------------------------- read
-- afu descriptor double word
if r.cfg_read and r.mmio_dw then
v.mmio_rdata := v.cfg_data;
-- afu descriptor word
elsif r.cfg_read and i.ha.ad(0) then
v.mmio_rdata := v.cfg_data(PSL_WORD_WIDTH - 1 downto 0) & v.cfg_data(PSL_WORD_WIDTH - 1 downto 0);
-- afu descriptor other word
elsif r.cfg_read then
v.mmio_rdata := v.cfg_data(PSL_WORD_WIDTH - 1 downto 0) & v.cfg_data(PSL_WORD_WIDTH - 1 downto 0);
-- read register double word
elsif r.mmio_read and r.mmio_dw then
case i.ha.ad is
-- debug data
when MMIO_REG_ADDRESS =>
v.mmio_rdata := v.reg;
when others => null;
end case;
else
v.mmio_rdata := (others => '0');
end if;
----------------------------------------------------------------------------------------------------------------------- output
v.ack := r.cfg_read or r.cfg_write or r.mmio_read or r.mmio_write;
q <= v;
o.ah.ack <= r.ack;
o.ah.data <= r.mmio_rdata;
end process;
----------------------------------------------------------------------------------------------------------------------- reset & registers
reg : process(i.cr)
begin
if rising_edge(i.cr.clk) then
if i.cr.rst then
mmio_reset(r);
else
r <= q;
end if;
end if;
end process;
end architecture logic;
|
--------------------------------------------------------------------------------
-- ion_core.vhdl -- MIPS32r2(tm) compatible CPU core
--------------------------------------------------------------------------------
-- This is the main project module. It contains the CPU plus the TCMs and caches
-- if it is configured to have any.
-- The user does not need to tinker with any modules at or below this level.
--------------------------------------------------------------------------------
-- FIXME when caches are missing they should be replaced with a WB bridge.
-- TODO add brief usage instructions.
-- TODO add reference to datasheet.
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ion_core is
generic(
-- Size of code TCM block in 32-bit words.
-- Set to a power of 2 or to zero to disable code TCM.
TCM_CODE_SIZE : integer := 2048;
-- Contents of code TCM. Defaults to zero.
TCM_CODE_INIT : t_obj_code := zero_objcode(16);
-- Size of data TCM block in 32-bit words.
-- Set to a power of 2 or to zero to disable data TCM.
TCM_DATA_SIZE : integer := 2048;
-- Contents of data TCM.
TCM_DATA_INIT : t_obj_code := zero_objcode(16);
-- Size of data cache in lines.
-- Set to a power of 2 or 0 to disable the data cache.
DATA_CACHE_LINES : integer := 128;
-- Size of code cache in lines.
-- Set to a power of 2 or 0 to disable the code cache.
CODE_CACHE_LINES : integer := 128;
-- Type of memory to be used for register bank in xilinx HW
XILINX_REGBANK : string := "distributed" -- {distributed|block}
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
-- Code cache refill port.
CODE_WB_MOSI_O : out t_wishbone_mosi;
CODE_WB_MISO_I : in t_wishbone_miso;
-- Data cache refill port.
DATA_WB_MOSI_O : out t_wishbone_mosi;
DATA_WB_MISO_I : in t_wishbone_miso;
-- Uncached data WB bridge port.
DATA_UC_WB_MOSI_O : out t_wishbone_mosi;
DATA_UC_WB_MISO_I : in t_wishbone_miso;
-- COP2 interface.
COP2_MOSI_O : out t_cop2_mosi;
COP2_MISO_I : in t_cop2_miso;
IRQ_I : in std_logic_vector(5 downto 0)
);
end; --entity ion_cpu
architecture rtl of ion_core is
--------------------------------------------------------------------------------
-- CPU interface signals
signal data_mosi : t_cpumem_mosi;
signal data_miso : t_cpumem_miso;
signal code_mosi : t_cpumem_mosi;
signal code_miso : t_cpumem_miso;
signal cache_ctrl_mosi : t_cache_mosi;
signal icache_ctrl_miso : t_cache_miso;
signal dcache_ctrl_miso : t_cache_miso;
--------------------------------------------------------------------------------
-- Code space signals
-- Address decoding signals.
signal code_mux_ctrl : std_logic_vector(1 downto 0);
signal code_mux_ctrl_reg : std_logic_vector(1 downto 0);
signal code_ce : std_logic_vector(1 downto 0);
-- Instruction Cache MISO bus & enable signal.
signal icache_miso : t_cpumem_miso;
-- Code TCM MISO bus & enable signal.
signal ctcm_c_miso : t_cpumem_miso;
-- Bus from CTCM arbiter to CTCM.
signal ctcm_mosi : t_cpumem_mosi;
signal ctcm_miso : t_cpumem_miso;
--------------------------------------------------------------------------------
-- Data space signals
-- Address decoding signals.
signal data_mux_ctrl : std_logic_vector(2 downto 0);
signal data_mux_ctrl_reg : std_logic_vector(2 downto 0);
signal data_ce : std_logic_vector(3 downto 0);
-- Data Cache MISO bus & enable signal.
signal dcache_miso : t_cpumem_miso;
signal dcache_ce : std_logic;
-- Data TCM MISO bus & enable signal.
signal dtcm_miso : t_cpumem_miso;
signal dtcm_ce : std_logic;
-- Code TCM MISO bus & enable signal (CTCM seen from data bus).
signal ctcm_d_miso : t_cpumem_miso;
-- Uncached Data, external WB bridge MISO bus & enable signal.
signal ucd_wb_mosi : t_cpumem_mosi;
signal ucd_wb_miso : t_cpumem_miso;
signal void_miso : t_cpumem_miso;
--------------------------------------------------------------------------------
-- Address decoding constant & constant functions.
-- Data TCM mapped to the start of KSEG1 uncached area.
constant DTCM_BASE : t_word := X"A0000000";
constant DTCM_ASIZE : integer := log2(TCM_DATA_SIZE+2);
-- Code TCM mapped to reset vector within KSEG1 uncached area.
constant CTCM_BASE : t_word := X"BFC00000";
constant CTCM_ASIZE : integer := log2(TCM_CODE_SIZE+2);
-- Code TCM accessible on data bus on the same address as on the code bus.
constant DCTCM_BASE : t_word := X"BFC00000";
-- Wishbone port is mapped to high 1GB area, meant for I/O mostly.
constant DWB_BASE : t_word := X"c0000000";
constant DWB_ASIZE : integer := 30;
-- NOTE: all the functions defined in this entity are "constant functions" that
-- can be used in synthesizable rtl as long as their parameters are constants.
-- Return '1' if high 's' of address 'a' match those of address 'b'.
function adecode(a : t_word; b : t_word; s : integer) return std_logic is
begin
if a(31 downto s+1) = b(31 downto s+1) then
return '1';
else
return '0';
end if;
end function adecode;
-- Decode address to see if it is within the cached area.
-- (Cached addresses are all addresses from 0x00000000 to 0x9fffffff.)
-- Return '1' if address 'a' is cached, '0' otherwise.
function cached(a : t_word) return std_logic is
begin
if a(31 downto 29) = "101" or a(31 downto 30) = "11" then
return '0';
else
return '1';
end if;
end function cached;
begin
--------------------------------------------------------------------------------
-- CPU
cpu: entity work.ION_CPU
generic map (
XILINX_REGBANK => XILINX_REGBANK
)
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
DATA_MOSI_O => data_mosi,
DATA_MISO_I => data_miso,
CODE_MOSI_O => code_mosi,
CODE_MISO_I => code_miso,
CACHE_CTRL_MOSI_O => cache_ctrl_mosi,
ICACHE_CTRL_MISO_I => icache_ctrl_miso,
DCACHE_CTRL_MISO_I => dcache_ctrl_miso,
COP2_MOSI_O => COP2_MOSI_O,
COP2_MISO_I => COP2_MISO_I,
IRQ_I => IRQ_I
);
--------------------------------------------------------------------------------
-- Code Bus interconnect.
-- Address decoding --------------------------------------------------------
-- Decode the index of the slave being addressed.
code_mux_ctrl <=
"01" when adecode(code_mosi.addr, CTCM_BASE, CTCM_ASIZE) = '1' else
"10" when cached(code_mosi.addr) = '1' else
"00";
-- Convert slave index to one-hot enable signal vector.
with code_mux_ctrl select code_ce <=
"01" when "01",
"10" when "10",
"00" when others;
-- Code MISO multiplexor -----------------------------------------------
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
code_mux_ctrl_reg <= (others => '0');
elsif code_mosi.rd_en='1' then
code_mux_ctrl_reg <= code_mux_ctrl;
end if;
end if;
end process;
with code_mux_ctrl_reg select code_miso <=
ctcm_c_miso when "01",
icache_miso when "10",
void_miso when others;
-- MISO to be fed to the CPU by the code and data MISO multiplexors when
-- no valid area is addressed.
void_miso.mwait <= '0';
void_miso.rd_data <= (others => '0');
-- Code cache ----------------------------------------------------------
code_cache_present:
if CODE_CACHE_LINES > 0 generate
code_cache: entity work.ION_CACHE
generic map (
NUM_LINES => CODE_CACHE_LINES
)
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
-- FIXME there should be a MISO for each cache in the control port
CACHE_CTRL_MOSI_I => cache_ctrl_mosi,
CACHE_CTRL_MISO_O => OPEN,
CE_I => code_ce(1),
CPU_MOSI_I => code_mosi,
CPU_MISO_O => icache_miso,
MEM_MOSI_O => CODE_WB_MOSI_O,
MEM_MISO_I => CODE_WB_MISO_I
);
end generate code_cache_present;
code_cache_missing:
if CODE_CACHE_LINES = 0 generate
icache_miso.mwait <= '0';
icache_miso.rd_data <= (others => '0');
-- FIXME a missing code cache should be replaced by a WB bridge.
CODE_WB_MOSI_O.cyc <= '0';
CODE_WB_MOSI_O.stb <= '0';
icache_ctrl_miso.present <= '0';
end generate code_cache_missing;
-- Code TCM ------------------------------------------------------------
tcm_code_present:
if TCM_CODE_SIZE > 0 generate
-- Arbiter: share Code TCM between Code and Data space accesses.
-- note that Data accesses have priority necessarily.
code_arbiter: entity work.ION_CTCM_ARBITER
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
MASTER_D_CE_I => data_ce(2),
MASTER_D_MOSI_I => data_mosi,
MASTER_D_MISO_O => ctcm_d_miso,
MASTER_C_CE_I => code_ce(0),
MASTER_C_MOSI_I => code_mosi,
MASTER_C_MISO_O => ctcm_c_miso,
SLAVE_MOSI_O => ctcm_mosi,
SLAVE_MISO_I => ctcm_miso
);
-- Code TCM block.
code_tcm: entity work.ION_TCM_CODE
generic map (
SIZE => TCM_CODE_SIZE,
INIT_DATA => TCM_CODE_INIT
)
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
EN_I => code_ce(0),
MEM_MOSI_I => ctcm_mosi,
MEM_MISO_O => ctcm_miso
);
end generate tcm_code_present;
tcm_code_missing:
if TCM_CODE_SIZE = 0 generate
ctcm_miso.mwait <= '0';
ctcm_miso.rd_data <= (others => '0');
end generate tcm_code_missing;
--------------------------------------------------------------------------------
-- Data Bus interconnect.
-- Address decoding --------------------------------------------------------
-- Decode the index of the slave being addressed.
data_mux_ctrl <=
"001" when adecode(data_mosi.addr, DTCM_BASE, DTCM_ASIZE) = '1' else
"011" when adecode(data_mosi.addr, DCTCM_BASE, CTCM_ASIZE) = '1' else
"010" when cached(data_mosi.addr) = '1' else
"100" when adecode(data_mosi.addr, DWB_BASE, DWB_ASIZE) = '1' else
"100";
-- Convert slave index to one-hot enable signal vector.
with data_mux_ctrl select data_ce <=
"0001" when "001",
"0010" when "010",
"0100" when "011",
"1000" when "100",
"0000" when others;
-- Data MISO multiplexor -----------------------------------------------
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
data_mux_ctrl_reg <= (others => '0');
elsif data_mosi.rd_en='1' or data_mosi.wr_be/="0000" then
data_mux_ctrl_reg <= data_mux_ctrl;
end if;
end if;
end process;
with data_mux_ctrl_reg select data_miso <=
dtcm_miso when "001",
dcache_miso when "010",
ctcm_d_miso when "011",
ucd_wb_miso when "100",
void_miso when others;
-- Data cache ----------------------------------------------------------
data_cache_present:
if DATA_CACHE_LINES > 0 generate
data_cache: entity work.ION_CACHE
generic map (
NUM_LINES => DATA_CACHE_LINES
)
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
-- FIXME there should be a MISO for each cache in the control port
CACHE_CTRL_MOSI_I => cache_ctrl_mosi,
CACHE_CTRL_MISO_O => dcache_ctrl_miso,
CE_I => data_ce(1),
CPU_MOSI_I => data_mosi,
CPU_MISO_O => dcache_miso,
MEM_MOSI_O => DATA_WB_MOSI_O,
MEM_MISO_I => DATA_WB_MISO_I
);
end generate data_cache_present;
data_cache_missing:
if DATA_CACHE_LINES = 0 generate
dcache_miso.mwait <= '0';
dcache_miso.rd_data <= (others => '0');
-- FIXME a missing data cache should be replaced by a WB bridge.
DATA_WB_MOSI_O.cyc <= '0';
DATA_WB_MOSI_O.stb <= '0';
dcache_ctrl_miso.present <= '0';
end generate data_cache_missing;
-- Data TCM ------------------------------------------------------------
tcm_data_present:
if TCM_DATA_SIZE > 0 generate
data_tcm: entity work.ION_TCM_DATA
generic map (
SIZE => TCM_DATA_SIZE,
INIT_DATA => TCM_DATA_INIT
)
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
EN_I => data_ce(0),
MEM_MOSI_I => data_mosi,
MEM_MISO_O => dtcm_miso
);
end generate tcm_data_present;
tcm_data_missing:
if TCM_DATA_SIZE = 0 generate
dtcm_miso.mwait <= '0';
dtcm_miso.rd_data <= (others => '0');
end generate tcm_data_missing;
-- Wishbone Bridge ---------------------------------------------------------
-- The CPU side of the WB bridge will only be enabled if addressed.
with data_ce(3) select ucd_wb_mosi.rd_en <=
data_mosi.rd_en when '1',
'0' when others;
with data_ce(3) select ucd_wb_mosi.wr_be <=
data_mosi.wr_be when '1',
"0000" when others;
ucd_wb_mosi.addr <= data_mosi.addr;
ucd_wb_mosi.wr_data <= data_mosi.wr_data;
-- WB bridge instance.
data_wb_bridge: entity work.ION_WISHBONE_BRIDGE
port map (
CLK_I => CLK_I,
RESET_I => RESET_I,
ION_MOSI_I => ucd_wb_mosi,
ION_MISO_O => ucd_wb_miso,
WISHBONE_MOSI_O => DATA_UC_WB_MOSI_O,
WISHBONE_MISO_I => DATA_UC_WB_MISO_I
);
end architecture rtl;
|
-- megafunction wizard: %RAM initializer%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMEM_INIT
-- ============================================================
-- File Name: ram_init.vhd
-- Megafunction Name(s):
-- ALTMEM_INIT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altmem_init CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone III" INIT_TO_ZERO="YES" NUMWORDS=256 PORT_ROM_DATA_READY="PORT_UNUSED" ROM_READ_LATENCY=1 WIDTH=8 WIDTHAD=8 clock dataout init init_busy ram_address ram_wren
--VERSION_BEGIN 12.1SP1 cbx_altmem_init 2013:01:31:18:04:58:SJ cbx_altsyncram 2013:01:31:18:04:59:SJ cbx_cycloneii 2013:01:31:18:04:59:SJ cbx_lpm_add_sub 2013:01:31:18:04:59:SJ cbx_lpm_compare 2013:01:31:18:04:59:SJ cbx_lpm_counter 2013:01:31:18:04:59:SJ cbx_lpm_decode 2013:01:31:18:04:59:SJ cbx_lpm_mux 2013:01:31:18:04:59:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:04:59:SJ cbx_stratixii 2013:01:31:18:04:59:SJ cbx_stratixiii 2013:01:31:18:05:00:SJ cbx_stratixv 2013:01:31:18:05:00:SJ cbx_util_mgl 2013:01:31:18:04:59:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_compare 2 lpm_counter 2 reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ram_init_meminit_m6k IS
PORT
(
clock : IN STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
init : IN STD_LOGIC;
init_busy : OUT STD_LOGIC;
ram_address : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
ram_wren : OUT STD_LOGIC
);
END ram_init_meminit_m6k;
ARCHITECTURE RTL OF ram_init_meminit_m6k IS
SIGNAL capture_init : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL prev_state : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_prev_state_w_lg_w_q_range41w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_prev_state_w_lg_w_q_range40w42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_prev_state_w_q_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_prev_state_w_q_range41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_d : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL state_reg : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_state_reg_sclr : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL wire_state_reg_sload : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL wire_state_reg_w_lg_w_q_range2w7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_lg_w_q_range1w3w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_lg_w_q_range22w24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_lg_w_q_range31w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_q_range1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_q_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_q_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_q_range31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_cmpr_aeb : STD_LOGIC;
SIGNAL wire_addr_cmpr_alb : STD_LOGIC;
SIGNAL wire_addr_cmpr_datab : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_wait_cmpr_aeb : STD_LOGIC;
SIGNAL wire_wait_cmpr_alb : STD_LOGIC;
SIGNAL wire_gnd_vector : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_ctr_cnt_en : STD_LOGIC;
SIGNAL wire_addr_ctr_q : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_wait_ctr_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_wait_ctr_sclr : STD_LOGIC;
SIGNAL wire_w_lg_ram_addr_state44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_init38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL addrct_eq_numwords : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL addrct_lt_numwords : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL clken : STD_LOGIC;
SIGNAL done_state : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL idle_state : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL ram_addr_state : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL ram_write_state : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reset_state_machine : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL state_machine_clken : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL waitct_eq_latency : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL waitct_lt_latency : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT lpm_counter
GENERIC
(
lpm_avalue : STRING := "0";
lpm_direction : STRING := "DEFAULT";
lpm_modulus : NATURAL := 0;
lpm_port_updown : STRING := "PORT_CONNECTIVITY";
lpm_pvalue : STRING := "0";
lpm_svalue : STRING := "0";
lpm_width : NATURAL;
lpm_type : STRING := "lpm_counter"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aload : IN STD_LOGIC := '0';
aset : IN STD_LOGIC := '0';
cin : IN STD_LOGIC := '1';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
cnt_en : IN STD_LOGIC := '1';
cout : OUT STD_LOGIC;
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
eq : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
sclr : IN STD_LOGIC := '0';
sload : IN STD_LOGIC := '0';
sset : IN STD_LOGIC := '0';
updown : IN STD_LOGIC := '1'
);
END COMPONENT;
BEGIN
wire_gnd_vector <= "0";
wire_w_lg_init38w(0) <= init OR capture_init(0);
addrct_eq_numwords(0) <= wire_addr_cmpr_aeb;
addrct_lt_numwords(0) <= wire_addr_cmpr_alb;
clken <= '1';
dataout <= (OTHERS => '0');
done_state(0) <= (state_reg(1) AND state_reg(0));
idle_state(0) <= ((NOT state_reg(1)) AND wire_state_reg_w_lg_w_q_range1w3w(0));
init_busy <= capture_init(0);
ram_addr_state(0) <= ((NOT state_reg(1)) AND state_reg(0));
ram_address <= wire_addr_ctr_q;
ram_wren <= ((NOT prev_state(1)) AND prev_state(0));
ram_write_state(0) <= wire_state_reg_w_lg_w_q_range2w7w(0);
reset_state_machine(0) <= (ram_write_state(0) AND addrct_lt_numwords(0));
state_machine_clken(0) <= (clken AND (((idle_state(0) AND capture_init(0)) OR (done_state(0) AND waitct_eq_latency(0))) OR (capture_init(0) AND (((NOT (ram_addr_state(0) AND waitct_lt_latency(0))) OR (ram_addr_state(0) AND waitct_eq_latency(0))) OR (ram_write_state(0) AND addrct_eq_numwords(0))))));
waitct_eq_latency(0) <= wire_wait_cmpr_aeb;
waitct_lt_latency(0) <= wire_wait_cmpr_alb;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN capture_init(0) <= (wire_w_lg_init38w(0) AND (NOT done_state(0)));
END IF;
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN prev_state <= state_reg;
END IF;
END IF;
END PROCESS;
wire_prev_state_w_lg_w_q_range41w43w(0) <= wire_prev_state_w_q_range41w(0) AND wire_prev_state_w_lg_w_q_range40w42w(0);
wire_prev_state_w_lg_w_q_range40w42w(0) <= NOT wire_prev_state_w_q_range40w(0);
wire_prev_state_w_q_range40w(0) <= prev_state(0);
wire_prev_state_w_q_range41w(0) <= prev_state(1);
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN
IF (state_machine_clken(0) = '1') THEN
IF (wire_state_reg_sclr(0) = '1') THEN state_reg(0) <= '0';
ELSIF (wire_state_reg_sload(0) = '1') THEN state_reg(0) <= '1';
ELSE state_reg(0) <= wire_state_reg_d(0);
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN
IF (state_machine_clken(0) = '1') THEN
IF (wire_state_reg_sclr(1) = '1') THEN state_reg(1) <= '0';
ELSIF (wire_state_reg_sload(1) = '1') THEN state_reg(1) <= '1';
ELSE state_reg(1) <= wire_state_reg_d(1);
END IF;
END IF;
END IF;
END PROCESS;
wire_state_reg_d <= ( wire_state_reg_w_lg_w_q_range31w33w & wire_state_reg_w_lg_w_q_range22w24w);
wire_state_reg_sclr <= ( reset_state_machine & "0");
wire_state_reg_sload <= ( "0" & reset_state_machine);
wire_state_reg_w_lg_w_q_range2w7w(0) <= wire_state_reg_w_q_range2w(0) AND wire_state_reg_w_lg_w_q_range1w3w(0);
wire_state_reg_w_lg_w_q_range1w3w(0) <= NOT wire_state_reg_w_q_range1w(0);
wire_state_reg_w_lg_w_q_range22w24w(0) <= NOT wire_state_reg_w_q_range22w(0);
wire_state_reg_w_lg_w_q_range31w33w(0) <= wire_state_reg_w_q_range31w(0) XOR wire_state_reg_w_q_range22w(0);
wire_state_reg_w_q_range1w(0) <= state_reg(0);
wire_state_reg_w_q_range2w(0) <= state_reg(1);
wire_state_reg_w_q_range22w(0) <= state_reg(0);
wire_state_reg_w_q_range31w(0) <= state_reg(1);
wire_addr_cmpr_datab <= (OTHERS => '1');
addr_cmpr : lpm_compare
GENERIC MAP (
LPM_WIDTH => 8
)
PORT MAP (
aeb => wire_addr_cmpr_aeb,
alb => wire_addr_cmpr_alb,
dataa => wire_addr_ctr_q,
datab => wire_addr_cmpr_datab
);
wait_cmpr : lpm_compare
GENERIC MAP (
LPM_WIDTH => 1
)
PORT MAP (
aeb => wire_wait_cmpr_aeb,
alb => wire_wait_cmpr_alb,
dataa => wire_wait_ctr_q,
datab => wire_gnd_vector
);
wire_addr_ctr_cnt_en <= wire_prev_state_w_lg_w_q_range41w43w(0);
addr_ctr : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 256,
lpm_port_updown => "PORT_UNUSED",
lpm_width => 8
)
PORT MAP (
clk_en => clken,
clock => clock,
cnt_en => wire_addr_ctr_cnt_en,
q => wire_addr_ctr_q,
sclr => idle_state(0)
);
wire_wait_ctr_sclr <= wire_w_lg_ram_addr_state44w(0);
wire_w_lg_ram_addr_state44w(0) <= NOT ram_addr_state(0);
wait_ctr : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 1,
lpm_port_updown => "PORT_UNUSED",
lpm_width => 1
)
PORT MAP (
clk_en => clken,
clock => clock,
cnt_en => ram_addr_state(0),
q => wire_wait_ctr_q,
sclr => wire_wait_ctr_sclr
);
END RTL; --ram_init_meminit_m6k
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ram_init IS
PORT
(
clock : IN STD_LOGIC ;
init : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
init_busy : OUT STD_LOGIC ;
ram_address : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
ram_wren : OUT STD_LOGIC
);
END ram_init;
ARCHITECTURE RTL OF ram_init IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC ;
COMPONENT ram_init_meminit_m6k
PORT (
clock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
init : IN STD_LOGIC ;
init_busy : OUT STD_LOGIC ;
ram_address : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
ram_wren : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
dataout <= sub_wire0(7 DOWNTO 0);
init_busy <= sub_wire1;
ram_address <= sub_wire2(7 DOWNTO 0);
ram_wren <= sub_wire3;
ram_init_meminit_m6k_component : ram_init_meminit_m6k
PORT MAP (
clock => clock,
init => init,
dataout => sub_wire0,
init_busy => sub_wire1,
ram_address => sub_wire2,
ram_wren => sub_wire3
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: INIT_FILE STRING "UNUSED"
-- Retrieval info: CONSTANT: INIT_TO_ZERO STRING "YES"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmem_init"
-- Retrieval info: CONSTANT: NUMWORDS NUMERIC "256"
-- Retrieval info: CONSTANT: PORT_ROM_DATA_READY STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: ROM_READ_LATENCY NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTHAD NUMERIC "8"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL "dataout[7..0]"
-- Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0
-- Retrieval info: USED_PORT: init 0 0 0 0 INPUT NODEFVAL "init"
-- Retrieval info: CONNECT: @init 0 0 0 0 init 0 0 0 0
-- Retrieval info: USED_PORT: init_busy 0 0 0 0 OUTPUT NODEFVAL "init_busy"
-- Retrieval info: CONNECT: init_busy 0 0 0 0 @init_busy 0 0 0 0
-- Retrieval info: USED_PORT: ram_address 0 0 8 0 OUTPUT NODEFVAL "ram_address[7..0]"
-- Retrieval info: CONNECT: ram_address 0 0 8 0 @ram_address 0 0 8 0
-- Retrieval info: USED_PORT: ram_wren 0 0 0 0 OUTPUT NODEFVAL "ram_wren"
-- Retrieval info: CONNECT: ram_wren 0 0 0 0 @ram_wren 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init_inst.vhd TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.inc TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.cmp TRUE TRUE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %RAM initializer%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMEM_INIT
-- ============================================================
-- File Name: ram_init.vhd
-- Megafunction Name(s):
-- ALTMEM_INIT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altmem_init CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone III" INIT_TO_ZERO="YES" NUMWORDS=256 PORT_ROM_DATA_READY="PORT_UNUSED" ROM_READ_LATENCY=1 WIDTH=8 WIDTHAD=8 clock dataout init init_busy ram_address ram_wren
--VERSION_BEGIN 12.1SP1 cbx_altmem_init 2013:01:31:18:04:58:SJ cbx_altsyncram 2013:01:31:18:04:59:SJ cbx_cycloneii 2013:01:31:18:04:59:SJ cbx_lpm_add_sub 2013:01:31:18:04:59:SJ cbx_lpm_compare 2013:01:31:18:04:59:SJ cbx_lpm_counter 2013:01:31:18:04:59:SJ cbx_lpm_decode 2013:01:31:18:04:59:SJ cbx_lpm_mux 2013:01:31:18:04:59:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:04:59:SJ cbx_stratixii 2013:01:31:18:04:59:SJ cbx_stratixiii 2013:01:31:18:05:00:SJ cbx_stratixv 2013:01:31:18:05:00:SJ cbx_util_mgl 2013:01:31:18:04:59:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_compare 2 lpm_counter 2 reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ram_init_meminit_m6k IS
PORT
(
clock : IN STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
init : IN STD_LOGIC;
init_busy : OUT STD_LOGIC;
ram_address : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
ram_wren : OUT STD_LOGIC
);
END ram_init_meminit_m6k;
ARCHITECTURE RTL OF ram_init_meminit_m6k IS
SIGNAL capture_init : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL prev_state : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_prev_state_w_lg_w_q_range41w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_prev_state_w_lg_w_q_range40w42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_prev_state_w_q_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_prev_state_w_q_range41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_d : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL state_reg : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_state_reg_sclr : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL wire_state_reg_sload : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL wire_state_reg_w_lg_w_q_range2w7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_lg_w_q_range1w3w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_lg_w_q_range22w24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_lg_w_q_range31w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_q_range1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_q_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_q_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_q_range31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_cmpr_aeb : STD_LOGIC;
SIGNAL wire_addr_cmpr_alb : STD_LOGIC;
SIGNAL wire_addr_cmpr_datab : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_wait_cmpr_aeb : STD_LOGIC;
SIGNAL wire_wait_cmpr_alb : STD_LOGIC;
SIGNAL wire_gnd_vector : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_ctr_cnt_en : STD_LOGIC;
SIGNAL wire_addr_ctr_q : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_wait_ctr_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_wait_ctr_sclr : STD_LOGIC;
SIGNAL wire_w_lg_ram_addr_state44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_init38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL addrct_eq_numwords : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL addrct_lt_numwords : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL clken : STD_LOGIC;
SIGNAL done_state : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL idle_state : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL ram_addr_state : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL ram_write_state : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reset_state_machine : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL state_machine_clken : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL waitct_eq_latency : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL waitct_lt_latency : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT lpm_counter
GENERIC
(
lpm_avalue : STRING := "0";
lpm_direction : STRING := "DEFAULT";
lpm_modulus : NATURAL := 0;
lpm_port_updown : STRING := "PORT_CONNECTIVITY";
lpm_pvalue : STRING := "0";
lpm_svalue : STRING := "0";
lpm_width : NATURAL;
lpm_type : STRING := "lpm_counter"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aload : IN STD_LOGIC := '0';
aset : IN STD_LOGIC := '0';
cin : IN STD_LOGIC := '1';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
cnt_en : IN STD_LOGIC := '1';
cout : OUT STD_LOGIC;
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
eq : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
sclr : IN STD_LOGIC := '0';
sload : IN STD_LOGIC := '0';
sset : IN STD_LOGIC := '0';
updown : IN STD_LOGIC := '1'
);
END COMPONENT;
BEGIN
wire_gnd_vector <= "0";
wire_w_lg_init38w(0) <= init OR capture_init(0);
addrct_eq_numwords(0) <= wire_addr_cmpr_aeb;
addrct_lt_numwords(0) <= wire_addr_cmpr_alb;
clken <= '1';
dataout <= (OTHERS => '0');
done_state(0) <= (state_reg(1) AND state_reg(0));
idle_state(0) <= ((NOT state_reg(1)) AND wire_state_reg_w_lg_w_q_range1w3w(0));
init_busy <= capture_init(0);
ram_addr_state(0) <= ((NOT state_reg(1)) AND state_reg(0));
ram_address <= wire_addr_ctr_q;
ram_wren <= ((NOT prev_state(1)) AND prev_state(0));
ram_write_state(0) <= wire_state_reg_w_lg_w_q_range2w7w(0);
reset_state_machine(0) <= (ram_write_state(0) AND addrct_lt_numwords(0));
state_machine_clken(0) <= (clken AND (((idle_state(0) AND capture_init(0)) OR (done_state(0) AND waitct_eq_latency(0))) OR (capture_init(0) AND (((NOT (ram_addr_state(0) AND waitct_lt_latency(0))) OR (ram_addr_state(0) AND waitct_eq_latency(0))) OR (ram_write_state(0) AND addrct_eq_numwords(0))))));
waitct_eq_latency(0) <= wire_wait_cmpr_aeb;
waitct_lt_latency(0) <= wire_wait_cmpr_alb;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN capture_init(0) <= (wire_w_lg_init38w(0) AND (NOT done_state(0)));
END IF;
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN prev_state <= state_reg;
END IF;
END IF;
END PROCESS;
wire_prev_state_w_lg_w_q_range41w43w(0) <= wire_prev_state_w_q_range41w(0) AND wire_prev_state_w_lg_w_q_range40w42w(0);
wire_prev_state_w_lg_w_q_range40w42w(0) <= NOT wire_prev_state_w_q_range40w(0);
wire_prev_state_w_q_range40w(0) <= prev_state(0);
wire_prev_state_w_q_range41w(0) <= prev_state(1);
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN
IF (state_machine_clken(0) = '1') THEN
IF (wire_state_reg_sclr(0) = '1') THEN state_reg(0) <= '0';
ELSIF (wire_state_reg_sload(0) = '1') THEN state_reg(0) <= '1';
ELSE state_reg(0) <= wire_state_reg_d(0);
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN
IF (state_machine_clken(0) = '1') THEN
IF (wire_state_reg_sclr(1) = '1') THEN state_reg(1) <= '0';
ELSIF (wire_state_reg_sload(1) = '1') THEN state_reg(1) <= '1';
ELSE state_reg(1) <= wire_state_reg_d(1);
END IF;
END IF;
END IF;
END PROCESS;
wire_state_reg_d <= ( wire_state_reg_w_lg_w_q_range31w33w & wire_state_reg_w_lg_w_q_range22w24w);
wire_state_reg_sclr <= ( reset_state_machine & "0");
wire_state_reg_sload <= ( "0" & reset_state_machine);
wire_state_reg_w_lg_w_q_range2w7w(0) <= wire_state_reg_w_q_range2w(0) AND wire_state_reg_w_lg_w_q_range1w3w(0);
wire_state_reg_w_lg_w_q_range1w3w(0) <= NOT wire_state_reg_w_q_range1w(0);
wire_state_reg_w_lg_w_q_range22w24w(0) <= NOT wire_state_reg_w_q_range22w(0);
wire_state_reg_w_lg_w_q_range31w33w(0) <= wire_state_reg_w_q_range31w(0) XOR wire_state_reg_w_q_range22w(0);
wire_state_reg_w_q_range1w(0) <= state_reg(0);
wire_state_reg_w_q_range2w(0) <= state_reg(1);
wire_state_reg_w_q_range22w(0) <= state_reg(0);
wire_state_reg_w_q_range31w(0) <= state_reg(1);
wire_addr_cmpr_datab <= (OTHERS => '1');
addr_cmpr : lpm_compare
GENERIC MAP (
LPM_WIDTH => 8
)
PORT MAP (
aeb => wire_addr_cmpr_aeb,
alb => wire_addr_cmpr_alb,
dataa => wire_addr_ctr_q,
datab => wire_addr_cmpr_datab
);
wait_cmpr : lpm_compare
GENERIC MAP (
LPM_WIDTH => 1
)
PORT MAP (
aeb => wire_wait_cmpr_aeb,
alb => wire_wait_cmpr_alb,
dataa => wire_wait_ctr_q,
datab => wire_gnd_vector
);
wire_addr_ctr_cnt_en <= wire_prev_state_w_lg_w_q_range41w43w(0);
addr_ctr : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 256,
lpm_port_updown => "PORT_UNUSED",
lpm_width => 8
)
PORT MAP (
clk_en => clken,
clock => clock,
cnt_en => wire_addr_ctr_cnt_en,
q => wire_addr_ctr_q,
sclr => idle_state(0)
);
wire_wait_ctr_sclr <= wire_w_lg_ram_addr_state44w(0);
wire_w_lg_ram_addr_state44w(0) <= NOT ram_addr_state(0);
wait_ctr : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 1,
lpm_port_updown => "PORT_UNUSED",
lpm_width => 1
)
PORT MAP (
clk_en => clken,
clock => clock,
cnt_en => ram_addr_state(0),
q => wire_wait_ctr_q,
sclr => wire_wait_ctr_sclr
);
END RTL; --ram_init_meminit_m6k
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ram_init IS
PORT
(
clock : IN STD_LOGIC ;
init : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
init_busy : OUT STD_LOGIC ;
ram_address : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
ram_wren : OUT STD_LOGIC
);
END ram_init;
ARCHITECTURE RTL OF ram_init IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC ;
COMPONENT ram_init_meminit_m6k
PORT (
clock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
init : IN STD_LOGIC ;
init_busy : OUT STD_LOGIC ;
ram_address : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
ram_wren : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
dataout <= sub_wire0(7 DOWNTO 0);
init_busy <= sub_wire1;
ram_address <= sub_wire2(7 DOWNTO 0);
ram_wren <= sub_wire3;
ram_init_meminit_m6k_component : ram_init_meminit_m6k
PORT MAP (
clock => clock,
init => init,
dataout => sub_wire0,
init_busy => sub_wire1,
ram_address => sub_wire2,
ram_wren => sub_wire3
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: INIT_FILE STRING "UNUSED"
-- Retrieval info: CONSTANT: INIT_TO_ZERO STRING "YES"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmem_init"
-- Retrieval info: CONSTANT: NUMWORDS NUMERIC "256"
-- Retrieval info: CONSTANT: PORT_ROM_DATA_READY STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: ROM_READ_LATENCY NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTHAD NUMERIC "8"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL "dataout[7..0]"
-- Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0
-- Retrieval info: USED_PORT: init 0 0 0 0 INPUT NODEFVAL "init"
-- Retrieval info: CONNECT: @init 0 0 0 0 init 0 0 0 0
-- Retrieval info: USED_PORT: init_busy 0 0 0 0 OUTPUT NODEFVAL "init_busy"
-- Retrieval info: CONNECT: init_busy 0 0 0 0 @init_busy 0 0 0 0
-- Retrieval info: USED_PORT: ram_address 0 0 8 0 OUTPUT NODEFVAL "ram_address[7..0]"
-- Retrieval info: CONNECT: ram_address 0 0 8 0 @ram_address 0 0 8 0
-- Retrieval info: USED_PORT: ram_wren 0 0 0 0 OUTPUT NODEFVAL "ram_wren"
-- Retrieval info: CONNECT: ram_wren 0 0 0 0 @ram_wren 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init_inst.vhd TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.inc TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.cmp TRUE TRUE
-- Retrieval info: LIB_FILE: lpm
|
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <[email protected]>
--
-- Create Date: 09/15/2007
-- Last Update: 06/23/2008
-- Project Name: camellia-vhdl
-- Description: Camellia top level module, for 128/192/256-bit keys
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity CAMELLIA256 is
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (0 to 127); -- input data
input_en : in STD_LOGIC; -- input enable
key : in STD_LOGIC_VECTOR (0 to 255); -- key
key_len : in STD_LOGIC_VECTOR (0 to 1); -- key lenght
enc_dec : in STD_LOGIC; -- dec=0 enc, dec=1 dec
output : out STD_LOGIC_VECTOR (0 to 127); -- en/decrypted data
output_rdy : out STD_LOGIC -- output ready
);
end CAMELLIA256;
architecture RTL of CAMELLIA256 is
component KEYSCHED256 is
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
kl_in : in STD_LOGIC_VECTOR (0 to 127);
kr_in : in STD_LOGIC_VECTOR (0 to 127);
kl_out : out STD_LOGIC_VECTOR (0 to 127);
kr_out : out STD_LOGIC_VECTOR (0 to 127);
ka_out : out STD_LOGIC_VECTOR (0 to 127);
kb_out : out STD_LOGIC_VECTOR (0 to 127)
);
end component;
component SIXROUND256 is
generic (
k1e128_offset : INTEGER; -- encryption 128bit
k1e128_shift : INTEGER;
k2e128_offset : INTEGER;
k2e128_shift : INTEGER;
k3e128_offset : INTEGER;
k3e128_shift : INTEGER;
k4e128_offset : INTEGER;
k4e128_shift : INTEGER;
k5e128_offset : INTEGER;
k5e128_shift : INTEGER;
k6e128_offset : INTEGER;
k6e128_shift : INTEGER;
k1d128_offset : INTEGER; -- decryption 128bit
k1d128_shift : INTEGER;
k2d128_offset : INTEGER;
k2d128_shift : INTEGER;
k3d128_offset : INTEGER;
k3d128_shift : INTEGER;
k4d128_offset : INTEGER;
k4d128_shift : INTEGER;
k5d128_offset : INTEGER;
k5d128_shift : INTEGER;
k6d128_offset : INTEGER;
k6d128_shift : INTEGER;
k1e256_offset : INTEGER; -- encryption 192/256bit
k1e256_shift : INTEGER;
k2e256_offset : INTEGER;
k2e256_shift : INTEGER;
k3e256_offset : INTEGER;
k3e256_shift : INTEGER;
k4e256_offset : INTEGER;
k4e256_shift : INTEGER;
k5e256_offset : INTEGER;
k5e256_shift : INTEGER;
k6e256_offset : INTEGER;
k6e256_shift : INTEGER;
k1d256_offset : INTEGER; -- decryption 192/256bit
k1d256_shift : INTEGER;
k2d256_offset : INTEGER;
k2d256_shift : INTEGER;
k3d256_offset : INTEGER;
k3d256_shift : INTEGER;
k4d256_offset : INTEGER;
k4d256_shift : INTEGER;
k5d256_offset : INTEGER;
k5d256_shift : INTEGER;
k6d256_offset : INTEGER;
k6d256_shift : INTEGER
);
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
dec1 : in STD_LOGIC;
k_len1 : in STD_LOGIC_VECTOR (0 to 1);
k1 : in STD_LOGIC_VECTOR (0 to 511);
dec2 : in STD_LOGIC;
k_len2 : in STD_LOGIC_VECTOR (0 to 1);
k2 : in STD_LOGIC_VECTOR (0 to 511);
dec3 : in STD_LOGIC;
k_len3 : in STD_LOGIC_VECTOR (0 to 1);
k3 : in STD_LOGIC_VECTOR (0 to 511);
dec4 : in STD_LOGIC;
k_len4 : in STD_LOGIC_VECTOR (0 to 1);
k4 : in STD_LOGIC_VECTOR (0 to 511);
dec5 : in STD_LOGIC;
k_len5 : in STD_LOGIC_VECTOR (0 to 1);
k5 : in STD_LOGIC_VECTOR (0 to 511);
dec6 : in STD_LOGIC;
k_len6 : in STD_LOGIC_VECTOR (0 to 1);
k6 : in STD_LOGIC_VECTOR (0 to 511);
l_in : in STD_LOGIC_VECTOR (0 to 63);
r_in : in STD_LOGIC_VECTOR (0 to 63);
l_out : out STD_LOGIC_VECTOR (0 to 63);
r_out : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
component FL256 is
generic (
fl_ke128_offset : INTEGER; -- 128bit encryption
fl_ke128_shift : INTEGER;
fli_ke128_offset : INTEGER;
fli_ke128_shift : INTEGER;
fl_kd128_offset : INTEGER; -- 128bit decryption
fl_kd128_shift : INTEGER;
fli_kd128_offset : INTEGER;
fli_kd128_shift : INTEGER;
fl_ke256_offset : INTEGER; -- 192/256bit encryption
fl_ke256_shift : INTEGER;
fli_ke256_offset : INTEGER;
fli_ke256_shift : INTEGER;
fl_kd256_offset : INTEGER; -- 192/256bit decryption
fl_kd256_shift : INTEGER;
fli_kd256_offset : INTEGER;
fli_kd256_shift : INTEGER
);
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
fl_in : in STD_LOGIC_VECTOR (0 to 63);
fli_in : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 511);
k_len : in STD_LOGIC_VECTOR (0 to 1);
dec : in STD_LOGIC;
fl_out : out STD_LOGIC_VECTOR (0 to 63);
fli_out : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
-- input registers
signal reg_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg_kr_int : STD_LOGIC_VECTOR (0 to 127);
signal reg_k_len : STD_LOGIC_VECTOR (0 to 1);
signal reg_dec : STD_LOGIC;
signal reg_rdy : STD_LOGIC;
-- used by pre-whitening
signal kw1_enc : STD_LOGIC_VECTOR (0 to 63);
signal kw2_enc : STD_LOGIC_VECTOR (0 to 63);
signal ka_s111_dec128 : STD_LOGIC_VECTOR (0 to 127);
signal kw1_dec128 : STD_LOGIC_VECTOR (0 to 63);
signal kw2_dec128 : STD_LOGIC_VECTOR (0 to 63);
signal ka_s111_dec256 : STD_LOGIC_VECTOR (0 to 127);
signal kw1_dec256 : STD_LOGIC_VECTOR (0 to 63);
signal kw2_dec256 : STD_LOGIC_VECTOR (0 to 63);
signal kw1 : STD_LOGIC_VECTOR (0 to 63);
signal kw2 : STD_LOGIC_VECTOR (0 to 63);
signal w1 : STD_LOGIC_VECTOR (0 to 63);
signal w2 : STD_LOGIC_VECTOR (0 to 63);
-- used by post-whitening
signal ka_s111_enc128 : STD_LOGIC_VECTOR (0 to 127);
signal kw3_enc128 : STD_LOGIC_VECTOR (0 to 63);
signal kw4_enc128 : STD_LOGIC_VECTOR (0 to 63);
signal ka_s111_enc256 : STD_LOGIC_VECTOR (0 to 127);
signal kw3_enc256 : STD_LOGIC_VECTOR (0 to 63);
signal kw4_enc256 : STD_LOGIC_VECTOR (0 to 63);
signal kw3_dec : STD_LOGIC_VECTOR (0 to 63);
signal kw4_dec : STD_LOGIC_VECTOR (0 to 63);
signal kw3 : STD_LOGIC_VECTOR (0 to 63);
signal kw4 : STD_LOGIC_VECTOR (0 to 63);
signal w3 : STD_LOGIC_VECTOR (0 to 63);
signal w4 : STD_LOGIC_VECTOR (0 to 63);
-- registers used during key schedule
signal reg_a1_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a1_dec : STD_LOGIC;
signal reg_a1_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a1_rdy : STD_LOGIC;
signal reg_a2_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a2_dec : STD_LOGIC;
signal reg_a2_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a2_rdy : STD_LOGIC;
signal reg_a3_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a3_dec : STD_LOGIC;
signal reg_a3_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a3_rdy : STD_LOGIC;
signal reg_a4_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a4_dec : STD_LOGIC;
signal reg_a4_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a4_rdy : STD_LOGIC;
signal reg_a5_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a5_dec : STD_LOGIC;
signal reg_a5_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a5_rdy : STD_LOGIC;
signal reg_a6_m : STD_LOGIC_VECTOR (0 to 127);
signal reg_a6_dec : STD_LOGIC;
signal reg_a6_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_a6_rdy : STD_LOGIC;
-- registers used during 6-rounds and fls
signal reg_b1_dec : STD_LOGIC;
signal reg_b1_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b1_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b1_rdy : STD_LOGIC;
signal reg_b2_dec : STD_LOGIC;
signal reg_b2_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b2_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b2_rdy : STD_LOGIC;
signal reg_b3_dec : STD_LOGIC;
signal reg_b3_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b3_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b3_rdy : STD_LOGIC;
signal reg_b4_dec : STD_LOGIC;
signal reg_b4_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b4_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b4_rdy : STD_LOGIC;
signal reg_b5_dec : STD_LOGIC;
signal reg_b5_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b5_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b5_rdy : STD_LOGIC;
signal reg_b6_dec : STD_LOGIC;
signal reg_b6_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b6_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b6_rdy : STD_LOGIC;
signal reg_b7_dec : STD_LOGIC;
signal reg_b7_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b7_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b7_rdy : STD_LOGIC;
signal reg_b8_dec : STD_LOGIC;
signal reg_b8_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b8_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b8_rdy : STD_LOGIC;
signal reg_b9_dec : STD_LOGIC;
signal reg_b9_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b9_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b9_rdy : STD_LOGIC;
signal reg_b10_dec : STD_LOGIC;
signal reg_b10_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b10_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b10_rdy : STD_LOGIC;
signal reg_b11_dec : STD_LOGIC;
signal reg_b11_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b11_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b11_rdy : STD_LOGIC;
signal reg_b12_dec : STD_LOGIC;
signal reg_b12_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b12_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b12_rdy : STD_LOGIC;
signal reg_b13_dec : STD_LOGIC;
signal reg_b13_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b13_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b13_rdy : STD_LOGIC;
signal reg_b14_dec : STD_LOGIC;
signal reg_b14_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b14_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b14_rdy : STD_LOGIC;
signal reg_b15_dec : STD_LOGIC;
signal reg_b15_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b15_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b15_rdy : STD_LOGIC;
signal reg_b16_dec : STD_LOGIC;
signal reg_b16_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b16_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b16_rdy : STD_LOGIC;
signal reg_b17_dec : STD_LOGIC;
signal reg_b17_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b17_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b17_rdy : STD_LOGIC;
signal reg_b18_dec : STD_LOGIC;
signal reg_b18_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b18_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b18_rdy : STD_LOGIC;
signal reg_b19_dec : STD_LOGIC;
signal reg_b19_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b19_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b19_rdy : STD_LOGIC;
signal reg_b20_dec : STD_LOGIC;
signal reg_b20_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b20_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b20_rdy : STD_LOGIC;
signal reg_b21_dec : STD_LOGIC;
signal reg_b21_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b21_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b21_rdy : STD_LOGIC;
signal reg_b22_dec : STD_LOGIC;
signal reg_b22_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b22_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b22_rdy : STD_LOGIC;
signal reg_b23_dec : STD_LOGIC;
signal reg_b23_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b23_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b23_rdy : STD_LOGIC;
signal reg_b24_dec : STD_LOGIC;
signal reg_b24_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b24_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b24_rdy : STD_LOGIC;
signal reg_b25_dec : STD_LOGIC;
signal reg_b25_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b25_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b25_rdy : STD_LOGIC;
signal reg_b26_dec : STD_LOGIC;
signal reg_b26_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b26_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b26_rdy : STD_LOGIC;
signal reg_b27_dec : STD_LOGIC;
signal reg_b27_k : STD_LOGIC_VECTOR (0 to 511);
signal reg_b27_klen : STD_LOGIC_VECTOR (0 to 1);
signal reg_b27_rdy : STD_LOGIC;
-- registers used for 128bit key encryptions
signal reg_l128_1 : STD_LOGIC_VECTOR (0 to 63);
signal reg_r128_1 : STD_LOGIC_VECTOR (0 to 63);
signal reg_l128_2 : STD_LOGIC_VECTOR (0 to 63);
signal reg_r128_2 : STD_LOGIC_VECTOR (0 to 63);
signal reg_l128_3 : STD_LOGIC_VECTOR (0 to 63);
signal reg_r128_3 : STD_LOGIC_VECTOR (0 to 63);
signal reg_l128_4 : STD_LOGIC_VECTOR (0 to 63);
signal reg_r128_4 : STD_LOGIC_VECTOR (0 to 63);
signal reg_l128_5 : STD_LOGIC_VECTOR (0 to 63);
signal reg_r128_5 : STD_LOGIC_VECTOR (0 to 63);
signal reg_l128_6 : STD_LOGIC_VECTOR (0 to 63);
signal reg_r128_6 : STD_LOGIC_VECTOR (0 to 63);
signal reg_l128_7 : STD_LOGIC_VECTOR (0 to 63);
signal reg_r128_7 : STD_LOGIC_VECTOR (0 to 63);
-- components outputs
signal out_ksched : STD_LOGIC_VECTOR (0 to 511); -- key schedule
signal out_r1l : STD_LOGIC_VECTOR (0 to 63); -- first six-round
signal out_r1r : STD_LOGIC_VECTOR (0 to 63);
signal out_r2l : STD_LOGIC_VECTOR (0 to 63); -- second six-round
signal out_r2r : STD_LOGIC_VECTOR (0 to 63);
signal out_r3l : STD_LOGIC_VECTOR (0 to 63); -- third six-round
signal out_r3r : STD_LOGIC_VECTOR (0 to 63);
signal out_r4l : STD_LOGIC_VECTOR (0 to 63); -- fourth six-round
signal out_r4r : STD_LOGIC_VECTOR (0 to 63);
signal out_fl1l : STD_LOGIC_VECTOR (0 to 63); -- first fl
signal out_fl1r : STD_LOGIC_VECTOR (0 to 63);
signal out_fl2l : STD_LOGIC_VECTOR (0 to 63); -- second fl
signal out_fl2r : STD_LOGIC_VECTOR (0 to 63);
signal out_fl3l : STD_LOGIC_VECTOR (0 to 63); -- third fl
signal out_fl3r : STD_LOGIC_VECTOR (0 to 63);
-- misc signals
signal kr_int : STD_LOGIC_VECTOR (0 to 127);
-- constants
constant KL_OFFSET : INTEGER := 0;
constant KR_OFFSET : INTEGER := 128;
constant KA_OFFSET : INTEGER := 256;
constant KB_OFFSET : INTEGER := 384;
begin
KEY_SCHED: KEYSCHED256
PORT MAP (
reset => reset,
clk => clk,
kl_in => reg_kl,
kr_in => reg_kr_int,
kl_out => out_ksched(KL_OFFSET to KL_OFFSET+127),
kr_out => out_ksched(KR_OFFSET to KR_OFFSET+127),
ka_out => out_ksched(KA_OFFSET to KA_OFFSET+127),
kb_out => out_ksched(KB_OFFSET to KB_OFFSET+127)
);
SIX1: SIXROUND256
GENERIC MAP(
k1e128_offset => KA_OFFSET,
k1e128_shift => 0,
k2e128_offset => KA_OFFSET,
k2e128_shift => 0,
k3e128_offset => KL_OFFSET,
k3e128_shift => 15,
k4e128_offset => KL_OFFSET,
k4e128_shift => 15,
k5e128_offset => KA_OFFSET,
k5e128_shift => 15,
k6e128_offset => KA_OFFSET,
k6e128_shift => 15,
k1d128_offset => KL_OFFSET,
k1d128_shift => 111,
k2d128_offset => KL_OFFSET,
k2d128_shift => 111,
k3d128_offset => KA_OFFSET,
k3d128_shift => 94,
k4d128_offset => KA_OFFSET,
k4d128_shift => 94,
k5d128_offset => KL_OFFSET,
k5d128_shift => 94,
k6d128_offset => KL_OFFSET,
k6d128_shift => 94,
k1e256_offset => KB_OFFSET,
k1e256_shift => 0,
k2e256_offset => KB_OFFSET,
k2e256_shift => 0,
k3e256_offset => KR_OFFSET,
k3e256_shift => 15,
k4e256_offset => KR_OFFSET,
k4e256_shift => 15,
k5e256_offset => KA_OFFSET,
k5e256_shift => 15,
k6e256_offset => KA_OFFSET,
k6e256_shift => 15,
k1d256_offset => KL_OFFSET,
k1d256_shift => 111,
k2d256_offset => KL_OFFSET,
k2d256_shift => 111,
k3d256_offset => KA_OFFSET,
k3d256_shift => 94,
k4d256_offset => KA_OFFSET,
k4d256_shift => 94,
k5d256_offset => KR_OFFSET,
k5d256_shift => 94,
k6d256_offset => KR_OFFSET,
k6d256_shift => 94
)
PORT MAP(
reset => reset,
clk => clk,
dec1 => reg_a6_dec,
k_len1 => reg_a6_klen,
k1 => out_ksched,
dec2 => reg_b1_dec,
k_len2 => reg_b1_klen,
k2 => reg_b1_k,
dec3 => reg_b2_dec,
k_len3 => reg_b2_klen,
k3 => reg_b2_k,
dec4 => reg_b3_dec,
k_len4 => reg_b3_klen,
k4 => reg_b3_k,
dec5 => reg_b4_dec,
k_len5 => reg_b4_klen,
k5 => reg_b4_k,
dec6 => reg_b5_dec,
k_len6 => reg_b5_klen,
k6 => reg_b5_k,
l_in => w1,
r_in => w2,
l_out => out_r1l,
r_out => out_r1r
);
SIX2: SIXROUND256
GENERIC MAP(
k1e128_offset => KL_OFFSET,
k1e128_shift => 45,
k2e128_offset => KL_OFFSET,
k2e128_shift => 45,
k3e128_offset => KA_OFFSET,
k3e128_shift => 45,
k4e128_offset => KL_OFFSET,
k4e128_shift => 60,
k5e128_offset => KA_OFFSET,
k5e128_shift => 60,
k6e128_offset => KA_OFFSET,
k6e128_shift => 60,
k1d128_offset => KA_OFFSET,
k1d128_shift => 60,
k2d128_offset => KA_OFFSET,
k2d128_shift => 60,
k3d128_offset => KL_OFFSET,
k3d128_shift => 60,
k4d128_offset => KA_OFFSET,
k4d128_shift => 45,
k5d128_offset => KL_OFFSET,
k5d128_shift => 45,
k6d128_offset => KL_OFFSET,
k6d128_shift => 45,
k1e256_offset => KB_OFFSET,
k1e256_shift => 30,
k2e256_offset => KB_OFFSET,
k2e256_shift => 30,
k3e256_offset => KL_OFFSET,
k3e256_shift => 45,
k4e256_offset => KL_OFFSET,
k4e256_shift => 45,
k5e256_offset => KA_OFFSET,
k5e256_shift => 45,
k6e256_offset => KA_OFFSET,
k6e256_shift => 45,
k1d256_offset => KL_OFFSET,
k1d256_shift => 77,
k2d256_offset => KL_OFFSET,
k2d256_shift => 77,
k3d256_offset => KB_OFFSET,
k3d256_shift => 60,
k4d256_offset => KB_OFFSET,
k4d256_shift => 60,
k5d256_offset => KR_OFFSET,
k5d256_shift => 60,
k6d256_offset => KR_OFFSET,
k6d256_shift => 60
)
PORT MAP(
reset => reset,
clk => clk,
dec1 => reg_b7_dec,
k_len1 => reg_b7_klen,
k1 => reg_b7_k,
dec2 => reg_b8_dec,
k_len2 => reg_b8_klen,
k2 => reg_b8_k,
dec3 => reg_b9_dec,
k_len3 => reg_b9_klen,
k3 => reg_b9_k,
dec4 => reg_b10_dec,
k_len4 => reg_b10_klen,
k4 => reg_b10_k,
dec5 => reg_b11_dec,
k_len5 => reg_b11_klen,
k5 => reg_b11_k,
dec6 => reg_b12_dec,
k_len6 => reg_b12_klen,
k6 => reg_b12_k,
l_in => out_fl1l,
r_in => out_fl1r,
l_out => out_r2l,
r_out => out_r2r
);
SIX3: SIXROUND256
GENERIC MAP(
k1e128_offset => KL_OFFSET,
k1e128_shift => 94,
k2e128_offset => KL_OFFSET,
k2e128_shift => 94,
k3e128_offset => KA_OFFSET,
k3e128_shift => 94,
k4e128_offset => KA_OFFSET,
k4e128_shift => 94,
k5e128_offset => KL_OFFSET,
k5e128_shift => 111,
k6e128_offset => KL_OFFSET,
k6e128_shift => 111,
k1d128_offset => KA_OFFSET,
k1d128_shift => 15,
k2d128_offset => KA_OFFSET,
k2d128_shift => 15,
k3d128_offset => KL_OFFSET,
k3d128_shift => 15,
k4d128_offset => KL_OFFSET,
k4d128_shift => 15,
k5d128_offset => KA_OFFSET,
k5d128_shift => 0,
k6d128_offset => KA_OFFSET,
k6d128_shift => 0,
k1e256_offset => KR_OFFSET,
k1e256_shift => 60,
k2e256_offset => KR_OFFSET,
k2e256_shift => 60,
k3e256_offset => KB_OFFSET,
k3e256_shift => 60,
k4e256_offset => KB_OFFSET,
k4e256_shift => 60,
k5e256_offset => KL_OFFSET,
k5e256_shift => 77,
k6e256_offset => KL_OFFSET,
k6e256_shift => 77,
k1d256_offset => KA_OFFSET,
k1d256_shift => 45,
k2d256_offset => KA_OFFSET,
k2d256_shift => 45,
k3d256_offset => KL_OFFSET,
k3d256_shift => 45,
k4d256_offset => KL_OFFSET,
k4d256_shift => 45,
k5d256_offset => KB_OFFSET,
k5d256_shift => 30,
k6d256_offset => KB_OFFSET,
k6d256_shift => 30
)
PORT MAP(
reset => reset,
clk => clk,
dec1 => reg_b14_dec,
k_len1 => reg_b14_klen,
k1 => reg_b14_k,
dec2 => reg_b15_dec,
k_len2 => reg_b15_klen,
k2 => reg_b15_k,
dec3 => reg_b16_dec,
k_len3 => reg_b16_klen,
k3 => reg_b16_k,
dec4 => reg_b17_dec,
k_len4 => reg_b17_klen,
k4 => reg_b17_k,
dec5 => reg_b18_dec,
k_len5 => reg_b18_klen,
k5 => reg_b18_k,
dec6 => reg_b19_dec,
k_len6 => reg_b19_klen,
k6 => reg_b19_k,
l_in => out_fl2l,
r_in => out_fl2r,
l_out => out_r3l,
r_out => out_r3r
);
SIX4: SIXROUND256
GENERIC MAP(
k1e128_offset => 0,
k1e128_shift => 0,
k2e128_offset => 0,
k2e128_shift => 0,
k3e128_offset => 0,
k3e128_shift => 0,
k4e128_offset => 0,
k4e128_shift => 0,
k5e128_offset => 0,
k5e128_shift => 0,
k6e128_offset => 0,
k6e128_shift => 0,
k1d128_offset => 0,
k1d128_shift => 0,
k2d128_offset => 0,
k2d128_shift => 0,
k3d128_offset => 0,
k3d128_shift => 0,
k4d128_offset => 0,
k4d128_shift => 0,
k5d128_offset => 0,
k5d128_shift => 0,
k6d128_offset => 0,
k6d128_shift => 0,
k1e256_offset => KR_OFFSET,
k1e256_shift => 94,
k2e256_offset => KR_OFFSET,
k2e256_shift => 94,
k3e256_offset => KA_OFFSET,
k3e256_shift => 94,
k4e256_offset => KA_OFFSET,
k4e256_shift => 94,
k5e256_offset => KL_OFFSET,
k5e256_shift => 111,
k6e256_offset => KL_OFFSET,
k6e256_shift => 111,
k1d256_offset => KA_OFFSET,
k1d256_shift => 15,
k2d256_offset => KA_OFFSET,
k2d256_shift => 15,
k3d256_offset => KR_OFFSET,
k3d256_shift => 15,
k4d256_offset => KR_OFFSET,
k4d256_shift => 15,
k5d256_offset => KB_OFFSET,
k5d256_shift => 0,
k6d256_offset => KB_OFFSET,
k6d256_shift => 0
)
PORT MAP(
reset => reset,
clk => clk,
dec1 => reg_b21_dec,
k_len1 => reg_b21_klen,
k1 => reg_b21_k,
dec2 => reg_b22_dec,
k_len2 => reg_b22_klen,
k2 => reg_b22_k,
dec3 => reg_b23_dec,
k_len3 => reg_b23_klen,
k3 => reg_b23_k,
dec4 => reg_b24_dec,
k_len4 => reg_b24_klen,
k4 => reg_b24_k,
dec5 => reg_b25_dec,
k_len5 => reg_b25_klen,
k5 => reg_b25_k,
dec6 => reg_b26_dec,
k_len6 => reg_b26_klen,
k6 => reg_b26_k,
l_in => out_fl3l,
r_in => out_fl3r,
l_out => out_r4l,
r_out => out_r4r
);
FL1: FL256
GENERIC MAP (
fl_ke128_offset => KA_OFFSET,
fl_ke128_shift => 30,
fli_ke128_offset => KA_OFFSET,
fli_ke128_shift => 30,
fl_kd128_offset => KL_OFFSET,
fl_kd128_shift => 77,
fli_kd128_offset => KL_OFFSET,
fli_kd128_shift => 77,
fl_ke256_offset => KR_OFFSET,
fl_ke256_shift => 30,
fli_ke256_offset => KR_OFFSET,
fli_ke256_shift => 30,
fl_kd256_offset => KA_OFFSET,
fl_kd256_shift => 77,
fli_kd256_offset => KA_OFFSET,
fli_kd256_shift => 77
)
PORT MAP (
reset => reset,
clk => clk,
fl_in => out_r1l,
fli_in => out_r1r,
k => reg_b7_k,
k_len => reg_b7_klen,
dec => reg_b7_dec,
fl_out => out_fl1l,
fli_out => out_fl1r
);
FL2: FL256
GENERIC MAP (
fl_ke128_offset => KL_OFFSET,
fl_ke128_shift => 77,
fli_ke128_offset => KL_OFFSET,
fli_ke128_shift => 77,
fl_kd128_offset => KA_OFFSET,
fl_kd128_shift => 30,
fli_kd128_offset => KA_OFFSET,
fli_kd128_shift => 30,
fl_ke256_offset => KL_OFFSET,
fl_ke256_shift => 60,
fli_ke256_offset => KL_OFFSET,
fli_ke256_shift => 60,
fl_kd256_offset => KL_OFFSET,
fl_kd256_shift => 60,
fli_kd256_offset => KL_OFFSET,
fli_kd256_shift => 60
)
PORT MAP (
reset => reset,
clk => clk,
fl_in => out_r2l,
fli_in => out_r2r,
k => reg_b14_k,
k_len => reg_b14_klen,
dec => reg_b14_dec,
fl_out => out_fl2l,
fli_out => out_fl2r
);
FL3: FL256
GENERIC MAP (
fl_ke128_offset => 0,
fl_ke128_shift => 0,
fli_ke128_offset => 0,
fli_ke128_shift => 0,
fl_kd128_offset => 0,
fl_kd128_shift => 0,
fli_kd128_offset => 0,
fli_kd128_shift => 0,
fl_ke256_offset => KA_OFFSET,
fl_ke256_shift => 77,
fli_ke256_offset => KA_OFFSET,
fli_ke256_shift => 77,
fl_kd256_offset => KR_OFFSET,
fl_kd256_shift => 30,
fli_kd256_offset => KR_OFFSET,
fli_kd256_shift => 30
)
PORT MAP (
reset => reset,
clk => clk,
fl_in => out_r3l,
fli_in => out_r3r,
k => reg_b21_k,
k_len => reg_b21_klen,
dec => reg_b21_dec,
fl_out => out_fl3l,
fli_out => out_fl3r
);
process(reset, clk)
begin
if(reset = '1') then
reg_m <= (others=>'0');
reg_kl <= (others=>'0');
reg_kr_int <= (others=>'0');
reg_k_len <= (others=>'0');
reg_dec <= '0';
reg_rdy <= '0';
reg_a1_rdy <= '0';
reg_a2_rdy <= '0';
reg_a3_rdy <= '0';
reg_a4_rdy <= '0';
reg_a5_rdy <= '0';
reg_a6_rdy <= '0';
reg_b1_rdy <= '0';
reg_b2_rdy <= '0';
reg_b3_rdy <= '0';
reg_b4_rdy <= '0';
reg_b5_rdy <= '0';
reg_b6_rdy <= '0';
reg_b7_rdy <= '0';
reg_b8_rdy <= '0';
reg_b9_rdy <= '0';
reg_b10_rdy <= '0';
reg_b11_rdy <= '0';
reg_b12_rdy <= '0';
reg_b13_rdy <= '0';
reg_b14_rdy <= '0';
reg_b15_rdy <= '0';
reg_b16_rdy <= '0';
reg_b17_rdy <= '0';
reg_b18_rdy <= '0';
reg_b19_rdy <= '0';
reg_b20_rdy <= '0';
reg_b21_rdy <= '0';
reg_b22_rdy <= '0';
reg_b23_rdy <= '0';
reg_b24_rdy <= '0';
reg_b25_rdy <= '0';
reg_b26_rdy <= '0';
reg_b27_rdy <= '0';
output_rdy <= '0';
elsif(rising_edge(clk)) then
reg_m <= input;
reg_kl <= key(0 to 127);
reg_kr_int <= kr_int;
reg_dec <= enc_dec;
reg_k_len <= key_len;
reg_rdy <= input_en;
reg_a1_m <= reg_m;
reg_a1_dec <= reg_dec;
reg_a1_klen <= reg_k_len;
reg_a1_rdy <= reg_rdy;
reg_a2_m <= reg_a1_m;
reg_a2_dec <= reg_a1_dec;
reg_a2_klen <= reg_a1_klen;
reg_a2_rdy <= reg_a1_rdy;
reg_a3_m <= reg_a2_m;
reg_a3_dec <= reg_a2_dec;
reg_a3_klen <= reg_a2_klen;
reg_a3_rdy <= reg_a2_rdy;
reg_a4_m <= reg_a3_m;
reg_a4_dec <= reg_a3_dec;
reg_a4_klen <= reg_a3_klen;
reg_a4_rdy <= reg_a3_rdy;
reg_a5_m <= reg_a4_m;
reg_a5_dec <= reg_a4_dec;
reg_a5_klen <= reg_a4_klen;
reg_a5_rdy <= reg_a4_rdy;
reg_a6_m <= reg_a5_m;
reg_a6_dec <= reg_a5_dec;
reg_a6_klen <= reg_a5_klen;
reg_a6_rdy <= reg_a5_rdy;
reg_b1_dec <= reg_a6_dec;
reg_b1_k <= out_ksched;
reg_b1_klen <= reg_a6_klen;
reg_b1_rdy <= reg_a6_rdy;
reg_b2_dec <= reg_b1_dec;
reg_b2_k <= reg_b1_k;
reg_b2_klen <= reg_b1_klen;
reg_b2_rdy <= reg_b1_rdy;
reg_b3_dec <= reg_b2_dec;
reg_b3_k <= reg_b2_k;
reg_b3_klen <= reg_b2_klen;
reg_b3_rdy <= reg_b2_rdy;
reg_b4_dec <= reg_b3_dec;
reg_b4_k <= reg_b3_k;
reg_b4_klen <= reg_b3_klen;
reg_b4_rdy <= reg_b3_rdy;
reg_b5_dec <= reg_b4_dec;
reg_b5_k <= reg_b4_k;
reg_b5_klen <= reg_b4_klen;
reg_b5_rdy <= reg_b4_rdy;
reg_b6_dec <= reg_b5_dec;
reg_b6_k <= reg_b5_k;
reg_b6_klen <= reg_b5_klen;
reg_b6_rdy <= reg_b5_rdy;
reg_b7_dec <= reg_b6_dec;
reg_b7_k <= reg_b6_k;
reg_b7_klen <= reg_b6_klen;
reg_b7_rdy <= reg_b6_rdy;
reg_b8_dec <= reg_b7_dec;
reg_b8_k <= reg_b7_k;
reg_b8_klen <= reg_b7_klen;
reg_b8_rdy <= reg_b7_rdy;
reg_b9_dec <= reg_b8_dec;
reg_b9_k <= reg_b8_k;
reg_b9_klen <= reg_b8_klen;
reg_b9_rdy <= reg_b8_rdy;
reg_b10_dec <= reg_b9_dec;
reg_b10_k <= reg_b9_k;
reg_b10_klen <= reg_b9_klen;
reg_b10_rdy <= reg_b9_rdy;
reg_b11_dec <= reg_b10_dec;
reg_b11_k <= reg_b10_k;
reg_b11_klen <= reg_b10_klen;
reg_b11_rdy <= reg_b10_rdy;
reg_b12_dec <= reg_b11_dec;
reg_b12_k <= reg_b11_k;
reg_b12_klen <= reg_b11_klen;
reg_b12_rdy <= reg_b11_rdy;
reg_b13_dec <= reg_b12_dec;
reg_b13_k <= reg_b12_k;
reg_b13_klen <= reg_b12_klen;
reg_b13_rdy <= reg_b12_rdy;
reg_b14_dec <= reg_b13_dec;
reg_b14_k <= reg_b13_k;
reg_b14_klen <= reg_b13_klen;
reg_b14_rdy <= reg_b13_rdy;
reg_b15_dec <= reg_b14_dec;
reg_b15_k <= reg_b14_k;
reg_b15_klen <= reg_b14_klen;
reg_b15_rdy <= reg_b14_rdy;
reg_b16_dec <= reg_b15_dec;
reg_b16_k <= reg_b15_k;
reg_b16_klen <= reg_b15_klen;
reg_b16_rdy <= reg_b15_rdy;
reg_b17_dec <= reg_b16_dec;
reg_b17_k <= reg_b16_k;
reg_b17_klen <= reg_b16_klen;
reg_b17_rdy <= reg_b16_rdy;
reg_b18_dec <= reg_b17_dec;
reg_b18_k <= reg_b17_k;
reg_b18_klen <= reg_b17_klen;
reg_b18_rdy <= reg_b17_rdy;
reg_b19_dec <= reg_b18_dec;
reg_b19_k <= reg_b18_k;
reg_b19_klen <= reg_b18_klen;
reg_b19_rdy <= reg_b18_rdy;
reg_b20_dec <= reg_b19_dec;
reg_b20_k <= reg_b19_k;
reg_b20_klen <= reg_b19_klen;
reg_b20_rdy <= reg_b19_rdy;
reg_b21_dec <= reg_b20_dec;
reg_b21_k <= reg_b20_k;
reg_b21_klen <= reg_b20_klen;
reg_b21_rdy <= reg_b20_rdy;
reg_b22_dec <= reg_b21_dec;
reg_b22_k <= reg_b21_k;
reg_b22_klen <= reg_b21_klen;
reg_b22_rdy <= reg_b21_rdy;
reg_b23_dec <= reg_b22_dec;
reg_b23_k <= reg_b22_k;
reg_b23_klen <= reg_b22_klen;
reg_b23_rdy <= reg_b22_rdy;
reg_b24_dec <= reg_b23_dec;
reg_b24_k <= reg_b23_k;
reg_b24_klen <= reg_b23_klen;
reg_b24_rdy <= reg_b23_rdy;
reg_b25_dec <= reg_b24_dec;
reg_b25_k <= reg_b24_k;
reg_b25_klen <= reg_b24_klen;
reg_b25_rdy <= reg_b24_rdy;
reg_b26_dec <= reg_b25_dec;
reg_b26_k <= reg_b25_k;
reg_b26_klen <= reg_b25_klen;
reg_b26_rdy <= reg_b25_rdy;
reg_b27_dec <= reg_b26_dec;
reg_b27_k <= reg_b26_k;
reg_b27_klen <= reg_b26_klen;
reg_b27_rdy <= reg_b26_rdy;
reg_l128_1 <= out_r3l;
reg_r128_1 <= out_r3r;
reg_l128_2 <= reg_l128_1;
reg_r128_2 <= reg_r128_1;
reg_l128_3 <= reg_l128_2;
reg_r128_3 <= reg_r128_2;
reg_l128_4 <= reg_l128_3;
reg_r128_4 <= reg_r128_3;
reg_l128_5 <= reg_l128_4;
reg_r128_5 <= reg_r128_4;
reg_l128_6 <= reg_l128_5;
reg_r128_6 <= reg_r128_5;
reg_l128_7 <= reg_l128_6;
reg_r128_7 <= reg_r128_6;
-- output
output <= w3 & w4;
output_rdy <= reg_b27_rdy;
end if;
end process;
--kr depends on key lenght
kr_int <= (others=>'0') when key_len(0)='0' else
key(128 to 191) & not key(128 to 191) when key_len="10" else
key(128 to 255);
-- pre-whitening
kw1_enc <= out_ksched(KL_OFFSET to KL_OFFSET+63);
kw2_enc <= out_ksched(KL_OFFSET+64 to KL_OFFSET+127);
ka_s111_dec128 <= out_ksched(KA_OFFSET+111 to KA_OFFSET+127) &
out_ksched(KA_OFFSET to KA_OFFSET+110);
kw1_dec128 <= ka_s111_dec128(0 to 63);
kw2_dec128 <= ka_s111_dec128(64 to 127);
ka_s111_dec256 <= out_ksched(KB_OFFSET+111 to KB_OFFSET+127) &
out_ksched(KB_OFFSET to KB_OFFSET+110);
kw1_dec256 <= ka_s111_dec256(0 to 63);
kw2_dec256 <= ka_s111_dec256(64 to 127);
kw1 <= kw1_dec128 when reg_a6_dec='1' and reg_a6_klen(0)='0' else
kw1_dec256 when reg_a6_dec='1' and reg_a6_klen(0)='1' else
kw1_enc;
kw2 <= kw2_dec128 when reg_a6_dec='1' and reg_a6_klen(0)='0' else
kw2_dec256 when reg_a6_dec='1' and reg_a6_klen(0)='1' else
kw2_enc;
w1 <= reg_a6_m(0 to 63) xor kw1;
w2 <= reg_a6_m(64 to 127) xor kw2;
-- post-whitening
ka_s111_enc128 <= reg_b27_k(KA_OFFSET+111 to KA_OFFSET+127) &
reg_b27_k(KA_OFFSET to KA_OFFSET+110);
kw3_enc128 <= ka_s111_enc128(0 to 63);
kw4_enc128 <= ka_s111_enc128(64 to 127);
ka_s111_enc256 <= reg_b27_k(KB_OFFSET+111 to KB_OFFSET+127) &
reg_b27_k(KB_OFFSET to KB_OFFSET+110);
kw3_enc256 <= ka_s111_enc256(0 to 63);
kw4_enc256 <= ka_s111_enc256(64 to 127);
kw3_dec <= reg_b27_k(KL_OFFSET to KL_OFFSET+63);
kw4_dec <= reg_b27_k(KL_OFFSET+64 to KL_OFFSET+127);
kw3 <= kw3_enc128 when reg_b27_dec='0' and reg_b27_klen(0)='0' else
kw3_enc256 when reg_b27_dec='0' and reg_b27_klen(0)='1' else
kw3_dec;
kw4 <= kw4_enc128 when reg_b27_dec='0' and reg_b27_klen(0)='0' else
kw4_enc256 when reg_b27_dec='0' and reg_b27_klen(0)='1' else
kw4_dec;
w3 <= reg_r128_7 xor kw3 when reg_b27_klen(0)='0' else
out_r4r xor kw3;
w4 <= reg_l128_7 xor kw4 when reg_b27_klen(0)='0' else
out_r4l xor kw4;
end RTL;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_reg-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture behavioral of reg is
begin
behavior : process (clk) is
begin
if rising_edge(clk) then
q <= d;
end if;
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_reg-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture behavioral of reg is
begin
behavior : process (clk) is
begin
if rising_edge(clk) then
q <= d;
end if;
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_reg-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
architecture behavioral of reg is
begin
behavior : process (clk) is
begin
if rising_edge(clk) then
q <= d;
end if;
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1927.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n02i01927ent IS
END c07s02b01x00p01n02i01927ent;
ARCHITECTURE c07s02b01x00p01n02i01927arch OF c07s02b01x00p01n02i01927ent IS
BEGIN
TESTING: PROCESS
type A is array ( 1 to 1, 1 to 1 ) of BOOLEAN;
variable A1 : A;
BEGIN
A1 := A'(1=>(1=>TRUE)) or A'(1=>(1=>FALSE)); -- Failure_here
-- SEMANTIC ERROR: "or" not defined for multi-dimensional arrays.
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n02i01927d - Logical operators are not valid for multi-dimensional arrays."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01927arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1927.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n02i01927ent IS
END c07s02b01x00p01n02i01927ent;
ARCHITECTURE c07s02b01x00p01n02i01927arch OF c07s02b01x00p01n02i01927ent IS
BEGIN
TESTING: PROCESS
type A is array ( 1 to 1, 1 to 1 ) of BOOLEAN;
variable A1 : A;
BEGIN
A1 := A'(1=>(1=>TRUE)) or A'(1=>(1=>FALSE)); -- Failure_here
-- SEMANTIC ERROR: "or" not defined for multi-dimensional arrays.
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n02i01927d - Logical operators are not valid for multi-dimensional arrays."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01927arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1927.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n02i01927ent IS
END c07s02b01x00p01n02i01927ent;
ARCHITECTURE c07s02b01x00p01n02i01927arch OF c07s02b01x00p01n02i01927ent IS
BEGIN
TESTING: PROCESS
type A is array ( 1 to 1, 1 to 1 ) of BOOLEAN;
variable A1 : A;
BEGIN
A1 := A'(1=>(1=>TRUE)) or A'(1=>(1=>FALSE)); -- Failure_here
-- SEMANTIC ERROR: "or" not defined for multi-dimensional arrays.
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n02i01927d - Logical operators are not valid for multi-dimensional arrays."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01927arch;
|
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of ROC_WIDTH : constant is 1;
attribute mti_svvh_generic_type of TOC_WIDTH : constant is 1;
end glbl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2448.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p02n02i02448ent IS
END c07s03b02x02p02n02i02448ent;
ARCHITECTURE c07s03b02x02p02n02i02448arch OF c07s03b02x02p02n02i02448ent IS
BEGIN
TESTING: PROCESS
type t13 is array (bit'('0') to bit'('0')) of integer;
variable v13 : t13;
BEGIN
v13 := (bit'('0') => 13); -- No_failure_here
assert NOT(v13(bit'('0'))=13)
report "***PASSED TEST: c07s03b02x02p02n02i02448"
severity NOTE;
assert (v13(bit'('0'))=13)
report "***FAILED TEST: c07s03b02x02p02n02i02448 - Named association of an array aggregate can have a choice that is a null range only if the aggregate includes a single element association."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p02n02i02448arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2448.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p02n02i02448ent IS
END c07s03b02x02p02n02i02448ent;
ARCHITECTURE c07s03b02x02p02n02i02448arch OF c07s03b02x02p02n02i02448ent IS
BEGIN
TESTING: PROCESS
type t13 is array (bit'('0') to bit'('0')) of integer;
variable v13 : t13;
BEGIN
v13 := (bit'('0') => 13); -- No_failure_here
assert NOT(v13(bit'('0'))=13)
report "***PASSED TEST: c07s03b02x02p02n02i02448"
severity NOTE;
assert (v13(bit'('0'))=13)
report "***FAILED TEST: c07s03b02x02p02n02i02448 - Named association of an array aggregate can have a choice that is a null range only if the aggregate includes a single element association."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p02n02i02448arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2448.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p02n02i02448ent IS
END c07s03b02x02p02n02i02448ent;
ARCHITECTURE c07s03b02x02p02n02i02448arch OF c07s03b02x02p02n02i02448ent IS
BEGIN
TESTING: PROCESS
type t13 is array (bit'('0') to bit'('0')) of integer;
variable v13 : t13;
BEGIN
v13 := (bit'('0') => 13); -- No_failure_here
assert NOT(v13(bit'('0'))=13)
report "***PASSED TEST: c07s03b02x02p02n02i02448"
severity NOTE;
assert (v13(bit'('0'))=13)
report "***FAILED TEST: c07s03b02x02p02n02i02448 - Named association of an array aggregate can have a choice that is a null range only if the aggregate includes a single element association."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p02n02i02448arch;
|
-- This VHDL application uses processes to generate 3 types of digital signals (triangular, saw-tooth, and sine) with FPGA hardware.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.all;
ENTITY generador IS
PORT
(
AB : OUT STD_LOGIC; -- Señal A/B
DIGIT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Palabra digital
CS : OUT STD_LOGIC; -- Señal CS
WR : OUT STD_LOGIC; -- Señal WR
LDAC : OUT STD_LOGIC; -- Señal LDAC
TIPO : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- Selector de forma de señal
AMP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- Selector de amplitud de señal
FREC : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- Selector de frecuencia de señal
CLK_INT : IN STD_LOGIC; -- Reloj de 25.175 MHz
CLEAR : OUT STD_LOGIC --Señal CLR
);
END generador;
ARCHITECTURE dcse OF generador IS
CONSTANT MAX : INTEGER := 25175; -- Valor máximo del contador que genera la señal de muestreo
-- dado el oscilador interno
SIGNAL muestreo : STD_LOGIC:= '0'; -- Señal de muestreo que determina cada cuánto tiempo
-- varío la señal analógica de salida
SIGNAL INC : STD_LOGIC := '0'; -- Señal que usaremos para ver si debo o no incrementar
-- la señal en el diente de sierra (para que tenga la misma
-- frecuencia que las demás y no el doble)
SIGNAL k : INTEGER := 0; -- Contador para la señal de muestreo
SIGNAL n : INTEGER RANGE 0 TO 255;
SIGNAL ValorDigit : INTEGER RANGE 0 TO 5100 := 0;-- Señal digital que introduzco en el convertidor
-- para generar la señal analógica
SIGNAL SumRes : STD_LOGIC:='0'; -- Señal que indica si debo sumar o restar
-- (para la señal triangular)
SIGNAL ampMax : INTEGER; -- Señal que nos determina cuál es la amplitud de la señal
SIGNAL divisor : INTEGER;
SIGNAL comp : INTEGER; -- Señal que marca el límite a comparar para así
-- generar señales de diferentes frecuencias
SIGNAL seno : INTEGER RANGE 0 TO 255; -- Valor de la señal armónica, entre 0 y 255
SIGNAL resultado : INTEGER RANGE 0 TO 255; -- Resultado final a mostrar por la salida digital
-- (que deberá ser pasado de entero a vector de bits)
BEGIN
AB <= '0'; -- Elegimos el canal A para sacar las señales
LDAC <= '0'; -- LDAC permanentemente a 0
CLEAR <= '1'; -- CLR permanentemente inactiva (a 1)
-- Proceso para seleccionar la amplitud de la señal
PROCESS(AMP)
BEGIN
CASE AMP IS
WHEN "00" => ampMax <= 51; -- 1 voltio
WHEN "01" => ampMax <= 102; -- 2 voltios
WHEN "10" => ampMax <= 153; -- 3 voltios
WHEN "11" => ampMax <= 255; -- 5 voltios
WHEN OTHERS => ampMax <= 0; -- 0 voltios
END CASE;
END PROCESS;
PROCESS(AMP)
BEGIN
CASE AMP IS
WHEN "00" => divisor <= 50; -- 1 voltio
WHEN "01" => divisor <= 25; -- 2 voltios
WHEN "10" => divisor <= 17; -- 3 voltios
WHEN "11" => divisor <= 10; -- 5 voltios
WHEN OTHERS => divisor <= 1; -- 0 voltios
END CASE;
END PROCESS;
-- Procesor para elegir la frecuencia de la señal
PROCESS(FREC)
BEGIN
CASE FREC IS
WHEN "00" => comp <= 393; -- 62.5 Hz
WHEN "01" => comp <= 197; -- 125 Hz
WHEN "10" => comp <= 98; -- 250 Hz
WHEN "11" => comp <= 49;-- Muestreo de 512kHz -> 25.175MHz/512kHz = 49.1699 (500 Hz)
WHEN OTHERS => comp <= 49;-- Muestreo de 512kHz -> 25.175MHz/512kHz = 49.1699 (500 Hz)
END CASE;
END PROCESS;
PROCESS (CLK_INT)
BEGIN
-- Cada vez que hay flanco de subida en el generador interno
IF CLK_INT'event AND CLK_INT='1' THEN
-- Incremento el contador
k <= k + 1;
IF k >= comp THEN
-- Si sobrepaso el valor para generar la señal de muestreo, la invierto
muestreo <= NOT muestreo;
-- Introduzco este valor en CS y WR
CS <= muestreo;
WR <= muestreo;
-- Reinicio el contador
k <= 0;
END IF;
END IF;
END PROCESS;
PROCESS (muestreo)
BEGIN
IF muestreo'event AND muestreo='0' THEN
-- Cada vez que deba introducir una muestra en la entrada del convertidor D/A
-- Varío el valor de la señal que determina si debo o no incrementar el diente de sierra
INC <= NOT INC;
IF TIPO = "01" THEN -- Señal diente de sierra
IF ValorDigit >= (ampMax*10) THEN
-- Si la señal digital genera una salida superior al valor máximo de amplitud por 10
-- Multiplico por 10 porque así puedo hacer el mínimo incremento que he definido, que será
-- de 0.2 (51/255) en la señal de 1 voltio de amplitud. Si multiplico por 10, el incremento
-- será de 2, por lo que sí será apreciable en la variable integer
IF INC='1' THEN
-- Si además está activa la señal INC, es cuando el diente de sierra vuelve a 0
-- al haber alcanzado su máximo
ValorDigit <= 0;
END IF;
ELSE
IF INC='1' THEN -- Así se incrementa cada 2 muestras y ocupa el periodo
-- Añado el incremento correspondiente (para la amplitud máxima, será 1 de 255),
-- multiplicado por 10
ValorDigit <= ValorDigit + 10*ampMax/255;
END IF;
END IF;
-- El resultado es justo la señal dd dividida entre 10
resultado <= ValorDigit/10;
END IF;
IF TIPO = "10" THEN -- Señal triangular
IF ValorDigit >= ((ampMax-1)*10) THEN
-- Si sobrepaso el límite superior, activo la señal en modo Resta
SumRes <= '1';
END IF;
IF ValorDigit = 10*ampMax/255 THEN
-- Si llego al límite inferior, activo la señal en modo Suma
SumRes <= '0';
END IF;
IF SumRes = '0' THEN
-- En modo Suma incremento
ValorDigit <= ValorDigit + 10*ampMax/255;
ELSE
-- En caso contrario decremento
ValorDigit <= ValorDigit - 10*ampMax/255;
END IF;
-- Una vez más, el resultado dividido entre 10
resultado <= ValorDigit/10;
END IF;
IF TIPO = "11" THEN -- Señal senoidal
IF ValorDigit >= 510 THEN
-- Si llego al límite 510 (las posibles fases), vuelvo a 0
ValorDigit <= 0;
ELSE
-- En caso contrario, incremento una unidad
ValorDigit <= ValorDigit + 1;
END IF;
-- El resultado es el valor del seno, normalizado según la amplitud máxima
resultado <= (seno*10/divisor);
END IF;
-- En la salida digital muestro resultado
DIGIT <= CONV_STD_LOGIC_VECTOR(resultado,8);
END IF;
END PROCESS;
WITH ValorDigit SELECT
-- Según el valor de ValorDigit (que será la fase en este caso), muestro un valor
-- u otro del seno entre 0 y 255. El código ha sido generado con Matlab
seno <=
128 WHEN 0,
129 WHEN 1,
131 WHEN 2,
132 WHEN 3,
134 WHEN 4,
135 WHEN 5,
137 WHEN 6,
138 WHEN 7,
140 WHEN 8,
142 WHEN 9,
143 WHEN 10,
145 WHEN 11,
146 WHEN 12,
148 WHEN 13,
149 WHEN 14,
151 WHEN 15,
152 WHEN 16,
154 WHEN 17,
155 WHEN 18,
157 WHEN 19,
158 WHEN 20,
160 WHEN 21,
162 WHEN 22,
163 WHEN 23,
165 WHEN 24,
166 WHEN 25,
167 WHEN 26,
169 WHEN 27,
170 WHEN 28,
172 WHEN 29,
173 WHEN 30,
175 WHEN 31,
176 WHEN 32,
178 WHEN 33,
179 WHEN 34,
181 WHEN 35,
182 WHEN 36,
183 WHEN 37,
185 WHEN 38,
186 WHEN 39,
188 WHEN 40,
189 WHEN 41,
190 WHEN 42,
192 WHEN 43,
193 WHEN 44,
194 WHEN 45,
196 WHEN 46,
197 WHEN 47,
198 WHEN 48,
200 WHEN 49,
201 WHEN 50,
202 WHEN 51,
203 WHEN 52,
205 WHEN 53,
206 WHEN 54,
207 WHEN 55,
208 WHEN 56,
210 WHEN 57,
211 WHEN 58,
212 WHEN 59,
213 WHEN 60,
214 WHEN 61,
215 WHEN 62,
217 WHEN 63,
218 WHEN 64,
219 WHEN 65,
220 WHEN 66,
221 WHEN 67,
222 WHEN 68,
223 WHEN 69,
224 WHEN 70,
225 WHEN 71,
226 WHEN 72,
227 WHEN 73,
228 WHEN 74,
229 WHEN 75,
230 WHEN 76,
231 WHEN 77,
232 WHEN 78,
233 WHEN 79,
234 WHEN 80,
234 WHEN 81,
235 WHEN 82,
236 WHEN 83,
237 WHEN 84,
238 WHEN 85,
238 WHEN 86,
239 WHEN 87,
240 WHEN 88,
241 WHEN 89,
241 WHEN 90,
242 WHEN 91,
243 WHEN 92,
243 WHEN 93,
244 WHEN 94,
245 WHEN 95,
245 WHEN 96,
246 WHEN 97,
246 WHEN 98,
247 WHEN 99,
248 WHEN 100,
248 WHEN 101,
249 WHEN 102,
249 WHEN 103,
250 WHEN 104,
250 WHEN 105,
250 WHEN 106,
251 WHEN 107,
251 WHEN 108,
252 WHEN 109,
252 WHEN 110,
252 WHEN 111,
253 WHEN 112,
253 WHEN 113,
253 WHEN 114,
253 WHEN 115,
254 WHEN 116,
254 WHEN 117,
254 WHEN 118,
254 WHEN 119,
254 WHEN 120,
255 WHEN 121,
255 WHEN 122,
255 WHEN 123,
255 WHEN 124,
255 WHEN 125,
255 WHEN 126,
255 WHEN 127,
255 WHEN 128,
255 WHEN 129,
255 WHEN 130,
255 WHEN 131,
255 WHEN 132,
255 WHEN 133,
255 WHEN 134,
255 WHEN 135,
254 WHEN 136,
254 WHEN 137,
254 WHEN 138,
254 WHEN 139,
254 WHEN 140,
253 WHEN 141,
253 WHEN 142,
253 WHEN 143,
253 WHEN 144,
252 WHEN 145,
252 WHEN 146,
252 WHEN 147,
251 WHEN 148,
251 WHEN 149,
250 WHEN 150,
250 WHEN 151,
250 WHEN 152,
249 WHEN 153,
249 WHEN 154,
248 WHEN 155,
248 WHEN 156,
247 WHEN 157,
246 WHEN 158,
246 WHEN 159,
245 WHEN 160,
245 WHEN 161,
244 WHEN 162,
243 WHEN 163,
243 WHEN 164,
242 WHEN 165,
241 WHEN 166,
241 WHEN 167,
240 WHEN 168,
239 WHEN 169,
238 WHEN 170,
238 WHEN 171,
237 WHEN 172,
236 WHEN 173,
235 WHEN 174,
234 WHEN 175,
234 WHEN 176,
233 WHEN 177,
232 WHEN 178,
231 WHEN 179,
230 WHEN 180,
229 WHEN 181,
228 WHEN 182,
227 WHEN 183,
226 WHEN 184,
225 WHEN 185,
224 WHEN 186,
223 WHEN 187,
222 WHEN 188,
221 WHEN 189,
220 WHEN 190,
219 WHEN 191,
218 WHEN 192,
217 WHEN 193,
215 WHEN 194,
214 WHEN 195,
213 WHEN 196,
212 WHEN 197,
211 WHEN 198,
210 WHEN 199,
208 WHEN 200,
207 WHEN 201,
206 WHEN 202,
205 WHEN 203,
203 WHEN 204,
202 WHEN 205,
201 WHEN 206,
200 WHEN 207,
198 WHEN 208,
197 WHEN 209,
196 WHEN 210,
194 WHEN 211,
193 WHEN 212,
192 WHEN 213,
190 WHEN 214,
189 WHEN 215,
188 WHEN 216,
186 WHEN 217,
185 WHEN 218,
183 WHEN 219,
182 WHEN 220,
181 WHEN 221,
179 WHEN 222,
178 WHEN 223,
176 WHEN 224,
175 WHEN 225,
173 WHEN 226,
172 WHEN 227,
170 WHEN 228,
169 WHEN 229,
167 WHEN 230,
166 WHEN 231,
165 WHEN 232,
163 WHEN 233,
162 WHEN 234,
160 WHEN 235,
158 WHEN 236,
157 WHEN 237,
155 WHEN 238,
154 WHEN 239,
152 WHEN 240,
151 WHEN 241,
149 WHEN 242,
148 WHEN 243,
146 WHEN 244,
145 WHEN 245,
143 WHEN 246,
142 WHEN 247,
140 WHEN 248,
138 WHEN 249,
137 WHEN 250,
135 WHEN 251,
134 WHEN 252,
132 WHEN 253,
131 WHEN 254,
129 WHEN 255,
128 WHEN 256,
126 WHEN 257,
124 WHEN 258,
123 WHEN 259,
121 WHEN 260,
120 WHEN 261,
118 WHEN 262,
117 WHEN 263,
115 WHEN 264,
113 WHEN 265,
112 WHEN 266,
110 WHEN 267,
109 WHEN 268,
107 WHEN 269,
106 WHEN 270,
104 WHEN 271,
103 WHEN 272,
101 WHEN 273,
100 WHEN 274,
98 WHEN 275,
97 WHEN 276,
95 WHEN 277,
93 WHEN 278,
92 WHEN 279,
90 WHEN 280,
89 WHEN 281,
88 WHEN 282,
86 WHEN 283,
85 WHEN 284,
83 WHEN 285,
82 WHEN 286,
80 WHEN 287,
79 WHEN 288,
77 WHEN 289,
76 WHEN 290,
74 WHEN 291,
73 WHEN 292,
72 WHEN 293,
70 WHEN 294,
69 WHEN 295,
67 WHEN 296,
66 WHEN 297,
65 WHEN 298,
63 WHEN 299,
62 WHEN 300,
61 WHEN 301,
59 WHEN 302,
58 WHEN 303,
57 WHEN 304,
55 WHEN 305,
54 WHEN 306,
53 WHEN 307,
52 WHEN 308,
50 WHEN 309,
49 WHEN 310,
48 WHEN 311,
47 WHEN 312,
45 WHEN 313,
44 WHEN 314,
43 WHEN 315,
42 WHEN 316,
41 WHEN 317,
40 WHEN 318,
38 WHEN 319,
37 WHEN 320,
36 WHEN 321,
35 WHEN 322,
34 WHEN 323,
33 WHEN 324,
32 WHEN 325,
31 WHEN 326,
30 WHEN 327,
29 WHEN 328,
28 WHEN 329,
27 WHEN 330,
26 WHEN 331,
25 WHEN 332,
24 WHEN 333,
23 WHEN 334,
22 WHEN 335,
21 WHEN 336,
21 WHEN 337,
20 WHEN 338,
19 WHEN 339,
18 WHEN 340,
17 WHEN 341,
17 WHEN 342,
16 WHEN 343,
15 WHEN 344,
14 WHEN 345,
14 WHEN 346,
13 WHEN 347,
12 WHEN 348,
12 WHEN 349,
11 WHEN 350,
10 WHEN 351,
10 WHEN 352,
9 WHEN 353,
9 WHEN 354,
8 WHEN 355,
7 WHEN 356,
7 WHEN 357,
6 WHEN 358,
6 WHEN 359,
5 WHEN 360,
5 WHEN 361,
5 WHEN 362,
4 WHEN 363,
4 WHEN 364,
3 WHEN 365,
3 WHEN 366,
3 WHEN 367,
2 WHEN 368,
2 WHEN 369,
2 WHEN 370,
2 WHEN 371,
1 WHEN 372,
1 WHEN 373,
1 WHEN 374,
1 WHEN 375,
1 WHEN 376,
0 WHEN 377,
0 WHEN 378,
0 WHEN 379,
0 WHEN 380,
0 WHEN 381,
0 WHEN 382,
0 WHEN 383,
0 WHEN 384,
0 WHEN 385,
0 WHEN 386,
0 WHEN 387,
0 WHEN 388,
0 WHEN 389,
0 WHEN 390,
0 WHEN 391,
1 WHEN 392,
1 WHEN 393,
1 WHEN 394,
1 WHEN 395,
1 WHEN 396,
2 WHEN 397,
2 WHEN 398,
2 WHEN 399,
2 WHEN 400,
3 WHEN 401,
3 WHEN 402,
3 WHEN 403,
4 WHEN 404,
4 WHEN 405,
5 WHEN 406,
5 WHEN 407,
5 WHEN 408,
6 WHEN 409,
6 WHEN 410,
7 WHEN 411,
7 WHEN 412,
8 WHEN 413,
9 WHEN 414,
9 WHEN 415,
10 WHEN 416,
10 WHEN 417,
11 WHEN 418,
12 WHEN 419,
12 WHEN 420,
13 WHEN 421,
14 WHEN 422,
14 WHEN 423,
15 WHEN 424,
16 WHEN 425,
17 WHEN 426,
17 WHEN 427,
18 WHEN 428,
19 WHEN 429,
20 WHEN 430,
21 WHEN 431,
21 WHEN 432,
22 WHEN 433,
23 WHEN 434,
24 WHEN 435,
25 WHEN 436,
26 WHEN 437,
27 WHEN 438,
28 WHEN 439,
29 WHEN 440,
30 WHEN 441,
31 WHEN 442,
32 WHEN 443,
33 WHEN 444,
34 WHEN 445,
35 WHEN 446,
36 WHEN 447,
37 WHEN 448,
38 WHEN 449,
40 WHEN 450,
41 WHEN 451,
42 WHEN 452,
43 WHEN 453,
44 WHEN 454,
45 WHEN 455,
47 WHEN 456,
48 WHEN 457,
49 WHEN 458,
50 WHEN 459,
52 WHEN 460,
53 WHEN 461,
54 WHEN 462,
55 WHEN 463,
57 WHEN 464,
58 WHEN 465,
59 WHEN 466,
61 WHEN 467,
62 WHEN 468,
63 WHEN 469,
65 WHEN 470,
66 WHEN 471,
67 WHEN 472,
69 WHEN 473,
70 WHEN 474,
72 WHEN 475,
73 WHEN 476,
74 WHEN 477,
76 WHEN 478,
77 WHEN 479,
79 WHEN 480,
80 WHEN 481,
82 WHEN 482,
83 WHEN 483,
85 WHEN 484,
86 WHEN 485,
88 WHEN 486,
89 WHEN 487,
90 WHEN 488,
92 WHEN 489,
93 WHEN 490,
95 WHEN 491,
97 WHEN 492,
98 WHEN 493,
100 WHEN 494,
101 WHEN 495,
103 WHEN 496,
104 WHEN 497,
106 WHEN 498,
107 WHEN 499,
109 WHEN 500,
110 WHEN 501,
112 WHEN 502,
113 WHEN 503,
115 WHEN 504,
117 WHEN 505,
118 WHEN 506,
120 WHEN 507,
121 WHEN 508,
123 WHEN 509,
124 WHEN 510,
126 WHEN 511,
0 WHEN OTHERS;
END dcse;
|
CONFIGURATION Decoder_Behavior_config OF Decoder IS
FOR Behavior
END FOR;
END Decoder_Behavior_config; |
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2004/11/23 01:04:03 $
--
-- History:
-- DET 2001-08-30 First Version
-- LCW Nov 8, 2004 -- updated for NCSim
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity opb_ipif_v2_00_h.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2004/11/23 01:04:03 $
--
-- History:
-- DET 2001-08-30 First Version
-- LCW Nov 8, 2004 -- updated for NCSim
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity opb_ipif_v2_00_h.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2833.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity REPORT is
end REPORT;
ENTITY c13s09b00x00p99n01i02833ent IS
END c13s09b00x00p99n01i02833ent;
ARCHITECTURE c13s09b00x00p99n01i02833arch OF c13s09b00x00p99n01i02833ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02833 - Reserved word REPORT can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02833arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2833.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity REPORT is
end REPORT;
ENTITY c13s09b00x00p99n01i02833ent IS
END c13s09b00x00p99n01i02833ent;
ARCHITECTURE c13s09b00x00p99n01i02833arch OF c13s09b00x00p99n01i02833ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02833 - Reserved word REPORT can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02833arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2833.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity REPORT is
end REPORT;
ENTITY c13s09b00x00p99n01i02833ent IS
END c13s09b00x00p99n01i02833ent;
ARCHITECTURE c13s09b00x00p99n01i02833arch OF c13s09b00x00p99n01i02833ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02833 - Reserved word REPORT can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02833arch;
|
-- NEED RESULT: ARCH00564: Aliasing - composite generic subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00564
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.4 (1)
-- 4.3.4 (2)
-- 4.3.4 (13)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00564)
-- ENT00564_Test_Bench(ARCH00564_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00564 of GENERIC_STANDARD_TYPES is
constant co_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
constant co_st_string_1 : st_string
:= c_st_string_1 ;
constant co_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
constant co_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
constant co_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
constant co_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
signal si_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
signal si_st_string_1 : st_string
:= c_st_string_1 ;
signal si_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
signal si_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
signal si_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
signal si_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
alias as_st_bit_vector_1 : st_bit_vector
is si_st_bit_vector_1 ;
alias as_st_string_1 : st_string
is si_st_string_1 ;
alias as_st_rec1_1 : st_rec1
is si_st_rec1_1 ;
alias as_st_rec2_1 : st_rec2
is si_st_rec2_1 ;
alias as_st_rec3_1 : st_rec3
is si_st_rec3_1 ;
alias as_st_arr1_1 : st_arr1
is si_st_arr1_1 ;
type test is (initial, intermediate, final) ;
signal synch : test := initial ;
signal s_correct1 : boolean ;
signal s_correct2 : boolean ;
begin
process
variable correct : boolean := true ;
begin
if synch = initial then
correct := correct and as_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and as_st_string_1 = c_st_string_1 ;
correct := correct and as_st_rec1_1 = c_st_rec1_1 ;
correct := correct and as_st_rec2_1 = c_st_rec2_1 ;
correct := correct and as_st_rec3_1 = c_st_rec3_1 ;
correct := correct and as_st_arr1_1 = c_st_arr1_1 ;
si_st_bit_vector_1 <= c_st_bit_vector_2 ;
si_st_string_1 <= c_st_string_2 ;
si_st_rec1_1 <= c_st_rec1_2 ;
si_st_rec2_1 <= c_st_rec2_2 ;
si_st_rec3_1 <= c_st_rec3_2 ;
si_st_arr1_1 <= c_st_arr1_2 ;
synch <= intermediate ;
as_st_bit_vector_1 <= transport c_st_bit_vector_1 after 1 ns ;
as_st_string_1 <= transport c_st_string_1 after 1 ns ;
as_st_rec1_1 <= transport c_st_rec1_1 after 1 ns ;
as_st_rec2_1 <= transport c_st_rec2_1 after 1 ns ;
as_st_rec3_1 <= transport c_st_rec3_1 after 1 ns ;
as_st_arr1_1 <= transport c_st_arr1_1 after 1 ns ;
synch <= transport final after 1 ns ;
s_correct1 <= correct ;
end if ;
wait ;
end process ;
process (synch)
procedure p1 is
variable correct : boolean ;
variable va_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
variable va_st_string_1 : st_string
:= c_st_string_1 ;
variable va_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
variable va_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
variable va_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
variable va_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
alias ac_st_bit_vector_1 : st_bit_vector
is co_st_bit_vector_1 ;
alias ac_st_string_1 : st_string
is co_st_string_1 ;
alias ac_st_rec1_1 : st_rec1
is co_st_rec1_1 ;
alias ac_st_rec2_1 : st_rec2
is co_st_rec2_1 ;
alias ac_st_rec3_1 : st_rec3
is co_st_rec3_1 ;
alias ac_st_arr1_1 : st_arr1
is co_st_arr1_1 ;
alias av_st_bit_vector_1 : st_bit_vector
is va_st_bit_vector_1 ;
alias av_st_string_1 : st_string
is va_st_string_1 ;
alias av_st_rec1_1 : st_rec1
is va_st_rec1_1 ;
alias av_st_rec2_1 : st_rec2
is va_st_rec2_1 ;
alias av_st_rec3_1 : st_rec3
is va_st_rec3_1 ;
alias av_st_arr1_1 : st_arr1
is va_st_arr1_1 ;
begin
if synch = intermediate then
-- test that variables denote same object
correct := s_correct1 ;
correct := correct and av_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and av_st_string_1 = c_st_string_1 ;
correct := correct and av_st_rec1_1 = c_st_rec1_1 ;
correct := correct and av_st_rec2_1 = c_st_rec2_1 ;
correct := correct and av_st_rec3_1 = c_st_rec3_1 ;
correct := correct and av_st_arr1_1 = c_st_arr1_1 ;
va_st_bit_vector_1 := c_st_bit_vector_2 ;
va_st_string_1 := c_st_string_2 ;
va_st_rec1_1 := c_st_rec1_2 ;
va_st_rec2_1 := c_st_rec2_2 ;
va_st_rec3_1 := c_st_rec3_2 ;
va_st_arr1_1 := c_st_arr1_2 ;
correct := correct and av_st_bit_vector_1 = c_st_bit_vector_2 ;
correct := correct and av_st_string_1 = c_st_string_2 ;
correct := correct and av_st_rec1_1 = c_st_rec1_2 ;
correct := correct and av_st_rec2_1 = c_st_rec2_2 ;
correct := correct and av_st_rec3_1 = c_st_rec3_2 ;
correct := correct and av_st_arr1_1 = c_st_arr1_2 ;
av_st_bit_vector_1 := c_st_bit_vector_1 ;
av_st_string_1 := c_st_string_1 ;
av_st_rec1_1 := c_st_rec1_1 ;
av_st_rec2_1 := c_st_rec2_1 ;
av_st_rec3_1 := c_st_rec3_1 ;
av_st_arr1_1 := c_st_arr1_1 ;
correct := correct and va_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and va_st_string_1 = c_st_string_1 ;
correct := correct and va_st_rec1_1 = c_st_rec1_1 ;
correct := correct and va_st_rec2_1 = c_st_rec2_1 ;
correct := correct and va_st_rec3_1 = c_st_rec3_1 ;
correct := correct and va_st_arr1_1 = c_st_arr1_1 ;
-- test that signals denote same object
correct := correct and as_st_bit_vector_1 = c_st_bit_vector_2 ;
correct := correct and as_st_string_1 = c_st_string_2 ;
correct := correct and as_st_rec1_1 = c_st_rec1_2 ;
correct := correct and as_st_rec2_1 = c_st_rec2_2 ;
correct := correct and as_st_rec3_1 = c_st_rec3_2 ;
correct := correct and as_st_arr1_1 = c_st_arr1_2 ;
correct := correct and si_st_bit_vector_1 = c_st_bit_vector_2 ;
correct := correct and si_st_string_1 = c_st_string_2 ;
correct := correct and si_st_rec1_1 = c_st_rec1_2 ;
correct := correct and si_st_rec2_1 = c_st_rec2_2 ;
correct := correct and si_st_rec3_1 = c_st_rec3_2 ;
correct := correct and si_st_arr1_1 = c_st_arr1_2 ;
-- test that constants denote same object
correct := correct and ac_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and ac_st_string_1 = c_st_string_1 ;
correct := correct and ac_st_rec1_1 = c_st_rec1_1 ;
correct := correct and ac_st_rec2_1 = c_st_rec2_1 ;
correct := correct and ac_st_rec3_1 = c_st_rec3_1 ;
correct := correct and ac_st_arr1_1 = c_st_arr1_1 ;
s_correct2 <= correct ;
end if ;
end p1 ;
begin
p1 ;
end process ;
--
process (synch)
variable correct : boolean ;
begin
if synch = final then
correct := s_correct2 ;
correct := correct and si_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and si_st_string_1 = c_st_string_1 ;
correct := correct and si_st_rec1_1 = c_st_rec1_1 ;
correct := correct and si_st_rec2_1 = c_st_rec2_1 ;
correct := correct and si_st_rec3_1 = c_st_rec3_1 ;
correct := correct and si_st_arr1_1 = c_st_arr1_1 ;
test_report ( "ARCH00564" ,
"Aliasing - composite generic subtypes" ,
correct) ;
end if ;
end process ;
end ARCH00564 ;
--
entity ENT00564_Test_Bench is
end ENT00564_Test_Bench ;
--
architecture ARCH00564_Test_Bench of ENT00564_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00564 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00564_Test_Bench ;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity unite is
Port (
LED : out std_ulogic_vector(3 downto 0);
CLK_66MHZ : in std_ulogic;
SDA, SCL: inout std_logic;
USER_RESET : in std_logic
);
end unite;
architecture Behavioral of unite is
signal duty_cycle : unsigned(7 downto 0);
signal scl_i : std_logic; -- i2c clock line input
signal scl_o : std_logic; -- i2c clock line output
signal scl_oen : std_logic; -- i2c clock line output enable, active low
signal sda_i : std_logic; -- i2c data line input
signal sda_o : std_logic; -- i2c data line output
signal sda_oen : std_logic;
signal start,
stop,
read,
write,
ack_in : std_logic;
signal din : std_logic_vector(7 downto 0);
signal dout : std_logic_vector(7 downto 0);
signal cmd_ack : std_logic; -- command done
signal ack_out : std_logic;
-- we ignore those values:
signal i2c_busy, i2c_al : std_logic;
begin
pwm : entity work.LEDPWM(Behavioral)
generic map (WIDTH => 25)
port map (
CLK_66MHZ => CLK_66MHZ,
LED => LED,
duty_cycle => duty_cycle
);
tristate : entity work.tristate(Behavioral)
port map (
-- Interface to byte_ctrl
scl_i => scl_i, -- i2c clock line input
scl_o => scl_o, -- i2c clock line output
scl_oen => scl_oen, -- i2c clock line output enable, active low
sda_i => sda_i, -- i2c data line input
sda_o => sda_o, -- i2c data line output
sda_oen => sda_oen, -- i2c data line output enable, active low
-- Interface to the outside world
scl => SCL,
sda => SDA
);
fsm : entity work.FSM(moore)
port map (
clk => CLK_66MHZ,
out_val=> duty_cycle,
user_reset => USER_RESET,
-- everything below is the interface to the i2c driver
start => start,
stop => stop,
read => read,
write => write,
ack_in => ack_in,
din => din,
dout => dout,
cmd_ack=> cmd_ack
);
i2c : entity work.i2c_master_byte_ctrl(structural)
port map (
clk => CLK_66MHZ,
rst => USER_RESET, -- synchronous active high reset (WISHBONE compatible)
nReset => '1', -- asynchronous active low reset (FPGA compatible)
ena => '1', -- core enable signal
clk_cnt => "0000000010100101",
--clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start => start,
stop => stop,
read => read,
write => write,
ack_in => ack_in,
din => din,
-- output signals
cmd_ack => cmd_ack,
ack_out => open,
i2c_busy => open, -- ignored
i2c_al => open, -- ignored
dout => dout,
-- i2c lines
scl_i => scl_i, -- i2c clock line input
scl_o => scl_o, -- i2c clock line output
scl_oen => scl_oen, -- i2c clock line output enable, active low
sda_i => sda_i, -- i2c data line input
sda_o => sda_o, -- i2c data line output
sda_oen => sda_oen -- i2c data line output enable, active low
);
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- Altera Stratix-III LEON3 Demonstration design test bench
-- Copyright (C) 2007 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1; -- number of ram banks
dbits : integer := CFG_DDR2SP_DATAWIDTH
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
constant lresp : boolean := false;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal Rst : std_logic := '0'; -- Reset
signal clk : std_logic := '0';
signal clk125 : std_logic := '0';
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal txd1, rxd1 : std_ulogic;
-- PSRAM and FLASH control
signal sram_advn : std_logic;
signal sram_csn : std_logic;
signal sram_wen : std_logic;
signal sram_ben : std_logic_vector (0 to 3);
signal sram_oen : std_ulogic;
signal sram_clk : std_ulogic;
signal sram_adscn : std_ulogic;
signal sram_psn : std_ulogic;
signal sram_adv_n : std_ulogic;
signal sram_wait : std_logic_vector(1 downto 0);
signal flash_clk, flash_cen, max_csn : std_logic;
signal flash_advn, flash_oen, flash_resetn, flash_wen : std_logic;
-- DDR2 memory
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_odt : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (8 downto 0); -- ddr dm
signal ddr_dqsp : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_dqsn : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_rdqs : std_logic_vector (8 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (15 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (2 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (71 downto 0); -- ddr data
signal ddr_dq2 : std_logic_vector (71 downto 0); -- ddr data
--signal ddra_cke : std_logic;
--signal ddra_csb : std_logic;
--signal ddra_web : std_ulogic; -- ddr write enable
--signal ddra_rasb : std_ulogic; -- ddr ras
--signal ddra_casb : std_ulogic; -- ddr cas
--signal ddra_ad : std_logic_vector (15 downto 0); -- ddr address
--signal ddra_ba : std_logic_vector (2 downto 0); -- ddr bank address
--signal ddrb_cke : std_logic;
--signal ddrb_csb : std_logic;
--signal ddrb_web : std_ulogic; -- ddr write enable
--signal ddrb_rasb : std_ulogic; -- ddr ras
--signal ddrb_casb : std_ulogic; -- ddr cas
--signal ddrb_ad : std_logic_vector (15 downto 0); -- ddr address
--signal ddrb_ba : std_logic_vector (2 downto 0); -- ddr bank address
--signal ddrab_clk : std_logic_vector(1 downto 0);
--signal ddrab_clkb : std_logic_vector(1 downto 0);
--signal ddrab_odt : std_logic_vector(1 downto 0);
--signal ddrab_dqsp : std_logic_vector(1 downto 0); -- ddr dqs
--signal ddrab_dqsn : std_logic_vector(1 downto 0); -- ddr dqs
--signal ddrab_dm : std_logic_vector(1 downto 0); -- ddr dm
--signal ddrab_dq : std_logic_vector (15 downto 0);-- ddr data
-- Ethernet
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk125 <= not clk125 after 4 * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
address(0) <= '0';
ddr_dq(71 downto dbits) <= (others => 'H');
ddr_dq2(71 downto dbits) <= (others => 'H');
ddr_dqsp(8 downto dbits/8) <= (others => 'H');
ddr_dqsn(8 downto dbits/8) <= (others => 'H');
ddr_rdqs(8 downto dbits/8) <= (others => 'H');
ddr_dm(8 downto dbits/8) <= (others => 'H');
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow, 50000, dbits)
port map (rst, clk, clk125, error, dsubren, dsuact,
-- rxd1, txd1,
gpio, address(25 downto 1), data, open,
sram_advn, sram_csn, sram_wen, sram_ben, sram_oen, sram_clk, sram_psn, sram_wait,
flash_clk, flash_advn, flash_cen, flash_oen, flash_resetn, flash_wen,
max_csn, iosn,
ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_odt, ddr_web,
ddr_rasb, ddr_casb, ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq,
open, open,
-- ddra_cke, ddra_csb, ddra_web, ddra_rasb, ddra_casb, ddra_ad(14 downto 0), ddra_ba, ddrb_cke,
-- ddrb_csb, ddrb_web, ddrb_rasb, ddrb_casb, ddrb_ad(14 downto 0), ddrb_ba, ddrab_clk, ddrab_clkb,
-- ddrab_odt, ddrab_dqsp, ddrab_dqsn, ddrab_dm, ddrab_dq,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n
);
ddr2delay : delay_wire
generic map(data_width => dbits, delay_atob => 0.0, delay_btoa => 5.5)
port map(a => ddr_dq(dbits-1 downto 0), b => ddr_dq2(dbits-1 downto 0));
ddr0 : ddr2ram
generic map(width => dbits, abits => 13, babits =>2, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>1, density => 2)
port map (ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke(0), csn => ddr_csb(0),
odt => ddr_odt(0), rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm(dbits/8-1 downto 0), ba => ddr_ba(1 downto 0),
a => ddr_ad(12 downto 0), dq => ddr_dq2(dbits-1 downto 0),
dqs => ddr_dqsp(dbits/8-1 downto 0), dqsn =>ddr_dqsn(dbits/8-1 downto 0));
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31 downto 16),
gnd, gnd, flash_cen, flash_wen, flash_oen);
-- -- 32 bit prom
-- prom0 : for i in 0 to 3 generate
-- sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
-- port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), flash_cen,
-- flash_wen, flash_oen);
-- end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), sram_csn,
sram_wen, sram_oen);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, sram_oen, sram_wen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
--Copyright (C) 2017 Siavoosh Payandeh Azad
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
entity RegisterFile is
generic (BitWidth: integer);
port ( clk : in std_logic;
rst: in std_logic;
Data_in_mem : in std_logic_vector (BitWidth-1 downto 0);
Data_in_CU : in std_logic_vector (BitWidth-1 downto 0);
Data_in_DPU_LOW : in std_logic_vector (BitWidth-1 downto 0);
Data_in_ACC_LOW : in std_logic_vector (BitWidth-1 downto 0);
Data_in_ACC_HI : in std_logic_vector (BitWidth-1 downto 0);
Data_in_R2 : in std_logic_vector (BitWidth-1 downto 0);
Data_in_sel : in RFILE_IN_MUX;
RFILE_in_address : in std_logic_vector (RFILE_SEL_WIDTH-1 downto 0);
WB_enable : in std_logic_vector (3 downto 0);
Register_out_sel_1 : in std_logic_vector (RFILE_SEL_WIDTH-1 downto 0);
Register_out_sel_2 : in std_logic_vector (RFILE_SEL_WIDTH-1 downto 0);
Data_out_1 : out std_logic_vector (BitWidth-1 downto 0);
Data_out_2 : out std_logic_vector (BitWidth-1 downto 0)
);
end RegisterFile;
architecture Behavioral of RegisterFile is
type RFILE_type is array (0 to RFILE_DEPTH-1) of std_logic_vector(BitWidth-1 downto 0) ;
signal RFILE : RFILE_type := ((others=> (others=>'0')));
signal Data_in: std_logic_vector (BitWidth-1 downto 0):= (others=>'0');
alias address_in : std_logic_vector(RFILE_SEL_WIDTH-1 downto 0) is RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0);
begin
CLOCK_PROCCESS: process (clk,rst)begin
if rst = '1' then
RFILE <= ((others=> (others=>'0')));
elsif clk'event and clk='1' then
if WB_enable(0) = '1' then
RFILE(to_integer(unsigned(RFILE_in_address)))(7 downto 0) <= Data_in(7 downto 0);
end if;
if WB_enable(1) = '1' then
RFILE(to_integer(unsigned(RFILE_in_address)))(15 downto 8) <= Data_in(15 downto 8);
end if;
if WB_enable(2) = '1' then
RFILE(to_integer(unsigned(RFILE_in_address)))(23 downto 16) <= Data_in(23 downto 16);
end if;
if WB_enable(3) = '1' then
RFILE(to_integer(unsigned(RFILE_in_address)))(31 downto 23) <= Data_in(31 downto 23);
end if;
RFILE(0) <= (others=>'0');
end if;
end process;
DATA_INPUT_SELECT: process(Data_in_mem,Data_in_CU,Data_in_ACC_HI, Data_in_ACC_LOW, Data_in_DPU_LOW, Data_in_sel)begin
case Data_in_sel is
when CU => Data_in <= Data_in_CU;
when DPU_LOW => Data_in <= Data_in_DPU_LOW;
when ACC_LOW => Data_in <= Data_in_ACC_LOW;
when ACC_HI => Data_in <= Data_in_ACC_HI;
when R2 => Data_in <= Data_in_R2;
when FROM_MEM8 => Data_in <= ZERO16 & ZERO8 & Data_in_mem(7 downto 0);
when FROM_MEM16 => Data_in <= ZERO16 & Data_in_mem(15 downto 0);
when FROM_MEM8_SGINED =>
if Data_in_mem(7) = '0' then
Data_in <= ZERO16 & ZERO8 & Data_in_mem(7 downto 0);
else
Data_in <= ONE16 & ONE8 & Data_in_mem(7 downto 0);
end if;
when FROM_MEM16_SGINED =>
if Data_in_mem(15) = '0' then
Data_in <= ZERO16 & Data_in_mem(15 downto 0);
else
Data_in <= ONE16 & Data_in_mem(15 downto 0);
end if;
when FROM_MEM32 => Data_in <= Data_in_mem;
when others => Data_in <= (others=>'0');
end case;
end process;
OUTPUT_1_MANAGEMENT: process(Register_out_sel_1, address_in, Data_in, WB_enable)begin
-- here we bypass the REGFILE if the address_in = Register_out_sel_1 to avoid some of the data-hazards
-- be carefull if you remove the checks for Data_in_sel then you might end up with a nice combinatorial loop
if address_in = Register_out_sel_1 and WB_enable /= "0000" then
Data_out_1 <= Data_in;
else
Data_out_1<= RFILE(to_integer(unsigned(Register_out_sel_1)));
end if;
end process;
OUTPUT_2_MANAGEMENT: process(Register_out_sel_2, address_in, Data_in, WB_enable)begin
-- here we bypass the REGFILE if the address_in = Register_out_sel_2 to avoid some of the data-hazards
-- be carefull if you remove the checks for Data_in_sel then you might end up with a nice combinatorial loop
if address_in = Register_out_sel_2 and WB_enable /= "0000" then
Data_out_2 <= Data_in;
else
Data_out_2<= RFILE(to_integer(unsigned(Register_out_sel_2)));
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- mdm_primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm_primitives.vhd
--
-- Description: one bit AND function using carry-chain
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm_primitives.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
--
-- History:
-- stefana 2014-05-23 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity carry_and is
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_and;
architecture IMP of carry_and is
signal carry_out_i : std_logic;
begin -- architecture IMP
MUXCY_I : MUXCY_L
port map (
DI => '0',
CI => Carry_IN,
S => A,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
library IEEE;
use IEEE.std_logic_1164.all;
entity carry_or_vec is
generic (
Size : natural);
port (
Carry_In : in std_logic;
In_Vec : in std_logic_vector(0 to Size-1);
Carry_Out : out std_logic);
end entity carry_or_vec;
library unisim;
use unisim.vcomponents.all;
architecture IMP of carry_or_vec is
constant C_BITS_PER_LUT : natural := 6;
signal sel : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT) - 1);
signal carry : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT));
signal sig1 : std_logic_vector(0 to sel'length*C_BITS_PER_LUT - 1);
begin -- architecture IMP
assign_sigs : process (In_Vec) is
begin -- process assign_sigs
sig1 <= (others => '0');
sig1(0 to Size-1) <= In_Vec;
end process assign_sigs;
carry(carry'right) <= Carry_In;
The_Compare : for I in sel'right downto sel'left generate
begin
Compare_All_Bits: process(sig1)
variable sel_I : std_logic;
begin
sel_I := '0';
Compare_Bits: for J in C_BITS_PER_LUT - 1 downto 0 loop
sel_I := sel_I or ( sig1(C_BITS_PER_LUT * I + J) );
end loop Compare_Bits;
sel(I) <= not sel_I;
end process Compare_All_Bits;
MUXCY_L_I1 : MUXCY_L
port map (
DI => '1', -- [in std_logic S = 0]
CI => Carry(I+1), -- [in std_logic S = 1]
S => sel(I), -- [in std_logic (Select)]
LO => Carry(I)); -- [out std_logic]
end generate The_Compare;
Carry_Out <= Carry(0);
end architecture IMP;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity carry_or is
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_or;
architecture IMP of carry_or is
signal carry_out_i : std_logic;
signal A_N : std_logic;
begin -- architecture IMP
A_N <= not A;
MUXCY_I : MUXCY_L
port map (
DI => '1',
CI => Carry_IN,
S => A_N,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity select_bit is
generic (
sel_value : std_logic_vector(1 downto 0));
port (
Mask : in std_logic_vector(1 downto 0);
Request : in std_logic_vector(1 downto 0);
Carry_In : in std_logic;
Carry_Out : out std_logic);
end entity select_bit;
architecture IMP of select_bit is
signal di : std_logic;
signal sel : std_logic;
begin -- architecture IMP
-- Just pass the carry value if none is requesting or is enabled
sel <= not( (Request(1) and Mask(1)) or (Request(0) and Mask(0)));
di <= ((Request(0) and Mask(0) and sel_value(0))) or
( not(Request(0) and Mask(0)) and Request(1) and Mask(1) and sel_value(1));
MUXCY_I : MUXCY_L
port map (
DI => di,
CI => Carry_In,
S => sel,
LO => Carry_Out);
end architecture IMP;
|
-------------------------------------------------------------------------------
-- mdm_primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm_primitives.vhd
--
-- Description: one bit AND function using carry-chain
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm_primitives.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
--
-- History:
-- stefana 2014-05-23 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity carry_and is
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_and;
architecture IMP of carry_and is
signal carry_out_i : std_logic;
begin -- architecture IMP
MUXCY_I : MUXCY_L
port map (
DI => '0',
CI => Carry_IN,
S => A,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
library IEEE;
use IEEE.std_logic_1164.all;
entity carry_or_vec is
generic (
Size : natural);
port (
Carry_In : in std_logic;
In_Vec : in std_logic_vector(0 to Size-1);
Carry_Out : out std_logic);
end entity carry_or_vec;
library unisim;
use unisim.vcomponents.all;
architecture IMP of carry_or_vec is
constant C_BITS_PER_LUT : natural := 6;
signal sel : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT) - 1);
signal carry : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT));
signal sig1 : std_logic_vector(0 to sel'length*C_BITS_PER_LUT - 1);
begin -- architecture IMP
assign_sigs : process (In_Vec) is
begin -- process assign_sigs
sig1 <= (others => '0');
sig1(0 to Size-1) <= In_Vec;
end process assign_sigs;
carry(carry'right) <= Carry_In;
The_Compare : for I in sel'right downto sel'left generate
begin
Compare_All_Bits: process(sig1)
variable sel_I : std_logic;
begin
sel_I := '0';
Compare_Bits: for J in C_BITS_PER_LUT - 1 downto 0 loop
sel_I := sel_I or ( sig1(C_BITS_PER_LUT * I + J) );
end loop Compare_Bits;
sel(I) <= not sel_I;
end process Compare_All_Bits;
MUXCY_L_I1 : MUXCY_L
port map (
DI => '1', -- [in std_logic S = 0]
CI => Carry(I+1), -- [in std_logic S = 1]
S => sel(I), -- [in std_logic (Select)]
LO => Carry(I)); -- [out std_logic]
end generate The_Compare;
Carry_Out <= Carry(0);
end architecture IMP;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity carry_or is
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_or;
architecture IMP of carry_or is
signal carry_out_i : std_logic;
signal A_N : std_logic;
begin -- architecture IMP
A_N <= not A;
MUXCY_I : MUXCY_L
port map (
DI => '1',
CI => Carry_IN,
S => A_N,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity select_bit is
generic (
sel_value : std_logic_vector(1 downto 0));
port (
Mask : in std_logic_vector(1 downto 0);
Request : in std_logic_vector(1 downto 0);
Carry_In : in std_logic;
Carry_Out : out std_logic);
end entity select_bit;
architecture IMP of select_bit is
signal di : std_logic;
signal sel : std_logic;
begin -- architecture IMP
-- Just pass the carry value if none is requesting or is enabled
sel <= not( (Request(1) and Mask(1)) or (Request(0) and Mask(0)));
di <= ((Request(0) and Mask(0) and sel_value(0))) or
( not(Request(0) and Mask(0)) and Request(1) and Mask(1) and sel_value(1));
MUXCY_I : MUXCY_L
port map (
DI => di,
CI => Carry_In,
S => sel,
LO => Carry_Out);
end architecture IMP;
|
-------------------------------------------------------------------------------
-- mdm_primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm_primitives.vhd
--
-- Description: one bit AND function using carry-chain
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm_primitives.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
--
-- History:
-- stefana 2014-05-23 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity carry_and is
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_and;
architecture IMP of carry_and is
signal carry_out_i : std_logic;
begin -- architecture IMP
MUXCY_I : MUXCY_L
port map (
DI => '0',
CI => Carry_IN,
S => A,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
library IEEE;
use IEEE.std_logic_1164.all;
entity carry_or_vec is
generic (
Size : natural);
port (
Carry_In : in std_logic;
In_Vec : in std_logic_vector(0 to Size-1);
Carry_Out : out std_logic);
end entity carry_or_vec;
library unisim;
use unisim.vcomponents.all;
architecture IMP of carry_or_vec is
constant C_BITS_PER_LUT : natural := 6;
signal sel : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT) - 1);
signal carry : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT));
signal sig1 : std_logic_vector(0 to sel'length*C_BITS_PER_LUT - 1);
begin -- architecture IMP
assign_sigs : process (In_Vec) is
begin -- process assign_sigs
sig1 <= (others => '0');
sig1(0 to Size-1) <= In_Vec;
end process assign_sigs;
carry(carry'right) <= Carry_In;
The_Compare : for I in sel'right downto sel'left generate
begin
Compare_All_Bits: process(sig1)
variable sel_I : std_logic;
begin
sel_I := '0';
Compare_Bits: for J in C_BITS_PER_LUT - 1 downto 0 loop
sel_I := sel_I or ( sig1(C_BITS_PER_LUT * I + J) );
end loop Compare_Bits;
sel(I) <= not sel_I;
end process Compare_All_Bits;
MUXCY_L_I1 : MUXCY_L
port map (
DI => '1', -- [in std_logic S = 0]
CI => Carry(I+1), -- [in std_logic S = 1]
S => sel(I), -- [in std_logic (Select)]
LO => Carry(I)); -- [out std_logic]
end generate The_Compare;
Carry_Out <= Carry(0);
end architecture IMP;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity carry_or is
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_or;
architecture IMP of carry_or is
signal carry_out_i : std_logic;
signal A_N : std_logic;
begin -- architecture IMP
A_N <= not A;
MUXCY_I : MUXCY_L
port map (
DI => '1',
CI => Carry_IN,
S => A_N,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity select_bit is
generic (
sel_value : std_logic_vector(1 downto 0));
port (
Mask : in std_logic_vector(1 downto 0);
Request : in std_logic_vector(1 downto 0);
Carry_In : in std_logic;
Carry_Out : out std_logic);
end entity select_bit;
architecture IMP of select_bit is
signal di : std_logic;
signal sel : std_logic;
begin -- architecture IMP
-- Just pass the carry value if none is requesting or is enabled
sel <= not( (Request(1) and Mask(1)) or (Request(0) and Mask(0)));
di <= ((Request(0) and Mask(0) and sel_value(0))) or
( not(Request(0) and Mask(0)) and Request(1) and Mask(1) and sel_value(1));
MUXCY_I : MUXCY_L
port map (
DI => di,
CI => Carry_In,
S => sel,
LO => Carry_Out);
end architecture IMP;
|
-------------------------------------------------------------------------------
-- mdm_primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm_primitives.vhd
--
-- Description: one bit AND function using carry-chain
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm_primitives.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
--
-- History:
-- stefana 2014-05-23 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity carry_and is
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_and;
architecture IMP of carry_and is
signal carry_out_i : std_logic;
begin -- architecture IMP
MUXCY_I : MUXCY_L
port map (
DI => '0',
CI => Carry_IN,
S => A,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
library IEEE;
use IEEE.std_logic_1164.all;
entity carry_or_vec is
generic (
Size : natural);
port (
Carry_In : in std_logic;
In_Vec : in std_logic_vector(0 to Size-1);
Carry_Out : out std_logic);
end entity carry_or_vec;
library unisim;
use unisim.vcomponents.all;
architecture IMP of carry_or_vec is
constant C_BITS_PER_LUT : natural := 6;
signal sel : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT) - 1);
signal carry : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT));
signal sig1 : std_logic_vector(0 to sel'length*C_BITS_PER_LUT - 1);
begin -- architecture IMP
assign_sigs : process (In_Vec) is
begin -- process assign_sigs
sig1 <= (others => '0');
sig1(0 to Size-1) <= In_Vec;
end process assign_sigs;
carry(carry'right) <= Carry_In;
The_Compare : for I in sel'right downto sel'left generate
begin
Compare_All_Bits: process(sig1)
variable sel_I : std_logic;
begin
sel_I := '0';
Compare_Bits: for J in C_BITS_PER_LUT - 1 downto 0 loop
sel_I := sel_I or ( sig1(C_BITS_PER_LUT * I + J) );
end loop Compare_Bits;
sel(I) <= not sel_I;
end process Compare_All_Bits;
MUXCY_L_I1 : MUXCY_L
port map (
DI => '1', -- [in std_logic S = 0]
CI => Carry(I+1), -- [in std_logic S = 1]
S => sel(I), -- [in std_logic (Select)]
LO => Carry(I)); -- [out std_logic]
end generate The_Compare;
Carry_Out <= Carry(0);
end architecture IMP;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity carry_or is
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_or;
architecture IMP of carry_or is
signal carry_out_i : std_logic;
signal A_N : std_logic;
begin -- architecture IMP
A_N <= not A;
MUXCY_I : MUXCY_L
port map (
DI => '1',
CI => Carry_IN,
S => A_N,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity select_bit is
generic (
sel_value : std_logic_vector(1 downto 0));
port (
Mask : in std_logic_vector(1 downto 0);
Request : in std_logic_vector(1 downto 0);
Carry_In : in std_logic;
Carry_Out : out std_logic);
end entity select_bit;
architecture IMP of select_bit is
signal di : std_logic;
signal sel : std_logic;
begin -- architecture IMP
-- Just pass the carry value if none is requesting or is enabled
sel <= not( (Request(1) and Mask(1)) or (Request(0) and Mask(0)));
di <= ((Request(0) and Mask(0) and sel_value(0))) or
( not(Request(0) and Mask(0)) and Request(1) and Mask(1) and sel_value(1));
MUXCY_I : MUXCY_L
port map (
DI => di,
CI => Carry_In,
S => sel,
LO => Carry_Out);
end architecture IMP;
|
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`protect end_protected
|
entity func15 is
end entity;
architecture test of func15 is
-- Generated invalid LLVM IR
function outer(d : bit_vector(7 downto 0)) return bit is
function inner(x : in bit) return bit is
begin
return not x;
end function;
begin
return inner(d(2));
end function;
begin
process is
begin
assert outer(X"ff") = '0';
wait;
end process;
end architecture;
|
entity func15 is
end entity;
architecture test of func15 is
-- Generated invalid LLVM IR
function outer(d : bit_vector(7 downto 0)) return bit is
function inner(x : in bit) return bit is
begin
return not x;
end function;
begin
return inner(d(2));
end function;
begin
process is
begin
assert outer(X"ff") = '0';
wait;
end process;
end architecture;
|
entity func15 is
end entity;
architecture test of func15 is
-- Generated invalid LLVM IR
function outer(d : bit_vector(7 downto 0)) return bit is
function inner(x : in bit) return bit is
begin
return not x;
end function;
begin
return inner(d(2));
end function;
begin
process is
begin
assert outer(X"ff") = '0';
wait;
end process;
end architecture;
|
entity func15 is
end entity;
architecture test of func15 is
-- Generated invalid LLVM IR
function outer(d : bit_vector(7 downto 0)) return bit is
function inner(x : in bit) return bit is
begin
return not x;
end function;
begin
return inner(d(2));
end function;
begin
process is
begin
assert outer(X"ff") = '0';
wait;
end process;
end architecture;
|
entity func15 is
end entity;
architecture test of func15 is
-- Generated invalid LLVM IR
function outer(d : bit_vector(7 downto 0)) return bit is
function inner(x : in bit) return bit is
begin
return not x;
end function;
begin
return inner(d(2));
end function;
begin
process is
begin
assert outer(X"ff") = '0';
wait;
end process;
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : ddr3_controller.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity ddr3_controller is
generic
(
C1_P0_MASK_SIZE : integer := 4;
C1_P0_DATA_PORT_SIZE : integer := 32;
C1_P1_MASK_SIZE : integer := 4;
C1_P1_DATA_PORT_SIZE : integer := 32;
C1_MEMCLK_PERIOD : integer := 2500;
-- Memory data transfer clock period.
C1_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C1_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C1_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C1_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C1_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C1_MEM_ADDR_WIDTH : integer := 14;
-- External memory address width.
C1_MEM_BANKADDR_WIDTH : integer := 3;
-- External memory bank address width.
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 2500;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 14;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_reset_n : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
mcb1_dram_udm : out std_logic;
c1_sys_clk_p : in std_logic;
c1_sys_clk_n : in std_logic;
c1_sys_rst_i : in std_logic;
c1_calib_done : out std_logic;
c1_clk0 : out std_logic;
c1_rst0 : out std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk_p : in std_logic;
c3_sys_clk_n : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c1_p0_cmd_clk : in std_logic;
c1_p0_cmd_en : in std_logic;
c1_p0_cmd_instr : in std_logic_vector(2 downto 0);
c1_p0_cmd_bl : in std_logic_vector(5 downto 0);
c1_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c1_p0_cmd_empty : out std_logic;
c1_p0_cmd_full : out std_logic;
c1_p0_wr_clk : in std_logic;
c1_p0_wr_en : in std_logic;
c1_p0_wr_mask : in std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
c1_p0_wr_data : in std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_wr_full : out std_logic;
c1_p0_wr_empty : out std_logic;
c1_p0_wr_count : out std_logic_vector(6 downto 0);
c1_p0_wr_underrun : out std_logic;
c1_p0_wr_error : out std_logic;
c1_p0_rd_clk : in std_logic;
c1_p0_rd_en : in std_logic;
c1_p0_rd_data : out std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_rd_full : out std_logic;
c1_p0_rd_empty : out std_logic;
c1_p0_rd_count : out std_logic_vector(6 downto 0);
c1_p0_rd_overflow : out std_logic;
c1_p0_rd_error : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic
);
end ddr3_controller;
architecture arc of ddr3_controller is
component memc1_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc1_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(2 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb1_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb1_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb1_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_reset_n : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
mcb1_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(2 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(2 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_reset_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
constant C1_CLKOUT0_DIVIDE : integer := 1;
constant C1_CLKOUT1_DIVIDE : integer := 1;
constant C1_CLKOUT2_DIVIDE : integer := 16;
constant C1_CLKOUT3_DIVIDE : integer := 8;
constant C1_CLKFBOUT_MULT : integer := 2;
constant C1_DIVCLK_DIVIDE : integer := 1;
constant C1_INCLK_PERIOD : integer := ((C1_MEMCLK_PERIOD * C1_CLKFBOUT_MULT) / (C1_DIVCLK_DIVIDE * C1_CLKOUT0_DIVIDE * 2));
constant C1_ARB_NUM_TIME_SLOTS : integer := 12;
constant C1_ARB_TIME_SLOT_0 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_1 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_2 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_3 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_4 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_5 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_6 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_7 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_8 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_9 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_10 : bit_vector(2 downto 0) := o"0";
constant C1_ARB_TIME_SLOT_11 : bit_vector(2 downto 0) := o"0";
constant C1_MEM_TRAS : integer := 36000;
constant C1_MEM_TRCD : integer := 13500;
constant C1_MEM_TREFI : integer := 7800000;
constant C1_MEM_TRFC : integer := 160000;
constant C1_MEM_TRP : integer := 13500;
constant C1_MEM_TWR : integer := 15000;
constant C1_MEM_TRTP : integer := 7500;
constant C1_MEM_TWTR : integer := 7500;
constant C1_MEM_TYPE : string := "DDR3";
constant C1_MEM_DENSITY : string := "2Gb";
constant C1_MEM_BURST_LEN : integer := 8;
constant C1_MEM_CAS_LATENCY : integer := 6;
constant C1_MEM_NUM_COL_BITS : integer := 10;
constant C1_MEM_DDR1_2_ODS : string := "FULL";
constant C1_MEM_DDR2_RTT : string := "50OHMS";
constant C1_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C1_MEM_DDR2_3_PA_SR : string := "FULL";
constant C1_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C1_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C1_MEM_DDR3_ODS : string := "DIV6";
constant C1_MEM_DDR3_RTT : string := "DIV4";
constant C1_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C1_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C1_MEM_MOBILE_PA_SR : string := "FULL";
constant C1_MEM_MDDR_ODS : string := "FULL";
constant C1_MC_CALIB_BYPASS : string := "NO";
constant C1_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C1_MC_CALIBRATION_DELAY : string := "HALF";
constant C1_SKIP_IN_TERM_CAL : integer := 0;
constant C1_SKIP_DYNAMIC_CAL : integer := 0;
constant C1_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C1_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C1_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C1_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C1_DQ0_TAP_DELAY_VAL : integer := 0;
constant C1_DQ1_TAP_DELAY_VAL : integer := 0;
constant C1_DQ2_TAP_DELAY_VAL : integer := 0;
constant C1_DQ3_TAP_DELAY_VAL : integer := 0;
constant C1_DQ4_TAP_DELAY_VAL : integer := 0;
constant C1_DQ5_TAP_DELAY_VAL : integer := 0;
constant C1_DQ6_TAP_DELAY_VAL : integer := 0;
constant C1_DQ7_TAP_DELAY_VAL : integer := 0;
constant C1_DQ8_TAP_DELAY_VAL : integer := 0;
constant C1_DQ9_TAP_DELAY_VAL : integer := 0;
constant C1_DQ10_TAP_DELAY_VAL : integer := 0;
constant C1_DQ11_TAP_DELAY_VAL : integer := 0;
constant C1_DQ12_TAP_DELAY_VAL : integer := 0;
constant C1_DQ13_TAP_DELAY_VAL : integer := 0;
constant C1_DQ14_TAP_DELAY_VAL : integer := 0;
constant C1_DQ15_TAP_DELAY_VAL : integer := 0;
constant C1_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 16;
constant C3_CLKOUT3_DIVIDE : integer := 8;
constant C3_CLKFBOUT_MULT : integer := 2;
constant C3_DIVCLK_DIVIDE : integer := 1;
constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_1 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_2 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_3 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_4 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_5 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_6 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_7 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_8 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_9 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_10 : bit_vector(2 downto 0) := o"0";
constant C3_ARB_TIME_SLOT_11 : bit_vector(2 downto 0) := o"0";
constant C3_MEM_TRAS : integer := 36000;
constant C3_MEM_TRCD : integer := 13500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 160000;
constant C3_MEM_TRP : integer := 13500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR3";
constant C3_MEM_DENSITY : string := "2Gb";
constant C3_MEM_BURST_LEN : integer := 8;
constant C3_MEM_CAS_LATENCY : integer := 6;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV4";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 0;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
signal c1_sys_clk : std_logic;
signal c1_async_rst : std_logic;
signal c1_sysclk_2x : std_logic;
signal c1_sysclk_2x_180 : std_logic;
signal c1_pll_ce_0 : std_logic;
signal c1_pll_ce_90 : std_logic;
signal c1_pll_lock : std_logic;
signal c1_mcb_drp_clk : std_logic;
signal c1_cmp_error : std_logic;
signal c1_cmp_data_valid : std_logic;
signal c1_vio_modify_enable : std_logic;
signal c1_error_status : std_logic_vector(127 downto 0);
signal c1_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c1_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c1_cmp_data : std_logic_vector(31 downto 0);
signal c3_sys_clk : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c1_selfrefresh_enter : std_logic;
signal c1_selfrefresh_mode : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
c1_sys_clk <= '0';
c3_sys_clk <= '0';
c1_selfrefresh_enter <= '0';
c3_selfrefresh_enter <= '0';
memc1_infrastructure_inst : memc1_infrastructure
generic map
(
C_RST_ACT_LOW => C1_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C1_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C1_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C1_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C1_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C1_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C1_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C1_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C1_INCLK_PERIOD
)
port map
(
sys_clk_p => c1_sys_clk_p,
sys_clk_n => c1_sys_clk_n,
sys_clk => c1_sys_clk,
sys_rst_i => c1_sys_rst_i,
clk0 => c1_clk0,
rst0 => c1_rst0,
async_rst => c1_async_rst,
sysclk_2x => c1_sysclk_2x,
sysclk_2x_180 => c1_sysclk_2x_180,
pll_ce_0 => c1_pll_ce_0,
pll_ce_90 => c1_pll_ce_90,
pll_lock => c1_pll_lock,
mcb_drp_clk => c1_mcb_drp_clk
);
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc1_wrapper_inst : memc1_wrapper
generic map
(
C_MEMCLK_PERIOD => C1_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C1_CALIB_SOFT_IP,
C_SIMULATION => C1_SIMULATION,
C_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C1_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C1_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C1_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C1_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C1_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C1_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C1_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C1_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C1_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C1_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C1_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C1_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C1_ARB_TIME_SLOT_11,
C_MEM_TRAS => C1_MEM_TRAS,
C_MEM_TRCD => C1_MEM_TRCD,
C_MEM_TREFI => C1_MEM_TREFI,
C_MEM_TRFC => C1_MEM_TRFC,
C_MEM_TRP => C1_MEM_TRP,
C_MEM_TWR => C1_MEM_TWR,
C_MEM_TRTP => C1_MEM_TRTP,
C_MEM_TWTR => C1_MEM_TWTR,
C_MEM_ADDR_ORDER => C1_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C_MEM_TYPE => C1_MEM_TYPE,
C_MEM_DENSITY => C1_MEM_DENSITY,
C_MEM_BURST_LEN => C1_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C1_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C1_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C1_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C1_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C1_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C1_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C1_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C1_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C1_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C1_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C1_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C1_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C1_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C1_MEM_DDR3_AUTO_SR,
C_MEM_MOBILE_PA_SR => C1_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C1_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C1_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C1_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C1_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C1_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C1_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C1_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C1_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C1_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C1_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C1_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C1_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C1_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C1_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C1_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C1_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C1_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C1_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C1_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C1_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C1_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C1_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C1_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C1_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C1_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C1_DQ15_TAP_DELAY_VAL
)
port map
(
mcb1_dram_dq => mcb1_dram_dq,
mcb1_dram_a => mcb1_dram_a,
mcb1_dram_ba => mcb1_dram_ba,
mcb1_dram_ras_n => mcb1_dram_ras_n,
mcb1_dram_cas_n => mcb1_dram_cas_n,
mcb1_dram_we_n => mcb1_dram_we_n,
mcb1_dram_odt => mcb1_dram_odt,
mcb1_dram_reset_n => mcb1_dram_reset_n,
mcb1_dram_cke => mcb1_dram_cke,
mcb1_dram_dm => mcb1_dram_dm,
mcb1_dram_udqs => mcb1_dram_udqs,
mcb1_dram_udqs_n => mcb1_dram_udqs_n,
mcb1_rzq => mcb1_rzq,
mcb1_zio => mcb1_zio,
mcb1_dram_udm => mcb1_dram_udm,
calib_done => c1_calib_done,
async_rst => c1_async_rst,
sysclk_2x => c1_sysclk_2x,
sysclk_2x_180 => c1_sysclk_2x_180,
pll_ce_0 => c1_pll_ce_0,
pll_ce_90 => c1_pll_ce_90,
pll_lock => c1_pll_lock,
mcb_drp_clk => c1_mcb_drp_clk,
mcb1_dram_dqs => mcb1_dram_dqs,
mcb1_dram_dqs_n => mcb1_dram_dqs_n,
mcb1_dram_ck => mcb1_dram_ck,
mcb1_dram_ck_n => mcb1_dram_ck_n,
p0_cmd_clk => c1_p0_cmd_clk,
p0_cmd_en => c1_p0_cmd_en,
p0_cmd_instr => c1_p0_cmd_instr,
p0_cmd_bl => c1_p0_cmd_bl,
p0_cmd_byte_addr => c1_p0_cmd_byte_addr,
p0_cmd_empty => c1_p0_cmd_empty,
p0_cmd_full => c1_p0_cmd_full,
p0_wr_clk => c1_p0_wr_clk,
p0_wr_en => c1_p0_wr_en,
p0_wr_mask => c1_p0_wr_mask,
p0_wr_data => c1_p0_wr_data,
p0_wr_full => c1_p0_wr_full,
p0_wr_empty => c1_p0_wr_empty,
p0_wr_count => c1_p0_wr_count,
p0_wr_underrun => c1_p0_wr_underrun,
p0_wr_error => c1_p0_wr_error,
p0_rd_clk => c1_p0_rd_clk,
p0_rd_en => c1_p0_rd_en,
p0_rd_data => c1_p0_rd_data,
p0_rd_full => c1_p0_rd_full,
p0_rd_empty => c1_p0_rd_empty,
p0_rd_count => c1_p0_rd_count,
p0_rd_overflow => c1_p0_rd_overflow,
p0_rd_error => c1_p0_rd_error,
selfrefresh_enter => c1_selfrefresh_enter,
selfrefresh_mode => c1_selfrefresh_mode
);
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p0_cmd_clk => c3_p0_cmd_clk,
p0_cmd_en => c3_p0_cmd_en,
p0_cmd_instr => c3_p0_cmd_instr,
p0_cmd_bl => c3_p0_cmd_bl,
p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
p0_cmd_empty => c3_p0_cmd_empty,
p0_cmd_full => c3_p0_cmd_full,
p0_wr_clk => c3_p0_wr_clk,
p0_wr_en => c3_p0_wr_en,
p0_wr_mask => c3_p0_wr_mask,
p0_wr_data => c3_p0_wr_data,
p0_wr_full => c3_p0_wr_full,
p0_wr_empty => c3_p0_wr_empty,
p0_wr_count => c3_p0_wr_count,
p0_wr_underrun => c3_p0_wr_underrun,
p0_wr_error => c3_p0_wr_error,
p0_rd_clk => c3_p0_rd_clk,
p0_rd_en => c3_p0_rd_en,
p0_rd_data => c3_p0_rd_data,
p0_rd_full => c3_p0_rd_full,
p0_rd_empty => c3_p0_rd_empty,
p0_rd_count => c3_p0_rd_count,
p0_rd_overflow => c3_p0_rd_overflow,
p0_rd_error => c3_p0_rd_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
end arc;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sweep is
Port ( mclk : in STD_LOGIC;
sweep_out : out std_logic_vector(1 downto 0));
end sweep;
architecture arch of sweep is
signal q: std_logic_vector(11 downto 0);
begin
--clock divider
process(mclk)
begin
if q = "1111111111" then
q <= "0000000000";
elsif mclk'event and mclk = '1' then
q <= std_logic_vector(unsigned(q)+1);
end if;
end process;
sweep_out <= q(11)&q(10);
end arch; |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sweep is
Port ( mclk : in STD_LOGIC;
sweep_out : out std_logic_vector(1 downto 0));
end sweep;
architecture arch of sweep is
signal q: std_logic_vector(11 downto 0);
begin
--clock divider
process(mclk)
begin
if q = "1111111111" then
q <= "0000000000";
elsif mclk'event and mclk = '1' then
q <= std_logic_vector(unsigned(q)+1);
end if;
end process;
sweep_out <= q(11)&q(10);
end arch; |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_ethernetlite:3.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_ethernetlite_v3_0;
USE axi_ethernetlite_v3_0.axi_ethernetlite;
ENTITY design_1_axi_ethernetlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END design_1_axi_ethernetlite_0_0;
ARCHITECTURE design_1_axi_ethernetlite_0_0_arch OF design_1_axi_ethernetlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_ethernetlite IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ACLK_PERIOD_PS : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_INCLUDE_MDIO : INTEGER;
C_INCLUDE_INTERNAL_LOOPBACK : INTEGER;
C_INCLUDE_GLOBAL_BUFFERS : INTEGER;
C_DUPLEX : INTEGER;
C_TX_PING_PONG : INTEGER;
C_RX_PING_PONG : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END COMPONENT axi_ethernetlite;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "axi_ethernetlite,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_ethernetlite_0_0_arch : ARCHITECTURE IS "design_1_axi_ethernetlite_0_0,axi_ethernetlite,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "design_1_axi_ethernetlite_0_0,axi_ethernetlite,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_ethernetlite,x_ipVersion=3.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_INSTANCE=axi_ethernetlite_inst,C_S_AXI_ACLK_PERIOD_PS=10000,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4LITE,C_INCLUDE_MDIO=1,C_INCLUDE_INTERNAL_LOOPBACK=0,C_INCLUDE_GLOBAL_BUFFERS=1,C_DUPLEX=1,C_TX_PING_PONG=1,C_RX_PING_PONG=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_crs: SIGNAL IS "xilinx.com:interface:mii:1.0 MII CRS";
ATTRIBUTE X_INTERFACE_INFO OF phy_dv: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_DV";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_col: SIGNAL IS "xilinx.com:interface:mii:1.0 MII COL";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_er: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_ER";
ATTRIBUTE X_INTERFACE_INFO OF phy_rst_n: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RST_N";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_en: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_EN";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_i: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_I";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_o: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_O";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_t: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_T";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdc: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDC";
BEGIN
U0 : axi_ethernetlite
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "axi_ethernetlite_inst",
C_S_AXI_ACLK_PERIOD_PS => 10000,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4LITE",
C_INCLUDE_MDIO => 1,
C_INCLUDE_INTERNAL_LOOPBACK => 0,
C_INCLUDE_GLOBAL_BUFFERS => 1,
C_DUPLEX => 1,
C_TX_PING_PONG => 1,
C_RX_PING_PONG => 1
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
ip2intc_irpt => ip2intc_irpt,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => '1',
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
phy_tx_clk => phy_tx_clk,
phy_rx_clk => phy_rx_clk,
phy_crs => phy_crs,
phy_dv => phy_dv,
phy_rx_data => phy_rx_data,
phy_col => phy_col,
phy_rx_er => phy_rx_er,
phy_rst_n => phy_rst_n,
phy_tx_en => phy_tx_en,
phy_tx_data => phy_tx_data,
phy_mdio_i => phy_mdio_i,
phy_mdio_o => phy_mdio_o,
phy_mdio_t => phy_mdio_t,
phy_mdc => phy_mdc
);
END design_1_axi_ethernetlite_0_0_arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_ethernetlite:3.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_ethernetlite_v3_0;
USE axi_ethernetlite_v3_0.axi_ethernetlite;
ENTITY design_1_axi_ethernetlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END design_1_axi_ethernetlite_0_0;
ARCHITECTURE design_1_axi_ethernetlite_0_0_arch OF design_1_axi_ethernetlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_ethernetlite IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ACLK_PERIOD_PS : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_INCLUDE_MDIO : INTEGER;
C_INCLUDE_INTERNAL_LOOPBACK : INTEGER;
C_INCLUDE_GLOBAL_BUFFERS : INTEGER;
C_DUPLEX : INTEGER;
C_TX_PING_PONG : INTEGER;
C_RX_PING_PONG : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END COMPONENT axi_ethernetlite;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "axi_ethernetlite,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_ethernetlite_0_0_arch : ARCHITECTURE IS "design_1_axi_ethernetlite_0_0,axi_ethernetlite,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "design_1_axi_ethernetlite_0_0,axi_ethernetlite,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_ethernetlite,x_ipVersion=3.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_INSTANCE=axi_ethernetlite_inst,C_S_AXI_ACLK_PERIOD_PS=10000,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4LITE,C_INCLUDE_MDIO=1,C_INCLUDE_INTERNAL_LOOPBACK=0,C_INCLUDE_GLOBAL_BUFFERS=1,C_DUPLEX=1,C_TX_PING_PONG=1,C_RX_PING_PONG=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_crs: SIGNAL IS "xilinx.com:interface:mii:1.0 MII CRS";
ATTRIBUTE X_INTERFACE_INFO OF phy_dv: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_DV";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_col: SIGNAL IS "xilinx.com:interface:mii:1.0 MII COL";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_er: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_ER";
ATTRIBUTE X_INTERFACE_INFO OF phy_rst_n: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RST_N";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_en: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_EN";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_i: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_I";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_o: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_O";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_t: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_T";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdc: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDC";
BEGIN
U0 : axi_ethernetlite
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "axi_ethernetlite_inst",
C_S_AXI_ACLK_PERIOD_PS => 10000,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4LITE",
C_INCLUDE_MDIO => 1,
C_INCLUDE_INTERNAL_LOOPBACK => 0,
C_INCLUDE_GLOBAL_BUFFERS => 1,
C_DUPLEX => 1,
C_TX_PING_PONG => 1,
C_RX_PING_PONG => 1
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
ip2intc_irpt => ip2intc_irpt,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => '1',
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
phy_tx_clk => phy_tx_clk,
phy_rx_clk => phy_rx_clk,
phy_crs => phy_crs,
phy_dv => phy_dv,
phy_rx_data => phy_rx_data,
phy_col => phy_col,
phy_rx_er => phy_rx_er,
phy_rst_n => phy_rst_n,
phy_tx_en => phy_tx_en,
phy_tx_data => phy_tx_data,
phy_mdio_i => phy_mdio_i,
phy_mdio_o => phy_mdio_o,
phy_mdio_t => phy_mdio_t,
phy_mdc => phy_mdc
);
END design_1_axi_ethernetlite_0_0_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2887.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x00p04n01i02887ent IS
PORT ( d : IN bit;
q : OUT bit);
END c02s01b01x00p04n01i02887ent;
ARCHITECTURE c02s01b01x00p04n01i02887arch OF c02s01b01x00p04n01i02887ent IS
procedure proc1 (variable p1 : in bit);
procedure proc2 (variable p1 : buffer bit);
procedure proc1 (variable p1 : in bit) is
variable v1 : bit;
begin
v1 := p1;
end;
procedure proc2 (variable p1 : buffer bit) is
variable v1 : bit;
begin
v1 := p1;
end;
BEGIN
proc1 (d);
proc2 (d);
q <= d;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x00p04n01i02887 - Buffer is not an allowed mode for formal parameter of a procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x00p04n01i02887arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2887.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x00p04n01i02887ent IS
PORT ( d : IN bit;
q : OUT bit);
END c02s01b01x00p04n01i02887ent;
ARCHITECTURE c02s01b01x00p04n01i02887arch OF c02s01b01x00p04n01i02887ent IS
procedure proc1 (variable p1 : in bit);
procedure proc2 (variable p1 : buffer bit);
procedure proc1 (variable p1 : in bit) is
variable v1 : bit;
begin
v1 := p1;
end;
procedure proc2 (variable p1 : buffer bit) is
variable v1 : bit;
begin
v1 := p1;
end;
BEGIN
proc1 (d);
proc2 (d);
q <= d;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x00p04n01i02887 - Buffer is not an allowed mode for formal parameter of a procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x00p04n01i02887arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2887.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x00p04n01i02887ent IS
PORT ( d : IN bit;
q : OUT bit);
END c02s01b01x00p04n01i02887ent;
ARCHITECTURE c02s01b01x00p04n01i02887arch OF c02s01b01x00p04n01i02887ent IS
procedure proc1 (variable p1 : in bit);
procedure proc2 (variable p1 : buffer bit);
procedure proc1 (variable p1 : in bit) is
variable v1 : bit;
begin
v1 := p1;
end;
procedure proc2 (variable p1 : buffer bit) is
variable v1 : bit;
begin
v1 := p1;
end;
BEGIN
proc1 (d);
proc2 (d);
q <= d;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x00p04n01i02887 - Buffer is not an allowed mode for formal parameter of a procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x00p04n01i02887arch;
|
-- Group 2: Gesture Control Interface top level file
-- Eric Smith, Chris Chmilar, Rajan Jassal
-- This file is a modified version of the top level file provided in lab 1
-- Nancy Minderman
-- [email protected]
-- This file makes extensive use of Altera template structures.
-- This file is the top-level file for lab 1 winter 2014 for version 12.1sp1 on Windows 7
-- A library clause declares a name as a library. It
-- does not create the library; it simply forward declares
-- it.
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
-- SIGNED and UNSIGNED types, and relevant functions
use ieee.numeric_std.all;
-- Basic sequential functions and concurrent procedures
use ieee.VITAL_Primitives.all;
use work.DE2_CONSTANTS.all;
entity DE2Component is
port
(
-- Input ports and 50 MHz Clock --
-- Push Buttons
KEY : in std_logic_vector (3 downto 0);
-- Switches
SW : in std_logic_vector (7 downto 0);
-- Clock
CLOCK_50 : in std_logic;
-- Green leds on board --
LEDG : out DE2_LED_GREEN;
--LCD on board
--LCD_BLON : out std_logic;
--LCD_ON : out std_logic;
--LCD_DATA : inout DE2_LCD_DATA_BUS;
--LCD_RS : out std_logic;
--LCD_EN : out std_logic;
--LCD_RW : out std_logic;
--UART interface
UART_TXD : out std_logic; -- UART Transmitter
UART_RXD : in std_logic; -- UART Receiver
--SDRAM on board
--DRAM_ADDR : out std_logic_vector (11 downto 0);
DRAM_ADDR : out DE2_SDRAM_ADDR_BUS;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
--DRAM_DQ : inout std_logic_vector (15 downto 0);
DRAM_DQ : inout DE2_SDRAM_DATA_BUS;
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- SRAM on board
SRAM_ADDR : out DE2_SRAM_ADDR_BUS;
SRAM_DQ : inout DE2_SRAM_DATA_BUS;
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic;
--Serial port pins made by us
--UART_RXD : in std_LOGIC_VECTOR(7 downto 0);
--UART_TXD : out std_LOGIC_VECTOR(7 downto 0);
-- ISP1362 USB core interface
OTG_DATA : inout std_logic_vector(15 downto 0); -- ISP1362 Data bus 16 Bits
OTG_ADDR : out std_logic_vector(1 downto 0); -- ISP1362 Address 2 Bits
OTG_CS_N : out std_logic; -- ISP1362 Chip Select
OTG_RD_N : out std_logic; -- ISP1362 Write
OTG_WR_N : out std_logic; -- ISP1362 Read
OTG_RST_N : out std_logic; -- ISP1362 Reset
OTG_INT0 : in std_logic; -- ISP1362 Interrupt 0 (for DC)
OTG_INT1 : in std_logic; -- ISP1362 Interrupt 1 (for HC)
OTG_FSPEED : out std_logic; -- USB Full Speed, 0 = Enable, Z = Disable
OTG_LSPEED : out std_logic; -- USB Low Speed, 0 = Enable, Z = Disable
OTG_DREQ0 : in std_logic; -- ISP1362 DMA Request 0
OTG_DREQ1 : in std_logic; -- ISP1362 DMA Request 1
OTG_DACK0_N : out std_logic_vector(0 downto 0) := "Z"; -- ISP1362 DMA Acknowledge 0 (not used)
OTG_DACK1_N : out std_logic_vector(0 downto 0) := "Z" -- ISP1362 DMA Acknowledge 1 (not used)
);
end DE2Component;
architecture structure of DE2Component is
component niosII_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
--sdram
sdram_0_wire_addr : out DE2_SDRAM_ADDR_BUS; -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout DE2_SDRAM_DATA_BUS := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
altpll_0_c0_clk : out std_logic; -- clk
green_leds_external_connection_export : out DE2_LED_GREEN; -- export
switches_external_connection_export : in std_logic := 'X'; -- export
--sram
sram_0_external_interface_DQ : inout DE2_SRAM_DATA_BUS := (others => 'X'); -- DQ
sram_0_external_interface_ADDR : out DE2_SRAM_ADDR_BUS; -- ADDR
sram_0_external_interface_LB_N : out std_logic; -- LB_N
sram_0_external_interface_UB_N : out std_logic; -- UB_N
sram_0_external_interface_CE_N : out std_logic; -- CE_N
sram_0_external_interface_OE_N : out std_logic; -- OE_N
sram_0_external_interface_WE_N : out std_logic; -- WE_N
--Serial port
rs232_0_external_interface_RXD : in std_lOGIC;
rs232_0_external_interface_TXD : out std_LOGIC;
--uart_0_external_connection_rxd : in std_lOGIC;
--uart_0_external_connection_txd : out std_lOGIC;
--ISP1362 Interface
usb_component_0_conduit_DATA : inout std_logic_vector(15 downto 0);
usb_component_0_conduit_ADDR : out std_logic_vector(1 downto 0);
usb_component_0_conduit_CS_N : out std_logic;
usb_component_0_conduit_RD_N : out std_logic;
usb_component_0_conduit_WR_N : out std_logic;
usb_component_0_conduit_RST_N : out std_logic;
usb_component_0_conduit_INT0 : in std_logic;
usb_component_0_conduit_INT1 : in std_logic
--LCD interface
--character_lcd_0_external_interface_DATA : inout DE2_LCD_DATA_BUS := (others => 'X'); -- DATA
--character_lcd_0_external_interface_ON : out std_logic; -- ON
--character_lcd_0_external_interface_BLON : out std_logic; -- BLON
--character_lcd_0_external_interface_EN : out std_logic; -- EN
--character_lcd_0_external_interface_RS : out std_logic; -- RS
--character_lcd_0_external_interface_RW : out std_logic -- RW
);
end component niosII_system;
-- These signals are for matching the provided IP core to
-- The specific SDRAM chip in our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
--Setting USB Speed config
OTG_FSPEED <= '0';
OTG_LSPEED <= 'Z';
--Memory related signal settings. Appears to be used for combining two signals into a singal interface.
DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
-- Component Instantiation Statement (optional)
u0 : component niosII_system
port map (
clk_clk => CLOCK_50,
reset_reset_n => KEY(0),
sdram_0_wire_addr => DRAM_ADDR,
sdram_0_wire_ba => BA,
sdram_0_wire_cas_n => DRAM_CAS_N,
sdram_0_wire_cke => DRAM_CKE,
sdram_0_wire_cs_n => DRAM_CS_N,
sdram_0_wire_dq => DRAM_DQ,
sdram_0_wire_dqm => DQM,
sdram_0_wire_ras_n => DRAM_RAS_N,
sdram_0_wire_we_n => DRAM_WE_N,
altpll_0_c0_clk => DRAM_CLK,
green_leds_external_connection_export => LEDG,
switches_external_connection_export => SW(0),
sram_0_external_interface_DQ => SRAM_DQ,
sram_0_external_interface_ADDR => SRAM_ADDR,
sram_0_external_interface_LB_N => SRAM_LB_N,
sram_0_external_interface_UB_N => SRAM_UB_N,
sram_0_external_interface_CE_N => SRAM_CE_N,
sram_0_external_interface_OE_N => SRAM_OE_N,
sram_0_external_interface_WE_N => SRAM_WE_N,
--character_lcd_0_external_interface_DATA => LCD_DATA,
--character_lcd_0_external_interface_ON => LCD_ON,
--character_lcd_0_external_interface_BLON => LCD_BLON,
--character_lcd_0_external_interface_EN => LCD_EN,
--character_lcd_0_external_interface_RS => LCD_RS,
--character_lcd_0_external_interface_RW => LCD_RW,
usb_component_0_conduit_DATA => OTG_DATA,
usb_component_0_conduit_ADDR => OTG_ADDR,
usb_component_0_conduit_CS_N => OTG_CS_N,
usb_component_0_conduit_RD_N => OTG_RD_N,
usb_component_0_conduit_WR_N => OTG_WR_N,
usb_component_0_conduit_RST_N => OTG_RST_N,
usb_component_0_conduit_INT0 => OTG_INT0,
usb_component_0_conduit_INT1 => OTG_INT1,
rs232_0_external_interface_RXD => UART_RXD,
rs232_0_external_interface_TXD => UART_TXD
--uart_0_external_connection_txd => UART_TXD,
--uart_0_external_connection_rxd => UART_RXD
);
end structure;
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
package DE2_CONSTANTS is
type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic;
type DE2_LED_GREEN is array(7 downto 0) of std_logic;
type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic;
type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic;
end DE2_CONSTANTS;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grlfpw
-- File: grlfpw.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU LITE / GRLFPC wrapper
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.gencomp.all;
entity grlfpw_net is
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 1 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of grlfpw_net is
component grlfpw_0_axcelerator is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3 is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_unisim
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_stratixii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_stratixiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_cycloneiii
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_actfus is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3e is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
component grlfpw_0_proasic3l is
port(
rst : in std_logic;
clk : in std_logic;
holdn : in std_logic;
cpi_flush : in std_logic;
cpi_exack : in std_logic;
cpi_a_rs1 : in std_logic_vector (4 downto 0);
cpi_d_pc : in std_logic_vector (31 downto 0);
cpi_d_inst : in std_logic_vector (31 downto 0);
cpi_d_cnt : in std_logic_vector (1 downto 0);
cpi_d_trap : in std_logic;
cpi_d_annul : in std_logic;
cpi_d_pv : in std_logic;
cpi_a_pc : in std_logic_vector (31 downto 0);
cpi_a_inst : in std_logic_vector (31 downto 0);
cpi_a_cnt : in std_logic_vector (1 downto 0);
cpi_a_trap : in std_logic;
cpi_a_annul : in std_logic;
cpi_a_pv : in std_logic;
cpi_e_pc : in std_logic_vector (31 downto 0);
cpi_e_inst : in std_logic_vector (31 downto 0);
cpi_e_cnt : in std_logic_vector (1 downto 0);
cpi_e_trap : in std_logic;
cpi_e_annul : in std_logic;
cpi_e_pv : in std_logic;
cpi_m_pc : in std_logic_vector (31 downto 0);
cpi_m_inst : in std_logic_vector (31 downto 0);
cpi_m_cnt : in std_logic_vector (1 downto 0);
cpi_m_trap : in std_logic;
cpi_m_annul : in std_logic;
cpi_m_pv : in std_logic;
cpi_x_pc : in std_logic_vector (31 downto 0);
cpi_x_inst : in std_logic_vector (31 downto 0);
cpi_x_cnt : in std_logic_vector (1 downto 0);
cpi_x_trap : in std_logic;
cpi_x_annul : in std_logic;
cpi_x_pv : in std_logic;
cpi_lddata : in std_logic_vector (31 downto 0);
cpi_dbg_enable : in std_logic;
cpi_dbg_write : in std_logic;
cpi_dbg_fsr : in std_logic;
cpi_dbg_addr : in std_logic_vector (4 downto 0);
cpi_dbg_data : in std_logic_vector (31 downto 0);
cpo_data : out std_logic_vector (31 downto 0);
cpo_exc : out std_logic;
cpo_cc : out std_logic_vector (1 downto 0);
cpo_ccv : out std_logic;
cpo_ldlock : out std_logic;
cpo_holdn : out std_logic;
cpo_dbg_data : out std_logic_vector (31 downto 0);
rfi1_rd1addr : out std_logic_vector (3 downto 0);
rfi1_rd2addr : out std_logic_vector (3 downto 0);
rfi1_wraddr : out std_logic_vector (3 downto 0);
rfi1_wrdata : out std_logic_vector (31 downto 0);
rfi1_ren1 : out std_logic;
rfi1_ren2 : out std_logic;
rfi1_wren : out std_logic;
rfi2_rd1addr : out std_logic_vector (3 downto 0);
rfi2_rd2addr : out std_logic_vector (3 downto 0);
rfi2_wraddr : out std_logic_vector (3 downto 0);
rfi2_wrdata : out std_logic_vector (31 downto 0);
rfi2_ren1 : out std_logic;
rfi2_ren2 : out std_logic;
rfi2_wren : out std_logic;
rfo1_data1 : in std_logic_vector (31 downto 0);
rfo1_data2 : in std_logic_vector (31 downto 0);
rfo2_data1 : in std_logic_vector (31 downto 0);
rfo2_data2 : in std_logic_vector (31 downto 0));
end component;
begin
strtxii : if (tech = altera) or (tech = stratix1) or (tech = stratix2) generate
grlfpw0 : grlfpw_0_stratixii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
strtxiii : if (tech = stratix3) or (tech = stratix4) generate
grlfpw40 : grlfpw_0_stratixiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
cyc3 : if (tech = cyclone3) generate
grlfpw40 : grlfpw_0_cycloneiii
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
ax : if (tech = axcel) or (tech = axdsp) generate
grlfpw0 : grlfpw_0_axcelerator
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
fus : if (tech = actfus) generate
grlfpw0 : grlfpw_0_actfus
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3 : if (tech = apa3) generate
grlfpw0 : grlfpw_0_proasic3
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3l : if (tech = apa3l) generate
grlfpw0 : grlfpw_0_proasic3l
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
pa3e : if (tech = apa3e) generate
grlfpw0 : grlfpw_0_proasic3e
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
uni : if (is_unisim(tech) = 1) generate
grlfpw0 : grlfpw_0_unisim
port map (rst, clk, holdn, cpi_flush, cpi_exack, cpi_a_rs1, cpi_d_pc,
cpi_d_inst, cpi_d_cnt, cpi_d_trap, cpi_d_annul, cpi_d_pv, cpi_a_pc,
cpi_a_inst, cpi_a_cnt, cpi_a_trap, cpi_a_annul, cpi_a_pv, cpi_e_pc,
cpi_e_inst, cpi_e_cnt, cpi_e_trap, cpi_e_annul, cpi_e_pv, cpi_m_pc,
cpi_m_inst, cpi_m_cnt, cpi_m_trap, cpi_m_annul, cpi_m_pv, cpi_x_pc,
cpi_x_inst, cpi_x_cnt, cpi_x_trap, cpi_x_annul, cpi_x_pv, cpi_lddata,
cpi_dbg_enable, cpi_dbg_write, cpi_dbg_fsr, cpi_dbg_addr, cpi_dbg_data,
cpo_data, cpo_exc, cpo_cc, cpo_ccv, cpo_ldlock, cpo_holdn, cpo_dbg_data,
rfi1_rd1addr, rfi1_rd2addr, rfi1_wraddr, rfi1_wrdata, rfi1_ren1,
rfi1_ren2, rfi1_wren, rfi2_rd1addr, rfi2_rd2addr, rfi2_wraddr,
rfi2_wrdata, rfi2_ren1, rfi2_ren2, rfi2_wren, rfo1_data1,
rfo1_data2, rfo2_data1, rfo2_data2 );
end generate;
end;
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: controller-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 21:36:38 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture of DLX control section.
--
use work.bv_arithmetic.all, std.textio.all;
architecture behaviour of controller is
begin -- behaviour
sequencer : process
alias IR_opcode : dlx_opcode is current_instruction(0 to 5);
alias IR_sp_func : dlx_sp_func is current_instruction(26 to 31);
alias IR_fp_func : dlx_fp_func is current_instruction(27 to 31);
alias IR_rs1 : dlx_reg_addr is current_instruction(6 to 10);
alias IR_rs2 : dlx_reg_addr is current_instruction(11 to 15);
alias IR_Itype_rd : dlx_reg_addr is current_instruction(11 to 15);
alias IR_Rtype_rd : dlx_reg_addr is current_instruction(16 to 20);
alias IR_immed16 : dlx_immed16 is current_instruction(16 to 31);
alias IR_immed26 : dlx_immed26 is current_instruction(6 to 31);
variable IR_opcode_num : dlx_opcode_num;
variable IR_sp_func_num : dlx_sp_func_num;
variable IR_fp_func_num : dlx_fp_func_num;
variable result_of_set_is_1, branch_taken : boolean;
variable L : line;
procedure bus_instruction_fetch is
begin
-- use PC as address
mem_addr_mux_sel <= '0' after Tpd_clk_ctrl;
-- set up memory control signals
width <= width_word after Tpd_clk_ctrl;
ifetch <= '1' after Tpd_clk_ctrl;
mem_enable <= '1' after Tpd_clk_ctrl;
-- wait until phi2, then enable IR input
wait until phi2 = '1';
ir_latch_en <= '1' after Tpd_clk_ctrl;
-- wait until memory is ready at end of phi2
loop
wait until phi2 = '0';
if reset = '1' then
return;
end if;
exit when ready = '1';
end loop;
-- disable IR input and memory control signals
ir_latch_en <= '0' after Tpd_clk_ctrl;
mem_enable <= '0' after Tpd_clk_ctrl;
end bus_instruction_fetch;
procedure bus_data_read(read_width : in mem_width) is
begin
-- use MAR as address
mem_addr_mux_sel <= '1' after Tpd_clk_ctrl;
-- set up memory control signals
width <= read_width after Tpd_clk_ctrl;
ifetch <= '0' after Tpd_clk_ctrl;
mem_enable <= '1' after Tpd_clk_ctrl;
-- wait until phi2, then enable MDR input
wait until phi2 = '1';
mdr_mux_sel <= '1' after Tpd_clk_ctrl;
mdr_latch_en <= '1' after Tpd_clk_ctrl;
-- wait until memory is ready at end of phi2
loop
wait until phi2 = '0';
if reset = '1' then
return;
end if;
exit when ready = '1';
end loop;
-- disable MDR input and memory control signals
mdr_latch_en <= '0' after Tpd_clk_ctrl;
mem_enable <= '0' after Tpd_clk_ctrl;
end bus_data_read;
procedure bus_data_write(write_width : in mem_width) is
begin
-- use MAR as address
mem_addr_mux_sel <= '1' after Tpd_clk_ctrl;
-- enable MDR output
mdr_out_en3 <= '1' after Tpd_clk_ctrl;
-- set up memory control signals
width <= write_width after Tpd_clk_ctrl;
ifetch <= '0' after Tpd_clk_ctrl;
write_enable <= '1' after Tpd_clk_ctrl;
mem_enable <= '1' after Tpd_clk_ctrl;
-- wait until memory is ready at end of phi2
loop
wait until phi2 = '0';
if reset = '1' then
return;
end if;
exit when ready = '1';
end loop;
-- disable MDR output and memory control signals
write_enable <= '0' after Tpd_clk_ctrl;
mem_enable <= '0' after Tpd_clk_ctrl;
mdr_out_en3 <= '0' after Tpd_clk_ctrl;
end bus_data_write;
procedure do_set_result is
begin
wait until phi1 = '1';
if result_of_set_is_1 then
const2 <= X"0000_0001" after Tpd_clk_const;
else
const2 <= X"0000_0000" after Tpd_clk_const;
end if;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_pass_s2 after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
const2 <= null after Tpd_clk_const;
--
wait until phi2 = '1';
c_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
c_latch_en <= '0' after Tpd_clk_ctrl;
end do_set_result;
procedure do_EX_set_unsigned(immed : boolean) is
begin
wait until phi1 = '1';
a_out_en <= '1' after Tpd_clk_ctrl;
if immed then
ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
ir_immed_unsigned2 <= '1' after Tpd_clk_ctrl;
ir_immed_en2 <= '1' after Tpd_clk_ctrl;
else
b_out_en <= '1' after Tpd_clk_ctrl;
end if;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_subu after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
if immed then
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
else
b_out_en <= '0' after Tpd_clk_ctrl;
end if;
--
wait until phi2 = '0';
if immed then
case IR_opcode is
when op_sequi =>
result_of_set_is_1 := alu_zero = '1';
when op_sneui =>
result_of_set_is_1 := alu_zero /= '1';
when op_sltui =>
result_of_set_is_1 := alu_overflow = '1';
when op_sgtui =>
result_of_set_is_1 := alu_overflow /= '1' and alu_zero /= '1';
when op_sleui =>
result_of_set_is_1 := alu_overflow = '1' or alu_zero = '1';
when op_sgeui =>
result_of_set_is_1 := alu_overflow /= '1';
when others =>
null;
end case;
else
case IR_sp_func is
when sp_func_sequ =>
result_of_set_is_1 := alu_zero = '1';
when sp_func_sneu =>
result_of_set_is_1 := alu_zero /= '1';
when sp_func_sltu =>
result_of_set_is_1 := alu_overflow = '1';
when sp_func_sgtu =>
result_of_set_is_1 := alu_overflow /= '1' and alu_zero /= '1';
when sp_func_sleu =>
result_of_set_is_1 := alu_overflow = '1' or alu_zero = '1';
when sp_func_sgeu =>
result_of_set_is_1 := alu_overflow /= '1';
when others =>
null;
end case;
end if;
--
do_set_result;
end do_EX_set_unsigned;
procedure do_EX_set_signed(immed : boolean) is
begin
wait until phi1 = '1';
a_out_en <= '1' after Tpd_clk_ctrl;
if immed then
ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '1' after Tpd_clk_ctrl;
else
b_out_en <= '1' after Tpd_clk_ctrl;
end if;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_sub after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
if immed then
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
else
b_out_en <= '0' after Tpd_clk_ctrl;
end if;
--
wait until phi2 = '0';
if immed then
case IR_opcode is
when op_seqi =>
result_of_set_is_1 := alu_zero = '1';
when op_snei =>
result_of_set_is_1 := alu_zero /= '1';
when op_slti =>
result_of_set_is_1 := alu_negative = '1';
when op_sgti =>
result_of_set_is_1 := alu_negative /= '1' and alu_zero /= '1';
when op_slei =>
result_of_set_is_1 := alu_negative = '1' or alu_zero = '1';
when op_sgei =>
result_of_set_is_1 := alu_negative /= '1';
when others =>
null;
end case;
else
case IR_sp_func is
when sp_func_seq =>
result_of_set_is_1 := alu_zero = '1';
when sp_func_sne =>
result_of_set_is_1 := alu_zero /= '1';
when sp_func_slt =>
result_of_set_is_1 := alu_negative = '1';
when sp_func_sgt =>
result_of_set_is_1 := alu_negative /= '1' and alu_zero /= '1';
when sp_func_sle =>
result_of_set_is_1 := alu_negative = '1' or alu_zero = '1';
when sp_func_sge =>
result_of_set_is_1 := alu_negative /= '1';
when others =>
null;
end case;
end if;
--
do_set_result;
end do_EX_set_signed;
procedure do_EX_arith_logic is
begin
wait until phi1 = '1';
a_out_en <= '1' after Tpd_clk_ctrl;
b_out_en <= '1' after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
case IR_sp_func is
when sp_func_add =>
alu_function <= alu_add after Tpd_clk_ctrl;
when sp_func_addu =>
alu_function <= alu_addu after Tpd_clk_ctrl;
when sp_func_sub =>
alu_function <= alu_sub after Tpd_clk_ctrl;
when sp_func_subu =>
alu_function <= alu_subu after Tpd_clk_ctrl;
when sp_func_and =>
alu_function <= alu_and after Tpd_clk_ctrl;
when sp_func_or =>
alu_function <= alu_or after Tpd_clk_ctrl;
when sp_func_xor =>
alu_function <= alu_xor after Tpd_clk_ctrl;
when sp_func_sll =>
alu_function <= alu_sll after Tpd_clk_ctrl;
when sp_func_srl =>
alu_function <= alu_srl after Tpd_clk_ctrl;
when sp_func_sra =>
alu_function <= alu_sra after Tpd_clk_ctrl;
when others =>
null;
end case; -- IR_sp_func
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
b_out_en <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
c_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
c_latch_en <= '0' after Tpd_clk_ctrl;
end do_EX_arith_logic;
procedure do_EX_arith_logic_immed is
begin
wait until phi1 = '1';
a_out_en <= '1' after Tpd_clk_ctrl;
ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
if IR_opcode = op_addi or IR_opcode = op_subi then
ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
else
ir_immed_unsigned2 <= '1' after Tpd_clk_ctrl;
end if;
ir_immed_en2 <= '1' after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
case IR_opcode is
when op_addi =>
alu_function <= alu_add after Tpd_clk_ctrl;
when op_subi =>
alu_function <= alu_sub after Tpd_clk_ctrl;
when op_addui =>
alu_function <= alu_addu after Tpd_clk_ctrl;
when op_subui =>
alu_function <= alu_subu after Tpd_clk_ctrl;
when op_andi =>
alu_function <= alu_and after Tpd_clk_ctrl;
when op_ori =>
alu_function <= alu_or after Tpd_clk_ctrl;
when op_xori =>
alu_function <= alu_xor after Tpd_clk_ctrl;
when op_slli =>
alu_function <= alu_sll after Tpd_clk_ctrl;
when op_srli =>
alu_function <= alu_srl after Tpd_clk_ctrl;
when op_srai =>
alu_function <= alu_sra after Tpd_clk_ctrl;
when others =>
null;
end case; -- IR_opcode
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
c_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
c_latch_en <= '0' after Tpd_clk_ctrl;
end do_EX_arith_logic_immed;
procedure do_EX_link is
begin
wait until phi1 = '1';
pc_out_en1 <= '1' after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
pc_out_en1 <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
c_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
c_latch_en <= '0' after Tpd_clk_ctrl;
end do_EX_link;
procedure do_EX_lhi is
begin
wait until phi1 = '1';
ir_immed_sel1 <= immed_size_16 after Tpd_clk_ctrl;
ir_immed_unsigned1 <= '1' after Tpd_clk_ctrl;
ir_immed_en1 <= '1' after Tpd_clk_ctrl;
const2 <= X"0000_0010" after Tpd_clk_const; -- shift by 16 bits
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_sll after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
ir_immed_en1 <= '0' after Tpd_clk_ctrl;
const2 <= null after Tpd_clk_const;
--
wait until phi2 = '1';
c_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
c_latch_en <= '0' after Tpd_clk_ctrl;
end do_EX_lhi;
procedure do_EX_branch is
begin
wait until phi1 = '1';
a_out_en <= '1' after Tpd_clk_ctrl;
const2 <= X"0000_0000" after Tpd_clk_const;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_sub after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
const2 <= null after Tpd_clk_const;
--
wait until phi2 = '0';
if IR_opcode = op_beqz then
branch_taken := alu_zero = '1';
else
branch_taken := alu_zero /= '1';
end if;
end do_EX_branch;
procedure do_EX_load_store is
begin
wait until phi1 = '1';
a_out_en <= '1' after Tpd_clk_ctrl;
ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '1' after Tpd_clk_ctrl;
alu_function <= alu_add after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
mar_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
mar_latch_en <= '0' after Tpd_clk_ctrl;
end do_EX_load_store;
procedure do_MEM_jump is
begin
wait until phi1 = '1';
pc_out_en1 <= '1' after Tpd_clk_ctrl;
ir_immed_sel2 <= immed_size_26 after Tpd_clk_ctrl;
ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '1' after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_add after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
pc_out_en1 <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
pc_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
pc_latch_en <= '0' after Tpd_clk_ctrl;
end do_MEM_jump;
procedure do_MEM_jump_reg is
begin
wait until phi1 = '1';
a_out_en <= '1' after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
pc_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
pc_latch_en <= '0' after Tpd_clk_ctrl;
end do_MEM_jump_reg;
procedure do_MEM_branch is
begin
wait until phi1 = '1';
pc_out_en1 <= '1' after Tpd_clk_ctrl;
ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '1' after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_add after Tpd_clk_ctrl;
--
wait until phi1 = '0';
alu_latch_en <= '0' after Tpd_clk_ctrl;
pc_out_en1 <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
pc_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
pc_latch_en <= '0' after Tpd_clk_ctrl;
end do_MEM_branch;
procedure do_MEM_load is
begin
wait until phi1 = '1';
bus_data_read(width_word);
if reset = '1' then
return;
end if;
--
wait until phi1 = '1';
mdr_out_en1 <= '1' after Tpd_clk_ctrl;
alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi1 = '0';
mdr_out_en1 <= '0' after Tpd_clk_ctrl;
alu_latch_en <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
c_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
c_latch_en <= '0' after Tpd_clk_ctrl;
end do_MEM_load;
procedure do_MEM_store is
begin
wait until phi1 = '1';
b_out_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_pass_s2 after Tpd_clk_ctrl;
alu_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi1 = '0';
b_out_en <= '0' after Tpd_clk_ctrl;
alu_latch_en <= '0' after Tpd_clk_ctrl;
--
wait until phi2 = '1';
mdr_mux_sel <= '0' after Tpd_clk_ctrl;
mdr_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
mdr_latch_en <= '0' after Tpd_clk_ctrl;
--
wait until phi1 = '1';
bus_data_write(width_word);
end do_MEM_store;
procedure do_WB(Rd : dlx_reg_addr) is
begin
wait until phi1 = '1';
reg_dest_addr <= Rd after Tpd_clk_ctrl;
reg_write <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
reg_write <= '0' after Tpd_clk_ctrl;
end do_WB;
begin -- sequencer
--
----------------------------------------------------------------
-- initialize all control signals
----------------------------------------------------------------
if debug then
write(L, string'("controller: initializing"));
writeline(output, L);
end if;
--
halt <= '0' after Tpd_clk_ctrl;
width <= width_word after Tpd_clk_ctrl;
write_enable <= '0' after Tpd_clk_ctrl;
mem_enable <= '0' after Tpd_clk_ctrl;
ifetch <= '0' after Tpd_clk_ctrl;
alu_latch_en <= '0' after Tpd_clk_ctrl;
alu_function <= alu_add after Tpd_clk_ctrl;
reg_s1_addr <= B"00000" after Tpd_clk_ctrl;
reg_s2_addr <= B"00000" after Tpd_clk_ctrl;
reg_dest_addr <= B"00000" after Tpd_clk_ctrl;
reg_write <= '0' after Tpd_clk_ctrl;
c_latch_en <= '0' after Tpd_clk_ctrl;
a_latch_en <= '0' after Tpd_clk_ctrl;
a_out_en <= '0' after Tpd_clk_ctrl;
b_latch_en <= '0' after Tpd_clk_ctrl;
b_out_en <= '0' after Tpd_clk_ctrl;
temp_latch_en <= '0' after Tpd_clk_ctrl;
temp_out_en1 <= '0' after Tpd_clk_ctrl;
temp_out_en2 <= '0' after Tpd_clk_ctrl;
iar_latch_en <= '0' after Tpd_clk_ctrl;
iar_out_en1 <= '0' after Tpd_clk_ctrl;
iar_out_en2 <= '0' after Tpd_clk_ctrl;
pc_latch_en <= '0' after Tpd_clk_ctrl;
pc_out_en1 <= '0' after Tpd_clk_ctrl;
pc_out_en2 <= '0' after Tpd_clk_ctrl;
mar_latch_en <= '0' after Tpd_clk_ctrl;
mar_out_en1 <= '0' after Tpd_clk_ctrl;
mar_out_en2 <= '0' after Tpd_clk_ctrl;
mem_addr_mux_sel <= '0' after Tpd_clk_ctrl;
mdr_latch_en <= '0' after Tpd_clk_ctrl;
mdr_out_en1 <= '0' after Tpd_clk_ctrl;
mdr_out_en2 <= '0' after Tpd_clk_ctrl;
mdr_out_en3 <= '0' after Tpd_clk_ctrl;
mdr_mux_sel <= '0' after Tpd_clk_ctrl;
ir_latch_en <= '0' after Tpd_clk_ctrl;
ir_immed_sel1 <= immed_size_16 after Tpd_clk_ctrl;
ir_immed_sel2 <= immed_size_16 after Tpd_clk_ctrl;
ir_immed_unsigned1 <= '0' after Tpd_clk_ctrl;
ir_immed_unsigned2 <= '0' after Tpd_clk_ctrl;
ir_immed_en1 <= '0' after Tpd_clk_ctrl;
ir_immed_en2 <= '0' after Tpd_clk_ctrl;
const1 <= null after Tpd_clk_const;
const2 <= null after Tpd_clk_const;
--
wait until phi2 = '0' and reset = '0';
--
----------------------------------------------------------------
-- control loop
----------------------------------------------------------------
loop
--
----------------------------------------------------------------
-- fetch next instruction (IF)
----------------------------------------------------------------
wait until phi1 = '1';
if debug then
write(L, string'("controller: instruction fetch"));
writeline(output, L);
end if;
--
bus_instruction_fetch;
--
----------------------------------------------------------------
-- instruction decode, source register read, and PC increment (ID)
----------------------------------------------------------------
wait until phi1 = '1';
if debug then
write(L, string'("controller: decode, reg-read and PC incr"));
writeline(output, L);
end if;
--
IR_opcode_num := bv_to_natural(IR_opcode);
IR_sp_func_num := bv_to_natural(IR_sp_func);
IR_fp_func_num := bv_to_natural(IR_fp_func);
--
reg_s1_addr <= IR_rs1 after Tpd_clk_ctrl;
reg_s2_addr <= IR_rs2 after Tpd_clk_ctrl;
a_latch_en <= '1' after Tpd_clk_ctrl;
b_latch_en <= '1' after Tpd_clk_ctrl;
--
pc_out_en1 <= '1' after Tpd_clk_ctrl;
const2 <= X"0000_0004" after Tpd_clk_const;
alu_latch_en <= '1' after Tpd_clk_ctrl;
alu_function <= alu_addu after Tpd_clk_ctrl;
--
wait until phi1 = '0';
a_latch_en <= '0' after Tpd_clk_ctrl;
b_latch_en <= '0' after Tpd_clk_ctrl;
alu_latch_en <= '0' after Tpd_clk_ctrl;
pc_out_en1 <= '0' after Tpd_clk_ctrl;
const2 <= null after Tpd_clk_const;
--
wait until phi2 = '1';
pc_latch_en <= '1' after Tpd_clk_ctrl;
--
wait until phi2 = '0';
pc_latch_en <= '0' after Tpd_clk_ctrl;
--
----------------------------------------------------------------
-- execute instruction, (EX, MEM, WB)
----------------------------------------------------------------
if debug then
write(L, string'("controller: execute"));
writeline(output, L);
end if;
--
case IR_opcode is
when op_special =>
case IR_sp_func is
when sp_func_nop =>
null;
when sp_func_sequ | sp_func_sneu |
sp_func_sltu | sp_func_sgtu |
sp_func_sleu | sp_func_sgeu =>
do_EX_set_unsigned(immed => false);
do_WB(IR_Rtype_rd);
when sp_func_add | sp_func_addu |
sp_func_sub | sp_func_subu |
sp_func_and | sp_func_or | sp_func_xor |
sp_func_sll | sp_func_srl | sp_func_sra =>
do_EX_arith_logic;
do_WB(IR_Rtype_rd);
when sp_func_seq | sp_func_sne |
sp_func_slt | sp_func_sgt |
sp_func_sle | sp_func_sge =>
do_EX_set_signed(immed => false);
do_WB(IR_Rtype_rd);
when sp_func_movi2s =>
assert false
report "MOVI2S instruction not implemented" severity warning;
when sp_func_movs2i =>
assert false
report "MOVS2I instruction not implemented" severity warning;
when sp_func_movf =>
assert false
report "MOVF instruction not implemented" severity warning;
when sp_func_movd =>
assert false
report "MOVD instruction not implemented" severity warning;
when sp_func_movfp2i =>
assert false
report "MOVFP2I instruction not implemented" severity warning;
when sp_func_movi2fp =>
assert false
report "MOVI2FP instruction not implemented" severity warning;
when others =>
assert false
report "undefined special instruction function" severity error;
end case;
when op_fparith =>
case IR_fp_func is
when fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf |
fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd |
fp_func_mult | fp_func_multu | fp_func_div | fp_func_divu |
fp_func_cvtf2d | fp_func_cvtf2i | fp_func_cvtd2f |
fp_func_cvtd2i | fp_func_cvti2f | fp_func_cvti2d |
fp_func_eqf | fp_func_nef | fp_func_ltf | fp_func_gtf |
fp_func_lef | fp_func_gef | fp_func_eqd | fp_func_ned |
fp_func_ltd | fp_func_gtd | fp_func_led | fp_func_ged =>
assert false
report "floating point instructions not implemented" severity warning;
when others =>
assert false
report "undefined floating point instruction function" severity error;
end case;
when op_j =>
do_MEM_jump;
when op_jr =>
do_MEM_jump_reg;
when op_jal =>
do_EX_link;
do_MEM_jump;
do_WB(natural_to_bv(link_reg, 5));
when op_jalr =>
do_EX_link;
do_MEM_jump_reg;
do_WB(natural_to_bv(link_reg, 5));
when op_beqz | op_bnez =>
do_EX_branch;
if branch_taken then
do_MEM_branch;
end if;
when op_bfpt =>
assert false
report "BFPT instruction not implemented" severity warning;
when op_bfpf =>
assert false
report "BFPF instruction not implemented" severity warning;
when op_addi | op_subi |
op_addui | op_subui |
op_andi | op_ori | op_xori |
op_slli | op_srli | op_srai =>
do_EX_arith_logic_immed;
do_WB(IR_Itype_rd);
when op_lhi =>
do_EX_lhi;
do_WB(IR_Itype_rd);
when op_rfe =>
assert false
report "RFE instruction not implemented" severity warning;
when op_trap =>
assert false
report "TRAP instruction encountered, execution halted"
severity note;
wait until phi1 = '1';
halt <= '1' after Tpd_clk_ctrl;
wait until reset = '1';
exit;
when op_seqi | op_snei | op_slti |
op_sgti | op_slei | op_sgei =>
do_EX_set_signed(immed => true);
do_WB(IR_Itype_rd);
when op_lb =>
assert false
report "LB instruction not implemented" severity warning;
when op_lh =>
assert false
report "LH instruction not implemented" severity warning;
when op_lw =>
do_EX_load_store;
do_MEM_load;
exit when reset = '1';
do_WB(IR_Itype_rd);
when op_sw =>
do_EX_load_store;
do_MEM_store;
exit when reset = '1';
when op_lbu =>
assert false
report "LBU instruction not implemented" severity warning;
when op_lhu =>
assert false
report "LHU instruction not implemented" severity warning;
when op_sb =>
assert false
report "SB instruction not implemented" severity warning;
when op_sh =>
assert false
report "SH instruction not implemented" severity warning;
when op_lf =>
assert false
report "LF instruction not implemented" severity warning;
when op_ld =>
assert false
report "LD instruction not implemented" severity warning;
when op_sf =>
assert false
report "SF instruction not implemented" severity warning;
when op_sd =>
assert false
report "SD instruction not implemented" severity warning;
when op_sequi | op_sneui | op_sltui |
op_sgtui | op_sleui | op_sgeui =>
do_EX_set_unsigned(immed => true);
do_WB(IR_Itype_rd);
when others =>
assert false
report "undefined instruction" severity error;
end case;
--
end loop;
--
----------------------------------------------------------------
-- loop exited on reset
----------------------------------------------------------------
assert reset = '1'
report "Internal error: reset code reached with reset = '0'"
severity failure;
--
-- start again
--
end process sequencer;
end behaviour;
|
library verilog;
use verilog.vl_types.all;
entity finalproject_sdram_input_efifo_module is
port(
clk : in vl_logic;
rd : in vl_logic;
reset_n : in vl_logic;
wr : in vl_logic;
wr_data : in vl_logic_vector(61 downto 0);
almost_empty : out vl_logic;
almost_full : out vl_logic;
empty : out vl_logic;
full : out vl_logic;
rd_data : out vl_logic_vector(61 downto 0)
);
end finalproject_sdram_input_efifo_module;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1.1
-- Version history :
-- V1 : 2015-04-07 : Mickael Carl (CNES): Creation
-- V1.1 : 2016-05-03 : F.Manni (CNES) : add initialization for D_re
-------------------------------------------------------------------------------------------------
-- File name : STD_03600_bad.vhd
-- File Creation date : 2015-04-07
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Reset sensitive level: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_03600_bad is
port (
i_Reset_n : in std_logic; -- Reset signal
i_Clock : in std_logic; -- Clock signal
i_D : in std_logic; -- Async signal
o_Q : out std_logic -- Rising edge of i_D
);
end STD_03600_bad;
--CODE
architecture Behavioral of STD_03600_bad is
signal D_r1 : std_logic; -- D signal registered 1 time
signal D_r2 : std_logic; -- D signal registered 2 times
signal D_re : std_logic; -- Module output
signal Reset : std_logic; -- Reset signal (active high)
begin
P_First_Register : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
D_r1 <= '0';
elsif (rising_edge(i_Clock)) then
D_r1 <= i_D;
end if;
end process;
Reset <= not i_Reset_n;
P_Second_Register : process(Reset, i_Clock)
begin
if (Reset = '1') then
D_r2 <= '0';
D_re <= '0';
elsif (rising_edge(i_Clock)) then
D_r2 <= D_r1;
D_re <= D_r1 and not D_r2;
end if;
end process;
o_Q <= D_re;
end Behavioral;
--CODE
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Block1 IS
PORT(
D : IN STD_LOGIC;
C : IN STD_LOGIC;
B : IN STD_LOGIC;
A : IN STD_LOGIC;
E : OUT STD_LOGIC);
END Block1;
ARCHITECTURE logic OF Block1 IS
BEGIN
E <= (D AND C AND A) OR (NOT(C) AND NOT(A)) OR (A AND NOT(B));
END logic;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc73.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p09n02i00073ent IS
END c04s03b01x02p09n02i00073ent;
ARCHITECTURE c04s03b01x02p09n02i00073arch OF c04s03b01x02p09n02i00073ent IS
signal s1 : bit register; -- Failure_here
-- a guarded signal, but is not a resolved signal.
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x02p09n02i00073- Guarded signal should be a resolved signal."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x02p09n02i00073arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc73.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p09n02i00073ent IS
END c04s03b01x02p09n02i00073ent;
ARCHITECTURE c04s03b01x02p09n02i00073arch OF c04s03b01x02p09n02i00073ent IS
signal s1 : bit register; -- Failure_here
-- a guarded signal, but is not a resolved signal.
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x02p09n02i00073- Guarded signal should be a resolved signal."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x02p09n02i00073arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc73.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p09n02i00073ent IS
END c04s03b01x02p09n02i00073ent;
ARCHITECTURE c04s03b01x02p09n02i00073arch OF c04s03b01x02p09n02i00073ent IS
signal s1 : bit register; -- Failure_here
-- a guarded signal, but is not a resolved signal.
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x02p09n02i00073- Guarded signal should be a resolved signal."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x02p09n02i00073arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_0_0;
ARCHITECTURE system_vga_sync_0_0_arch OF system_vga_sync_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "vga_sync,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_0_0_arch : ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_FRONT_DELAY=16,H_BACK_DELAY=48,H_RETRACE_DELAY=96,V_SIZE=480,V_FRONT_DELAY=10,V_BACK_DELAY=33,V_RETRACE_DELAY=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk_25 => clk_25,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_0_0_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_0_0;
ARCHITECTURE system_vga_sync_0_0_arch OF system_vga_sync_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "vga_sync,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_0_0_arch : ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_FRONT_DELAY=16,H_BACK_DELAY=48,H_RETRACE_DELAY=96,V_SIZE=480,V_FRONT_DELAY=10,V_BACK_DELAY=33,V_RETRACE_DELAY=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk_25 => clk_25,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_0_0_arch;
|
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity lifo_tb is
-- Generic declarations of the tested unit
generic(
m : INTEGER := 5;
n : INTEGER := 16 );
end lifo_tb;
architecture TB_ARCHITECTURE of lifo_tb is
-- Component declaration of the tested unit
component lifo
generic(
m : INTEGER := 5;
n : INTEGER := 16 );
port(
EN : in STD_LOGIC;
CLK : in STD_LOGIC;
WR : in STD_LOGIC;
RB : out STD_LOGIC_VECTOR(n-1 downto 0);
WB : in STD_LOGIC_VECTOR(n-1 downto 0) );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal EN : STD_LOGIC;
signal CLK : STD_LOGIC;
signal WR : STD_LOGIC;
signal WB : STD_LOGIC_VECTOR(n-1 downto 0);
-- Observed signals - signals mapped to the output ports of tested entity
signal RB : STD_LOGIC_VECTOR(n-1 downto 0);
constant CLK_Period: time := 10 ns;
begin
-- Unit Under Test port map
UUT : lifo
generic map (
m => m,
n => n
)
port map (
EN => EN,
CLK => CLK,
WR => WR,
RB => RB,
WB => WB
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
MAIN: process
begin
wait for clk_period;
en <= '1';
WR <= '0';
wb <= "0000000000000001";
wait for clk_period;
wb <= "0000000000000010";
wait for clk_period;
wb <= "0000000000000011";
wait for clk_period;
WR <= '1';
wait for clk_period;
wait for clk_period;
wait for clk_period;
en <= '0';
wait for clk_period;
en <= '1';
WR <= '0';
wb <= "0000000000001001";
wait for clk_period;
wb <= "0000000000001010";
wait for clk_period;
wb <= "0000000000001011";
wait for clk_period;
wb <= "0000000000001100";
wait for clk_period;
wb <= "0000000000001101";
wait for clk_period;
en <= '0';
wait for clk_period;
WR <= '1';
en <= '1';
wait for clk_period;
wait for clk_period;
wait for clk_period;
en <= '0';
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_lifo of lifo_tb is
for TB_ARCHITECTURE
for UUT : lifo
use entity work.lifo(beh);
end for;
end for;
end TESTBENCH_FOR_lifo;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1457.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01457ent IS
END c08s07b00x00p04n01i01457ent;
ARCHITECTURE c08s07b00x00p04n01i01457arch OF c08s07b00x00p04n01i01457ent IS
BEGIN
TESTING : PROCESS
variable a : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
BEGIN
if a = 0 then
m := 1;
elsif a = 1 then
k := 1;
end if;
wait for 5 ns;
assert NOT((m = 0) and (k = 1))
report "***PASSED TEST: c08s07b00x00p04n01i01457"
severity NOTE;
assert (m = 0) and (k = 1)
report "***FAILED TEST: c08s07b00x00p04n01i01457 - only the condition after the ELSIF statement is TRUE, all others should be FALSE"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s07b00x00p04n01i01457arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1457.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01457ent IS
END c08s07b00x00p04n01i01457ent;
ARCHITECTURE c08s07b00x00p04n01i01457arch OF c08s07b00x00p04n01i01457ent IS
BEGIN
TESTING : PROCESS
variable a : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
BEGIN
if a = 0 then
m := 1;
elsif a = 1 then
k := 1;
end if;
wait for 5 ns;
assert NOT((m = 0) and (k = 1))
report "***PASSED TEST: c08s07b00x00p04n01i01457"
severity NOTE;
assert (m = 0) and (k = 1)
report "***FAILED TEST: c08s07b00x00p04n01i01457 - only the condition after the ELSIF statement is TRUE, all others should be FALSE"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s07b00x00p04n01i01457arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1457.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01457ent IS
END c08s07b00x00p04n01i01457ent;
ARCHITECTURE c08s07b00x00p04n01i01457arch OF c08s07b00x00p04n01i01457ent IS
BEGIN
TESTING : PROCESS
variable a : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
BEGIN
if a = 0 then
m := 1;
elsif a = 1 then
k := 1;
end if;
wait for 5 ns;
assert NOT((m = 0) and (k = 1))
report "***PASSED TEST: c08s07b00x00p04n01i01457"
severity NOTE;
assert (m = 0) and (k = 1)
report "***FAILED TEST: c08s07b00x00p04n01i01457 - only the condition after the ELSIF statement is TRUE, all others should be FALSE"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s07b00x00p04n01i01457arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc681.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:01 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00681ent IS
END c03s04b01x00p23n01i00681ent;
ARCHITECTURE c03s04b01x00p23n01i00681arch OF c03s04b01x00p23n01i00681ent IS
type FT is file of INTEGER;
BEGIN
TESTING: PROCESS
file S1: FT open write_mode is "iofile.47";
BEGIN
WRITE(S1,3);
WRITE(S1,2);
WRITE(S1,1);
wait for 10 ns;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00681 - The output file will tested by test file s010402.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00681arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc681.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:01 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00681ent IS
END c03s04b01x00p23n01i00681ent;
ARCHITECTURE c03s04b01x00p23n01i00681arch OF c03s04b01x00p23n01i00681ent IS
type FT is file of INTEGER;
BEGIN
TESTING: PROCESS
file S1: FT open write_mode is "iofile.47";
BEGIN
WRITE(S1,3);
WRITE(S1,2);
WRITE(S1,1);
wait for 10 ns;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00681 - The output file will tested by test file s010402.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00681arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc681.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:01 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00681ent IS
END c03s04b01x00p23n01i00681ent;
ARCHITECTURE c03s04b01x00p23n01i00681arch OF c03s04b01x00p23n01i00681ent IS
type FT is file of INTEGER;
BEGIN
TESTING: PROCESS
file S1: FT open write_mode is "iofile.47";
BEGIN
WRITE(S1,3);
WRITE(S1,2);
WRITE(S1,1);
wait for 10 ns;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00681 - The output file will tested by test file s010402.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00681arch;
|
----------------------------------------------------------------------
---- ----
---- iteration_synth.vhd ----
---- ----
---- This file is part of the turbo decoder IP core project ----
---- http://www.opencores.org/projects/turbocodes/ ----
---- ----
---- Author(s): ----
---- - David Brochart([email protected]) ----
---- ----
---- All additional information is available in the README.txt ----
---- file. ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2005 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
architecture synth of iteration is
signal zout1 : ARRAY4c;
signal zout2 : ARRAY4c;
signal zout1Perm : ARRAY4c;
signal zoutInt1 : ARRAY4c;
signal zout2Int : ARRAY4c;
signal tmp0 : std_logic_vector(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto 0);
signal tmp1 : std_logic_vector(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto 0);
signal tmp2 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp3 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp4 : std_logic_vector(SIG_WIDTH * 4 - 1 downto 0);
signal tmp5 : std_logic_vector(SIG_WIDTH * 4 - 1 downto 0);
signal tmp6 : std_logic_vector(Z_WIDTH * 4 - 1 downto 0);
signal tmp7 : std_logic_vector(Z_WIDTH * 4 - 1 downto 0);
signal tmp8 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp9 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp10 : std_logic_vector(SIG_WIDTH * 8 - 1 downto 0);
signal tmp11 : std_logic_vector(SIG_WIDTH * 8 - 1 downto 0);
signal abDel1Perm : ARRAY2a;
signal abDel1PermInt: ARRAY2a;
signal aDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal bDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yIntDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wIntDel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal aDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal bDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wDel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal aDecInt : std_logic;
signal bDecInt : std_logic;
signal aDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal bDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yIntDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wIntDel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yIntDel4 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wIntDel4 : std_logic_vector(SIG_WIDTH - 1 downto 0);
begin
sova_i0 : sova port map (
clk => clk,
rst => rst,
aNoisy => a,
bNoisy => b,
yNoisy => y,
wNoisy => w,
zin => zin,
zout => zout1,
aClean => aDec,
bClean => bDec
);
zPermut_i0 : zPermut generic map (
flip => (TREL1_LEN + TREL2_LEN + 2 + delay + 1) mod 2
)
port map (
flipflop => flipflop,
z => zout1,
zPerm => zout1Perm
);
tmp0 <= zout1Perm(0) & zout1Perm(1) & zout1Perm(2) & zout1Perm(3) & abDel1Perm(0) & abDel1Perm(1);
interleaver_i0 : interleaver generic map (
delay => TREL1_LEN + TREL2_LEN + 2 + delay,
way => 0
)
port map (
clk => clk,
rst => rst,
d => tmp0,
q => tmp1
);
zoutInt1(0) <= tmp1(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 3 + SIG_WIDTH * 2);
zoutInt1(1) <= tmp1(Z_WIDTH * 3 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 2 + SIG_WIDTH * 2);
zoutInt1(2) <= tmp1(Z_WIDTH * 2 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 1 + SIG_WIDTH * 2);
zoutInt1(3) <= tmp1(Z_WIDTH * 1 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 0 + SIG_WIDTH * 2);
abDel1PermInt(0) <= tmp1(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
abDel1PermInt(1) <= tmp1(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
tmp2 <= a & b & y & w & yInt & wInt;
delayer_i0 : delayer generic map (
delay => TREL1_LEN + TREL2_LEN
)
port map (
clk => clk,
rst => rst,
d => tmp2,
q => tmp3
);
aDel1 <= tmp3(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
bDel1 <= tmp3(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
yDel1 <= tmp3(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
wDel1 <= tmp3(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
yIntDel1 <= tmp3(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wIntDel1 <= tmp3(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
abPermut_i0 : abPermut generic map (
flip => (TREL1_LEN + TREL2_LEN + 2 + delay + 1) mod 2
)
port map (
flipflop => flipflop,
a => aDel1,
b => bDel1,
abPerm => abDel1Perm
);
tmp4 <= aDel1 & bDel1 & yDel1 & wDel1;
delayer_i1 : delayer generic map (
delay => FRSIZE
)
port map (
clk => clk,
rst => rst,
d => tmp4,
q => tmp5
);
aDel2 <= tmp5(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
bDel2 <= tmp5(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
yDel2 <= tmp5(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wDel2 <= tmp5(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
sova_i1 : sova port map (
clk => clk,
rst => rst,
aNoisy => abDel1PermInt(1),
bNoisy => abDel1PermInt(0),
yNoisy => yIntDel1,
wNoisy => wIntDel1,
zin => zoutInt1,
zout => zout2,
aClean => aDecInt,
bClean => bDecInt
);
tmp6 <= zout2(0) & zout2(1) & zout2(2) & zout2(3);
deinterleaver_i0 : interleaver generic map (
delay => 2 * (TREL1_LEN + TREL2_LEN + 2) + FRSIZE + delay,
way => 1
)
port map (
clk => clk,
rst => rst,
d => tmp6,
q => tmp7
);
zout2Int(0) <= tmp7(Z_WIDTH * 4 - 1 downto Z_WIDTH * 3);
zout2Int(1) <= tmp7(Z_WIDTH * 3 - 1 downto Z_WIDTH * 2);
zout2Int(2) <= tmp7(Z_WIDTH * 2 - 1 downto Z_WIDTH * 1);
zout2Int(3) <= tmp7(Z_WIDTH * 1 - 1 downto Z_WIDTH * 0);
zPermut_i1 : zPermut generic map (
flip => (2 * (TREL1_LEN + TREL2_LEN + 2) + FRSIZE + delay) mod 2
)
port map (
flipflop => flipflop,
z => zout2Int,
zPerm => zout
);
tmp8 <= aDel2 & bDel2 & yDel2 & wDel2 & yIntDel1 & wIntDel1;
delayer_i2 : delayer generic map (
delay => TREL1_LEN + TREL2_LEN
)
port map (
clk => clk,
rst => rst,
d => tmp8,
q => tmp9
);
aDel3 <= tmp9(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
bDel3 <= tmp9(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
yDel3 <= tmp9(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
wDel3 <= tmp9(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
yIntDel3 <= tmp9(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wIntDel3 <= tmp9(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
tmp10 <= aDel3 & bDel3 & yDel3 & wDel3 & yIntDel3 & wIntDel3 & yIntDel4 & wIntDel4;
delayer_i3 : delayer generic map (
delay => FRSIZE
)
port map (
clk => clk,
rst => rst,
d => tmp10,
q => tmp11
);
aDel <= tmp11(SIG_WIDTH * 8 - 1 downto SIG_WIDTH * 7);
bDel <= tmp11(SIG_WIDTH * 7 - 1 downto SIG_WIDTH * 6);
yDel <= tmp11(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
wDel <= tmp11(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
yIntDel4 <= tmp11(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
wIntDel4 <= tmp11(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
yIntDel <= tmp11(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wIntDel <= tmp11(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
end;
|
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_brams_v6.vhd
-- Description: BlockRAM module for Virtex6 PCIe Block
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pcie_brams_v6 is
generic (
-- the number of BRAMs to use
-- supported values are:
-- 1,2,4,8,18
NUM_BRAMS : integer := 0;
-- BRAM read address latency
--
-- value meaning
-- ====================================================
-- 0 BRAM read address port sample
-- 1 BRAM read address port sample and a pipeline stage on the address port
RAM_RADDR_LATENCY : integer := 1;
-- BRAM read data latency
--
-- value meaning
-- ====================================================
-- 1 no BRAM OREG
-- 2 use BRAM OREG
-- 3 use BRAM OREG and a pipeline stage on the data port
RAM_RDATA_LATENCY : integer := 1;
-- BRAM write latency
-- The BRAM write port is synchronous
--
-- value meaning
-- ====================================================
-- 0 BRAM write port sample
-- 1 BRAM write port sample plus pipeline stage
RAM_WRITE_LATENCY : integer := 1
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
wen : in std_logic;
waddr : in std_logic_vector(12 downto 0);
wdata : in std_logic_vector(71 downto 0);
ren : in std_logic;
rce : in std_logic;
raddr : in std_logic_vector(12 downto 0);
rdata : out std_logic_vector(71 downto 0)
);
end pcie_brams_v6;
architecture v6_pcie of pcie_brams_v6 is
component pcie_bram_v6 is
generic (
DOB_REG : integer;
WIDTH : integer
);
port (
user_clk_i : in std_logic;
reset_i : in std_logic;
wen_i : in std_logic;
waddr_i : in std_logic_vector(12 downto 0);
wdata_i : in std_logic_vector(WIDTH - 1 downto 0);
ren_i : in std_logic;
rce_i : in std_logic;
raddr_i : in std_logic_vector(12 downto 0);
rdata_o : out std_logic_vector(WIDTH - 1 downto 0)
);
end component;
FUNCTION to_integer (
in_val : IN boolean) RETURN integer IS
BEGIN
IF (in_val) THEN
RETURN(1);
ELSE
RETURN(0);
END IF;
END to_integer;
-- turn on the bram output register
constant DOB_REG : integer := to_integer(RAM_RDATA_LATENCY > 1);
-- calculate the data width of the individual brams
function width (
constant NUM_BRAM : integer)
return integer is
variable WIDTH_BRAM : integer := 1;
begin -- width
if (NUM_BRAM = 1) then
WIDTH_BRAM := 72;
elsif (NUM_BRAM = 2) then
WIDTH_BRAM := 36;
elsif (NUM_BRAM = 4) then
WIDTH_BRAM := 18;
elsif (NUM_BRAM = 8) then
WIDTH_BRAM := 9;
else
WIDTH_BRAM := 4;
end if;
return WIDTH_BRAM;
end width;
constant BRAM_WIDTH : integer := width(NUM_BRAMS);
constant TCQ : integer := 1;
signal wen_int : std_logic;
signal waddr_int : std_logic_vector(12 downto 0);
signal wdata_int : std_logic_vector(71 downto 0);
signal wen_dly : std_logic := '0';
signal waddr_dly : std_logic_vector(12 downto 0) := (others => '0');
signal wdata_dly : std_logic_vector(71 downto 0) := (others => '0');
-- if (RAM_WRITE_LATENCY == 1)
-- model the delays for ram read latency
signal ren_int : std_logic;
signal raddr_int : std_logic_vector(12 downto 0);
signal rdata_int : std_logic_vector(71 downto 0);
signal ren_dly : std_logic;
signal raddr_dly : std_logic_vector(12 downto 0);
signal rdata_dly : std_logic_vector(71 downto 0);
begin
--synthesis translate_off
process
begin
-- $display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d", now, to_stdlogic(NUM_BRAMS), to_stdlogicvector(DOB_REG, 13), ("00000000000000000000000000000000000000000000000000000000000000000" & WIDTH), to_stdlogic(RAM_WRITE_LATENCY), to_stdlogic(RAM_RADDR_LATENCY), to_stdlogicvector(RAM_RDATA_LATENCY, 13));
case NUM_BRAMS is
when 1 | 2 | 4 | 8 | 18 =>
when others =>
-- $display("[%t] %m Error NUM_BRAMS %0d not supported", now, to_stdlogic(NUM_BRAMS));
-- $finish();
end case; -- case(NUM_BRAMS)
case RAM_RADDR_LATENCY is
when 0 | 1 =>
when others =>
-- $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", now, to_stdlogic(RAM_RADDR_LATENCY));
-- $finish();
end case; -- case (RAM_RADDR_LATENCY)
case RAM_RDATA_LATENCY is
when 1 | 2 | 3 =>
when others =>
-- $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", now, to_stdlogic(RAM_RDATA_LATENCY));
-- $finish();
end case; -- case (RAM_RDATA_LATENCY)
case RAM_WRITE_LATENCY is
when 0 | 1 =>
when others =>
-- $display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", now, to_stdlogic(RAM_WRITE_LATENCY));
-- $finish();
end case; -- case(RAM_WRITE_LATENCY)
wait;
end process;
--synthesis translate_on
-- model the delays for ram write latency
wr_lat_2 : if (RAM_WRITE_LATENCY = 1) generate
process (user_clk_i)
begin
if (user_clk_i'event and user_clk_i = '1') then
if (reset_i = '1') then
wen_dly <= '0' after (TCQ)*1 ps;
waddr_dly <= "0000000000000" after (TCQ)*1 ps;
wdata_dly <= "000000000000000000000000000000000000000000000000000000000000000000000000" after (TCQ)*1 ps;
else
wen_dly <= wen after (TCQ)*1 ps;
waddr_dly <= waddr after (TCQ)*1 ps;
wdata_dly <= wdata after (TCQ)*1 ps;
end if;
end if;
end process;
wen_int <= wen_dly;
waddr_int <= waddr_dly;
wdata_int <= wdata_dly;
end generate;
wr_lat_1 : if (RAM_WRITE_LATENCY = 0) generate
wen_int <= wen;
waddr_int <= waddr;
wdata_int <= wdata;
end generate;
raddr_lat_2 : if (RAM_RADDR_LATENCY = 1) generate
process (user_clk_i)
begin
if (user_clk_i'event and user_clk_i = '1') then
if (reset_i = '1') then
ren_dly <= '0' after (TCQ)*1 ps;
raddr_dly <= "0000000000000" after (TCQ)*1 ps;
else
ren_dly <= ren after (TCQ)*1 ps;
raddr_dly <= raddr after (TCQ)*1 ps;
end if;
end if;
end process;
ren_int <= ren_dly;
raddr_int <= raddr_dly;
end generate; -- block: rd_lat_addr_2
raddr_lat_1 : if (not(RAM_RADDR_LATENCY = 1)) generate
ren_int <= ren;
raddr_int <= raddr;
end generate;
rdata_lat_3 : if (RAM_RDATA_LATENCY = 3) generate
process (user_clk_i)
begin
if (user_clk_i'event and user_clk_i = '1') then
if (reset_i = '1') then
rdata_dly <= "000000000000000000000000000000000000000000000000000000000000000000000000" after (TCQ)*1 ps;
else
rdata_dly <= rdata_int after (TCQ)*1 ps;
end if;
end if;
end process;
rdata <= rdata_dly;
end generate; -- block: rd_lat_data_3
rdata_lat_1_2 : if (not(RAM_RDATA_LATENCY = 3)) generate
rdata <= rdata_int after (TCQ)*1 ps;
end generate;
-- instantiate the brams
brams : for i in 0 to NUM_BRAMS - 1 generate
ram : pcie_bram_v6
generic map (
DOB_REG => DOB_REG,
WIDTH => BRAM_WIDTH
)
port map (
user_clk_i => user_clk_i,
reset_i => reset_i,
wen_i => wen_int,
waddr_i => waddr_int,
wdata_i => wdata_int((((i + 1) * BRAM_WIDTH) - 1) downto (i * BRAM_WIDTH)),
ren_i => ren_int,
raddr_i => raddr_int,
rdata_o => rdata_int((((i + 1) * BRAM_WIDTH) - 1) downto (i * BRAM_WIDTH)),
rce_i => rce
);
end generate;
-- pcie_brams_v6
end v6_pcie;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_unit is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC;
SHIFT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end shift_unit;
architecture Combinational of shift_unit is
signal shift_left, shift_right, shift_result : std_logic_vector (23 downto 0) := (OTHERS => '0');
signal sreg : std_logic_vector (3 downto 0) := (OTHERS => '0');
signal a : std_logic_vector (23 downto 0);
begin
a <= X"00" & RA;
shift_left <= to_stdlogicvector(to_bitvector(a) sll conv_integer(SHIFT));
shift_right <= to_stdlogicvector(to_bitvector(a) srl conv_integer(SHIFT));
shift_result <= shift_left when OP='0' else shift_right;
--SREG(3) <= RESULT(7); -- Negative with signed logic
sreg(2) <= '1' when shift_result(15 downto 0) = x"00000000" else '0'; -- Zero
--SREG(1) <= RESULT(8) xor RESULT(7); -- Overflow with signed logic
sreg(0) <= shift_result(16) or shift_result(17) or shift_result(18) or shift_result(19) or shift_result(20) or shift_result(21) or shift_result(22) or shift_result(23); -- Carry
SHIFT_OUT <= shift_result (15 downto 0);
SREG_OUT <= sreg;
end Combinational;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_unit is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC;
SHIFT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end shift_unit;
architecture Combinational of shift_unit is
signal shift_left, shift_right, shift_result : std_logic_vector (23 downto 0) := (OTHERS => '0');
signal sreg : std_logic_vector (3 downto 0) := (OTHERS => '0');
signal a : std_logic_vector (23 downto 0);
begin
a <= X"00" & RA;
shift_left <= to_stdlogicvector(to_bitvector(a) sll conv_integer(SHIFT));
shift_right <= to_stdlogicvector(to_bitvector(a) srl conv_integer(SHIFT));
shift_result <= shift_left when OP='0' else shift_right;
--SREG(3) <= RESULT(7); -- Negative with signed logic
sreg(2) <= '1' when shift_result(15 downto 0) = x"00000000" else '0'; -- Zero
--SREG(1) <= RESULT(8) xor RESULT(7); -- Overflow with signed logic
sreg(0) <= shift_result(16) or shift_result(17) or shift_result(18) or shift_result(19) or shift_result(20) or shift_result(21) or shift_result(22) or shift_result(23); -- Carry
SHIFT_OUT <= shift_result (15 downto 0);
SREG_OUT <= sreg;
end Combinational;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_unit is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC;
SHIFT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end shift_unit;
architecture Combinational of shift_unit is
signal shift_left, shift_right, shift_result : std_logic_vector (23 downto 0) := (OTHERS => '0');
signal sreg : std_logic_vector (3 downto 0) := (OTHERS => '0');
signal a : std_logic_vector (23 downto 0);
begin
a <= X"00" & RA;
shift_left <= to_stdlogicvector(to_bitvector(a) sll conv_integer(SHIFT));
shift_right <= to_stdlogicvector(to_bitvector(a) srl conv_integer(SHIFT));
shift_result <= shift_left when OP='0' else shift_right;
--SREG(3) <= RESULT(7); -- Negative with signed logic
sreg(2) <= '1' when shift_result(15 downto 0) = x"00000000" else '0'; -- Zero
--SREG(1) <= RESULT(8) xor RESULT(7); -- Overflow with signed logic
sreg(0) <= shift_result(16) or shift_result(17) or shift_result(18) or shift_result(19) or shift_result(20) or shift_result(21) or shift_result(22) or shift_result(23); -- Carry
SHIFT_OUT <= shift_result (15 downto 0);
SREG_OUT <= sreg;
end Combinational;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_unit is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC;
SHIFT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end shift_unit;
architecture Combinational of shift_unit is
signal shift_left, shift_right, shift_result : std_logic_vector (23 downto 0) := (OTHERS => '0');
signal sreg : std_logic_vector (3 downto 0) := (OTHERS => '0');
signal a : std_logic_vector (23 downto 0);
begin
a <= X"00" & RA;
shift_left <= to_stdlogicvector(to_bitvector(a) sll conv_integer(SHIFT));
shift_right <= to_stdlogicvector(to_bitvector(a) srl conv_integer(SHIFT));
shift_result <= shift_left when OP='0' else shift_right;
--SREG(3) <= RESULT(7); -- Negative with signed logic
sreg(2) <= '1' when shift_result(15 downto 0) = x"00000000" else '0'; -- Zero
--SREG(1) <= RESULT(8) xor RESULT(7); -- Overflow with signed logic
sreg(0) <= shift_result(16) or shift_result(17) or shift_result(18) or shift_result(19) or shift_result(20) or shift_result(21) or shift_result(22) or shift_result(23); -- Carry
SHIFT_OUT <= shift_result (15 downto 0);
SREG_OUT <= sreg;
end Combinational;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_unit is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC;
SHIFT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end shift_unit;
architecture Combinational of shift_unit is
signal shift_left, shift_right, shift_result : std_logic_vector (23 downto 0) := (OTHERS => '0');
signal sreg : std_logic_vector (3 downto 0) := (OTHERS => '0');
signal a : std_logic_vector (23 downto 0);
begin
a <= X"00" & RA;
shift_left <= to_stdlogicvector(to_bitvector(a) sll conv_integer(SHIFT));
shift_right <= to_stdlogicvector(to_bitvector(a) srl conv_integer(SHIFT));
shift_result <= shift_left when OP='0' else shift_right;
--SREG(3) <= RESULT(7); -- Negative with signed logic
sreg(2) <= '1' when shift_result(15 downto 0) = x"00000000" else '0'; -- Zero
--SREG(1) <= RESULT(8) xor RESULT(7); -- Overflow with signed logic
sreg(0) <= shift_result(16) or shift_result(17) or shift_result(18) or shift_result(19) or shift_result(20) or shift_result(21) or shift_result(22) or shift_result(23); -- Carry
SHIFT_OUT <= shift_result (15 downto 0);
SREG_OUT <= sreg;
end Combinational;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_unit is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC;
SHIFT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end shift_unit;
architecture Combinational of shift_unit is
signal shift_left, shift_right, shift_result : std_logic_vector (23 downto 0) := (OTHERS => '0');
signal sreg : std_logic_vector (3 downto 0) := (OTHERS => '0');
signal a : std_logic_vector (23 downto 0);
begin
a <= X"00" & RA;
shift_left <= to_stdlogicvector(to_bitvector(a) sll conv_integer(SHIFT));
shift_right <= to_stdlogicvector(to_bitvector(a) srl conv_integer(SHIFT));
shift_result <= shift_left when OP='0' else shift_right;
--SREG(3) <= RESULT(7); -- Negative with signed logic
sreg(2) <= '1' when shift_result(15 downto 0) = x"00000000" else '0'; -- Zero
--SREG(1) <= RESULT(8) xor RESULT(7); -- Overflow with signed logic
sreg(0) <= shift_result(16) or shift_result(17) or shift_result(18) or shift_result(19) or shift_result(20) or shift_result(21) or shift_result(22) or shift_result(23); -- Carry
SHIFT_OUT <= shift_result (15 downto 0);
SREG_OUT <= sreg;
end Combinational;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_unit is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC;
SHIFT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end shift_unit;
architecture Combinational of shift_unit is
signal shift_left, shift_right, shift_result : std_logic_vector (23 downto 0) := (OTHERS => '0');
signal sreg : std_logic_vector (3 downto 0) := (OTHERS => '0');
signal a : std_logic_vector (23 downto 0);
begin
a <= X"00" & RA;
shift_left <= to_stdlogicvector(to_bitvector(a) sll conv_integer(SHIFT));
shift_right <= to_stdlogicvector(to_bitvector(a) srl conv_integer(SHIFT));
shift_result <= shift_left when OP='0' else shift_right;
--SREG(3) <= RESULT(7); -- Negative with signed logic
sreg(2) <= '1' when shift_result(15 downto 0) = x"00000000" else '0'; -- Zero
--SREG(1) <= RESULT(8) xor RESULT(7); -- Overflow with signed logic
sreg(0) <= shift_result(16) or shift_result(17) or shift_result(18) or shift_result(19) or shift_result(20) or shift_result(21) or shift_result(22) or shift_result(23); -- Carry
SHIFT_OUT <= shift_result (15 downto 0);
SREG_OUT <= sreg;
end Combinational;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:57:23 03/28/2016
-- Design Name:
-- Module Name: shift_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_unit is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC;
SHIFT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end shift_unit;
architecture Combinational of shift_unit is
signal shift_left, shift_right, shift_result : std_logic_vector (23 downto 0) := (OTHERS => '0');
signal sreg : std_logic_vector (3 downto 0) := (OTHERS => '0');
signal a : std_logic_vector (23 downto 0);
begin
a <= X"00" & RA;
shift_left <= to_stdlogicvector(to_bitvector(a) sll conv_integer(SHIFT));
shift_right <= to_stdlogicvector(to_bitvector(a) srl conv_integer(SHIFT));
shift_result <= shift_left when OP='0' else shift_right;
--SREG(3) <= RESULT(7); -- Negative with signed logic
sreg(2) <= '1' when shift_result(15 downto 0) = x"00000000" else '0'; -- Zero
--SREG(1) <= RESULT(8) xor RESULT(7); -- Overflow with signed logic
sreg(0) <= shift_result(16) or shift_result(17) or shift_result(18) or shift_result(19) or shift_result(20) or shift_result(21) or shift_result(22) or shift_result(23); -- Carry
SHIFT_OUT <= shift_result (15 downto 0);
SREG_OUT <= sreg;
end Combinational;
|
package pkg is
function identifier return integer;
-- procedure identifier;
-- alias identifier_alias_fun is identifier[return integer];
alias identifier_alias_proc is identifier[];
end package;
|
package pkg is
function identifier return integer;
-- procedure identifier;
-- alias identifier_alias_fun is identifier[return integer];
alias identifier_alias_proc is identifier[];
end package;
|
package pkg is
function identifier return integer;
-- procedure identifier;
-- alias identifier_alias_fun is identifier[return integer];
alias identifier_alias_proc is identifier[];
end package;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.net.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romdepth : integer := 25; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
-- clocks
signal OSC_50_BANK2 : std_logic := '0';
signal OSC_50_BANK3 : std_logic := '0';
signal OSC_50_BANK4 : std_logic := '0';
signal OSC_50_BANK5 : std_logic := '0';
signal OSC_50_BANK6 : std_logic := '0';
signal OSC_50_BANK7 : std_logic := '0';
signal PLL_CLKIN_p : std_logic := '0';
signal SMA_CLKIN_p : std_logic := '0';
--signal SMA_GXBCLK_p : std_logic;
signal GCLKIN : std_logic := '0';
-- signal GCLKOUT_FPGA : std_logic := '0';
-- signal SMA_CLKOUT_p : std_logic := '0';
signal clk_125 : std_logic := '0';
-- cpu reset
signal CPU_RESET_n : std_ulogic := '0';
-- max i/o
-- signal MAX_CONF_D : std_logic_vector(3 downto 0);
-- signal MAX_I2C_SCLK : std_logic;
-- signal MAX_I2C_SDAT : std_logic;
-- LEDs
signal LED : std_logic_vector(7 downto 0);
-- buttons
signal BUTTON : std_logic_vector(3 downto 0);
-- switches
signal SW : std_logic_vector(3 downto 0);
-- slide switches
signal SLIDE_SW : std_logic_vector(3 downto 0);
-- temperature
-- signal TEMP_SMCLK : std_logic;
-- signal TEMP_SMDAT : std_logic;
-- signal TEMP_INT_n : std_logic;
-- current
signal CSENSE_ADC_FO : std_logic;
signal CSENSE_SCK : std_logic;
signal CSENSE_SDI : std_logic;
signal CSENSE_SDO : std_logic;
signal CSENSE_CS_n : std_logic_vector(1 downto 0);
-- fan
signal FAN_CTRL : std_logic;
-- eeprom
signal EEP_SCL : std_logic;
signal EEP_SDA : std_logic;
-- sdcard
-- signal SD_CLK : std_logic;
-- signal SD_CMD : std_logic;
-- signal SD_DAT : std_logic_vector(3 downto 0);
-- signal SD_WP_n : std_logic;
-- Ethernet interfaces
signal ETH_INT_n : std_logic_vector(3 downto 0);
signal ETH_MDC : std_logic_vector(3 downto 0);
signal ETH_MDIO : std_logic_vector(3 downto 0);
signal ETH_RST_n : std_ulogic;
signal ETH_RX_p : std_logic_vector(3 downto 0);
signal ETH_TX_p : std_logic_vector(3 downto 0);
-- PCIe interfaces
--signal PCIE_PREST_n : std_ulogic;
--signal PCIE_REFCLK_p : std_ulogic;
--signal PCIE_RX_p : std_logic_vector(7 downto 0);
--signal PCIE_SMBCLK : std_logic;
--signal PCIE_SMBDAT : std_logic;
--signal PCIE_TX_p : std_logic_vector(7 downto 0);
--signal PCIE_WAKE_n : std_logic;
-- Flash and SRAM, shared signals
signal FSM_A : std_logic_vector(25 downto 1);
signal FSM_D : std_logic_vector(15 downto 0);
-- Flash control
signal FLASH_ADV_n : std_ulogic;
signal FLASH_CE_n : std_ulogic;
signal FLASH_CLK : std_ulogic;
signal FLASH_OE_n : std_ulogic;
signal FLASH_RESET_n : std_ulogic;
signal FLASH_RYBY_n : std_ulogic;
signal FLASH_WE_n : std_ulogic;
-- SSRAM control
signal SSRAM_ADV : std_ulogic;
signal SSRAM_BWA_n : std_ulogic;
signal SSRAM_BWB_n : std_ulogic;
signal SSRAM_CE_n : std_ulogic;
signal SSRAM_CKE_n : std_ulogic;
signal SSRAM_CLK : std_ulogic;
signal SSRAM_OE_n : std_ulogic;
signal SSRAM_WE_n : std_ulogic;
-- USB OTG
--signal OTG_A : std_logic_vector(17 downto 1);
--signal OTG_CS_n : std_ulogic;
--signal OTG_D : std_logic_vector(31 downto 0);
--signal OTG_DC_DACK : std_ulogic;
--signal OTG_DC_DREQ : std_ulogic;
--signal OTG_DC_IRQ : std_ulogic;
--signal OTG_HC_DACK : std_ulogic;
--signal OTG_HC_DREQ : std_ulogic;
--signal OTG_HC_IRQ : std_ulogic;
--signal OTG_OE_n : std_ulogic;
--signal OTG_RESET_n : std_ulogic;
--signal OTG_WE_n : std_ulogic;
-- SATA
--signal SATA_REFCLK_p : std_logic;
--signal SATA_HOST_RX_p : std_logic_vector(1 downto 0);
--signal SATA_HOST_TX_p : std_logic_vector(1 downto 0);
--signal SATA_DEVICE_RX_p : std_logic_vector(1 downto 0);
--signal SATA_DEVICE_TX_p : std_logic_vector(1 downto 0);
-- DDR2 SODIMM
signal M1_DDR2_addr : std_logic_vector(15 downto 0);
signal M1_DDR2_ba : std_logic_vector(2 downto 0);
signal M1_DDR2_cas_n : std_logic;
signal M1_DDR2_cke : std_logic_vector(1 downto 0);
signal M1_DDR2_clk : std_logic_vector(1 downto 0);
signal M1_DDR2_clk_n : std_logic_vector(1 downto 0);
signal M1_DDR2_cs_n : std_logic_vector(1 downto 0);
signal M1_DDR2_dm : std_logic_vector(7 downto 0);
signal M1_DDR2_dq : std_logic_vector(63 downto 0);
signal M1_DDR2_dqs : std_logic_vector(7 downto 0);
signal M1_DDR2_dqsn : std_logic_vector(7 downto 0);
signal M1_DDR2_odt : std_logic_vector(1 downto 0);
signal M1_DDR2_ras_n : std_logic;
-- signal M1_DDR2_SA : std_logic_vector(1 downto 0);
-- signal M1_DDR2_SCL : std_logic;
-- signal M1_DDR2_SDA : std_logic;
signal M1_DDR2_we_n : std_logic;
signal M1_DDR2_oct_rdn : std_logic;
signal M1_DDR2_oct_rup : std_logic;
-- DDR2 SODIMM
--signal M2_DDR2_addr : std_logic_vector(15 downto 0);
--signal M2_DDR2_ba : std_logic_vector(2 downto 0);
--signal M2_DDR2_cas_n : std_logic;
--signal M2_DDR2_cke : std_logic_vector(1 downto 0);
--signal M2_DDR2_clk : std_logic_vector(1 downto 0);
--signal M2_DDR2_clk_n : std_logic_vector(1 downto 0);
--signal M2_DDR2_cs_n : std_logic_vector(1 downto 0);
--signal M2_DDR2_dm : std_logic_vector(7 downto 0);
--signal M2_DDR2_dq : std_logic_vector(63 downto 0);
--signal M2_DDR2_dqs : std_logic_vector(7 downto 0);
--signal M2_DDR2_dqsn : std_logic_vector(7 downto 0);
--signal M2_DDR2_odt : std_logic_vector(1 downto 0);
--signal M2_DDR2_ras_n : std_logic;
--signal M2_DDR2_SA : std_logic_vector(1 downto 0);
--signal M2_DDR2_SCL : std_logic;
--signal M2_DDR2_SDA : std_logic;
--signal M2_DDR2_we_n : std_logic;
-- GPIO
signal GPIO0_D : std_logic_vector(35 downto 0);
-- signal GPIO1_D : std_logic_vector(35 downto 0);
-- Ext I/O
signal EXT_IO : std_logic;
-- HSMC A
-- signal HSMA_CLKIN_n1 : std_logic;
-- signal HSMA_CLKIN_n2 : std_logic;
-- signal HSMA_CLKIN_p1 : std_logic;
-- signal HSMA_CLKIN_p2 : std_logic;
-- signal HSMA_CLKIN0 : std_logic;
signal HSMA_CLKOUT_n2 : std_logic;
signal HSMA_CLKOUT_p2 : std_logic;
-- signal HSMA_D : std_logic_vector(3 downto 0);
-- HSMA_GXB_RX_p : std_logic_vector(3 downto 0);
-- HSMA_GXB_TX_p : std_logic_vector(3 downto 0);
-- signal HSMA_OUT_n1 : std_logic;
-- signal HSMA_OUT_p1 : std_logic;
-- signal HSMA_OUT0 : std_logic;
-- HSMA_REFCLK_p : in std_logic;
-- signal HSMA_RX_n : std_logic_vector(16 downto 0);
-- signal HSMA_RX_p : std_logic_vector(16 downto 0);
-- signal HSMA_TX_n : std_logic_vector(16 downto 0);
-- signal HSMA_TX_p : std_logic_vector(16 downto 0);
-- HSMC_B
-- signal HSMB_CLKIN_n1 : std_logic;
-- signal HSMB_CLKIN_n2 : std_logic;
-- signal HSMB_CLKIN_p1 : std_logic;
-- signal HSMB_CLKIN_p2 : std_logic;
-- signal HSMB_CLKIN0 : std_logic;
-- signal HSMB_CLKOUT_n2 : std_logic;
-- signal HSMB_CLKOUT_p2 : std_logic;
-- signal HSMB_D : std_logic_vector(3 downto 0);
-- signal HSMB_GXB_RX_p : in std_logic_vector(3 downto 0);
-- signal HSMB_GXB_TX_p : out std_logic_vector(3 downto 0);
-- signal HSMB_OUT_n1 : std_logic;
-- signal HSMB_OUT_p1 : std_logic;
-- signal HSMB_OUT0 : std_logic;
-- signal HSMB_REFCLK_p : in std_logic;
-- signal HSMB_RX_n : std_logic_vector(16 downto 0);
-- signal HSMB_RX_p : std_logic_vector(16 downto 0);
-- signal HSMB_TX_n : std_logic_vector(16 downto 0);
-- signal HSMB_TX_p : std_logic_vector(16 downto 0);
-- HSMC i2c
-- signal HSMC_SCL : std_logic;
-- signal HSMC_SDA : std_logic;
-- Display
-- signal SEG0_D : std_logic_vector(6 downto 0);
-- signal SEG1_D : std_logic_vector(6 downto 0);
-- signal SEG0_DP : std_ulogic;
-- signal SEG1_DP : std_ulogic;
-- UART
signal UART_CTS : std_ulogic;
signal UART_RTS : std_ulogic;
signal UART_RXD : std_logic;
signal UART_TXD : std_logic;
signal dsuen, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal sgmii_rstn : std_logic;
signal dummy_ethi : eth_in_type;
signal dummy_etho : eth_out_type;
signal sgmii0_rxd : std_logic_vector(7 downto 0);
signal sgmii0_rx_dv : std_logic;
signal sgmii0_rx_er : std_logic;
signal sgmii0_rx_col : std_logic;
signal sgmii0_rx_crs : std_logic;
signal sgmii0_rx_clk : std_logic;
signal phy0_rxd : std_logic_vector(7 downto 0);
signal phy0_rx_dv : std_logic;
signal phy0_rx_er : std_logic;
signal phy0_rx_col : std_logic;
signal phy0_rx_crs : std_logic;
signal phy0_rx_clk : std_logic;
signal sgmii0_txd : std_logic_vector(7 downto 0);
signal sgmii0_tx_en : std_logic;
signal sgmii0_tx_er : std_logic;
signal sgmii0_gtx_clk : std_logic;
signal phy0_txd : std_logic_vector(7 downto 0);
signal phy0_tx_en : std_logic;
signal phy0_tx_er : std_logic;
signal phy0_gtx_clk : std_logic;
signal sgmii1_rxd : std_logic_vector(7 downto 0);
signal sgmii1_rx_dv : std_logic;
signal sgmii1_rx_er : std_logic;
signal sgmii1_rx_col : std_logic;
signal sgmii1_rx_crs : std_logic;
signal sgmii1_rx_clk : std_logic;
signal phy1_rxd : std_logic_vector(7 downto 0);
signal phy1_rx_dv : std_logic;
signal phy1_rx_er : std_logic;
signal phy1_rx_col : std_logic;
signal phy1_rx_crs : std_logic;
signal phy1_rx_clk : std_logic;
signal sgmii1_txd : std_logic_vector(7 downto 0);
signal sgmii1_tx_en : std_logic;
signal sgmii1_tx_er : std_logic;
signal sgmii1_gtx_clk : std_logic;
signal phy1_txd : std_logic_vector(7 downto 0);
signal phy1_tx_en : std_logic;
signal phy1_tx_er : std_logic;
signal phy1_gtx_clk : std_logic;
signal rst_125 : std_logic;
constant lresp : boolean := false;
constant slips : integer := 11;
signal ETH_RX_p_d : std_logic;
begin
-- clock and reset
-- 50 MHz clocks
OSC_50_BANK2 <= not OSC_50_BANK2 after 10 ns;
OSC_50_BANK3 <= not OSC_50_BANK3 after 10 ns;
OSC_50_BANK4 <= not OSC_50_BANK4 after 10 ns;
OSC_50_BANK5 <= not OSC_50_BANK5 after 10 ns;
OSC_50_BANK6 <= not OSC_50_BANK6 after 10 ns;
OSC_50_BANK7 <= not OSC_50_BANK7 after 10 ns;
-- 100 MHz
PLL_CLKIN_p <= not PLL_CLKIN_p after 5 ns;
SMA_CLKIN_p <= not SMA_CLKIN_p after 10 ns;
GCLKIN <= not GCLKIN after 10 ns;
clk_125 <= not clk_125 after 4 ns;
CPU_RESET_n <= '0', '1' after 200 ns;
sgmii_rstn <= '0', '1' after 1000 ns;
-- various interfaces
-- MAX_CONF_D <= (others => 'H');
-- MAX_I2C_SDAT <= 'H';
BUTTON <= "HHHH";
SW <= (others => 'H');
SLIDE_SW <= (others => 'L');
-- TEMP_SMDAT <= 'H';
-- TEMP_INT_n <= 'H';
CSENSE_SCK <= 'H';
CSENSE_SDO <= 'H';
EEP_SDA <= 'H';
-- SD_CMD <= 'H';
-- SD_DAT <= (others => 'H');
-- SD_WP_n <= 'H';
GPIO0_D <= (others => 'H');
-- GPIO1_D <= (others => 'H');
EXT_IO <= 'H';
LED(0) <= 'H';
-- HSMC_SDA <= 'H';
UART_RTS <= '1';
UART_RXD <= 'H';
-- LEON3 SoC
d3 : entity work.leon3mp
generic map (
fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
OSC_50_BANK2, OSC_50_BANK3, OSC_50_BANK4, OSC_50_BANK5, OSC_50_BANK6,
OSC_50_BANK7, PLL_CLKIN_p, SMA_CLKIN_p,
-- SMA_GXBCLK_p
GCLKIN,
-- GCLKOUT_FPGA, SMA_CLKOUT_p,
-- cpu reset
CPU_RESET_n,
-- max i/o
-- MAX_CONF_D, MAX_I2C_SCLK, MAX_I2C_SDAT,
-- LEDs
LED,
-- buttons
BUTTON,
-- switches
SW,
-- slide switches
SLIDE_SW,
-- temperature
-- TEMP_SMCLK, TEMP_SMDAT, TEMP_INT_n,
-- current
CSENSE_ADC_FO, CSENSE_SCK, CSENSE_SDI, CSENSE_SDO, CSENSE_CS_n,
-- fan
FAN_CTRL,
-- eeprom
EEP_SCL, EEP_SDA,
-- sdcard
-- SD_CLK, SD_CMD, SD_DAT, SD_WP_n,
-- Ethernet interfaces
ETH_INT_n, ETH_MDC, ETH_MDIO, ETH_RST_n, ETH_RX_p, ETH_TX_p,
-- PCIe interfaces
-- PCIE_PREST_n, PCIE_REFCLK_p, PCIE_RX_p, PCIE_SMBCLK,
-- PCIE_SMBDAT, PCIE_TX_p PCIE_WAKE_n
-- Flash and SRAM, shared signals
FSM_A, FSM_D,
-- Flash control
FLASH_ADV_n, FLASH_CE_n, FLASH_CLK, FLASH_OE_n,
FLASH_RESET_n, FLASH_RYBY_n, FLASH_WE_n,
-- SSRAM control
SSRAM_ADV, SSRAM_BWA_n, SSRAM_BWB_n, SSRAM_CE_n,
SSRAM_CKE_n, SSRAM_CLK, SSRAM_OE_n, SSRAM_WE_n,
-- USB OTG
-- OTG_A, OTG_CS_n, OTG_D, OTG_DC_DACK, OTG_DC_DRE, OTG_DC_IRQ,
-- OTG_HC_DACK, OTG_HC_DREQ, OTG_HC_IRQ, OTG_OE_n, OTG_RESET_n,
-- OTG_WE_n,
-- SATA
-- SATA_REFCLK_p, SATA_HOST_RX_p, SATA_HOST_TX_p, SATA_DEVICE_RX_p, SATA_DEVICE_TX_p,
-- DDR2 SODIMM
M1_DDR2_addr, M1_DDR2_ba, M1_DDR2_cas_n, M1_DDR2_cke, M1_DDR2_clk, M1_DDR2_clk_n,
M1_DDR2_cs_n, M1_DDR2_dm, M1_DDR2_dq, M1_DDR2_dqs, M1_DDR2_dqsn, M1_DDR2_odt,
M1_DDR2_ras_n,
-- M1_DDR2_SA, M1_DDR2_SCL, M1_DDR2_SDA,
M1_DDR2_we_n,
M1_DDR2_oct_rdn, M1_DDR2_oct_rup,
-- DDR2 SODIMM
-- M2_DDR2_addr, M2_DDR2_ba, M2_DDR2_cas_n, M2_DDR2_cke, M2_DDR2_clk, M2_DDR2_clk_n
-- M2_DDR2_cs_n, M2_DDR2_dm, M2_DDR2_dq, M2_DDR2_dqs, M2_DDR2_dqsn, M2_DDR2_odt,
-- M2_DDR2_ras_n, M2_DDR2_SA, M2_DDR2_SCL, M2_DDR2_SDA M2_DDR2_we_n
-- GPIO
GPIO0_D,
-- GPIO1_D,
-- Ext I/O
-- EXT_IO,
-- HSMC A
-- HSMA_CLKIN_n1, HSMA_CLKIN_n2, HSMA_CLKIN_p1, HSMA_CLKIN_p2, HSMA_CLKIN0,
HSMA_CLKOUT_n2, HSMA_CLKOUT_p2,
-- HSMA_D,
-- HSMA_GXB_RX_p, HSMA_GXB_TX_p,
-- HSMA_OUT_n1, HSMA_OUT_p1, HSMA_OUT0,
-- HSMA_REFCLK_p,
-- HSMA_RX_n, HSMA_RX_p, HSMA_TX_n, HSMA_TX_p,
-- HSMC_B
-- HSMB_CLKIN_n1, HSMB_CLKIN_n2, HSMB_CLKIN_p1, HSMB_CLKIN_p2, HSMB_CLKIN0,
-- HSMB_CLKOUT_n2, HSMB_CLKOUT_p2, HSMB_D,
-- HSMB_GXB_RX_p, HSMB_GXB_TX_p,
-- HSMB_OUT_n1, HSMB_OUT_p1, HSMB_OUT0,
-- HSMB_REFCLK_p,
-- HSMB_RX_n, HSMB_RX_p, HSMB_TX_n, HSMB_TX_p,
-- HSMC i2c
-- HSMC_SCL, HSMC_SDA,
-- Display
-- SEG0_D, SEG1_D, SEG0_DP, SEG1_DP,
-- UART
UART_CTS, UART_RTS, UART_RXD, UART_TXD
);
ethsim0 : if CFG_GRETH /= 0 generate
rst_125 <= not CPU_RESET_n;
-- delaying rx line
ETH_RX_p(0) <= transport ETH_RX_p_d after 0.8 ns * slips;
-- connecting PHY through SGMII to MAC
p0: phy
generic map(
address => 0
)
port map(
rstn => CPU_RESET_n,
mdio => ETH_MDIO(0),
tx_clk => open,
rx_clk => open,
rxd => phy0_rxd,
rx_dv => phy0_rx_dv,
rx_er => phy0_rx_er,
rx_col => phy0_rx_col,
rx_crs => phy0_rx_crs,
txd => phy0_txd,
tx_en => phy0_tx_en,
tx_er => phy0_tx_er,
mdc => ETH_MDC(0),
gtx_clk => phy0_gtx_clk
);
phy0_txd <= sgmii0_rxd;
phy0_tx_en <= sgmii0_rx_dv;
phy0_tx_er <= sgmii0_rx_er;
phy0_gtx_clk <= sgmii0_gtx_clk;
sgmii0_txd <= phy0_rxd;
sgmii0_tx_en <= phy0_rx_dv;
sgmii0_tx_er <= phy0_rx_er;
sgmii0: sgmii
generic map (
fabtech => fabtech
)
port map(
clk_125 => clk_125,
rst_125 => rst_125,
ser_rx_p => ETH_TX_p(0),
ser_tx_p => ETH_RX_p_d,
txd => sgmii0_txd,
tx_en => sgmii0_tx_en,
tx_er => sgmii0_tx_er,
tx_clk => sgmii0_gtx_clk,
rxd => sgmii0_rxd,
rx_dv => sgmii0_rx_dv,
rx_er => sgmii0_rx_er,
rx_col => sgmii0_rx_col,
rx_crs => sgmii0_rx_crs,
rx_clk => sgmii0_rx_clk,
mdc => ETH_MDC(0)
);
end generate;
ethsim1 : if CFG_GRETH2 /= 0 generate
-- connecting PHY through SGMII to MAC
p1: phy
generic map(
address => 1
)
port map(
rstn => CPU_RESET_n,
mdio => ETH_MDIO(1),
tx_clk => open,
rx_clk => open,
rxd => phy1_rxd,
rx_dv => phy1_rx_dv,
rx_er => phy1_rx_er,
rx_col => phy1_rx_col,
rx_crs => phy1_rx_crs,
txd => phy1_txd,
tx_en => phy1_tx_en,
tx_er => phy1_tx_er,
mdc => ETH_MDC(1),
gtx_clk => phy1_gtx_clk
);
phy1_txd <= sgmii1_rxd;
phy1_tx_en <= sgmii1_rx_dv;
phy1_tx_er <= sgmii1_rx_er;
phy1_gtx_clk <= sgmii1_gtx_clk;
sgmii1_txd <= phy1_rxd;
sgmii1_tx_en <= phy1_rx_dv;
sgmii1_tx_er <= phy1_rx_er;
sgmii1: sgmii
generic map (
fabtech => fabtech
)
port map(
clk_125 => clk_125,
rst_125 => rst_125,
ser_rx_p => ETH_TX_p(1),
ser_tx_p => ETH_RX_p(1),
txd => sgmii1_txd,
tx_en => sgmii1_tx_en,
tx_er => sgmii1_tx_er,
tx_clk => sgmii1_gtx_clk,
rxd => sgmii1_rxd,
rx_dv => sgmii1_rx_dv,
rx_er => sgmii1_rx_er,
rx_col => sgmii1_rx_col,
rx_crs => sgmii1_rx_crs,
rx_clk => sgmii1_rx_clk,
mdc => ETH_MDC(1)
);
end generate;
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (FSM_A(romdepth downto 1), FSM_D, FLASH_CE_n, FLASH_CE_n, FLASH_CE_n,
FLASH_WE_n, FLASH_OE_n);
FLASH_RYBY_n <= 'H';
test0 : grtestmod
generic map ( width => 16 )
port map ( CPU_RESET_n, OSC_50_BANK3, LED(0), FSM_A(20 downto 1), FSM_D,
'0', FLASH_OE_n, FLASH_WE_n);
iuerr : process
begin
wait for 2500 ns;
if to_x01(LED(0)) = '1' then wait on LED(0); end if;
assert (to_x01(LED(0)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
FSM_D <= buskeep(FSM_D) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);--
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);--
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);--
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);--
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);--
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);--
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);--
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);--
end;--
begin--
dsucfg(UART_TXD, UART_RXD);--
wait;
end process;
end ;
|
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