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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FF_TagRam64x36 is
port (
wea : in STD_LOGIC;
web : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( C_TAGRAM_AWIDTH-1 downto 0 );
addrb : in STD_LOGIC_VECTOR ( C_TAGRAM_AWIDTH-1 downto 0 );
douta : out STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
dina : in STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
clk : in STD_LOGIC
);
end FF_TagRam64x36;
architecture STRUCTURE of FF_TagRam64x36 is
TYPE FF_RAM_Matrix is ARRAY (C_TAG_MAP_WIDTH-1 downto 0)
of std_logic_vector (C_TAGRAM_DWIDTH-1 downto 0);
signal FF_Reg : FF_RAM_Matrix;
signal FF_Muxer_a : STD_LOGIC_VECTOR ( C_TAG_MAP_WIDTH-1 downto 0 );
signal FF_Muxer_b : STD_LOGIC_VECTOR ( C_TAG_MAP_WIDTH-1 downto 0 );
--
signal wea_r1 : STD_LOGIC;
signal web_r1 : STD_LOGIC;
signal dina_r1 : STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
signal dinb_r1 : STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
signal douta_i : STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
signal doutb_i : STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
begin
douta <= douta_i;
doutb <= (OTHERS=>'0'); -- doutb_i;
-- ---------------------------------------
--
Syn_Delay_Writes:
process ( clk )
begin
if clk'event and clk = '1' then
wea_r1 <= wea;
web_r1 <= web;
dina_r1 <= dina;
dinb_r1 <= dinb;
end if;
end process;
-- ---------------------------------------
--
FF_Address:
process ( clk )
begin
if clk'event and clk = '1' then
FOR k IN 0 TO C_TAG_MAP_WIDTH-1 LOOP
if addra=CONV_STD_LOGIC_VECTOR(k, C_TAGRAM_AWIDTH)
then
FF_Muxer_a(k) <= '1';
else
FF_Muxer_a(k) <= '0';
end if;
END LOOP;
FOR k IN 0 TO C_TAG_MAP_WIDTH-1 LOOP
if addrb=CONV_STD_LOGIC_VECTOR(k, C_TAGRAM_AWIDTH)
then
FF_Muxer_b(k) <= '1';
else
FF_Muxer_b(k) <= '0';
end if;
END LOOP;
end if;
end process;
-- ---------------------------------------
--
FF_Matrix_Write:
process ( clk )
begin
if clk'event and clk = '1' then
FOR k IN 0 TO C_TAG_MAP_WIDTH-1 LOOP
if wea_r1='1' and web_r1='1' and FF_Muxer_a(k)='1' and FF_Muxer_b(k)='1' then
FF_Reg(k) <= dina_r1;
elsif wea_r1='1' and FF_Muxer_a(k)='1' then
FF_Reg(k) <= dina_r1;
elsif web_r1='1' and FF_Muxer_b(k)='1' then
FF_Reg(k) <= dinb_r1;
else
FF_Reg(k) <= FF_Reg(k);
end if;
END LOOP;
end if;
end process;
-- ---------------------------------------
--
FF_Matrix_Read:
process ( clk )
begin
if clk'event and clk = '1' then
case FF_Muxer_a is
when X"0000000000000001" =>
douta_i <= FF_Reg(0);
when X"0000000000000002" =>
douta_i <= FF_Reg(1);
when X"0000000000000004" =>
douta_i <= FF_Reg(2);
when X"0000000000000008" =>
douta_i <= FF_Reg(3);
when X"0000000000000010" =>
douta_i <= FF_Reg(4);
when X"0000000000000020" =>
douta_i <= FF_Reg(5);
when X"0000000000000040" =>
douta_i <= FF_Reg(6);
when X"0000000000000080" =>
douta_i <= FF_Reg(7);
when X"0000000000000100" =>
douta_i <= FF_Reg(8);
when X"0000000000000200" =>
douta_i <= FF_Reg(9);
when X"0000000000000400" =>
douta_i <= FF_Reg(10);
when X"0000000000000800" =>
douta_i <= FF_Reg(11);
when X"0000000000001000" =>
douta_i <= FF_Reg(12);
when X"0000000000002000" =>
douta_i <= FF_Reg(13);
when X"0000000000004000" =>
douta_i <= FF_Reg(14);
when X"0000000000008000" =>
douta_i <= FF_Reg(15);
when X"0000000000010000" =>
douta_i <= FF_Reg(16);
when X"0000000000020000" =>
douta_i <= FF_Reg(17);
when X"0000000000040000" =>
douta_i <= FF_Reg(18);
when X"0000000000080000" =>
douta_i <= FF_Reg(19);
when X"0000000000100000" =>
douta_i <= FF_Reg(20);
when X"0000000000200000" =>
douta_i <= FF_Reg(21);
when X"0000000000400000" =>
douta_i <= FF_Reg(22);
when X"0000000000800000" =>
douta_i <= FF_Reg(23);
when X"0000000001000000" =>
douta_i <= FF_Reg(24);
when X"0000000002000000" =>
douta_i <= FF_Reg(25);
when X"0000000004000000" =>
douta_i <= FF_Reg(26);
when X"0000000008000000" =>
douta_i <= FF_Reg(27);
when X"0000000010000000" =>
douta_i <= FF_Reg(28);
when X"0000000020000000" =>
douta_i <= FF_Reg(29);
when X"0000000040000000" =>
douta_i <= FF_Reg(30);
when X"0000000080000000" =>
douta_i <= FF_Reg(31);
when X"0000000100000000" =>
douta_i <= FF_Reg(32);
when X"0000000200000000" =>
douta_i <= FF_Reg(33);
when X"0000000400000000" =>
douta_i <= FF_Reg(34);
when X"0000000800000000" =>
douta_i <= FF_Reg(35);
when X"0000001000000000" =>
douta_i <= FF_Reg(36);
when X"0000002000000000" =>
douta_i <= FF_Reg(37);
when X"0000004000000000" =>
douta_i <= FF_Reg(38);
when X"0000008000000000" =>
douta_i <= FF_Reg(39);
when X"0000010000000000" =>
douta_i <= FF_Reg(40);
when X"0000020000000000" =>
douta_i <= FF_Reg(41);
when X"0000040000000000" =>
douta_i <= FF_Reg(42);
when X"0000080000000000" =>
douta_i <= FF_Reg(43);
when X"0000100000000000" =>
douta_i <= FF_Reg(44);
when X"0000200000000000" =>
douta_i <= FF_Reg(45);
when X"0000400000000000" =>
douta_i <= FF_Reg(46);
when X"0000800000000000" =>
douta_i <= FF_Reg(47);
when X"0001000000000000" =>
douta_i <= FF_Reg(48);
when X"0002000000000000" =>
douta_i <= FF_Reg(49);
when X"0004000000000000" =>
douta_i <= FF_Reg(50);
when X"0008000000000000" =>
douta_i <= FF_Reg(51);
when X"0010000000000000" =>
douta_i <= FF_Reg(52);
when X"0020000000000000" =>
douta_i <= FF_Reg(53);
when X"0040000000000000" =>
douta_i <= FF_Reg(54);
when X"0080000000000000" =>
douta_i <= FF_Reg(55);
when X"0100000000000000" =>
douta_i <= FF_Reg(56);
when X"0200000000000000" =>
douta_i <= FF_Reg(57);
when X"0400000000000000" =>
douta_i <= FF_Reg(58);
when X"0800000000000000" =>
douta_i <= FF_Reg(59);
when X"1000000000000000" =>
douta_i <= FF_Reg(60);
when X"2000000000000000" =>
douta_i <= FF_Reg(61);
when X"4000000000000000" =>
douta_i <= FF_Reg(62);
-- when X"8000000000000000" =>
-- douta_i <= FF_Reg(63);
when OTHERS =>
douta_i <= FF_Reg(63);
end case;
end if;
end process;
end architecture STRUCTURE;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2011 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (8);
constant CFG_DDRSP_RSKEW : integer := (0);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0b#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 1;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (2);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
constant CFG_SPIMCTRL_OFFSET : integer := 16#50000#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (4);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0#;
constant CFG_GRGPIO_WIDTH : integer := (6);
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (2);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 1;
constant CFG_SPICTRL_TWEN : integer := 1;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-------------------------------------------------------------------------------
-- Title : Instruction Cache L1
-- Project :
-------------------------------------------------------------------------------
-- File : Instruction_Cache.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-11-10
-- Last update: 2017-01-01
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Level 1 cache for instruction fetch
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-10 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cache_defs.all;
-------------------------------------------------------------------------------
entity Instruction_Cache is
generic (
ADDR_WIDTH : integer;
DATA_WIDTH : integer
);
port (
clk : in std_logic;
rst : in std_logic;
-- stall_req : in std_logic;
addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
data_valid : out std_logic;
-- L2 connections
o_creq : out cache_request_t;
i_cresp : in cache_response_t
);
end entity Instruction_Cache;
-------------------------------------------------------------------------------
architecture rtl of Instruction_Cache is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal i_porta_req : std_logic;
signal fetch_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal fetched_instr_valid : std_logic;
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
L1_Instr : entity work.SinglePort_Associative_Cache
generic map (
WRITE_BACK => false)
port map (
clk => clk,
rst => rst,
i_porta_req => i_porta_req,
i_porta_we => '0',
i_porta_do_write_through => '0',
i_porta_addr => fetch_addr,
i_porta_write_data => (others => 'X'),
o_porta_read_data => data,
o_porta_valid => fetched_instr_valid,
-- Carry over
o_creq => o_creq,
i_cresp => i_cresp
);
i_porta_req <= '1' when rst = '0';
data_valid <= fetched_instr_valid;
fetch_addr <= addr;
end architecture rtl;
-------------------------------------------------------------------------------
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end LBDR;
architecture behavior of LBDR is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
begin
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
process(clk, reset)
begin
if reset = '0' then
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
elsif clk'event and clk = '1' then
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
end if;
end process;
-- The combionational part
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
END; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end LBDR;
architecture behavior of LBDR is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
begin
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
process(clk, reset)
begin
if reset = '0' then
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
elsif clk'event and clk = '1' then
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
end if;
end process;
-- The combionational part
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
END; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end LBDR;
architecture behavior of LBDR is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
begin
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0';
E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0';
W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0';
S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0';
process(clk, reset)
begin
if reset = '0' then
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
elsif clk'event and clk = '1' then
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
end if;
end process;
-- The combionational part
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
END; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity repro3 is
port (
clk : std_logic;
led : out std_logic);
end;
architecture behav of repro3 is
constant LOOKUP_LEN : integer := 6;
constant LOOKUP_TABLE : unsigned(LOOKUP_LEN*8-1 downto 0) :=
x"010205" & x"060708";
signal brt : unsigned(7 downto 0) := (others => '0');
begin
led <= brt (0);
lookup_p : process(Clk)
variable idx : integer range 0 to LOOKUP_LEN-1 := LOOKUP_LEN-1;
begin
if rising_edge(Clk) then
brt <= lookup_table(8*idx+7 downto 8*idx);
if idx /= 0 then
idx := idx - 1;
else
idx := LOOKUP_LEN-1;
end if;
end if;
end process;
end behav;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sat Dec 24 01:08:44 2016
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- d:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_tex/bg_tex_sim_netlist.vhdl
-- Design : bg_tex
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_bindec : entity is "bindec";
end bg_tex_bindec;
architecture STRUCTURE of bg_tex_bindec is
begin
\/i_\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => addra(1),
I1 => addra(0),
O => ena_array(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end bg_tex_blk_mem_gen_mux;
architecture STRUCTURE of bg_tex_blk_mem_gen_mux is
signal sel_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\douta[10]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7),
I4 => sel_pipe_d1(0),
O => douta(7)
);
\douta[11]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOPADOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0),
I4 => sel_pipe_d1(0),
O => douta(8)
);
\douta[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0),
I4 => sel_pipe_d1(0),
O => douta(0)
);
\douta[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1),
I4 => sel_pipe_d1(0),
O => douta(1)
);
\douta[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2),
I4 => sel_pipe_d1(0),
O => douta(2)
);
\douta[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3),
I4 => sel_pipe_d1(0),
O => douta(3)
);
\douta[7]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4),
I4 => sel_pipe_d1(0),
O => douta(4)
);
\douta[8]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5),
I4 => sel_pipe_d1(0),
O => douta(5)
);
\douta[9]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0ACFC0"
)
port map (
I0 => DOADO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6),
I4 => sel_pipe_d1(0),
O => douta(6)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bg_tex_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bg_tex_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"000000000E000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000007000000000000000000000000038000000000000000000000000",
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INIT_11 => X"0000040000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"8000000000000000000000000000000000000000000000000000000000000000",
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INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000004000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000040000",
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INIT_1A => X"0080200000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000040000000000020000000000000000000000000000000000000",
INIT_1C => X"00000000000080000000000000008004000000000000000000000A0000000000",
INIT_1D => X"0000000000000200000000000000000000000000000000001000000000000001",
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INIT_1F => X"0000000008000000010000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000004000040000000000000000000000000000000000000",
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INIT_23 => X"0000000000000000000000000000000000000000000000000000000000040000",
INIT_24 => X"0000000000000000000400020000000000000000000000000000000000000000",
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INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0080000000000000000000000000000000000000000000000000800000000000",
INIT_28 => X"0000000000000800000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => douta(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4C => X"000000000000000C000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000003000000000000000000000000000000000000",
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INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"00000000000000000000000C0000000000000000000000000200000000000000",
INITP_05 => X"00000007E0000000000000000000000000F00000000000000000000000003800",
INITP_06 => X"0000F0000000000001FF8000000000700000000000003FC00000000020000000",
INITP_07 => X"FFFBF80000000003F8000001FFFFFFFE0000000001F00000000FFF07FF000000",
INITP_08 => X"1FFE0000FFFFFFF9C0000000000FFE00003FFFFFF3F00000000007F8000007FF",
INITP_09 => X"F800000000007FFF801FFFFFFFF800000000003FFF0007FFFFFFF90000000000",
INITP_0A => X"F0FFFFFFFFFFF00000000001FFFE03FFFFFFFFF80000000000FFFF807FFFFFFF",
INITP_0B => X"0000000007F87FFFFFFFFFFFE00000000007FF0FFFFFFFFFFFF00000000003FF",
INITP_0C => X"FFFFFFFFC40000000000021FFFFFFFFFFFF1800000000007C3FFFFFFFFFFFFC0",
INITP_0D => X"000000001FFFFFFFFFFE020000000000001FFFFFFFFFFF190000000000001FFF",
INITP_0E => X"81FFF8300000000000003FFFFFE1FFF8080000000000001FFFFFFFFFFC040000",
INITP_0F => X"000007FFBFFC23FFFFE00000000000074047FE11FFF8E00000000000040FC0FF",
INIT_00 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_01 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_02 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_03 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_04 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_05 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_06 => X"1A161A161A161A161A161A161616161616161616161616161616161616161616",
INIT_07 => X"1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16",
INIT_08 => X"1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16",
INIT_09 => X"1616161616161A161A161A161A161A161A161A161A161A161A161A161A161A16",
INIT_0A => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_0B => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_0C => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_0D => X"161616161616161616161616161616161616161616161616161A161616161616",
INIT_0E => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_0F => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_10 => X"1A161A161A161A161A161A161A161A1616161616161616161616161616161616",
INIT_11 => X"1A161A161A161A161A161A161A161A161A161A161A0020161A161A161A161A16",
INIT_12 => X"1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16",
INIT_13 => X"1616161616161616161616161A161A161A161A161A161A161A161A161A161A16",
INIT_14 => X"1616161616161616161616060000161616161616161616161616161616161616",
INIT_15 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_16 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_17 => X"16160000201616161616161616161616161616161616161616161616161A1616",
INIT_18 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_19 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_1A => X"1A161A161A161A161A161A161A161A161A161A1616161616161A161616161616",
INIT_1B => X"1A161A161A161A161A161A161A161A161A161A161A161A160000000016161A16",
INIT_1C => X"1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16",
INIT_1D => X"1616161616161616161616161A161616161616161A161A161A161A161A161A16",
INIT_1E => X"161616161616161616161616161600000000001A161616161616161616161616",
INIT_1F => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_20 => X"1616161616161616161A16161616161616161616161616161616161616161616",
INIT_21 => X"1616161600007600000016161616161616161616161616161616161616161616",
INIT_22 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_23 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_24 => X"0016161A161A161A161A161A161A161A161A161A161A161A161616161616161A",
INIT_25 => X"161A161A161A161A161A161A161A161A161A161A161A161A161A000076760000",
INIT_26 => X"161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A",
INIT_27 => X"16161616161616161616161616161616161A161A16161616161A161A161A161A",
INIT_28 => X"1616161616161616161616161616160000007676760000001616161616161616",
INIT_29 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_2A => X"1616161616161A161616161A1616161616161616161616161616161616161616",
INIT_2B => X"16161616000000EE7676BA76000020161A161616161616161616161616161616",
INIT_2C => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_2D => X"161616161A161A16161600001616161616161616161616161616161616161616",
INIT_2E => X"7676760000001616161A161A161A161A161A161A161A161A161A161616161616",
INIT_2F => X"161A161A161A161A161A161A161A161A161A161A161A161A161A0000EE767676",
INIT_30 => X"16007600001A161A161A161A161A161A161A161A161A161A161A161A161A161A",
INIT_31 => X"1616161616161616161616161616161616161A16161A1616161616161616161A",
INIT_32 => X"1616161616161616161616161616161600007676BA76BA767676000016161616",
INIT_33 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_34 => X"1616161616161616161616161616161616161616161616160076767600161616",
INIT_35 => X"001616161600007676767676767676BA76000016161A16161616161616161616",
INIT_36 => X"1616161616161616161616161616161616161616160000000000000000000000",
INIT_37 => X"161A16161A161616161A161A1616160076BA7676001616161616161616161616",
INIT_38 => X"76BA76767676767600001A1616161A161A161A161A161A161A161A161A161A16",
INIT_39 => X"161A161A161A161A000000007676767676767676767676760000000000767676",
INIT_3A => X"16161616161A0076763276760002161A161A161A161A161A161A161A161A161A",
INIT_3B => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_3C => X"767676BA7676BA7676BA7676BA76767676767676BA76BA767676BA7676767600",
INIT_3D => X"BA76767676000016461A16161616161616161616161616161616161616160076",
INIT_3E => X"161616161616161616161616161A16161A16161616161A161616161A16007676",
INIT_3F => X"7676767676BA76BA76BA767676EE7676327676BA76EE0016161A161616161616",
INIT_40 => X"1616161616161616161616161616161616161600007676767676767676767676",
INIT_41 => X"1A161A16161616161A1616161616161A161616160076767676BA767676EE0202",
INIT_42 => X"76767676AA003276767676760216161616161A161A161A161A161A161A161A16",
INIT_43 => X"1A161A161A161A161A0076767676BA76BA7676BA7676BA7676BA767676767676",
INIT_44 => X"161616161616161A1616160076BA7676767676BA7676760000161A161A161A16",
INIT_45 => X"BA76461616161A1616161616161616161616161616161616161616161A161616",
INIT_46 => X"767676BA7676767676767676767676767676BA76767676767676BA7676006676",
INIT_47 => X"1A16007676767676BA7676763276760000161616161616161616161616160000",
INIT_48 => X"1616161616161616161616161616161616161616161616161A16161A16161616",
INIT_49 => X"7676BA7676BA7676767676BA76BA76BA767676767620AA766620161616161616",
INIT_4A => X"7676BA76BA76767600001616161616161616161600767676BA767676767676BA",
INIT_4B => X"161A161A161A161A16161A161A161616161616161616161616007676BA767676",
INIT_4C => X"767676767676767676BA76BA7622002016161A16161A161A161A161A161A161A",
INIT_4D => X"BA0000AA1A161A161A16007676BA76767676BA76BA767676767676767676BA76",
INIT_4E => X"161616161616161616161A16161A161600BA767676BA76767676767676BA7676",
INIT_4F => X"7676767632006606161616161616161616161616161616161616161616161616",
INIT_50 => X"0076BA767676767676767676767676BA7676BA76767676BA7676767676767676",
INIT_51 => X"161616161616160076767676767676BA7676767676767676764600AA16161600",
INIT_52 => X"16161A16161616161616161616161616161616161616161A161616161A161616",
INIT_53 => X"76767676BA7676767676767676767676BA76BA76BA76BA767676BA767600161A",
INIT_54 => X"76BA7676BA76767676BA767676BA76EE64000000000076767676767676BA76BA",
INIT_55 => X"161A161A161A161A161A161A16161616161A161616161616161A16161A160032",
INIT_56 => X"76BA76BA76767676767676767676767676767676001616161616161A161A161A",
INIT_57 => X"7676762A640000AA327676767676BA767676BA7676767676BA7676767676BA76",
INIT_58 => X"161616161A1616161616161616161A16161616161600327676767676767676BA",
INIT_59 => X"7676767676BA767676BA767600161A1616161616161616161616161616161616",
INIT_5A => X"BA7676BA767676BA767676767676767676BA76767676767676767676BA767676",
INIT_5B => X"161A1616161616161A1616160032BA7676BA7676BA767676A06600AA32BA7676",
INIT_5C => X"767632001616161A1616161616161616161616161616161616161616161A1616",
INIT_5D => X"76BA7676BA767676767676BA7676BA76767676767676BA76BA76BA767676BA76",
INIT_5E => X"16161A16007676767676767676600200EE767676767676767676767676767676",
INIT_5F => X"161A161A161A161A161A161A161A161A161A161616161A161616161616161616",
INIT_60 => X"BA76767676767676BA7676BA76767676767676767676767676BA001616161616",
INIT_61 => X"7632460022EE76BA7676BA7676BA7676BA767676BA7676767676767676BA7676",
INIT_62 => X"16161616161616161616161616161616161616161A16161A16161600007676BA",
INIT_63 => X"76767676767676767676BA32000000767600161A1616161A1616161616161616",
INIT_64 => X"767676767676767676BA767676BA767676BA7676767676767676BA767676BA76",
INIT_65 => X"1A161A1616161A16161616161616161616168E1600AA76460000007676BA7676",
INIT_66 => X"76760000EE33EEEEEE0016161A16161616161616161616161616161616161616",
INIT_67 => X"767676767676BA7676767676BA7676BA767676BA76767676BA7676BA76BA76BA",
INIT_68 => X"161A16161A16161A161A16002000000000006676767676BA7676BA7676BA7676",
INIT_69 => X"0016161616161616161A161A161A161A161A161A161A16161616161A16161616",
INIT_6A => X"76BA767676767676767676767676767676767676767676760000007777AA0076",
INIT_6B => X"16160000000000000000667676767676767676767676767676BA767676767676",
INIT_6C => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_6D => X"7676BA7676BA7676BA76767676767600000066EE460076001A16161A16161A16",
INIT_6E => X"00000076BA3276BA767676BA7676BA767676BA767676BA76767676BA767676BA",
INIT_6F => X"16161616161A161A1616161A16161616161A16161A1616161616000000000000",
INIT_70 => X"76BA76BA76760000000000000076001616161616161616161616161616161616",
INIT_71 => X"BA76767676767676767676BA7676767676767676BA7676767676767676767676",
INIT_72 => X"1A1616161616161A16161616161A161A16161600000000000000007676767676",
INIT_73 => X"00000000760016161A16161A16161A161A161A161A161A161A161A1616161616",
INIT_74 => X"7676767676BA76BA767676000000007676BA767676BA767676767676BA000000",
INIT_75 => X"161A1616161616161A1616000000000000007676BA7676767676BA7676BA7676",
INIT_76 => X"1616161616161616161616161616161616161616161616161616161A16161616",
INIT_77 => X"7600004666AA00767676BA767676767676767676760000000000767600161616",
INIT_78 => X"161616000076AA00000000EE7676767676760000000000007676767676767676",
INIT_79 => X"161616161616161616161A161A1616161A16161A161616161616161616161616",
INIT_7A => X"7676767676BA76BA76BA7676760000007676BAEE001A16161A16161A16161616",
INIT_7B => X"EE76000000000000007600EEEE767676BA76BA76767676000000EEBBEE000076",
INIT_7C => X"16161616161A161616161616161A161A16161A161A1616161A16161600767632",
INIT_7D => X"76767676767676767676760000161616161616161A161A161A161A161A161A16",
INIT_7E => X"76007676BA767676767676BA76BA000000AA77EE000076BA767676BA76767676",
INIT_7F => X"161616161616161616161616161A1616161A16160076BA767676767676767676",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"E1F9E0000000000007FEFFF00FFFFC40000000000007FF7FF807FFFF00000000",
INITP_01 => X"000FF7FFC1FF8FCFC0000000000007FBFFE07FC3E7E0000000000007FDFFE01F",
INITP_02 => X"3E0000000000003FDFFFFFFFF99F0000000000001FEFFFFFFFFF9F8000000000",
INITP_03 => X"F07C7C7F0F7F00000000000001FC7F1C7FE0BF38000000000000FF3FC07FFF07",
INITP_04 => X"00000000001F81F3FDFFCDFF0000000000000FE0F9FEFFCEFFC0000000000007",
INITP_05 => X"DFCFFFFFF00000000000002C01CFF7FFCFF80000000000001C01E7FBFF8BFE00",
INITP_06 => X"000000007801C07FFFFFF00000000000003003CF1FFFFFD00000000000003801",
INITP_07 => X"FFFFFFC0000000000000B81E7FFFFFFFE00000000000007C0CC3FFFFFFE00000",
INITP_08 => X"00000FA1FFFFFFFFFF80000000000003D87FFFFFFFFFC0000000000001F81F3F",
INITP_09 => X"FFFE0000000000007607FFFFFFFFFF0000000000003F83FFFFFFFFFF80000000",
INITP_0A => X"01603FFF7FFFEFFC000000000000F01FFFFFFFF7FE000000000000FC0FFFFFFF",
INITP_0B => X"60000000000003807FFEFFFFBFB0000000000003403FFEFFFFDFD80000000000",
INITP_0C => X"C0FFFDFFFDFB8000000000000782FFFDFFFEFEC0000000000007827FFDFFFF7E",
INITP_0D => X"00000000001F31FFFBFFEFEF8000000000000F90FFFBFFFBF780000000000002",
INITP_0E => X"1FF3FF1EFF8000000000001CFFFFE9FF3F7FC000000000001E7FFFF3FF9FBF80",
INITP_0F => X"0000000031FFCFCFFF07FE00000000000039FF9FE7FE2DFF00000000000018FE",
INIT_00 => X"4600000000161A16161A161616161616161616161616161A1616161616161616",
INIT_01 => X"76767676760000000000000000767676BA76767676767676BA76BA767676BA76",
INIT_02 => X"16161616161616161616161A007676BA76BA76BA76BA76760076767676BA7676",
INIT_03 => X"16161616161616161616161616161616161A1616161A1616161A161616161A16",
INIT_04 => X"00000000767676767676767676BA7676767676BA767600206060600000161616",
INIT_05 => X"1A161616003276767676767676BA760076BA7676767676BA7676767600000000",
INIT_06 => X"161A161A16161A1616161A161616161616161A161616161A161A1616161A1616",
INIT_07 => X"7676BAEE6600AA76767676763200A0606060600016161A16161A161A161A161A",
INIT_08 => X"767676767676007676767676BA76767676BA76000000000000000076BA7676BA",
INIT_09 => X"16161616161616161616161A1616161616161A16161616161616161600767676",
INIT_0A => X"767676EE00606060A06060001616161616161616161616161616161616161616",
INIT_0B => X"BA767676767676BA767676000000000000767676767676767676000000AABA76",
INIT_0C => X"161616161616161616161616161A16161A16161602BA76BA7676BA7676007676",
INIT_0D => X"60600016161A1616161616161616161616161A1616161A1616161A1616161A16",
INIT_0E => X"7676EE000000007676BA7676BA7676BA76AA4620767676BA7676AA0060A06060",
INIT_0F => X"16161A1616161616161A1600767676767676767600BA767676BA7676BA767676",
INIT_10 => X"161A161A161A161A1616161A1616161A161616161616161A16161A161A161A16",
INIT_11 => X"76767676767676767676BA76767632BA76EE0060606060A0600016161616161A",
INIT_12 => X"161600767676BA7676BA7600767676767676767676767676BA76767676767676",
INIT_13 => X"16161616161616161616161616161616161616161616161A161616161A161616",
INIT_14 => X"767676BA7600AA76BA00206060206060001A16161A1616161616161616161616",
INIT_15 => X"767600767676BA7676BA7676767632327676BA7676BA7676BA767676BA7676BA",
INIT_16 => X"1616161A1616161A16161616161616161616161616161A16160076BA76767676",
INIT_17 => X"AA2060A0606060001616161616161616161616161616161A1616161A1616161A",
INIT_18 => X"7676AA2000200020EE7676767676767676BA7676767676760000000000767676",
INIT_19 => X"1A161A161616161A161616161A161600767676767676BA76000076BA76767676",
INIT_1A => X"161A16161A161A161A161A161A1616161A1616161A161616161616161A161616",
INIT_1B => X"66BA3276BA7676767676760000000060600076767676767666006060A0001616",
INIT_1C => X"1A161616161600767676BA76767600160076767676BA3276000060606020A000",
INIT_1D => X"1616161616161616161616161616161616161616161616161616161A16161616",
INIT_1E => X"EE0000006060A02000767676BA76BA76AA000000000616161616161616161616",
INIT_1F => X"7676767600161616007676767676AA00E060A06060A0A6206676767676BA7676",
INIT_20 => X"1A1616161A1616161A1616161A1616161616161A161616161A161616003276BA",
INIT_21 => X"76BA3276767676BA7676001616161A16161A161616161616161616161A161616",
INIT_22 => X"76BA7676BA6400A0606020606060200076BA7676767676BA7676000020606000",
INIT_23 => X"161A1616161A161A161616161A161616161A1600BA76767676BA7600161A1600",
INIT_24 => X"EE00161A1616161616161A161A161A161A161616161A1616161A161616161616",
INIT_25 => X"60A06060606000327676767676BA767676760060606000767676767676767676",
INIT_26 => X"1616161616161616161600767676763276001616161600767676767600A06060",
INIT_27 => X"1616161616161616161A16161616161616161616161616161616161616161616",
INIT_28 => X"BA76BA76767676BA76EE00A060007676BA76BA767676760016161616161A1616",
INIT_29 => X"16160076BA32E82000161A1616160076BA767620606020606060A02020003276",
INIT_2A => X"16161616161A1616161A1616161A1616161A161616161A16161A16161A161616",
INIT_2B => X"7676000076BA767676763276BA00161A1616161616161A161616161616161616",
INIT_2C => X"1616161A1600EE7676764660A060A060606060200032767676767676767676BA",
INIT_2D => X"1616161616161A161616161A1616161616161616161A161A1600BAE820326000",
INIT_2E => X"76BA7676001616161A161A161616161A161A161A161A161A16161A1616161A16",
INIT_2F => X"BA7620602060606060A0E00076BA7676767676BA76767676BA76767676767676",
INIT_30 => X"1A16161616161A16161A1616161616161600207660E00000161616161600EE76",
INIT_31 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_32 => X"6420AA767676BA76BA767676767676767676BA7676BA76767676007600161616",
INIT_33 => X"161616161616161600EE2032E8AA200016161A160A00767676BA206060A06060",
INIT_34 => X"1616161616161A16161A1616161A161616161A16161616161616161A16161616",
INIT_35 => X"7676BA7676BA7676767676767676BA767676763200161616161A161A16161616",
INIT_36 => X"0032603260A622001616161A000000767676A0A0E020E0606076BA7676767676",
INIT_37 => X"16161616161616161616161A16161A161A161616161A16161A161A161A161616",
INIT_38 => X"76BA76767676767676BA760000161A1616161616161A161A161A161A16161616",
INIT_39 => X"161616007676000076766000A0A076767676767676767676767676767676BA76",
INIT_3A => X"1616161616161616161616161616161616161616161A16120020326032202000",
INIT_3B => X"767676001616161616161A16161616161616161616161A16161A16161A161616",
INIT_3C => X"007676BA76BA3276BA7676BA76BA76BA7676BA76767676767676BA767676BA76",
INIT_3D => X"1A161A16161A1616161616161616160032AA203260EE001A1600EE76BA767600",
INIT_3E => X"16161616161616161616161A16161616161616161616161A1616161A16161616",
INIT_3F => X"76327676767676767676767676BA7676767676BA76767676BA76001616161A16",
INIT_40 => X"1A1616161A1600206032203220A6001600EEEE7676BA76760000767676767676",
INIT_41 => X"1A161616161A16161A161616161616161A161616161A16161616161616161A16",
INIT_42 => X"76BA76767676BA767676767676BA76767676001A1616161A16161A161A161A16",
INIT_43 => X"3220EE7620001600EE3276767676767676BA7676BA7676BA767676767676BA76",
INIT_44 => X"1A1616161616161616161A1616161616161A161616161616161A161616003220",
INIT_45 => X"76767676767676BA760016161616161616161616161616161616161616161616",
INIT_46 => X"76767676BA76BA76767676767676767676BA76BA7676767676BA7676767676BA",
INIT_47 => X"16161616161A161616161A1616161616161616003220322076E0200016160076",
INIT_48 => X"7600161A1616161A1616161616161616161A16161A161616161616161A161616",
INIT_49 => X"BA7676BA7676BA767676767676BA76767676BA7676767676BA76BA7676767676",
INIT_4A => X"161616161A161A161600322032603220324600161600767676BA767676767676",
INIT_4B => X"1A161A161A161A1616161616161616161A161616161A161A16161A1616161A16",
INIT_4C => X"7676767676767676767676BA76763276767676BA767676BA001616161A161616",
INIT_4D => X"00207620EE2032A00016161A0076BA7676767676767676767676767676767676",
INIT_4E => X"1A16161A161A16161616161616161616161616161616161616161A161616161A",
INIT_4F => X"76767676BA76327676767676BA76760016161616161616161616161616161616",
INIT_50 => X"1616160076767676BA76BA76BA767676BA3276BA7676BA76BA767676BA7676BA",
INIT_51 => X"161A161616161A16161A1616161A161A16161616161616003220322076600016",
INIT_52 => X"76767676767676001A1616161A16161616161616161616161616161616161616",
INIT_53 => X"7676767676BA7676767676767676767676BA7676767676767676767600BA76BA",
INIT_54 => X"16161A16161616161616161A1616160032203220A016161A1616007676767676",
INIT_55 => X"161A1616161A161A161A161A161A16161A161616161616161616161A16161616",
INIT_56 => X"007676BA7676767676767676BA767676BA76320076767676BA76767676760016",
INIT_57 => X"1A1616161A160060A66032001A16161616002ABA76BA7676767676767676BA76",
INIT_58 => X"1616161616161616161A16161A1616161A16161616161A161616161616161616",
INIT_59 => X"76BA767676BA7676763200767676767676760076BA0016161616161616161616",
INIT_5A => X"EE20001616161A0060AA76767676BA76BA7676767676320076767676BA767676",
INIT_5B => X"16161616161616161616161A1616161616161A161A1616161616161616163260",
INIT_5C => X"320076BA767676BA76002A76001616161A16161616161616161616161A161616",
INIT_5D => X"607676767676767676BA7676767676007676767676BA767676767676767676BA",
INIT_5E => X"1A161616161A161A16161616161A16161A1616161600322032A62016161620A0",
INIT_5F => X"20767600161A1616161A161A161A161A161A1616161A16161A161616161A1616",
INIT_60 => X"7676BA76BA760032BA76767676BA767676BA76767676763200767676BA7632EE",
INIT_61 => X"1616161616161616161A16160020326032E0201666602A666676BA7676767676",
INIT_62 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_63 => X"76BA76767676BA767676BA76BA76320076767676767676007676001616161616",
INIT_64 => X"161616160032203260EEA000006660202A767676BA76BA7676767676BA2A0076",
INIT_65 => X"161A1616161A16161A1616161A1616161A161A16161616161A161A16161A1616",
INIT_66 => X"7676767676320076BA767676BA0076762A201616161A16161616161616161616",
INIT_67 => X"A03200004660A0667676BA76767676767676767676BA00767676767676767676",
INIT_68 => X"16161616161A16161616161A161A16161616161616161616161A161600EE20A6",
INIT_69 => X"76BA762A0076BA767600001616161A161A161A161A161A1616161A1616161616",
INIT_6A => X"7676767676BA76BA7676BA7676003276BA7676BA7676BA767676767676007676",
INIT_6B => X"1616161616161616161A16161A161A1616161600207632203260AA76AA0000AA",
INIT_6C => X"76000016161616161616161616161616161616161A161616161A161616161616",
INIT_6D => X"767676767600767676767676767676BA76BA7600767676767676760076767676",
INIT_6E => X"16161616161616161A160032206032200022BA76EE00003276BA767676767676",
INIT_6F => X"161616161616161A161616161616161616161616161A161A1616161616161A16",
INIT_70 => X"7676BA767676767676000076BA76BA7676202A76BA7676BA76EE001A16161616",
INIT_71 => X"161600203220762200767676767676767676BA76767676BA7676BA76000076BA",
INIT_72 => X"1A16161A1616161616161A1616161616161A161A16161616161A161616161616",
INIT_73 => X"00007676763276320076BA7676767676767600161A161A161A161A161A161616",
INIT_74 => X"7676BA767676BA76767676BA76767676767676EE7600E8BA767676BA76767676",
INIT_75 => X"161616161616161A1616161616161A1616161A161A1616161A16003220326020",
INIT_76 => X"76767676BA7676BA760016161616161616161616161616161616161616161A16",
INIT_77 => X"0000E8BA7676BA7676BA76762220767676767676BA7676760000EE7676767600",
INIT_78 => X"16161A161616161616161616161A1616161200322060004676767676767676EE",
INIT_79 => X"0246161616161616161616161A1616161A1616161616161A16161A161A161616",
INIT_7A => X"76BA7600007676BA7676767676BA76AA0000BA00767600BA7676767676767676",
INIT_7B => X"161616161616161A1600322032A000327676BA7676BA7676BA20003276767676",
INIT_7C => X"161A1616161A16161616161616161616161616161616161616161A1616161A16",
INIT_7D => X"76BA767676327632000000000076767676BA7676BA76760002020000161A161A",
INIT_7E => X"16003260A666607676767676767676767676000032BA76767676000076767676",
INIT_7F => X"161616161A16161A1616161A16161A161616161A161616161A161A1616161616",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(12),
I1 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"FFFFFFEF80000000000013FFC07FFFFFF88000000000000BFFE61FFFFFFC0000",
INITP_01 => X"000000E7FFFFFFFFFFFC00000000000047FFCFFFFFFFFF80000000000003FFE1",
INITP_02 => X"FFF000000000000001FFF87FFFFFF800000000000000FFFEFFFFFFFE00000000",
INITP_03 => X"0001FF56FE0FFF0000000000000001FFA37FFFFFC000000000000001FFE53FFF",
INITP_04 => X"0000000000000003FDFB0003F80000000000000003FEBDE007FE000000000000",
INITP_05 => X"03EC000000400000000000000003F6000001E00000000000000003FBC00001F0",
INITP_06 => X"00000000000001A0000000000000000000000003D80000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000003000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"76767676767676BA76767676767600000000000016161616161616161616161A",
INIT_01 => X"7676BA7676BA767676767600EE7676EE0000AA76BA76767676767676BA763276",
INIT_02 => X"16161616161616161616161616161A161616161A1616161A000000A020A03276",
INIT_03 => X"76BA7676BA00E82076000000161616161A1616161A1616161616161616161616",
INIT_04 => X"7676EE0000000000002A767676BA7676BA76767676BA767676BA76BA76767676",
INIT_05 => X"1A16161A16161616161616161A16161600000032E00276BA76767676767676BA",
INIT_06 => X"76AA0016161A1616161A161616161616161A16161A16161A16161A16161A1616",
INIT_07 => X"76BA767676767676BA7676767676BA76767676BA767676767676760076BA7676",
INIT_08 => X"1616161616161616160000A022A0767676BA7676BA76767676BA76000000EE32",
INIT_09 => X"161616161A16161616161616161616161616161616161616161616161616161A",
INIT_0A => X"7676BA767676767676767676BA76BA7676767676767676BA76001A1616161616",
INIT_0B => X"0076AA2000767676767676767676BA767676AAAA32BA76BA76767676BA767676",
INIT_0C => X"1A1616161A16161A16161A16161A16161A1616161A1616161A1616161A161A16",
INIT_0D => X"76767676767676767676762ABA76000016161616161A1616161A161616161616",
INIT_0E => X"BA7676767676767676BA76767676767676BA767676767676BA7676767676BA76",
INIT_0F => X"1616161616161616161A161616161616161A16161616160032762A22AA767676",
INIT_10 => X"6600200000001616161A161616161A161616161616161616161A161616161616",
INIT_11 => X"7676BA767676BA76767676BA76BA76767676BA76767676BA7676767676BA76EE",
INIT_12 => X"1616161A161616161616161616160000BA76BA7676BA767676BA7676BA76BAE8",
INIT_13 => X"161A1616161616161A161616161A16161616161A1616161A16161A16161A1616",
INIT_14 => X"76767676767676767676BA7676767676BA76BA7676EE000020200020161A1616",
INIT_15 => X"161A161A16160032767676767676767676767676760020000076767676767676",
INIT_16 => X"1616161616161616161616161A161616161616161616161616161616161A1616",
INIT_17 => X"76767676BA767676767676326000202000001616161616161616161A16161616",
INIT_18 => X"7676BA7676BA767676BA76000032007600EE76BA7676BA76BA7676767676BA76",
INIT_19 => X"1A16161616161A16161A1616161A161A16161A1616161A161616161616160076",
INIT_1A => X"767600002060600016161A16161A1616161A16161A1616161A16161616161A16",
INIT_1B => X"76007600EE007676007676767676767676BA76BA767676767676BA7676767676",
INIT_1C => X"16161A1616161616161616161616161616161A161600EEBA767676767676BA76",
INIT_1D => X"1616161616161A1616161616161A161616161A16161616161616161616161616",
INIT_1E => X"7676BA76767676EEAAEEEEEE76BA76BA76767676BA76BA76EE00200020200016",
INIT_1F => X"161A1616161A161A1616161A1600EE767676BA7676767676007600320032BA00",
INIT_20 => X"16161616161616161616161A1616161A161A1616161A16161616161616161A16",
INIT_21 => X"000000606632767676767676767676200020202000161A16161A161616161616",
INIT_22 => X"16161616160076BA7676767676BA7600BAE8BA7676760076767676EEA0000000",
INIT_23 => X"161616161616161616161A1616161A161616161A1616161616161A1616161616",
INIT_24 => X"76BA767676EE0060A02000661616161616161A16161A16161A161A1616161616",
INIT_25 => X"7676BA7676760076BA7676767600BA76A0000000206020202060000000A02A76",
INIT_26 => X"16161616161616161A16161616161A16161616161616161A16161A1616007676",
INIT_27 => X"0016161A16161A161616161616161616161616161A161616161A16161A161616",
INIT_28 => X"7632002000AA46002020202020002020202020200020AA767676BA7666002000",
INIT_29 => X"1616161A1616161616161A161616161616161616160076BA7676767676007676",
INIT_2A => X"161A16161A161616161A161616161A1616161616161A161616161A1616161A16",
INIT_2B => X"2020202020202020202060200000002A76767660202000201616161616161616",
INIT_2C => X"1616161A16161A16161A16161600767676BA76760076BAE82000000000002060",
INIT_2D => X"16161616161616161A16161616161A161616161A161616161A161616161A161A",
INIT_2E => X"0000000000002066EE2A00200000161A16161A1616161A161616161616161A16",
INIT_2F => X"16161A161600767676BA76007676200020000000002020000060206000602020",
INIT_30 => X"161A161616161A16161616161616161616161616161616161616161616161616",
INIT_31 => X"00600000161616161616161A161616161A16161A161616161616161616161616",
INIT_32 => X"767600BA32002020200000206000202020202020000000001616161616161600",
INIT_33 => X"16161A16161A16161A161A16161616161A16161A16161A161616161A16007676",
INIT_34 => X"16161616161616161616161616161A161616161A161A161616161A161616161A",
INIT_35 => X"2020202020600020000000161616161616161A1616161616161616161616161A",
INIT_36 => X"1616161A161A16161616161616161616161616161600EE76760076A000202020",
INIT_37 => X"1A16161A16161616161616161616161616161616161616161616161616161616",
INIT_38 => X"161616161A161A161616161A1616161A16161A161A16161616161A161A161616",
INIT_39 => X"1616161A16161A1616161A16160076BA00460020202000000020602020000016",
INIT_3A => X"161616161A161A16161A16161A16161A16161A16161A1616161616161616161A",
INIT_3B => X"161616161A161616161616161616161A16161616161A161616161616161A1616",
INIT_3C => X"1616161A1600002200000020602000200000001616161616161A161616161A16",
INIT_3D => X"1616161616161616161616161616161A16161616161616161A1616161616161A",
INIT_3E => X"161616161A16161616161616161616161A16161616161616161A161616161616",
INIT_3F => X"20002020200000166616161616161A1616161616161616161A1616161616161A",
INIT_40 => X"161A16161A1616161A161A161A1616161616161A161616161616161616000000",
INIT_41 => X"161A1616161A1616161A16161616161616161616161A16161A16161A16161A16",
INIT_42 => X"1A161A1616161616161A161616161A16161616161A1616161A1616161616161A",
INIT_43 => X"16161616161616161A1616161616161A1616161616AA00006060200000161616",
INIT_44 => X"16161A1616161A16161A16161616161616161616161616161616161616161616",
INIT_45 => X"16161A16161616161A16161616161616161A16161A16161616161A1616161616",
INIT_46 => X"16161A161A1616161A161A1616600000202000166A1A16161616161A16161A16",
INIT_47 => X"16161A16161A16161A16161A16161A16161A16161A1616161616161A161A1616",
INIT_48 => X"1A1616161A161616161616161616161616161616161A16161616161616161616",
INIT_49 => X"1616161A160020600020161A16161616161616161616161616161A1616161616",
INIT_4A => X"16161616161616161616161616161A161A161616161616161616161616161616",
INIT_4B => X"1A1616161A161A1616161A1616161A1616161616161A16161616161616161616",
INIT_4C => X"16161616161A161A16161A1616161A16161616161A161616161A1616161A1616",
INIT_4D => X"1A16161A1616161616161616161A161A16161616161A16161616161616000046",
INIT_4E => X"161616161616161A1616161616161A16161A16161A16161A16161A16161A1616",
INIT_4F => X"1616161A1616161616161A16161616161616161616161616161A16161616161A",
INIT_50 => X"1A161A16161616161A161A1616161A161616161616161616161A161616161616",
INIT_51 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_52 => X"161616161A1616161A1616161A1616161616161616161616161A161616161616",
INIT_53 => X"161616161616161A161A1616161616161616161616161A1616161616161A161A",
INIT_54 => X"161A16161A16161A16161A16161A16161A16161A161A16161616161616161616",
INIT_55 => X"161616161616161616161616161616161616161616161616161A1616161A1616",
INIT_56 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_57 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_58 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_59 => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_5A => X"1616161616161616161616161616161616161616161616161616161616161616",
INIT_5B => X"0000000000001616161616161616161616161616161616161616161616161616",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(13),
I1 => addra(12),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bg_tex_blk_mem_gen_prim_width;
architecture STRUCTURE of bg_tex_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bg_tex_blk_mem_gen_prim_wrapper_init
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \bg_tex_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\bg_tex_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_width__parameterized1\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \bg_tex_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\bg_tex_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_width__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \bg_tex_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\bg_tex_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
DOPADOP(0) => DOPADOP(0),
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_tex_blk_mem_gen_prim_width__parameterized3\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_tex_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \bg_tex_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \bg_tex_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\bg_tex_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bg_tex_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bg_tex_blk_mem_gen_generic_cstr is
signal ena_array : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_8\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.bg_tex_bindec
port map (
addra(1 downto 0) => addra(13 downto 12),
ena_array(0) => ena_array(0)
);
\has_mux_a.A\: entity work.bg_tex_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6) => \ramloop[4].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5) => \ramloop[4].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4) => \ramloop[4].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3) => \ramloop[4].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2) => \ramloop[4].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1) => \ramloop[4].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0) => \ramloop[4].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[2].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[2].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[2].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[2].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[2].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[2].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[2].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[2].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[4].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[2].ram.r_n_8\,
DOADO(7) => \ramloop[3].ram.r_n_0\,
DOADO(6) => \ramloop[3].ram.r_n_1\,
DOADO(5) => \ramloop[3].ram.r_n_2\,
DOADO(4) => \ramloop[3].ram.r_n_3\,
DOADO(3) => \ramloop[3].ram.r_n_4\,
DOADO(2) => \ramloop[3].ram.r_n_5\,
DOADO(1) => \ramloop[3].ram.r_n_6\,
DOADO(0) => \ramloop[3].ram.r_n_7\,
DOPADOP(0) => \ramloop[3].ram.r_n_8\,
addra(1 downto 0) => addra(13 downto 12),
clka => clka,
douta(8 downto 0) => douta(11 downto 3)
);
\ramloop[0].ram.r\: entity work.bg_tex_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\bg_tex_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(2 downto 1),
douta(1 downto 0) => douta(2 downto 1),
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\bg_tex_blk_mem_gen_prim_width__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[2].ram.r_n_0\,
\douta[10]\(6) => \ramloop[2].ram.r_n_1\,
\douta[10]\(5) => \ramloop[2].ram.r_n_2\,
\douta[10]\(4) => \ramloop[2].ram.r_n_3\,
\douta[10]\(3) => \ramloop[2].ram.r_n_4\,
\douta[10]\(2) => \ramloop[2].ram.r_n_5\,
\douta[10]\(1) => \ramloop[2].ram.r_n_6\,
\douta[10]\(0) => \ramloop[2].ram.r_n_7\,
\douta[11]\(0) => \ramloop[2].ram.r_n_8\,
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\bg_tex_blk_mem_gen_prim_width__parameterized2\
port map (
DOADO(7) => \ramloop[3].ram.r_n_0\,
DOADO(6) => \ramloop[3].ram.r_n_1\,
DOADO(5) => \ramloop[3].ram.r_n_2\,
DOADO(4) => \ramloop[3].ram.r_n_3\,
DOADO(3) => \ramloop[3].ram.r_n_4\,
DOADO(2) => \ramloop[3].ram.r_n_5\,
DOADO(1) => \ramloop[3].ram.r_n_6\,
DOADO(0) => \ramloop[3].ram.r_n_7\,
DOPADOP(0) => \ramloop[3].ram.r_n_8\,
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
wea(0) => wea(0)
);
\ramloop[4].ram.r\: entity work.\bg_tex_blk_mem_gen_prim_width__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[4].ram.r_n_0\,
\douta[10]\(6) => \ramloop[4].ram.r_n_1\,
\douta[10]\(5) => \ramloop[4].ram.r_n_2\,
\douta[10]\(4) => \ramloop[4].ram.r_n_3\,
\douta[10]\(3) => \ramloop[4].ram.r_n_4\,
\douta[10]\(2) => \ramloop[4].ram.r_n_5\,
\douta[10]\(1) => \ramloop[4].ram.r_n_6\,
\douta[10]\(0) => \ramloop[4].ram.r_n_7\,
\douta[11]\(0) => \ramloop[4].ram.r_n_8\,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bg_tex_blk_mem_gen_top;
architecture STRUCTURE of bg_tex_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bg_tex_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bg_tex_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bg_tex_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bg_tex_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bg_tex_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bg_tex_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bg_tex_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bg_tex_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bg_tex_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bg_tex_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bg_tex_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bg_tex_blk_mem_gen_v8_3_5 : entity is "4";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bg_tex_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bg_tex_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bg_tex_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bg_tex_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 6.22775 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bg_tex_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bg_tex_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bg_tex_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bg_tex_blk_mem_gen_v8_3_5 : entity is "bg_tex.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bg_tex_blk_mem_gen_v8_3_5 : entity is "bg_tex.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bg_tex_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bg_tex_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 11130;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 11130;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bg_tex_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bg_tex_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bg_tex_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bg_tex_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bg_tex_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bg_tex_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 11130;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 11130;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bg_tex_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bg_tex_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bg_tex_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bg_tex_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bg_tex_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_tex_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_tex_blk_mem_gen_v8_3_5 : entity is "yes";
end bg_tex_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bg_tex_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bg_tex_blk_mem_gen_v8_3_5_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_tex is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bg_tex : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bg_tex : entity is "bg_tex,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_tex : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bg_tex : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bg_tex;
architecture STRUCTURE of bg_tex is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "4";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 6.22775 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bg_tex.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bg_tex.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 11130;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 11130;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 11130;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 11130;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bg_tex_blk_mem_gen_v8_3_5
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => B"00000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.eth_config.all;
entity m_eth is
generic(
RAM_RD_CYCLE : natural := 2;
RAM_WR_CYCLE : natural := 2;
RAM_RD_DELAY : natural := 1 ; --1
RAM_AWIDTH : natural := 32
);
port(
txclk : in std_logic;
txd : out std_logic_vector(3 downto 0);
txen : out std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(3 downto 0);
rxdv : in std_logic;
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
TxFIFO_W_Clk : in std_logic;
TxFIFO_Clr : in std_logic;
TxFIFO_W_Block : in std_logic;
TxFIFO_WE : in std_logic;
TxFIFO_WAddr : in std_logic_vector( TX_TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
TxFIFO_WData : in std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
TxFIFO_Full : out std_logic;
RxFIFO_R_Clk : in std_logic;
RxFIFO_R_Block : in std_logic;
RxFIFO_RAddr : in std_logic_vector( RX_TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
RxFIFO_RData : out std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
RxFIFO_Empty : out std_logic;
localtime : in std_logic_vector(31 downto 0);
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked: out std_logic;
----------------------------------------------
debugIO_port_id : out std_logic_vector(15 downto 0);
debugIO_write_strobe: out std_logic;
debugIO_out_port : out std_logic_vector(15 downto 0);
debugIO_read_strobe : out std_logic;
debugIO_in_port : in std_logic_vector(15 downto 0);
progIO_id : out std_logic_vector(3 downto 0);
progIO_reset : out std_logic;
progIO_wren : out std_logic;
progIO_addr : out std_logic_vector(9 downto 0);
progIO_wdata : out std_logic_vector(15 downto 0);
progIO_rdata : in std_logic_vector(15 downto 0);
------------------------------------------------------------------------
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_wdata : out std_logic_vector(15 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_rdata : in std_logic_vector(15 downto 0);
--
test : out std_logic_vector(1 downto 0);
s_HighPri_Tx_Req : in std_logic;
m48_HighPri_Tx_Req_DesMac : in std_logic_vector( 47 downto 0 );
m16_HighPri_Tx_Req_Addr : in std_logic_vector( 15 downto 0 );
m16_HighPri_Tx_Req_Data : in std_logic_vector( 15 downto 0 );
local_id_MAC0_Req : in std_logic_vector(7 downto 0);
local_id_MAC0_A : in std_logic_vector(7 downto 0);
local_id_MAC0_B : in std_logic_vector(7 downto 0);
local_id : in std_logic_vector(39 downto 0)
);
end entity;
architecture arch_eth of m_eth is
component ethrx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 12;
FIFO_AWIDTH : NATURAL := 2;
WR_CYCLE : NATURAL := 1;
RAM_AWIDTH : NATURAL :=32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(3 downto 0);
rxdv : in std_logic;
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
eth_dma_ce : in std_logic;
ethrx_busy : out std_logic;
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked : out std_logic;
lastframe_flag : out std_logic;
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
---------------
-- test : out std_logic_vector(3 downto 0);
ram_wdata : out std_logic_vector(15 downto 0));
end component;
component ethrx_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end component;
component ethrx_task
generic(
TASKFIFO_DWIDTH : natural := 8;
TASKFIFO_BLOCK_DEPTH : natural := 8;
TASKFIFO_BLOCK_AWIDTH : natural := 3;
TASKFIFO_DEPTH : natural := 16;
TASKFIFO_AWIDTH : natural := 4;
TASKFIFO_RAM_TYPE : string := "DIS_RAM"
);
port(
reset : in std_logic;
-- Task Input
RxFIFO_R_Clk : in std_logic;
RxFIFO_R_Block : in std_logic;
RxFIFO_RAddr : in std_logic_vector( TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
RxFIFO_RData : out std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
RxFIFO_Full : out std_logic;
RxFIFO_Empty : out std_logic;
fifo_wr_block : in std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end component;
component dma2rxtask
port(
reset : in std_logic;
zcpsm_clk : in std_logic;
busy : in std_logic;
lastframe : in std_logic;
rxtask_wr_block : out std_logic
);
end component;
component asyncwrite
port(
reset : in std_logic;
async_clk : in std_logic;
sync_clk : in std_logic;
async_wren : in std_logic;
trigger : in std_logic;
sync_wren : out std_logic;
over : out std_logic;
flag : out std_logic);
end component;
component ethtx
generic(
HEAD_AWIDTH : NATURAL := 5;
BUFF_AWIDTH : NATURAL := 5;
FIFO_AWIDTH : NATURAL := 2;
RD_CYCLE : NATURAL := 1;
RD_DELAY : NATURAL := 1;
RAM_AWIDTH : NATURAL := 32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(3 downto 0);
txen : out std_logic;
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
ram_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
ram_rdata : in std_logic_vector(15 downto 0);
-- localtime --
localtime : in std_logic_vector(31 downto 0)
);
end component;
component ethtx_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end component;
component ethtx_task
generic(
TASKFIFO_DWIDTH : natural := 8;
TASKFIFO_BLOCK_DEPTH : natural := 16;
TASKFIFO_BLOCK_AWIDTH : natural := 4;
TASKFIFO_DEPTH : natural := 16;
TASKFIFO_AWIDTH : natural := 4;
TASKFIFO_RAM_TYPE : string := "DIS_RAM"
);
port(
reset : in std_logic;
-- Task Input
TxFIFO_W_Clk : in std_logic;
TxFIFO_Clr : in std_logic;
TxFIFO_W_Block : in std_logic;
TxFIFO_WE : in std_logic;
TxFIFO_WAddr : in std_logic_vector( TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
TxFIFO_WData : in std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
TxFIFO_Full : out std_logic;
TxFIFO_Empty : out std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end component;
component Eth_Tx_HighPriority
port(
reset : in std_logic;
clk : in std_logic;
clk_zcpsm : in std_logic;
s_Tx_Req : in std_logic;
m48_Tx_Req_DesMac : in std_logic_vector( 47 downto 0 );
m16_Tx_Req_Addr : in std_logic_vector( 15 downto 0 );
m16_Tx_Req_Data : in std_logic_vector( 15 downto 0 );
port_id : in std_logic_vector(7 downto 0);
write_strobe : in std_logic;
out_port : in std_logic_vector(7 downto 0);
read_strobe : in std_logic;
in_port : out std_logic_vector(7 downto 0)
);
end component;
component db_zcpsm
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0));
end component;
component zcpsmIO2bus16
port(
reset : in std_logic;
debug_port_id : out std_logic_vector(15 downto 0);
debug_write_strobe : out std_logic;
debug_out_port : out std_logic_vector(15 downto 0);
debug_read_strobe : out std_logic;
debug_in_port : in std_logic_vector(15 downto 0);
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0));
end component;
component zcpsmDecode
port (
port_id_H : in std_logic_vector(3 downto 0);
ce : out std_logic_vector(15 downto 0)
);
end component;
component macAddrConfig
port (
ethtx_port_id : in std_logic_vector(7 downto 0);
ethrx_port_id : in std_logic_vector(7 downto 0);
db_port_id : in std_logic_vector(7 downto 0);
local_id_MAC0_Req : in std_logic_vector(7 downto 0);
local_id_MAC0_A : in std_logic_vector(7 downto 0);
local_id_MAC0_B : in std_logic_vector(7 downto 0);
local_id : in std_logic_vector(39 downto 0);
ethtx_in_port : out std_logic_vector(7 downto 0);
ethrx_in_port : out std_logic_vector(7 downto 0);
db_in_port : out std_logic_vector(7 downto 0)
);
end component;
signal ethrx_port_id : std_logic_vector(7 downto 0);
signal ethrx_write_strobe : std_logic;
signal ethrx_out_port : std_logic_vector(7 downto 0);
signal ethrx_read_strobe : std_logic;
signal ethrx_in_port : std_logic_vector(7 downto 0);
signal ethtx_port_id : std_logic_vector(7 downto 0);
signal ethtx_write_strobe : std_logic;
signal ethtx_out_port : std_logic_vector(7 downto 0);
signal ethtx_read_strobe : std_logic;
signal ethtx_in_port : std_logic_vector(7 downto 0);
signal db_port_id : std_logic_vector(7 downto 0);
signal db_write_strobe : std_logic;
signal db_out_port : std_logic_vector(7 downto 0);
signal db_read_strobe : std_logic;
signal db_in_port : std_logic_vector(7 downto 0);
signal debug_port_id : std_logic_vector(15 downto 0);
signal debug_write_strobe : std_logic;
signal debug_out_port : std_logic_vector(15 downto 0);
signal debug_read_strobe : std_logic;
signal debug_in_port : std_logic_vector(15 downto 0);
signal debug_in_port_pro : std_logic_vector(15 downto 0);
signal lastframe_flag : std_logic;
signal ethrx_busy : std_logic;
signal rxtask_wr_block : std_logic;
signal rxtask_wr_block_Reg : std_logic;
signal ethtx_task_ce : std_logic;
signal eth_tx_ce : std_logic;
signal eth_rx_ce : std_logic;
signal eth_rxdma_ce : std_logic;
signal ethrx_task_ce : std_logic;
signal db_rx_ce : std_logic;
signal db_tx_ce : std_logic;
signal db_debug_ce : std_logic;
signal txen_buf : std_logic;
signal db_ce : std_logic_vector(15 downto 0);
signal ethtx_ce : std_logic_vector(15 downto 0);
signal ethrx_ce : std_logic_vector(15 downto 0);
begin
test(0) <= not rxdv;
test(1) <= not txen_buf;
------------------------------------------------------------------------------
-- RX
------------------------------------------------------------------------------
u_rx : ethrx
generic map(
HEAD_AWIDTH => ETHRX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHRX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHRX_FIFO_AWIDTH,
WR_CYCLE => RAM_WR_CYCLE,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
rxclk => rxclk,
rxd => rxd,
rxdv => rxdv,
db_ce => db_rx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_rx_ce,
eth_port_id => ethrx_port_id(3 downto 0),
eth_write_strobe => ethrx_write_strobe,
eth_out_port => ethrx_out_port,
eth_read_strobe => ethrx_read_strobe,
eth_in_port => ethrx_in_port,
eth_dma_ce => eth_rxdma_ce,
ethrx_busy => ethrx_busy,
recvtime => recvtime,
recvtime_valid => recvtime_valid,
localtime_locked => localtime_locked,
lastframe_flag => lastframe_flag,
ram_wren => ram_wren,
ram_waddr => ram_waddr,
-----
ram_wdata => ram_wdata
);
-- db_rx_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_RX else '0';
-- eth_rx_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RX else '0';
-- eth_rxdma_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RXDMA else '0';
db_rx_ce <= db_ce(conv_integer(PORTS_DB_RX));
eth_rx_ce <= ethrx_ce(conv_integer(PORTS_ETH_RX));
eth_rxdma_ce <= ethrx_ce(conv_integer(PORTS_ETH_RXDMA));
u_ethrx_zcpsm : ethrx_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => ethrx_port_id,
write_strobe => ethrx_write_strobe,
out_port => ethrx_out_port,
read_strobe => ethrx_read_strobe,
in_port => ethrx_in_port
);
u_ethrx_zcpsm_ce : zcpsmDecode
port map(
port_id_H => ethrx_port_id( 7 downto 4),
ce => ethrx_ce
);
u_ethrx_task : ethrx_task
generic map (
TASKFIFO_DWIDTH => TASKFIFO_DWIDTH,
TASKFIFO_BLOCK_DEPTH => RX_TASKFIFO_BLOCK_DEPTH,
TASKFIFO_BLOCK_AWIDTH => RX_TASKFIFO_BLOCK_AWIDTH,
TASKFIFO_DEPTH => RX_TASKFIFO_DEPTH,
TASKFIFO_AWIDTH => RX_TASKFIFO_AWIDTH,
TASKFIFO_RAM_TYPE => RX_TASKFIFO_RAM_TYPE
)
port map(
reset => reset,
-- Task Input
RxFIFO_R_Clk => RxFIFO_R_Clk,
RxFIFO_R_Block => RxFIFO_R_Block,
RxFIFO_RAddr => RxFIFO_RAddr,
RxFIFO_RData => RxFIFO_RData,
RxFIFO_Full => open,
-- RxFIFO_Full => RxFIFO_Full,
RxFIFO_Empty => RxFIFO_Empty,
fifo_wr_block => rxtask_wr_block,
-- zcpsm
zcpsm_clk => zcpsm_clk,
zcpsm_ce => ethrx_task_ce,
zcpsm_port_id => ethrx_port_id(3 downto 0),
zcpsm_write_strobe => ethrx_write_strobe,
zcpsm_out_port => ethrx_out_port,
zcpsm_read_strobe => ethrx_read_strobe,
zcpsm_in_port => ethrx_in_port
);
-- ethrx_task_ce <= '1' when ethrx_port_id(7 downto 4) = PORTS_ETH_RX_TASK else '0';
ethrx_task_ce <= ethrx_ce(conv_integer(PORTS_ETH_RX_TASK));
u_dma2rxtask: dma2rxtask
port map(
reset => reset,
zcpsm_clk => zcpsm_clk,
busy => ethrx_busy,
lastframe => lastframe_flag,
rxtask_wr_block => rxtask_wr_block_Reg
);
-- ethrx_in_port <= local_id_MAC0_A when ethrx_port_id = PORT_ETH_LOCAL_ID_0_A else
-- local_id_MAC0_B when ethrx_port_id = PORT_ETH_LOCAL_ID_0_B else
-- local_id( 39 downto 32 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_1 else
-- local_id( 31 downto 24 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_2 else
-- local_id( 23 downto 16 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_3 else
-- local_id( 15 downto 8 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_4 else
-- local_id( 7 downto 0 ) when ethrx_port_id = PORT_ETH_LOCAL_ID_5 else
-- (others => 'Z');
u_wr_block : asyncwrite -- rxtask_wr_block must be synchronized with clk
port map(
reset => reset,
async_clk => zcpsm_clk,
sync_clk => clk,
async_wren => rxtask_wr_block_Reg,
trigger => '1',
sync_wren => rxtask_wr_block,
over => open,
flag => open
);
------------------------------------------------------------------------------
-- TX
------------------------------------------------------------------------------
u_tx : ethtx
generic map(
HEAD_AWIDTH => ETHTX_HEAD_AWIDTH,
BUFF_AWIDTH => ETHTX_BUFF_AWIDTH,
FIFO_AWIDTH => ETHTX_FIFO_AWIDTH,
RD_CYCLE => RAM_RD_CYCLE,
RD_DELAY => RAM_RD_DELAY,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
zcpsm_clk => zcpsm_clk,
reset => reset,
txclk => txclk,
txd => txd,
txen => txen_buf,
db_ce => db_tx_ce,
db_port_id => db_port_id(3 downto 0),
db_write_strobe => db_write_strobe,
db_out_port => db_out_port,
db_read_strobe => db_read_strobe,
db_in_port => db_in_port,
eth_ce => eth_tx_ce,
eth_port_id => ethtx_port_id(3 downto 0),
eth_write_strobe => ethtx_write_strobe,
eth_out_port => ethtx_out_port,
eth_read_strobe => ethtx_read_strobe,
eth_in_port => ethtx_in_port,
ram_raddr => ram_raddr,
ram_rdata => ram_rdata,
-- local time--
localtime => localtime
);
txen <= txen_buf;
-- db_tx_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_TX else '0';
-- eth_tx_ce <= '1' when ethtx_port_id(7 downto 4) = PORTS_ETH_TX else '0';
db_tx_ce <= db_ce(conv_integer(PORTS_DB_TX));
eth_tx_ce <= ethtx_ce(conv_integer(PORTS_ETH_TX));
-- eth tx zcpsm
u_ethtx_zcpsm : ethtx_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => ethtx_port_id,
write_strobe => ethtx_write_strobe,
out_port => ethtx_out_port,
read_strobe => ethtx_read_strobe,
in_port => ethtx_in_port
);
u_ethtx_zcpsm_ce : zcpsmDecode
port map(
port_id_H => ethtx_port_id( 7 downto 4),
ce => ethtx_ce
);
mo_Eth_Tx_HighPriority : Eth_Tx_HighPriority
port map(
reset => reset,
clk => clk,
clk_zcpsm => zcpsm_clk,
s_Tx_Req => s_HighPri_Tx_Req,
m48_Tx_Req_DesMac => m48_HighPri_Tx_Req_DesMac,
m16_Tx_Req_Addr => m16_HighPri_Tx_Req_Addr,
m16_Tx_Req_Data => m16_HighPri_Tx_Req_Data,
port_id => ethtx_port_id,
write_strobe => ethtx_write_strobe,
out_port => ethtx_out_port,
read_strobe => ethtx_read_strobe,
in_port => ethtx_in_port
);
u_ethtx_task : ethtx_task
generic map(
TASKFIFO_DWIDTH => TASKFIFO_DWIDTH,
TASKFIFO_BLOCK_DEPTH => TX_TASKFIFO_BLOCK_DEPTH,
TASKFIFO_BLOCK_AWIDTH => TX_TASKFIFO_BLOCK_AWIDTH,
TASKFIFO_DEPTH => TX_TASKFIFO_DEPTH,
TASKFIFO_AWIDTH => TX_TASKFIFO_AWIDTH,
TASKFIFO_RAM_TYPE => TX_TASKFIFO_RAM_TYPE
)
port map(
reset => reset,
-- Task Input
TxFIFO_W_Clk => TxFIFO_W_Clk,
TxFIFO_Clr => TxFIFO_Clr,
TxFIFO_W_Block => TxFIFO_W_Block,
TxFIFO_WE => TxFIFO_WE,
TxFIFO_WAddr => TxFIFO_WAddr,
TxFIFO_WData => TxFIFO_WData,
TxFIFO_Full => TxFIFO_Full,
-- TxFIFO_Empty => TxFIFO_Empty,
TxFIFO_Empty => open,
-- zcpsm
zcpsm_clk => zcpsm_clk,
zcpsm_ce => ethtx_task_ce,
zcpsm_port_id => ethtx_port_id(3 downto 0),
zcpsm_write_strobe => ethtx_write_strobe,
zcpsm_out_port => ethtx_out_port,
zcpsm_read_strobe => ethtx_read_strobe,
zcpsm_in_port => ethtx_in_port
);
-- ethtx_task_ce <= '1' when ethtx_port_id(7 downto 4) = PORTS_ETH_TX_TASK else '0';
ethtx_task_ce <= ethtx_ce(conv_integer(PORTS_ETH_TX_TASK));
-- ethtx_in_port <= local_id_MAC0_Req when ethtx_port_id = PORT_ETH_LOCAL_ID_0_REQ else
-- local_id_MAC0_A when ethtx_port_id = PORT_ETH_LOCAL_ID_0_A else
-- local_id_MAC0_B when ethtx_port_id = PORT_ETH_LOCAL_ID_0_B else
-- local_id( 39 downto 32 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_1 else
-- local_id( 31 downto 24 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_2 else
-- local_id( 23 downto 16 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_3 else
-- local_id( 15 downto 8 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_4 else
-- local_id( 7 downto 0 ) when ethtx_port_id = PORT_ETH_LOCAL_ID_5 else
-- (others => 'Z');
------------------------------------------------------------------------------
-- DB zcpsm
------------------------------------------------------------------------------
u_db_zcpsm : db_zcpsm
port map(
reset => reset,
clk => zcpsm_clk,
port_id => db_port_id,
write_strobe => db_write_strobe,
out_port => db_out_port,
read_strobe => db_read_strobe,
in_port => db_in_port
);
u_db_zcpsm_ce : zcpsmDecode
port map(
port_id_H => db_port_id( 7 downto 4),
ce => db_ce
);
------------------------------------------------------------------------------
-- DEBUG & PROG
------------------------------------------------------------------------------
u_zcpsmIO2bus16 : zcpsmIO2bus16
port map(
reset => reset,
zcpsm_clk => zcpsm_clk,
debug_port_id => debug_port_id,
debug_write_strobe => debug_write_strobe,
debug_out_port => debug_out_port,
debug_read_strobe => debug_read_strobe,
debug_in_port => debug_in_port,
zcpsm_ce => db_debug_ce,
zcpsm_port_id => db_port_id(3 downto 0),
zcpsm_write_strobe => db_write_strobe,
zcpsm_out_port => db_out_port,
zcpsm_read_strobe => db_read_strobe,
zcpsm_in_port => db_in_port
);
-- db_debug_ce <= '1' when db_port_id(7 downto 4) = PORTS_DB_DEBUG else '0';
db_debug_ce <= db_ce(conv_integer(PORTS_DB_DEBUG));
------------------------------------------------------------------------------
-- IO
------------------------------------------------------------------------------
debugIO_port_id <= debug_port_id;
debugIO_write_strobe<= debug_write_strobe;
debugIO_out_port <= debug_out_port;
debugIO_read_strobe <= debug_read_strobe;
debug_in_port <= debug_in_port_pro when debug_port_id(15 downto 12) = PORTS_DEBUG_PROG else
debugIO_in_port;
------------------------------------------------------------------------------
-- LOCAL ID
------------------------------------------------------------------------------
-- db_in_port <= local_id_MAC0_A when db_port_id = PORT_DB_LOCAL_ID_0_A else
-- local_id_MAC0_B when db_port_id = PORT_DB_LOCAL_ID_0_B else
-- local_id( 39 downto 32 ) when db_port_id = PORT_DB_LOCAL_ID_1 else
-- local_id( 31 downto 24 ) when db_port_id = PORT_DB_LOCAL_ID_2 else
-- local_id( 23 downto 16 ) when db_port_id = PORT_DB_LOCAL_ID_3 else
-- local_id( 15 downto 8 ) when db_port_id = PORT_DB_LOCAL_ID_4 else
-- local_id( 7 downto 0 ) when db_port_id = PORT_DB_LOCAL_ID_5 else
-- (others => 'Z');
u_macAddr : macAddrConfig
port map(
ethtx_port_id => ethtx_port_id,
ethrx_port_id => ethrx_port_id,
db_port_id => db_port_id,
local_id_MAC0_Req => local_id_MAC0_Req,
local_id_MAC0_A => local_id_MAC0_A,
local_id_MAC0_B => local_id_MAC0_B,
local_id => local_id,
ethtx_in_port => ethtx_in_port,
ethrx_in_port => ethrx_in_port,
db_in_port => db_in_port
);
end arch_eth;
|
----------------------------------------------------------------------------------
-- axi_dispctrl.vhd - entity/architecture pair
----------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
----------------------------------------------------------------------------------
--
-- *******************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- *******************************************************************************
--
----------------------------------------------------------------------------------
-- Filename: axi_dispctrl.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Sat Sep 28 10:06:38 2013 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
----------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_dispctrl_v1_00_a;
use axi_dispctrl_v1_00_a.user_logic;
----------------------------------------------------------------------------------
-- Entity section
----------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity axi_dispctrl is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_USE_BUFR_DIV5 : integer := 0;
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
-- Parameters of Axi Slave Bus Interface S_AXIS_MM2S
C_S_AXIS_MM2S_TDATA_WIDTH : integer := 32;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
S_AXIS_ACLK : in STD_LOGIC; --not currently used
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : OUT std_logic;
RED_O : OUT std_logic_vector(7 downto 0);
GREEN_O : OUT std_logic_vector(7 downto 0);
BLUE_O : OUT std_logic_vector(7 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0);
ENABLE_O : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_dispctrl;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_dispctrl is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 13;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity axi_dispctrl_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
C_USE_BUFR_DIV5 => C_USE_BUFR_DIV5,
C_RED_WIDTH => C_RED_WIDTH,
C_GREEN_WIDTH => C_GREEN_WIDTH,
C_BLUE_WIDTH => C_BLUE_WIDTH,
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_MM2S_TDATA_WIDTH,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
REF_CLK_I => REF_CLK_I,
PXL_CLK_O => PXL_CLK_O,
VDMA_CLK_O => VDMA_CLK_O,
PXL_CLK_5X_O => PXL_CLK_5X_O,
LOCKED_O => LOCKED_O,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
FSYNC_O => FSYNC_O,
DEBUG_O => DEBUG_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
BLUE_O => BLUE_O,
ENABLE_O => ENABLE_O,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
----------------------------------------------------------------------------------
-- axi_dispctrl.vhd - entity/architecture pair
----------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
----------------------------------------------------------------------------------
--
-- *******************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- *******************************************************************************
--
----------------------------------------------------------------------------------
-- Filename: axi_dispctrl.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Sat Sep 28 10:06:38 2013 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
----------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_dispctrl_v1_00_a;
use axi_dispctrl_v1_00_a.user_logic;
----------------------------------------------------------------------------------
-- Entity section
----------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity axi_dispctrl is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_USE_BUFR_DIV5 : integer := 0;
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
-- Parameters of Axi Slave Bus Interface S_AXIS_MM2S
C_S_AXIS_MM2S_TDATA_WIDTH : integer := 32;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
S_AXIS_ACLK : in STD_LOGIC; --not currently used
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : OUT std_logic;
RED_O : OUT std_logic_vector(7 downto 0);
GREEN_O : OUT std_logic_vector(7 downto 0);
BLUE_O : OUT std_logic_vector(7 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0);
ENABLE_O : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_dispctrl;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_dispctrl is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 13;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity axi_dispctrl_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
C_USE_BUFR_DIV5 => C_USE_BUFR_DIV5,
C_RED_WIDTH => C_RED_WIDTH,
C_GREEN_WIDTH => C_GREEN_WIDTH,
C_BLUE_WIDTH => C_BLUE_WIDTH,
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_MM2S_TDATA_WIDTH,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
REF_CLK_I => REF_CLK_I,
PXL_CLK_O => PXL_CLK_O,
VDMA_CLK_O => VDMA_CLK_O,
PXL_CLK_5X_O => PXL_CLK_5X_O,
LOCKED_O => LOCKED_O,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
FSYNC_O => FSYNC_O,
DEBUG_O => DEBUG_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
BLUE_O => BLUE_O,
ENABLE_O => ENABLE_O,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
----------------------------------------------------------------------------------
-- axi_dispctrl.vhd - entity/architecture pair
----------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
----------------------------------------------------------------------------------
--
-- *******************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- *******************************************************************************
--
----------------------------------------------------------------------------------
-- Filename: axi_dispctrl.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Sat Sep 28 10:06:38 2013 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
----------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_dispctrl_v1_00_a;
use axi_dispctrl_v1_00_a.user_logic;
----------------------------------------------------------------------------------
-- Entity section
----------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity axi_dispctrl is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_USE_BUFR_DIV5 : integer := 0;
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
-- Parameters of Axi Slave Bus Interface S_AXIS_MM2S
C_S_AXIS_MM2S_TDATA_WIDTH : integer := 32;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
VDMA_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
S_AXIS_ACLK : in STD_LOGIC; --not currently used
S_AXIS_ARESETN : in std_logic;
S_AXIS_TDATA : in STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TVALID : in STD_LOGIC;
S_AXIS_TLAST : in std_logic;
S_AXIS_TREADY : out STD_LOGIC;
FSYNC_O : OUT std_logic;
HSYNC_O : OUT std_logic;
VSYNC_O : OUT std_logic;
DE_O : OUT std_logic;
RED_O : OUT std_logic_vector(7 downto 0);
GREEN_O : OUT std_logic_vector(7 downto 0);
BLUE_O : OUT std_logic_vector(7 downto 0);
DEBUG_O : out std_logic_vector(31 downto 0);
ENABLE_O : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_dispctrl;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_dispctrl is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 13;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity axi_dispctrl_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
C_USE_BUFR_DIV5 => C_USE_BUFR_DIV5,
C_RED_WIDTH => C_RED_WIDTH,
C_GREEN_WIDTH => C_GREEN_WIDTH,
C_BLUE_WIDTH => C_BLUE_WIDTH,
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_MM2S_TDATA_WIDTH,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
REF_CLK_I => REF_CLK_I,
PXL_CLK_O => PXL_CLK_O,
VDMA_CLK_O => VDMA_CLK_O,
PXL_CLK_5X_O => PXL_CLK_5X_O,
LOCKED_O => LOCKED_O,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_ARESETN => S_AXIS_ARESETN,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TSTRB => S_AXIS_TSTRB,
S_AXIS_TVALID => S_AXIS_TVALID,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TREADY => S_AXIS_TREADY,
FSYNC_O => FSYNC_O,
DEBUG_O => DEBUG_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
BLUE_O => BLUE_O,
ENABLE_O => ENABLE_O,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY fifo_generator_input_buffer IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END fifo_generator_input_buffer;
ARCHITECTURE fifo_generator_input_buffer_arch OF fifo_generator_input_buffer IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_input_buffer_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 12,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx9",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 4093,
C_PROG_FULL_THRESH_NEGATE_VAL => 4092,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 12,
C_WR_DEPTH => 4096,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 12,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_input_buffer_arch;
|
`protect begin_protected
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20336)
`protect data_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect end_protected
|
-------------------------------------------------------------------------------
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, if-then-else, block, function, procedure, component.
entity ENT00001 is
port (
rst : in bit;
clk : in bit;
shift_toggle : in bit;
add_op1 : in bit_vector(3 downto 0);
add_op2 : in bit_vector(3 downto 0);
mul_op : in integer;
result : out bit_vector(3 downto 0)
);
end ENT00001;
architecture ARCH00001 of ENT00001 is
-- simple summator with l'size = r'size without size'controll
function add_bit_vector (l,r : bit_vector) return bit_vector is
variable left : bit_vector(l'length-1 downto 0);
variable right : bit_vector(r'length-1 downto 0);
variable res : bit_vector(l'length-1 downto 0);
variable c : bit_vector(l'length downto 0);
begin
left := l;
right := r;
c(0) := '0';
sum_loop: for i in 0 to res'length-1 loop
res(i) := (left(i) xor right(i)) xor c(i);
c(i+1) := ((left(i) xor right(i)) and c(i)) or (left(i) and right(i));
end loop;
return res;
end function add_bit_vector;
function strange_mul (op : bit_vector; multiplier : integer) return bit_vector is
variable v : bit_vector(op'length-1 downto 0);
variable r : bit_vector(op'length-1 downto 0);
begin
v := op;
r := v;
if multiplier > 1 then
mul_loop: for i in 1 to multiplier-1 loop
r := add_bit_vector(r, v);
end loop;
end if;
return r;
end strange_mul;
procedure recurse (num : integer) is
begin
if num > 0 then
recurse(num-1);
end if;
end recurse;
signal result_for_shift, result_t, result_asyn : bit_vector(3 downto 0);
signal shift_en_tst : bit;
signal shift_en_tst_clk, shift_toggle_clk : bit_vector(1 downto 0);
begin
async_logic: process(add_op1, add_op2, mul_op, shift_toggle, result_t)
variable vres : bit_vector(3 downto 0);
variable sum : bit_vector(3 downto 0);
begin
vres := result_t;
sum := add_bit_vector(add_op1,add_op2);
if shift_toggle = '0' then
vres := strange_mul(sum, mul_op);
end if;
result_for_shift <= vres;
recurse(5);
end process;
shift: process (shift_toggle, result_for_shift)
variable vout : bit_vector(3 downto 0);
begin
vout := result_for_shift;
if shift_toggle = '1' then
vout := vout(2 downto 0) & '0';
end if;
-- result_asyn <= vout;
end process;
shift_block : block
port (
input : in bit_vector(3 downto 0)
; shift_en : in bit
; shift_en_out : out bit
; output : out bit_vector(3 downto 0)
);
port map (
input => result_for_shift
, shift_en => shift_toggle
, shift_en_out => shift_en_tst
, output => result_asyn
);
signal output_t : bit_vector(3 downto 0);
function shiftZeroFunc (x : bit_vector) return bit_vector is
variable v, r : bit_vector(x'length-1 downto 0);
begin
v := x;
r := v(v'high-1 downto 0) & '0';
return r;
end function;
procedure bufXOut4 (bi : in bit_vector(3 downto 0); bo : out bit_vector(3 downto 0)) is
begin
bo(0) := bi(3);
bo(1) := bi(2);
bo(2) := bi(1);
bo(3) := bi(0);
end procedure;
begin
shift_en_out <= shift_en;
output <= output_t;
process (input, shift_en)
variable vout : bit_vector(3 downto 0);
variable voutX : bit_vector(3 downto 0);
begin
vout := input;
if shift_en = '1' then
vout := shiftZeroFunc(vout);
end if;
bufXOut4(vout(3 downto 0), voutX);
output_t(3 downto 0) <= voutX after 0.2 us;
end process;
end block shift_block;
result <= result_t;
sync: process (rst, clk)
begin
if rst = '1' then
result_t <= x"0";
shift_en_tst_clk <= "00";
shift_toggle_clk <= "00";
elsif clk'event and clk = '1' then
result_t <= result_asyn;
shift_en_tst_clk <= shift_en_tst_clk(0) & shift_en_tst;
shift_toggle_clk <= shift_toggle_clk(0) & shift_toggle;
assert shift_en_tst_clk(1) = shift_toggle_clk(1)
report "Input shift_toggle is not transmit to input port shift_en of the block 'shift_block'"
severity FAILURE;
end if;
end process;
end;
entity ENT00001_Test_Bench is
end ENT00001_Test_Bench;
architecture ARCH00001_Test_Bench of ENT00001_Test_Bench is
-- Component declaration of the tested unit
component ENT00001
port(
rst : in bit;
clk : in bit;
shift_toggle : in bit;
add_op1 : in bit_vector(3 downto 0);
add_op2 : in bit_vector(3 downto 0);
mul_op : in integer;
result : out bit_vector(3 downto 0) );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal rst : bit;
signal clk : bit := '0';
signal shift_toggle : bit := '0';
signal add_op1 : bit_vector(3 downto 0);
signal add_op2 : bit_vector(3 downto 0);
signal mul_op : integer;
-- Observed signals - signals mapped to the output ports of tested entity
signal result : bit_vector(3 downto 0);
-- Add your code here ...
begin
-- Unit Under Test port map
UUT : ENT00001
port map (
rst => rst,
clk => clk,
shift_toggle => shift_toggle,
add_op1 => add_op1,
add_op2 => add_op2,
mul_op => mul_op,
result => result
);
-- Add your stimulus here ...
process (clk)
variable init : boolean := true;
variable done : boolean := false;
begin
if init then
rst <= '1';
init := false;
elsif clk'event and clk = '1' then
if not done then
done := true;
rst <= '0';
end if;
end if;
end process;
clk <= not clk after 1 us;
shift_toggle <= not shift_toggle after 20 us;
add_op1 <= x"1";
add_op2 <= x"2";
mul_op <= 2;
end ARCH00001_Test_Bench;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_7series_ddr2_dq16_ad13_ba3
-- File: ahb2mig_7series_ddr2.vhd
-- Author: Pascal Trotta
--
-- This is a AHB-2.0 interface for the Xilinx Virtex-7 MIG. (adapted from
-- ahb2mig_7series to work with 16-bit ddr2 memories)
-- Notes: - works only with 32-bit bus
-- - does not replicate output data
-- - does not support MIG interface model
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.all;
use gaisler.ahb2mig_7series_pkg.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.config_types.all;
use grlib.config.all;
library std;
use std.textio.all;
entity ahb2mig_7series_ddr2_dq16_ad13_ba3 is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
maxwriteburst : integer := 8;
maxreadburst : integer := 8;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_reset_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_i : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end ;
architecture rtl of ahb2mig_7series_ddr2_dq16_ad13_ba3 is
type bstate_type is (idle, start, read_cmd, read_data, read_wait, read_output, write_cmd, write_burst);
constant maxburst : integer := 8;
constant maxmigcmds : integer := 3;
constant wrsteps : integer := log2(32);
constant wrmask : integer := log2(32/8);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd : std_logic_vector(2 downto 0);
cmd_en : std_logic;
wr_en : std_logic;
wr_end : std_logic;
cmd_count : unsigned(31 downto 0);
wr_count : unsigned(31 downto 0);
rd_count : unsigned(31 downto 0);
hready : std_logic;
hwrite : std_logic;
hwdata_burst : std_logic_vector(128*maxmigcmds-1 downto 0);
mask_burst : std_logic_vector(16*maxmigcmds-1 downto 0);
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(31 downto 0);
haddr_start : std_logic_vector(31 downto 0);
haddr_offset : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
int_buffer : unsigned(128*maxmigcmds-1 downto 0);
rd_buffer : unsigned(128*maxmigcmds-1 downto 0);
wdf_data_buffer : std_logic_vector(127 downto 0);
wdf_mask_buffer : std_logic_vector(15 downto 0);
migcommands : integer;
nxt : std_logic;
maxrburst : integer;
end record;
type mig_in_type is record
app_addr : std_logic_vector(26 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
app_wdf_data : std_logic_vector(127 downto 0);
app_wdf_end : std_logic;
app_wdf_mask : std_logic_vector(15 downto 0);
app_wdf_wren : std_logic;
end record;
type mig_out_type is record
app_rd_data : std_logic_vector(127 downto 0);
app_rd_data_end : std_logic;
app_rd_data_valid : std_logic;
app_rdy : std_logic;
app_wdf_rdy : std_logic;
end record;
signal rin, r, rnxt, rnxtin : reg_type;
signal migin : mig_in_type;
signal migout,migoutraw : mig_out_type;
component mig is
port (
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
sys_clk_i : in std_logic;
clk_ref_i : in std_logic;
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(127 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(15 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(127 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
sys_rst : in std_logic
);
end component mig;
begin
comb: process( rst_n_syn, r, rin, ahbsi, migout )
-- Design temp variables
variable v,vnxt : reg_type;
variable writedata : std_logic_vector(255 downto 0);
variable wmask : std_logic_vector(AHBDW/4-1 downto 0);
variable shift_steps : natural;
variable hrdata_shift_steps : natural;
variable steps_write : unsigned(31 downto 0);
variable shift_steps_write : natural;
variable shift_steps_write_mask : natural;
variable startaddress : unsigned(v.haddr'length-1 downto 0);
variable start_address : std_logic_vector(v.haddr'length-1 downto 0);
variable step_offset : unsigned(steps_write'length-1 downto 0);
variable haddr_offset : unsigned(steps_write'length-1 downto 0);
begin
-- Make all register visible for the statemachine
v := r; vnxt := rnxt;
-- workout the start address in AHB2MIG buffer based upon
startaddress := resize(unsigned(unsigned(ahbsi.haddr(ahbsi.haddr'left-5 downto 4)) & "000"),startaddress'length);
-- Adjust offset in memory buffer
start_address := std_logic_vector(startaddress);
-- Workout local offset to be able to adust for warp-around
haddr_offset := unsigned(r.haddr_start) - unsigned(unsigned(r.haddr_offset(r.haddr_offset'length-1 downto 4))&"0000");
step_offset := resize(unsigned(haddr_offset(5 downto 4)&"00"),step_offset'length);
-- Fetch AMBA Commands
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready and not ahbsi.htrans(0)) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
vnxt.cmd_count:= (others => '0');
vnxt.wr_count := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.hrdata := (others => '0');
-- Clear old pointers and MIG command signals
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
-- Hold info regarding transaction and execute
vnxt.hburst := ahbsi.hburst;
vnxt.hwrite := ahbsi.hwrite;
vnxt.hsize := ahbsi.hsize;
vnxt.hmaster := ahbsi.hmaster;
vnxt.hready := '0';
vnxt.htrans := ahbsi.htrans;
vnxt.bstate := start;
vnxt.haddr := start_address;
vnxt.haddr_start := ahbsi.haddr;
vnxt.haddr_offset := ahbsi.haddr;
vnxt.cmd(2 downto 0) := (others => '0');
vnxt.cmd(0) := not ahbsi.hwrite;
if (r.bstate = idle) then vnxt.nxt := '0'; else vnxt.nxt := '1'; end if;
-- Clear some old stuff
vnxt.int_buffer := (others => '0');
vnxt.rd_buffer := (others => '0');
vnxt.wdf_data_buffer := (others => '0');
vnxt.wdf_mask_buffer := (others => '0');
end if;
case r.bstate is
when idle =>
-- Clear old pointers and MIG command signals
v.cmd := (others => '0');
v.cmd_en := '0';
v.wr_en := '0';
v.wr_end := '0';
v.hready := '1';
v.hwrite := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.rd_count := (others => '0');
vnxt.cmd := (others => '0');
vnxt.cmd_en := '0';
vnxt.wr_en := '0';
vnxt.wr_end := '0';
vnxt.hready := '1';
vnxt.hwrite := '0';
vnxt.hwdata_burst := (others => '0');
vnxt.mask_burst := (others => '0');
vnxt.rd_count := (others => '0');
vnxt.wr_count := (others => '0');
vnxt.cmd_count := (others => '0');
-- Check if this is a single or burst transfer (and not a BUSY transfer)
if (( ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready) = '1'
and (ahbsi.hwrite = '0' or ahbsi.hwrite = '1' )) then
-- Hold info regarding transaction and execute
v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite;
v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
v.htrans := ahbsi.htrans;
v.bstate := start;
v.haddr := start_address;
v.haddr_start := ahbsi.haddr;
v.haddr_offset := ahbsi.haddr;
v.cmd := (others => '0');
v.cmd(0) := not ahbsi.hwrite;
end if;
when start =>
v.migcommands := nbrmigcmds16(r.hwrite,r.hsize,ahbsi.htrans,step_offset,AHBDW);
-- Check if a write command shall be issued to the DDR3 memory
if r.hwrite = '1' then
wmask := (others => '0');
writedata := (others => '0');
if ((ahbsi.htrans /= HTRANS_SEQ) or ((ahbsi.htrans = HTRANS_SEQ) and (r.rd_count > 0) and (r.rd_count <= maxburst))) then
-- work out how many steps we need to shift the input
steps_write := ahbselectdatanoreplicastep16(r.haddr_start(7 downto 2),r.hsize(2 downto 0)) + step_offset;
shift_steps_write := to_integer(shift_left(steps_write,wrsteps));
shift_steps_write_mask := to_integer(shift_left(steps_write,wrmask));
-- generate mask for complete burst (only need to use addr[3:0])
wmask := ahbselectdatanoreplicamask(r.haddr_start(6 downto 0),r.hsize(2 downto 0));
v.mask_burst := r.mask_burst or std_logic_vector(shift_left(resize(unsigned(wmask), r.mask_burst'length),shift_steps_write_mask));
-- fetch all wdata before write to memory can begin (only supports upto 128bits i.e. addr[4:0]
writedata(AHBDW-1 downto 0) := ahbselectdatanoreplica(ahbsi.hwdata(AHBDW-1 downto 0),r.haddr_start(4 downto 0),r.hsize(2 downto 0));
v.hwdata_burst := r.hwdata_burst or std_logic_vector(shift_left(resize(unsigned(writedata),v.hwdata_burst'length),shift_steps_write));
v.haddr_start := ahbsi.haddr;
end if;
-- Check if this is a cont burst longer than internal buffer
if (ahbsi.htrans = HTRANS_SEQ) then
if (r.rd_count < maxburst-1) then
v.hready := '1';
else
v.hready := '0';
end if;
if (r.rd_count >= maxburst) then
if (r.htrans = HTRANS_SEQ) then
v.bstate := write_cmd;
end if;
v.htrans := ahbsi.htrans;
end if;
else
v.bstate := write_cmd;
v.htrans := ahbsi.htrans;
end if;
-- Else issue a read command when ready
else
if migout.app_rdy = '1' and migout.app_wdf_rdy = '1' then
v.cmd := "001";
v.bstate := read_cmd;
v.htrans := ahbsi.htrans;
v.cmd_count := to_unsigned(0,v.cmd_count'length);
end if;
end if;
when write_cmd =>
-- Check if burst has ended due to max size burst
if (ahbsi.htrans /= HTRANS_SEQ) then
v.htrans := (others => '0');
end if;
-- Stop when addr and write command is accepted by mig
if (r.wr_count >= r.migcommands) and (r.cmd_count >= r.migcommands) then
if (r.htrans /= HTRANS_SEQ) then
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
else
v.bstate := idle;
end if;
else -- Cont burst and work out new offset for next write command
v.bstate := write_burst;
v.hready := '1';
end if;
end if;
when write_burst =>
v.bstate := start;
v.hready := '0';
v.hwdata_burst := (others => '0');
v.mask_burst := (others => '0');
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
end if;
when read_cmd =>
v.hready := '0';
v.rd_count := (others => '0');
-- stop when read command is accepted ny mig.
if (r.cmd_count >= r.migcommands) then
v.bstate := read_data;
--v.int_buffer := (others => '0');
end if;
when read_data =>
-- We are not ready yet so issue a read command to the memory controller
v.hready := '0';
-- If read data is valid store data in buffers
if (migout.app_rd_data_valid = '1') then
v.rd_count := r.rd_count + 1;
-- Viviado seems to misinterpet the following shift construct and
-- therefore changed to a if-else statement
--v.int_buffer := r.int_buffer or shift_left( resize(unsigned(migout.app_rd_data),r.int_buffer'length),
-- to_integer(shift_left(r.rd_count,9)));
if (r.rd_count = 0) then
v.int_buffer(127 downto 0) := unsigned(migout.app_rd_data);
elsif (r.rd_count = 1) then
v.int_buffer(255 downto 128) := unsigned(migout.app_rd_data);
end if;
end if;
if (r.rd_count >= r.migcommands) then
v.rd_buffer := r.int_buffer;
v.bstate := read_output;
v.rd_count := to_unsigned(0,v.rd_count'length);
end if;
when read_output =>
-- Data is fetched from memory and ready to be transfered
v.hready := '1';
-- uses the "wr_count" signal to keep track of number of bytes output'd to AHB
-- Select correct 32bit output
v.hrdata := ahbselectdatanoreplicaoutput16(r.haddr_start(7 downto 0),r.wr_count,r.hsize,r.rd_buffer,r.wr_count,false);
-- Count number of bytes send
v.wr_count := r.wr_count + 1;
-- Set maximum read burst depending on the starting address offset
case r.haddr_start(3 downto 2) is
when "01" => v.maxrburst := 7;
when "10" => v.maxrburst := 6;
when "11" => v.maxrburst := 5;
when others => v.maxrburst := 8;
end case;
-- Check if this was the last transaction
if (r.wr_count >= v.maxrburst-1) then
v.bstate := read_wait;
end if;
-- Check if transfer was interrupted or no burst
if (ahbsi.htrans = HTRANS_IDLE) or ((ahbsi.htrans = HTRANS_NONSEQ) and (r.wr_count < maxburst)) then
v.bstate := read_wait;
v.wr_count := (others => '0');
v.rd_count := (others => '0');
v.cmd_count := (others => '0');
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
end if;
end if;
when read_wait =>
if ((r.wr_count >= v.maxrburst) and (ahbsi.htrans = HTRANS_SEQ)) then
v.hready := '0';
v.bstate := start;
v.haddr_start := ahbsi.haddr;
v.haddr := start_address;
v.haddr_offset := ahbsi.haddr;
else
-- Check if we have a pending transaction
if (vnxt.nxt = '1') then
v := vnxt;
vnxt.nxt := '0';
v.bstate := start;
else
v.bstate := idle;
v.hready := '1';
end if;
end if;
when others =>
v.bstate := idle;
end case;
if ((ahbsi.htrans /= HTRANS_SEQ) and (r.bstate = start)) then
v.hready := '0';
end if;
if rst_n_syn = '0' then
v.bstate := idle; v.hready := '1'; v.cmd_en := '0'; v.wr_en := '0'; v.wr_end := '0'; v.maxrburst := maxburst;
end if;
rin <= v;
rnxtin <= vnxt;
end process;
ahbso.hready <= r.hready;
ahbso.hresp <= "00";
ahbso.hrdata <= ahbdrivedata(r.hrdata);
migin.app_addr <= r.haddr(26 downto 2) & "00";
migin.app_cmd <= r.cmd;
migin.app_en <= r.cmd_en;
migin.app_wdf_data <= r.wdf_data_buffer;
migin.app_wdf_end <= r.wr_end;
migin.app_wdf_mask <= r.wdf_mask_buffer;
migin.app_wdf_wren <= r.wr_en;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.prdata <= (others => '0');
regs : process(clk_amba)
begin
if rising_edge(clk_amba) then
-- Copy variables into registers (Default values)
r <= rin;
rnxt <= rnxtin;
-- add extra pipe-stage for read data
migout <= migoutraw;
-- IDLE Clear
if ((r.bstate = idle) or (r.bstate = read_wait)) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
if (r.bstate = write_burst) then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= to_unsigned(1,r.rd_count'length);
end if;
-- Read AHB write data
if (r.bstate = start) and (r.hwrite = '1') then
r.rd_count <= r.rd_count + 1;
end if;
-- Write command repsonse
if r.bstate = write_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
if (r.wr_count < 1 ) then
r.wr_en <= '1';
r.wr_end <= '1';
r.wdf_mask_buffer <= not r.mask_burst(15 downto 0);
r.wdf_data_buffer <= r.hwdata_burst(127 downto 0);
end if;
if (migoutraw.app_wdf_rdy = '1') and (r.wr_en = '1' ) then
if (r.wr_count = 0) then
r.wdf_mask_buffer <= not r.mask_burst(31 downto 16);
r.wdf_data_buffer <= r.hwdata_burst(255 downto 128);
elsif (r.wr_count = 1) then --to support 3 migcmds
r.wdf_mask_buffer <= not r.mask_burst(47 downto 32);
r.wdf_data_buffer <= r.hwdata_burst(383 downto 256);
else
r.wdf_mask_buffer <= not r.mask_burst(31 downto 16);
r.wdf_data_buffer <= r.hwdata_burst(255 downto 128);
end if;
r.wr_count <= r.wr_count + 1;
if (r.wr_count >= r.migcommands - 1) then
r.wr_en <= '0';
r.wr_end <= '0';
end if;
end if;
end if;
-- Burst Write Wait
if r.bstate = write_burst then
r.cmd_count <= (others => '0');
r.wr_count <= (others => '0');
r.rd_count <= (others => '0');
end if;
-- Read command repsonse
if r.bstate = read_cmd then
if (r.cmd_count < 1) then
r.cmd_en <= '1';
end if;
if (migoutraw.app_rdy = '1') and (r.cmd_en = '1' ) then
r.cmd_count <= r.cmd_count + 1;
if (r.cmd_count < r.migcommands-1 ) then
r.haddr <= r.haddr + 8;
end if;
if (r.cmd_count >= r.migcommands-1) then
r.cmd_en <= '0';
end if;
end if;
end if;
end if;
end process;
MCB_inst : mig
port map (
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
sys_clk_i => sys_clk_i,
clk_ref_i => clk_ref_i,
app_addr => migin.app_addr,
app_cmd => migin.app_cmd,
app_en => migin.app_en,
app_rdy => migoutraw.app_rdy,
app_wdf_data => migin.app_wdf_data,
app_wdf_end => migin.app_wdf_end,
app_wdf_mask => migin.app_wdf_mask,
app_wdf_wren => migin.app_wdf_wren,
app_wdf_rdy => migoutraw.app_wdf_rdy,
app_rd_data => migoutraw.app_rd_data,
app_rd_data_end => migoutraw.app_rd_data_end,
app_rd_data_valid => migoutraw.app_rd_data_valid,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => open,
app_ref_ack => open,
app_zq_ack => open,
ui_clk => ui_clk,
ui_clk_sync_rst => ui_clk_sync_rst,
init_calib_complete => calib_done,
sys_rst => rst_n_async
);
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1687.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p03n01i01687ent IS
port (B:Bit);
END c09s02b00x00p03n01i01687ent;
ARCHITECTURE c09s02b00x00p03n01i01687arch OF c09s02b00x00p03n01i01687ent IS
BEGIN
TESTING: PROCESS(B)
component C1 port ( B : BIT ); -- illegal: no component declaration here
end component ;
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p03n01i01687 - Component declarations are not permitted in process statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p03n01i01687arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1687.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p03n01i01687ent IS
port (B:Bit);
END c09s02b00x00p03n01i01687ent;
ARCHITECTURE c09s02b00x00p03n01i01687arch OF c09s02b00x00p03n01i01687ent IS
BEGIN
TESTING: PROCESS(B)
component C1 port ( B : BIT ); -- illegal: no component declaration here
end component ;
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p03n01i01687 - Component declarations are not permitted in process statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p03n01i01687arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1687.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p03n01i01687ent IS
port (B:Bit);
END c09s02b00x00p03n01i01687ent;
ARCHITECTURE c09s02b00x00p03n01i01687arch OF c09s02b00x00p03n01i01687ent IS
BEGIN
TESTING: PROCESS(B)
component C1 port ( B : BIT ); -- illegal: no component declaration here
end component ;
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p03n01i01687 - Component declarations are not permitted in process statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p03n01i01687arch;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: <componenet name>_top.vhd
--
-- Description:
-- This is the actual FIFO core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity afifo_32_v6_top is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(32-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(4-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end afifo_32_v6_top;
architecture xilinx of afifo_32_v6_top is
SIGNAL WR_CLK_i : std_logic;
SIGNAL RD_CLK_i : std_logic;
component afifo_32_v6 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
fg0 : afifo_32_v6
port map (
WR_CLK => WR_CLK_i,
RD_CLK => RD_CLK_i,
RST => RST,
WR_EN => WR_EN,
RD_EN => RD_EN,
DIN => DIN,
DOUT => DOUT,
FULL => FULL,
EMPTY => EMPTY);
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => WR_CLK_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => RD_CLK_i
);
end xilinx;
|
--------------------------------------------------------------------------------
-- DA2 Reference Component
--------------------------------------------------------------------------------
-- Author : Ioana Dabacan
-- CopyRight 2008 Digilent Ro.
--------------------------------------------------------------------------------
-- Desription : This file is the VHDL code for a PMOD-DA2 controller.
--
--------------------------------------------------------------------------------
-- Revision History:
-- Feb/29/2008 (Created) Ioana Dabacan
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--------------------------------------------------------------------------------
--
-- Title : DA1 controller entity
--
-- Inputs : 5
-- Outputs : 5
--
-- Description: This is the DA2 Reference Component entity. The input ports are
-- a 50MHz clock and and an asynchronous reset button along with the
-- data to be serially shifted in the 2 DAC121S101 chips on a DA2
-- Pmod on each clock cycle.There is also a signal to start a
-- conversion.
-- The outputs of this entity are: a output clock signal, two serial
-- output signals D1 and D2, a sync signal to synchronize the data
-- in the DAC121S101 chip, a done signal to tell that the chip is
-- done converting the data and another set of data can be sent.
--
---------------------------------------------------------------------------------
entity DA2RefComp is
Port (
--General usage
CLK : in std_logic; -- System Clock (50MHz)
RST : in std_logic;
--Pmod interface signals
D1 : out std_logic;
D2 : out std_logic;
CLK_OUT : out std_logic;
nSYNC : out std_logic;
--User interface signals
DATA1 : in std_logic_vector(11 downto 0);
DATA2 : in std_logic_vector(11 downto 0);
START : in std_logic;
DONE : out std_logic
);
end DA2RefComp ;
architecture DA2 of DA2RefComp is
-- control constant: Normal Operation
constant control : std_logic_vector(3 downto 0) := "0000";
------------------------------------------------------------------------------------
-- Title : signal assignments
--
-- Description: The following signals are enumerated signals for the
-- finite state machine,2 temporary vectors to be shifted out to the
-- DAC121S101 chips, a divided clock signal to drive the DAC121S101 chips,
-- a counter to divide the internal 50 MHz clock signal,
-- a 4-bit counter to be used to shift out the 16-bit register,
-- and 2 enable signals for the paralel load and shift of the
-- shift register.
--
------------------------------------------------------------------------------------
type states is (Idle,
ShiftOut,
SyncData);
signal current_state : states;
signal next_state : states;
signal temp1 : std_logic_vector(15 downto 0);
signal temp2 : std_logic_vector(15 downto 0);
signal clk_div : std_logic;
signal clk_counter : std_logic_vector(27 downto 0);
signal shiftCounter : std_logic_vector(3 downto 0);
signal enShiftCounter: std_logic;
signal enParalelLoad : std_logic;
begin
------------------------------------------------------------------------------------
--
-- Title : Clock Divider
--
-- Description: The following process takes a 50 MHz clock and divides it down to a
-- 25 MHz clock signal by assigning the signals clk_out and clk_div
-- to the 2nd bit of the clk_counter vector. clk_div is used by
-- the Finite State Machine and clk_out is used by the DAC121S101 chips.
--
------------------------------------------------------------------------------------
clock_divide : process(rst,clk)
begin
if rst = '1' then
clk_counter <= "0000000000000000000000000000";
elsif (clk = '1' and clk'event) then
clk_counter <= clk_counter + '1';
end if;
end process;
clk_div <= clk_counter(0);
clk_out <= clk_counter(0);
-----------------------------------------------------------------------------------
--
-- Title : counter
--
-- Description: This is the process were the teporary registers will be loaded and
-- shifted.When the enParalelLoad signal is generated inside the state
-- the temp1 and temp2 registers will be loaded with the 8 bits of control
-- concatenated with the 8 bits of data. When the enShiftCounter is
-- activated, the 16-bits of data inside the temporary registers will be
-- shifted. A 4-bit counter is used to keep shifting the data
-- inside temp1 and temp 2 for 16 clock cycles.
--
-----------------------------------------------------------------------------------
counter : process(clk_div, enParalelLoad, enShiftCounter)
begin
if (clk_div = '1' and clk_div'event) then
if enParalelLoad = '1' then
shiftCounter <= "0000";
temp1 <= control & DATA1;
temp2 <= control & DATA2;
elsif (enShiftCounter = '1') then
temp1 <= temp1(14 downto 0)&temp1(15);
temp2 <= temp2(14 downto 0)&temp2(15);
shiftCounter <= shiftCounter + '1';
end if;
end if;
end process;
D1 <= temp1(15);
D2 <= temp2(15);
---------------------------------------------------------------------------------
--
-- Title : Finite State Machine
--
-- Description: This 3 processes represent the FSM that contains three states.
-- First one is the Idle state in which the temporary registers are
-- assigned the updated value of the input "DATA1" and "DATA2".
-- The next state is the ShiftOut state which is the state where the
-- 16-bits of temporary registers are shifted out left from the MSB
-- to the two serial outputs, D1 and D2. Immediately following the
-- second state is the third state SyncData. This state drives the
-- output signal sync high for2 clock signals telling the DAC121S101
-- to latch the 16-bit data it just recieved in the previous state.
-- Notes: The data will change on the upper edge of the clock signal. Their
-- is also an asynchronous reset that will reset all signals to their
-- original state.
--
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--
-- Title : SYNC_PROC
--
-- Description: This is the process were the states are changed synchronously. At
-- reset the current state becomes Idle state.
--
-----------------------------------------------------------------------------------
SYNC_PROC: process (clk_div, rst)
begin
if (clk_div'event and clk_div = '1') then
if (rst = '1') then
current_state <= Idle;
else
current_state <= next_state;
end if;
end if;
end process;
-----------------------------------------------------------------------------------
--
-- Title : OUTPUT_DECODE
--
-- Description: This is the process were the output signals are generated
-- unsynchronously based on the state only (Moore State Machine).
--
-----------------------------------------------------------------------------------
OUTPUT_DECODE: process (current_state)
begin
if current_state = Idle then
enShiftCounter <='0';
DONE <='1';
nSYNC <='1';
enParalelLoad <= '1';
elsif current_state = ShiftOut then
enShiftCounter <='1';
DONE <='0';
nSYNC <='0';
enParalelLoad <= '0';
else --if current_state = SyncData then
enShiftCounter <='0';
DONE <='0';
nSYNC <='1';
enParalelLoad <= '0';
end if;
end process;
-----------------------------------------------------------------------------------
--
-- Title : NEXT_STATE_DECODE
--
-- Description: This is the process were the next state logic is generated
-- depending on the current state and the input signals.
--
-----------------------------------------------------------------------------------
NEXT_STATE_DECODE: process (current_state, START, shiftCounter)
begin
next_state <= current_state; --default is to stay in current state
case (current_state) is
when Idle =>
if START = '1' then
next_state <= ShiftOut;
end if;
when ShiftOut =>
if shiftCounter = x"F" then
next_state <= SyncData;
end if;
when SyncData =>
if START = '0' then
next_state <= Idle;
end if;
when others =>
next_state <= Idle;
end case;
end process;
end DA2; |
-- $Id: simclkcnt.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: simclkcnt - sim
-- Description: test bench system clock cycle counter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 12.1-14.7; viv 2016.2; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 2.0 CLK_CYCLE now an integer
-- 2011-11-12 423 1.0.1 now numeric_std clean
-- 2010-11-13 72 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity simclkcnt is -- test bench system clock cycle counter
port (
CLK : in slbit; -- clock
CLK_CYCLE : out integer -- clock cycle number
);
end entity simclkcnt;
architecture sim of simclkcnt is
signal R_CLKCNT : integer := 0;
begin
proc_clk: process (CLK)
begin
if rising_edge(CLK) then
R_CLKCNT <= R_CLKCNT + 1;
end if;
end process proc_clk;
CLK_CYCLE <= R_CLKCNT;
end sim;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 14:13:12 11/03/2015
-- Design Name:
-- Module Name: trafo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity trafo is
Port ( X1 : in STD_LOGIC_VECTOR(15 downto 0);
X2 : in STD_LOGIC_VECTOR(15 downto 0);
X3 : in STD_LOGIC_VECTOR(15 downto 0);
X4 : in STD_LOGIC_VECTOR(15 downto 0);
Z1 : in STD_LOGIC_VECTOR(15 downto 0);
Z2 : in STD_LOGIC_VECTOR(15 downto 0);
Z3 : in STD_LOGIC_VECTOR(15 downto 0);
Z4 : in STD_LOGIC_VECTOR(15 downto 0);
Y1 : OUT STD_LOGIC_VECTOR(15 downto 0);
Y2 : OUT STD_LOGIC_VECTOR(15 downto 0);
Y3 : OUT STD_LOGIC_VECTOR(15 downto 0);
Y4 : OUT STD_LOGIC_VECTOR(15 downto 0));
end trafo;
architecture Behavioral of trafo is
COMPONENT addop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
begin
mulop_1: mulop PORT MAP (
X => X1,
Y => Z1,
O => Y1
);
mulop_2: mulop PORT MAP (
X => X4,
Y => Z4,
O => Y4
);
addop_1: addop PORT MAP (
A => X3,
B => Z2,
O => Y2
);
addop_2: addop PORT MAP (
A => X2,
B => Z3,
O => Y3
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 14:13:12 11/03/2015
-- Design Name:
-- Module Name: trafo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity trafo is
Port ( X1 : in STD_LOGIC_VECTOR(15 downto 0);
X2 : in STD_LOGIC_VECTOR(15 downto 0);
X3 : in STD_LOGIC_VECTOR(15 downto 0);
X4 : in STD_LOGIC_VECTOR(15 downto 0);
Z1 : in STD_LOGIC_VECTOR(15 downto 0);
Z2 : in STD_LOGIC_VECTOR(15 downto 0);
Z3 : in STD_LOGIC_VECTOR(15 downto 0);
Z4 : in STD_LOGIC_VECTOR(15 downto 0);
Y1 : OUT STD_LOGIC_VECTOR(15 downto 0);
Y2 : OUT STD_LOGIC_VECTOR(15 downto 0);
Y3 : OUT STD_LOGIC_VECTOR(15 downto 0);
Y4 : OUT STD_LOGIC_VECTOR(15 downto 0));
end trafo;
architecture Behavioral of trafo is
COMPONENT addop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
begin
mulop_1: mulop PORT MAP (
X => X1,
Y => Z1,
O => Y1
);
mulop_2: mulop PORT MAP (
X => X4,
Y => Z4,
O => Y4
);
addop_1: addop PORT MAP (
A => X3,
B => Z2,
O => Y2
);
addop_2: addop PORT MAP (
A => X2,
B => Z3,
O => Y3
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 14:13:12 11/03/2015
-- Design Name:
-- Module Name: trafo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity trafo is
Port ( X1 : in STD_LOGIC_VECTOR(15 downto 0);
X2 : in STD_LOGIC_VECTOR(15 downto 0);
X3 : in STD_LOGIC_VECTOR(15 downto 0);
X4 : in STD_LOGIC_VECTOR(15 downto 0);
Z1 : in STD_LOGIC_VECTOR(15 downto 0);
Z2 : in STD_LOGIC_VECTOR(15 downto 0);
Z3 : in STD_LOGIC_VECTOR(15 downto 0);
Z4 : in STD_LOGIC_VECTOR(15 downto 0);
Y1 : OUT STD_LOGIC_VECTOR(15 downto 0);
Y2 : OUT STD_LOGIC_VECTOR(15 downto 0);
Y3 : OUT STD_LOGIC_VECTOR(15 downto 0);
Y4 : OUT STD_LOGIC_VECTOR(15 downto 0));
end trafo;
architecture Behavioral of trafo is
COMPONENT addop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
begin
mulop_1: mulop PORT MAP (
X => X1,
Y => Z1,
O => Y1
);
mulop_2: mulop PORT MAP (
X => X4,
Y => Z4,
O => Y4
);
addop_1: addop PORT MAP (
A => X3,
B => Z2,
O => Y2
);
addop_2: addop PORT MAP (
A => X2,
B => Z3,
O => Y3
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 14:13:12 11/03/2015
-- Design Name:
-- Module Name: trafo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity trafo is
Port ( X1 : in STD_LOGIC_VECTOR(15 downto 0);
X2 : in STD_LOGIC_VECTOR(15 downto 0);
X3 : in STD_LOGIC_VECTOR(15 downto 0);
X4 : in STD_LOGIC_VECTOR(15 downto 0);
Z1 : in STD_LOGIC_VECTOR(15 downto 0);
Z2 : in STD_LOGIC_VECTOR(15 downto 0);
Z3 : in STD_LOGIC_VECTOR(15 downto 0);
Z4 : in STD_LOGIC_VECTOR(15 downto 0);
Y1 : OUT STD_LOGIC_VECTOR(15 downto 0);
Y2 : OUT STD_LOGIC_VECTOR(15 downto 0);
Y3 : OUT STD_LOGIC_VECTOR(15 downto 0);
Y4 : OUT STD_LOGIC_VECTOR(15 downto 0));
end trafo;
architecture Behavioral of trafo is
COMPONENT addop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
begin
mulop_1: mulop PORT MAP (
X => X1,
Y => Z1,
O => Y1
);
mulop_2: mulop PORT MAP (
X => X4,
Y => Z4,
O => Y4
);
addop_1: addop PORT MAP (
A => X3,
B => Z2,
O => Y2
);
addop_2: addop PORT MAP (
A => X2,
B => Z3,
O => Y3
);
end Behavioral;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_64_d32.vhd
-- /___/ /\ Timestamp: Wed Jul 16 14:58:26 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_64_d32.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_64_d32.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_d32.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_64_d32.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_64_d32
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_64_d32 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_64_d32;
architecture STRUCTURE of fifo_generator_64_d32 is
signal N0 : STD_LOGIC;
signal N22 : STD_LOGIC;
signal Result_0_1 : STD_LOGIC;
signal Result_1_1 : STD_LOGIC;
signal Result_2_1 : STD_LOGIC;
signal Result_3_1 : STD_LOGIC;
signal Result_4_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_16 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_17 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_18 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_19 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_20 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_36 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_37 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_38 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_40 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_41 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_42 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_44 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_190 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_191 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_192 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_193 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_197 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_198 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_199 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_200 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_201 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_202 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM114_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM113_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM112_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM111_SPO_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM10_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM10_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM9_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM9_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_0_UNCONNECTED : STD_LOGIC;
signal Result : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000 : STD_LOGIC_VECTOR ( 63 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i : STD_LOGIC_VECTOR ( 63 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i;
empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_44;
dout(63) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(63);
dout(62) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(62);
dout(61) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(61);
dout(60) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(60);
dout(59) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(59);
dout(58) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(58);
dout(57) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(57);
dout(56) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(56);
dout(55) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(55);
dout(54) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(54);
dout(53) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(53);
dout(52) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(52);
dout(51) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(51);
dout(50) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(50);
dout(49) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(49);
dout(48) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(48);
dout(47) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(47);
dout(46) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(46);
dout(45) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(45);
dout(44) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(44);
dout(43) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(43);
dout(42) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(42);
dout(41) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(41);
dout(40) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(40);
dout(39) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(39);
dout(38) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(38);
dout(37) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(37);
dout(36) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(36);
dout(35) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(35);
dout(34) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(34);
dout(33) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(33);
dout(32) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(32);
dout(31) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(31);
dout(30) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(30);
dout(29) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(29);
dout(28) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(28);
dout(27) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(27);
dout(26) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(26);
dout(25) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(25);
dout(24) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(24);
dout(23) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(23);
dout(22) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(22);
dout(21) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(21);
dout(20) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(20);
dout(19) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(19);
dout(18) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(18);
dout(17) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(17);
dout(16) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(16);
dout(15) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(15);
dout(14) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(14);
dout(13) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(13);
dout(12) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(12);
dout(11) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(11);
dout(10) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(10);
dout(9) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(9);
dout(8) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(8);
dout(7) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(7);
dout(6) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(6);
dout(5) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(5);
dout(4) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(4);
dout(3) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(3);
dout(2) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(2);
dout(1) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(1);
dout(0) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(0);
XST_GND : GND
port map (
G => N0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_d1_12
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
D => Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_0_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
D => Result_1_1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_2_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_3_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
D => Result(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1),
D => Result_4_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_199,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_190
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_198,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_199
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_192,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_193
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_201,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_202
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_197,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_198
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_191,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_192
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_201,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_200
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_200,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_201
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_192,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_191
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_197
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM114 : RAM32X1D
port map (
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
D => din(63),
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM114_SPO_UNCONNECTED,
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(63)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM113 : RAM32X1D
port map (
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
D => din(62),
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM113_SPO_UNCONNECTED,
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(62)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM112 : RAM32X1D
port map (
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
D => din(61),
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM112_SPO_UNCONNECTED,
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(61)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM111 : RAM32X1D
port map (
A0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
A1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
A2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
A3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
A4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
D => din(60),
DPRA0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
DPRA1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
DPRA2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
DPRA3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
DPRA4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
SPO => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM111_SPO_UNCONNECTED,
DPO => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(60)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM10 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(55),
DIA(0) => din(54),
DIB(1) => din(57),
DIB(0) => din(56),
DIC(1) => din(59),
DIC(0) => din(58),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(55),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(54),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(57),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(56),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(59),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(58),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM10_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM10_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(43),
DIA(0) => din(42),
DIB(1) => din(45),
DIB(0) => din(44),
DIC(1) => din(47),
DIC(0) => din(46),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(43),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(42),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(45),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(44),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(47),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(46),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM8_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(37),
DIA(0) => din(36),
DIB(1) => din(39),
DIB(0) => din(38),
DIC(1) => din(41),
DIC(0) => din(40),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(37),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(36),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(39),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(38),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(41),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(40),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM7_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM9 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(49),
DIA(0) => din(48),
DIB(1) => din(51),
DIB(0) => din(50),
DIC(1) => din(53),
DIC(0) => din(52),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(49),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(48),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(51),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(50),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(53),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(52),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM9_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM9_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(25),
DIA(0) => din(24),
DIB(1) => din(27),
DIB(0) => din(26),
DIC(1) => din(29),
DIC(0) => din(28),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(25),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(24),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(27),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(26),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(29),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(28),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM5_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(19),
DIA(0) => din(18),
DIB(1) => din(21),
DIB(0) => din(20),
DIC(1) => din(23),
DIC(0) => din(22),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(19),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(18),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(21),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(20),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(23),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(22),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM4_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(31),
DIA(0) => din(30),
DIB(1) => din(33),
DIB(0) => din(32),
DIC(1) => din(35),
DIC(0) => din(34),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(31),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(30),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(33),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(32),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(35),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(34),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM6_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(7),
DIA(0) => din(6),
DIB(1) => din(9),
DIB(0) => din(8),
DIC(1) => din(11),
DIC(0) => din(10),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(7),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(6),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(9),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(8),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(11),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(10),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM2_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(1),
DIA(0) => din(0),
DIB(1) => din(3),
DIB(0) => din(2),
DIC(1) => din(5),
DIC(0) => din(4),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(1),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(0),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(3),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(2),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(5),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(4),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM1_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3 : RAM32M
generic map(
INIT_C => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_D => X"0000000000000000",
INIT_A => X"0000000000000000"
)
port map (
WCLK => clk,
WE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
DIA(1) => din(13),
DIA(0) => din(12),
DIB(1) => din(15),
DIB(0) => din(14),
DIC(1) => din(17),
DIC(0) => din(16),
DID(1) => N0,
DID(0) => N0,
ADDRA(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRA(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRA(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRB(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRB(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRB(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRC(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
ADDRC(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
ADDRC(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
ADDRC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
ADDRC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
ADDRD(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
ADDRD(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
ADDRD(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
ADDRD(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
ADDRD(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
DOA(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(13),
DOA(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(12),
DOB(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(15),
DOB(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(14),
DOC(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(17),
DOC(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(16),
DOD(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_1_UNCONNECTED,
DOD(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_Mram_RAM3_DOD_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_63 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(63),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(63)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_62 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(62),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(62)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_61 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(61),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(61)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_60 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(60),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(60)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_59 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(59),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(59)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_58 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(58),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(58)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_57 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(57),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(57)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_56 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(56),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(56)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_55 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(55),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(55)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_54 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(54),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(54)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_53 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(53),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(53)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_52 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(52),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(52)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_51 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(51),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(51)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_50 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(50),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(50)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_49 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(49),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(49)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_48 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(48),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(48)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_47 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(47),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(47)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_46 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(46),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(46)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_45 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(45),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(45)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_44 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(44),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(44)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_43 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(43),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(43)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_42 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(42),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(42)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_41 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(41),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(41)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_40 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(40),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(40)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_39 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(39),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(39)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_38 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(38),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(38)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_37 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(37),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(37)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_36 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(36),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(36)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_35 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(35),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(35)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_34 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(34),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(34)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_33 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(33),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(33)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_32 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(32),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(32)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_31 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(31),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(31)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_30 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(30),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(30)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_29 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(29),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(29)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_28 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(28),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(28)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_27 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(27),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(27)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_26 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(26),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(26)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_25 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(25),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(25)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_24 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(24),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(24)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_23 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(23),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(23)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_22 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(22),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(22)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_21 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(21),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(21)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_20 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(20),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(20)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_19 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(19),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(19)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_18 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(18),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(18)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_17 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(17),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(17)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_16 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(16),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(16)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_15 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(15),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(15)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_14 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(14),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(14)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_13 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(13),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(13)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_12 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(12),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(12)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_11 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(11),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(11)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_10 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(10),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(10)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_9 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(9),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(9)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(8),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(7),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(6),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(5),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(4),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_varindex0000(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gdm_dm_dout_i(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_198,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_198,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_44
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_198,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_200,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_202,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_191,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_193,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grhf_rhf_ram_valid_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_1_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_1_11 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
O => Result_2_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_2_11 : LUT3
generic map(
INIT => X"6C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
O => Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
O => Result_3_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_3_11 : LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
O => Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_4_11 : LUT5
generic map(
INIT => X"6CCCCCCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
O => Result_4_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_4_11 : LUT5
generic map(
INIT => X"6CCCCCCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
O => Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i_SW0 : LUT6
generic map(
INIT => X"7FBFDFEFF7FBFDFE"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
O => N22
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_c1_dout_i : LUT5
generic map(
INIT => X"00008421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d1(2),
I4 => N22,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41 : LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_41
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb82 : LUT4
generic map(
INIT => X"7BDE"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93 : LUT6
generic map(
INIT => X"FFFFFFFFFFFF6FF6"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb41_41,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_42
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_190,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_36
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044 : LUT4
generic map(
INIT => X"8421"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_38
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104 : LUT6
generic map(
INIT => X"8008200240041001"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(2),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_37
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000142 : LUT6
generic map(
INIT => X"8E8A8A8AAEAAAAAA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000010_36,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or000044_38,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000104_37,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049 : LUT6
generic map(
INIT => X"7FBFDFEFF7FBFDFE"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(1),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(4),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_20
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129 : LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(4),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_16
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_17
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182 : LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count_d2(2),
I4 => rd_en,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000156_17,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_18
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_19
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000232 : LUT6
generic map(
INIT => X"EAEAEAC8AAAAAA88"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000213_19,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000129_16,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000076,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or000049_20,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000182_18,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb132 : LUT6
generic map(
INIT => X"F4F4F0F444440044"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_190,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_40,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_ram_rd_en_i,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb93_42,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_comp1,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2 : LUT4
generic map(
INIT => X"0C04"
)
port map (
I0 => rd_en,
I1 => wr_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_43,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_14,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb2_40
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_count(0),
O => Result_0_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Mcount_count_xor_0_11_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_count(0),
O => Result(0)
);
end STRUCTURE;
-- synthesis translate_on
|
library verilog;
use verilog.vl_types.all;
entity butter_2 is
generic(
RST_LVL : integer := 0
);
port(
clk : in vl_logic;
rst : in vl_logic;
butt2_real0 : in vl_logic_vector(15 downto 0);
butt2_imag0 : in vl_logic_vector(15 downto 0);
butt2_real1 : in vl_logic_vector(15 downto 0);
butt2_imag1 : in vl_logic_vector(15 downto 0);
factor_real : in vl_logic_vector(15 downto 0);
factor_imag : in vl_logic_vector(15 downto 0);
y0_real : out vl_logic_vector(15 downto 0);
y0_imag : out vl_logic_vector(15 downto 0);
y1_real : out vl_logic_vector(15 downto 0);
y1_imag : out vl_logic_vector(15 downto 0)
);
end butter_2;
|
-------------------------------------------------------------------------------
-- Title : Human Readable Name for the module in this file.
-- Project : fpga_logic_analyzer
-------------------------------------------------------------------------------
-- File : vhdl_file_template.vhd
-- Created : 2016-02-22
-- Last update: 2016-02-22
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: This is where you will describe this file
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Ashton Johnson, Paul Henny, Ian Swepston, David Hurt
-------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-22 1.0 (your name) Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
|
-------------------------------------------------------------------------------
-- Title : ALU substracter
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : ALU_Substracter.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-12-06
-- Last update: 2016-12-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-06 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity ALU_Substracter is
generic (
DATA_WIDTH : integer
);
port (
i_ra : in unsigned(DATA_WIDTH - 1 downto 0);
i_rb : in unsigned(DATA_WIDTH - 1 downto 0);
o_q : out unsigned(DATA_WIDTH * 2 - 1 downto 0)
);
end entity ALU_Substracter;
-------------------------------------------------------------------------------
architecture rtl of ALU_Substracter is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal result : unsigned(DATA_WIDTH downto 0);
signal sign_extend : unsigned(DATA_WIDTH - 2 downto 0);
begin -- architecture rtl
o_q <= sign_extend & result;
result <= resize(i_ra, DATA_WIDTH + 1) - resize(i_rb, DATA_WIDTH + 1);
sign_extend <= (others => result(DATA_WIDTH));
end architecture rtl;
-------------------------------------------------------------------------------
|
-- $Id: tb_tst_sram_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2015 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_sram_n4
-- Description: Configuration for tb_tst_sram_n4 for tb_nexys4_cram
--
-- Dependencies: sys_tst_sram_n4
--
-- To test: sys_tst_sram_n4
--
-- Verified:
-- Date Rev Code ghdl ise Target Comment
-- 2013-??-?? 534 - 0.29 13.1 O40d xc6slx16 ???
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-06 643 1.1 use tb_nexys4_cram now
-- 2013-09-21 534 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_sram_n4 of tb_nexys4_cram is
for sim
for all : nexys4_cram_aif
use entity work.sys_tst_sram_n4;
end for;
end for;
end tb_tst_sram_n4;
|
architecture RTL of FIFO is
begin
process is
begin
end process;
process (a, b) is
begin
end process;
-- Violations below
process
begin
end process;
process (a, b)
begin
end process;
process(a,b)begin end process;
end architecture RTL;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE WORK.LIB.ALL;
ENTITY AP IS
PORT(
clock : IN std_logic;
rst : IN std_logic;
-- AP Memory/Arbiter
MemDataIn : IN AP_data_width;
MemDataOut: OUT AP_data_width;
MemAddr : OUT AP_mem_addr_width;
wrMem : OUT std_logic;
startArb : OUT std_logic;
arbMode : OUT std_logic;
arbReady : IN std_logic;
-- Fault State Memory
FSdataIn : IN AP_data_width;
FSdataOut : OUT AP_data_width;
FSwrite : OUT std_logic;
FSaddr : OUT std_logic_vector (6 downto 0);
SlotNr : OUT std_logic_vector (1 downto 0);
slot : IN std_logic;
lRP : IN std_logic;
rRP : IN std_logic;
resetFS : OUT std_logic;
-- PuT
PuTHalt : IN std_logic;
PuTContinue : OUT std_logic;
PuTReset : OUT std_logic
);
END AP;
ARCHITECTURE behave OF AP IS
-- COMPONENTS ---------
COMPONENT AP_regFile IS
PORT(
clock : IN std_logic;
rst : IN std_logic;
enable : IN std_logic;
wrAddr : IN AP_reg_select;
wrData : IN AP_data_width;
rp1Addr : IN AP_reg_select;
rp2Addr : IN AP_reg_select;
rp1Data : OUT AP_data_width;
rp2Data : OUT AP_data_width
);
END COMPONENT;
COMPONENT AP_reg_generic IS
GENERIC (reg_width : natural := 8);
PORT(
clock : IN std_logic;
rst : IN std_logic;
enable : IN std_logic;
input : IN std_logic_vector (reg_width-1 downto 0);
output : OUT std_logic_vector (reg_width-1 downto 0)
);
END COMPONENT;
COMPONENT AP_Alu IS
PORT(
clock : IN std_logic;
rst : IN std_logic;
OP_A : IN AP_data_width;
OP_B : IN AP_data_width;
ALU_OP : IN std_logic_vector(3 downto 0);
RESULT : OUT AP_data_width;
carry_out : OUT std_logic;
zero_out : OUT std_logic;
sign_out : OUT std_logic;
overflow_out : OUT std_logic
);
END COMPONENT;
-- SIGNALS ------------
signal RF_wrAddr, RF_Addr1, RF_Addr2 : AP_reg_select;
signal RF_en, IR_en, FSaddr_en, SlotNr_en, MBR_en, MAR_H_en, MAR_L_en, PC_en, rstTimer, incTimer : std_logic;
signal carry, overflow, sign, zero : std_logic;
signal RF_in, RF_out1, RF_out2, IR_out, Alu_in1, Alu_in2, Alu_out : AP_data_width;
signal MAR_L_out, MAR_L_in, MBR_out, MBR_in : AP_data_width;
signal MAR_H_out, MAR_H_in : std_logic_vector(AP_ADDR_WIDTH - AP_WIDTH - 1 downto 0);
signal Alu_opc : std_logic_vector(3 downto 0);
signal timer : std_logic_vector(3 downto 0);
signal FSaddr_in : std_logic_vector(6 downto 0);
signal SlotNr_in, SlotNr_out : std_logic_vector(1 downto 0);
signal PC_out, PC_in : AP_mem_addr_width;
signal instCh_in, instCh_out : std_logic_vector(0 downto 0);
signal instCh_en : std_logic;
BEGIN
SlotNr <= SlotNr_out;
control: process(IR_out, timer, PC_out, RF_out1, RF_out2, Alu_out,
MemDataIN, MBR_out, MAR_L_out, MAR_H_out, FSdataIn,
arbReady, carry, zero, sign, overflow, PuTHalt, SlotNr_out)
variable jmpCond : std_logic := '0';
begin
-- default-values
IR_en <= '0';
PC_en <= '0';
RF_en <= '0';
MBR_en <= '0';
MAR_H_en <= '0';
MAR_L_en <= '0';
FSaddr_en <= '0';
FSwrite <= '0';
wrMem <= '0';
rstTimer <= '0';
startArb <= '0';
arbMode <= '0';
incTimer <= '1';
PuTContinue <= '0';
PuTReset <= '0';
SlotNr_en <= '0';
instCh_en <= '0';
resetFS <= '0';
PC_in <= PC_out;
MemAddr <= PC_out;
Alu_opc <= (others => '0');
RF_Addr1 <= IR_out(3 downto 2);
RF_Addr2 <= IR_out(1 downto 0);
RF_wrAddr <= IR_out(3 downto 2);
Alu_in1 <= RF_out1;
Alu_in2 <= RF_out2;
RF_in <= Alu_out;
MBR_in <= MemDataIN;
MAR_H_in <= RF_out1(AP_ADDR_WIDTH - AP_WIDTH - 1 downto 0);
MAR_L_in <= RF_out1;
MemDataOut <= MBR_out;
FSaddr_in <= RF_out1(6 downto 0);
FSdataOut <= RF_out1;
SlotNr_in <= Alu_out(1 downto 0);
instCh_in <= IR_out(0 downto 0);
if(timer = "0000") then
-- fetch
MemAddr <= PC_out;
IR_en <= '1';
PC_en <= '1';
PC_in <= PC_out + 1;
else
if(IR_out(7) = '0') then
-- AluOp with 2 Operands
Alu_opc <= IR_out(7 downto 4);
RF_Addr1 <= IR_out(3 downto 2);
RF_Addr2 <= IR_out(1 downto 0);
RF_wrAddr <= IR_out(3 downto 2);
Alu_in1 <= RF_out1;
Alu_in2 <= RF_out2;
RF_in <= Alu_out;
RF_en <= '1';
rstTimer <= '1';
elsif(IR_out(7 downto 5) = "101") then
-- AluOp with 1 Operand
Alu_opc <= IR_out(5 downto 2);
RF_Addr1 <= IR_out(1 downto 0);
RF_wrAddr <= IR_out(1 downto 0);
Alu_in1 <= RF_out1;
RF_in <= Alu_out;
RF_en <= '1';
rstTimer <= '1';
elsif(IR_out(7 downto 5) /= "111") then
-- Ops with 1 Operand
RF_Addr1 <= IR_out(1 downto 0);
RF_wrAddr <= IR_out(1 downto 0);
case IR_out(7 downto 2) is
when "100000" =>
-- load
if(timer = "0001") then
MemAddr <= MAR_H_out & MAR_L_out;
MBR_en <= '1';
MBR_in <= MemDataIN;
elsif(timer = "0010") then
RF_in <= MBR_out;
RF_en <= '1';
rstTimer <= '1';
end if;
when "100001" =>
-- store
if(timer = "0001") then
MBR_in <= RF_out1;
MBR_en <= '1';
elsif(timer = "0010") then
wrMem <= '1';
MemAddr <= MAR_H_out & MAR_L_out;
rstTimer <= '1';
end if;
when "100010" =>
-- ldc
if(timer = "0001") then
PC_en <= '1';
PC_in <= PC_out + 1;
MBR_in <= MemDataIN;
MBR_en <= '1';
elsif(timer = "0010") then
RF_in <= MBR_out;
RF_en <= '1';
rstTimer <= '1';
end if;
when "100011" =>
-- setMarL
MAR_L_in <= RF_out1;
MAR_L_en <= '1';
rstTimer <= '1';
when "100100" =>
-- setMarH
MAR_H_in <= RF_out1(AP_ADDR_WIDTH - AP_WIDTH - 1 downto 0);
MAR_H_en <= '1';
rstTimer <= '1';
when "100101" | "100110" =>
-- incMar | decMar
if(timer = "0001") then
Alu_in1 <= MAR_L_out;
Alu_in2 <= "000000" & IR_out(1 downto 0);
if(IR_out(7 downto 2) = "100101") then
Alu_opc <= "0001"; -- add
else
Alu_opc <= "0010"; -- sub
end if;
MAR_L_in <= Alu_out;
MAR_L_en <= '1';
elsif(timer = "0010") then
if(carry = '1') then
Alu_in1(AP_WIDTH - 1 downto AP_ADDR_WIDTH - AP_WIDTH) <= (others => '0');
Alu_in1(AP_ADDR_WIDTH - AP_WIDTH - 1 downto 0) <= MAR_H_out;
if(IR_out(7 downto 2) = "100101") then
Alu_opc <= "1011"; -- inc
else
Alu_opc <= "1100"; -- dec
end if;
MAR_H_in <= Alu_out(AP_ADDR_WIDTH - AP_WIDTH - 1 downto 0);
MAR_H_en <= '1';
end if;
rstTimer <= '1';
end if;
when "110000" =>
-- setFSaddr
FSaddr_en <= '1';
FSaddr_in <= RF_out1(6 downto 0);
rstTimer <= '1';
when "110001" =>
-- readFS
RF_in <= FSdataIn;
RF_en <= '1';
rstTimer <= '1';
when "110010" =>
-- writeFS
FSdataOut <= RF_out1;
FSwrite <= '1';
rstTimer <= '1';
when others =>
rstTimer <= '1';
end case;
elsif(IR_out(7 downto 5) = "111") then
-- no Operands
if(IR_out(4) = '0') then
-- jumps
if(timer = "0001") then
case IR_out(4 downto 0) is
when "00000" =>
jmpCond := '1';
when "00001" =>
jmpCond := carry;
when "00010" =>
jmpCond := not carry;
when "00011" =>
jmpCond := sign;
when "00100" =>
jmpCond := not sign;
when "00101" =>
jmpCond := overflow;
when "00110" =>
jmpCond := not overflow;
when "00111" =>
jmpCond := zero;
when "01000" =>
jmpCond := not zero;
when "01001" =>
jmpCond := slot;
when "01010" =>
if(SlotNr_out = "11") then
jmpCond := '0';
else
jmpCond := '1';
end if;
when "01011" =>
jmpCond := not lRP;
when "01100" =>
jmpCond := not rRP;
when "01111" =>
jmpCond := not PuTHalt;
when others =>
jmpCond := '0';
end case;
PC_en <= '1';
PC_in <= PC_out + 1;
if(jmpCond = '1') then
MBR_in <= MemDataIN;
MBR_en <= '1';
end if;
elsif(timer = "0010") then
if(jmpCond = '0') then
PC_en <= '1';
PC_in <= PC_out + 1;
rstTimer <= '1';
else
PC_in(AP_ADDR_WIDTH-1 downto AP_WIDTH)
<= MBR_out(AP_ADDR_WIDTH - AP_WIDTH - 1 downto 0);
PC_en <= '1';
MBR_in <= MemDataIN;
MBR_en <= '1';
end if;
elsif(timer = "0011") then
PC_in(AP_WIDTH-1 downto 0) <= MBR_out;
PC_en <= '1';
MemAddr <= MAR_H_out & MAR_L_out; -- im PC könnte in diesem Takt eine zu hohe Adresse stehen (falls der adressierbare Bereich größer ist als der Speicher)
rstTimer <= '1';
end if;
else -- IR_out(4) /= '0' -> no Operand, no jump
case IR_out(4 downto 0) is
when "10000" | "10001" =>
-- fetchInstr | storeInstr.
arbMode <= IR_out(0);
incTimer <= '0';
if(timer = "0001") then
MemAddr <= MAR_H_out & MAR_L_out;
startArb <= not IR_out(0) or instCh_out(0);
incTimer <= '1';
elsif(arbReady = '1') then
rstTimer <= '1';
end if;
when "10010" =>
-- continuePuT
PuTContinue <= '1';
rstTimer <= '1';
when "10011" =>
-- resetPuT
PuTReset <= '1';
rstTimer <= '1';
when "10100" =>
-- resetFS
resetFS <= '1';
rstTimer <= '1';
when "10101" =>
-- setMar
if(timer = "0001") then
MBR_in <= MemDataIN;
MBR_en <= '1';
PC_en <= '1';
PC_in <= PC_out + 1;
elsif(timer = "0010") then
MAR_H_in <= MBR_out(AP_ADDR_WIDTH - AP_WIDTH - 1 downto 0);
MAR_H_en <= '1';
MBR_in <= MemDataIN;
MBR_en <= '1';
PC_en <= '1';
PC_in <= PC_out + 1;
elsif(timer = "0011") then
MAR_L_in <= MBR_out;
MAR_L_en <= '1';
rstTimer <= '1';
end if;
when "11000" | "11001" =>
-- rstInstChanged | setInstChanged
instCh_in <= IR_out(0 downto 0);
instCh_en <= '1';
rstTimer <= '1';
when "11010" =>
-- rstSlotNr
SlotNr_in <= "00";
SlotNr_en <= '1';
rstTimer <= '1';
when "11011" | "11100" =>
-- incSlotNr | decSlotNr
Alu_in1 <= "000000" & SlotNr_out;
Alu_opc <= IR_out(3 downto 0);
SlotNr_in <= Alu_out(1 downto 0);
SlotNr_en <= '1';
rstTimer <= '1';
when others =>
rstTimer <= '1';
end case;
end if;
end if;
end if;
end process;
timer_process: process(clock, rst)
begin
if (rst = '1') then
timer <= (others => '0');
elsif (clock'event and clock = '1') then
if(rstTimer = '1') then
timer <= (others => '0');
elsif(incTimer = '1') then
timer <= timer + 1;
end if;
end if;
end process;
PC: AP_reg_generic
GENERIC MAP (reg_width => AP_ADDR_WIDTH)
PORT MAP (
clock => clock,
rst => rst,
enable => PC_en,
input => PC_in,
output => PC_out
);
IR: AP_reg_generic
GENERIC MAP (reg_width => AP_WIDTH)
PORT MAP (
clock => clock,
rst => rst,
enable => IR_en,
input => MemDataIN,
output => IR_out
);
MBR: AP_reg_generic
GENERIC MAP (reg_width => AP_WIDTH)
PORT MAP (
clock => clock,
rst => rst,
enable => MBR_en,
input => MBR_in,
output => MBR_out
);
MAR_H: AP_reg_generic
GENERIC MAP (reg_width => AP_ADDR_WIDTH - AP_WIDTH)
PORT MAP (
clock => clock,
rst => rst,
enable => MAR_H_en,
input => MAR_H_in,
output => MAR_H_out
);
MAR_L: AP_reg_generic
GENERIC MAP (reg_width => AP_WIDTH)
PORT MAP (
clock => clock,
rst => rst,
enable => MAR_L_en,
input => MAR_L_in,
output => MAR_L_out
);
FS_addr: AP_reg_generic
GENERIC MAP (reg_width => 7)
PORT MAP (
clock => clock,
rst => rst,
enable => FSaddr_en,
input => FSaddr_in,
output => FSaddr
);
SlotNr_reg: AP_reg_generic
GENERIC MAP (reg_width => 2)
PORT MAP (
clock => clock,
rst => rst,
enable => SlotNr_en,
input => SlotNr_in,
output => SlotNr_out
);
regFile: AP_regFile
PORT MAP (
clock => clock,
rst => rst,
enable => RF_en,
wrAddr => RF_wrAddr,
wrData => RF_in,
rp1Addr => RF_Addr1,
rp2Addr => RF_Addr2,
rp1Data => RF_out1,
rp2Data => RF_out2
);
ALU: AP_Alu
PORT MAP (
clock => clock,
rst => rst,
OP_A => Alu_in1,
OP_B => Alu_in2,
ALU_OP => Alu_opc,
RESULT => Alu_out,
carry_out => carry,
zero_out => zero,
sign_out => sign,
overflow_out => overflow
);
InstChanged: AP_reg_generic
GENERIC MAP (reg_width => 1)
PORT MAP (
clock => clock,
rst => rst,
enable => instCh_en,
input => instCh_in,
output => instCh_out
);
END behave; |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_2_8;
USE axi_quad_spi_v3_2_8.axi_quad_spi;
ENTITY PmodNAV_axi_quad_spi_0_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END PmodNAV_axi_quad_spi_0_0;
ARCHITECTURE PmodNAV_axi_quad_spi_0_0_arch OF PmodNAV_axi_quad_spi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF PmodNAV_axi_quad_spi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
Async_Clk : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_UC_FAMILY : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
C_SHARED_STARTUP : INTEGER;
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
C_LSB_STUP : INTEGER
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
clk : IN STD_LOGIC;
gsr : IN STD_LOGIC;
gts : IN STD_LOGIC;
keyclearb : IN STD_LOGIC;
usrcclkts : IN STD_LOGIC;
usrdoneo : IN STD_LOGIC;
usrdonets : IN STD_LOGIC;
pack : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF PmodNAV_axi_quad_spi_0_0_arch: ARCHITECTURE IS "axi_quad_spi,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF PmodNAV_axi_quad_spi_0_0_arch : ARCHITECTURE IS "PmodNAV_axi_quad_spi_0_0,axi_quad_spi,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF PmodNAV_axi_quad_spi_0_0_arch: ARCHITECTURE IS "PmodNAV_axi_quad_spi_0_0,axi_quad_spi,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_quad_spi,x_ipVersion=3.2,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,Async_Clk=1,C_FAMILY=zynq,C_SELECT_XPM=0,C_SUB_FAMILY=zynq,C_INSTANCE=axi_quad_spi_inst,C_SPI_MEM_ADDR_BITS=24,C_TYPE_OF_AXI4_INTERFACE=0,C_XIP_MODE=0,C_UC_FAMILY=0,C_FIFO_DEPTH=16,C_SCK_RATIO=16,C_NUM_SS_BITS=1,C_NUM_TRANSFER_BITS=8,C_SPI_MODE=0,C_USE_STARTUP=0,C_SPI_MEMORY=1,C_S_AXI_ADDR_WIDTH=7" &
",C_S_AXI_DATA_WIDTH=32,C_S_AXI4_ADDR_WIDTH=24,C_S_AXI4_DATA_WIDTH=32,C_S_AXI4_ID_WIDTH=1,C_SHARED_STARTUP=0,C_S_AXI4_BASEADDR=0xFFFFFFFF,C_S_AXI4_HIGHADDR=0x00000000,C_LSB_STUP=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
Async_Clk => 1,
C_FAMILY => "zynq",
C_SELECT_XPM => 0,
C_SUB_FAMILY => "zynq",
C_INSTANCE => "axi_quad_spi_inst",
C_SPI_MEM_ADDR_BITS => 24,
C_TYPE_OF_AXI4_INTERFACE => 0,
C_XIP_MODE => 0,
C_UC_FAMILY => 0,
C_FIFO_DEPTH => 16,
C_SCK_RATIO => 16,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 0,
C_USE_STARTUP => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 1,
C_SHARED_STARTUP => 0,
C_S_AXI4_BASEADDR => X"FFFFFFFF",
C_S_AXI4_HIGHADDR => X"00000000",
C_LSB_STUP => 0
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi4_aclk => '0',
s_axi4_aresetn => '0',
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => '0',
io3_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
clk => '0',
gsr => '0',
gts => '0',
keyclearb => '0',
usrcclkts => '0',
usrdoneo => '0',
usrdonets => '0',
pack => '0',
ip2intc_irpt => ip2intc_irpt
);
END PmodNAV_axi_quad_spi_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity ent;
architecture arch of ent is
signal test: natural;
begin
LL: case test generate
when =>
end generate;
end architecture arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity ent;
architecture arch of ent is
signal test: natural;
begin
LL: case test generate
when =>
end generate;
end architecture arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spax
-- File: ddr2spax.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: DDR2 memory controller with asynch AHB interface
-- Based on ddr2sp(16/32/64)a, generalized and expanded
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
library techmap;
use techmap.gencomp.ddr2phy_has_datavalid;
use techmap.gencomp.ddr2phy_ptctrl;
entity ddr2spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
-- dqsgating : integer := 0;
nosync : integer := 0;
dqsgating : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
rstdel : integer := 200;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
hwidth : in std_ulogic
);
end ddr2spax;
architecture rtl of ddr2spax is
constant REVISION : integer := 1;
constant ramwt: integer := 0;
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(ddrbits*2);
function pick(choice: boolean; t,f: integer) return integer is
begin
if choice then return t; else return f; end if;
end;
constant xahbw: integer := pick(ft/=0 and ahbbits<64, 64, ahbbits);
constant l2ahbw: integer := log2(xahbw);
-- For non-FT, write buffer has room for two write bursts and is addressable
-- down to 32-bit level on write (AHB) side.
-- For FT, the write buffer has room for one write burst and is addressable
-- down to 64-bit level on write side.
-- Write buffer dimensions
constant wbuf_rabits_s: integer := 1+l2blen-l2ddrw;
constant wbuf_rabits_r: integer := wbuf_rabits_s-FT;
constant wbuf_rdbits: integer := pick(ft/=0, 3*ddrbits, 2*ddrbits);
constant wbuf_wabits: integer := pick(ft/=0, l2blen-6, 1+l2blen-5);
constant wbuf_wdbits: integer := pick(ft/=0, xahbw+xahbw/2, xahbw);
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw;
constant rbuf_rdbits: integer := wbuf_wdbits;
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := pick(ft/=0, 3*ddrbits, 2*ddrbits);
signal request : ddr_request_type;
signal start_tog : std_logic;
signal response : ddr_response_type;
signal wbwaddr: std_logic_vector(wbuf_wabits-1 downto 0);
signal wbwdata: std_logic_vector(wbuf_wdbits-1 downto 0);
signal wbraddr: std_logic_vector(wbuf_rabits_s-1 downto 0);
signal wbrdata: std_logic_vector(wbuf_rdbits-1 downto 0);
signal rbwaddr: std_logic_vector(rbuf_wabits-1 downto 0);
signal rbwdata: std_logic_vector(rbuf_wdbits-1 downto 0);
signal rbraddr: std_logic_vector(rbuf_rabits-1 downto 0);
signal rbrdata: std_logic_vector(rbuf_rdbits-1 downto 0);
signal wbwrite,wbwritebig,rbwrite: std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of rbwdata : signal is true;
attribute syn_keep of rbwdata : signal is true;
attribute syn_preserve of rbwdata : signal is true;
signal vcc: std_ulogic;
signal sdox: ddrctrl_out_type;
signal ce: std_logic;
begin
vcc <= '1';
gft0: if ft=0 generate
ahbc : ddr2spax_ahb
generic map (hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
nosync => nosync, burstlen => burstlen, ahbbits => xahbw, revision => revision,
ddrbits => ddrbits, regarea => 0)
port map (ahb_rst, clk_ahb, ahbsi, ahbso, request, start_tog, response,
wbwaddr, wbwdata, wbwrite, wbwritebig, rbraddr, rbrdata, hwidth, FTFE_BEID_DDR2);
ce <= '0';
end generate;
gft1: if ft/=0 generate
ftc: ft_ddr2spax_ahb
generic map (hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
nosync => nosync, burstlen => burstlen, ahbbits => xahbw, bufbits => xahbw+xahbw/2,
ddrbits => ddrbits, hwidthen => hwidthen, devid => GAISLER_DDR2SP, revision => revision)
port map (ahb_rst, clk_ahb, ahbsi, ahbso, ce, request, start_tog, response,
wbwaddr, wbwdata, wbwrite, wbwritebig, rbraddr, rbrdata, hwidth, '0', open, open, FTFE_BEID_DDR2);
end generate;
ddrc : ddr2spax_ddr
generic map (ddrbits => ddrbits,
pwron => pwron, MHz => MHz, TRFC => TRFC, col => col, Mbyte => Mbyte,
readdly => readdly, odten => odten, octen => octen, dqsgating => dqsgating,
nosync => nosync, eightbanks => eightbanks, dqsse => dqsse, burstlen => burstlen,
chkbits => ft*ddrbits/2, bigmem => bigmem, raspipe => raspipe,
hwidthen => hwidthen, phytech => phytech, hasdqvalid => ddr2phy_has_datavalid(phytech),
rstdel => rstdel, phyptctrl => ddr2phy_ptctrl(phytech), scantest => scantest,
ddr_syncrst => ddr_syncrst)
port map (ddr_rst, clk_ddr, request, start_tog, response, sdi, sdox,
wbraddr, wbrdata, rbwaddr, rbwdata, rbwrite, hwidth,
'0', ddr_request_none, open, ahbsi.testen, ahbsi.testrst, ahbsi.testoen);
sdoproc: process(sdox,ce)
variable o: ddrctrl_out_type;
begin
o := sdox;
o.ce := ce;
sdo <= o;
end process;
wbuf: ddr2buf
generic map (tech => memtech, wabits => wbuf_wabits, wdbits => wbuf_wdbits,
rabits => wbuf_rabits_r, rdbits => wbuf_rdbits,
sepclk => 1, wrfst => ramwt)
port map ( rclk => clk_ddr, renable => vcc, raddress => wbraddr(wbuf_rabits_r-1 downto 0),
dataout => wbrdata, wclk => clk_ahb, write => wbwrite,
writebig => wbwritebig, waddress => wbwaddr, datain => wbwdata);
rbuf: ddr2buf
generic map (tech => memtech, wabits => rbuf_wabits, wdbits => rbuf_wdbits,
rabits => rbuf_rabits, rdbits => rbuf_rdbits,
sepclk => 1, wrfst => ramwt)
port map ( rclk => clk_ahb, renable => vcc, raddress => rbraddr,
dataout => rbrdata,
wclk => clk_ddr, write => rbwrite,
writebig => '0', waddress => rbwaddr, datain => rbwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddr2spa: DDR2 controller rev " &
tost(REVISION) & ", " & tost(ddrbits) & " bit width, " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
-------------------------------------------------------------------------------
-- (C) Copyright 2013-2015 Authors and the Free Software Foundation.
--
-- This file is part of OpenRIO.
--
-- OpenRIO is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- OpenRIO is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU General Lesser Public License
-- along with OpenRIO. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Description
-- This file containing an implementation of the transmission channel
-- independent parts of the LP-Serial Physical Layer Specification
-- (RapidIO 2.2, part 6).
--
-- Author(s):
-- - Magnus Rosenius, [email protected]
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RioSerial
--
-- clk - System clock.
-- areset_n - System reset. Asynchronous, active low.
--
-- portLinkTimeout_i - The number of ticks to wait for a packet-accepted before
-- a timeout occurrs.
-- linkInitialized_o - Indicates if a link partner is answering with valid
-- status-control-symbols.
-- inputPortEnable_i - Activate the input port for non-maintenance packets. If
-- deasserted, only non-maintenance packets are allowed.
-- outputPortEnable_i - Activate the output port for non-maintenance packets.
-- If deasserted, only non-maintenance packets are allowed.
--
-- This interface makes it possible to read and write ackId in both outbound
-- and inbound directions. All input signals are validated by localAckIdWrite.
-- localAckIdWrite_i - Indicate if a localAckId write operation is ongoing.
-- Usually this signal is high one tick.
-- clrOutstandingAckId_i - Clear outstanding ackId, i.e. reset the transmission
-- window. The signal is only read if localAckIdWrite_i is high.
-- inboundAckId_i - The value to set the inbound ackId (the ackId that the
-- next inbound packet should have) to. This signal is only read if localAckIdWrite
-- is high.
-- outstandingAckId_i - The value to set the outstanding ackId (the ackId
-- transmitted but not acknowledged) to. This signal is only read if localAckIdWrite
-- is high.
-- outboundAckId_i - The value to set the outbound ackId (the ackId that the
-- next outbound packet will have) to. This signal is only read if localAckIdWrite
-- is high.
-- inboundAckId_o - The current inbound ackId.
-- outstandingAckId_o - The current outstanding ackId.
-- outboundAckId_o - The current outbound ackId.
--
-- This is the interface to the packet buffering sublayer.
-- The window signals are used to send packets without removing them from the
-- memory storage. This way, many packet can be sent without awaiting
-- packet-accepted symbols and if a packet-accepted gets lost, it is possible
-- to revert and resend a packet. This is achived by reading readWindowEmpty
-- for new packet and asserting readWindowNext when a packet has been sent.
-- When the packet-accepted is received, readFrame should be asserted to remove the
-- packet from the storage. If a packet-accepted is missing, readWindowReset is
-- asserted to set the current packet to read to the one that has not received
-- a packet-accepted.
-- readFrameEmpty_i - Indicate if a packet is ready in the outbound direction.
-- Once deasserted, it is possible to read the packet content using
-- readContent_o to update readContentData and readContentEnd.
-- readFrame_o - Assert this signal for one tick to discard the oldest packet.
-- It should be used when a packet has been fully read, a linkpartner has
-- accepted it and the resources occupied by it should be returned to be
-- used for new packets.
-- readFrameRestart_o - Assert this signal to restart the reading of the
-- current packet. readContentData and readContentEnd will be reset to the
-- first content of the packet.
-- readFrameAborted_i - This signal is asserted if the current packet was
-- aborted while it was written. It is used when a transmitter starts to send a
-- packet before it has been fully received and it is cancelled before it is
-- completed. A one tick asserted readFrameRestart signal resets this signal.
-- readWindowEmpty_i - Indicate if there are more packets to send.
-- readWindowReset_o - Reset the current packet to the oldest stored in the memory.
-- readWindowNext_o - Indicate that a new packet should be read. Must only be
-- asserted if readWindowEmpty is deasserted. It should be high for one tick.
-- readContentEmpty_i - Indicate if there are any packet content to be read.
-- This signal is updated directly when packet content is written making it
-- possible to read packet content before the full packet has been written to
-- the memory storage.
-- readContent_o - Update readContentData and readContentEnd.
-- readContentEnd_i - Indicate if the end of the current packet has been
-- reached. When asserted, readContentData is not valid.
-- readContentData_i - The content of the current packet.
-- writeFrameFull_i - Indicate if the inbound packet storage is ready to accept
-- a new packet.
-- writeFrame_o - Indicate that a new complete inbound packet has been written.
-- writeFrameAbort_o - Indicate that the current packet is aborted and that all
-- data written for this packet should be discarded.
-- writeContent_o - Indicate that writeContentData is valid and should be
-- written into the packet content storage.
-- writeContentData_o - The content to write to the packet content storage.
--
-- This is the interface to the PCS (Physical Control Sublayer). Four types of
-- symbols exist, idle, control, data and error.
-- Idle symbols are transmitted when nothing else can be transmitted. They are
-- mainly intended to enforce a timing on the transmitted symbols. This is
-- needed to be able to guarantee that a status-control-symbol is transmitted
-- at least once every 256 symbol.
-- Control symbols contain control-symbols as described by the standard.
-- Data symbols contains a 32-bit fragment of a RapidIO packet.
-- Error symbols indicate that a corrupted symbol was received. This could be
-- used by a PCS layer to indicate that a transmission error was detected and
-- that the above layers should send link-requests to ensure the synchronism
-- between the link-partners.
-- The signals in this interface are:
-- portInitialized_i - An asserted signal on this pin indicates that the PCS
-- layer has established synchronization with the link and is ready to accept
-- symbols.
-- outboundSymbolEmpty_o - An asserted signal indicates that there are no
-- outbound symbols to read. Once deasserted, outboundSymbol_o will be
-- already be valid. This signal will be updated one tick after
-- outboundSymbolRead_i has been asserted.
-- outboundSymbolRead_i - Indicate that outboundSymbol_o has been read and a
-- new value could be accepted. It should be active for one tick.
-- outboundSymbol_o - The outbound symbol. The two MSB bits are the type of the
-- symbol.
-- bit 34-33
-- 00=IDLE, the rest of the bits are not used.
-- 01=CONTROL, the control symbols payload (24 bits) are placed in the MSB
-- part of the symbol data.
-- 10=ERROR, the rest of the bits are not used.
-- 11=DATA, all the remaining bits contain the data-symbol payload.
-- inboundSymbolFull_o - An asserted signal indicates that no more inbound
-- symbols can be accepted.
-- inboundSymbolWrite_i - Indicate that inboundSymbol_i contains valid
-- information that should be forwarded. Should be active for one tick.
-- inboundSymbol_i - The inbound symbol. See outboundSymbol_o for formating.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for RioSerial.
-------------------------------------------------------------------------------
entity RioSerial is
generic(
TIMEOUT_WIDTH : natural);
port(
-- System signals.
clk : in std_logic;
areset_n : in std_logic;
-- Status signals for maintenance operations.
portLinkTimeout_i : in std_logic_vector(TIMEOUT_WIDTH-1 downto 0);
linkInitialized_o : out std_logic;
inputPortEnable_i : in std_logic;
outputPortEnable_i : in std_logic;
linkUninitPacketDiscardActive_i : in std_logic;
-- Support for portLocalAckIdCSR.
localAckIdWrite_i : in std_logic;
clrOutstandingAckId_i : in std_logic;
inboundAckId_i : in std_logic_vector(4 downto 0);
outstandingAckId_i : in std_logic_vector(4 downto 0);
outboundAckId_i : in std_logic_vector(4 downto 0);
inboundAckId_o : out std_logic_vector(4 downto 0);
outstandingAckId_o : out std_logic_vector(4 downto 0);
outboundAckId_o : out std_logic_vector(4 downto 0);
-- Outbound frame interface.
readFrameEmpty_i : in std_logic;
readFrame_o : out std_logic;
readFrameRestart_o : out std_logic;
readFrameAborted_i : in std_logic;
readWindowEmpty_i : in std_logic;
readWindowReset_o : out std_logic;
readWindowNext_o : out std_logic;
readContentEmpty_i : in std_logic;
readContent_o : out std_logic;
readContentEnd_i : in std_logic;
readContentData_i : in std_logic_vector(31 downto 0);
-- Inbound frame interface.
writeFrameFull_i : in std_logic;
writeFrame_o : out std_logic;
writeFrameAbort_o : out std_logic;
writeContent_o : out std_logic;
writeContentData_o : out std_logic_vector(31 downto 0);
-- PCS layer signals.
portInitialized_i : in std_logic;
outboundSymbolEmpty_o : out std_logic;
outboundSymbolRead_i : in std_logic;
outboundSymbol_o : out std_logic_vector(33 downto 0);
inboundSymbolFull_o : out std_logic;
inboundSymbolWrite_i : in std_logic;
inboundSymbol_i : in std_logic_vector(33 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for RioSerial.
-------------------------------------------------------------------------------
architecture RioSerialImpl of RioSerial is
component RioFifo1 is
generic(
WIDTH : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
empty_o : out std_logic;
read_i : in std_logic;
data_o : out std_logic_vector(WIDTH-1 downto 0);
full_o : out std_logic;
write_i : in std_logic;
data_i : in std_logic_vector(WIDTH-1 downto 0));
end component;
component RioTransmitter is
generic(
TIMEOUT_WIDTH : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
portLinkTimeout_i : in std_logic_vector(TIMEOUT_WIDTH-1 downto 0);
portEnable_i : in std_logic;
linkUninitPacketDiscardActive_i : in std_logic;
localAckIdWrite_i : in std_logic;
clrOutstandingAckId_i : in std_logic;
outstandingAckId_i : in std_logic_vector(4 downto 0);
outboundAckId_i : in std_logic_vector(4 downto 0);
outstandingAckId_o : out std_logic_vector(4 downto 0);
outboundAckId_o : out std_logic_vector(4 downto 0);
portInitialized_i : in std_logic;
txFull_i : in std_logic;
txWrite_o : out std_logic;
txControl_o : out std_logic_vector(1 downto 0);
txData_o : out std_logic_vector(31 downto 0);
txControlEmpty_i : in std_logic;
txControlSymbol_i : in std_logic_vector(12 downto 0);
txControlUpdate_o : out std_logic;
rxControlEmpty_i : in std_logic;
rxControlSymbol_i : in std_logic_vector(12 downto 0);
rxControlUpdate_o : out std_logic;
linkInitialized_i : in std_logic;
linkInitialized_o : out std_logic;
ackIdStatus_i : in std_logic_vector(4 downto 0);
readFrameEmpty_i : in std_logic;
readFrame_o : out std_logic;
readFrameRestart_o : out std_logic;
readFrameAborted_i : in std_logic;
readWindowEmpty_i : in std_logic;
readWindowReset_o : out std_logic;
readWindowNext_o : out std_logic;
readContentEmpty_i : in std_logic;
readContent_o : out std_logic;
readContentEnd_i : in std_logic;
readContentData_i : in std_logic_vector(31 downto 0));
end component;
component RioReceiver is
port(
clk : in std_logic;
areset_n : in std_logic;
portEnable_i : in std_logic;
localAckIdWrite_i : in std_logic;
inboundAckId_i : in std_logic_vector(4 downto 0);
inboundAckId_o : out std_logic_vector(4 downto 0);
portInitialized_i : in std_logic;
rxEmpty_i : in std_logic;
rxRead_o : out std_logic;
rxControl_i : in std_logic_vector(1 downto 0);
rxData_i : in std_logic_vector(31 downto 0);
txControlWrite_o : out std_logic;
txControlSymbol_o : out std_logic_vector(12 downto 0);
rxControlWrite_o : out std_logic;
rxControlSymbol_o : out std_logic_vector(12 downto 0);
ackIdStatus_o : out std_logic_vector(4 downto 0);
linkInitialized_o : out std_logic;
writeFrameFull_i : in std_logic;
writeFrame_o : out std_logic;
writeFrameAbort_o : out std_logic;
writeContent_o : out std_logic;
writeContentData_o : out std_logic_vector(31 downto 0));
end component;
signal linkInitializedRx : std_logic;
signal linkInitializedTx : std_logic;
signal ackIdStatus : std_logic_vector(4 downto 0);
signal txControlWrite : std_logic;
signal txControlWriteSymbol : std_logic_vector(12 downto 0);
signal txControlReadEmpty : std_logic;
signal txControlRead : std_logic;
signal txControlReadSymbol : std_logic_vector(12 downto 0);
signal rxControlWrite : std_logic;
signal rxControlWriteSymbol : std_logic_vector(12 downto 0);
signal rxControlReadEmpty : std_logic;
signal rxControlRead : std_logic;
signal rxControlReadSymbol : std_logic_vector(12 downto 0);
signal outboundFull : std_logic;
signal outboundWrite : std_logic;
signal outboundControl : std_logic_vector(1 downto 0);
signal outboundData : std_logic_vector(31 downto 0);
signal outboundSymbol : std_logic_vector(33 downto 0);
signal inboundEmpty : std_logic;
signal inboundRead : std_logic;
signal inboundControl : std_logic_vector(1 downto 0);
signal inboundData : std_logic_vector(31 downto 0);
signal inboundSymbol : std_logic_vector(33 downto 0);
begin
linkInitialized_o <=
'1' when ((linkInitializedRx = '1') and (linkInitializedTx = '1')) else '0';
-----------------------------------------------------------------------------
-- Serial layer modules.
-----------------------------------------------------------------------------
Transmitter: RioTransmitter
generic map(
TIMEOUT_WIDTH=>TIMEOUT_WIDTH)
port map(
clk=>clk, areset_n=>areset_n,
portLinkTimeout_i=>portLinkTimeout_i,
portEnable_i=>outputPortEnable_i,
localAckIdWrite_i=>localAckIdWrite_i,
clrOutstandingAckId_i=>clrOutstandingAckId_i,
linkUninitPacketDiscardActive_i=>linkUninitPacketDiscardActive_i,
outstandingAckId_i=>outstandingAckId_i,
outboundAckId_i=>outboundAckId_i,
outstandingAckId_o=>outstandingAckId_o,
outboundAckId_o=>outboundAckId_o,
portInitialized_i=>portInitialized_i,
txFull_i=>outboundFull, txWrite_o=>outboundWrite,
txControl_o=>outboundControl, txData_o=>outboundData,
txControlEmpty_i=>txControlReadEmpty, txControlSymbol_i=>txControlReadSymbol,
txControlUpdate_o=>txControlRead,
rxControlEmpty_i=>rxControlReadEmpty, rxControlSymbol_i=>rxControlReadSymbol,
rxControlUpdate_o=>rxControlRead,
linkInitialized_o=>linkInitializedTx,
linkInitialized_i=>linkInitializedRx, ackIdStatus_i=>ackIdStatus,
readFrameEmpty_i=>readFrameEmpty_i, readFrame_o=>readFrame_o,
readFrameRestart_o=>readFrameRestart_o, readFrameAborted_i=>readFrameAborted_i,
readWindowEmpty_i=>readWindowEmpty_i,
readWindowReset_o=>readWindowReset_o, readWindowNext_o=>readWindowNext_o,
readContentEmpty_i=>readContentEmpty_i, readContent_o=>readContent_o,
readContentEnd_i=>readContentEnd_i, readContentData_i=>readContentData_i);
TxSymbolFifo: RioFifo1
generic map(WIDTH=>13)
port map(
clk=>clk, areset_n=>areset_n,
empty_o=>txControlReadEmpty, read_i=>txControlRead, data_o=>txControlReadSymbol,
full_o=>open, write_i=>txControlWrite, data_i=>txControlWriteSymbol);
RxSymbolFifo: RioFifo1
generic map(WIDTH=>13)
port map(
clk=>clk, areset_n=>areset_n,
empty_o=>rxControlReadEmpty, read_i=>rxControlRead, data_o=>rxControlReadSymbol,
full_o=>open, write_i=>rxControlWrite, data_i=>rxControlWriteSymbol);
Receiver: RioReceiver
port map(
clk=>clk, areset_n=>areset_n,
portEnable_i=>inputPortEnable_i,
localAckIdWrite_i=>localAckIdWrite_i,
inboundAckId_i=>inboundAckId_i,
inboundAckId_o=>inboundAckId_o,
portInitialized_i=>portInitialized_i,
rxEmpty_i=>inboundEmpty, rxRead_o=>inboundRead,
rxControl_i=>inboundControl, rxData_i=>inboundData,
txControlWrite_o=>txControlWrite, txControlSymbol_o=>txControlWriteSymbol,
rxControlWrite_o=>rxControlWrite, rxControlSymbol_o=>rxControlWriteSymbol,
ackIdStatus_o=>ackIdStatus,
linkInitialized_o=>linkInitializedRx,
writeFrameFull_i=>writeFrameFull_i,
writeFrame_o=>writeFrame_o, writeFrameAbort_o=>writeFrameAbort_o,
writeContent_o=>writeContent_o, writeContentData_o=>writeContentData_o);
-----------------------------------------------------------------------------
-- PCS layer FIFO interface.
-----------------------------------------------------------------------------
outboundSymbol <= outboundControl & outboundData;
OutboundSymbolFifo: RioFifo1
generic map(WIDTH=>34)
port map(
clk=>clk, areset_n=>areset_n,
empty_o=>outboundSymbolEmpty_o, read_i=>outboundSymbolRead_i, data_o=>outboundSymbol_o,
full_o=>outboundFull, write_i=>outboundWrite, data_i=>outboundSymbol);
inboundControl <= inboundSymbol(33 downto 32);
inboundData <= inboundSymbol(31 downto 0);
InboundSymbolFifo: RioFifo1
generic map(WIDTH=>34)
port map(
clk=>clk, areset_n=>areset_n,
empty_o=>inboundEmpty, read_i=>inboundRead, data_o=>inboundSymbol,
full_o=>inboundSymbolFull_o, write_i=>inboundSymbolWrite_i, data_i=>inboundSymbol_i);
end architecture;
-------------------------------------------------------------------------------
-- RioTransmitter
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for RioTransmitter.
-------------------------------------------------------------------------------
entity RioTransmitter is
generic(
TIMEOUT_WIDTH : natural);
port(
-- System signals.
clk : in std_logic;
areset_n : in std_logic;
-- Status signals used for maintenance.
portLinkTimeout_i : in std_logic_vector(TIMEOUT_WIDTH-1 downto 0);
portEnable_i : in std_logic;
linkUninitPacketDiscardActive_i : in std_logic;
-- Support for localAckIdCSR.
localAckIdWrite_i : in std_logic;
clrOutstandingAckId_i : in std_logic;
outstandingAckId_i : in std_logic_vector(4 downto 0);
outboundAckId_i : in std_logic_vector(4 downto 0);
outstandingAckId_o : out std_logic_vector(4 downto 0);
outboundAckId_o : out std_logic_vector(4 downto 0);
-- Port output interface.
portInitialized_i : in std_logic;
txFull_i : in std_logic;
txWrite_o : out std_logic;
txControl_o : out std_logic_vector(1 downto 0);
txData_o : out std_logic_vector(31 downto 0);
-- Control symbols aimed to the transmitter.
txControlEmpty_i : in std_logic;
txControlSymbol_i : in std_logic_vector(12 downto 0);
txControlUpdate_o : out std_logic;
-- Control symbols from the receiver to send.
rxControlEmpty_i : in std_logic;
rxControlSymbol_i : in std_logic_vector(12 downto 0);
rxControlUpdate_o : out std_logic;
-- Internal signalling from the receiver part.
linkInitialized_o : out std_logic;
linkInitialized_i : in std_logic;
ackIdStatus_i : in std_logic_vector(4 downto 0);
-- Frame buffer interface.
readFrameEmpty_i : in std_logic;
readFrame_o : out std_logic;
readFrameRestart_o : out std_logic;
readFrameAborted_i : in std_logic;
readWindowEmpty_i : in std_logic;
readWindowReset_o : out std_logic;
readWindowNext_o : out std_logic;
readContentEmpty_i : in std_logic;
readContent_o : out std_logic;
readContentEnd_i : in std_logic;
readContentData_i : in std_logic_vector(31 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for RioTransmitter.
-------------------------------------------------------------------------------
architecture RioTransmitterImpl of RioTransmitter is
constant NUMBER_STATUS_TRANSMIT : natural := 15;
constant NUMBER_LINK_RESPONSE_RETRIES : natural := 2;
constant NUMBER_PACKET_ERRORS_ALLOWED : natural := 3;
component MemorySimpleDualPortAsync is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1;
INIT_VALUE : std_logic := 'U');
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
component Crc5ITU is
port(
d_i : in std_logic_vector(18 downto 0);
crc_o : out std_logic_vector(4 downto 0));
end component;
type StateType is (STATE_UNINITIALIZED, STATE_PORT_INITIALIZED,
STATE_NORMAL,
STATE_OUTPUT_RETRY_STOPPED,
STATE_SEND_LINK_REQUEST, STATE_OUTPUT_ERROR_STOPPED,
STATE_RECOVER, STATE_FATAL_ERROR);
signal stateCurrent, stateNext : StateType;
signal statusReceivedCurrent, statusReceivedNext : std_logic;
signal counterCurrent, counterNext : natural range 0 to 15;
signal packetErrorCurrent, packetErrorNext : natural range 0 to NUMBER_PACKET_ERRORS_ALLOWED+1;
signal symbolsTransmittedCurrent, symbolsTransmittedNext : natural range 0 to 255;
type FrameStateType is (FRAME_START, FRAME_CHECK, FRAME_ACKID, FRAME_BODY, FRAME_END);
signal frameStateCurrent, frameStateNext : FrameStateType;
signal ackIdCurrent, ackIdNext : unsigned(4 downto 0) := (others=>'0');
signal ackIdWindowCurrent, ackIdWindowNext : unsigned(4 downto 0) := (others=>'0');
signal bufferStatusCurrent, bufferStatusNext : std_logic_vector(4 downto 0);
signal stype0 : std_logic_vector(2 downto 0);
signal parameter0 : std_logic_vector(4 downto 0);
signal parameter1 : std_logic_vector(4 downto 0);
signal stype1 : std_logic_vector(2 downto 0);
signal cmd : std_logic_vector(2 downto 0);
signal txControlStype0 : std_logic_vector(2 downto 0);
signal txControlParameter0 : std_logic_vector(4 downto 0);
signal txControlParameter1 : std_logic_vector(4 downto 0);
signal rxControlStype0 : std_logic_vector(2 downto 0);
signal rxControlParameter0 : std_logic_vector(4 downto 0);
signal rxControlParameter1 : std_logic_vector(4 downto 0);
signal symbolWrite : std_logic;
signal symbolType : std_logic_vector(1 downto 0);
signal symbolControl : std_logic_vector(31 downto 0);
signal symbolData : std_logic_vector(31 downto 0);
signal crcCalculated : std_logic_vector(4 downto 0);
signal timeoutWrite : std_logic;
signal timeoutCounter : unsigned(TIMEOUT_WIDTH downto 0);
signal timeoutFrame : unsigned(TIMEOUT_WIDTH downto 0);
signal timeoutElapsed : unsigned(TIMEOUT_WIDTH downto 0);
signal timeoutDelta : unsigned(TIMEOUT_WIDTH downto 0);
signal timeoutExpired : std_logic;
signal timeoutAddress : std_logic_vector(4 downto 0);
signal timeoutMemoryOut : std_logic_vector(TIMEOUT_WIDTH downto 0);
begin
linkInitialized_o <= '0' when ((stateCurrent = STATE_UNINITIALIZED) or
(stateCurrent = STATE_PORT_INITIALIZED)) else '1';
-----------------------------------------------------------------------------
-- Assign control symbol from fifo signals.
-----------------------------------------------------------------------------
txControlStype0 <= txControlSymbol_i(12 downto 10);
txControlParameter0 <= txControlSymbol_i(9 downto 5);
txControlParameter1 <= txControlSymbol_i(4 downto 0);
rxControlStype0 <= rxControlSymbol_i(12 downto 10);
rxControlParameter0 <= rxControlSymbol_i(9 downto 5);
rxControlParameter1 <= rxControlSymbol_i(4 downto 0);
-----------------------------------------------------------------------------
-- Outbound symbol creation logic.
-----------------------------------------------------------------------------
symbolControl(31 downto 29) <= stype0;
symbolControl(28 downto 24) <= parameter0;
symbolControl(23 downto 19) <= parameter1;
symbolControl(18 downto 16) <= stype1;
symbolControl(15 downto 13) <= cmd;
symbolControl(12 downto 8) <= crcCalculated;
symbolControl(7 downto 0) <= x"00";
Crc5Calculator: Crc5ITU
port map(
d_i=>symbolControl(31 downto 13), crc_o=>crcCalculated);
txWrite_o <= symbolWrite;
txControl_o <= symbolType;
txData_o <= symbolControl when (symbolType = SYMBOL_CONTROL) else symbolData;
-----------------------------------------------------------------------------
-- Packet timeout logic.
-----------------------------------------------------------------------------
-- Note that the timer is one bit larger to be able to detect a timeout on a
-- free-running counter.
process(areset_n, clk)
begin
if (areset_n = '0') then
timeoutCounter <= (others=>'0');
elsif (clk'event and clk = '1') then
timeoutCounter <= timeoutCounter + 1;
end if;
end process;
timeoutElapsed <= timeoutCounter - timeoutFrame;
timeoutDelta <= unsigned('0' & portLinkTimeout_i) - timeoutElapsed;
timeoutExpired <= timeoutDelta(TIMEOUT_WIDTH);
timeoutFrame <= unsigned(timeoutMemoryOut);
TimeoutMemory: MemorySimpleDualPortAsync
generic map(ADDRESS_WIDTH=>5, DATA_WIDTH=>TIMEOUT_WIDTH+1, INIT_VALUE=>'0')
port map(
clkA_i=>clk, enableA_i=>timeoutWrite,
addressA_i=>timeoutAddress, dataA_i=>std_logic_vector(timeoutCounter),
addressB_i=>std_logic_vector(ackIdCurrent), dataB_o=>timeoutMemoryOut);
-----------------------------------------------------------------------------
-- Main outbound symbol handler, synchronous part.
-----------------------------------------------------------------------------
process(areset_n, clk)
begin
if (areset_n = '0') then
stateCurrent <= STATE_UNINITIALIZED;
statusReceivedCurrent <= '0';
counterCurrent <= 0;
packetErrorCurrent <= 0;
symbolsTransmittedCurrent <= 0;
frameStateCurrent <= FRAME_START;
ackIdCurrent <= (others => '0');
ackIdWindowCurrent <= (others => '0');
bufferStatusCurrent <= (others => '0');
elsif (clk'event and clk = '1') then
stateCurrent <= stateNext;
statusReceivedCurrent <= statusReceivedNext;
counterCurrent <= counterNext;
packetErrorCurrent <= packetErrorNext;
symbolsTransmittedCurrent <= symbolsTransmittedNext;
frameStateCurrent <= frameStateNext;
ackIdCurrent <= ackIdNext;
ackIdWindowCurrent <= ackIdWindowNext;
bufferStatusCurrent <= bufferStatusNext;
end if;
end process;
-----------------------------------------------------------------------------
-- Main outbound symbol handler, combinatorial part.
-----------------------------------------------------------------------------
process(stateCurrent,
statusReceivedCurrent, counterCurrent, packetErrorCurrent,
symbolsTransmittedCurrent,
frameStateCurrent, ackIdCurrent, ackIdWindowCurrent, bufferStatusCurrent,
txControlStype0, txControlParameter0, txControlParameter1,
rxControlStype0, rxControlParameter0, rxControlParameter1,
portEnable_i, linkUninitPacketDiscardActive_i,
localAckIdWrite_i, clrOutstandingAckId_i,
outstandingAckId_i, outboundAckId_i,
txFull_i,
txControlEmpty_i, txControlSymbol_i,
rxControlEmpty_i, rxControlSymbol_i,
portInitialized_i, linkInitialized_i, ackIdStatus_i,
readFrameEmpty_i, readFrameAborted_i,
readWindowEmpty_i,
readContentEmpty_i, readContentEnd_i, readContentData_i,
timeoutExpired)
begin
stateNext <= stateCurrent;
statusReceivedNext <= statusReceivedCurrent;
counterNext <= counterCurrent;
packetErrorNext <= packetErrorCurrent;
symbolsTransmittedNext <= symbolsTransmittedCurrent;
frameStateNext <= frameStateCurrent;
ackIdNext <= ackIdCurrent;
ackIdWindowNext <= ackIdWindowCurrent;
bufferStatusNext <= bufferStatusCurrent;
txControlUpdate_o <= '0';
rxControlUpdate_o <= '0';
readFrame_o <= '0';
readFrameRestart_o <= '0';
readWindowReset_o <= '0';
readWindowNext_o <= '0';
readContent_o <= '0';
symbolWrite <= '0';
symbolType <= (others=>'U');
stype0 <= (others=>'U');
parameter0 <= (others=>'U');
parameter1 <= (others=>'U');
stype1 <= (others=>'U');
cmd <= (others=>'U');
symbolData <= (others=>'U');
timeoutWrite <= '0';
timeoutAddress <= (others=>'U');
outstandingAckId_o <= std_logic_vector(ackIdCurrent);
outboundAckId_o <= std_logic_vector(ackIdWindowCurrent);
-- Check if a localAckIdWrite is active.
if (localAckIdWrite_i = '1') then
-- A localAckIdWrite is active.
-- Check if all outstanding packets should be discarded.
if (clrOutstandingAckId_i = '1') then
-- Delete all outbound packets.
-- REMARK: Remove all packets in another way... what if uninitialized???
stateNext <= STATE_RECOVER;
end if;
-- Set ackIds.
ackIdNext <= unsigned(outstandingAckId_i);
ackIdWindowNext <= unsigned(outboundAckId_i);
else
-- A localAckIdWrite is not active.
-- Act on the current state.
case (stateCurrent) is
when STATE_UNINITIALIZED =>
-----------------------------------------------------------------------
-- This state is entered at startup. A port that is not initialized
-- should only transmit idle sequences.
-----------------------------------------------------------------------
-- Check if the port is initialized.
if (portInitialized_i = '0') then
-- Port not initialized.
-- Check if any new symbols from the link partner has been received.
if (txControlEmpty_i = '0') then
-- New symbols have been received.
-- Discard all new symbols in this state.
txControlUpdate_o <= '1';
else
-- No new symbols from the link partner.
-- Dont do anything.
end if;
-- Check if any new symbols should be transmitted to the link partner.
if (rxControlEmpty_i = '0') then
-- New symbols should be transmitted.
-- Do not forward any symbols in this state.
rxControlUpdate_o <= '1';
else
-- No new symbols to transmit.
-- Dont do anything.
end if;
-- Check if a new symbol should be transmitted.
if (txFull_i = '0') then
-- A new symbol should be transmitted.
-- Send idle sequence.
symbolWrite <= '1';
symbolType <= SYMBOL_IDLE;
else
-- The outbound fifo is full.
-- Dont do anything.
end if;
-- Check if a new full packet is ready.
if (readFrameEmpty_i = '0') then
-- A new full packet is ready.
-- It is not possible to send the packet now. If the packet is not
-- discarded it might congest the full system if the link does not
-- go initialized. To avoid a congested switch, the packet is
-- discarded and will have to be resent by the source when the link
-- is up and running.
-- First check if the linkUninitPacketDiscardActive timer is running.
if (linkUninitPacketDiscardActive_i = '0') then
-- The timer is not active.
-- It is ok to discard the packet.
readFrame_o <= '1';
end if;
else
-- No new full packets are ready.
-- Dont do anything.
end if;
else
-- Port is initialized.
-- Go to the initialized state and reset the counters.
statusReceivedNext <= '0';
counterNext <= NUMBER_STATUS_TRANSMIT;
symbolsTransmittedNext <= 0;
stateNext <= STATE_PORT_INITIALIZED;
end if;
when STATE_PORT_INITIALIZED =>
-----------------------------------------------------------------------
-- The specification requires a status control symbol being sent at
-- least every 1024 code word until an error-free status has been
-- received. This implies that at most 256 idle sequences should be
-- sent in between status control symbols. Once an error-free status has
-- been received, status symbols may be sent more rapidly. At least 15
-- statuses has to be transmitted once an error-free status has been
-- received.
---------------------------------------------------------------------
-- Check if the port is initialized.
if (portInitialized_i = '1') then
-- Port is initialized.
-- Check if we are ready to change state to linkInitialized.
if ((linkInitialized_i = '1') and (counterCurrent = 0)) then
-- Receiver has received enough error free status symbols and we have
-- transmitted enough.
-- Initialize framing before entering the normal state.
ackIdWindowNext <= ackIdCurrent;
frameStateNext <= FRAME_START;
readWindowReset_o <= '1';
-- Considder the link initialized.
stateNext <= STATE_NORMAL;
else
-- Not ready to change state to linkInitialized.
-- Dont do anything.
end if;
-- Check if any new symbols from the link partner has been received.
if (txControlEmpty_i = '0') then
-- New symbols have been received.
-- Check if the new symbol is a status.
if (txControlStype0 = STYPE0_STATUS) then
-- A new status control symbol has been received.
statusReceivedNext <= '1';
-- Set the ackId and the linkpartner buffer status to what is indicated
-- in the received control symbol.
ackIdNext <= unsigned(txControlParameter0);
bufferStatusNext <= txControlParameter1;
packetErrorNext <= 0;
else
-- Did not receive a status control symbol.
-- Discard it.
end if;
-- Update to the next control symbol received by the receiver.
txControlUpdate_o <= '1';
else
-- No new symbols from the link partner.
-- Dont do anything.
end if;
-- Check if any new symbols should be transmitted to the link partner.
if (rxControlEmpty_i = '0') then
-- New symbols should be transmitted.
-- Do not forward any symbols in this state.
rxControlUpdate_o <= '1';
else
-- No new symbols to transmit.
-- Dont do anything.
end if;
-- Check if a new symbol may be transmitted.
if (txFull_i = '0') then
-- A new symbol can be transmitted.
-- Check if idle sequence or a status symbol should be transmitted.
if (((statusReceivedCurrent = '0') and (symbolsTransmittedCurrent = 255)) or
((statusReceivedCurrent = '1') and (symbolsTransmittedCurrent > 15))) then
-- A status symbol should be transmitted.
-- Send a status control symbol to the link partner.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= STYPE0_STATUS;
parameter0 <= ackIdStatus_i;
parameter1 <= "11111";
stype1 <= STYPE1_NOP;
cmd <= "000";
-- Reset idle sequence transmission counter.
symbolsTransmittedNext <= 0;
-- Check if the number of transmitted statuses should be updated.
if (statusReceivedCurrent = '1') and (counterCurrent /= 0) then
counterNext <= counterCurrent - 1;
end if;
else
-- A idle sequence should be transmitted.
symbolWrite <= '1';
symbolType <= SYMBOL_IDLE;
-- Increment the idle sequence transmission counter.
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
end if;
else
-- Cannot send a new symbol.
-- Dont do anything.
end if;
else
-- Go back to the uninitialized state.
stateNext <= STATE_UNINITIALIZED;
end if;
when STATE_NORMAL =>
-------------------------------------------------------------------
-- This state is the normal state. It relays frames and handle flow
-- control.
-------------------------------------------------------------------
-- Check that both the port and link is initialized.
if (portInitialized_i = '1') and (linkInitialized_i = '1') then
-- The port and link is initialized.
-- Check if any control symbol has been received from the link
-- partner.
if (txControlEmpty_i = '0') then
-- A control symbol has been received.
-- Check the received control symbol.
case txControlStype0 is
when STYPE0_STATUS =>
-- Save the number of buffers in the link partner.
bufferStatusNext <= txControlParameter1;
when STYPE0_PACKET_ACCEPTED =>
-- The link partner is accepting a frame.
-- Save the number of buffers in the link partner.
bufferStatusNext <= txControlParameter1;
-- Check if expecting this type of reply and that the ackId is
-- expected.
if ((ackIdCurrent /= ackIdWindowCurrent) and
(ackIdCurrent = unsigned(txControlParameter0))) then
-- The packet-accepted is expected and the ackId is the expected.
-- The frame has been accepted by the link partner.
-- Update to a new buffer and increment the ackId.
readFrame_o <= '1';
ackIdNext <= ackIdCurrent + 1;
packetErrorNext <= 0;
else
-- Unexpected packet-accepted or packet-accepted for
-- unexpected ackId.
counterNext <= NUMBER_LINK_RESPONSE_RETRIES;
stateNext <= STATE_SEND_LINK_REQUEST;
end if;
when STYPE0_PACKET_RETRY =>
-- The link partner has asked for a frame retransmission.
-- Save the number of buffers in the link partner.
bufferStatusNext <= txControlParameter1;
-- Check if the ackId is the one expected.
if (ackIdCurrent = unsigned(txControlParameter0)) then
-- The ackId to retry is expected.
-- Go to the output-retry-stopped state.
stateNext <= STATE_OUTPUT_RETRY_STOPPED;
else
-- Unexpected ackId to retry.
counterNext <= NUMBER_LINK_RESPONSE_RETRIES;
stateNext <= STATE_SEND_LINK_REQUEST;
end if;
when STYPE0_PACKET_NOT_ACCEPTED =>
-- Packet was rejected by the link-partner.
-- REMARK: Indicate that this has happened to the outside...
counterNext <= NUMBER_LINK_RESPONSE_RETRIES;
stateNext <= STATE_SEND_LINK_REQUEST;
when STYPE0_LINK_RESPONSE =>
-- Dont expect or need a link-response in this state.
-- Discard it.
when STYPE0_VC_STATUS =>
-- Not supported.
-- Discard it.
when STYPE0_RESERVED =>
-- Not supported.
-- Discard it.
when STYPE0_IMPLEMENTATION_DEFINED =>
-- Not supported.
-- Discard it.
when others =>
null;
end case;
-- Indicate the control symbol has been processed.
txControlUpdate_o <= '1';
else
-- No control symbol has been received.
-- Check if the oldest frame timeout has expired.
if ((ackIdCurrent /= ackIdWindowCurrent) and
(timeoutExpired = '1')) then
-- There has been a timeout on a transmitted frame.
-- Send link-request.
counterNext <= NUMBER_LINK_RESPONSE_RETRIES;
stateNext <= STATE_SEND_LINK_REQUEST;
else
-- There has been no timeout.
-- Check if the outbound fifo needs new data.
if (txFull_i = '0') then
-- There is room available in the outbound FIFO.
-- Check if there are any events from the receiver.
if (rxControlEmpty_i = '0') then
-- A symbol from the receiver should be transmitted.
-- Send the receiver symbol and a NOP.
-- REMARK: Combine this symbol with an STYPE1 to more effectivly
-- utilize the link.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= rxControlStype0;
parameter0 <= rxControlParameter0;
parameter1 <= rxControlParameter1;
stype1 <= STYPE1_NOP;
cmd <= "000";
-- Remove the symbol from the fifo.
rxControlUpdate_o <= '1';
-- Check if the transmitted symbol contains status about
-- available buffers.
if ((rxControlStype0 = STYPE0_PACKET_ACCEPTED) or
(rxControlStype0 = STYPE0_PACKET_RETRY)) then
-- A symbol containing the bufferStatus has been sent.
symbolsTransmittedNext <= 0;
else
-- A symbol not containing the bufferStatus has been sent.
-- REMARK: symbolsTransmitted might overflow...
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
end if;
else
-- No events from the receiver.
-- Check if a status symbol must be sent.
if (symbolsTransmittedCurrent = 255) then
-- A status symbol must be sent.
-- Reset the number of transmitted symbols between statuses.
symbolsTransmittedNext <= 0;
-- Send status.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= STYPE0_STATUS;
parameter0 <= ackIdStatus_i;
parameter1 <= "11111";
stype1 <= STYPE1_NOP;
cmd <= "000";
else
-- A status symbol does not have to be sent.
-- Check if a frame transfer is in progress.
case frameStateCurrent is
when FRAME_START =>
---------------------------------------------------------------
-- No frame has been started.
---------------------------------------------------------------
-- Wait for a new frame to arrive from the frame buffer,
-- for new buffers to be available at the link-partner
-- and also check that a maximum 31 frames are outstanding.
if ((readWindowEmpty_i = '0') and (bufferStatusCurrent /= "00000") and
((ackIdWindowCurrent - ackIdCurrent) /= 31)) then
-- New data is available for transmission and there
-- is room to receive it at the other side.
-- Indicate that a control symbol has been sent to start the
-- transmission of the frame.
frameStateNext <= FRAME_CHECK;
-- Update the output from the frame buffer to contain the
-- data when it is read later.
readContent_o <= '1';
else
-- There are no frame data to send or the link partner has
-- no available buffers.
-- Send idle-sequence.
symbolWrite <= '1';
symbolType <= SYMBOL_IDLE;
-- A symbol not containing the buffer status has been sent.
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
end if;
when FRAME_CHECK =>
-------------------------------------------------------
-- Check if we are allowed to transmit this packet.
-------------------------------------------------------
-- Check if this packet is allowed to be transmitted.
if ((portEnable_i = '1') or (readContentData_i(19 downto 16) = FTYPE_MAINTENANCE_CLASS)) then
-- The packet may be transmitted.
-- Indicate that a control symbol has been sent to start the
-- transmission of the frame.
frameStateNext <= FRAME_ACKID;
-- Send a control symbol to start the packet and a status to complete
-- the symbol.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= STYPE0_STATUS;
parameter0 <= ackIdStatus_i;
parameter1 <= "11111";
stype1 <= STYPE1_START_OF_PACKET;
cmd <= "000";
-- A symbol containing the bufferStatus has been sent.
symbolsTransmittedNext <= 0;
else
-- The packet should be discarded.
-- Check that there are no outstanding packets that
-- has not been acknowledged.
if(ackIdWindowCurrent /= ackIdCurrent) then
-- There are packets that has not been acknowledged.
-- Send idle-sequence.
symbolWrite <= '1';
symbolType <= SYMBOL_IDLE;
-- A symbol not containing the buffer status has been sent.
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
else
-- No unacknowledged packets.
-- It is now safe to remove the unallowed frame.
readFrame_o <= '1';
-- Go back and send a new frame.
frameStateNext <= FRAME_START;
end if;
end if;
when FRAME_ACKID =>
---------------------------------------------------------------
-- Send the first packet content containing our current
-- ackId.
---------------------------------------------------------------
-- Write a new data symbol and fill in our ackId on the
-- packet.
symbolWrite <= '1';
symbolType <= SYMBOL_DATA;
symbolData <= std_logic_vector(ackIdWindowCurrent) & "0" & readContentData_i(25 downto 0);
-- Continue to send the rest of the body of the packet.
readContent_o <= '1';
frameStateNext <= FRAME_BODY;
-- A symbol not containing the buffer status has been sent.
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
when FRAME_BODY =>
---------------------------------------------------------------
-- The frame has not been fully sent.
-- Send a data symbol.
---------------------------------------------------------------
-- REMARK: Add support for partial frames...
-- Check if the frame is ending.
if (readContentEnd_i = '0') then
-- The frame is not ending.
-- Write a new data symbol.
symbolWrite <= '1';
symbolType <= SYMBOL_DATA;
symbolData <= readContentData_i;
-- Continue to send the rest of the body of the packet.
readContent_o <= '1';
-- A symbol not containing the buffer status has been sent.
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
else
-- The frame is ending.
-- Update the window to the next frame.
-- It takes one tick for the output from the frame
-- buffer to get updated.
readWindowNext_o <= '1';
-- Proceed to check if there is another frame to start
-- with directly.
frameStateNext <= FRAME_END;
end if;
when FRAME_END =>
---------------------------------------------------------------
-- A frame has ended and the window has been updated.
-- Check if the next symbol should end the frame or if a
-- new one should be started.
---------------------------------------------------------------
-- Check if there is a new frame pending.
if (readWindowEmpty_i = '1') then
-- No new frame is pending.
-- Send a control symbol to end the packet.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= STYPE0_STATUS;
parameter0 <= ackIdStatus_i;
parameter1 <= "11111";
stype1 <= STYPE1_END_OF_PACKET;
cmd <= "000";
-- A symbol containing the bufferStatus has been sent.
symbolsTransmittedNext <= 0;
end if;
-- Update the window ackId.
ackIdWindowNext <= ackIdWindowCurrent + 1;
-- Start timeout supervision for transmitted frame.
timeoutWrite <= '1';
timeoutAddress <= std_logic_vector(ackIdWindowCurrent);
-- Start a new frame the next time.
frameStateNext <= FRAME_START;
when others =>
---------------------------------------------------------------
--
---------------------------------------------------------------
null;
end case;
end if;
end if;
else
-- Wait for new storage in the transmission FIFO to become
-- available.
-- Dont do anything.
end if;
end if;
end if;
else
-- The port or the link has become uninitialized.
-- Go back to the uninitialized state.
stateNext <= STATE_UNINITIALIZED;
end if;
when STATE_OUTPUT_RETRY_STOPPED =>
-----------------------------------------------------------------------
-- This is the output-retry-stopped state described in 5.9.1.5.
-----------------------------------------------------------------------
-- Check if the outbound fifo needs new data.
if (txFull_i = '0') then
-- There is room available in the outbound FIFO.
-- Send a restart-from-retry control symbol to acknowledge the restart
-- of the frame.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= STYPE0_STATUS;
parameter0 <= ackIdStatus_i;
parameter1 <= "11111";
stype1 <= STYPE1_RESTART_FROM_RETRY;
cmd <= "000";
-- Make sure there wont be any timeout before the frame is
-- starting to be retransmitted.
timeoutWrite <= '1';
timeoutAddress <= std_logic_vector(ackIdCurrent);
-- Restart the frame transmission.
ackIdWindowNext <= ackIdCurrent;
frameStateNext <= FRAME_START;
readWindowReset_o <= '1';
-- Proceed back to the normal state.
stateNext <= STATE_NORMAL;
-- A symbol containing the bufferStatus has been sent.
symbolsTransmittedNext <= 0;
end if;
when STATE_SEND_LINK_REQUEST =>
-----------------------------------------------------------------------
-- Send a link-request symbol when the transmission fifo is ready. Then
-- always proceed to the output-error-state.
-----------------------------------------------------------------------
-- Check if the outbound fifo needs new data.
if (txFull_i = '0') then
-- There is room available in the outbound FIFO.
-- Send a link-request symbol.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= STYPE0_STATUS;
parameter0 <= ackIdStatus_i;
parameter1 <= "11111";
stype1 <= STYPE1_LINK_REQUEST;
cmd <= LINK_REQUEST_CMD_INPUT_STATUS;
-- Write the current timer value.
timeoutWrite <= '1';
timeoutAddress <= std_logic_vector(ackIdCurrent);
-- Proceed to the output-error-stopped state.
stateNext <= STATE_OUTPUT_ERROR_STOPPED;
-- A symbol containing the bufferStatus has been sent.
symbolsTransmittedNext <= 0;
end if;
when STATE_OUTPUT_ERROR_STOPPED =>
-------------------------------------------------------------------
-- This state is the error stopped state described in 5.13.2.7.
-------------------------------------------------------------------
-- Check that both the port and link is initialized.
if (portInitialized_i = '1') and (linkInitialized_i = '1') then
-- The port and link is initialized.
-- Check if any control symbol has been received from the link
-- partner.
if (txControlEmpty_i = '0') then
-- A control symbol has been received.
-- Check the received control symbol.
case txControlStype0 is
when STYPE0_PACKET_ACCEPTED =>
-- Wait for a link-response.
-- Discard these.
when STYPE0_PACKET_RETRY =>
-- Wait for a link-response.
-- Discard these.
when STYPE0_PACKET_NOT_ACCEPTED =>
-- Wait for a link-response.
-- Discard these.
when STYPE0_STATUS =>
-- Wait for a link-response.
-- Discard these.
when STYPE0_LINK_RESPONSE =>
-- Check if the link partner return value is acceptable.
if ((unsigned(txControlParameter0) - ackIdCurrent) <=
(ackIdWindowCurrent - ackIdCurrent)) then
-- Recoverable error.
-- Use the received ackId and recover by removing packets
-- that were received by the link-partner.
ackIdWindowNext <= unsigned(txControlParameter0);
stateNext <= STATE_RECOVER;
else
-- Totally out of sync.
stateNext <= STATE_FATAL_ERROR;
end if;
when STYPE0_VC_STATUS =>
-- Not supported.
when STYPE0_RESERVED =>
-- Not supported.
when STYPE0_IMPLEMENTATION_DEFINED =>
-- Not supported.
when others =>
null;
end case;
-- Indicate the control symbol has been processed.
txControlUpdate_o <= '1';
else
-- No control symbol has been received.
-- Check if the timeout for a link-response has expired.
if (timeoutExpired = '1') then
-- There was no reply on the link-request.
-- Count the number of retransmissions and abort if
-- no reply has been received for too many times.
if (counterCurrent /= 0) then
-- Not sent link-request too many times.
-- Send another link-request.
counterNext <= counterCurrent - 1;
stateNext <= STATE_SEND_LINK_REQUEST;
else
-- No response for too many times.
stateNext <= STATE_FATAL_ERROR;
end if;
else
-- There has been no timeout.
-- Check if the outbound fifo needs new data.
if (txFull_i = '0') then
-- There is room available in the outbound FIFO.
-- Check if there are any events from the receiver.
if (rxControlEmpty_i = '0') then
-- A symbol from the receiver should be transmitted.
-- Send the receiver symbol and a NOP.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= rxControlStype0;
parameter0 <= rxControlParameter0;
parameter1 <= rxControlParameter1;
stype1 <= STYPE1_NOP;
cmd <= "000";
-- Remove the symbol from the fifo.
rxControlUpdate_o <= '1';
-- Check if the transmitted symbol contains status about
-- available buffers.
-- The receiver never send any status so that does not have
-- to be checked.
if ((rxControlStype0 = STYPE0_PACKET_ACCEPTED) or
(rxControlStype0 = STYPE0_PACKET_RETRY)) then
-- A symbol containing the bufferStatus has been sent.
symbolsTransmittedNext <= 0;
else
-- A symbol not containing the buffer status has been sent.
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
end if;
else
-- No events from the receiver.
-- There are no frame data to send or the link partner has
-- no available buffers.
-- Check if a status symbol must be sent.
if (symbolsTransmittedCurrent = 255) then
-- A status symbol must be sent.
-- Reset the number of transmitted symbols between statuses.
symbolsTransmittedNext <= 0;
-- Send status.
symbolWrite <= '1';
symbolType <= SYMBOL_CONTROL;
stype0 <= STYPE0_STATUS;
parameter0 <= ackIdStatus_i;
parameter1 <= "11111";
stype1 <= STYPE1_NOP;
cmd <= "000";
else
-- A status symbol does not have to be sent.
-- Send idle-sequence.
symbolWrite <= '1';
symbolType <= SYMBOL_IDLE;
-- A symbol not containing the buffer status has been sent.
symbolsTransmittedNext <= symbolsTransmittedCurrent + 1;
end if;
end if;
else
-- Wait for new storage in the transmission FIFO to become
-- available.
-- Dont do anything.
end if;
end if;
end if;
else
-- The port or the link has become uninitialized.
-- Go back to the uninitialized state.
stateNext <= STATE_UNINITIALIZED;
end if;
when STATE_RECOVER =>
-----------------------------------------------------------------------
-- A recoverable error condition has occurred.
-- When this state is entered, ackIdWindow should contain the ackId to
-- proceed with.
-----------------------------------------------------------------------
-- Check if the expected ackId has incremented enough.
if (ackIdCurrent /= ackIdWindowCurrent) then
-- Remove this frame. It has been received by the link-partner.
readFrame_o <= '1';
ackIdNext <= ackIdCurrent + 1;
packetErrorNext <= 0;
elsif (packetErrorCurrent = NUMBER_PACKET_ERRORS_ALLOWED) then
-- Remove this frame. It has been rejected by the link-partner too
-- many times.
packetErrorNext <= packetErrorCurrent + 1;
readFrame_o <= '1';
else
-- Keep this frame.
-- Restart the window and the frame transmission.
frameStateNext <= FRAME_START;
readWindowReset_o <= '1';
stateNext <= STATE_NORMAL;
if (packetErrorCurrent /= NUMBER_PACKET_ERRORS_ALLOWED+1) then
packetErrorNext <= packetErrorCurrent + 1;
else
packetErrorNext <= 0;
end if;
end if;
when STATE_FATAL_ERROR =>
-----------------------------------------------------------------------
-- A fatal error condition has occurred.
-----------------------------------------------------------------------
-- Reset the window and resynchronize the link.
-- REMARK: Count these situations...
-- REMARK: Do something else here???
readWindowReset_o <= '1';
stateNext <= STATE_UNINITIALIZED;
when others =>
-------------------------------------------------------------------
--
-------------------------------------------------------------------
null;
end case;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
entity RioReceiver is
port(
clk : in std_logic;
areset_n : in std_logic;
-- Status signals used for maintenance.
portEnable_i : in std_logic;
-- Support for localAckIdCSR.
localAckIdWrite_i : in std_logic;
inboundAckId_i : in std_logic_vector(4 downto 0);
inboundAckId_o : out std_logic_vector(4 downto 0);
-- Port input interface.
portInitialized_i : in std_logic;
rxEmpty_i : in std_logic;
rxRead_o : out std_logic;
rxControl_i : in std_logic_vector(1 downto 0);
rxData_i : in std_logic_vector(31 downto 0);
-- Receiver has received a control symbol containing:
-- packet-accepted, packet-retry, packet-not-accepted,
-- status, VC_status, link-response
txControlWrite_o : out std_logic;
txControlSymbol_o : out std_logic_vector(12 downto 0);
-- Reciever wants to signal the link partner:
-- a new frame has been accepted => packet-accepted(rxAckId, bufferStatus)
-- a frame needs to be retransmitted due to buffering =>
-- packet-retry(rxAckId, bufferStatus)
-- a frame is rejected due to errors => packet-not-accepted
-- a link-request should be answered => link-response
rxControlWrite_o : out std_logic;
rxControlSymbol_o : out std_logic_vector(12 downto 0);
-- Status signals used internally.
ackIdStatus_o : out std_logic_vector(4 downto 0);
linkInitialized_o : out std_logic;
-- Frame buffering interface.
writeFrameFull_i : in std_logic;
writeFrame_o : out std_logic;
writeFrameAbort_o : out std_logic;
writeContent_o : out std_logic;
writeContentData_o : out std_logic_vector(31 downto 0));
end entity;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
architecture RioReceiverImpl of RioReceiver is
component Crc5ITU is
port(
d_i : in std_logic_vector(18 downto 0);
crc_o : out std_logic_vector(4 downto 0));
end component;
component Crc16CITT is
port(
d_i : in std_logic_vector(15 downto 0);
crc_i : in std_logic_vector(15 downto 0);
crc_o : out std_logic_vector(15 downto 0));
end component;
type StateType is (STATE_UNINITIALIZED, STATE_PORT_INITIALIZED,
STATE_NORMAL,
STATE_INPUT_RETRY_STOPPED, STATE_INPUT_ERROR_STOPPED);
signal state : StateType;
signal statusCounter : natural range 0 to 7;
signal ackId : unsigned(4 downto 0);
signal frameIndex : natural range 0 to 70;
signal stype0 : std_logic_vector(2 downto 0);
signal parameter0 : std_logic_vector(4 downto 0);
signal parameter1 : std_logic_vector(4 downto 0);
signal stype1 : std_logic_vector(2 downto 0);
signal cmd : std_logic_vector(2 downto 0);
signal crc5 : std_logic_vector(4 downto 0);
signal crc5Calculated : std_logic_vector(4 downto 0);
signal crc16Valid : std_logic;
signal crc16Data : std_logic_vector(31 downto 0);
signal crc16Current : std_logic_vector(15 downto 0);
signal crc16Temp : std_logic_vector(15 downto 0);
signal crc16Next : std_logic_vector(15 downto 0);
signal rxRead : std_logic;
begin
linkInitialized_o <= '0' when ((state = STATE_UNINITIALIZED) or
(state = STATE_PORT_INITIALIZED)) else '1';
ackIdStatus_o <= std_logic_vector(ackId);
-----------------------------------------------------------------------------
-- Get the entries in a control symbol.
-----------------------------------------------------------------------------
stype0 <= rxData_i(31 downto 29);
parameter0 <= rxData_i(28 downto 24);
parameter1 <= rxData_i(23 downto 19);
stype1 <= rxData_i(18 downto 16);
cmd <= rxData_i(15 downto 13);
crc5 <= rxData_i(12 downto 8);
-----------------------------------------------------------------------------
-- Entity for CRC-5 calculation on control symbols according to the standard.
-----------------------------------------------------------------------------
Crc5Calculator: Crc5ITU
port map(
d_i=>rxData_i(31 downto 13), crc_o=>crc5Calculated);
-----------------------------------------------------------------------------
-- Entities for CRC-16 calculation on 32-bit data in frames according to the
-- standard.
-----------------------------------------------------------------------------
-- If the CRC is correct, there is either zero in crc16Next if no pad exists
-- or zero in crc16Temp and crc16Data(15 downto 0). This means that crc16Next
-- will always be zero here if the CRC is correct.
crc16Valid <= '1' when (crc16Next = x"0000") else '0';
Crc16High: Crc16CITT
port map(
d_i=>crc16Data(31 downto 16), crc_i=>crc16Current, crc_o=>crc16Temp);
Crc16Low: Crc16CITT
port map(
d_i=>crc16Data(15 downto 0), crc_i=>crc16Temp, crc_o=>crc16Next);
-----------------------------------------------------------------------------
-- Main inbound symbol handler.
-----------------------------------------------------------------------------
rxRead_o <= rxRead;
inboundAckId_o <= std_logic_vector(ackId);
process(areset_n, clk)
begin
if (areset_n = '0') then
state <= STATE_UNINITIALIZED;
rxRead <= '0';
txControlWrite_o <= '0';
txControlSymbol_o <= (others => '0');
rxControlWrite_o <= '0';
rxControlSymbol_o <= (others => '0');
writeFrame_o <= '0';
writeFrameAbort_o <= '0';
writeContent_o <= '0';
writeContentData_o <= (others => '0');
-- REMARK: Use frameIndex instead of this...
statusCounter <= 0;
frameIndex <= 0;
ackId <= (others => '0');
crc16Current <= (others => '0');
crc16Data <= (others => '0');
elsif (clk'event and clk = '1') then
rxRead <= '0';
txControlWrite_o <= '0';
rxControlWrite_o <= '0';
writeFrame_o <= '0';
writeFrameAbort_o <= '0';
writeContent_o <= '0';
-- Check if a locakAckIdWrite is active.
if (localAckIdWrite_i = '1') then
-- A localAckIdWrite is active.
-- Set ackId.
ackId <= unsigned(inboundAckId_i);
else
-- A localAckIdWrite is not active.
-- Act on the current state.
case state is
when STATE_UNINITIALIZED =>
-----------------------------------------------------------------------
-- This state is entered at startup. A port that is not initialized
-- should discard all received symbols.
-----------------------------------------------------------------------
-- Check if the port is initialized.
if (portInitialized_i = '0') then
-- Port not initialized.
-- Check if a new symbol is ready to be read.
if (rxRead = '0') and (rxEmpty_i = '0') then
-- New symbol ready.
-- Discard all received symbols in this state.
rxRead <= '1';
else
-- No new symbol ready to be read.
-- Dont do anything.
end if;
else
-- Port is initialized.
-- Go to the initialized state and reset the counters.
state <= STATE_PORT_INITIALIZED;
statusCounter <= 0;
end if;
when STATE_PORT_INITIALIZED =>
---------------------------------------------------------------------
-- The port has been initialized and status control symbols are being
-- received on the link to check if it is working. Count the number
-- of error-free status symbols and considder the link initialized
-- when enough of them has been received. Frames are not allowed
-- here.
---------------------------------------------------------------------
-- Check if the port is initialized.
if (portInitialized_i = '1') then
-- Port is initialized.
-- Check if a new symbol is ready to be read.
if (rxRead = '0') and (rxEmpty_i = '0') then
-- There is a new symbol to read.
-- Check the type of symbol.
if (rxControl_i = SYMBOL_CONTROL) then
-- This is a control symbol that is not a packet delimiter.
-- Check if the control symbol has a valid checksum.
if (crc5Calculated = crc5) then
-- The control symbol has a valid checksum.
-- Forward the stype0 part of the symbol to the transmitter.
txControlWrite_o <= '1';
txControlSymbol_o <= stype0 & parameter0 & parameter1;
-- Check the stype0 part if we should count the number of
-- error-free status symbols.
if (stype0 = STYPE0_STATUS) then
-- The symbol is a status.
-- Check if enough status symbols have been received.
if (statusCounter = 7) then
-- Enough status symbols have been received.
-- Reset all packets.
frameIndex <= 0;
writeFrameAbort_o <= '1';
-- Set the link as initialized.
state <= STATE_NORMAL;
else
-- Increase the number of error-free status symbols that
-- has been received.
statusCounter <= statusCounter + 1;
end if;
else
-- The symbol is not a status.
-- Dont do anything.
end if;
else
-- A control symbol with CRC5 error was recevied.
statusCounter <= 0;
end if;
else
-- Symbol that is not allowed in this state have been received.
-- Discard it.
end if;
-- Update to the next symbol.
rxRead <= '1';
else
-- No new symbol ready to be read.
-- Dont do anything.
end if;
else
-- Go back to the uninitialized state.
state <= STATE_UNINITIALIZED;
end if;
when STATE_NORMAL =>
---------------------------------------------------------------------
-- The port has been initialized and enough error free status symbols
-- have been received. Forward data frames to the frame buffer
-- interface. This is the normal operational state.
---------------------------------------------------------------------
-- Check that the port is initialized.
if (portInitialized_i = '1') then
-- The port and link is initialized.
-- Check if a new symbol is ready to be read.
if (rxRead = '0') and (rxEmpty_i = '0') then
-- There is a new symbol to read.
-- Check the type of symbol.
if (rxControl_i = SYMBOL_CONTROL) then
-- This is a control symbol with or without a packet delimiter.
-- Check if the control symbol has a valid CRC-5.
if (crc5Calculated = crc5) then
-- The control symbol is correct.
-- Forward the stype0 part of the symbol to the transmitter.
txControlWrite_o <= '1';
txControlSymbol_o <= stype0 & parameter0 & parameter1;
-- Check the stype1 part.
case stype1 is
when STYPE1_START_OF_PACKET =>
-------------------------------------------------------------
-- Start the reception of a new frame or end a currently
-- ongoing frame.
-------------------------------------------------------------
-- Check if a frame has already been started.
if (frameIndex /= 0) then
-- A frame is already started.
-- Complete the last frame and start to ackumulate a new one
-- and update the ackId.
-- Check the CRC-16 and the length of the received frame.
if (crc16Valid = '1') and (frameIndex > 3) then
-- The CRC-16 is ok.
-- Reset the frame index to indicate the frame is started.
frameIndex <= 1;
-- Update the frame buffer to indicate that the frame has
-- been completly received.
writeFrame_o <= '1';
-- Update ackId.
ackId <= ackId + 1;
-- Send packet-accepted.
-- The buffer status is appended by the transmitter
-- when sent to get the latest number.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_ACCEPTED & std_logic_vector(ackId) & "11111";
else
-- The CRC-16 is not ok.
-- Make the transmitter send a packet-not-accepted to indicate
-- that the received packet contained a CRC error.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_NOT_ACCEPTED &
"00000" &
PACKET_NOT_ACCEPTED_CAUSE_PACKET_CRC;
state <= STATE_INPUT_ERROR_STOPPED;
end if;
else
-- No frame has been started.
-- Reset the frame index to indicate the frame is started.
frameIndex <= 1;
end if;
when STYPE1_END_OF_PACKET =>
-------------------------------------------------------------
-- End the reception of an old frame.
-------------------------------------------------------------
-- Check the CRC-16 and the length of the received frame.
if (crc16Valid = '1') and (frameIndex > 3) then
-- The CRC-16 is ok.
-- Reset frame reception to indicate that no frame is ongoing.
frameIndex <= 0;
-- Update the frame buffer to indicate that the frame has
-- been completly received.
writeFrame_o <= '1';
-- Update ackId.
ackId <= ackId + 1;
-- Send packet-accepted.
-- The buffer status is appended by the transmitter
-- when sent to get the latest number.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_ACCEPTED & std_logic_vector(ackId) & "11111";
else
-- The CRC-16 is not ok.
-- Make the transmitter send a packet-not-accepted to indicate
-- that the received packet contained a CRC error.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_NOT_ACCEPTED &
"00000" &
PACKET_NOT_ACCEPTED_CAUSE_PACKET_CRC;
state <= STATE_INPUT_ERROR_STOPPED;
end if;
when STYPE1_STOMP =>
-------------------------------------------------------------
-- Restart the reception of an old frame.
-------------------------------------------------------------
-- See 5.10 in the standard.
-- Make the transmitter send a packet-retry to indicate
-- that the packet cannot be accepted.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_RETRY & std_logic_vector(ackId) & "11111";
-- Enter the input retry-stopped state.
state <= STATE_INPUT_RETRY_STOPPED;
when STYPE1_RESTART_FROM_RETRY =>
-------------------------------------------------------------
-- The receiver indicates a restart from a retry sent
-- from us.
-------------------------------------------------------------
-- See 5.10 in the standard.
-- Protocol error, this symbol should not be received here since
-- we should have been in input-retry-stopped.
-- Send a packet-not-accepted to indicate that a protocol
-- error has occurred.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_NOT_ACCEPTED &
"00000" &
PACKET_NOT_ACCEPTED_CAUSE_GENERAL_ERROR;
state <= STATE_INPUT_ERROR_STOPPED;
when STYPE1_LINK_REQUEST =>
-------------------------------------------------------------
-- Reply to a LINK-REQUEST.
-------------------------------------------------------------
-- Check the command part.
if (cmd = "100") then
-- Return input port status command.
-- This functions as a link-request(restart-from-error)
-- control symbol under error situations.
-- Send a link response containing an ok reply.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_LINK_RESPONSE & std_logic_vector(ackId) & "10000";
elsif (cmd = "011") then
-- Reset device command.
-- Discard this.
else
-- Unsupported command.
-- Discard this.
end if;
-- Abort the frame and reset frame reception.
frameIndex <= 0;
writeFrameAbort_o <= '1';
when STYPE1_MULTICAST_EVENT =>
-------------------------------------------------------------
-- Multicast symbol.
-------------------------------------------------------------
-- Discard the symbol.
when STYPE1_RESERVED =>
-------------------------------------------------------------
-- Reserved.
-------------------------------------------------------------
-- Not supported, dont do anything.
when STYPE1_NOP =>
-------------------------------------------------------------
-- NOP, no operation.
-------------------------------------------------------------
-- Dont do anything.
when others =>
-------------------------------------------------------------
--
-------------------------------------------------------------
-- NOP, no operation, dont do anything.
null;
end case;
else
-- The control symbol contains a crc error.
-- Send a packet-not-accepted to indicate that a corrupted
-- control-symbol has been received and change state.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_NOT_ACCEPTED &
"00000" &
PACKET_NOT_ACCEPTED_CAUSE_CONTROL_CRC;
state <= STATE_INPUT_ERROR_STOPPED;
end if;
elsif (rxControl_i = SYMBOL_DATA) then
-- This is a data symbol.
-- REMARK: Add check for in-the-middle-crc here...
-- Check if a frame has been started.
-- Index=0 not started
-- index=1 started and expecting to receive the first data.
-- index=others, the index of the received data.
if (frameIndex /= 0) and (frameIndex /= 70) then
-- A frame has been started and is not too long.
-- Check if the ackId is correct.
if (((frameIndex = 1) and (unsigned(rxData_i(31 downto 27)) = ackId)) or
(frameIndex /= 1)) then
-- This is the first data symbol containing the ackId which
-- is matching or receiving the rest of the frame.
-- Check if the packet ftype is allowed.
-- If the portEnable is deasserted only maintenance
-- packets are allowed.
if (((frameIndex = 1) and
((portEnable_i = '1') or (rxData_i(19 downto 16) = FTYPE_MAINTENANCE_CLASS))) or
(frameIndex /= 1)) then
-- The packet is allowed.
-- Check if there is buffers available to store the new packet.
if(writeFrameFull_i = '0') then
-- There is buffering space available to store the new data.
-- Write the data to the frame FIFO.
writeContent_o <= '1';
writeContentData_o <= rxData_i;
-- Increment the number of received data symbols.
frameIndex <= frameIndex + 1;
-- Update the saved crc result with the output from the CRC calculation.
if (frameIndex = 1) then
-- Note that the ackId should not be included when the CRC
-- is calculated.
crc16Data <= "000000" & rxData_i(25 downto 0);
crc16Current <= (others => '1');
else
crc16Data <= rxData_i;
crc16Current <= crc16Next;
end if;
else
-- The packet buffer is full.
-- Let the link-partner resend the packet.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_RETRY & std_logic_vector(ackId) & "11111";
state <= STATE_INPUT_RETRY_STOPPED;
end if;
else
-- The non-maintenance packets are not allowed.
-- Send packet-not-accepted.
rxControlWrite_o <= '1';
rxControlSymbol_o <=
STYPE0_PACKET_NOT_ACCEPTED & "00000" & PACKET_NOT_ACCEPTED_CAUSE_NON_MAINTENANCE_STOPPED;
state <= STATE_INPUT_ERROR_STOPPED;
end if;
else
-- The ackId is unexpected.
-- Send packet-not-accepted.
rxControlWrite_o <= '1';
rxControlSymbol_o <=
STYPE0_PACKET_NOT_ACCEPTED & "00000" & PACKET_NOT_ACCEPTED_CAUSE_UNEXPECTED_ACKID;
state <= STATE_INPUT_ERROR_STOPPED;
end if;
else
-- A frame has not been started or is too long.
-- Send packet-not-accepted.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_NOT_ACCEPTED & "00000" & PACKET_NOT_ACCEPTED_CAUSE_GENERAL_ERROR;
state <= STATE_INPUT_ERROR_STOPPED;
end if;
else
-- Idle sequence received.
-- Discard these.
end if;
-- Update to the next symbol.
rxRead <= '1';
else
-- No new symbol received.
-- Dont do anything.
end if;
else
-- The port has become uninitialized.
-- Go back to the uninitialized state.
state <= STATE_UNINITIALIZED;
end if;
when STATE_INPUT_RETRY_STOPPED =>
---------------------------------------------------------------------
-- This state is entered when a frame could not be accepted. All
-- symbols except restart-from-retry and link-request are discarded.
-- A restart-from-retry triggers a state change into the normal
-- link-initialized state.
---------------------------------------------------------------------
-- Check that the port is initialized.
if (portInitialized_i = '1') then
-- The port and link is initialized.
-- Check if a new symbol is ready to be read.
if (rxRead = '0') and (rxEmpty_i = '0') then
-- There is a new symbol to read.
-- Check the type of symbol.
if (rxControl_i = SYMBOL_CONTROL) then
-- This is a control symbol with or without a packet delimiter.
-- Check if the control symbol has a valid CRC-5.
if (crc5Calculated = crc5) then
-- The control symbol is correct.
-- Forward the stype0 part of the symbol to the transmitter.
txControlWrite_o <= '1';
txControlSymbol_o <= stype0 & parameter0 & parameter1;
-- Check the stype1 part.
case stype1 is
when STYPE1_RESTART_FROM_RETRY =>
-------------------------------------------------------------
-- The receiver indicates a restart from a retry sent
-- from us.
-------------------------------------------------------------
-- Abort the frame and reset frame reception.
frameIndex <= 0;
writeFrameAbort_o <= '1';
-- Go back to the normal operational state.
state <= STATE_NORMAL;
when STYPE1_LINK_REQUEST =>
-------------------------------------------------------------
-- Received a link-request.
-------------------------------------------------------------
-- Check the command part.
if (cmd = "100") then
-- Return input port status command.
-- This functions as a link-request(restart-from-error)
-- control symbol under error situations.
-- Send a link response containing an ok reply.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_LINK_RESPONSE & std_logic_vector(ackId) & "00100";
elsif (cmd = "011") then
-- Reset device command.
-- Discard this.
else
-- Unsupported command.
-- Discard this.
end if;
-- Abort the frame and reset frame reception.
frameIndex <= 0;
writeFrameAbort_o <= '1';
-- Go back to the normal operational state.
state <= STATE_NORMAL;
when others =>
-------------------------------------------------------------
--
-------------------------------------------------------------
-- Discard other control symbols.
null;
end case;
else
-- The control symbol contains a crc error.
-- Send a packet-not-accepted to indicate that a corrupted
-- control-symbol has been received and change state.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_PACKET_NOT_ACCEPTED &
"00000" &
PACKET_NOT_ACCEPTED_CAUSE_CONTROL_CRC;
state <= STATE_INPUT_ERROR_STOPPED;
end if;
elsif (rxControl_i = SYMBOL_DATA) then
-- This is a data symbol.
-- Discard all data symbols in this state.
else
-- Idle sequence received.
-- Discard other symbols.
end if;
-- Update to the next symbol.
rxRead <= '1';
else
-- No new symbol received.
-- Dont do anything.
end if;
else
-- The port has become uninitialized.
-- Go back to the uninitialized state.
state <= STATE_UNINITIALIZED;
end if;
when STATE_INPUT_ERROR_STOPPED =>
---------------------------------------------------------------------
-- This state is entered when an error situation has occurred. When in this
-- state, all symbols should be discarded until a link-request-symbols has
-- been received. See section 5.13.2.6 in part 6 of the standard.
-- Note that it is only the input side of the port that are affected, not the
-- output side. Packets may still be transmitted and acknowledges should be
-- accepted.
---------------------------------------------------------------------
-- Check that the port is initialized.
if (portInitialized_i = '1') then
-- The port and link is initialized.
-- Check if a new symbol is ready to be read.
if (rxRead = '0') and (rxEmpty_i = '0') then
-- There is a new symbol to read.
-- Check the type of symbol.
if (rxControl_i = SYMBOL_CONTROL) then
-- This is a control symbol with or without a packet delimiter.
-- Check if the control symbol has a valid CRC-5.
if (crc5Calculated = crc5) then
-- The control symbol is correct.
-- Forward the stype0 part of the symbol to the transmitter.
txControlWrite_o <= '1';
txControlSymbol_o <= stype0 & parameter0 & parameter1;
-- Check the stype1 part.
case stype1 is
when STYPE1_LINK_REQUEST =>
-------------------------------------------------------------
-- Received a link-request.
-------------------------------------------------------------
-- Check the command part.
-- REMARK: Should also send a status-control-symbol
-- directly following this symbol...
if (cmd = "100") then
-- Return input port status command.
-- This functions as a link-request(restart-from-error)
-- control symbol under error situations.
-- Send a link response containing an ok reply.
rxControlWrite_o <= '1';
rxControlSymbol_o <= STYPE0_LINK_RESPONSE & std_logic_vector(ackId) & "00101";
elsif (cmd = "011") then
-- Reset device command.
-- Discard this.
else
-- Unsupported command.
-- Discard this.
end if;
-- Abort the frame and reset frame reception.
frameIndex <= 0;
writeFrameAbort_o <= '1';
-- Go back to the normal operational state.
state <= STATE_NORMAL;
when others =>
-------------------------------------------------------------
--
-------------------------------------------------------------
-- Discard other control symbols.
null;
end case;
else
-- The control symbol contains a crc error.
-- Error is ignored in this state.
end if;
else
-- Other symbol received.
-- All other symbols are discarded in this state.
end if;
-- Update to the next symbol.
rxRead <= '1';
else
-- No new symbol received.
-- Dont do anything.
end if;
else
-- The port has become uninitialized.
-- Go back to the uninitialized state.
state <= STATE_UNINITIALIZED;
end if;
when others =>
---------------------------------------------------------------------
--
---------------------------------------------------------------------
null;
end case;
end if;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
-- A CRC-5 calculator following the implementation proposed in the 2.2
-- standard.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
entity Crc5ITU is
port(
d_i : in std_logic_vector(18 downto 0);
crc_o : out std_logic_vector(4 downto 0));
end entity;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
architecture Crc5Impl of Crc5ITU is
signal d : std_logic_vector(0 to 18);
signal c : std_logic_vector(0 to 4);
begin
-- Reverse the bit vector indexes to make them the same as in the standard.
d(18) <= d_i(0); d(17) <= d_i(1); d(16) <= d_i(2); d(15) <= d_i(3);
d(14) <= d_i(4); d(13) <= d_i(5); d(12) <= d_i(6); d(11) <= d_i(7);
d(10) <= d_i(8); d(9) <= d_i(9); d(8) <= d_i(10); d(7) <= d_i(11);
d(6) <= d_i(12); d(5) <= d_i(13); d(4) <= d_i(14); d(3) <= d_i(15);
d(2) <= d_i(16); d(1) <= d_i(17); d(0) <= d_i(18);
-- Calculate the resulting crc.
c(0) <= d(18) xor d(16) xor d(15) xor d(12) xor
d(10) xor d(5) xor d(4) xor d(3) xor
d(1) xor d(0);
c(1) <= (not d(18)) xor d(17) xor d(15) xor d(13) xor
d(12) xor d(11) xor d(10) xor d(6) xor
d(3) xor d(2) xor d(0);
c(2) <= (not d(18)) xor d(16) xor d(14) xor d(13) xor
d(12) xor d(11) xor d(7) xor d(4) xor
d(3) xor d(1);
c(3) <= (not d(18)) xor d(17) xor d(16) xor d(14) xor
d(13) xor d(10) xor d(8) xor d(3) xor
d(2) xor d(1);
c(4) <= d(18) xor d(17) xor d(15) xor d(14) xor
d(11) xor d(9) xor d(4) xor d(3) xor
d(2) xor d(0);
-- Reverse the bit vector indexes to make them the same as in the standard.
crc_o(4) <= c(0); crc_o(3) <= c(1); crc_o(2) <= c(2); crc_o(1) <= c(3);
crc_o(0) <= c(4);
end architecture;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Chip toplevel design with MMC feature set
--
-- $Id: chip-mmc-a.vhd,v 1.7 2007-08-06 23:31:42 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture mmc of chip is
component spi_boot
generic (
width_bit_cnt_g : integer := 6;
width_img_cnt_g : integer := 2;
num_bits_per_img_g : integer := 18;
sd_init_g : integer := 0;
mmc_compat_clk_div_g : integer := 0;
width_mmc_clk_div_g : integer := 0;
reset_level_g : integer := 0
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
set_sel_i : in std_logic_vector(31-width_img_cnt_g-num_bits_per_img_g
downto 0);
spi_clk_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_data_in_i : in std_logic;
spi_data_out_o : out std_logic;
spi_en_outs_o : out std_logic;
start_i : in std_logic;
mode_i : in std_logic;
config_n_o : out std_logic;
detached_o : out std_logic;
cfg_init_n_i : in std_logic;
cfg_done_i : in std_logic;
dat_done_i : in std_logic;
cfg_clk_o : out std_logic;
cfg_dat_o : out std_logic
);
end component;
signal spi_clk_s : std_logic;
signal spi_cs_n_s : std_logic;
signal spi_data_out_s : std_logic;
signal spi_en_outs_s : std_logic;
constant width_img_cnt_c : integer := 2; -- 4 images
constant num_bits_per_img_c : integer := 18; -- 256 kByte per image
constant set_sel_width_c : integer := 31-width_img_cnt_c-num_bits_per_img_c;
signal set_sel_s : std_logic_vector(set_sel_width_c downto 0);
begin
set_sel_s <= (3 => not set_sel_n_i(3),
2 => not set_sel_n_i(2),
1 => not set_sel_n_i(1),
0 => not set_sel_n_i(0),
others => '0');
spi_boot_b : spi_boot
generic map (
width_bit_cnt_g => 12, -- 512 bytes per block
width_img_cnt_g => width_img_cnt_c,
num_bits_per_img_g => num_bits_per_img_c,
sd_init_g => 0, -- no SD specific initialization
mmc_compat_clk_div_g => 13, -- MMC compat 400 kHz > 10 MHz / (13*2)
width_mmc_clk_div_g => 4 -- need 5 bits for MMC compat divider
)
port map (
clk_i => clk_i,
reset_i => reset_i,
set_sel_i => set_sel_s,
spi_clk_o => spi_clk_s,
spi_cs_n_o => spi_cs_n_s,
spi_data_in_i => spi_data_in_i,
spi_data_out_o => spi_data_out_s,
spi_en_outs_o => spi_en_outs_s,
start_i => start_i,
mode_i => mode_i,
config_n_o => config_n_o,
detached_o => detached_o,
cfg_init_n_i => cfg_init_n_i,
cfg_done_i => cfg_done_i,
dat_done_i => dat_done_i,
cfg_clk_o => cfg_clk_o,
cfg_dat_o => cfg_dat_o
);
-----------------------------------------------------------------------------
-- Three state drivers for SPI outputs.
-----------------------------------------------------------------------------
spi_clk_o <= spi_clk_s
when spi_en_outs_s = '1' else
'Z';
spi_cs_n_o <= spi_cs_n_s
when spi_en_outs_s = '1' else
'Z';
spi_data_out_o <= spi_data_out_s
when spi_en_outs_s = '1' else
'Z';
end mmc;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2005/04/07 20:44:23 arniml
-- add new port detached_o
--
-- Revision 1.5 2005/03/09 19:48:34 arniml
-- invert level of set_sel input
--
-- Revision 1.4 2005/03/08 22:07:12 arniml
-- added set selection
--
-- Revision 1.3 2005/02/18 06:42:13 arniml
-- clarify wording for images
--
-- Revision 1.2 2005/02/16 18:54:39 arniml
-- added tri-state drivers for spi outputs
--
-- Revision 1.1 2005/02/08 20:41:32 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gray_testbench is end gray_testbench;
architecture behavioral of gray_testbench is
signal input : std_logic_vector(3 downto 0);
signal output : std_logic_vector(3 downto 0);
component mux
port (
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
s : in std_logic_vector(1 downto 0);
m : out std_logic
);
end component;
begin
process begin
for j in 0 to 15 loop
input <= std_logic_vector(to_unsigned(j,4));
wait for 10 ns;
end loop;
end process;
output(3) <= input(3);
uut1 : mux
port map (
a => '0',
b => '1',
c => '1',
d => '0',
s => input(3 downto 2),
m => output(2)
);
uut2 : mux
port map (
a => '0',
b => '1',
c => '1',
d => '0',
s => input(2 downto 1),
m => output(1)
);
uut3 : mux
port map (
a => '0',
b => '1',
c => '1',
d => '0',
s => input(1 downto 0),
m => output(0)
);
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
entity PULLUP is
port (
O : out std_logic
);
attribute syn_not_a_driver : boolean;
attribute syn_not_a_driver of O : signal is true;
end entity PULLUP;
architecture bb of PULLUP is
attribute syn_black_box of bb : architecture is true;
attribute syn_noprune of bb : architecture is true;
begin
end architecture bb;
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
entity PULLDOWN is
port (
O : out std_logic
);
attribute syn_not_a_driver : boolean;
attribute syn_not_a_driver of O : signal is true;
end entity PULLDOWN;
architecture bb of PULLDOWN is
attribute syn_black_box of bb : architecture is true;
attribute syn_noprune of bb : architecture is true;
begin
end architecture bb;
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
entity LUT1 is
generic (INIT : bit_vector(1 downto 0));
port (
O : out std_logic;
I0 : in std_logic
);
end entity LUT1;
architecture lut of LUT1 is
attribute xc_map of lut : architecture is "lut";
begin
O <= To_StdULogic(INIT(1)) when I0 = '1' else To_StdULogic(INIT(0));
end architecture lut;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library synplify;
use synplify.attributes.all;
entity LUT2 is
generic (INIT : bit_vector(3 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic
);
end entity LUT2;
architecture lut of LUT2 is
attribute xc_map of lut : architecture is "lut";
signal b : std_logic_vector(1 downto 0);
signal tmp : integer range 0 to 7;
begin
b <= (I1, I0);
tmp <= conv_integer(b);
O <= To_StdULogic(INIT(tmp));
end architecture lut;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library synplify;
use synplify.attributes.all;
entity LUT3 is
generic (INIT : bit_vector(7 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic
);
end entity LUT3;
architecture lut of LUT3 is
attribute xc_map of lut : architecture is "lut";
signal b : std_logic_vector(2 downto 0);
signal tmp : integer range 0 to 7;
begin
b <= (I2, I1, I0);
tmp <= conv_integer(b);
O <= To_StdULogic(INIT(tmp));
end architecture lut;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library synplify;
use synplify.attributes.all;
entity LUT4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end entity LUT4;
architecture lut of LUT4 is
attribute xc_map of lut : architecture is "lut";
signal b : std_logic_vector(3 downto 0);
signal tmp : integer range 0 to 15;
begin
b <= (I3, I2, I1, I0);
tmp <= conv_integer(b);
O <= To_StdUlogic(INIT(tmp));
end architecture lut;
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
package components is
attribute syn_black_box of components : package is true;
attribute syn_noprune : boolean;
component BSCAN_VIRTEX2
port (
TDO1 : in std_logic;
TDO2 : in std_logic;
CAPTURE : out std_logic;
DRCK1 : out std_logic;
DRCK2 : out std_logic;
RESET : out std_logic;
SEL1 : out std_logic;
SEL2 : out std_logic;
SHIFT : out std_logic;
TDI : out std_logic;
UPDATE : out std_logic
);
end component;
attribute syn_black_box of BSCAN_VIRTEX2 : component is true;
component BUF
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of BUF : component is true;
component BUFCF
port (
O : out std_logic;
I : in std_logic
);
end component;
component BUFE
port (
O : out std_logic;
E : in std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of BUFE : component is true;
attribute black_box_tri_pins of BUFE : component is "O";
component BUFG
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of BUFG : component is true;
component BUFGDLL
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of BUFGDLL : component is true;
component BUFGMUX0
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of BUFGMUX0 : component is true;
component BUFGMUX1
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of BUFGMUX1 : component is true;
component BUFGP
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of BUFGP : component is true;
component BUFT
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of BUFT : component is true;
attribute black_box_tri_pins of BUFT : component is "O";
component CAPTURE_VIRTEX2
port (
CAP : in std_logic;
CLK : in std_logic
);
end component;
attribute syn_black_box of CAPTURE_VIRTEX2 : component is true;
attribute syn_noprune of CAPTURE_VIRTEX2 : component is true;
component CLKDLL
port (
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLKDV : out std_logic;
LOCKED : out std_logic;
CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of CLKDLL : component is true;
component CLKDLLE
port (
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
LOCKED : out std_logic;
CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of CLKDLLE : component is true;
component CLKDLLHF
port (
CLK0 : out std_logic;
CLK180 : out std_logic;
CLKDV : out std_logic;
LOCKED : out std_logic;
CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of CLKDLLHF : component is true;
component DCM
generic (DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DUTY_CYCLE_CORRECTION : boolean := TRUE;
CLKIN_DIVIDE_BY_2 : boolean := FALSE;
CLK_FEEDBACK : string := "1X";
CLKOUT_PHASE_SHIFT : string := "NONE";
FACTORY_JF : bit_vector := X"C080";
STARTUP_WAIT : boolean := FALSE;
DSS_MODE : string := "NONE";
PHASE_SHIFT : integer := 0 ;
CLKFX_MULTIPLY : integer := 4 ;
CLKFX_DIVIDE : integer := 1;
CLKDV_DIVIDE : real := 2.0;
CLKIN_PERIOD : real := 0.0;
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"
);
port ( CLKIN : in std_logic;
CLKFB : in std_logic;
DSSEN : in std_logic;
PSINCDEC : in std_logic;
PSEN : in std_logic;
PSCLK : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector(7 downto 0)
);
end component;
attribute syn_black_box of DCM : component is true;
component FD
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FD : component is true;
component FDC
port (
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FDC : component is true;
component FDCE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FDCE : component is true;
component FDCE_1
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FDCE_1 : component is true;
component FDCP
port (
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDCP : component is true;
component FDCPE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDCPE : component is true;
component FDCPE_1
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDCPE_1 : component is true;
component FDCP_1
port (
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDCP_1 : component is true;
component FDC_1
port (
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FDC_1 : component is true;
component FDDRCPE
port (
Q : out std_logic;
C0 : in std_logic;
C1 : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDDRCPE : component is true;
component FDDRRSE
port (
Q : out std_logic;
C0 : in std_logic;
C1 : in std_logic;
CE : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
R : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDDRRSE : component is true;
component FDE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FDE : component is true;
component FDE_1
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FDE_1 : component is true;
component FDP
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDP : component is true;
component FDPE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDPE : component is true;
component FDPE_1
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDPE_1 : component is true;
component FDP_1
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDP_1 : component is true;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
attribute syn_black_box of FDR : component is true;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
attribute syn_black_box of FDRE : component is true;
component FDRE_1
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
attribute syn_black_box of FDRE_1 : component is true;
component FDRS
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDRS : component is true;
component FDRSE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDRSE : component is true;
component FDRSE_1
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDRSE_1 : component is true;
component FDRS_1
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDRS_1 : component is true;
component FDR_1
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
attribute syn_black_box of FDR_1 : component is true;
component FDS
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDS : component is true;
component FDSE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDSE : component is true;
component FDSE_1
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDSE_1 : component is true;
component FDS_1
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDS_1 : component is true;
component FD_1
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FD_1 : component is true;
component GND
port (
G : out std_logic
);
end component;
attribute syn_black_box of GND : component is true;
attribute syn_noprune of GND : component is true;
component IBUF
generic (
IOSTANDARD : string := "default"
);
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF : component is true;
component IBUFDS
generic (
IOSTANDARD : string := "default"
);
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS : component is true;
component IBUFDS_BLVDS_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_BLVDS_25 : component is true;
component IBUFDS_LDT_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_LDT_25 : component is true;
component IBUFDS_LVDSEXT_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_LVDSEXT_25 : component is true;
component IBUFDS_LVDSEXT_33
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_LVDSEXT_33 : component is true;
component IBUFDS_LVDS_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_LVDS_25 : component is true;
component IBUFDS_LVDS_33
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_LVDS_33 : component is true;
component IBUFDS_LVPECL_33
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_LVPECL_33 : component is true;
component IBUFDS_ULVDS_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_ULVDS_25 : component is true;
component IBUFG
generic (
IOSTANDARD : string := "default"
);
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG : component is true;
component IBUFGDS
generic (
IOSTANDARD : string := "default"
);
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS : component is true;
component IBUFGDS_BLVDS_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_BLVDS_25 : component is true;
component IBUFGDS_LDT_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_LDT_25 : component is true;
component IBUFGDS_LVDSEXT_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_LVDSEXT_25 : component is true;
component IBUFGDS_LVDSEXT_33
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_LVDSEXT_33 : component is true;
component IBUFGDS_LVDS_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_LVDS_25 : component is true;
component IBUFGDS_LVDS_33
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_LVDS_33 : component is true;
component IBUFGDS_LVPECL_33
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_LVPECL_33 : component is true;
component IBUFGDS_ULVDS_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_ULVDS_25 : component is true;
component IBUFG_AGP
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_AGP : component is true;
component IBUFG_GTL
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_GTL : component is true;
component IBUFG_GTL_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_GTL_DCI : component is true;
component IBUFG_GTLP
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_GTLP : component is true;
component IBUFG_GTLP_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_GTLP_DCI : component is true;
component IBUFG_HSTL_I
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_I : component is true;
component IBUFG_HSTL_I_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_I_18 : component is true;
component IBUFG_HSTL_I_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_I_DCI : component is true;
component IBUFG_HSTL_I_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_I_DCI_18 : component is true;
component IBUFG_HSTL_II
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_II : component is true;
component IBUFG_HSTL_II_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_II_18 : component is true;
component IBUFG_HSTL_II_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_II_DCI : component is true;
component IBUFG_HSTL_II_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_II_DCI_18 : component is true;
component IBUFG_HSTL_III
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_III : component is true;
component IBUFG_HSTL_III_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_III_18 : component is true;
component IBUFG_HSTL_III_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_III_DCI : component is true;
component IBUFG_HSTL_III_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_III_DCI_18 : component is true;
component IBUFG_HSTL_IV
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_IV : component is true;
component IBUFG_HSTL_IV_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_IV_18 : component is true;
component IBUFG_HSTL_IV_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_IV_DCI : component is true;
component IBUFG_HSTL_IV_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_IV_DCI_18 : component is true;
component IBUFG_LVDCI_15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVDCI_15 : component is true;
component IBUFG_LVDCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVDCI_18 : component is true;
component IBUFG_LVDCI_25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVDCI_25 : component is true;
component IBUFG_LVDCI_33
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVDCI_33 : component is true;
component IBUFG_LVDCI_DV2_15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVDCI_DV2_15 : component is true;
component IBUFG_LVDCI_DV2_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVDCI_DV2_18 : component is true;
component IBUFG_LVDCI_DV2_25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVDCI_DV2_25 : component is true;
component IBUFG_LVCMOS15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVCMOS15 : component is true;
component IBUFG_LVCMOS18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVCMOS18 : component is true;
component IBUFG_LVCMOS2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVCMOS2 : component is true;
component IBUFG_LVCMOS25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVCMOS25 : component is true;
component IBUFG_PCI33_3
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_PCI33_3 : component is true;
component IBUFG_PCI66_3
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_PCI66_3 : component is true;
component IBUFG_PCIX
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_PCIX : component is true;
component IBUFG_SSTL2_I
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_SSTL2_I : component is true;
component IBUFG_SSTL2_I_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_SSTL2_I_DCI : component is true;
component IBUFG_SSTL2_II
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_SSTL2_II : component is true;
component IBUFG_SSTL2_II_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_SSTL2_II_DCI : component is true;
component IBUF_AGP
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_AGP : component is true;
component IBUF_GTL
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_GTL : component is true;
component IBUF_GTL_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_GTL_DCI : component is true;
component IBUF_GTLP
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_GTLP : component is true;
component IBUF_GTLP_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_GTLP_DCI : component is true;
component IBUF_HSTL_I
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_I : component is true;
component IBUF_HSTL_I_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_I_18 : component is true;
component IBUF_HSTL_I_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_I_DCI : component is true;
component IBUF_HSTL_I_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_I_DCI_18 : component is true;
component IBUF_HSTL_II
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_II : component is true;
component IBUF_HSTL_II_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_II_18 : component is true;
component IBUF_HSTL_II_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_II_DCI : component is true;
component IBUF_HSTL_II_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_II_DCI_18 : component is true;
component IBUF_HSTL_III
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_III : component is true;
component IBUF_HSTL_III_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_III_18 : component is true;
component IBUF_HSTL_III_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_III_DCI : component is true;
component IBUF_HSTL_III_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_III_DCI_18 : component is true;
component IBUF_HSTL_IV
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_IV : component is true;
component IBUF_HSTL_IV_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_IV_18 : component is true;
component IBUF_HSTL_IV_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_IV_DCI : component is true;
component IBUF_HSTL_IV_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_IV_DCI_18 : component is true;
component IBUF_LVCMOS15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVCMOS15 : component is true;
component IBUF_LVCMOS18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVCMOS18 : component is true;
component IBUF_LVCMOS2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVCMOS2 : component is true;
component IBUF_LVCMOS25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVCMOS25 : component is true;
component IBUF_LVDCI_15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDCI_15 : component is true;
component IBUF_LVDCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDCI_18 : component is true;
component IBUF_LVDCI_25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDCI_25 : component is true;
component IBUF_LVDCI_33
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDCI_33 : component is true;
component IBUF_LVDCI_DV2_15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDCI_DV2_15 : component is true;
component IBUF_LVDCI_DV2_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDCI_DV2_18 : component is true;
component IBUF_LVDCI_DV2_25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDCI_DV2_25 : component is true;
component IBUF_LVDS
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDS : component is true;
component IBUF_LVPECL
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVPECL : component is true;
component IBUF_PCI33_3
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_PCI33_3 : component is true;
component IBUF_PCI66_3
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_PCI66_3 : component is true;
component IBUF_PCIX
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_PCIX : component is true;
component IBUF_SSTL2_I
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_SSTL2_I : component is true;
component IBUF_SSTL2_I_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_SSTL2_I_DCI : component is true;
component IBUF_SSTL2_II
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_SSTL2_II : component is true;
component IBUF_SSTL2_II_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_SSTL2_II_DCI : component is true;
component INV
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of INV : component is true;
component PIPEBUF
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of PIPEBUF : component is true;
component IOBUF
generic (
IOSTANDARD : string := "default";
SLEW : string := "SLOW";
DRIVE : integer := 12
);
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF : component is true;
component IOBUFDS
generic (
IOSTANDARD : string := "default";
SLEW : string := "SLOW";
DRIVE : integer := 12
);
port (
O : out std_logic;
IO : inout std_logic;
IOB : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUFDS : component is true;
component IOBUFDS_BLVDS_25
port (
O : out std_logic;
IO : inout std_logic;
IOB : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUFDS_BLVDS_25 : component is true;
component IOBUFDS_LVPECL_33
port (
O : out std_logic;
IO : inout std_logic;
IOB : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUFDS_LVPECL_33 : component is true;
component IOBUF_F_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_F_12 : component is true;
component IOBUF_F_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_F_16 : component is true;
component IOBUF_F_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_F_2 : component is true;
component IOBUF_F_24
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_F_24 : component is true;
component IOBUF_F_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_F_4 : component is true;
component IOBUF_F_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_F_6 : component is true;
component IOBUF_F_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_F_8 : component is true;
component IOBUF_GTL
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_GTL : component is true;
component IOBUF_GTL_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_GTL_DCI : component is true;
component IOBUF_GTLP
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_GTLP : component is true;
component IOBUF_GTLP_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_GTLP_DCI : component is true;
component IOBUF_HSTL_I
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_I : component is true;
component IOBUF_HSTL_I_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_I_18 : component is true;
component IOBUF_HSTL_I_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_I_DCI : component is true;
component IOBUF_HSTL_II
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_II : component is true;
component IOBUF_HSTL_II_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_II_18 : component is true;
component IOBUF_HSTL_II_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_II_DCI : component is true;
component IOBUF_HSTL_II_DCI_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_II_DCI_18 : component is true;
component IOBUF_HSTL_III
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_III : component is true;
component IOBUF_HSTL_III_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_III_18 : component is true;
component IOBUF_HSTL_III_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_III_DCI : component is true;
component IOBUF_HSTL_III_DCI_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_III_DCI_18 : component is true;
component IOBUF_HSTL_IV
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_IV : component is true;
component IOBUF_HSTL_IV_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_IV_18 : component is true;
component IOBUF_HSTL_IV_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_IV_DCI : component is true;
component IOBUF_HSTL_IV_DCI_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_IV_DCI_18 : component is true;
component IOBUF_LVCMOS15
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15 : component is true;
component IOBUF_LVCMOS15_F_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_12 : component is true;
component IOBUF_LVCMOS15_F_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_16 : component is true;
component IOBUF_LVCMOS15_F_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_2 : component is true;
component IOBUF_LVCMOS15_F_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_4 : component is true;
component IOBUF_LVCMOS15_F_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_6 : component is true;
component IOBUF_LVCMOS15_F_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_8 : component is true;
component IOBUF_LVCMOS15_S_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_12 : component is true;
component IOBUF_LVCMOS15_S_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_16 : component is true;
component IOBUF_LVCMOS15_S_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_2 : component is true;
component IOBUF_LVCMOS15_S_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_4 : component is true;
component IOBUF_LVCMOS15_S_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_6 : component is true;
component IOBUF_LVCMOS15_S_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_8 : component is true;
component IOBUF_LVCMOS18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18 : component is true;
component IOBUF_LVCMOS18_F_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_12 : component is true;
component IOBUF_LVCMOS18_F_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_16 : component is true;
component IOBUF_LVCMOS18_F_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_2 : component is true;
component IOBUF_LVCMOS18_F_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_4 : component is true;
component IOBUF_LVCMOS18_F_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_6 : component is true;
component IOBUF_LVCMOS18_F_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_8 : component is true;
component IOBUF_LVCMOS18_S_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_12 : component is true;
component IOBUF_LVCMOS18_S_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_16 : component is true;
component IOBUF_LVCMOS18_S_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_2 : component is true;
component IOBUF_LVCMOS18_S_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_4 : component is true;
component IOBUF_LVCMOS18_S_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_6 : component is true;
component IOBUF_LVCMOS18_S_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_8 : component is true;
component IOBUF_LVCMOS2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS2 : component is true;
component IOBUF_LVCMOS25
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25 : component is true;
component IOBUF_LVCMOS25_F_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_12 : component is true;
component IOBUF_LVCMOS25_F_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_16 : component is true;
component IOBUF_LVCMOS25_F_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_2 : component is true;
component IOBUF_LVCMOS25_F_24
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_24 : component is true;
component IOBUF_LVCMOS25_F_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_4 : component is true;
component IOBUF_LVCMOS25_F_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_6 : component is true;
component IOBUF_LVCMOS25_F_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_8 : component is true;
component IOBUF_LVCMOS25_S_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_12 : component is true;
component IOBUF_LVCMOS25_S_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_16 : component is true;
component IOBUF_LVCMOS25_S_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_2 : component is true;
component IOBUF_LVCMOS25_S_24
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_24 : component is true;
component IOBUF_LVCMOS25_S_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_4 : component is true;
component IOBUF_LVCMOS25_S_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_6 : component is true;
component IOBUF_LVCMOS25_S_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_8 : component is true;
component IOBUF_LVDCI_15
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDCI_15 : component is true;
component IOBUF_LVDCI_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDCI_18 : component is true;
component IOBUF_LVDCI_25
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDCI_25 : component is true;
component IOBUF_LVDCI_33
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDCI_33 : component is true;
component IOBUF_LVDCI_DV2_15
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDCI_DV2_15 : component is true;
component IOBUF_LVDCI_DV2_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDCI_DV2_18 : component is true;
component IOBUF_LVDCI_DV2_25
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDCI_DV2_25 : component is true;
component IOBUF_LVDS
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDS : component is true;
component IOBUF_LVPECL
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVPECL : component is true;
component IOBUF_PCI33_3
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_PCI33_3 : component is true;
component IOBUF_PCI66_3
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_PCI66_3 : component is true;
component IOBUF_PCIX
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_PCIX : component is true;
component IOBUF_SSTL2_I
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_SSTL2_I : component is true;
component IOBUF_SSTL2_I_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_SSTL2_I_DCI : component is true;
component IOBUF_SSTL2_II
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_SSTL2_II : component is true;
component IOBUF_SSTL2_II_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_SSTL2_II_DCI : component is true;
component IOBUF_S_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_S_12 : component is true;
component IOBUF_S_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_S_16 : component is true;
component IOBUF_S_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_S_2 : component is true;
component IOBUF_S_24
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_S_24 : component is true;
component IOBUF_S_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_S_4 : component is true;
component IOBUF_S_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_S_6 : component is true;
component IOBUF_S_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_S_8 : component is true;
component KEEPER
port (
O : inout std_logic
);
end component;
attribute syn_black_box of KEEPER : component is true;
attribute syn_noprune of KEEPER : component is true;
component LD
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic
);
end component;
attribute syn_black_box of LD : component is true;
component LDC
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic
);
end component;
attribute syn_black_box of LDC : component is true;
component LDCE
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic
);
end component;
attribute syn_black_box of LDCE : component is true;
component LDCE_1
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic
);
end component;
attribute syn_black_box of LDCE_1 : component is true;
component LDCP
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDCP : component is true;
component LDCPE
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDCPE : component is true;
component LDCPE_1
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDCPE_1 : component is true;
component LDCP_1
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDCP_1 : component is true;
component LDC_1
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic
);
end component;
attribute syn_black_box of LDC_1 : component is true;
component LDE
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic
);
end component;
attribute syn_black_box of LDE : component is true;
component LDE_1
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic
);
end component;
attribute syn_black_box of LDE_1 : component is true;
component LDP
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDP : component is true;
component LDPE
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDPE : component is true;
component LDPE_1
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDPE_1 : component is true;
component LDP_1
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDP_1 : component is true;
component LD_1
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic
);
end component;
attribute syn_black_box of LD_1 : component is true;
component LUT1
generic(INIT : bit_vector := "00");
port (
O : out std_logic;
I0 : in std_logic
);
end component;
attribute syn_black_box of LUT1 : component is true;
attribute xc_map of LUT1 : component is "lut";
component LUT1_D
generic(INIT : bit_vector := "00");
port (
LO : out std_logic;
O : out std_logic;
I0 : in std_logic
);
end component;
attribute syn_black_box of LUT1_D : component is true;
attribute xc_map of LUT1_D : component is "lut";
component LUT1_L
generic(INIT : bit_vector := "00");
port (
LO : out std_logic;
I0 : in std_logic
);
end component;
attribute syn_black_box of LUT1_L : component is true;
attribute xc_map of LUT1_L : component is "lut";
component LUT2
generic(INIT : bit_vector := X"0");
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic
);
end component;
attribute syn_black_box of LUT2 : component is true;
attribute xc_map of LUT2 : component is "lut";
component LUT2_D
generic(INIT : bit_vector := X"0");
port (
LO : out std_logic;
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic
);
end component;
attribute syn_black_box of LUT2_D : component is true;
attribute xc_map of LUT2_D : component is "lut";
component LUT2_L
generic(INIT : bit_vector := X"0");
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic
);
end component;
attribute syn_black_box of LUT2_L : component is true;
attribute xc_map of LUT2_L : component is "lut";
component LUT3
generic(INIT : bit_vector := X"00");
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic
);
end component;
attribute syn_black_box of LUT3 : component is true;
attribute xc_map of LUT3 : component is "lut";
component LUT3_D
generic(INIT : bit_vector := X"00");
port (
LO : out std_logic;
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic
);
end component;
attribute syn_black_box of LUT3_D : component is true;
attribute xc_map of LUT3_D : component is "lut";
component LUT3_L
generic(INIT : bit_vector := X"00");
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic
);
end component;
attribute syn_black_box of LUT3_L : component is true;
attribute xc_map of LUT3_L : component is "lut";
component LUT4
generic(INIT : bit_vector := X"0000");
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component;
attribute syn_black_box of LUT4 : component is true;
attribute xc_map of LUT4 : component is "lut";
component LUT4_D
generic(INIT : bit_vector := X"0000");
port (
LO : out std_logic;
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component;
attribute syn_black_box of LUT4_D : component is true;
attribute xc_map of LUT4_D : component is "lut";
component LUT4_L
generic(INIT : bit_vector := X"0000");
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component;
attribute syn_black_box of LUT4_L : component is true;
attribute xc_map of LUT4_L : component is "lut";
component MULT18X18
port (
P : out std_logic_vector(35 downto 0);
A : in std_logic_Vector(17 downto 0);
B : in std_logic_vector(17 downto 0)
);
end component;
attribute syn_black_box of MULT18X18 : component is true;
component MULT18X18S
port (A : in STD_LOGIC_VECTOR (17 downto 0);
B : in STD_LOGIC_VECTOR (17 downto 0);
C : in STD_ULOGIC ;
CE : in STD_ULOGIC ;
P : out STD_LOGIC_VECTOR (35 downto 0);
R : in STD_ULOGIC );
end component;
attribute syn_black_box of MULT18X18S : component is true;
component MULT_AND
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic
);
end component;
attribute syn_black_box of MULT_AND : component is true;
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXCY : component is true;
component MUXCY_D
port (
O : out std_logic;
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXCY_D : component is true;
component MUXCY_L
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXCY_L : component is true;
component MUXF5
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF5 : component is true;
component MUXF5_D
port (
O : out std_logic;
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF5_D : component is true;
component MUXF5_L
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF5_L : component is true;
component MUXF6
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF6 : component is true;
component MUXF6_D
port (
O : out std_logic;
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF6_D : component is true;
component MUXF6_L
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF6_L : component is true;
component MUXF7
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF7 : component is true;
component MUXF7_D
port (
O : out std_logic;
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF7_D : component is true;
component MUXF7_L
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF7_L : component is true;
component MUXF8
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF8 : component is true;
component MUXF8_D
port (
O : out std_logic;
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF8_D : component is true;
component MUXF8_L
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF8_L : component is true;
component OBUF
generic (
IOSTANDARD : string := "default";
SLEW : string := "SLOW";
DRIVE : integer := 12
);
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF : component is true;
component OBUFDS
generic (
IOSTANDARD : string := "default";
SLEW : string := "SLOW";
DRIVE : integer := 12
);
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS : component is true;
component OBUFDS_BLVDS_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_BLVDS_25 : component is true;
component OBUFDS_LDT_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_LDT_25 : component is true;
component OBUFDS_LVDSEXT_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_LVDSEXT_25 : component is true;
component OBUFDS_LVDSEXT_33
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_LVDSEXT_33 : component is true;
component OBUFDS_LVDS_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_LVDS_25 : component is true;
component OBUFDS_LVDS_33
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_LVDS_33 : component is true;
component OBUFDS_ULVDS_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_ULVDS_25 : component is true;
component OBUFDS_LVPECL_33
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_LVPECL_33 : component is true;
component OBUFT
generic (
IOSTANDARD : string := "default";
SLEW : string := "SLOW";
DRIVE : integer := 12
);
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT : component is true;
attribute black_box_tri_pins of OBUFT : component is "O";
component OBUFTDS
generic (
IOSTANDARD : string := "default";
SLEW : string := "SLOW";
DRIVE : integer := 12
);
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS : component is true;
attribute black_box_tri_pins of OBUFTDS : component is "O,OB";
component OBUFTDS_BLVDS_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_BLVDS_25 : component is true;
attribute black_box_tri_pins of OBUFTDS_BLVDS_25 : component is "O,OB";
component OBUFTDS_LDT_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_LDT_25 : component is true;
attribute black_box_tri_pins of OBUFTDS_LDT_25 : component is "O,OB";
component OBUFTDS_LVDSEXT_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_LVDSEXT_25 : component is true;
attribute black_box_tri_pins of OBUFTDS_LVDSEXT_25 : component is "O,OB";
component OBUFTDS_LVDSEXT_33
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_LVDSEXT_33 : component is true;
attribute black_box_tri_pins of OBUFTDS_LVDSEXT_33 : component is "O,OB";
component OBUFTDS_LVDS_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_LVDS_25 : component is true;
attribute black_box_tri_pins of OBUFTDS_LVDS_25 : component is "O,OB";
component OBUFTDS_LVDS_33
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_LVDS_33 : component is true;
attribute black_box_tri_pins of OBUFTDS_LVDS_33 : component is "O,OB";
component OBUFTDS_ULVDS_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_ULVDS_25 : component is true;
attribute black_box_tri_pins of OBUFTDS_ULVDS_25 : component is "O,OB";
component OBUFTDS_LVPECL_33
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_LVPECL_33 : component is true;
attribute black_box_tri_pins of OBUFTDS_LVPECL_33 : component is "O,OB";
component OBUFT_AGP
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_AGP : component is true;
attribute black_box_tri_pins of OBUFT_AGP : component is "O";
component OBUFT_F_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_F_12 : component is true;
attribute black_box_tri_pins of OBUFT_F_12 : component is "O";
component OBUFT_F_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_F_16 : component is true;
attribute black_box_tri_pins of OBUFT_F_16 : component is "O";
component OBUFT_F_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_F_2 : component is true;
attribute black_box_tri_pins of OBUFT_F_2 : component is "O";
component OBUFT_F_24
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_F_24 : component is true;
attribute black_box_tri_pins of OBUFT_F_24 : component is "O";
component OBUFT_F_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_F_4 : component is true;
attribute black_box_tri_pins of OBUFT_F_4 : component is "O";
component OBUFT_F_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_F_6 : component is true;
attribute black_box_tri_pins of OBUFT_F_6 : component is "O";
component OBUFT_F_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_F_8 : component is true;
attribute black_box_tri_pins of OBUFT_F_8 : component is "O";
component OBUFT_GTL
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_GTL : component is true;
attribute black_box_tri_pins of OBUFT_GTL : component is "O";
component OBUFT_GTL_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_GTL_DCI : component is true;
attribute black_box_tri_pins of OBUFT_GTL_DCI : component is "O";
component OBUFT_GTLP
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_GTLP : component is true;
attribute black_box_tri_pins of OBUFT_GTLP : component is "O";
component OBUFT_GTLP_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_GTLP_DCI : component is true;
attribute black_box_tri_pins of OBUFT_GTLP_DCI : component is "O";
component OBUFT_HSTL_I
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_I : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_I : component is "O";
component OBUFT_HSTL_I_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_I_18 : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_I_18 : component is "O";
component OBUFT_HSTL_I_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_I_DCI : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_I_DCI : component is "O";
component OBUFT_HSTL_I_DCI_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_Box of OBUFT_HSTL_I_DCI_18 : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_I_DCI_18 : component is "O";
component OBUFT_HSTL_II
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_II : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_II : component is "O";
component OBUFT_HSTL_II_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_II_18 : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_II_18 : component is "O";
component OBUFT_HSTL_II_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_II_DCI : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_II_DCI : component is "O";
component OBUFT_HSTL_II_DCI_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_II_DCI_18 : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_II_DCI_18 : component is "O";
component OBUFT_HSTL_III
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_III : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_III : component is "O";
component OBUFT_HSTL_III_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_III_18 : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_III_18 : component is "O";
component OBUFT_HSTL_III_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_III_DCI : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_III_DCI : component is "O";
component OBUFT_HSTL_III_DCI_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_III_DCI_18 : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_III_DCI_18 : component is "O";
component OBUFT_HSTL_IV
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_IV : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_IV : component is "O";
component OBUFT_HSTL_IV_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_IV_DCI : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_IV_DCI : component is "O";
component OBUFT_HSTL_IV_DCI_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_IV_DCI_18 : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_IV_DCI_18 : component is "O";
component OBUFT_LVCMOS15
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15 : component is "O";
component OBUFT_LVCMOS15_F_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_F_12 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_F_12 : component is "O";
component OBUFT_LVCMOS15_F_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_F_16 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_F_16 : component is "O";
component OBUFT_LVCMOS15_F_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_F_2 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_F_2 : component is "O";
component OBUFT_LVCMOS15_F_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_F_4 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_F_4 : component is "O";
component OBUFT_LVCMOS15_F_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_F_6 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_F_6 : component is "O";
component OBUFT_LVCMOS15_F_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_F_8 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_F_8 : component is "O";
component OBUFT_LVCMOS15_S_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_S_12 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_S_12 : component is "O";
component OBUFT_LVCMOS15_S_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_S_16 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_S_16 : component is "O";
component OBUFT_LVCMOS15_S_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_S_2 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_S_2 : component is "O";
component OBUFT_LVCMOS15_S_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_S_4 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_S_4 : component is "O";
component OBUFT_LVCMOS15_S_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_S_6 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_S_6 : component is "O";
component OBUFT_LVCMOS15_S_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_S_8 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_S_8 : component is "O";
component OBUFT_LVCMOS18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18 : component is "O";
component OBUFT_LVCMOS18_F_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_F_12 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_F_12 : component is "O";
component OBUFT_LVCMOS18_F_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_F_16 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_F_16 : component is "O";
component OBUFT_LVCMOS18_F_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_F_2 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_F_2 : component is "O";
component OBUFT_LVCMOS18_F_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_F_4 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_F_4 : component is "O";
component OBUFT_LVCMOS18_F_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_F_6 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_F_6 : component is "O";
component OBUFT_LVCMOS18_F_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_F_8 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_F_8 : component is "O";
component OBUFT_LVCMOS18_S_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_S_12 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_S_12 : component is "O";
component OBUFT_LVCMOS18_S_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_S_16 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_S_16 : component is "O";
component OBUFT_LVCMOS18_S_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_S_2 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_S_2 : component is "O";
component OBUFT_LVCMOS18_S_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_S_4 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_S_4 : component is "O";
component OBUFT_LVCMOS18_S_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_S_6 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_S_6 : component is "O";
component OBUFT_LVCMOS18_S_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_S_8 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_S_8 : component is "O";
component OBUFT_LVCMOS2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS2 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS2 : component is "O";
component OBUFT_LVCMOS25
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25 : component is "O";
component OBUFT_LVCMOS25_F_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_F_12 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_F_12 : component is "O";
component OBUFT_LVCMOS25_F_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_F_16 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_F_16 : component is "O";
component OBUFT_LVCMOS25_F_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_F_2 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_F_2 : component is "O";
component OBUFT_LVCMOS25_F_24
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_F_24 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_F_24 : component is "O";
component OBUFT_LVCMOS25_F_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_F_4 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_F_4 : component is "O";
component OBUFT_LVCMOS25_F_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_F_6 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_F_6 : component is "O";
component OBUFT_LVCMOS25_F_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_F_8 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_F_8 : component is "O";
component OBUFT_LVCMOS25_S_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_S_12 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_S_12 : component is "O";
component OBUFT_LVCMOS25_S_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_S_16 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_S_16 : component is "O";
component OBUFT_LVCMOS25_S_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_S_2 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_S_2 : component is "O";
component OBUFT_LVCMOS25_S_24
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_S_24 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_S_24 : component is "O";
component OBUFT_LVCMOS25_S_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_S_4 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_S_4 : component is "O";
component OBUFT_LVCMOS25_S_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_S_6 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_S_6 : component is "O";
component OBUFT_LVCMOS25_S_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_S_8 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_S_8 : component is "O";
component OBUFT_LVDCI_15
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDCI_15 : component is true;
attribute black_box_tri_pins of OBUFT_LVDCI_15 : component is "O";
component OBUFT_LVDCI_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDCI_18 : component is true;
attribute black_box_tri_pins of OBUFT_LVDCI_18 : component is "O";
component OBUFT_LVDCI_25
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDCI_25 : component is true;
attribute black_box_tri_pins of OBUFT_LVDCI_25 : component is "O";
component OBUFT_LVDCI_33
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDCI_33 : component is true;
attribute black_box_tri_pins of OBUFT_LVDCI_33 : component is "O";
component OBUFT_LVDCI_DV2_15
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDCI_DV2_15 : component is true;
attribute black_box_tri_pins of OBUFT_LVDCI_DV2_15 : component is "O";
component OBUFT_LVDCI_DV2_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDCI_DV2_18 : component is true;
attribute black_box_tri_pins of OBUFT_LVDCI_DV2_18 : component is "O";
component OBUFT_LVDCI_DV2_25
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDCI_DV2_25 : component is true;
attribute black_box_tri_pins of OBUFT_LVDCI_DV2_25 : component is "O";
component OBUFT_LVDS
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDS : component is true;
attribute black_box_tri_pins of OBUFT_LVDS : component is "O";
component OBUFT_LVPECL
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVPECL : component is true;
attribute black_box_tri_pins of OBUFT_LVPECL : component is "O";
component OBUFT_PCI33_3
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_PCI33_3 : component is true;
attribute black_box_tri_pins of OBUFT_PCI33_3 : component is "O";
component OBUFT_PCI66_3
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_PCI66_3 : component is true;
attribute black_box_tri_pins of OBUFT_PCI66_3 : component is "O";
component OBUFT_PCIX
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_PCIX : component is true;
attribute black_box_tri_pins of OBUFT_PCIX : component is "O";
component OBUFT_SSTL2_I
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_SSTL2_I : component is true;
attribute black_box_tri_pins of OBUFT_SSTL2_I : component is "O";
component OBUFT_SSTL2_I_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_SSTL2_I_DCI : component is true;
attribute black_box_tri_pins of OBUFT_SSTL2_I_DCI : component is "O";
component OBUFT_SSTL2_II
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_SSTL2_II : component is true;
attribute black_box_tri_pins of OBUFT_SSTL2_II : component is "O";
component OBUFT_SSTL2_II_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_SSTL2_II_DCI : component is true;
attribute black_box_tri_pins of OBUFT_SSTL2_II_DCI : component is "O";
component OBUFT_S_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_S_12 : component is true;
attribute black_box_tri_pins of OBUFT_S_12 : component is "O";
component OBUFT_S_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_S_16 : component is true;
attribute black_box_tri_pins of OBUFT_S_16 : component is "O";
component OBUFT_S_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_S_2 : component is true;
attribute black_box_tri_pins of OBUFT_S_2 : component is "O";
component OBUFT_S_24
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_S_24 : component is true;
attribute black_box_tri_pins of OBUFT_S_24 : component is "O";
component OBUFT_S_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_S_4 : component is true;
attribute black_box_tri_pins of OBUFT_S_4 : component is "O";
component OBUFT_S_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_S_6 : component is true;
attribute black_box_tri_pins of OBUFT_S_6 : component is "O";
component OBUFT_S_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_S_8 : component is true;
attribute black_box_tri_pins of OBUFT_S_8 : component is "O";
component OBUF_AGP
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_AGP : component is true;
component OBUF_F_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_F_12 : component is true;
component OBUF_F_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_F_16 : component is true;
component OBUF_F_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_F_2 : component is true;
component OBUF_F_24
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_F_24 : component is true;
component OBUF_F_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_F_4 : component is true;
component OBUF_F_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_F_6 : component is true;
component OBUF_F_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_F_8 : component is true;
component OBUF_GTL
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_GTL : component is true;
component OBUF_GTL_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_GTL_DCI : component is true;
component OBUF_GTLP
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_GTLP : component is true;
component OBUF_GTLP_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_GTLP_DCI : component is true;
component OBUF_HSTL_I
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_I : component is true;
component OBUF_HSTL_I_18
port (
O : out std_logic;
i : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_I_18 : component is true;
component OBUF_HSTL_I_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_I_DCI : component is true;
component OBUF_HSTL_I_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_Box of OBUF_HSTL_I_DCI_18 : component is true;
component OBUF_HSTL_II
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_II : component is true;
component OBUF_HSTL_II_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_II_18 : component is true;
component OBUF_HSTL_II_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_II_DCI : component is true;
component OBUF_HSTL_II_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_II_DCI_18 : component is true;
component OBUF_HSTL_III
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_III : component is true;
component OBUF_HSTL_III_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_III_18 : component is true;
component OBUF_HSTL_III_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_III_DCI : component is true;
component OBUF_HSTL_IV
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_IV : component is true;
component OBUF_HSTL_IV_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_IV_18 : component is true;
component OBUF_HSTL_IV_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_IV_DCI : component is true;
component OBUF_HSTL_IV_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_IV_DCI_18 : component is true;
component OBUF_LVCMOS15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15 : component is true;
component OBUF_LVCMOS15_F_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_F_12 : component is true;
component OBUF_LVCMOS15_F_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_F_16 : component is true;
component OBUF_LVCMOS15_F_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_F_2 : component is true;
component OBUF_LVCMOS15_F_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_F_4 : component is true;
component OBUF_LVCMOS15_F_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_F_6 : component is true;
component OBUF_LVCMOS15_F_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_F_8 : component is true;
component OBUF_LVCMOS15_S_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_S_12 : component is true;
component OBUF_LVCMOS15_S_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_S_16 : component is true;
component OBUF_LVCMOS15_S_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_S_2 : component is true;
component OBUF_LVCMOS15_S_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_S_4 : component is true;
component OBUF_LVCMOS15_S_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_S_6 : component is true;
component OBUF_LVCMOS15_S_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_S_8 : component is true;
component OBUF_LVCMOS18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18 : component is true;
component OBUF_LVCMOS18_F_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_F_12 : component is true;
component OBUF_LVCMOS18_F_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_F_16 : component is true;
component OBUF_LVCMOS18_F_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_F_2 : component is true;
component OBUF_LVCMOS18_F_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_F_4 : component is true;
component OBUF_LVCMOS18_F_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_F_6 : component is true;
component OBUF_LVCMOS18_F_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_F_8 : component is true;
component OBUF_LVCMOS18_S_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_S_12 : component is true;
component OBUF_LVCMOS18_S_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_S_16 : component is true;
component OBUF_LVCMOS18_S_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_S_2 : component is true;
component OBUF_LVCMOS18_S_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_S_4 : component is true;
component OBUF_LVCMOS18_S_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_S_6 : component is true;
component OBUF_LVCMOS18_S_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_S_8 : component is true;
component OBUF_LVCMOS2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS2 : component is true;
component OBUF_LVCMOS25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25 : component is true;
component OBUF_LVCMOS25_F_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_F_12 : component is true;
component OBUF_LVCMOS25_F_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_F_16 : component is true;
component OBUF_LVCMOS25_F_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_F_2 : component is true;
component OBUF_LVCMOS25_F_24
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_F_24 : component is true;
component OBUF_LVCMOS25_F_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_F_4 : component is true;
component OBUF_LVCMOS25_F_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_F_6 : component is true;
component OBUF_LVCMOS25_F_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_F_8 : component is true;
component OBUF_LVCMOS25_S_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_S_12 : component is true;
component OBUF_LVCMOS25_S_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_S_16 : component is true;
component OBUF_LVCMOS25_S_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_S_2 : component is true;
component OBUF_LVCMOS25_S_24
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_S_24 : component is true;
component OBUF_LVCMOS25_S_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_S_4 : component is true;
component OBUF_LVCMOS25_S_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_S_6 : component is true;
component OBUF_LVCMOS25_S_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_S_8 : component is true;
component OBUF_LVDS
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDS : component is true;
component OBUF_LVDCI_15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDCI_15 : component is true;
component OBUF_LVDCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDCI_18 : component is true;
component OBUF_LVDCI_25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDCI_25 : component is true;
component OBUF_LVDCI_33
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDCI_33 : component is true;
component OBUF_LVDCI_DV2_15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDCI_DV2_15 : component is true;
component OBUF_LVDCI_DV2_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDCI_DV2_18 : component is true;
component OBUF_LVDCI_DV2_25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDCI_DV2_25 : component is true;
component OBUF_LVPECL
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVPECL : component is true;
component OBUF_PCI33_3
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_PCI33_3 : component is true;
component OBUF_PCI66_3
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_PCI66_3 : component is true;
component OBUF_PCIX
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_PCIX : component is true;
component OBUF_SSTL2_I
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_SSTL2_I : component is true;
component OBUF_SSTL2_I_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_SSTL2_I_DCI : component is true;
component OBUF_SSTL2_II
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_SSTL2_II : component is true;
component OBUF_SSTL2_II_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_SSTL2_II_DCI : component is true;
component OBUF_S_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_S_12 : component is true;
component OBUF_S_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_S_16 : component is true;
component OBUF_S_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_S_2 : component is true;
component OBUF_S_24
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_S_24 : component is true;
component OBUF_S_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_S_4 : component is true;
component OBUF_S_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_S_6 : component is true;
component OBUF_S_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_S_8 : component is true;
component ORCY
port (
O : out std_logic;
CI : in std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of ORCY : component is true;
component PULLDOWN
port (
O : out std_logic
);
end component;
attribute syn_black_box of PULLDOWN : component is true;
attribute syn_noprune of PULLDOWN : component is true;
component PULLUP
port (
O : out std_logic
);
end component;
attribute syn_black_box of PULLUP : component is true;
attribute syn_noprune of PULLUP : component is true;
component RAM128X1S
generic(INIT : bit_vector := X"00000000000000000000000000000000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
A6 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM128X1S : component is true;
component RAM128X1S_1
generic(INIT : bit_vector := X"00000000000000000000000000000000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
A6 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM128X1S_1 : component is true;
component RAM16X1D
generic(INIT : bit_vector := X"0000");
port (
DPO : out std_logic;
SPO : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM16X1D : component is true;
component RAM16X1D_1
generic(INIT : bit_vector := X"0000");
port (
DPO : out std_logic;
SPO : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM16X1D_1 : component is true;
component RAM16X1S
generic(INIT : bit_vector := X"0000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM16X1S : component is true;
component RAM16X1S_1
generic(INIT : bit_vector := X"0000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM16X1S_1 : component is true;
component RAM16X2S
generic (
INIT_00 : bit_vector(15 downto 0) := X"0000";
INIT_01 : bit_vector(15 downto 0) := X"0000"
);
port (
O0 : out std_logic;
O1 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM16X2S : component is true;
component RAM16X4S
generic (
INIT_00 : bit_vector(15 downto 0) := X"0000";
INIT_01 : bit_vector(15 downto 0) := X"0000";
INIT_02 : bit_vector(15 downto 0) := X"0000";
INIT_03 : bit_vector(15 downto 0) := X"0000"
);
port (
O0 : out std_logic;
O1 : out std_logic;
O2 : out std_logic;
O3 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM16X4S : component is true;
component RAM16X8S
generic (
INIT_00 : bit_vector(15 downto 0) := X"0000";
INIT_01 : bit_vector(15 downto 0) := X"0000";
INIT_02 : bit_vector(15 downto 0) := X"0000";
INIT_03 : bit_vector(15 downto 0) := X"0000";
INIT_04 : bit_vector(15 downto 0) := X"0000";
INIT_05 : bit_vector(15 downto 0) := X"0000";
INIT_06 : bit_vector(15 downto 0) := X"0000";
INIT_07 : bit_vector(15 downto 0) := X"0000"
);
port (
O : out std_logic_vector(7 downto 0);
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D : in std_logic_vector(7 downto 0);
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM16X8S : component is true;
component RAM32X1D
generic(INIT : bit_vector := X"00000000");
port (
DPO : out std_logic;
SPO : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
D : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
DPRA4 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM32X1D : component is true;
component RAM32X1D_1
generic(INIT : bit_vector := X"00000000");
port (
DPO : out std_logic;
SPO : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
D : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
DPRA4 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM32X1D_1 : component is true;
component RAM32X1S
generic(INIT : bit_vector := X"00000000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM32X1S : component is true;
component RAM32X1S_1
generic(INIT : bit_vector := X"00000000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM32X1S_1 : component is true;
component RAM32X2S
generic (
INIT_00 : bit_vector(31 downto 0) := X"00000000";
INIT_01 : bit_vector(31 downto 0) := X"00000000"
);
port (
O0 : out std_logic;
O1 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM32X2S : component is true;
component RAM32X4S
generic (
INIT_00 : bit_vector(31 downto 0) := X"00000000";
INIT_01 : bit_vector(31 downto 0) := X"00000000";
INIT_02 : bit_vector(31 downto 0) := X"00000000";
INIT_03 : bit_vector(31 downto 0) := X"00000000"
);
port (
O0 : out std_logic;
O1 : out std_logic;
O2 : out std_logic;
O3 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM32X4S : component is true;
component RAM32X8S
generic (
INIT_00 : bit_vector(31 downto 0) := X"00000000";
INIT_01 : bit_vector(31 downto 0) := X"00000000";
INIT_02 : bit_vector(31 downto 0) := X"00000000";
INIT_03 : bit_vector(31 downto 0) := X"00000000";
INIT_04 : bit_vector(31 downto 0) := X"00000000";
INIT_05 : bit_vector(31 downto 0) := X"00000000";
INIT_06 : bit_vector(31 downto 0) := X"00000000";
INIT_07 : bit_vector(31 downto 0) := X"00000000"
);
port (
O : out std_logic_vector(7 downto 0);
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
D : in std_logic_vector(7 downto 0);
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM32X8S : component is true;
component RAM64X1D
generic (INIT : bit_vector := X"0000000000000000");
port (
DPO : out std_logic;
SPO : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
D : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
DPRA4 : in std_logic;
DPRA5 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM64X1D : component is true;
component RAM64X1D_1
generic (INIT : bit_vector := X"0000000000000000");
port (
DPO : out std_logic;
SPO : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
D : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
DPRA4 : in std_logic;
DPRA5 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM64X1D_1 : component is true;
component RAM64X1S
generic (INIT : bit_vector := X"0000000000000000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM64X1S : component is true;
component RAM64X1S_1
generic (INIT : bit_vector := X"0000000000000000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM64X1S_1 : component is true;
component RAM64X2S
generic (
INIT_00 : bit_vector(63 downto 0) := X"0000000000000000";
INIT_01 : bit_vector(63 downto 0) := X"0000000000000000"
);
port (
O0 : out std_logic;
O1 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM64X2S : component is true;
component RAMB4_S1
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (11 downto 0);
DI : in std_logic_vector (0 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S1 : component is true;
component RAMB4_S16
port (
DO : out std_logic_vector (15 downto 0);
ADDR : in std_logic_vector (7 downto 0);
DI : in std_logic_vector (15 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S16 : component is true;
component RAMB4_S16_S16
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
ADDRA : in std_logic_vector (7 downto 0);
DIA : in std_logic_vector (15 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (15 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S16_S16 : component is true;
component RAMB4_S1_S1
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (11 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S1_S1 : component is true;
component RAMB4_S1_S16
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (15 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (15 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S1_S16 : component is true;
component RAMB4_S1_S2
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (10 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S1_S2 : component is true;
component RAMB4_S1_S4
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S1_S4 : component is true;
component RAMB4_S1_S8
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S1_S8 : component is true;
component RAMB4_S2
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (10 downto 0);
DI : in std_logic_vector (1 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S2 : component is true;
component RAMB4_S2_S16
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (15 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (15 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S2_S16 : component is true;
component RAMB4_S2_S2
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (10 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S2_S2 : component is true;
component RAMB4_S2_S4
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S2_S4 : component is true;
component RAMB4_S2_S8
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S2_S8 : component is true;
component RAMB4_S4
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (9 downto 0);
DI : in std_logic_vector (3 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S4 : component is true;
component RAMB4_S4_S16
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (15 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
DIA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (15 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S4_S16 : component is true;
component RAMB4_S4_S4
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
DIA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S4_S4 : component is true;
component RAMB4_S4_S8
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
DIA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S4_S8 : component is true;
component RAMB4_S8
port (
DO : out std_logic_vector (7 downto 0);
ADDR : in std_logic_vector (8 downto 0);
DI : in std_logic_vector (7 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S8 : component is true;
component RAMB4_S8_S16
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (15 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (7 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (15 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S8_S16 : component is true;
component RAMB4_S8_S8
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (7 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
component RAMB16_S1
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
DI : in std_logic_vector (0 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
SSR : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S1 : component is true;
component RAMB16_S18
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
SSR : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S18 : component is true;
component RAMB16_S18_S18
port (
DOA : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (15 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S18_S18 : component is true;
component RAMB16_S18_S36
port (
DOA : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (31 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S18_S36 : component is true;
component RAMB16_S1_S1
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (13 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (0 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S1_S1 : component is true;
component RAMB16_S1_S18
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (15 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S1_S18 : component is true;
component RAMB16_S1_S2
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (12 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S1_S2 : component is true;
component RAMB16_S1_S36
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (31 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S1_S36 : component is true;
component RAMB16_S1_S4
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (11 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S1_S4 : component is true;
component RAMB16_S1_S9
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (10 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (7 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S1_S9 : component is true;
component RAMB16_S2
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
DI : in std_logic_vector (1 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
SSR : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S2 : component is true;
component RAMB16_S2_S18
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (15 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S2_S18 : component is true;
component RAMB16_S2_S2
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (12 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S2_S2 : component is true;
component RAMB16_S2_S36
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (31 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S2_S36 : component is true;
component RAMB16_S2_S4
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (11 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S2_S4 : component is true;
component RAMB16_S2_S9
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (10 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (7 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S2_S9 : component is true;
component RAMB16_S36
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
SSR : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S36 : component is true;
component RAMB16_S36_S36
port (
DOA : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (31 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S36_S36 : component is true;
component RAMB16_S4
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
DI : in std_logic_vector (3 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
SSR : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S4 : component is true;
component RAMB16_S4_S18
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (15 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S4_S18 : component is true;
component RAMB16_S4_S36
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (31 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S4_S36 : component is true;
component RAMB16_S4_S4
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (11 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S4_S4 : component is true;
component RAMB16_S4_S9
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (10 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (7 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S4_S9 : component is true;
component RAMB16_S9
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
SSR : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S9 : component is true;
component RAMB16_S9_S18
port (
DOA : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (15 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S9_S18 : component is true;
component RAMB16_S9_S36
port (
DOA : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (31 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S9_S36 : component is true;
component RAMB16_S9_S9
port (
DOA : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (10 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (7 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S9_S9 : component is true;
component ROM16X1
generic(INIT : bit_vector := X"0000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic
);
end component;
attribute syn_black_box of ROM16X1 : component is true;
component ROM32X1
generic(INIT : bit_vector := X"00000000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic
);
end component;
attribute syn_black_box of ROM32X1 : component is true;
component ROM128X1
generic(INIT : bit_vector := X"00000000000000000000000000000000");
port (A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
O : out std_ulogic
);
end component;
attribute syn_black_box of ROM128X1 : component is true;
component ROM256X1
generic(INIT : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
port (A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
A7 : in std_ulogic;
O : out std_ulogic
);
end component;
attribute syn_black_box of ROM256X1 : component is true;
component ROM64X1
generic(INIT : bit_vector := X"0000000000000000");
port (A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
O : out std_ulogic
);
end component;
attribute syn_black_box of ROM64X1 : component is true;
component SRL16
port (
Q : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRL16 : component is true;
component SRL16E
port (
Q : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRL16E : component is true;
component SRL16E_1
port (
Q : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRL16E_1 : component is true;
component SRL16_1
port (
Q : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRL16_1 : component is true;
component SRLC16
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRLC16 : component is true;
component SRLC16E
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRLC16E : component is true;
component SRLC16E_1
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRLC16E_1 : component is true;
component SRLC16_1
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRLC16_1 : component is true;
component STARTUP_VIRTEX2_CLK
port (
CLK : in std_logic
);
end component;
attribute syn_black_box of STARTUP_VIRTEX2_CLK : component is true;
attribute syn_noprune of STARTUP_VIRTEX2_CLK : component is true;
attribute xc_alias of STARTUP_VIRTEX2_CLK : component is "STARTUP_VIRTEX2";
component STARTUP_VIRTEX2_GSR
port (
GSR : in std_logic
);
end component;
attribute syn_black_box of STARTUP_VIRTEX2_GSR : component is true;
attribute syn_noprune of STARTUP_VIRTEX2_GSR : component is true;
attribute xc_alias of STARTUP_VIRTEX2_GSR : component is "STARTUP_VIRTEX2";
component STARTUP_VIRTEX2_GTS
port (
GTS : in std_logic
);
end component;
attribute syn_black_box of STARTUP_VIRTEX2_GTS : component is true;
attribute syn_noprune of STARTUP_VIRTEX2_GTS : component is true;
attribute xc_alias of STARTUP_VIRTEX2_GTS : component is "STARTUP_VIRTEX2";
component STARTUP_VIRTEX2_ALL
port (
CLK,GSR,GTS : in std_logic := '0'
);
end component;
attribute syn_black_box of STARTUP_VIRTEX2_ALL : component is true;
attribute syn_noprune of STARTUP_VIRTEX2_ALL : component is true;
attribute xc_alias of STARTUP_VIRTEX2_ALL : component is "STARTUP_VIRTEX2";
component STARTUP_VIRTEX2
port (
CLK : in std_logic;
GSR : in std_logic;
GTS : in std_logic
);
end component;
component VCC
port (
P : out std_logic
);
end component;
attribute syn_black_box of VCC : component is true;
attribute syn_noprune of VCC : component is true;
component XORCY
port (
O : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end component;
attribute syn_black_box of XORCY : component is true;
component XORCY_D
port (
O : out std_logic;
LO : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end component;
attribute syn_black_box of XORCY_D : component is true;
component XORCY_L
port (
LO : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end component;
attribute syn_black_box of XORCY_L : component is true;
component GT_SWIFT
port (
TX_CRC_FORCE_VALUE : in std_logic_vector(7 downto 0);
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXCLKCORCNT : out std_logic_vector(2 downto 0);
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
RXP : in std_logic;
RXN : in std_logic;
GSR : in std_logic;
TXP : out std_logic;
TXN : out std_logic;
CONFIGENABLE : in std_logic;
CONFIGIN : in std_logic;
CONFIGOUT : out std_logic;
CRC_END_OF_PKT : in std_logic_vector(7 downto 0);
CRC_FORMAT : in std_logic_vector(1 downto 0);
CRC_START_OF_PKT : in std_logic_vector(7 downto 0);
CHAN_BOND_LIMIT : in std_logic_vector(4 downto 0);
REFCLK : in std_logic;
REFCLK2 : in std_logic;
REFCLKSEL : in std_logic;
RXUSRCLK : in std_logic;
TXUSRCLK : in std_logic;
RXUSRCLK2 : in std_logic;
TXUSRCLK2 : in std_logic;
RXRESET : in std_logic;
TXRESET : in std_logic;
POWERDOWN : in std_logic;
LOOPBACK : in std_logic_vector(1 downto 0);
TXDATA : in std_logic_vector(31 downto 0);
RX_LOSS_OF_SYNC_FSM : in std_logic;
RX_LOS_INVALID_INCR : in std_logic_vector(2 downto 0);
RX_LOS_THRESHOLD : in std_logic_vector(2 downto 0);
TXCHARDISPMODE : in std_logic_vector(3 downto 0);
TXCHARDISPVAL : in std_logic_vector(3 downto 0);
TXCHARISK : in std_logic_vector(3 downto 0);
TXBYPASS8B10B : in std_logic_vector(3 downto 0);
TXPOLARITY : in std_logic;
TXINHIBIT : in std_logic;
ENCHANSYNC : in std_logic;
RXPOLARITY : in std_logic;
CHBONDI : in std_logic_vector(3 downto 0);
RXRECCLK : out std_logic;
TXBUFERR : out std_logic;
TXFORCECRCERR : in std_logic;
TXRUNDISP : out std_logic_vector(3 downto 0);
TXKERR : out std_logic_vector(3 downto 0);
RXREALIGN : out std_logic;
RXCOMMADET : out std_logic;
RXCHECKINGCRC : out std_logic;
RXCRCERR : out std_logic;
RXDATA : out std_logic_vector(31 downto 0);
RXCHARISCOMMA : out std_logic_vector(3 downto 0);
RXCHARISK : out std_logic_vector(3 downto 0);
RXNOTINTABLE : out std_logic_vector(3 downto 0);
RXDISPERR : out std_logic_vector(3 downto 0);
RXRUNDISP : out std_logic_vector(3 downto 0);
RXBUFSTATUS : out std_logic_vector(1 downto 0);
CHBONDO : out std_logic_vector(3 downto 0);
CHBONDDONE : out std_logic;
TX_PREEMPHASIS : in std_logic_vector(1 downto 0);
TX_DIFF_CTRL : in std_logic_vector(2 downto 0);
RX_TERM_IMP : in std_logic;
SERDES_10B : in std_logic;
ALIGN_COMMA_MSB : in std_logic;
PCOMMA_DETECT : in std_logic;
PCOMMA_ALIGN : in std_logic;
MCOMMA_DETECT : in std_logic;
MCOMMA_ALIGN : in std_logic;
PCOMMA_10B_VALUE : in std_logic_vector(0 to 9);
MCOMMA_10B_VALUE : in std_logic_vector(0 to 9);
COMMA_10B_MASK : in std_logic_vector(0 to 9);
DEC_PCOMMA_DETECT : in std_logic;
DEC_MCOMMA_DETECT : in std_logic;
DEC_VALID_COMMA_ONLY : in std_logic;
RX_DECODE_USE : in std_logic;
RX_BUFFER_USE : in std_logic;
TX_BUFFER_USE : in std_logic;
CLK_CORRECT_USE : in std_logic;
CLK_COR_SEQ_LEN : in std_logic_vector(1 downto 0);
CLK_COR_INSERT_IDLE_FLAG : in std_logic;
CLK_COR_KEEP_IDLE : in std_logic;
CLK_COR_REPEAT_WAIT : in std_logic_vector(4 downto 0);
CLK_COR_SEQ_1_1 : in std_logic_vector(10 downto 0);
CLK_COR_SEQ_1_2 : in std_logic_vector(10 downto 0);
CLK_COR_SEQ_1_3 : in std_logic_vector(10 downto 0);
CLK_COR_SEQ_1_4 : in std_logic_vector(10 downto 0);
CLK_COR_SEQ_2_USE : in std_logic;
CLK_COR_SEQ_2_1 : in std_logic_vector(10 downto 0);
CLK_COR_SEQ_2_2 : in std_logic_vector(10 downto 0);
CLK_COR_SEQ_2_3 : in std_logic_vector(10 downto 0);
CLK_COR_SEQ_2_4 : in std_logic_vector(10 downto 0);
CHAN_BOND_MODE : in std_logic_vector(1 downto 0);
CHAN_BOND_SEQ_LEN : in std_logic_vector(1 downto 0);
CHAN_BOND_SEQ_1_1 : in std_logic_vector(10 downto 0);
CHAN_BOND_SEQ_1_2 : in std_logic_vector(10 downto 0);
CHAN_BOND_SEQ_1_3 : in std_logic_vector(10 downto 0);
CHAN_BOND_SEQ_1_4 : in std_logic_vector(10 downto 0);
CHAN_BOND_SEQ_2_USE : in std_logic;
CHAN_BOND_SEQ_2_1 : in std_logic_vector(10 downto 0);
CHAN_BOND_SEQ_2_2 : in std_logic_vector(10 downto 0);
CHAN_BOND_SEQ_2_3 : in std_logic_vector(10 downto 0);
CHAN_BOND_SEQ_2_4 : in std_logic_vector(10 downto 0);
CHAN_BOND_WAIT : in std_logic_vector(3 downto 0);
CHAN_BOND_OFFSET : in std_logic_vector(3 downto 0);
TX_CRC_USE : in std_logic;
RX_CRC_USE : in std_logic;
CHAN_BOND_ONE_SHOT : in std_logic;
RX_DATA_WIDTH : in std_logic_vector(1 downto 0);
TX_DATA_WIDTH : in std_logic_vector(1 downto 0)
);
end component;
attribute syn_black_box of GT_SWIFT : component is true;
component GT
port (
CHBONDDONE : out std_ulogic;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 3 downto 0);
RXCHARISK : out std_logic_vector ( 3 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 31 downto 0);
RXDISPERR : out std_logic_vector ( 3 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 3 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 3 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 3 downto 0 );
TXN : out std_ulogic;
TXP : out std_ulogic ;
TXRUNDISP : out std_logic_vector ( 3 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 3 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 3 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 3 downto 0 );
TXCHARISK : in std_logic_vector ( 3 downto 0 );
TXDATA : in std_logic_vector ( 31 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end Component;
attribute syn_black_box of GT : component is true;
component GT_AURORA_1
port (
CHBONDDONE : out std_ulogic ;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 0 downto 0);
RXCHARISK : out std_logic_vector ( 0 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 7 downto 0);
RXDISPERR : out std_logic_vector ( 0 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 0 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 0 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 0 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 0 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 0 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 0 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 0 downto 0 );
TXCHARISK : in std_logic_vector ( 0 downto 0 );
TXDATA : in std_logic_vector ( 7 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_AURORA_1 : component is true;
component GT_AURORA_2
port (
CHBONDDONE : out std_ulogic ;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 1 downto 0);
RXCHARISK : out std_logic_vector ( 1 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 15 downto 0);
RXDISPERR : out std_logic_vector ( 1 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 1 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 1 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 1 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 1 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 1 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 1 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 1 downto 0 );
TXCHARISK : in std_logic_vector ( 1 downto 0 );
TXDATA : in std_logic_vector ( 15 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_AURORA_2 : component is true;
component GT_AURORA_4
port (
CHBONDDONE : out std_ulogic ;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 3 downto 0);
RXCHARISK : out std_logic_vector ( 3 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 31 downto 0);
RXDISPERR : out std_logic_vector ( 3 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 3 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 3 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 3 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 3 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 3 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 3 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 3 downto 0 );
TXCHARISK : in std_logic_vector ( 3 downto 0 );
TXDATA : in std_logic_vector ( 31 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_AURORA_4 : component is true;
component GT_CUSTOM
port (
CHBONDDONE : out std_ulogic;
CHBONDO : out std_logic_vector(3 DOWNTO 0);
CONFIGOUT : out std_ulogic;
RXBUFSTATUS : out std_logic_vector(1 DOWNTO 0);
RXCHARISCOMMA : out std_logic_vector(3 DOWNTO 0);
RXCHARISK : out std_logic_vector(3 DOWNTO 0);
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 DOWNTO 0);
RXCOMMADET : out std_ulogic;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector(31 DOWNTO 0);
RXDISPERR : out std_logic_vector(3 DOWNTO 0);
RXLOSSOFSYNC : out std_logic_vector(1 DOWNTO 0);
RXNOTINTABLE : out std_logic_vector(3 DOWNTO 0);
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic;
RXRUNDISP : out std_logic_vector(3 DOWNTO 0);
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector(3 DOWNTO 0);
TXN : out std_ulogic;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector(3 DOWNTO 0);
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector(3 DOWNTO 0);
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic;
ENCHANSYNC : in std_ulogic;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector(1 DOWNTO 0);
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic;
RXP : in std_ulogic;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector(3 DOWNTO 0);
TXCHARDISPMODE : in std_logic_vector(3 DOWNTO 0);
TXCHARDISPVAL : in std_logic_vector(3 DOWNTO 0);
TXCHARISK : in std_logic_vector(3 DOWNTO 0);
TXDATA : in std_logic_vector(31 DOWNTO 0);
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2 : in std_logic
) ;
end component;
attribute syn_black_box of GT_CUSTOM : component is true;
component GT_ETHERNET_4
port (
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 3 downto 0);
RXCHARISK : out std_logic_vector ( 3 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 31 downto 0);
RXDISPERR : out std_logic_vector ( 3 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 3 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 3 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 3 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 3 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 3 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 3 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 3 downto 0 );
TXCHARISK : in std_logic_vector ( 3 downto 0 );
TXDATA : in std_logic_vector ( 31 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_ETHERNET_4 : component is true;
component GT_ETHERNET_1
port (
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 0 downto 0);
RXCHARISK : out std_logic_vector ( 0 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXDATA : out std_logic_vector ( 7 downto 0);
RXDISPERR : out std_logic_vector ( 0 downto 0) ;
RXNOTINTABLE : out std_logic_vector ( 0 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 0 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 0 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 0 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 0 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 0 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 0 downto 0 );
TXCHARISK : in std_logic_vector ( 0 downto 0 );
TXDATA : in std_logic_vector ( 7 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2 : in std_ulogic
);
end component;
attribute syn_black_box of GT_ETHERNET_1 : component is true;
component GT_ETHERNET_2
port (
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 1 downto 0);
RXCHARISK : out std_logic_vector ( 1 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 15 downto 0);
RXDISPERR : out std_logic_vector ( 1 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 1 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 1 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 1 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 1 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 1 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 1 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 1 downto 0 );
TXCHARISK : in std_logic_vector ( 1 downto 0 );
TXDATA : in std_logic_vector ( 15 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2 : in std_ulogic
);
end component;
attribute syn_black_box of GT_ETHERNET_2 : component is true;
component GT_FIBRE_CHAN_1
port (
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 0 downto 0);
RXCHARISK : out std_logic_vector ( 0 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 7 downto 0);
RXDISPERR : out std_logic_vector ( 0 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 0 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 0 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 0 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 0 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXFORCECRCERR : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 0 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 0 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 0 downto 0 );
TXCHARISK : in std_logic_vector ( 0 downto 0 );
TXDATA : in std_logic_vector ( 7 downto 0 );
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_FIBRE_CHAN_1 : component is true;
component GT_FIBRE_CHAN_2
port (
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 1 downto 0);
RXCHARISK : out std_logic_vector ( 1 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 15 downto 0);
RXDISPERR : out std_logic_vector ( 1 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 1 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 1 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 1 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 1 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 1 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 1 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 1 downto 0 );
TXCHARISK : in std_logic_vector ( 1 downto 0 );
TXDATA : in std_logic_vector ( 15 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_FIBRE_CHAN_2 : component is true;
component GT_FIBRE_CHAN_4
port (
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 3 downto 0);
RXCHARISK : out std_logic_vector ( 3 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 31 downto 0);
RXDISPERR : out std_logic_vector ( 3 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 3 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 3 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 3 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 3 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 3 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 3 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 3 downto 0 );
TXCHARISK : in std_logic_vector ( 3 downto 0 );
TXDATA : in std_logic_vector ( 31 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_FIBRE_CHAN_4 : component is true;
component GT_INFINIBAND_1
port (
CHBONDO : out std_logic_vector ( 3 downto 0 );
CHBONDDONE : out std_ulogic ;
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 0 downto 0);
RXCHARISK : out std_logic_vector ( 0 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 7 downto 0);
RXDISPERR : out std_logic_vector ( 0 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 0 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 0 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 0 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 0 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 0 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 0 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 0 downto 0 );
TXCHARISK : in std_logic_vector ( 0 downto 0 );
TXDATA : in std_logic_vector ( 7 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2 : in std_ulogic
);
end component;
attribute syn_black_box of GT_INFINIBAND_1 : component is true;
component GT_INFINIBAND_2
port (
CHBONDDONE : out std_ulogic ;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 1 downto 0);
RXCHARISK : out std_logic_vector ( 1 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 15 downto 0);
RXDISPERR : out std_logic_vector ( 1 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 1 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 1 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 1 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 1 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic ;
REFCLKSEL : in std_ulogic ;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 1 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 1 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 1 downto 0 );
TXCHARISK : in std_logic_vector ( 1 downto 0 );
TXDATA : in std_logic_vector ( 15 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2 : in std_ulogic
);
end component;
attribute syn_black_box of GT_INFINIBAND_2 : component is true;
component GT_INFINIBAND_4
port (
CHBONDO : out std_logic_vector ( 3 downto 0 );
CHBONDDONE : out std_ulogic ;
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 3 downto 0);
RXCHARISK : out std_logic_vector ( 3 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 31 downto 0);
RXDISPERR : out std_logic_vector ( 3 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 3 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 3 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 3 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 3 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 3 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 3 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 3 downto 0 );
TXCHARISK : in std_logic_vector ( 3 downto 0 );
TXDATA : in std_logic_vector ( 31 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_INFINIBAND_4 : component is true;
component GT_XAUI_1
port (
CHBONDDONE : out std_ulogic ;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 0 downto 0);
RXCHARISK : out std_logic_vector ( 0 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 7 downto 0);
RXDISPERR : out std_logic_vector ( 0 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 0 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 0 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 0 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 0 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 0 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 0 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 0 downto 0 );
TXCHARISK : in std_logic_vector ( 0 downto 0 );
TXDATA : in std_logic_vector ( 7 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_XAUI_1 : component is true;
component GT_XAUI_2
port (
CHBONDDONE : out std_ulogic ;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 1 downto 0);
RXCHARISK : out std_logic_vector ( 1 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 15 downto 0);
RXDISPERR : out std_logic_vector ( 1 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 1 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 1 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 1 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 1 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 1 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 1 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 1 downto 0 );
TXCHARISK : in std_logic_vector ( 1 downto 0 );
TXDATA : in std_logic_vector ( 15 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_XAUI_2 : component is true;
component GT_XAUI_4
port (
CHBONDDONE : out std_ulogic ;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 3 downto 0);
RXCHARISK : out std_logic_vector ( 3 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 31 downto 0);
RXDISPERR : out std_logic_vector ( 3 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 3 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 3 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 3 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 3 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXFORCECRCERR : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 3 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 3 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 3 downto 0 );
TXCHARISK : in std_logic_vector ( 3 downto 0 );
TXDATA : in std_logic_vector ( 31 downto 0 );
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_XAUI_4 : component is true;
component JTAGPPC
port (
TCK : out std_logic;
TDIPPC : out std_logic;
TMS : out std_logic;
TDOPPC : in std_logic;
TDOTSPPC : in std_logic
);
end component;
attribute syn_black_box of JTAGPPC : component is true;
component PPC405
port (
C405CPMCORESLEEPREQ : out std_ulogic;
C405CPMMSRCE : out std_ulogic;
C405CPMMSREE : out std_ulogic;
C405CPMTIMERIRQ : out std_ulogic;
C405CPMTIMERRESETREQ : out std_ulogic;
C405DBGMSRWE : out std_ulogic;
C405DBGSTOPACK : out std_ulogic;
C405DBGWBCOMPLETE : out std_ulogic;
C405DBGWBFULL : out std_ulogic;
C405DBGWBIAR : out std_logic_vector(0 TO 29);
C405DCRABUS : out std_logic_vector(0 TO 9);
C405DCRDBUSOUT : out std_logic_vector(0 TO 31);
C405DCRREAD : out std_ulogic;
C405DCRWRITE : out std_ulogic;
C405JTGCAPTUREDR : out std_ulogic;
C405JTGEXTEST : out std_ulogic;
C405JTGPGMOUT : out std_ulogic;
C405JTGSHIFTDR : out std_ulogic;
C405JTGTDO : out std_ulogic;
C405JTGTDOEN : out std_ulogic;
C405JTGUPDATEDR : out std_ulogic;
C405PLBDCUABORT : out std_ulogic;
C405PLBDCUABUS : out std_logic_vector(0 TO 31);
C405PLBDCUBE : out std_logic_vector(0 TO 7);
C405PLBDCUCACHEABLE : out std_ulogic;
C405PLBDCUGUARDED : out std_ulogic;
C405PLBDCUPRIORITY : out std_logic_vector(0 TO 1);
C405PLBDCUREQUEST : out std_ulogic;
C405PLBDCURNW : out std_ulogic;
C405PLBDCUSIZE2 : out std_ulogic;
C405PLBDCUU0ATTR : out std_ulogic;
C405PLBDCUWRDBUS : out std_logic_vector(0 TO 63);
C405PLBDCUWRITETHRU : out std_ulogic;
C405PLBICUABORT : out std_ulogic;
C405PLBICUABUS : out std_logic_vector(0 TO 29);
C405PLBICUCACHEABLE : out std_ulogic;
C405PLBICUPRIORITY : out std_logic_vector(0 TO 1);
C405PLBICUREQUEST : out std_ulogic;
C405PLBICUSIZE : out std_logic_vector(2 TO 3);
C405PLBICUU0ATTR : out std_ulogic;
C405RSTCHIPRESETREQ : out std_ulogic;
C405RSTCORERESETREQ : out std_ulogic;
C405RSTSYSRESETREQ : out std_ulogic;
C405TRCCYCLE : out std_ulogic;
C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 TO 1);
C405TRCODDEXECUTIONSTATUS : out std_logic_vector(0 TO 1);
C405TRCTRACESTATUS : out std_logic_vector(0 TO 3);
C405TRCTRIGGEREVENTOUT : out std_ulogic;
C405TRCTRIGGEREVENTTYPE : out std_logic_vector(0 TO 10);
C405XXXMACHINECHECK : out std_ulogic;
DSOCMBRAMABUS : out std_logic_vector(8 TO 29);
DSOCMBRAMBYTEWRITE : out std_logic_vector(0 TO 3);
DSOCMBRAMEN : out std_ulogic;
DSOCMBRAMWRDBUS : out std_logic_vector(0 TO 31);
DSOCMBUSY : out std_ulogic;
ISOCMBRAMEN : out std_ulogic;
ISOCMBRAMEVENWRITEEN : out std_ulogic;
ISOCMBRAMODDWRITEEN : out std_ulogic;
ISOCMBRAMRDABUS : out std_logic_vector(8 TO 28);
ISOCMBRAMWRABUS : out std_logic_vector(8 TO 28);
ISOCMBRAMWRDBUS : out std_logic_vector(0 TO 31);
BRAMDSOCMCLK : in std_ulogic;
BRAMDSOCMRDDBUS : in std_logic_vector(0 TO 31);
BRAMISOCMCLK : in std_ulogic;
BRAMISOCMRDDBUS : in std_logic_vector(0 TO 63);
CPMC405CLOCK : in std_ulogic;
CPMC405CORECLKINACTIVE : in std_ulogic;
CPMC405CPUCLKEN : in std_ulogic;
CPMC405JTAGCLKEN : in std_ulogic;
CPMC405TIMERCLKEN : in std_ulogic;
CPMC405TIMERTICK : in std_ulogic;
DBGC405DEBUGHALT : in std_ulogic;
DBGC405EXTBUSHOLDACK : in std_ulogic;
DBGC405UNCONDDEBUGEVENT : in std_ulogic;
DCRC405ACK : in std_ulogic;
DCRC405DBUSIN : in std_logic_vector(0 TO 31);
DSARCVALUE : in std_logic_vector(0 TO 7);
DSCNTLVALUE : in std_logic_vector(0 TO 7);
EICC405CRITINPUTIRQ : in std_ulogic;
EICC405EXTINPUTIRQ : in std_ulogic;
ISARCVALUE : in std_logic_vector(0 TO 7);
ISCNTLVALUE : in std_logic_vector(0 TO 7);
JTGC405BNDSCANTDO : in std_ulogic;
JTGC405TCK : in std_ulogic;
JTGC405TDI : in std_ulogic;
JTGC405TMS : in std_ulogic;
JTGC405TRSTNEG : in std_ulogic;
MCBCPUCLKEN : in std_ulogic;
MCBJTAGEN : in std_ulogic;
MCBTIMEREN : in std_ulogic;
MCPPCRST : in std_ulogic;
PLBC405DCUADDRACK : in std_ulogic;
PLBC405DCUBUSY : in std_ulogic;
PLBC405DCUERR : in std_ulogic;
PLBC405DCURDDACK : in std_ulogic;
PLBC405DCURDDBUS : in std_logic_vector(0 TO 63);
PLBC405DCURDWDADDR : in std_logic_vector(1 TO 3);
PLBC405DCUSSIZE1 : in std_ulogic;
PLBC405DCUWRDACK : in std_ulogic;
PLBC405ICUADDRACK : in std_ulogic;
PLBC405ICUBUSY : in std_ulogic;
PLBC405ICUERR : in std_ulogic;
PLBC405ICURDDACK : in std_ulogic;
PLBC405ICURDDBUS : in std_logic_vector(0 TO 63);
PLBC405ICURDWDADDR : in std_logic_vector(1 TO 3);
PLBC405ICUSSIZE1 : in std_ulogic;
PLBCLK : in std_ulogic;
RSTC405RESETCHIP : in std_ulogic;
RSTC405RESETCORE : in std_ulogic;
RSTC405RESETSYS : in std_ulogic;
TIEC405DETERMINISTICMULT : in std_ulogic;
TIEC405DISOPERANDFWD : in std_ulogic;
TIEC405MMUEN : in std_ulogic;
TIEDSOCMDCRADDR : in std_logic_vector(0 TO 7);
TIEISOCMDCRADDR : in std_logic_vector(0 TO 7);
TRCC405TRACEDISABLE : in std_ulogic;
TRCC405TRIGGEREVENTIN : in std_ulogic
);
end component ;
attribute syn_black_box of PPC405 : component is true;
component BUFGCE
port(
O : out STD_ULOGIC;
CE: in STD_ULOGIC;
I : in STD_ULOGIC);
end component;
attribute syn_black_box of BUFGCE : component is true;
component BUFGCE_1
port(
O : out STD_ULOGIC;
CE: in STD_ULOGIC;
I : in STD_ULOGIC);
end component;
attribute syn_black_box of BUFGCE_1 : component is true;
component IFDDRCPE
port(
Q0 : out STD_ULOGIC;
Q1 : out STD_ULOGIC;
D : in STD_ULOGIC;
C0 : in STD_ULOGIC;
C1 : in STD_ULOGIC;
CE : in STD_ULOGIC;
PRE : in STD_ULOGIC;
CLR : in STD_ULOGIC);
end component;
attribute syn_black_box of IFDDRCPE : component is true;
component IFDDRRSE
port(
Q0 : out STD_ULOGIC;
Q1 : out STD_ULOGIC;
C0 : in STD_ULOGIC;
C1 : in STD_ULOGIC;
CE : in STD_ULOGIC;
D : in STD_ULOGIC;
R : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
attribute syn_black_box of IFDDRRSE : component is true;
component OFDDRCPE
port(
Q : out STD_ULOGIC;
D0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
C0 : in STD_ULOGIC;
C1 : in STD_ULOGIC;
CE : in STD_ULOGIC;
PRE : in STD_ULOGIC;
CLR : in STD_ULOGIC);
end component;
attribute syn_black_box of OFDDRCPE : component is true;
component OFDDRRSE
port(
Q : out STD_ULOGIC;
C0 : in STD_ULOGIC;
C1 : in STD_ULOGIC;
CE : in STD_ULOGIC;
D0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
R : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
attribute syn_black_box of OFDDRRSE : component is true;
component OFDDRTCPE
port(
O : out STD_ULOGIC;
C0 : in STD_ULOGIC;
C1 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLR : in STD_ULOGIC;
D0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
PRE : in STD_ULOGIC;
T : in STD_ULOGIC);
end component;
attribute syn_black_box of OFDDRTCPE : component is true;
component OFDDRTRSE
port(
O : out STD_ULOGIC;
C0 : in STD_ULOGIC;
C1 : in STD_ULOGIC;
CE : in STD_ULOGIC;
D0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
R : in STD_ULOGIC;
S : in STD_ULOGIC;
T : in STD_ULOGIC);
end component;
attribute syn_black_box of OFDDRTRSE : component is true;
component STARTBUF_VIRTEX2
port( GSRIN : in std_ulogic := 'X';
GTSIN : in std_ulogic := 'X';
CLKIN : in std_ulogic := 'X';
GTSOUT : out std_ulogic
);
end component;
attribute syn_black_box of STARTBUF_VIRTEX2 : component is true;
end package components;
library IEEE;
use IEEE.std_logic_1164.all;
library virtex2;
use virtex2.components.all;
entity STARTUP_VIRTEX2 is
port(CLK, GSR, GTS: in std_logic := '0');
end STARTUP_VIRTEX2;
architecture struct of STARTUP_VIRTEX2 is
attribute syn_noprune of struct : architecture is true;
begin
gsr0 : STARTUP_VIRTEX2_GSR port map ( GSR => GSR );
gts0 : STARTUP_VIRTEX2_GTS port map ( GTS => GTS );
clk0 : STARTUP_VIRTEX2_CLK port map ( CLK => CLK);
end struct;
|
architecture rtl of fifo is
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is record a : std_logic; b : std_logic; end record;
begin
end architecture rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
Port ( Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0);
carry : in std_logic;
Salida : out STD_LOGIC_VECTOR (31 downto 0)
);
end ALU;
architecture Behavioral of ALU is
begin
process(ALUOP,Oper1,Oper2)
begin
case ALUOP is
when "000000" => --ADD
Salida <= Oper1 + Oper2;
when "000001" => --SUB
Salida <= Oper1 - Oper2;
when "000010" => --AND
Salida <= Oper1 and Oper2;
when "000011" => --ANDN
Salida <= Oper1 and not Oper2;
when "000100" => --OR
Salida <= Oper1 or Oper2;
when "000101" => --ORN
Salida <= Oper1 or not Oper2;
when "000110" => --XOR
Salida <= Oper1 xor Oper2;
when "000111" => --XNOR
Salida <= Oper1 xnor Oper2;
when "001000" => --SUBcc
Salida <= Oper1 - Oper2;
when "001001" => -- SUBx
Salida <= Oper1 - Oper2 - Carry;
when "001010" => --SUBxcc
Salida <= Oper1 - Oper2 - Carry;
when "001011" => --ANDcc
Salida <= Oper1 and Oper2;
when "001100" => --ANDNcc
Salida <= Oper1 and not Oper2;
when "001101" => --ORcc
Salida <= Oper1 or Oper2;
when "001110" => --ORNcc
Salida <= Oper1 or not Oper2;
when "001111" => --XORcc
Salida <= Oper1 xor Oper2;
when "010000" => --XNORcc
Salida <= Oper1 xnor Oper2;
when "010001" => --ADDx
Salida <= Oper1 + Oper2 + Carry;
when "010010" => --ADDxcc
Salida <= Oper1 + Oper2 + Carry;
when "010011" => --ADDcc
Salida <= Oper1 + Oper2;
when "100101" => --sll
Salida <= std_logic_vector(unsigned(Oper1) sll to_integer(unsigned(Oper2)));
when "100110" => --srl
Salida <= std_logic_vector(unsigned(Oper1) srl to_integer(unsigned(Oper2)));
--SAVE 57
when "111001" =>
Salida <= Oper1 + Oper2;
--RESTORE 58
when "111101" =>
Salida <= Oper1 + Oper2;
when others =>
Salida <= (others=>'1'); --error
end case;
end process;
end Behavioral;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library hwti_common_v1_00_a;
use hwti_common_v1_00_a.common.all;
entity hwtireg is
generic
(
REG_WIDTH : integer := 32;
USE_HIGH : boolean := false;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 64
);
port
(
clk : in std_logic;
rst : in std_logic;
rd : in std_logic;
wr : in std_logic;
data : in std_logic_vector(0 to C_DWIDTH-1);
rdack : out std_logic;
wrack : out std_logic;
value : out std_logic_vector(0 to REG_WIDTH-1);
output : out std_logic_vector(0 to C_DWIDTH-1)
);
end entity;
architecture behavioral of hwtireg is
signal reg : std_logic_vector(0 to REG_WIDTH-1);
begin
value <= reg;
wrack <= wr;
rdack <= rd;
output(C_DWIDTH-REG_WIDTH to C_DWIDTH-1) <= reg when rd = '1' else (others => '0');
zero : if( REG_WIDTH < C_DWIDTH ) generate
begin
output(0 to C_DWIDTH-REG_WIDTH-1) <= (others => '0');
end generate;
regproc : process(clk,rst,rd,wr,data,reg) is
begin
if( rising_edge(clk) ) then
if( rst = '1' ) then
reg <= (others => '0');
elsif( wr = '1' ) then
reg <= data(C_DWIDTH-REG_WIDTH to C_DWIDTH-1);
end if;
end if;
end process regproc;
end architecture;
|
-- matrix_pixel_gen.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity matrix_pixel_gen is
port (
CLK : in std_logic;
RST : in std_logic;
R : out std_logic_vector(71 downto 0);
G : out std_logic_vector(71 downto 0);
B : out std_logic_vector(71 downto 0);
PX_REQ : in std_logic
);
end entity;
architecture plain_numbers of matrix_pixel_gen is
begin
read_file : process(CLK, RST, PX_REQ)
file infile : text;
variable l : line;
variable vr0 : integer;
variable vg0 : integer;
variable vb0 : integer;
variable vr1 : integer;
variable vg1 : integer;
variable vb1 : integer;
variable vr2 : integer;
variable vg2 : integer;
variable vb2 : integer;
variable vr3 : integer;
variable vg3 : integer;
variable vb3 : integer;
variable vr4 : integer;
variable vg4 : integer;
variable vb4 : integer;
variable vr5 : integer;
variable vg5 : integer;
variable vb5 : integer;
variable vr6 : integer;
variable vg6 : integer;
variable vb6 : integer;
variable vr7 : integer;
variable vg7 : integer;
variable vb7 : integer;
variable vr8 : integer;
variable vg8 : integer;
variable vb8 : integer;
procedure read_matrix is
begin
readline(infile, l);
read(l, vr0); read(l, vg0); read(l, vb0);
read(l, vr1); read(l, vg1); read(l, vb1);
read(l, vr2); read(l, vg2); read(l, vb2);
read(l, vr3); read(l, vg3); read(l, vb3);
read(l, vr4); read(l, vg4); read(l, vb4);
read(l, vr5); read(l, vg5); read(l, vb5);
read(l, vr6); read(l, vg6); read(l, vb6);
read(l, vr7); read(l, vg7); read(l, vb7);
read(l, vr8); read(l, vg8); read(l, vb8);
R( 7 downto 0) <= conv_std_logic_vector(vr0, 8);
G( 7 downto 0) <= conv_std_logic_vector(vg0, 8);
B( 7 downto 0) <= conv_std_logic_vector(vb0, 8);
R(15 downto 8) <= conv_std_logic_vector(vr1, 8);
G(15 downto 8) <= conv_std_logic_vector(vg1, 8);
B(15 downto 8) <= conv_std_logic_vector(vb1, 8);
R(23 downto 16) <= conv_std_logic_vector(vr2, 8);
G(23 downto 16) <= conv_std_logic_vector(vg2, 8);
B(23 downto 16) <= conv_std_logic_vector(vb2, 8);
R(31 downto 24) <= conv_std_logic_vector(vr3, 8);
G(31 downto 24) <= conv_std_logic_vector(vg3, 8);
B(31 downto 24) <= conv_std_logic_vector(vb3, 8);
R(39 downto 32) <= conv_std_logic_vector(vr4, 8);
G(39 downto 32) <= conv_std_logic_vector(vg4, 8);
B(39 downto 32) <= conv_std_logic_vector(vb4, 8);
R(47 downto 40) <= conv_std_logic_vector(vr5, 8);
G(47 downto 40) <= conv_std_logic_vector(vg5, 8);
B(47 downto 40) <= conv_std_logic_vector(vb5, 8);
R(55 downto 48) <= conv_std_logic_vector(vr6, 8);
G(55 downto 48) <= conv_std_logic_vector(vg6, 8);
B(55 downto 48) <= conv_std_logic_vector(vb6, 8);
R(63 downto 56) <= conv_std_logic_vector(vr7, 8);
G(63 downto 56) <= conv_std_logic_vector(vg7, 8);
B(63 downto 56) <= conv_std_logic_vector(vb7, 8);
R(71 downto 64) <= conv_std_logic_vector(vr8, 8);
G(71 downto 64) <= conv_std_logic_vector(vg8, 8);
B(71 downto 64) <= conv_std_logic_vector(vb8, 8);
end procedure;
begin
if rising_edge(CLK) then
if RST = '1' or endfile(infile) then
file_close(infile);
file_open(infile, "input_file.txt", READ_MODE);
read_matrix;
elsif PX_REQ = '1' then
read_matrix;
end if;
end if;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- Title : Top DSP design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-02-25
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the DSP
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-02-25 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Custom common cores
use work.dbe_common_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_generic_pkg.all;
-- Ethernet MAC Modules and SDB structure
use work.ethmac_pkg.all;
-- Wishbone Fabric interface
use work.wr_fabric_pkg.all;
-- Etherbone slave core
use work.etherbone_pkg.all;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
-- DSP definitions
use work.dsp_cores_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_dsp is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-----------------------------------------
-- PHY pins
-----------------------------------------
-- Clock and resets to PHY (GMII). Not used in MII mode (10/100)
mgtx_clk_o : out std_logic;
mrstn_o : out std_logic;
-- PHY TX
mtx_clk_pad_i : in std_logic;
mtxd_pad_o : out std_logic_vector(3 downto 0);
mtxen_pad_o : out std_logic;
mtxerr_pad_o : out std_logic;
-- PHY RX
mrx_clk_pad_i : in std_logic;
mrxd_pad_i : in std_logic_vector(3 downto 0);
mrxdv_pad_i : in std_logic;
mrxerr_pad_i : in std_logic;
mcoll_pad_i : in std_logic;
mcrs_pad_i : in std_logic;
-- MII
mdc_pad_o : out std_logic;
md_pad_b : inout std_logic;
-----------------------------
-- FMC516 ports
-----------------------------
-- System I2C Bus. Slaves: Atmel AT24C512B Serial EEPROM,
-- AD7417 temperature diodes and AD7417 supply rails
sys_i2c_scl_b : inout std_logic;
sys_i2c_sda_b : inout std_logic;
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
adc_clk0_p_i : in std_logic;
adc_clk0_n_i : in std_logic;
adc_clk1_p_i : in std_logic;
adc_clk1_n_i : in std_logic;
adc_clk2_p_i : in std_logic;
adc_clk2_n_i : in std_logic;
adc_clk3_p_i : in std_logic;
adc_clk3_n_i : in std_logic;
-- DDR ADC data channels.
adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2-1 downto 0);
-- ADC clock (half of the sampling frequency) divider reset
adc_clk_div_rst_p_o : out std_logic;
adc_clk_div_rst_n_o : out std_logic;
-- FMC Front leds. Typical uses: Over Range or Full Scale
-- condition.
fmc_leds_o : out std_logic_vector(1 downto 0);
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o : out std_logic;
sys_spi_data_b : inout std_logic;
sys_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
-- External Trigger To/From FMC
m2c_trig_p_i : in std_logic;
m2c_trig_n_i : in std_logic;
c2m_trig_p_o : out std_logic;
c2m_trig_n_o : out std_logic;
-- LMK (National Semiconductor) is the clock and distribution IC,
-- programmable via Microwire Interface
lmk_lock_i : in std_logic;
lmk_sync_o : out std_logic;
lmk_uwire_latch_en_o : out std_logic;
lmk_uwire_data_o : out std_logic;
lmk_uwire_clock_o : out std_logic;
-- Programable VCXO via I2C
vcxo_i2c_sda_b : inout std_logic;
vcxo_i2c_scl_o : out std_logic;
vcxo_pd_l_o : out std_logic;
-- One-wire To/From DS2431 (VMETRO Data)
fmc_id_dq_b : inout std_logic;
-- One-wire To/From DS2432 SHA-1 (SP-Devices key)
fmc_key_dq_b : inout std_logic;
-- General board pins
fmc_pwr_good_i : in std_logic;
-- Internal/External clock distribution selection
fmc_clk_sel_o : out std_logic;
-- Reset ADCs
fmc_reset_adcs_n_o : out std_logic;
--FMC Present status
fmc_prsnt_m2c_l_i : in std_logic;
-- General board status
fmc_mmcm_lock_o : out std_logic;
fmc_lmk_lock_o : out std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_dsp;
architecture rtl of dbe_bpm_dsp is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 10;
-- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC,
--Etherbone, FMC516, Peripherals
-- Number of masters
constant c_masters : natural := 8; -- LM32 master, Data + Instruction,
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone
--constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB)
constant c_dpram_size : natural := 90112/4; -- in 32-bit words (90KB)
--constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB)
--constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB)
constant c_dpram_ethbuf_size : natural := 16384/4; -- in 32-bit words (16KB)
-- GPIO num pinscalc
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- TICs counter period. 100MHz clock -> msec granularity
constant c_tics_cntr_period : natural := 100000;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
-- number of the ADC reference clock used for all downstream
-- FPGA logic
constant c_adc_ref_clk : natural := 1;
-- DSP constants
constant c_dsp_ref_num_bits : natural := 24;
constant c_dsp_pos_num_bits : natural := 26;
constant c_xwb_etherbone_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"68202b22",
version => x"00000001",
date => x"20120912",
name => "GSI_ETHERBONE_CFG ")));
constant c_xwb_ethmac_adapter_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"2ff9a28e",
version => x"00000001",
date => x"20130701",
name => "ETHMAC_ADAPTER ")));
-- FMC516 layout. Size (0x00000FFF) is larger than needed. Just to be sure
-- no address overlaps will occur
constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter
constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400");
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 128KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size),
x"20000000"), -- 64KB RAM
3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30004000"), -- DMA control port
4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30005000"), -- Ethernet MAC control port
5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30006000"), -- Ethernet Adapter control port
6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30007000"), -- Etherbone control port
7 => f_sdb_embed_device(c_xwb_position_calc_core_sdb,
x"30008000"), -- Position Calc Core control port
8 => f_sdb_embed_bridge(c_fmc516_bridge_sdb, x"30010000"), -- FMC516 control port
9 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"30020000") -- General peripherals control port
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well
constant c_sdb_address : t_wishbone_address := x"30000000";
-- FMC516 ADC data constants
constant c_adc_data_ch0_lsb : natural := 0;
constant c_adc_data_ch0_msb : natural := c_num_adc_bits-1 + c_adc_data_ch0_lsb;
constant c_adc_data_ch1_lsb : natural := c_adc_data_ch0_msb + 1;
constant c_adc_data_ch1_msb : natural := c_num_adc_bits-1 + c_adc_data_ch1_lsb;
constant c_adc_data_ch2_lsb : natural := c_adc_data_ch1_msb + 1;
constant c_adc_data_ch2_msb : natural := c_num_adc_bits-1 + c_adc_data_ch2_lsb;
constant c_adc_data_ch3_lsb : natural := c_adc_data_ch2_msb + 1;
constant c_adc_data_ch3_msb : natural := c_num_adc_bits-1 + c_adc_data_ch3_lsb;
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_sys_n : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
-- 200 Mhz clocck for iodelay_ctrl
signal clk_200mhz : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
-- Ethernet MAC signals
signal ethmac_int : std_logic;
signal ethmac_md_in : std_logic;
signal ethmac_md_out : std_logic;
signal ethmac_md_oe : std_logic;
signal mtxd_pad_int : std_logic_vector(3 downto 0);
signal mtxen_pad_int : std_logic;
signal mtxerr_pad_int : std_logic;
signal mdc_pad_int : std_logic;
-- Ethrnet MAC adapter signals
signal irq_rx_done : std_logic;
signal irq_tx_done : std_logic;
-- Etherbone signals
signal wb_ebone_out : t_wishbone_master_out;
signal wb_ebone_in : t_wishbone_master_in;
signal eb_src_i : t_wrf_source_in;
signal eb_src_o : t_wrf_source_out;
signal eb_snk_i : t_wrf_sink_in;
signal eb_snk_o : t_wrf_sink_out;
-- DMA signals
signal dma_int : std_logic;
-- FMC516 Signals
signal wbs_fmc516_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
signal wbs_fmc516_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
signal fmc516_mmcm_lock_int : std_logic;
signal fmc516_lmk_lock_int : std_logic;
signal fmc516_fs_clk : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_fs_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_adc_data : std_logic_vector(c_num_adc_channels*16-1 downto 0);
signal fmc516_adc_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
--signal fmc_debug : std_logic;
--signal reset_adc_counter : unsigned(6 downto 0) := (others => '0');
signal fs_rst_sync_n : std_logic;
signal fs_rst_n : std_logic;
-- FMC516 Debug
signal fmc516_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
signal sys_spi_clk_int : std_logic;
--signal sys_spi_data_int : std_logic;
signal sys_spi_dout_int : std_logic;
signal sys_spi_din_int : std_logic;
signal sys_spi_miosio_oe_n_int : std_logic;
signal sys_spi_cs_adc0_n_int : std_logic;
signal sys_spi_cs_adc1_n_int : std_logic;
signal sys_spi_cs_adc2_n_int : std_logic;
signal sys_spi_cs_adc3_n_int : std_logic;
signal lmk_lock_int : std_logic;
signal lmk_sync_int : std_logic;
signal lmk_uwire_latch_en_int : std_logic;
signal lmk_uwire_data_int : std_logic;
signal lmk_uwire_clock_int : std_logic;
signal fmc_reset_adcs_n_int : std_logic;
signal fmc_reset_adcs_n_out : std_logic;
-- DSP signals
signal dsp_sysce : std_logic;
signal dsp_sysce_clr : std_logic;
signal dsp_sysclk : std_logic;
signal dsp_sysclk2x : std_logic;
signal dsp_rst_n : std_logic;
signal dsp_kx : std_logic_vector(24 downto 0);
signal dsp_ky : std_logic_vector(24 downto 0);
signal dsp_ksum : std_logic_vector(24 downto 0);
signal dsp_del_sig_div_thres : std_logic_vector(25 downto 0);
signal dsp_adc_ch0_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch1_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch2_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch3_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch0_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch1_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch2_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch3_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_bpf_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_bpf_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_mix_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_mix_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_poly35_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_poly35_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_cic_fofb_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_cic_fofb_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_x_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_y_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_q_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_sum_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_x_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_y_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_q_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_sum_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_x_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_y_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_q_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_sum_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_tbt_decim_q_ch01_incorrect : std_logic;
signal dsp_tbt_decim_q_ch23_incorrect : std_logic;
signal dsp_fofb_decim_q_01_missing : std_logic;
signal dsp_fofb_decim_q_23_missing : std_logic;
signal dsp_monit_cic_unexpected : std_logic;
signal dsp_monit_cfir_incorrect : std_logic;
signal dsp_monit_pfir_incorrect : std_logic;
signal dsp_clk_ce_1 : std_logic;
signal dsp_clk_ce_2 : std_logic;
signal dsp_clk_ce_35 : std_logic;
signal dsp_clk_ce_70 : std_logic;
signal dsp_clk_ce_1390000 : std_logic;
signal dsp_clk_ce_1112 : std_logic;
signal dsp_clk_ce_2224 : std_logic;
signal dsp_clk_ce_11120000 : std_logic;
signal dsp_clk_ce_22240000 : std_logic;
signal dsp_clk_ce_5000 : std_logic;
signal dsp_clk_ce_556 : std_logic;
signal dsp_clk_ce_2780000 : std_logic;
signal dsp_clk_ce_5560000 : std_logic;
signal clk_rffe_swap : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
-- Counter signal
--signal s_counter : unsigned(c_counter_width-1 downto 0);
-- 100MHz period or 1 second
--constant s_counter_full : integer := 100000000;
-- Chipscope control signals
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
signal CONTROL2 : std_logic_vector(35 downto 0);
signal CONTROL3 : std_logic_vector(35 downto 0);
signal CONTROL4 : std_logic_vector(35 downto 0);
signal CONTROL5 : std_logic_vector(35 downto 0);
signal CONTROL6 : std_logic_vector(35 downto 0);
-- Chipscope ILA 0 signals
signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 1 signals
signal TRIG_ILA1_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_4 : std_logic_vector(31 downto 0);
-- Chipscope ILA 2 signals
signal TRIG_ILA2_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA2_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_4 : std_logic_vector(31 downto 0);
-- Chipscope ILA 3 signals
signal TRIG_ILA3_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA3_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_4 : std_logic_vector(31 downto 0);
-- Chipscope ILA 4 signals
signal TRIG_ILA4_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA4_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA4_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA4_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA4_4 : std_logic_vector(31 downto 0);
-- Chipscope ILA 5 signals
signal TRIG_ILA5_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA5_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA5_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA5_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA5_4 : std_logic_vector(31 downto 0);
-- Chipscope ILA 6 signals
signal TRIG_ILA6_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA6_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA6_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA6_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA6_4 : std_logic_vector(31 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Controller 2 port
--component chipscope_icon_2_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0)
--);
--end component;
--component chipscope_icon_4_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0);
-- CONTROL2 : inout std_logic_vector(35 downto 0);
-- CONTROL3 : inout std_logic_vector(35 downto 0)
--);
--end component;
--component chipscope_icon_8_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0);
-- CONTROL2 : inout std_logic_vector(35 downto 0);
-- CONTROL3 : inout std_logic_vector(35 downto 0);
-- CONTROL4 : inout std_logic_vector(35 downto 0);
-- CONTROL5 : inout std_logic_vector(35 downto 0);
-- CONTROL6 : inout std_logic_vector(35 downto 0);
-- CONTROL7 : inout std_logic_vector(35 downto 0)
--);
--end component;
component chipscope_icon_7_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0);
CONTROL2 : inout std_logic_vector(35 downto 0);
CONTROL3 : inout std_logic_vector(35 downto 0);
CONTROL4 : inout std_logic_vector(35 downto 0);
CONTROL5 : inout std_logic_vector(35 downto 0);
CONTROL6 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)
);
end component;
component chipscope_ila_8192
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(7 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0);
TRIG4 : in std_logic_vector(31 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
cmp_reset : gc_reset
generic map(
g_clocks => 1 -- CLK_SYS
)
port map(
free_clk_i => sys_clk_gen,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(0) <= clk_sys;
clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n;
clk_sys_rst <= not clk_sys_rstn;
mrstn_o <= clk_sys_rstn;
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
rst_button_sys_n <= not rst_button_sys;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn;
cmp_lm32 : xwb_lm32
generic map(
g_profile => "medium_icache_debug"
) -- Including JTAG and I-cache (no divide)
port map(
clk_sys_i => clk_sys,
rst_n_i => lm32_rstn,
irq_i => lm32_interrupt,
dwb_o => cbar_slave_i(0), -- Data bus
dwb_i => cbar_slave_o(0),
iwb_o => cbar_slave_i(1), -- Instruction bus
iwb_i => cbar_slave_o(1)
);
-- Interrupt '0' is Ethmac.
-- Interrupt '1' is DMA completion.
-- Interrupt '2' is Button(0).
-- Interrupt '3' is Ethernet Adapter RX completion.
-- Interrupt '4' is Ethernet Adapter TX completion.
-- Interrupts 31 downto 5 are disabled
lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done,
4 => irq_tx_done, others => '0');
-- A DMA controller is master 2+3, slave 3, and interrupt 1
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(3),
slave_o => cbar_master_i(3),
r_master_i => cbar_slave_o(2),
r_master_o => cbar_slave_i(2),
w_master_i => cbar_slave_o(3),
w_master_o => cbar_slave_i(3),
interrupt_o => dma_int
);
-- Slave 0+1 is the RAM. Load a input file containing the embedded software
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
g_init_file => "../../../embedded-sw/dbe.ram",
--"../../top/ml_605/dbe_bpm_simple/sw/main.ram",
g_must_have_init_file => true,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
);
-- Slave 2 is the RAM Buffer for Ethernet MAC.
cmp_ethmac_buf_ram : xwb_dpram
generic map(
g_size => c_dpram_ethbuf_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => CLASSIC,
--g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
--g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(2),
slave1_o => cbar_master_i(2),
-- Second port connected to the crossbar
slave2_i => cc_dummy_slave_in, -- CYC always low
slave2_o => open
);
-- The Ethernet MAC is master 4, slave 4
cmp_xwb_ethmac : xwb_ethmac
generic map (
--g_ma_interface_mode => PIPELINED,
g_ma_interface_mode => CLASSIC, -- NOT used for now
--g_ma_address_granularity => WORD,
g_ma_address_granularity => BYTE, -- NOT used for now
g_sl_interface_mode => PIPELINED,
--g_sl_interface_mode => CLASSIC,
--g_sl_address_granularity => WORD
g_sl_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rst_i => clk_sys_rst,
-- WISHBONE slave
wb_slave_in => cbar_master_o(4),
wb_slave_out => cbar_master_i(4),
-- WISHBONE master
wb_master_in => cbar_slave_o(4),
wb_master_out => cbar_slave_i(4),
-- PHY TX
mtx_clk_pad_i => mtx_clk_pad_i,
--mtxd_pad_o => mtxd_pad_o,
mtxd_pad_o => mtxd_pad_int,
--mtxen_pad_o => mtxen_pad_o,
mtxen_pad_o => mtxen_pad_int,
--mtxerr_pad_o => mtxerr_pad_o,
mtxerr_pad_o => mtxerr_pad_int,
-- PHY RX
mrx_clk_pad_i => mrx_clk_pad_i,
mrxd_pad_i => mrxd_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxerr_pad_i => mrxerr_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcrs_pad_i => mcrs_pad_i,
-- MII
--mdc_pad_o => mdc_pad_o,
mdc_pad_o => mdc_pad_int,
md_pad_i => ethmac_md_in,
md_pad_o => ethmac_md_out,
md_padoe_o => ethmac_md_oe,
-- Interrupt
int_o => ethmac_int
);
---- Tri-state buffer for MII config
md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z';
ethmac_md_in <= md_pad_b;
mtxd_pad_o <= mtxd_pad_int;
mtxen_pad_o <= mtxen_pad_int;
mtxerr_pad_o <= mtxerr_pad_int;
mdc_pad_o <= mdc_pad_int;
--The Ethernet MAC Adapter is master 5+6, slave 5
cmp_xwb_ethmac_adapter : xwb_ethmac_adapter
port map(
clk_i => clk_sys,
rstn_i => clk_sys_rstn,
wb_slave_o => cbar_master_i(5),
wb_slave_i => cbar_master_o(5),
tx_ram_o => cbar_slave_i(5),
tx_ram_i => cbar_slave_o(5),
rx_ram_o => cbar_slave_i(6),
rx_ram_i => cbar_slave_o(6),
rx_eb_o => eb_snk_i,
rx_eb_i => eb_snk_o,
tx_eb_o => eb_src_i,
tx_eb_i => eb_src_o,
irq_tx_done_o => irq_tx_done,
irq_rx_done_o => irq_rx_done
);
-- The Etherbone is slave 6
cmp_eb_slave_core : eb_slave_core
generic map(
g_sdb_address => x"00000000" & c_sdb_address
)
port map
(
clk_i => clk_sys,
nRst_i => clk_sys_rstn,
-- EB streaming sink
snk_i => eb_snk_i,
snk_o => eb_snk_o,
-- EB streaming source
src_i => eb_src_i,
src_o => eb_src_o,
-- WB slave - Cfg IF
cfg_slave_o => cbar_master_i(6),
cfg_slave_i => cbar_master_o(6),
-- WB master - Bus IF
master_o => wb_ebone_out,
master_i => wb_ebone_in
);
cbar_slave_i(7) <= wb_ebone_out;
wb_ebone_in <= cbar_slave_o(7);
-- The FMC516 is slave 8
cmp_xwb_fmc516 : xwb_fmc516
generic map(
g_fpga_device => "VIRTEX6",
g_interface_mode => PIPELINED,
--g_address_granularity => WORD,
g_address_granularity => BYTE,
--g_adc_clk_period_values => default_adc_clk_period_values,
g_adc_clk_period_values => (0.0, 0.0, 8.882, 8.882), --476.066*35/148 aprox 112.583 MHz
--g_use_clk_chains => default_clk_use_chain,
-- using clock1 from FMC516 (CLK2_ M2C_P, CLK2_ M2C_M pair)
-- using clock0 from FMC516.
-- BUFIO can drive half-bank only, not the full IO bank
g_use_clk_chains => "0011",
g_use_data_chains => "1111",
g_map_clk_data_chains => (1,0,0,1),
-- Clock 1 is the adc reference clock
g_ref_clk => c_adc_ref_clk,
g_packet_size => 32,
g_sim => 0
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => cbar_master_o(8),
wb_slv_o => cbar_master_i(8),
-----------------------------
-- External ports
-----------------------------
-- System I2C Bus. Slaves: Atmel AT24C512B Serial EEPROM,
-- AD7417 temperature diodes and AD7417 supply rails
sys_i2c_scl_b => sys_i2c_scl_b,
sys_i2c_sda_b => sys_i2c_sda_b,
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
adc_clk0_p_i => adc_clk0_p_i,
adc_clk0_n_i => adc_clk0_n_i,
adc_clk1_p_i => adc_clk1_p_i,
adc_clk1_n_i => adc_clk1_n_i,
adc_clk2_p_i => adc_clk2_p_i,
adc_clk2_n_i => adc_clk2_n_i,
adc_clk3_p_i => adc_clk3_p_i,
adc_clk3_n_i => adc_clk3_n_i,
-- DDR ADC data channels.
adc_data_ch0_p_i => adc_data_ch0_p_i,
adc_data_ch0_n_i => adc_data_ch0_n_i,
adc_data_ch1_p_i => adc_data_ch1_p_i,
adc_data_ch1_n_i => adc_data_ch1_n_i,
adc_data_ch2_p_i => adc_data_ch2_p_i,
adc_data_ch2_n_i => adc_data_ch2_n_i,
adc_data_ch3_p_i => adc_data_ch3_p_i,
adc_data_ch3_n_i => adc_data_ch3_n_i,
-- ADC clock (half of the sampling frequency) divider reset
adc_clk_div_rst_p_o => adc_clk_div_rst_p_o,
adc_clk_div_rst_n_o => adc_clk_div_rst_n_o,
-- FMC Front leds. Typical uses: Over Range or Full Scale
-- condition.
fmc_leds_o => fmc_leds_o,
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o => sys_spi_clk_int,--sys_spi_clk_o,
sys_spi_data_b => sys_spi_data_b,
--sys_spi_dout_o => sys_spi_dout_int,
--sys_spi_din_i => sys_spi_din_int,
sys_spi_cs_adc0_n_o => sys_spi_cs_adc0_n_int, -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o => sys_spi_cs_adc1_n_int, -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o => sys_spi_cs_adc2_n_int, -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o => sys_spi_cs_adc3_n_int, -- SPI ADC CS channel 3
--sys_spi_miosio_oe_n_o => sys_spi_miosio_oe_n_int,
-- External Trigger To/From FMC
m2c_trig_p_i => m2c_trig_p_i,
m2c_trig_n_i => m2c_trig_n_i,
c2m_trig_p_o => c2m_trig_p_o,
c2m_trig_n_o => c2m_trig_n_o,
-- LMK (National Semiconductor) is the clock and distribution IC.
-- uWire interface
lmk_lock_i => lmk_lock_int,--lmk_lock_i,
lmk_sync_o => lmk_sync_int,--lmk_sync_o,
lmk_uwire_latch_en_o => lmk_uwire_latch_en_int,--lmk_uwire_latch_en_o,
lmk_uwire_data_o => lmk_uwire_data_int,--lmk_uwire_data_o,
lmk_uwire_clock_o => lmk_uwire_clock_int,--lmk_uwire_clock_o,
-- Programable VCXO via I2C
vcxo_i2c_sda_b => vcxo_i2c_sda_b,
vcxo_i2c_scl_o => vcxo_i2c_scl_o,
vcxo_pd_l_o => vcxo_pd_l_o,
-- One-wire To/From DS2431 (VMETRO Data)
fmc_id_dq_b => fmc_id_dq_b,
-- One-wire To/From DS2432 SHA-1 (SP-Devices key)
fmc_key_dq_b => fmc_key_dq_b,
-- General board pins
fmc_pwr_good_i => fmc_pwr_good_i,
-- Internal/External clock distribution selection
fmc_clk_sel_o => fmc_clk_sel_o,
-- Reset ADCs
fmc_reset_adcs_n_o => fmc_reset_adcs_n_o,--fmc_reset_adcs_n_int,
--FMC Present status
fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_l_i,
-----------------------------
-- ADC output signals. Continuous flow.
-----------------------------
adc_clk_o => fmc516_fs_clk,
adc_clk2x_o => fmc516_fs_clk2x,
adc_rst_n_o => open,
adc_data_o => fmc516_adc_data,
adc_data_valid_o => fmc516_adc_valid,
-----------------------------
-- General ADC output signals
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => open,
trig_hw_i => clk_rffe_swap, -- from Position Calculation Core
-- General board status
fmc_mmcm_lock_o => fmc516_mmcm_lock_int,
fmc_lmk_lock_o => fmc516_lmk_lock_int,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i => wbs_fmc516_in_array,
wbs_source_o => wbs_fmc516_out_array,
adc_dly_debug_o => adc_dly_debug_int,
fifo_debug_valid_o => fmc516_debug_valid_int,
fifo_debug_full_o => fmc516_debug_full_int,
fifo_debug_empty_o => fmc516_debug_empty_int
);
gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate
wbs_fmc516_in_array(i) <= cc_dummy_src_com_in;
end generate;
fmc_mmcm_lock_o <= fmc516_mmcm_lock_int;
fmc_lmk_lock_o <= fmc516_lmk_lock_int;
sys_spi_clk_o <= sys_spi_clk_int;
sys_spi_cs_adc0_n_o <= sys_spi_cs_adc0_n_int;
sys_spi_cs_adc1_n_o <= sys_spi_cs_adc1_n_int;
sys_spi_cs_adc2_n_o <= sys_spi_cs_adc2_n_int;
sys_spi_cs_adc3_n_o <= sys_spi_cs_adc3_n_int;
lmk_lock_int <= lmk_lock_i;
lmk_sync_o <= lmk_sync_int;
lmk_uwire_latch_en_o <= lmk_uwire_latch_en_int;
lmk_uwire_data_o <= lmk_uwire_data_int;
lmk_uwire_clock_o <= lmk_uwire_clock_int;
-- Position calc core is slave 7
cmp_xwb_position_calc_core : xwb_position_calc_core
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => WORD
)
port map (
rst_n_i => clk_sys_rstn,
clk_i => clk_sys, -- wishbone clock
fs_clk_i => dsp_sysclk2x, -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i => cbar_master_o(7),
wb_slv_o => cbar_master_i(7),
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i => fmc516_adc_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb),
adc_ch1_i => fmc516_adc_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb),
adc_ch2_i => fmc516_adc_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb),
adc_ch3_i => fmc516_adc_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb),
-----------------------------
-- DSP config parameter signals
-----------------------------
kx => dsp_kx,
ky => dsp_ky,
ksum => dsp_ksum,
del_sig_div_fofb_thres_i => dsp_del_sig_div_thres,
del_sig_div_tbt_thres_i => dsp_del_sig_div_thres,
del_sig_div_monit_thres_i => dsp_del_sig_div_thres,
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_dbg_data_o => dsp_adc_ch0_data,
adc_ch1_dbg_data_o => dsp_adc_ch1_data,
adc_ch2_dbg_data_o => dsp_adc_ch2_data,
adc_ch3_dbg_data_o => dsp_adc_ch3_data,
bpf_ch0_o => dsp_bpf_ch0,
--bpf_ch1_o => out std_logic_vector(23 downto 0);
bpf_ch2_o => dsp_bpf_ch2,
--bpf_ch3_o => out std_logic_vector(23 downto 0);
mix_ch0_i_o => dsp_mix_ch0,
--mix_ch0_q_o => out std_logic_vector(23 downto 0);
--mix_ch1_i_o => out std_logic_vector(23 downto 0);
--mix_ch1_q_o => out std_logic_vector(23 downto 0);
mix_ch2_i_o => dsp_mix_ch2,
--mix_ch2_q_o => out std_logic_vector(23 downto 0);
--mix_ch3_i_o => out std_logic_vector(23 downto 0);
--mix_ch3_q_o => out std_logic_vector(23 downto 0);
tbt_decim_ch0_i_o => dsp_poly35_ch0,
--tbt_decim_ch0_i_o => open,
--poly35_ch0_q_o => out std_logic_vector(23 downto 0);
--poly35_ch1_i_o => out std_logic_vector(23 downto 0);
--poly35_ch1_q_o => out std_logic_vector(23 downto 0);
tbt_decim_ch2_i_o => dsp_poly35_ch2,
--tbt_decim_ch2_i_o => open,
--poly35_ch2_q_o => out std_logic_vector(23 downto 0);
--poly35_ch3_i_o => out std_logic_vector(23 downto 0);
--poly35_ch3_q_o => out std_logic_vector(23 downto 0);
tbt_decim_q_ch01_incorrect_o => dsp_tbt_decim_q_ch01_incorrect,
tbt_decim_q_ch23_incorrect_o => dsp_tbt_decim_q_ch23_incorrect,
tbt_amp_ch0_o => dsp_tbt_amp_ch0,
tbt_amp_ch1_o => dsp_tbt_amp_ch1,
tbt_amp_ch2_o => dsp_tbt_amp_ch2,
tbt_amp_ch3_o => dsp_tbt_amp_ch3,
fofb_decim_ch0_i_o => dsp_cic_fofb_ch0, --out std_logic_vector(23 downto 0);
--cic_fofb_ch0_q_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch1_i_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch1_q_o => out std_logic_vector(24 downto 0);
fofb_decim_ch2_i_o => dsp_cic_fofb_ch2, --out std_logic_vector(23 downto 0);
--cic_fofb_ch2_q_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch3_i_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch3_q_o => out std_logic_vector(24 downto 0);
fofb_decim_q_01_missing_o => dsp_fofb_decim_q_01_missing,
fofb_decim_q_23_missing_o => dsp_fofb_decim_q_23_missing,
fofb_amp_ch0_o => dsp_fofb_amp_ch0,
fofb_amp_ch1_o => dsp_fofb_amp_ch1,
fofb_amp_ch2_o => dsp_fofb_amp_ch2,
fofb_amp_ch3_o => dsp_fofb_amp_ch3,
monit_amp_ch0_o => dsp_monit_amp_ch0,
monit_amp_ch1_o => dsp_monit_amp_ch1,
monit_amp_ch2_o => dsp_monit_amp_ch2,
monit_amp_ch3_o => dsp_monit_amp_ch3,
x_tbt_o => dsp_x_tbt,
y_tbt_o => dsp_y_tbt,
q_tbt_o => dsp_q_tbt,
sum_tbt_o => dsp_sum_tbt,
x_fofb_o => dsp_x_fofb,
y_fofb_o => dsp_y_fofb,
q_fofb_o => dsp_q_fofb,
sum_fofb_o => dsp_sum_fofb,
x_monit_o => dsp_x_monit,
y_monit_o => dsp_y_monit,
q_monit_o => dsp_q_monit,
sum_monit_o => dsp_sum_monit,
monit_cic_unexpected_o => dsp_monit_cic_unexpected,
monit_cfir_incorrect_o => dsp_monit_cfir_incorrect,
monit_pfir_incorrect_o => dsp_monit_pfir_incorrect,
-----------------------------
-- Output to RFFE board
-----------------------------
clk_swap_o => clk_rffe_swap,
ctrl1_o => open,
ctrl2_o => open,
-----------------------------
-- Clock drivers for various rates
-----------------------------
clk_ce_1_o => dsp_clk_ce_1,
clk_ce_1112_o => dsp_clk_ce_1112,
clk_ce_11120000_o => dsp_clk_ce_11120000,
clk_ce_1390000_o => dsp_clk_ce_1390000,
clk_ce_2_o => dsp_clk_ce_2,
clk_ce_2224_o => dsp_clk_ce_2224,
clk_ce_22240000_o => dsp_clk_ce_22240000,
clk_ce_2780000_o => dsp_clk_ce_2780000,
clk_ce_35_o => dsp_clk_ce_35,
clk_ce_5000_o => dsp_clk_ce_5000,
clk_ce_556_o => dsp_clk_ce_556,
clk_ce_5560000_o => dsp_clk_ce_5560000,
clk_ce_70_o => dsp_clk_ce_70
);
--dsp_poly35_ch0 <= (others => '0');
--dsp_poly35_ch2 <= (others => '0');
--
--dsp_monit_amp_ch0 <= (others => '0');
--dsp_monit_amp_ch1 <= (others => '0');
--dsp_monit_amp_ch2 <= (others => '0');
--dsp_monit_amp_ch3 <= (others => '0');
-- Signals for the DSP chain
dsp_sysce <= '1';
dsp_sysce_clr <= '0';
--dsp_sysclk <= fmc516_fs_clk(c_adc_ref_clk);
dsp_sysclk2x <= fmc516_fs_clk2x(c_adc_ref_clk); -- oversampled DSP chain
dsp_sysclk <= fmc516_fs_clk(c_adc_ref_clk); -- oversampled DSP chain
--dsp_rst_n <= fmc516_fs_rst_n(c_adc_ref_clk);
dsp_del_sig_div_thres <= "00000000000000001000000000"; -- aprox 1.22e-4 FIX26_22
--dsp_kx <= "100110001001011010000000"; -- 10000000 UFIX24_0
dsp_kx <= "0100000000000000000000000"; -- ??? UFIX25_0
--dsp_kx <= "00100110001001011010000000"; -- 10000000 UFIX26_0
--dsp_ky <= "100110001001011010000000"; -- 10000000 UFIX24_0
dsp_ky <= "0100000000000000000000000"; -- ??? UFIX25_0
--dsp_ky <= "00100110001001011010000000"; -- 10000000 UFIX26_0
dsp_ksum <= "0111111111111111111111111"; -- 1.0 FIX25_24
--dsp_ksum <= "10000000000000000000000000"; -- 1.0 FIX26_25
--dsp_ksum <= "100000000000000000000000"; -- 1.0 FIX24_23
--dsp_ksum <= "10000000000000000000000000"; -- 1.0 FIX26_25
-- The board peripherals components is slave 9
cmp_xwb_dbe_periph : xwb_dbe_periph
generic map(
-- NOT used!
--g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- NOT used!
--g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period => c_tics_cntr_period,
g_num_leds => c_leds_num_pins,
g_num_buttons => c_buttons_num_pins
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- UART
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- LEDs
led_out_o => gpio_leds_int,
led_in_i => gpio_leds_int,
led_oen_o => open,
-- Buttons
button_out_o => open,
button_in_i => buttons_i,
button_oen_o => open,
-- Wishbone
slave_i => cbar_master_o(9),
slave_o => cbar_master_i(9)
);
leds_o <= gpio_leds_int;
---- Xilinx Chipscope
--cmp_chipscope_icon_0 : chipscope_icon_4_port
--port map (
-- CONTROL0 => CONTROL0,
-- CONTROL1 => CONTROL1,
-- CONTROL2 => CONTROL2,
-- CONTROL3 => CONTROL3
--);
cmp_chipscope_icon_7_port : chipscope_icon_7_port
port map (
CONTROL0 => CONTROL0,
CONTROL1 => CONTROL1,
CONTROL2 => CONTROL2,
CONTROL3 => CONTROL3,
CONTROL4 => CONTROL4,
CONTROL5 => CONTROL5,
CONTROL6 => CONTROL6
);
cmp_chipscope_ila_0_fmc516_adc : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => fmc516_fs_clk(c_adc_ref_clk),
TRIG0 => TRIG_ILA0_0,
TRIG1 => TRIG_ILA0_1,
TRIG2 => TRIG_ILA0_2,
TRIG3 => TRIG_ILA0_3
);
-- FMC516 WBS master output data
--TRIG_ILA0_0 <= fmc516_adc_data(31 downto 16) &
-- fmc516_adc_data(47 downto 32);
TRIG_ILA0_0 <= dsp_adc_ch1_data &
dsp_adc_ch0_data;
TRIG_ILA0_1 <= dsp_adc_ch3_data &
dsp_adc_ch2_data;
TRIG_ILA0_2 <= (others => '0');
TRIG_ILA0_3 <= (others => '0');
-- FMC516 WBS master output data
--TRIG_ILA0_1(11 downto 0) <= adc_dly_reg_debug_int(1).clk_load &
-- adc_dly_reg_debug_int(1).data_load &
-- adc_dly_reg_debug_int(1).clk_dly_reg &
-- adc_dly_reg_debug_int(1).data_dly_reg;
--TRIG_ILA0_1(31 downto 12) <= (others => '0');
---- FMC516 WBS master output control signals
--TRIG_ILA0_2(17 downto 0) <= wbs_fmc516_out_array(1).cyc &
-- wbs_fmc516_out_array(1).stb &
-- wbs_fmc516_out_array(1).adr &
-- wbs_fmc516_out_array(1).sel &
-- wbs_fmc516_out_array(1).we &
-- wbs_fmc516_out_array(2).cyc &
-- wbs_fmc516_out_array(2).stb &
-- wbs_fmc516_out_array(2).adr &
-- wbs_fmc516_out_array(2).sel &
-- wbs_fmc516_out_array(2).we;
--TRIG_ILA0_2(18) <= fmc_reset_adcs_n_out;
--TRIG_ILA0_2(22 downto 19) <= fmc516_adc_valid;
--TRIG_ILA0_2(23) <= fmc516_mmcm_lock_int;
--TRIG_ILA0_2(24) <= fmc516_lmk_lock_int;
--TRIG_ILA0_2(25) <= fmc516_debug_valid_int(1);
--TRIG_ILA0_2(26) <= fmc516_debug_full_int(1);
--TRIG_ILA0_2(27) <= fmc516_debug_empty_int(1);
--TRIG_ILA0_2(31 downto 28) <= (others => '0');
--
--TRIG_ILA0_3 <= dsp_adc_ch3_data &
-- dsp_adc_ch2_data;
-- Mix and BPF data
cmp_chipscope_ila_8192_bpf_mix : chipscope_ila_8192
port map (
CONTROL => CONTROL1,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA1_0,
TRIG1 => TRIG_ILA1_1,
TRIG2 => TRIG_ILA1_2,
TRIG3 => TRIG_ILA1_3,
TRIG4 => TRIG_ILA1_4
);
TRIG_ILA1_0(0) <= dsp_clk_ce_1;
TRIG_ILA1_0(1) <= dsp_clk_ce_35;
TRIG_ILA1_0(2) <= dsp_clk_ce_1112;
TRIG_ILA1_0(3) <= dsp_clk_ce_1390000; -- not used
TRIG_ILA1_0(4) <= dsp_clk_ce_2780000;
TRIG_ILA1_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA1_0(7 downto 6) <= (others => '0');
--TRIG_ILA1_1(dsp_bpf_ch0'range) <= dsp_bpf_ch0;
--TRIG_ILA1_2(dsp_bpf_ch2'range) <= dsp_bpf_ch2;
--TRIG_ILA1_1(dsp_poly35_ch0'range) <= dsp_poly35_ch0;
--TRIG_ILA1_2(dsp_poly35_ch2'range) <= dsp_poly35_ch2;
--TRIG_ILA1_3(dsp_cic_fofb_ch0'range) <= dsp_cic_fofb_ch0;
--TRIG_ILA1_4(dsp_cic_fofb_ch2'range) <= dsp_cic_fofb_ch2;
TRIG_ILA1_1(dsp_monit_amp_ch0'range) <= dsp_monit_amp_ch0;
TRIG_ILA1_2(dsp_monit_amp_ch1'range) <= dsp_monit_amp_ch1;
TRIG_ILA1_3(dsp_monit_amp_ch2'range) <= dsp_monit_amp_ch2;
TRIG_ILA1_4(dsp_monit_amp_ch3'range) <= dsp_monit_amp_ch3;
TRIG_ILA1_4(dsp_monit_amp_ch3'left+3 downto
dsp_monit_amp_ch3'left+1) <= dsp_monit_cic_unexpected &
dsp_monit_cfir_incorrect &
dsp_monit_pfir_incorrect;
-- TBT amplitudes data
cmp_chipscope_ila_8192_tbt_amp : chipscope_ila_8192
port map (
CONTROL => CONTROL2,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA2_0,
TRIG1 => TRIG_ILA2_1,
TRIG2 => TRIG_ILA2_2,
TRIG3 => TRIG_ILA2_3,
TRIG4 => TRIG_ILA2_4
);
TRIG_ILA2_0(0) <= dsp_clk_ce_1;
TRIG_ILA2_0(1) <= dsp_clk_ce_35;
TRIG_ILA2_0(2) <= dsp_clk_ce_1112;
TRIG_ILA2_0(3) <= dsp_clk_ce_1390000;
TRIG_ILA2_0(4) <= dsp_clk_ce_2780000; -- not used
TRIG_ILA2_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA2_0(7 downto 6) <= (others => '0');
TRIG_ILA2_1(dsp_tbt_amp_ch0'range) <= dsp_tbt_amp_ch0;
TRIG_ILA2_2(dsp_tbt_amp_ch1'range) <= dsp_tbt_amp_ch1;
TRIG_ILA2_3(dsp_tbt_amp_ch2'range) <= dsp_tbt_amp_ch2;
TRIG_ILA2_4(dsp_tbt_amp_ch3'range) <= dsp_tbt_amp_ch3;
TRIG_ILA2_4(dsp_tbt_amp_ch3'left+2 downto
dsp_tbt_amp_ch3'left+1) <= dsp_tbt_decim_q_ch01_incorrect &
dsp_tbt_decim_q_ch23_incorrect;
-- TBT position data
cmp_chipscope_ila_8192_tbt_pos : chipscope_ila_8192
port map (
CONTROL => CONTROL3,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA3_0,
TRIG1 => TRIG_ILA3_1,
TRIG2 => TRIG_ILA3_2,
TRIG3 => TRIG_ILA3_3,
TRIG4 => TRIG_ILA3_4
);
TRIG_ILA3_0(0) <= dsp_clk_ce_1;
TRIG_ILA3_0(1) <= dsp_clk_ce_35;
TRIG_ILA3_0(2) <= dsp_clk_ce_1112;
TRIG_ILA3_0(3) <= dsp_clk_ce_1390000;
TRIG_ILA3_0(4) <= dsp_clk_ce_2780000; -- not used
TRIG_ILA3_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA3_0(7 downto 6) <= (others => '0');
TRIG_ILA3_1(dsp_x_tbt'range) <= dsp_x_tbt;
TRIG_ILA3_2(dsp_y_tbt'range) <= dsp_y_tbt;
TRIG_ILA3_3(dsp_q_tbt'range) <= dsp_q_tbt;
TRIG_ILA3_4(dsp_sum_tbt'range) <= dsp_sum_tbt;
-- FOFB amplitudes data
cmp_chipscope_ila_8192_fofb_amp : chipscope_ila_8192
port map (
CONTROL => CONTROL4,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA4_0,
TRIG1 => TRIG_ILA4_1,
TRIG2 => TRIG_ILA4_2,
TRIG3 => TRIG_ILA4_3,
TRIG4 => TRIG_ILA4_4
);
TRIG_ILA4_0(0) <= dsp_clk_ce_1;
TRIG_ILA4_0(1) <= dsp_clk_ce_35;
TRIG_ILA4_0(2) <= dsp_clk_ce_1112;
TRIG_ILA4_0(3) <= dsp_clk_ce_1390000;
TRIG_ILA4_0(4) <= dsp_clk_ce_2780000; -- not used
TRIG_ILA4_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA4_0(7 downto 6) <= (others => '0');
TRIG_ILA4_1(dsp_fofb_amp_ch0'range) <= dsp_fofb_amp_ch0;
TRIG_ILA4_2(dsp_fofb_amp_ch1'range) <= dsp_fofb_amp_ch1;
TRIG_ILA4_3(dsp_fofb_amp_ch2'range) <= dsp_fofb_amp_ch2;
TRIG_ILA4_4(dsp_fofb_amp_ch3'range) <= dsp_fofb_amp_ch3;
TRIG_ILA4_4(dsp_fofb_amp_ch3'left+2 downto
dsp_fofb_amp_ch3'left+1) <= dsp_fofb_decim_q_01_missing &
dsp_fofb_decim_q_23_missing;
-- FOFB position data
cmp_chipscope_ila_8192_fofb_pos : chipscope_ila_8192
port map (
CONTROL => CONTROL5,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA5_0,
TRIG1 => TRIG_ILA5_1,
TRIG2 => TRIG_ILA5_2,
TRIG3 => TRIG_ILA5_3,
TRIG4 => TRIG_ILA5_4
);
TRIG_ILA5_0(0) <= dsp_clk_ce_1;
TRIG_ILA5_0(1) <= dsp_clk_ce_35;
TRIG_ILA5_0(2) <= dsp_clk_ce_1112;
TRIG_ILA5_0(3) <= dsp_clk_ce_1390000;
TRIG_ILA5_0(4) <= dsp_clk_ce_2780000; -- not used
TRIG_ILA5_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA5_0(7 downto 6) <= (others => '0');
TRIG_ILA5_1(dsp_x_fofb'range) <= dsp_x_fofb;
TRIG_ILA5_2(dsp_y_fofb'range) <= dsp_y_fofb;
TRIG_ILA5_3(dsp_q_fofb'range) <= dsp_q_fofb;
TRIG_ILA5_4(dsp_sum_fofb'range) <= dsp_sum_fofb;
-- Monitoring position data
cmp_chipscope_ila_8192_monit_pos : chipscope_ila_8192
port map (
CONTROL => CONTROL6,
CLK => dsp_sysclk,
TRIG0 => TRIG_ILA6_0,
TRIG1 => TRIG_ILA6_1,
TRIG2 => TRIG_ILA6_2,
TRIG3 => TRIG_ILA6_3,
TRIG4 => TRIG_ILA6_4
);
TRIG_ILA6_0(0) <= dsp_clk_ce_1;
TRIG_ILA6_0(1) <= dsp_clk_ce_35;
TRIG_ILA6_0(2) <= dsp_clk_ce_1112;
TRIG_ILA6_0(3) <= dsp_clk_ce_1390000;
TRIG_ILA6_0(4) <= dsp_clk_ce_2780000; -- not used
TRIG_ILA6_0(5) <= dsp_clk_ce_11120000;
TRIG_ILA6_0(7 downto 6) <= (others => '0');
TRIG_ILA6_1(dsp_x_monit'range) <= dsp_x_monit;
TRIG_ILA6_2(dsp_y_monit'range) <= dsp_y_monit;
TRIG_ILA6_3(dsp_q_monit'range) <= dsp_q_monit;
TRIG_ILA6_4(dsp_sum_monit'range) <= dsp_sum_monit;
end rtl;
|
----------------------------------------------------------------------------------
--
-- Lab session #4: Invaders testbech
--
-- Testing the block controlling the space invaders
--
-- Each invader has its power encoded in 2 bits:
-- 00 -> no invader
-- 01 -> easy invader (1 shot) [green]
-- 10 -> medium invader (2 shots) [?]
-- 11 -> hard invader (3 shots) [white]
--
-- Authors:
-- David Estévez Fernández
-- Sergio Vilches Expósito
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY invaders_tb IS
END invaders_tb;
ARCHITECTURE behavior OF invaders_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT invaders
PORT(
clk : IN std_logic;
reset : IN std_logic;
start : in std_logic;
bullX : IN std_logic_vector(4 downto 0);
bullY : IN std_logic_vector(3 downto 0);
hit : OUT std_logic;
invArray : INOUT std_logic_vector(39 downto 0);
invLine : INOUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal start: std_logic := '0';
signal bullX : std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(10,5));
signal bullY : std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(10,4));
--BiDirs
signal invArray : std_logic_vector(39 downto 0);
signal invLine : std_logic_vector(3 downto 0);
--Outputs
signal hit : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: invaders PORT MAP (
clk => clk,
reset => reset,
start => start,
bullX => bullX,
bullY => bullY,
hit => hit,
invArray => invArray,
invLine => invLine
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
start <= '1';
wait for 1200 ms;
-- Simulate a bullet:
bullX <= std_logic_vector(to_unsigned(5,5));
bullY <= invLine;
wait until hit = '1';
-- Reset the bullet
bullX <= std_logic_vector(to_unsigned(0,5)) after clk_period;
bullY <= std_logic_vector(to_unsigned(0,4)) after clk_period;
wait;
end process;
END;
|
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`protect end_protected
|
--------------------------------------------------------------------------------
--
-- PROJECT: D0 Run IIb Trigger L1 Calorimeter upgrade
--
-- MODULE: Utility package
--
-- ELEMENT: -
--
-- DESCRIPTION: several utility types and functions
--
-- AUTHOR: D. Calvet [email protected]
--
-- DATE AND HISTORY:
-- Jan 2002
-- March 2004: revision and cleanup
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_BIT.all;
package utility_pkg is
--
-- Conversion functions NATURAL <-> STD_LOGIC_VECTOR
--
function Std_Logic_Vector_To_Natural ( SLV : std_logic_vector) return NATURAL;
function Natural_To_Std_Logic_Vector (val, SIZE : integer) return std_logic_vector;
--
-- Bit vector Array types
--
type bit_vector_N_32 is array (natural range<>) of bit_vector(31 downto 0);
type bit_vector_N_16 is array (natural range<>) of bit_vector(15 downto 0);
function Bit_Vector_To_String( bv: Bit_Vector; SIZE : integer) return String;
--
-- Std_Logic_Vector Array types
--
type std_logic_vector_N_16 is array(natural range<>) of std_logic_vector(15 downto 0);
type std_logic_vector_N_14 is array(natural range<>) of std_logic_vector(13 downto 0);
type std_logic_vector_N_10 is array(natural range<>) of std_logic_vector( 9 downto 0);
type std_logic_vector_N_8 is array(natural range<>) of std_logic_vector( 7 downto 0);
type std_logic_vector_N_6 is array(natural range<>) of std_logic_vector( 5 downto 0);
type std_logic_vector_N_5 is array(natural range<>) of std_logic_vector( 4 downto 0);
type std_logic_vector_N_4 is array(natural range<>) of std_logic_vector( 3 downto 0);
type std_logic_vector_N_3 is array(natural range<>) of std_logic_vector( 2 downto 0);
type std_logic_vector_N_2 is array(natural range<>) of std_logic_vector( 1 downto 0);
--
-- String Array types
--
type string_N_4 is array(natural range<>) of string(4 downto 1);
type string_N_8 is array(natural range<>) of string(8 downto 1);
--
-- 2 D Arrays
--
TYPE std_logic_2D_Array IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF std_logic;
function sl2da_to_slv(sl2da: std_logic_2D_Array; ix : integer ) return std_logic_vector;
--
-- Conversion functions to string
--
function Convert_To_String(val : INTEGER) return STRING;
function Convert_To_String(bv: Bit_Vector) return STRING;
function Convert_To_String(ti: TIME) return STRING;
--
-- Conversion functions from string
--
function Convert_From_String(str : STRING) return std_logic;
function Convert_From_String(str : STRING) return std_logic_vector;
end utility_pkg;
package body utility_pkg is
--
-- Convert standard logic vector to natural
--
function Std_Logic_Vector_To_Natural ( SLV : std_logic_vector) return NATURAL is
variable Result : NATURAL := 0; -- conversion result
begin
for i in SLV'range loop
Result:= Result * 2; -- shift the variable to left
case SLV(i) is
when '1' | 'H' => Result := Result + 1;
when '0' | 'L' => Result := Result + 0;
when others => null;
end case;
end loop;
return Result;
end Std_Logic_Vector_To_Natural;
--
-- Convert natural to standard logic vector of given size
--
function Natural_To_Std_Logic_Vector (val, SIZE : integer) return std_logic_vector is
variable result : std_logic_vector(SIZE-1 downto 0);
variable l_val : NATURAL := val;
begin
-- synopsys translate_off
assert SIZE > 1
report "Error : function missuse : Natural_To_Std_Logic_Vector(val, negative size)"
severity failure;
-- synopsys translate_on
for i in 0 to result'length-1 loop
if (l_val mod 2) = 0 then
result(i) := '0';
else
result(i) := '1';
end if;
l_val := l_val/2;
end loop;
return result;
end Natural_To_Std_Logic_Vector;
function Bit_Vector_To_String( bv: Bit_Vector; SIZE : integer) return String is
variable result : string(SIZE downto 1);
begin
for i in (SIZE-1) downto 0 loop
if bv(i) ='0' then
result(i+1) := '0';
else
result(i+1) := '1';
end if;
end loop;
return result;
end Bit_Vector_To_String;
function sl2da_to_slv(sl2da: std_logic_2D_Array; ix : integer ) return std_logic_vector is
variable result : std_logic_vector(sl2da'range(2));
begin
-- synopsys translate_off
--assert sl2da'length(2) /= 10
--report "Error : sl2da_to_slv : range is not 10"
--severity failure;
-- synopsys translate_on
for i in sl2da'range(2) loop
result(i) := sl2da(ix,i);
end loop;
return result;
end sl2da_to_slv;
--
-- Conversion functions integer to string
--
function Convert_To_String(val : INTEGER) return STRING is
variable result : STRING(11 downto 1) := "-2147483648"; -- smallest integer and longest string
variable tmp : INTEGER;
variable pos : NATURAL := 1;
variable digit : NATURAL;
begin
-- for the smallest integer MOD does not seem to work...
--if val = -2147483648 then : compilation error with Xilinx tools...
if val < -2147483647 then
pos := 12;
else
pos := 1;
tmp := abs(val);
loop
digit := abs(tmp MOD 10);
tmp := tmp / 10;
result(pos) := character'val(character'pos('0') + digit);
pos := pos + 1;
exit when pos = 12;
exit when tmp = 0;
end loop;
if val < 0 then
result(pos) := '-';
pos := pos + 1;
end if;
end if;
return result((pos-1) downto 1);
end Convert_To_String;
--
-- Conversion functions Bit_Vector to string
--
function Convert_To_String(bv: Bit_Vector) return STRING is
variable result : string(1 to bv'length);
variable index : NATURAL := 1;
begin
for i in bv'range loop
if bv(i) ='0' then
result(index) := '0';
else
result(index) := '1';
end if;
index := index + 1;
end loop;
return result;
end Convert_To_String;
--
-- Conversion functions TIME to string
--
-- Note: TIME'image(x) is VHDL'93 only. It returns a value in units of simulator's resolution
--
function Convert_To_String(ti: TIME) return STRING is
variable result : STRING(14 downto 1) := " "; -- longest string is "2147483647 min"
variable tmp : NATURAL;
variable pos : NATURAL := 1;
variable digit : NATURAL;
variable resol : TIME := TIME'succ(ti) - ti; -- time resolution
variable scale : NATURAL := 1;
variable unit : TIME;
begin
if resol = 100 sec then scale := 100; unit := 1 sec;
elsif resol = 10 sec then scale := 10; unit := 1 sec;
elsif resol = 1 sec then scale := 1; unit := 1 sec;
elsif resol = 100 ms then scale := 100; unit := 1 ms;
elsif resol = 10 ms then scale := 10; unit := 1 ms;
elsif resol = 1 ms then scale := 1; unit := 1 ms;
elsif resol = 100 us then scale := 100; unit := 1 us;
elsif resol = 10 us then scale := 10; unit := 1 us;
elsif resol = 1 us then scale := 1; unit := 1 us;
elsif resol = 100 ns then scale := 100; unit := 1 ns;
elsif resol = 10 ns then scale := 10; unit := 1 ns;
elsif resol = 1 ns then scale := 1; unit := 1 ns;
elsif resol = 100 ps then scale := 100; unit := 1 ps;
elsif resol = 10 ps then scale := 10; unit := 1 ps;
elsif resol = 1 ps then scale := 1; unit := 1 ps;
elsif resol = 100 fs then scale := 100; unit := 1 fs;
elsif resol = 10 fs then scale := 10; unit := 1 fs;
elsif resol = 1 fs then scale := 1; unit := 1 fs;
else scale := 0; unit := 1 fs;
end if;
-- Write unit (reversed order)
if unit = 1 hr then
result(pos) := 'r';
pos := pos + 1;
result(pos) := 'h';
pos := pos + 1;
result(pos) := ' ';
pos := pos + 1;
elsif unit = 1 sec then
result(pos) := 'c';
pos := pos + 1;
result(pos) := 'e';
pos := pos + 1;
result(pos) := 's';
pos := pos + 1;
elsif unit = 1 ms then
result(pos) := 's';
pos := pos + 1;
result(pos) := 'm';
pos := pos + 1;
result(pos) := ' ';
pos := pos + 1;
elsif unit = 1 us then
result(pos) := 's';
pos := pos + 1;
result(pos) := 'u';
pos := pos + 1;
result(pos) := ' ';
pos := pos + 1;
elsif unit = 1 ns then
result(pos) := 's';
pos := pos + 1;
result(pos) := 'n';
pos := pos + 1;
result(pos) := ' ';
pos := pos + 1;
elsif unit = 1 ps then
result(pos) := 's';
pos := pos + 1;
result(pos) := 'p';
pos := pos + 1;
result(pos) := ' ';
pos := pos + 1;
elsif unit = 1 fs then
result(pos) := 's';
pos := pos + 1;
result(pos) := 'f';
pos := pos + 1;
result(pos) := ' ';
pos := pos + 1;
else
result(pos) := '?';
pos := pos + 1;
result(pos) := '?';
pos := pos + 1;
result(pos) := ' ';
pos := pos + 1;
end if;
-- Convert TIME to NATURAL
tmp := scale * (ti / resol);
loop
digit := tmp MOD 10; -- extract last digit
tmp := tmp / 10;
result(pos) := character'val(character'pos('0') + digit);
pos := pos + 1;
exit when tmp = 0;
end loop;
-- Return result (put back in right order)
return result((pos-1) downto 1);
end Convert_To_String;
--
-- Conversion from string to std_logic
--
-- T'value(s) is VHDL'93
function Convert_From_String(str : STRING) return std_logic is
variable result : std_logic := '-';
begin
if str(1) = '0' then result := '0';
elsif str(1) = 'L' then result := 'L';
elsif str(1) = '1' then result := '1';
elsif str(1) = 'H' then result := 'H';
elsif str(1) = 'Z' then result := 'Z';
elsif str(1) = 'U' then result := 'U';
elsif str(1) = 'X' then result := 'X';
elsif str(1) = 'W' then result := 'W';
elsif str(1) = '-' then result := '-';
else
-- synopsys translate_off
assert FALSE
report "Error : cannot convert string '" & str & "' to std_logic"
severity failure;
-- synopsys translate_on
end if;
return result;
end Convert_From_String;
--
-- Conversion from string to std_logic_vector
--
-- T'value(s) is VHDL'93
function Convert_From_String(str : STRING) return std_logic_vector is
variable result : std_logic_vector((str'length-1) downto 0) := (others => '-');
variable index : INTEGER := str'length-1;
variable str_1 : STRING(1 to 1);
begin
for i in str'range loop
str_1(1) := str(i);
result(index) := Convert_From_String(str_1);
index := index - 1;
end loop;
return result;
end Convert_From_String;
end utility_pkg;
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: from_stdin
-- read a signle character from stdout
-- returns LF ('\n'=0x0a) if there are no charachters on input
-- on the first ever read, returna LF on the empty line read
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity from_stdin is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : out reg32);
end from_stdin;
architecture simulation of from_stdin is
begin
U_READ_IN: process(clk,sel)
variable L : line;
variable this : character;
variable good : boolean := FALSE;
begin
if falling_edge(clk) and sel = '0' then
read(L, this, good);
if not(good) then
readline(input, L);
this := LF;
end if;
data <= x"000000" & std_logic_vector(to_signed(character'pos(this),8));
assert TRUE report "STD_IOrd= " & this;
end if;
end process U_READ_IN;
end architecture simulation;
-- ++ from_stdin +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of from_stdin is
begin
data <= (others => 'X');
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: print_data
-- print an integer to stdout, 32bit hexadecimal
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity print_data is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in reg32);
end print_data;
architecture simulation of print_data is
file output : text open write_mode is "STD_OUTPUT";
begin
U_WRITE_OUT: process(sel,clk)
variable msg : line;
begin
if falling_edge(clk) and sel = '0' then
write ( msg, string'(SLV32HEX(data)) );
writeline( output, msg );
end if;
end process U_WRITE_OUT;
end architecture simulation;
-- ++ print_data +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of print_data is
begin
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: to_stdout
-- print a signle character to stdout
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity to_stdout is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector);
end to_stdout;
architecture simulation of to_stdout is
file output : text open write_mode is "STD_OUTPUT";
begin
U_WRITE_OUT: process(clk,sel)
variable msg : line;
begin
if falling_edge(clk) and sel = '0' then
if (data(7 downto 0) = x"00") or (data(7 downto 0) = x"0a") then
writeline( output, msg );
else
write(msg, character'val(to_integer( unsigned(data(7 downto 0)))));
end if;
end if;
end process U_WRITE_OUT;
end architecture simulation;
-- ++ to_stdout +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of to_stdout is
begin
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: write_data_to_file
-- write one 32bit integer to file "output.data"
-- if( addr(3 downto 0) ) = "0000" then write to file
-- if( addr(3 downto 0) ) = "0100" then close file
-- if( addr(3 downto 0) ) = "0111" then assert dump_ram
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity write_data_file is
generic (OUTPUT_FILE_NAME : string := "output.data");
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in reg32;
data : in reg32;
byte_sel : in reg4;
dump_ram : out std_logic);
end write_data_file;
architecture simulation of write_data_file is
type uint_file_type is file of integer;
file output_file: uint_file_type open write_mode is OUTPUT_FILE_NAME;
begin
U_write_uint: process (clk,sel)
begin
dump_ram <= '0';
if falling_edge(clk) and sel = '0' then
if addr(3 downto 0) = b"0000" then -- data write
if wr = '0' then
write( output_file, to_integer(signed(data)) );
assert TRUE report "IOwr[" & SLV32HEX(addr) &"]:" & SLV32HEX(data);
end if;
elsif addr(3 downto 0) = b"0100" then -- close output file
file_close(output_file);
elsif addr(3 downto 0) = b"0111" then -- dump RAM
dump_ram <= '1';
end if;
end if;
end process U_write_uint;
end architecture simulation; -- write_file_data
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of write_data_file is
begin
dump_ram <= 'X';
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: read_data_file
-- read one 32bit integer from file "input.data"
-- if not EOF then write data to file
-- else status <= 1
-- on a read, return last status (EOF=1 or otherwise=0)
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity read_data_file is
generic (INPUT_FILE_NAME : string := "input.data");
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in reg32;
data : out reg32;
byte_sel : in reg4);
end read_data_file;
architecture simulation of read_data_file is
type uint_file_type is file of integer;
file input_file: uint_file_type open read_mode is INPUT_FILE_NAME;
signal status : reg32 := (others => '0');
begin
U_read_uint: process(clk,sel)
variable datum : integer := 0;
variable value : reg32; -- for debugging only
begin
data <= (others => 'X');
if falling_edge(clk) and sel = '0' then
if addr(3 downto 0) = b"0000" then -- data read
if wr = '1' then
if not endfile(input_file) then
read( input_file, datum );
data <= std_logic_vector(to_signed(datum, 32));
status <= x"00000000"; -- NOT_EndOfFile
value := std_logic_vector(to_signed(datum, 32)); -- DEBUG
assert TRUE report "IOrd[" & SLV32HEX(addr) &"]:"& SLV32HEX(value);
else
status <= x"00000001"; -- EndOfFile
end if;
else
data <= (others => 'X');
end if;
else -- status read
if wr = '1' then
data <= status;
else
data <= (others => 'X');
end if;
end if;
end if;
end process U_read_uint;
end architecture simulation;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of read_data_file is
begin
data <= (others => 'X');
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: generate interrupt after N clock cycles
-- Generates an interrupt after N cycles, N <= 2**30
-- Counting stops on reaching limit stored to counter.
-- data(31) = 1 enables interrupt on reaching limit;
-- data(31) = 0 disables interrupts
-- data(30) = 1 enables counting
-- data(30) = 0 stops counter and delays interrupt (forever?)
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity do_interrupt is
port (rst : in std_logic;
clk : in std_logic; -- clock pulses counted
sel : in std_logic;
wr : in std_logic;
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
irq : out std_logic);
constant NUM_BITS : integer := 30;
subtype c_width is std_logic_vector(NUM_BITS - 1 downto 0);
constant START_COUNT : c_width := (others => '0');
end do_interrupt;
architecture behavioral of do_interrupt is
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component countNup is
generic (NUM_BITS: integer);
port(clk, rst, ld, en: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector;
co: out std_logic);
end component countNup;
component FFDsimple is
port(clk, rst : in std_logic;
D : in std_logic;
Q : out std_logic);
end component FFDsimple;
signal Dlimit, Qlimit, Q: c_width;
signal ld_cnt, ld_reg, en, cnt_en, int_en, equals : std_logic;
signal i_ena, c_ena : std_logic;
begin
ld_reg <= wr when sel = '0' else '1';
ld_cnt <= not ld_reg;
Dlimit <= data_inp(NUM_BITS-1 downto 0);
U_LIMIT: registerN generic map (NUM_BITS, START_COUNT)
port map (clk, rst, ld_reg, Dlimit, Qlimit);
en <= cnt_en and (not equals);
U_COUNTER: countNup generic map (NUM_BITS)
port map (clk, rst, ld_cnt, en, START_COUNT, Q, open);
c_ena <= data_inp(30) when (sel='0' and wr='0') else cnt_en;
U_COUNT_EN: FFDsimple port map (clk, rst, c_ena, cnt_en);
i_ena <= data_inp(31) when (sel='0' and wr='0') else int_en;
U_INTERR_EN: FFDsimple port map (clk, rst, i_ena, int_en);
equals <= '1' when (Q = Qlimit(NUM_BITS-1 downto 0) ) else '0';
irq <= '1' when (equals = '1' and int_en = '1') else '0';
data_out <= int_en & cnt_en & Q;
end behavioral;
-- ++ do_interrupt +++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: simple UART bus interface (a wrapper to the real UART)
-- 8 data bits, no parity, 1 stop bit (8N1), catches: framing, overrun
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity simple_uart is
port (rst : in std_logic;
clk : in std_logic; -- processor clock
sel : in std_logic;
wr : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_inp : in std_logic_vector;
data_out : out std_logic_vector;
txdat : out std_logic; -- serial transmission (output)
rxdat : in std_logic; -- serial reception (input)
rts : out std_logic;
cts : in std_logic;
irq : out std_logic; -- interrupt request
bit_rt : out std_logic_vector); -- communication speed; for TB only
end simple_uart;
architecture behavioral of simple_uart is
component uart_int is
port(clk, rst: in std_logic;
s_ctrlwr, s_stat : in std_logic; -- select registers
s_tx, s_rx : in std_logic; -- select registers
s_intwr, s_intrd : in std_logic; -- select interrupt register
d_inp: in std_logic_vector; -- 32 bit input
d_out: out std_logic_vector; -- 32 bit output
txdat: out std_logic; -- serial transmission (output)
rxdat: in std_logic; -- serial reception (input)
rts: out std_logic;
cts: in std_logic;
irq_all: out std_logic; -- interrupt request
bit_rt: out std_logic_vector); -- communication speed - for TB only
end component uart_int;
signal s_ctrlwr, s_stat, s_tx, s_rx, s_intwr, s_intrd : std_logic;
signal d_inp, d_out : reg32;
begin
U_UART: uart_int port map (clk, rst, s_ctrlwr, s_stat, s_tx, s_rx,
s_intwr, s_intrd,
d_inp,d_out, txdat,rxdat, rts,cts, irq, bit_rt);
-- a3a2 wr register (aligned to word addresses)
-- 00 0 control, W+r IO_UART_ADDR +0
-- 01 x status, R IO_UART_ADDR +4
-- 10 0 interrupt conmtrol W IO_UART_ADDR +8
-- 10 1 interrupt conmtrol R IO_UART_ADDR +8
-- 11 0 transmission W IO_UART_ADDR +12
-- 11 1 reception R IO_UART_ADDR +12
s_ctrlwr <= '1' when sel = '0' and addr = b"00" and wr = '0' else '0'; -- W
s_stat <= '1' when sel = '0' and addr = b"01" else '0'; -- R+W
s_intwr <= '1' when sel = '0' and addr = b"10" and wr = '0' else '0'; -- W
s_intrd <= '1' when sel = '0' and addr = b"10" and wr = '1' else '0'; -- R
s_tx <= '1' when sel = '0' and addr = b"11" and wr = '0' else '0'; -- W-O
s_rx <= '1' when sel = '0' and addr = b"11" and wr = '1' else '0'; -- R-O
data_out <= d_out;
d_inp <= data_inp;
end behavioral;
-- ++ simple uart +++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: system statistics: gather statistics in one place
-- processor reads performance counters, on word boundaries, adressed as
-- cnt_dc_ref when "00000", 0
-- cnt_dc_rd_hit when "00100", 4
-- cnt_dc_wr_hit when "01000", 8
-- cnt_dc_flush when "01100", 12
-- cnt_ic_ref when "10000", 16
-- cnt_ic_hit when "10100", 20
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity sys_stats is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
addr : in reg32;
data : out reg32;
cnt_dc_ref : in integer;
cnt_dc_rd_hit : in integer;
cnt_dc_wr_hit : in integer;
cnt_dc_flush : in integer;
cnt_ic_ref : in integer;
cnt_ic_hit : in integer);
end sys_stats;
architecture simulation of sys_stats is
begin
U_SYNC_OUTPUT: process(clk,sel)
variable i_c : integer := 0;
begin
data <= (others => '0');
if falling_edge(clk) and sel = '0' then
case addr(4 downto 2) is
when "000" => i_c := cnt_dc_ref;
when "001" => i_c := cnt_dc_rd_hit;
when "010" => i_c := cnt_dc_wr_hit;
when "011" => i_c := cnt_dc_flush;
when "100" => i_c := cnt_ic_ref;
when "101" => i_c := cnt_ic_hit;
when others => i_c := 0;
end case;
end if;
data <= std_logic_vector(to_signed(i_c,32));
end process U_SYNC_OUTPUT;
end architecture simulation;
-- ++ system statistics ++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of sys_stats is
begin
data <= (others => 'X');
end architecture fake;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: to_7seg
-- input format:
-- b14 b13 b12 b09 b08 b07..b04 b03..b02
-- red gre blu MSdot msdot MSdigit msdigit
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.p_wires.all;
entity to_7seg is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
wr : in std_logic;
data : in std_logic_vector;
display0 : out reg8;
display1 : out reg8;
red : out std_logic;
green : out std_logic;
blue : out std_logic);
-- 2 decimal points, 2 hex digits, 3 leds
constant NUM_BITS : integer := 15;
subtype c_width is std_logic_vector(NUM_BITS - 1 downto 0);
constant INIT_VALUE : c_width := (others => '0');
end to_7seg;
architecture behavioral of to_7seg is
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component display_7seg is
port(data_i : in std_logic_vector(3 downto 0);
decimal_i : in std_logic;
disp_7seg_o : out std_logic_vector(7 downto 0));
end component display_7seg;
signal value : std_logic_vector(NUM_BITS-1 downto 0);
signal middle : std_logic;
begin
U_HOLD_data: registerN generic map (NUM_BITS, INIT_VALUE)
port map (clk, rst, sel, data(NUM_BITS-1 downto 0), value);
red <= value(14);
green <= value(13);
blue <= value(12);
U_DSP1: display_7seg port map (value(7 downto 4), value(9), display1);
U_DSP0: display_7seg port map (value(3 downto 0), value(8), display0);
U_sim: process(sel,rst,clk)
begin
middle <= not(sel) and not(clk); -- to remove spurious reports
if rst = '1' then
assert not(rising_edge(middle))
report "dsp7seg: "& SLV32HEX(data) severity NOTE;
end if;
end process;
end behavioral;
-- ++ to_7seg +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: read_keys
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity read_keys is
generic (DEB_CYCLES: natural); -- debouncing interval
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
data : out reg32;
kbd : in std_logic_vector (11 downto 0);
sw : in std_logic_vector (3 downto 0));
constant DEB_BITS : integer := 16; -- debounce counter width
constant CNT_MAX : integer := (2**DEB_BITS - 1);
constant x_DEB_CYCLES : std_logic_vector(DEB_BITS-1 downto 0)
:= std_logic_vector(to_signed((CNT_MAX - DEB_CYCLES),DEB_BITS));
constant NUM_BITS : integer := 4; -- four bits to hold key number
subtype c_width is std_logic_vector(NUM_BITS - 1 downto 0);
constant NO_KEY : c_width := (others => '0');
end read_keys;
architecture behavioral of read_keys is
component FFD is
port(clk, rst, set : in std_logic;
D : in std_logic; Q : out std_logic);
end component FFD;
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector(NUM_BITS-1 downto 0);
Q: out std_logic_vector(NUM_BITS-1 downto 0));
end component registerN;
component countNup is
generic (NUM_BITS: integer := 16);
port(clk, rst, ld, en: in std_logic;
D: in std_logic_vector((NUM_BITS - 1) downto 0);
Q: out std_logic_vector((NUM_BITS - 1) downto 0);
co: out std_logic);
end component countNup;
type kbd_state is (st_idle, st_start, st_wait, st_load, st_release);
signal kbd_current_st, kbd_next_st : kbd_state;
attribute SYN_ENCODING of kbd_state : type is "safe";
-- signal kbd_dbg_st : integer; -- debugging only
signal cnt_ld, cnt_en, new_ld : std_logic;
signal press, debounced, rdy_clr, ready : std_logic;
signal keys_data, cpu_data : reg4;
signal d : reg2;
-- signal count : std_logic_vector(DEB_BITS-1 downto 0); -- debugging only
begin
data(31) <= ready;
data(30 downto 8) <= (others => '0');
data(7) <= sw(3);
data(6) <= sw(2);
data(5) <= sw(1);
data(4) <= sw(0);
data(3 downto 0) <= cpu_data(3 downto 0);
U_DEBOUNCER: countNup generic map (DEB_BITS)
port map (clk=>clk, rst=>rst, ld=>cnt_ld, en=>cnt_en,
D=>x_DEB_CYCLES, Q=>open, co=>debounced);
U_NEW_DATA: registerN generic map (4, NO_KEY)
port map (clk, rst, new_ld, keys_data, cpu_data);
d <= new_ld & sel; -- new_ld, sel active in '0'
with d select
rdy_clr <= '1' when "00",
'1' when "01",
'0' when "10",
ready when others;
U_READY: FFD port map (clk, rst, '1', rdy_clr, ready);
press <= BOOL2SL(keys_data /= b"0000");
-- translate key position to key code
-- code for key 0 cannot be zero; value-holding register is reset to "0000"
with kbd select
keys_data <= "0001" when "000000000001", -- 1
"0010" when "000000000010", -- 2
"0011" when "000000000100", -- 3
"0100" when "000000001000", -- 4
"0101" when "000000010000", -- 5
"0110" when "000000100000", -- 6
"0111" when "000001000000", -- 7
"1000" when "000010000000", -- 8
"1001" when "000100000000", -- 9
"1010" when "001000000000", -- *
"1111" when "010000000000", -- 0, cannot be "0000"
"1011" when "100000000000", -- #
"0000" when others; -- no key depressed
-- ---------------------------------------------------------------------
U_KBD_st_reg: process(rst,clk)
begin
if rst = '0' then
kbd_current_st <= st_idle;
elsif rising_edge(clk) then
kbd_current_st <= kbd_next_st;
end if;
end process U_KBD_st_reg; ----------------------------------------------
-- kbd_dbg_st <= integer(kbd_state'pos(kbd_current_st)); -- for debugging
U_KBD_st_transitions: process(kbd_current_st, press, debounced) --------
begin
case kbd_current_st is
when st_idle => -- 0
if press = '1' then
kbd_next_st <= st_start;
else
kbd_next_st <= st_idle;
end if;
when st_start => -- 1
kbd_next_st <= st_wait;
when st_wait => -- 2
if debounced = '1' then
kbd_next_st <= st_load;
else
kbd_next_st <= st_wait;
end if;
when st_load => -- 3
kbd_next_st <= st_release;
when st_release => -- 4
if press = '1' then
kbd_next_st <= st_release;
else
kbd_next_st <= st_idle;
end if;
end case;
end process U_KBD_st_transitions; ------------------------------------
U_KBD_outputs: process(kbd_current_st) ------------------------------
begin
case kbd_current_st is
when st_idle |st_release => -- 0,4
new_ld <= '1';
cnt_ld <= '0';
cnt_en <= '0';
when st_start => -- 1
new_ld <= '1';
cnt_ld <= '1';
cnt_en <= '0';
when st_wait => -- 2
new_ld <= '1';
cnt_ld <= '0';
cnt_en <= '1';
when st_load => -- 3
new_ld <= '0';
cnt_ld <= '1';
cnt_en <= '0';
end case;
end process U_KBD_outputs; -------------------------------------------
end behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: LCD display controller
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity LCD_display is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in std_logic; -- 0=constrol, 1=data
data_inp : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
LCD_DATA : inout std_logic_vector(7 downto 0); -- bidirectional bus
LCD_RS : out std_logic; -- LCD register select 0=ctrl, 1=data
LCD_RW : out std_logic; -- LCD read=1, 0=write
LCD_EN : out std_logic; -- LCD enable=1
LCD_BLON : out std_logic); -- LCD backlight on=1
constant NUM_BITS : integer := 8;
subtype c_width is std_logic_vector(NUM_BITS - 1 downto 0);
constant INIT_VALUE : c_width := (others => '0');
end LCD_display;
architecture rtl of LCD_display is
component wait_states is
generic (NUM_WAIT_STATES :integer);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component FFD is
port(clk, rst, set, D : in std_logic; Q : out std_logic);
end component FFD;
component FFDsimple is
port(clk, rst, D : in std_logic; Q : out std_logic);
end component FFDsimple;
type lcd_state is (st_init, st_idle, st_n, st_n1, st_n2, st_n3,
st_n4, st_n5, st_n6, st_n7, st_n8, st_n9, st_na, st_nb);
attribute SYN_ENCODING of lcd_state : type is "safe";
signal lcd_current_st, lcd_next_st : lcd_state;
signal lcd_current : integer; -- debugging only
signal waiting, wait1, wait2, n_sel: std_logic;
signal sel_rs, RS, sel_rw, RW,lcd_enable,lcd_read : std_logic;
signal inp_data, out_data : reg8;
begin
n_sel <= not(sel);
U_WAIT_ON_READS: component wait_states generic map (1)
port map (rst, clk, sel, wait1);
U_WAIT2: FFDsimple port map (clk, rst, wait1, wait2);
rdy <= not(wait1 or wait2 or waiting); -- wait for 260ns
sel_rs <= addr when sel = '0' else RS;
U_INPUT_RS: FFDsimple port map (clk, rst, sel_rs, RS);
U_INPUT: registerN generic map (NUM_BITS, INIT_VALUE)
port map (clk, rst, sel, data_inp(NUM_BITS-1 downto 0), inp_data);
U_OUTPUT: registerN generic map (NUM_BITS, INIT_VALUE)
port map (clk, rst, lcd_read, out_data, data_out(NUM_BITS-1 downto 0));
data_out(31 downto NUM_BITS) <= (others => 'X');
-- TESTING ONLY
-- out_data <= b"00000000" when RW = '1' else (others => 'X');
out_data <= LCD_DATA when RW = '1' else (others => 'Z');
LCD_DATA <= inp_data when RW = '0' else (others => 'Z');
LCD_RS <= RS; -- LCD register select 0=ctrl, 1=data
sel_rw <= wr when sel = '0' else RW;
U_INPUT_RW: FFD port map (clk, '1', rst, sel_rw, RW);
LCD_RW <= RW; -- LCD read=1, 0=write
LCD_EN <= lcd_enable; -- LCD enable=1
LCD_BLON <= '1'; -- LCD backlight
-- state register----------------------------------------------------
U_st_reg: process(rst,clk)
begin
if rst = '0' then
lcd_current_st <= st_init;
elsif rising_edge(clk) then
lcd_current_st <= lcd_next_st;
end if;
end process U_st_reg;
lcd_current <= lcd_state'pos(lcd_current_st); -- debugging only
U_st_transitions: process(lcd_current_st, RW, sel)
begin
case lcd_current_st is
when st_init => -- 0
lcd_next_st <= st_idle;
when st_idle => -- 1
if sel = '0' then
lcd_next_st <= st_n;
else
lcd_next_st <= st_idle;
end if;
when st_n => -- 2
lcd_next_st <= st_n1;
when st_n1 => -- 3, setup for Enable is 20ns
lcd_next_st <= st_n2;
when st_n2 => -- 4, keep Enable=1 for 200ns
lcd_next_st <= st_n3;
when st_n3 => -- 5, data setup is 100ns
lcd_next_st <= st_n4;
when st_n4 => -- 6
lcd_next_st <= st_n5;
when st_n5 => -- 7
lcd_next_st <= st_n6;
when st_n6 => -- 8
lcd_next_st <= st_n7;
when st_n7 => -- 9
lcd_next_st <= st_n8;
when st_n8 => -- 10, can read now
lcd_next_st <= st_n9;
when st_n9 => -- 11, data hold for Enable is >40ns
lcd_next_st <= st_na;
when st_na => -- 12
lcd_next_st <= st_nb;
when st_nb => -- 13
lcd_next_st <= st_idle;
when others => -- ??
lcd_next_st <= st_idle; -- Enable cycle >500ns
end case;
end process U_st_transitions;
U_st_outputs: process(lcd_current_st)
begin
case lcd_current_st is
when st_init =>
lcd_enable <= '0'; -- disable
lcd_read <= '1';
waiting <= '0';
when st_idle =>
lcd_enable <= '0'; -- disable
lcd_read <= '1';
waiting <= '0';
when st_n | st_n1 =>
lcd_enable <= '0'; -- disable, waiting for setup
lcd_read <= '1';
waiting <= '1';
when st_n2 | st_n3 | st_n4 | st_n5 | st_n6 | st_n7 =>
lcd_enable <= '1'; -- enable, waiting
lcd_read <= '1';
waiting <= '1';
when st_n8 =>
lcd_enable <= '1'; -- enable, still waiting
lcd_read <= '0';
waiting <= '1';
when st_n9 =>
lcd_enable <= '1'; -- enable, still waiting
lcd_read <= '1';
waiting <= '1';
when st_na =>
lcd_enable <= '0'; -- disable, still waiting
lcd_read <= '1';
waiting <= '1';
when st_nb =>
lcd_enable <= '0'; -- disable, stop waiting
lcd_read <= '1'; -- held inp data for 40ns
waiting <= '0';
when others =>
lcd_enable <= '0'; -- disable
lcd_read <= '1';
waiting <= '0';
end case;
end process U_st_outputs;
end architecture rtl;
-- -----------------------------------------------------------------------
-- -----------------------------------------------------------------------
architecture fake of LCD_display is
begin
rdy <= HI;
data_out <= (others => 'X');
LCD_RS <= LO; -- LCD register select 0=ctrl, 1=data
LCD_RW <= HI; -- LCD read=1, 0=write
LCD_EN <= LO; -- LCD enable=1
LCD_BLON <= LO; -- LCD backlight on=1
end architecture fake;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: SDcard bus interface (a wrapper to the SDcard controller)
-- base + b"0000" -> address register
-- base + b"0100" -> data registers (RD/WR)
-- base + b"1000" -> control register
-- base + b"1100" -> status register
--
-- Software must ALWAYS check status(31) = busy before reading/writing
-- to controller. If controller is not busy, check for errors.
-- In case of errors, reset controller by writing 0x10 to control register.
-- Wait states (rdy=0) are inserted as needed by the bus interface.
--
-- Control register: bit(4)=1 reset the controller (because of error)
-- bit(1)=1 perform a sector READ
-- bit(0)=1 perform a sector WRITE
-- bit(0) and bit(1) shall not be both set
--
-- Status register: bit(31)=1 controller is busy (busy_o=1)
-- bit(30)=1 simultaneous read and write commands
-- bit(15..0) controller error bits (see SDcard.vhd)
--
-- Address register: 32 bits, can be written to, and read from
--
-- Data register: data write (sw by CPU), data read (lw by CPU)
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.SdCardPckg.all;
use work.p_wires.all;
entity SDcard is
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic;
rdy : out std_logic;
wr : in std_logic;
addr : in reg2; -- a03, a02
data_inp : in reg32;
data_out : out reg32;
sdc_cs : out std_logic; -- SDcard chip-select
sdc_clk : out std_logic; -- SDcard serial clock
sdc_mosi_o : out std_logic; -- SDcard serial data out (to card)
sdc_miso_i : in std_logic; -- SDcard serial data inp (fro card)
irq : out std_logic); -- interrupt request (not yet used)
end SDCard;
architecture rtl of SDcard is
component wait_states is
generic (NUM_WAIT_STATES :integer);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component FFDsimple is
port(clk, rst, D : in std_logic; Q : out std_logic);
end component FFDsimple;
component SdCardCtrl is
generic (
FREQ_G : real; -- Master clock frequency (MHz).
INIT_SPI_FREQ_G : real; -- Slow SPI clock freq during init (MHz).
SPI_FREQ_G : real; -- Operational SPI freq. to the SD card (MHz).
BLOCK_SIZE_G : natural; -- Num bytes in an SD card block or sector.
CARD_TYPE_G : CardType_t); -- Type of SD card connected.
port (
-- Host-side interface signals.
clk_i : in std_logic; -- Master clock.
reset_i : in std_logic; -- active-high, synchronous reset.
rd_i : in std_logic; -- active-high read block request.
wr_i : in std_logic; -- active-high write block request.
continue_i : in std_logic; -- If true, inc address and continue R/W.
addr_i : in std_logic_vector; -- Block address.
data_i : in std_logic_vector; -- Data to write to block.
data_o : out std_logic_vector; -- Data read from block.
busy_o : out std_logic; -- High when controller is busy.
hndShk_i : in std_logic; -- High when host has new or has taken data.
hndShk_o : out std_logic; -- High when cntlr has taken or new data.
error_o : out std_logic_vector;
-- I/O signals to the external SD card.
cs_bo : out std_logic; -- Active-low chip-select.
sclk_o : out std_logic; -- Serial clock to SD card.
mosi_o : out std_logic; -- Serial data output to SD card.
miso_i : in std_logic; -- Serial data input from SD card.
state : out std_logic_vector); -- state, debugging only
end component SdCardCtrl;
-- use fake / rtl
for U_SDcard : SdCardCtrl use entity work.SdCardCtrl(fake);
signal s_addr, s_stat, s_ctrl, s_read, s_write : std_logic;
signal continue, busy, hndShk_i, hndShk_o, wr_i, rd_i : std_logic;
signal wait1, waiting, new_trans, new_data_rd, sdc_rst : std_logic;
signal ctrl_err, set_wr_i, set_rd_i : std_logic;
signal do_reset, do_reset1 : std_logic;
signal data_rd, data_rd_reg, data_wr_reg : reg8;
signal error_o : reg16;
signal addr_reg : reg32;
signal sel_data_out : reg3;
signal state : reg5;
signal w : reg5;
begin
U_SDcard: SdCardCtrl
-- generic map (50.0, 0.400, 12.5, 512, SD_CARD_E)
generic map (50.0, 25.0, 25.0, 512, SD_CARD_E)
port map (clk, sdc_rst, rd_i, wr_i, '0', addr_reg,
data_wr_reg, data_rd, busy, hndshk_i, open, error_o,
-- data_wr_reg, data_rd, busy, hndshk_i, hndshk_o, error_o,
sdc_cs, sdc_clk, sdc_mosi_o, sdc_miso_i, state);
hndshk_i <= waiting;
U_WAIT1: component wait_states generic map (1)
port map (rst, clk, new_trans, wait1);
U_WAIT: process(rst, clk, wait1, hndshk_o)
variable w : std_logic;
begin
if rst = '0' then
w := '0';
elsif rising_edge(clk) then
if wait1 = '1' then -- new transaction started
w := '1';
end if;
if hndshk_o = '1' then -- transaction ended
w := '0';
end if;
end if;
waiting <= w;
end process U_WAIT;
rdy <= not(wait1 or waiting); -- wait for controller
new_data_rd <= not(hndshk_o);
U_W1: FFDsimple port map (clk, rst, wait1, w(0));
U_W2: FFDsimple port map (clk, rst, w(0), w(1));
U_W3: FFDsimple port map (clk, rst, w(1), w(2));
U_W4: FFDsimple port map (clk, rst, w(2), w(3));
U_W5: FFDsimple port map (clk, rst, w(3), w(4));
U_W6: FFDsimple port map (clk, rst, w(4), hndshk_o);
-- a3a2 wr register (aligned to word addresses: a1a0=00)
-- 00 0 write to ADDR register (32 bits)
-- 00 1 returns current value of ADDR
-- 01 1 read from data register (8 bits, least significant byte)
-- 01 0 write to data register (8 bits, least significant byte)
-- 10 0 write to control register
-- 10 1 read from control register
-- 11 0 no effect (not possible to write to status register)
-- 11 1 read status register
new_trans <= '0' when addr = b"01" and sel = '0' else '1';
s_addr <= '0' when sel = '0' and addr = b"00" and wr = '0' else '1';
s_write <= '0' when sel = '0' and addr = b"01" and wr = '0' else '1';
s_read <= '0' when sel = '0' and addr = b"01" and wr = '1' else '1';
s_ctrl <= '1' when sel = '0' and addr = b"10" and wr = '0' else '0';
s_stat <= '1' when sel = '0' and addr = b"11" and wr = '1' else '0';
do_reset <= '1' when s_ctrl = '1' and data_inp(4) = '1' else '0';
U_RESET1: FFDsimple port map (clk, rst, do_reset, do_reset1);
sdc_rst <= not(rst) or do_reset or do_reset1; -- held HI for 2 cycles
-- hold wr_i active until first access to WR-register
set_wr_i <= ((s_ctrl and data_inp(0)) or (wr_i and s_write)) and s_write;
U_WR_STROBE: FFDsimple port map (clk, rst, set_wr_i, wr_i);
-- hold rd_i active until first access to RD-register
set_rd_i <= ((s_ctrl and data_inp(1)) or (rd_i and s_read)) and s_read;
U_RD_STROBE: FFDsimple port map (clk, rst, set_rd_i, rd_i);
ctrl_err <= wr_i and rd_i; -- cannot both read AND write
U_ADDR_REG: registerN generic map (32, x"00000000")
port map (clk, rst, s_addr, data_inp, addr_reg);
U_WRITE_REG: registerN generic map (8, x"00")
port map (clk, rst, s_write, data_inp(7 downto 0), data_wr_reg);
U_READ_REG: registerN generic map (8, x"00")
port map (clk, rst, new_data_rd, data_rd, data_rd_reg);
sel_data_out <= sel & addr;
with sel_data_out select
data_out <= addr_reg when "000",
x"000000" & data_rd_reg when "001",
x"000000" & b"000" & ctrl_err & b"00" & rd_i & wr_i when "010",
busy & ctrl_err & b"00" & b"000" & state & x"0" & error_o when "011",
(others => 'X') when others;
end architecture rtl;
-- ++ SDcard ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++ SDcard ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture fake of SDcard is
begin
rdy <= HI;
data_out <= (others => 'X');
sdc_cs <= HI;
sdc_clk <= LO; -- SDcard serial clock
sdc_mosi_o <= LO; -- SDcard serial data out (to card)
irq <= LO; -- interrupt request (not yet used)
end architecture fake;
-- ++ SDcard ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6272)
`protect data_block
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
package wishbone_pkg2 is
subtype my_vector is std_logic_vector;
type t_wishbone_master_out is record
dat : my_vector;
end record;
subtype t_wishbone_slave_in is t_wishbone_master_out;
end wishbone_pkg2;
library work;
use work.wishbone_pkg2.all;
library ieee;
use ieee.std_logic_1164.all;
entity repro2 is
end entity;
architecture bench of repro2 is
signal wbs_s : t_wishbone_slave_in(
dat(32-1 downto 0)
);
begin
stimulus : process
begin
wbs_s.dat <= x"deadbeef";
wait for 100 ns;
report "pass" severity note;
wait;
end process;
dut : block
port (wbs_i : in t_wishbone_slave_in);
port map (wbs_i => wbs_s);
begin
end block;
end architecture;
|
-- Copyright (c) 2015 University of Florida
--
-- This file is part of uaa.
--
-- uaa is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- uaa is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with uaa. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description:
-- The ram entity implements a ram with a standard 1-read port, 1-write port
-- interface. The ram is configurable in terms of data width (width of each
-- word), the address width, and the number of words. The ram has a write
-- enable for writes, but does not contain a read enable. Instead, the ram
-- reads from the read address every cycle.
--
-- The entity contains several different architectures that implement different
-- ram behaviors. e.g. synchronous reads, asynchronous reads, synchronoous
-- reads during writes.
--
-- Notes:
-- Asychronous reads are not supported by all FPGAs.
--
-------------------------------------------------------------------------------
-- Generics Description
-- word_width : The width in bits of a single word (required)
-- addr_width : The width in bits of an address, which also defines the
-- number of words (required)
-- num_words : The number of words in the memory. This generic will
-- usually be 2**addr_width, but the entity supports
-- non-powers of 2 (required)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description:
-- clk : clock input
-- wen : write enable (active high)
-- waddr : write address
-- wdata : write data
-- raddr : read address
-- rdata : read data
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram is
generic (
num_words : positive;
word_width : positive;
addr_width : positive
);
port (
clk : in std_logic;
-- write port
wen : in std_logic;
waddr : in std_logic_vector(addr_width-1 downto 0);
wdata : in std_logic_vector(word_width-1 downto 0);
-- read port
raddr : in std_logic_vector(addr_width-1 downto 0);
rdata : out std_logic_vector(word_width-1 downto 0)
);
end entity;
-- This architecture uses asynchronous reads that return the read data in the
-- same cycle.
architecture ASYNC_READ of ram is
type memory_type is array (natural range <>) of std_logic_vector(word_width-1 downto 0);
signal memory : memory_type(num_words-1 downto 0) := (others => (others => '0'));
begin
process(clk)
begin
if clk'event and clk = '1' then
if wen = '1' then
memory(to_integer(unsigned(waddr))) <= wdata;
end if;
end if;
end process;
rdata <= memory(to_integer(unsigned(raddr)));
end ASYNC_READ;
-- This architecture uses synchronous reads with a one-cycle delay. In the case
-- of reading and writing to the same address, the read returns the new data
-- that was written.
architecture SYNC_READ_DURING_WRITE of ram is
type memory_type is array (natural range <>) of std_logic_vector(word_width-1 downto 0);
signal memory : memory_type(num_words-1 downto 0) := (others => (others => '0'));
signal raddr_reg : std_logic_vector(addr_width-1 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
if wen = '1' then
memory(to_integer(unsigned(waddr))) <= wdata;
end if;
raddr_reg <= raddr;
end if;
end process;
rdata <= memory(to_integer(unsigned(raddr_reg)));
end SYNC_READ_DURING_WRITE;
-- This architecture uses synchronous reads with a one-cycle delay. In the case
-- of reading and writing to the same address, the read returns the data at
-- the address before the write.
architecture SYNC_READ of ram is
type memory_type is array (natural range <>) of std_logic_vector(word_width-1 downto 0);
signal memory : memory_type(num_words-1 downto 0) := (others => (others => '0'));
begin
process(clk)
begin
if clk'event and clk = '1' then
if wen = '1' then
memory(to_integer(unsigned(waddr))) <= wdata;
end if;
rdata <= memory(to_integer(unsigned(raddr)));
end if;
end process;
end SYNC_READ;
|
--------------------------------------------------------------------------------
-- File : temac_10_100_1000_fifo_block.v
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the FIFO Block level vhdl wrapper for the Tri-Mode
-- Ethernet MAC core. This wrapper enhances the standard MAC core
-- with an example FIFO. The interface to this FIFO is
-- designed to the AXI-S specification.
-- Please refer to core documentation for
-- additional FIFO and AXI-S information.
--
-- _________________________________________________________
-- | |
-- | FIFO BLOCK LEVEL WRAPPER |
-- | |
-- | _____________________ ______________________ |
-- | | _________________ | | | |
-- | | | | | | | |
-- -------->| | TX AXI FIFO | |---->| Tx Tx |--------->
-- | | | | | | AXI-S PHY | |
-- | | |_________________| | | I/F I/F | |
-- | | | | | |
-- AXI | | 10/100/1G | | TRI-MODE ETHERNET | |
-- Stream | | ETHERNET FIFO | | MAC CORE | | PHY I/F
-- | | | | BLOCK WRAPPER | |
-- | | _________________ | | | |
-- | | | | | | | |
-- <--------| | RX AXI FIFO | |<----| Rx Rx |<---------
-- | | | | | | AXI-S PHY | |
-- | | |_________________| | | I/F I/F | |
-- | |_____________________| |______________________| |
-- | |
-- |_________________________________________________________|
--
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- The module declaration for the fifo block level wrapper.
--------------------------------------------------------------------------------
entity temac_10_100_1000_fifo_block is
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_reset : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_axis_fifo_tlast : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_axis_fifo_tlast : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
clk_enable : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- Configuration Vector
-------------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0)
);
end temac_10_100_1000_fifo_block;
architecture wrapper of temac_10_100_1000_fifo_block is
------------------------------------------------------------------------------
-- Component declaration for the block level
------------------------------------------------------------------------------
component temac_10_100_1000_block
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic;
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
clk_enable : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
-- Configuration Vector
-----------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the fifo
------------------------------------------------------------------------------
component temac_10_100_1000_ten_100_1g_eth_fifo
generic (
FULL_DUPLEX_ONLY : boolean := true); -- If fifo is to be used only in full
-- duplex set to true for optimised implementation
port (
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
tx_collision : in std_logic;
tx_retransmit : in std_logic;
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tready : out std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
rx_fifo_overflow : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component temac_10_100_1000_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- Internal signals used in this fifo block level wrapper.
------------------------------------------------------------------------------
-- Note: KEEP attributes preserve signal names so they can be displayed in
-- simulator wave windows
signal rx_reset_int : std_logic; -- MAC Rx reset
signal tx_reset_int : std_logic; -- MAC Tx reset
signal tx_mac_resetn : std_logic;
signal rx_mac_resetn : std_logic;
signal tx_mac_reset : std_logic;
signal rx_mac_reset : std_logic;
-- MAC receiver client I/F
signal rx_axis_mac_tdata : std_logic_vector(7 downto 0);
signal rx_axis_mac_tvalid : std_logic;
signal rx_axis_mac_tlast : std_logic;
signal rx_axis_mac_tuser : std_logic;
-- MAC transmitter client I/F
signal tx_axis_mac_tdata : std_logic_vector(7 downto 0);
signal tx_axis_mac_tvalid : std_logic;
signal tx_axis_mac_tready : std_logic;
signal tx_axis_mac_tlast : std_logic;
signal tx_axis_mac_tuser : std_logic;
-- Note: KEEP attributes preserve signal names so they can be displayed in
-- simulator wave windows
-- attribute keep : string;
-- attribute keep of rx_axis_mac_tdata : signal is "true";
-- attribute keep of rx_axis_mac_tvalid : signal is "true";
-- attribute keep of rx_axis_mac_tlast : signal is "true";
-- attribute keep of rx_axis_mac_tuser : signal is "true";
-- attribute keep of tx_axis_mac_tdata : signal is "true";
-- attribute keep of tx_axis_mac_tvalid : signal is "true";
-- attribute keep of tx_axis_mac_tready : signal is "true";
-- attribute keep of tx_axis_mac_tlast : signal is "true";
-- attribute keep of tx_axis_mac_tuser : signal is "true";
begin
------------------------------------------------------------------------------
-- Connect the output clock signals
------------------------------------------------------------------------------
rx_reset <= rx_reset_int;
tx_reset <= tx_reset_int;
------------------------------------------------------------------------------
-- Instantiate the Tri-Mode EMAC Block wrapper
------------------------------------------------------------------------------
trimac_block : temac_10_100_1000_block
port map(
gtx_clk => gtx_clk,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Client Receiver Interface
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
rx_reset => rx_reset_int,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
-- Client Transmitter Interface
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
tx_reset => tx_reset_int,
tx_axis_mac_tdata => tx_axis_mac_tdata ,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_axis_mac_tready => tx_axis_mac_tready,
-- Flow Control
pause_req => pause_req,
pause_val => pause_val,
clk_enable => clk_enable,
speedis100 => speedis100,
speedis10100 => speedis10100,
-- GMII Interface
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
-- Configuration Vector
rx_configuration_vector => rx_configuration_vector,
tx_configuration_vector => tx_configuration_vector
);
------------------------------------------------------------------------------
-- Instantiate the user side FIFO
------------------------------------------------------------------------------
-- locally reset sync the mac generated resets - the resets are already fully sync
-- so adding a reset sync shouldn't change that
rx_mac_reset_gen : temac_10_100_1000_reset_sync
port map (
clk => gtx_clk,
enable => '1',
reset_in => rx_reset_int,
reset_out => rx_mac_reset
);
tx_mac_reset_gen : temac_10_100_1000_reset_sync
port map (
clk => gtx_clk,
enable => '1',
reset_in => tx_reset_int,
reset_out => tx_mac_reset
);
-- create inverted mac resets as the FIFO expects AXI compliant resets
tx_mac_resetn <= not tx_mac_reset;
rx_mac_resetn <= not rx_mac_reset;
user_side_FIFO : temac_10_100_1000_ten_100_1g_eth_fifo
generic map(
FULL_DUPLEX_ONLY => true
)
port map(
-- Transmit FIFO MAC TX Interface
tx_fifo_aclk => tx_fifo_clock,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_mac_aclk => gtx_clk,
tx_mac_resetn => tx_mac_resetn,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_fifo_overflow => open,
tx_fifo_status => open,
tx_collision => '0',
tx_retransmit => '0',
rx_fifo_aclk => rx_fifo_clock,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_mac_aclk => gtx_clk,
rx_mac_resetn => rx_mac_resetn,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tready => open, -- not used as MAC cannot throttle
rx_axis_mac_tuser => rx_axis_mac_tuser,
rx_fifo_status => open,
rx_fifo_overflow => open
);
end wrapper;
|
entity tc16 is
end;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tc16 is
signal clk : std_logic;
signal tg : std_logic;
begin
process (clk) is
begin
if ?? tg and falling_edge(clk) then
null;
end if;
end process;
end behav;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:clock_splitter:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_clock_splitter_0_0 IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END system_clock_splitter_0_0;
ARCHITECTURE system_clock_splitter_0_0_arch OF system_clock_splitter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT clock_splitter IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END COMPONENT clock_splitter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "clock_splitter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_clock_splitter_0_0_arch : ARCHITECTURE IS "system_clock_splitter_0_0,clock_splitter,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "system_clock_splitter_0_0,clock_splitter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=clock_splitter,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : clock_splitter
PORT MAP (
clk_in => clk_in,
latch_edge => latch_edge,
clk_out => clk_out
);
END system_clock_splitter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:clock_splitter:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_clock_splitter_0_0 IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END system_clock_splitter_0_0;
ARCHITECTURE system_clock_splitter_0_0_arch OF system_clock_splitter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT clock_splitter IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END COMPONENT clock_splitter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "clock_splitter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_clock_splitter_0_0_arch : ARCHITECTURE IS "system_clock_splitter_0_0,clock_splitter,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "system_clock_splitter_0_0,clock_splitter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=clock_splitter,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : clock_splitter
PORT MAP (
clk_in => clk_in,
latch_edge => latch_edge,
clk_out => clk_out
);
END system_clock_splitter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:clock_splitter:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_clock_splitter_0_0 IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END system_clock_splitter_0_0;
ARCHITECTURE system_clock_splitter_0_0_arch OF system_clock_splitter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT clock_splitter IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END COMPONENT clock_splitter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "clock_splitter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_clock_splitter_0_0_arch : ARCHITECTURE IS "system_clock_splitter_0_0,clock_splitter,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "system_clock_splitter_0_0,clock_splitter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=clock_splitter,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : clock_splitter
PORT MAP (
clk_in => clk_in,
latch_edge => latch_edge,
clk_out => clk_out
);
END system_clock_splitter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:clock_splitter:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_clock_splitter_0_0 IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END system_clock_splitter_0_0;
ARCHITECTURE system_clock_splitter_0_0_arch OF system_clock_splitter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT clock_splitter IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END COMPONENT clock_splitter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "clock_splitter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_clock_splitter_0_0_arch : ARCHITECTURE IS "system_clock_splitter_0_0,clock_splitter,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "system_clock_splitter_0_0,clock_splitter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=clock_splitter,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : clock_splitter
PORT MAP (
clk_in => clk_in,
latch_edge => latch_edge,
clk_out => clk_out
);
END system_clock_splitter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:clock_splitter:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_clock_splitter_0_0 IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END system_clock_splitter_0_0;
ARCHITECTURE system_clock_splitter_0_0_arch OF system_clock_splitter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT clock_splitter IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END COMPONENT clock_splitter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "clock_splitter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_clock_splitter_0_0_arch : ARCHITECTURE IS "system_clock_splitter_0_0,clock_splitter,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "system_clock_splitter_0_0,clock_splitter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=clock_splitter,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : clock_splitter
PORT MAP (
clk_in => clk_in,
latch_edge => latch_edge,
clk_out => clk_out
);
END system_clock_splitter_0_0_arch;
|
-------------------------------------------------------------------------------
-- system_mb_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05_a.all;
entity system_mb_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 1);
MPLB_Rst : out std_logic_vector(0 to 6);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 223);
M_UABus : in std_logic_vector(0 to 223);
M_BE : in std_logic_vector(0 to 55);
M_RNW : in std_logic_vector(0 to 6);
M_abort : in std_logic_vector(0 to 6);
M_busLock : in std_logic_vector(0 to 6);
M_TAttribute : in std_logic_vector(0 to 111);
M_lockErr : in std_logic_vector(0 to 6);
M_MSize : in std_logic_vector(0 to 13);
M_priority : in std_logic_vector(0 to 13);
M_rdBurst : in std_logic_vector(0 to 6);
M_request : in std_logic_vector(0 to 6);
M_size : in std_logic_vector(0 to 27);
M_type : in std_logic_vector(0 to 20);
M_wrBurst : in std_logic_vector(0 to 6);
M_wrDBus : in std_logic_vector(0 to 447);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 13);
Sl_MWrErr : in std_logic_vector(0 to 13);
Sl_MBusy : in std_logic_vector(0 to 13);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_SSize : in std_logic_vector(0 to 3);
Sl_wait : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 13);
PLB_MIRQ : out std_logic_vector(0 to 6);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 6);
PLB_MTimeout : out std_logic_vector(0 to 6);
PLB_MBusy : out std_logic_vector(0 to 6);
PLB_MRdErr : out std_logic_vector(0 to 6);
PLB_MWrErr : out std_logic_vector(0 to 6);
PLB_MRdBTerm : out std_logic_vector(0 to 6);
PLB_MRdDAck : out std_logic_vector(0 to 6);
PLB_MRdDBus : out std_logic_vector(0 to 447);
PLB_MRdWdAddr : out std_logic_vector(0 to 27);
PLB_MRearbitrate : out std_logic_vector(0 to 6);
PLB_MWrBTerm : out std_logic_vector(0 to 6);
PLB_MWrDAck : out std_logic_vector(0 to 6);
PLB_MSSize : out std_logic_vector(0 to 13);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 2);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic_vector(0 to 1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 6);
PLB_SMWrErr : out std_logic_vector(0 to 6);
PLB_SMBusy : out std_logic_vector(0 to 6);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end system_mb_plb_wrapper;
architecture STRUCTURE of system_mb_plb_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
mb_plb : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 7,
C_PLBV46_NUM_SLAVES => 2,
C_PLBV46_MID_WIDTH => 3,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 64,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief 8-bits memory block with the generic data size parameter.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
entity sram8_inferred is
generic (
abits : integer := 12;
byte_idx : integer := 0
);
port (
clk : in std_ulogic;
address : in std_logic_vector(abits-1 downto 0);
rdata : out std_logic_vector(7 downto 0);
we : in std_logic;
wdata : in std_logic_vector(7 downto 0)
);
end;
architecture arch_sram8_inferred of sram8_inferred is
constant SRAM_LENGTH : integer := 2**abits;
type ram_type is array (0 to SRAM_LENGTH-1) of std_logic_vector(7 downto 0);
signal ram : ram_type;
signal adr : std_logic_vector(abits-1 downto 0);
begin
reg : process (clk, address, wdata) begin
if rising_edge(clk) then
if we = '1' then
ram(conv_integer(address)) <= wdata;
end if;
adr <= address;
end if;
end process;
rdata <= ram(conv_integer(adr));
end;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief 8-bits memory block with the generic data size parameter.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
entity sram8_inferred is
generic (
abits : integer := 12;
byte_idx : integer := 0
);
port (
clk : in std_ulogic;
address : in std_logic_vector(abits-1 downto 0);
rdata : out std_logic_vector(7 downto 0);
we : in std_logic;
wdata : in std_logic_vector(7 downto 0)
);
end;
architecture arch_sram8_inferred of sram8_inferred is
constant SRAM_LENGTH : integer := 2**abits;
type ram_type is array (0 to SRAM_LENGTH-1) of std_logic_vector(7 downto 0);
signal ram : ram_type;
signal adr : std_logic_vector(abits-1 downto 0);
begin
reg : process (clk, address, wdata) begin
if rising_edge(clk) then
if we = '1' then
ram(conv_integer(address)) <= wdata;
end if;
adr <= address;
end if;
end process;
rdata <= ram(conv_integer(adr));
end;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief 8-bits memory block with the generic data size parameter.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
entity sram8_inferred is
generic (
abits : integer := 12;
byte_idx : integer := 0
);
port (
clk : in std_ulogic;
address : in std_logic_vector(abits-1 downto 0);
rdata : out std_logic_vector(7 downto 0);
we : in std_logic;
wdata : in std_logic_vector(7 downto 0)
);
end;
architecture arch_sram8_inferred of sram8_inferred is
constant SRAM_LENGTH : integer := 2**abits;
type ram_type is array (0 to SRAM_LENGTH-1) of std_logic_vector(7 downto 0);
signal ram : ram_type;
signal adr : std_logic_vector(abits-1 downto 0);
begin
reg : process (clk, address, wdata) begin
if rising_edge(clk) then
if we = '1' then
ram(conv_integer(address)) <= wdata;
end if;
adr <= address;
end if;
end process;
rdata <= ram(conv_integer(adr));
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace_mmb
-- File: ahbtrace_mmb.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB trace unit that can have registers on a separate bus and
-- select between several trace buses.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
entity ahbtrace_mmb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
ahbfilt : integer := 0;
ntrace : integer range 1 to 8 := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmiv : in ahb_mst_in_vector_type(0 to ntrace-1); -- Trace
tahbsiv : in ahb_slv_in_vector_type(0 to ntrace-1)
);
end;
architecture rtl of ahbtrace_mmb is
constant TBUFABITS : integer := log2(kbytes) + 6;
constant TIMEBITS : integer := 32;
constant FILTEN : boolean := ahbfilt /= 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBTRACE, 0, 0, irq),
4 => ahb_iobar (ioaddr, iomask),
others => zero32);
type tracebuf_in_type is record
addr : std_logic_vector(TBUFABITS-1 downto 0);
data : std_logic_vector(127 downto 0);
enable : std_logic;
write : std_logic_vector(3 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(127 downto 0);
end record;
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
end record;
type regtype is record
thaddr : std_logic_vector(31 downto 0);
thwrite : std_logic;
thtrans : std_logic_vector(1 downto 0);
thsize : std_logic_vector(2 downto 0);
thburst : std_logic_vector(2 downto 0);
thmaster : std_logic_vector(3 downto 0);
thmastlock : std_logic;
ahbactive : std_logic;
timer : std_logic_vector(TIMEBITS-1 downto 0);
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
hready : std_logic;
hready2 : std_logic;
hready3 : std_logic;
hsel : std_logic;
hwrite : std_logic;
haddr : std_logic_vector(TBUFABITS+3 downto 2);
hrdata : std_logic_vector(31 downto 0);
regacc : std_logic;
enable : std_logic; -- trace enable
bahb : std_logic; -- break on AHB watchpoint hit
bhit : std_logic; -- breakpoint hit
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
end record;
type fregtype is record
shsel : std_logic_vector(0 to NAHBSLV-1);
af : std_ulogic; -- Address filtering
fr : std_ulogic; -- Filter reads
fw : std_ulogic; -- Filter writes
smask : std_logic_vector(15 downto 0);
mmask : std_logic_vector(15 downto 0);
rf : std_ulogic; -- Retry filtering
end record;
type bregtype is record
bsel : std_logic_vector(log2(ntrace) downto 0);
end record;
function ahb_filt_hit (
r : regtype;
rf : fregtype;
hresp : std_logic_vector(1 downto 0)) return boolean is
variable hit : boolean;
begin
-- filter hit -> inhibit
hit := false;
-- Filter on read/write
if ((rf.fw and r.thwrite) or (rf.fr and not r.thwrite)) = '1' then
hit := true;
end if;
-- Filter on address range
if (((r.tbreg2.addr xor r.thaddr(31 downto 2)) and r.tbreg2.mask) /= zero32(29 downto 0)) then
if rf.af = '1' then hit := true; end if;
end if;
-- Filter on master mask
for i in rf.mmask'range loop
if i > NAHBMST-1 then exit; end if;
if i = conv_integer(r.thmaster) and rf.mmask(i) = '1' then
hit := true;
end if;
end loop;
-- Filter on slave mask
for i in rf.smask'range loop
if i > NAHBSLV-1 then exit; end if;
if (rf.shsel(i) and rf.smask(i)) /= '0' then
hit := true;
end if;
end loop;
-- Filter on retry response
if (rf.rf = '1' and hresp = HRESP_RETRY) then
hit := true;
end if;
return hit;
end function ahb_filt_hit;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal enable : std_logic_vector(1 downto 0);
signal r, rin : regtype;
signal rf, rfin : fregtype;
signal rb, rbin : bregtype;
begin
ctrl : process(rst, ahbsi, tahbmiv, tahbsiv, r, rf, rb, tbo)
variable v : regtype;
variable vabufi : tracebuf_in_type;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable bphit : std_logic;
variable bufdata : std_logic_vector(127 downto 0);
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable tahbmi : ahb_mst_in_type;
variable tahbsi : ahb_slv_in_type;
variable vf : fregtype;
variable vb : bregtype;
variable regaddr : std_logic_vector(4 downto 2);
variable tbaddr : std_logic_vector(3 downto 2);
begin
v := r; regsd := (others => '0'); vabufi.enable := '0';
vabufi.data := (others => '0'); vabufi.addr := (others => '0');
vabufi.write := (others => '0'); bphit := '0';
v.hready := r.hready2; v.hready2 := r.hready3; v.hready3 := '0';
bufdata := tbo.data;
hirq := (others => '0'); hirq(irq) := r.bhit;
vf := rf; vb := rb;
if ntrace = 1 then
tahbmi := tahbmiv(0); tahbsi := tahbsiv(0);
else
tahbmi := tahbmiv(conv_integer(rb.bsel));
tahbsi := tahbsiv(conv_integer(rb.bsel));
end if;
regaddr := r.haddr(4 downto 2); tbaddr := r.haddr(3 downto 2);
-- trace buffer index and delay counters
if r.enable = '1' then v.timer := r.timer + 1; end if;
aindex := r.aindex + 1;
-- check for AHB watchpoints
if (tahbsi.hready and r.ahbactive ) = '1' then
if ((((r.tbreg1.addr xor r.thaddr(31 downto 2)) and r.tbreg1.mask) = zero32(29 downto 0)) and
(((r.tbreg1.read and not r.thwrite) or (r.tbreg1.write and r.thwrite)) = '1'))
or ((((r.tbreg2.addr xor r.thaddr(31 downto 2)) and r.tbreg2.mask) = zero32(29 downto 0)) and
(((r.tbreg2.read and not r.thwrite) or (r.tbreg2.write and r.thwrite)) = '1'))
then
if (r.enable = '1') and (r.dcnten = '0') and
(r.delaycnt /= zero32(TBUFABITS-1 downto 0))
then v.dcnten := '1'; bphit := '1';
--else bphit := '1'; v.enable := '0'; end if;
elsif (r.enable = '1') and (r.dcnten = '0') then bphit := '1'; v.enable := '0'; end if;
end if;
end if;
-- generate buffer inputs
vabufi.write := "0000";
if r.enable = '1' then
vabufi.addr(TBUFABITS-1 downto 0) := r.aindex;
vabufi.data(127 downto 96) := r.timer;
vabufi.data(95) := bphit;
vabufi.data(94 downto 80) := tahbmi.hirq(15 downto 1);
vabufi.data(79) := r.thwrite;
vabufi.data(78 downto 77) := r.thtrans;
vabufi.data(76 downto 74) := r.thsize;
vabufi.data(73 downto 71) := r.thburst;
vabufi.data(70 downto 67) := r.thmaster;
vabufi.data(66) := r.thmastlock;
vabufi.data(65 downto 64) := tahbmi.hresp;
if r.thwrite = '1' then
vabufi.data(63 downto 32) := tahbsi.hwdata(31 downto 0);
else
vabufi.data(63 downto 32) := tahbmi.hrdata(31 downto 0);
end if;
vabufi.data(31 downto 0) := r.thaddr;
else
vabufi.addr(TBUFABITS-1 downto 0) := r.haddr(TBUFABITS+3 downto 4);
vabufi.data := ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0) &
ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0);
end if;
-- write trace buffer
if r.enable = '1' then
if (r.ahbactive and tahbsi.hready) = '1' then
if not (FILTEN and ahb_filt_hit(r, rf, tahbmi.hresp)) then
v.aindex := aindex;
vabufi.enable := '1'; vabufi.write := "1111";
end if;
end if;
end if;
-- trace buffer delay counter handling
if (r.dcnten = '1') and (r.ahbactive and tahbsi.hready) = '1' then
if (r.delaycnt = zero32(TBUFABITS-1 downto 0)) then
v.enable := '0'; v.dcnten := '0';
end if;
v.delaycnt := r.delaycnt - 1;
end if;
-- save AHB transfer parameters
if (tahbsi.hready = '1' ) then
v.thaddr := tahbsi.haddr; v.thwrite := tahbsi.hwrite; v.thtrans := tahbsi.htrans;
v.thsize := tahbsi.hsize; v.thburst := tahbsi.hburst;
v.thmaster := tahbsi.hmaster; v.thmastlock := tahbsi.hmastlock;
v.ahbactive := tahbsi.htrans(1);
if FILTEN then vf.shsel := tahbsi.hsel; end if;
end if;
-- AHB transfer parameters for register accesses
if (ahbsi.hready = '1' ) then
v.haddr := ahbsi.haddr(TBUFABITS+3 downto 2); v.hwrite := ahbsi.hwrite;
v.regacc := ahbsi.haddr(16);
v.hsel := ahbsi.htrans(1) and ahbsi.hsel(hindex);
end if;
-- AHB slave access to DSU registers and trace buffers
if (r.hsel and not r.hready) = '1' then
if r.regacc = '0' then -- registers
v.hready := '1';
case regaddr is
when "000" =>
regsd((TBUFABITS + 15) downto 16) := r.delaycnt;
if ntrace /= 1 then
regsd(15) := '1';
regsd(log2(ntrace)+12 downto 12) := vb.bsel;
end if;
if FILTEN then
regsd(5) := rf.rf;
regsd(4) := rf.af;
regsd(3) := rf.fr;
regsd(2) := rf.fw;
end if;
regsd(1 downto 0) := r.dcnten & r.enable;
if r.hwrite = '1' then
v.delaycnt := ahbsi.hwdata((TBUFABITS+ 15) downto 16);
if ntrace /= 1 then
vb.bsel := ahbsi.hwdata(log2(ntrace)+12 downto 12);
end if;
if FILTEN then
vf.rf := ahbsi.hwdata(5);
vf.af := ahbsi.hwdata(4);
vf.fr := ahbsi.hwdata(3);
vf.fw := ahbsi.hwdata(2);
end if;
v.dcnten := ahbsi.hwdata(1);
v.enable := ahbsi.hwdata(0);
end if;
when "001" =>
regsd((TBUFABITS - 1 + 4) downto 4) := r.aindex;
if r.hwrite = '1' then
v.aindex := ahbsi.hwdata((TBUFABITS- 1) downto 0);
end if;
when "010" =>
regsd((TIMEBITS - 1) downto 0) := r.timer;
if r.hwrite = '1' then
v.timer := ahbsi.hwdata((TIMEBITS- 1) downto 0);
end if;
when "011" =>
if FILTEN then
regsd(31 downto 0) := rf.smask & rf.mmask;
if r.hwrite = '1' then
vf.smask := ahbsi.hwdata(31 downto 16);
vf.mmask := ahbsi.hwdata(15 downto 0);
end if;
end if;
when "100" =>
regsd(31 downto 2) := r.tbreg1.addr;
if r.hwrite = '1' then
v.tbreg1.addr := ahbsi.hwdata(31 downto 2);
end if;
when "101" =>
regsd := r.tbreg1.mask & r.tbreg1.read & r.tbreg1.write;
if r.hwrite = '1' then
v.tbreg1.mask := ahbsi.hwdata(31 downto 2);
v.tbreg1.read := ahbsi.hwdata(1);
v.tbreg1.write := ahbsi.hwdata(0);
end if;
when "110" =>
regsd(31 downto 2) := r.tbreg2.addr;
if r.hwrite = '1' then
v.tbreg2.addr := ahbsi.hwdata(31 downto 2);
end if;
when others =>
regsd := r.tbreg2.mask & r.tbreg2.read & r.tbreg2.write;
if r.hwrite = '1' then
v.tbreg2.mask := ahbsi.hwdata(31 downto 2);
v.tbreg2.read := ahbsi.hwdata(1);
v.tbreg2.write := ahbsi.hwdata(0);
end if;
end case;
v.hrdata := regsd;
else -- read/write access to trace buffer
if r.hwrite = '1' then v.hready := '1'; else v.hready2 := not (r.hready2 or r.hready); end if;
vabufi.enable := not r.enable;
bufdata := tbo.data;
case tbaddr is
when "00" =>
v.hrdata := bufdata(127 downto 96);
if r.hwrite = '1' then
vabufi.write(3) := vabufi.enable;
end if;
when "01" =>
v.hrdata := bufdata(95 downto 64);
if r.hwrite = '1' then
vabufi.write(2) := vabufi.enable;
end if;
when "10" =>
v.hrdata := bufdata(63 downto 32);
if r.hwrite = '1' then
vabufi.write(1) := vabufi.enable;
end if;
when others =>
v.hrdata := bufdata(31 downto 0);
if r.hwrite = '1' then
vabufi.write(0) := vabufi.enable;
end if;
end case;
end if;
end if;
if ((ahbsi.hsel(hindex) and ahbsi.hready) = '1') and
((ahbsi.htrans = HTRANS_BUSY) or (ahbsi.htrans = HTRANS_IDLE))
then v.hready := '1'; end if;
if rst = '0' then
v.ahbactive := '0'; v.enable := '0'; v.timer := (others => '0');
v.hsel := '0'; v.dcnten := '0'; v.bhit := '0';
v.regacc := '0'; v.hready := '1';
v.tbreg1.read := '0'; v.tbreg1.write := '0';
v.tbreg2.read := '0'; v.tbreg2.write := '0';
if FILTEN then
vf.smask := (others => '0'); vf.mmask := (others => '0');
end if;
if ntrace /= 1 then vb.bsel := (others => '0'); end if;
end if;
tbi <= vabufi;
rin <= v; rfin <= vf; rbin <= vb;
ahbso.hconfig <= hconfig;
ahbso.hirq <= hirq;
ahbso.hsplit <= (others => '0');
ahbso.hrdata <= ahbdrivedata(r.hrdata);
ahbso.hready <= r.hready;
ahbso.hindex <= hindex;
end process;
ahbso.hresp <= HRESP_OKAY;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
fregs : if FILTEN generate
regs : process(clk)
begin if rising_edge(clk) then rf <= rfin; end if; end process;
end generate;
nofregs : if not FILTEN generate
rf.shsel <= (others => '0');
rf.af <= '0';
rf.fr <= '0';
rf.fw <= '0';
rf.smask <= (others => '0');
rf.mmask <= (others => '0');
rf.rf <= '0';
end generate;
bregs : if ntrace /= 1 generate
regs : process(clk)
begin if rising_edge(clk) then rb <= rbin; end if; end process;
end generate;
nobregs : if ntrace = 1 generate
rb.bsel <= (others => '0');
end generate;
enable <= tbi.enable & tbi.enable;
mem0 : for i in 0 to 1 generate
ram0 : syncram64 generic map (tech => tech, abits => TBUFABITS)
port map (clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data(((i*64)+63) downto (i*64)),
tbo.data(((i*64)+63) downto (i*64)), enable, tbi.write(i*2+1 downto i*2));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbtrace" & tost(hindex) &
": AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
|
--Part of Mano Basic Computer
--Behzad Mokhtari; [email protected]
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--Multipelexer
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity Multiplexer is
generic(N: integer:=3);
port(
Q: out std_logic;
E: in std_logic:= '1';
S: in std_logic_vector(n-1 downto 0);
I: in std_logic_vector(2**n-1 downto 0)
);
end Multiplexer;
architecture Structure of Multiplexer is
signal ou: std_logic_vector(1 downto 0);
component multiplexerBasic is
port(
Q: out std_logic;
E: in std_logic;
S: in std_logic;
I: in std_logic_vector(1 downto 0)
);
end component;
component Multiplexer is
generic(N: integer:=3);
port(
Q: out std_logic;
E: in std_logic;
S: in std_logic_vector(n-1 downto 0);
I: in std_logic_vector(2**n-1 downto 0)
);
end component;
begin
mul0: multiplexerBasic port map(I=>ou, S=>S(n-1), E=>E, Q=>Q);
cond: if n = 1 generate
ou <= I;
end generate cond;
Build: if n>1 generate
mulN0:component Multiplexer
generic map(N=>n-1)
port map(I=>I(2**(n-1)-1 downto 0), E=>E, S=>S(n-2 downto 0), Q=>ou(0));
mulN1:component Multiplexer
generic map(N=>n-1)
port map(I=>I(2**n-1 downto 2**(n-1)), E=>E, S=>S(n-2 downto 0), Q=>ou(1));
end generate Build;
end Structure; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testcase1 is
port (
sel : in unsigned(1 downto 0);
det : out std_logic
);
end testcase1;
architecture behavior of testcase1 is
begin
tc: process(sel)
begin
case to_integer(sel) is
when 0 to 1 =>
det <= '0';
when others =>
det <= '1';
end case;
end process;
end behavior;
|
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`protect end_protected
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: memoria_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY memoria_tb IS
END ENTITY;
ARCHITECTURE memoria_tb_ARCH OF memoria_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
memoria_synth_inst:ENTITY work.memoria_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: memoria_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY memoria_tb IS
END ENTITY;
ARCHITECTURE memoria_tb_ARCH OF memoria_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
memoria_synth_inst:ENTITY work.memoria_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCAM_Cell is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
cell_search_bit : in STD_LOGIC;
cell_dont_care_bit : in STD_LOGIC;
cell_match_bit_in : in STD_LOGIC ;
cell_match_bit_out : out STD_LOGIC);
end BCAM_Cell;
architecture Behavioral of BCAM_Cell is
signal FF: STD_LOGIC;
begin
process(clk, rst, we, cell_search_bit, cell_dont_care_bit, cell_match_bit_in)
begin
--reset data most important
if rst = '1' then
FF <= '0';
cell_match_bit_out <= '0';
-- write data from search
elsif we = '1' then
FF <= cell_search_bit;
cell_match_bit_out <= '0';
--search
--previous result is wrong therefore nothing matches
elsif cell_match_bit_in = '0' then
cell_match_bit_out <= '0';
--previous result matches
elsif cell_match_bit_in = '1' then
--check current cell if match
if FF = cell_search_bit then
cell_match_bit_out <= '1';
else
--current cell doesnt match
cell_match_bit_out <= '0';
end if;
end if;
end process;
end Behavioral ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Entity signextend is
Port (
clk : in std_logic;
in16 : in std_logic_vector(15 downto 0);
out32 : out std_logic_vector(31 downto 0)
);
End;
Architecture RTL of signextend is
begin
process (clk) begin
if rising_edge(clk) then
if in16(15)='0' then
out32 <= X"0000" & in16;
else
out32 <= X"ffff" & in16;
end if;
end if;
end process;
end RTL;
|
-------------------------------------------------------------------------------
-- axi_vdma_regdirect
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_regdirect.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_regdirect is
generic(
C_NUM_REGISTERS : integer := 6 ;
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
C_GENLOCK_MODE : integer range 0 to 3 := 0 ;
-----------------------------------------------------------------------
C_DYNAMIC_RESOLUTION : integer range 0 to 1 := 1 ;
-- Run time configuration of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 0 = Halt VDMA before writing new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 1 = Run time register configuration for new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE.
-----------------------------------------------------------------------
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
run_stop : in std_logic ; --
dmasr_halt : in std_logic ; --
stop : in std_logic ; --
--
reg_index : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
-- Register Direct Support --
prmtr_updt_complete : out std_logic ; --
regdir_idle : out std_logic ; --
--
-- Register Direct Mode Video Parameter In --
reg_module_vsize : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : out std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_strid : out std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : out std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_strt_addr : out STARTADDR_ARRAY_TYPE --
(0 to C_NUM_FSTORES - 1) ; --
reg_module_start_address1 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address2 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address3 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address4 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address5 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address6 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address7 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address8 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address9 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address10 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address11 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address12 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address13 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address14 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address15 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address16 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address17 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address18 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address19 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address20 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address21 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address22 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address23 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address24 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address25 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address26 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address27 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address28 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address29 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address30 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address31 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address32 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_regdirect;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_regdirect is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant VSYNC_INDEX : integer := 0; -- VSYNC Register index
constant HSYNC_INDEX : integer := 1; -- HSYNC Register index
constant DLY_STRIDE_INDEX : integer := 2; -- STRIDE/DLY Reg index
--constant RESERVED_INDEX3 : integer := 3; -- Reserved
constant STARTADDR1_INDEX : integer := 3; -- Start Address 1 Reg index
constant STARTADDR2_INDEX : integer := 4; -- Start Address 2 Reg index
constant STARTADDR3_INDEX : integer := 5; -- Start Address 3 Reg index
constant STARTADDR4_INDEX : integer := 6; -- Start Address 3 Reg index
constant STARTADDR5_INDEX : integer := 7; -- Start Address 3 Reg index
constant STARTADDR6_INDEX : integer := 8; -- Start Address 3 Reg index
constant STARTADDR7_INDEX : integer := 9; -- Start Address 3 Reg index
constant STARTADDR8_INDEX : integer := 10; -- Start Address 3 Reg index
constant STARTADDR9_INDEX : integer := 11; -- Start Address 3 Reg index
constant STARTADDR10_INDEX : integer := 12; -- Start Address 3 Reg index
constant STARTADDR11_INDEX : integer := 13; -- Start Address 3 Reg index
constant STARTADDR12_INDEX : integer := 14; -- Start Address 3 Reg index
constant STARTADDR13_INDEX : integer := 15; -- Start Address 3 Reg index
constant STARTADDR14_INDEX : integer := 16; -- Start Address 3 Reg index
constant STARTADDR15_INDEX : integer := 17; -- Start Address 3 Reg index
constant STARTADDR16_INDEX : integer := 18; -- Start Address 3 Reg index
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal prmtr_updt_complete_i : std_logic := '0';
signal reg_config_locked_i : std_logic := '0';
signal regdir_idle_i : std_logic := '0';
signal run_stop_d1 : std_logic := '0';
signal run_stop_re : std_logic := '0';
--signal reg_module_strt_addr_i : STARTADDR_ARRAY_TYPE(0 to MAX_FSTORES-1);
signal reg_module_start_address1_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address2_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address3_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address4_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address5_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address6_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address7_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address8_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address9_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address10_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address11_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address12_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address13_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address14_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address15_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address16_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address17_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address18_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address19_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address20_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address21_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address22_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address23_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address24_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address25_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address26_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address27_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address28_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address29_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address30_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address31_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address32_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Register DMACR RunStop bit to create a RE pulse
REG_RUN_RE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
run_stop_d1 <= '0';
else
run_stop_d1 <= run_stop;
end if;
end if;
end process REG_RUN_RE;
run_stop_re <= run_stop and not run_stop_d1;
-- Gen register direct idle flag to indicate when not idle.
-- Flag is asserted to NOT idle at start of run and to Idle
-- on reset, halt, or stop (i.e. error)
-- This is used to generate first fsync in free run mode.
REG_IDLE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or stop = '1')then
regdir_idle_i <= '1';
elsif(run_stop_re = '1')then
regdir_idle_i <= '0';
elsif(prmtr_updt_complete_i = '1')then
regdir_idle_i <= '1';
end if;
end if;
end process REG_IDLE;
regdir_idle <= regdir_idle_i;
-- Vertical Size Register
VSIZE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_vsize <= (others => '0');
elsif(axi2ip_wrce(VSYNC_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_vsize <= axi2ip_wrdata(VSIZE_DWIDTH-1 downto 0);
end if;
end if;
end process VSIZE_REGISTER;
VIDEO_PRMTR_UPDATE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or run_stop = '0')then
prmtr_updt_complete_i <= '0';
elsif(axi2ip_wrce(VSYNC_INDEX) = '1' and reg_config_locked_i = '0')then
prmtr_updt_complete_i <= '1';
else
prmtr_updt_complete_i <= '0';
end if;
end if;
end process VIDEO_PRMTR_UPDATE;
prmtr_updt_complete <= prmtr_updt_complete_i;
-- Horizontal Size Register
HSIZE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_hsize <= (others => '0');
elsif(axi2ip_wrce(HSYNC_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_hsize <= axi2ip_wrdata(HSIZE_DWIDTH-1 downto 0);
end if;
end if;
end process HSIZE_REGISTER;
-- Delay/Stride Register
--Genlock Slave mode
S_GEN_DLYSTRIDE_REGISTER : if C_GENLOCK_MODE = 1 generate
begin
S_DLYSTRIDE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
--reg_module_frmdly <= (others => '0');
reg_module_frmdly <= "00001"; --CR 709007
reg_module_strid <= (others => '0');
elsif(axi2ip_wrce(DLY_STRIDE_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_frmdly <= axi2ip_wrdata(FRMDLY_MSB downto FRMDLY_LSB);
reg_module_strid <= axi2ip_wrdata(STRIDE_DWIDTH-1 downto 0);
end if;
end if;
end process S_DLYSTRIDE_REGISTER;
end generate S_GEN_DLYSTRIDE_REGISTER;
--Genlock Master mode
M_GEN_DLYSTRIDE_REGISTER : if C_GENLOCK_MODE = 0 generate
begin
reg_module_frmdly <= (others => '0');
M_DLYSTRIDE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_strid <= (others => '0');
elsif(axi2ip_wrce(DLY_STRIDE_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_strid <= axi2ip_wrdata(STRIDE_DWIDTH-1 downto 0);
end if;
end if;
end process M_DLYSTRIDE_REGISTER;
end generate M_GEN_DLYSTRIDE_REGISTER;
--Dynamic Genlock Master mode
DM_GEN_DLYSTRIDE_REGISTER : if C_GENLOCK_MODE = 2 generate
begin
reg_module_frmdly <= (others => '0');
DM_DLYSTRIDE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_strid <= (others => '0');
elsif(axi2ip_wrce(DLY_STRIDE_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_strid <= axi2ip_wrdata(STRIDE_DWIDTH-1 downto 0);
end if;
end if;
end process DM_DLYSTRIDE_REGISTER;
end generate DM_GEN_DLYSTRIDE_REGISTER;
--Dynamic Genlock Slave mode
DS_GEN_DLYSTRIDE_REGISTER : if C_GENLOCK_MODE = 3 generate
begin
reg_module_frmdly <= (others => '0');
DS_DLYSTRIDE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_strid <= (others => '0');
elsif(axi2ip_wrce(DLY_STRIDE_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_strid <= axi2ip_wrdata(STRIDE_DWIDTH-1 downto 0);
end if;
end if;
end process DS_DLYSTRIDE_REGISTER;
end generate DS_GEN_DLYSTRIDE_REGISTER;
--No Dynamic resolution
GEN_REG_CONFIG_LOCK_BIT : if C_DYNAMIC_RESOLUTION = 0 generate
begin
REG_CONFIG_LOCKED : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
reg_config_locked_i <= '0';
elsif(axi2ip_wrce(VSYNC_INDEX) = '1')then
reg_config_locked_i <= '1';
end if;
end if;
end process REG_CONFIG_LOCKED;
end generate GEN_REG_CONFIG_LOCK_BIT;
--Dynamic resolution
GEN_NO_REG_CONFIG_LOCK_BIT : if C_DYNAMIC_RESOLUTION = 1 generate
begin
reg_config_locked_i <= '0';
end generate GEN_NO_REG_CONFIG_LOCK_BIT;
--*****************************************************************************
--** START ADDRESS REGISTERS
--*****************************************************************************
-- Generate C_NUM_FSTORE start address registeres
--GEN_START_ADDR_REG : for i in 1 to MAX_FSTORES generate
----signal j : integer := 1;
--
--begin
----j<= i;
--
-- -- Start Address Registers
-- START_ADDR : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_strt_addr_i(i-1) <= (others => '0');
-- -- Write to appropriate Start Address
--
-- elsif(i>= C_NUM_FSTORES)then
-- reg_module_strt_addr_i(i-1) <= (others => '0');
--
--
-- elsif(i<C_NUM_FSTORES and axi2ip_wrce(i+2) = '1'and C_NUM_FSTORES <17)then
-- reg_module_strt_addr_i(i-1) <= axi2ip_wrdata;
-- elsif(i<C_NUM_FSTORES and C_NUM_FSTORES >=17 and j<17 and axi2ip_wrce(i+2) = '1' and reg_index(0) = '0')then
-- --if(i<17 and axi2ip_wrce(i+2) = '1')then
-- --if(reg_index(0) = '0')then
-- reg_module_strt_addr_i(i-1) <= axi2ip_wrdata;
-- --elsif(reg_index(0) = '1')then
-- elsif(i<C_NUM_FSTORES and C_NUM_FSTORES >=17 and j<17 and axi2ip_wrce(i+2) = '1' and reg_index(0) = '1')then
-- reg_module_strt_addr_i(i+15) <= axi2ip_wrdata;
-- --end if;
-- --elsif(i>=17 and axi2ip_wrce(i-14) = '1')then
-- elsif(i<C_NUM_FSTORES and C_NUM_FSTORES >=17 and j>=17 and axi2ip_wrce(i-14) = '1' and reg_index(0) = '0')then
-- --if(reg_index(0) = '0')then
-- reg_module_strt_addr_i(i-17) <= axi2ip_wrdata;
-- --elsif(reg_index(0) = '1')then
-- elsif(i<C_NUM_FSTORES and C_NUM_FSTORES >=17 and j>=17 and axi2ip_wrce(i-14) = '1' and reg_index(0) = '1')then
-- reg_module_strt_addr_i(i-1) <= axi2ip_wrdata;
-- --end if;
-- --end if;
-- -- For frames greater than fstores the vectors are reserved
-- -- and set to zero
-- end if;
-- end if;
-- end process START_ADDR;
--end generate GEN_START_ADDR_REG;
-- Map only C_NUM_FSTORE vectors to output port
-- Number of Fstores Generate
GEN_NUM_FSTORES_1 : if C_NUM_FSTORES = 1 generate
-- Start Address Register
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
reg_module_start_address2_i <= (others => '0');
reg_module_start_address3_i <= (others => '0');
reg_module_start_address4_i <= (others => '0');
reg_module_start_address5_i <= (others => '0');
reg_module_start_address6_i <= (others => '0');
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_1;
-- Number of Fstores Generate
GEN_NUM_FSTORES_2 : if C_NUM_FSTORES = 2 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
reg_module_start_address3_i <= (others => '0');
reg_module_start_address4_i <= (others => '0');
reg_module_start_address5_i <= (others => '0');
reg_module_start_address6_i <= (others => '0');
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_2;
-- Number of Fstores Generate
GEN_NUM_FSTORES_3 : if C_NUM_FSTORES = 3 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
reg_module_start_address4_i <= (others => '0');
reg_module_start_address5_i <= (others => '0');
reg_module_start_address6_i <= (others => '0');
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_3;
-- Number of Fstores Generate
GEN_NUM_FSTORES_4 : if C_NUM_FSTORES = 4 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
reg_module_start_address5_i <= (others => '0');
reg_module_start_address6_i <= (others => '0');
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_4;
-- Number of Fstores Generate
GEN_NUM_FSTORES_5 : if C_NUM_FSTORES = 5 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
reg_module_start_address6_i <= (others => '0');
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_5;
-- Number of Fstores Generate
GEN_NUM_FSTORES_6 : if C_NUM_FSTORES = 6 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_6;
-- Number of Fstores Generate
GEN_NUM_FSTORES_7 : if C_NUM_FSTORES = 7 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_7;
-- Number of Fstores Generate
GEN_NUM_FSTORES_8 : if C_NUM_FSTORES = 8 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_8;
-- Number of Fstores Generate
GEN_NUM_FSTORES_9 : if C_NUM_FSTORES = 9 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_9;
-- Number of Fstores Generate
GEN_NUM_FSTORES_10 : if C_NUM_FSTORES = 10 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_10;
-- Number of Fstores Generate
GEN_NUM_FSTORES_11 : if C_NUM_FSTORES = 11 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_11;
-- Number of Fstores Generate
GEN_NUM_FSTORES_12 : if C_NUM_FSTORES = 12 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_12;
-- Number of Fstores Generate
GEN_NUM_FSTORES_13 : if C_NUM_FSTORES = 13 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_13;
-- Number of Fstores Generate
GEN_NUM_FSTORES_14 : if C_NUM_FSTORES = 14 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_14;
-- Number of Fstores Generate
GEN_NUM_FSTORES_15 : if C_NUM_FSTORES = 15 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_15;
-- Number of Fstores Generate
GEN_NUM_FSTORES_16 : if C_NUM_FSTORES = 16 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_16;
-- Number of Fstores Generate
GEN_NUM_FSTORES_17 : if C_NUM_FSTORES = 17 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_17;
-- Number of Fstores Generate
GEN_NUM_FSTORES_18 : if C_NUM_FSTORES = 18 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_18;
-- Number of Fstores Generate
GEN_NUM_FSTORES_19 : if C_NUM_FSTORES = 19 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_19;
-- Number of Fstores Generate
GEN_NUM_FSTORES_20 : if C_NUM_FSTORES = 20 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_20;
-- Number of Fstores Generate
GEN_NUM_FSTORES_21 : if C_NUM_FSTORES = 21 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_21;
-- Number of Fstores Generate
GEN_NUM_FSTORES_22 : if C_NUM_FSTORES = 22 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_22;
-- Number of Fstores Generate
GEN_NUM_FSTORES_23 : if C_NUM_FSTORES = 23 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_23;
-- Number of Fstores Generate
GEN_NUM_FSTORES_24 : if C_NUM_FSTORES = 24 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_24;
-- Number of Fstores Generate
GEN_NUM_FSTORES_25 : if C_NUM_FSTORES = 25 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_25;
-- Number of Fstores Generate
GEN_NUM_FSTORES_26 : if C_NUM_FSTORES = 26 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_26;
-- Number of Fstores Generate
GEN_NUM_FSTORES_27 : if C_NUM_FSTORES = 27 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_27;
-- Number of Fstores Generate
GEN_NUM_FSTORES_28 : if C_NUM_FSTORES = 28 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
--START_ADDR12 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address12_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address12_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
START_ADDR28 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address28_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR28;
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_28;
-- Number of Fstores Generate
GEN_NUM_FSTORES_29 : if C_NUM_FSTORES = 29 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
--START_ADDR12 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address12_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address12_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR12;
-- Start Address Register 13
--START_ADDR13 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address13_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address13_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
START_ADDR28 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address28_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR28;
START_ADDR29 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address29_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR29;
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_29;
-- Number of Fstores Generate
GEN_NUM_FSTORES_30 : if C_NUM_FSTORES = 30 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
--START_ADDR12 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address12_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address12_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR12;
-- Start Address Register 13
--START_ADDR13 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address13_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address13_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR13;
-- Start Address Register 14
--START_ADDR14 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address14_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address14_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
START_ADDR28 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address28_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR28;
START_ADDR29 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address29_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR29;
START_ADDR30 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address30_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR30;
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_30;
-- Number of Fstores Generate
GEN_NUM_FSTORES_31 : if C_NUM_FSTORES = 31 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
--START_ADDR12 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address12_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address12_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR12;
-- Start Address Register 13
--START_ADDR13 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address13_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address13_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR13;
-- Start Address Register 14
--START_ADDR14 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address14_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address14_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR14;
-- Start Address Register 15
--START_ADDR15 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address15_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address15_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
START_ADDR28 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address28_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR28;
START_ADDR29 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address29_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR29;
START_ADDR30 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address30_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR30;
START_ADDR31 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address15_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address31_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR31;
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_31;
-- Number of Fstores Generate
GEN_NUM_FSTORES_32 : if C_NUM_FSTORES = 32 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
--START_ADDR12 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address12_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address12_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR12;
-- Start Address Register 13
--START_ADDR13 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address13_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address13_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR13;
-- Start Address Register 14
--START_ADDR14 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address14_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address14_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR14;
-- Start Address Register 15
--START_ADDR15 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address15_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address15_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR15;
-- Start Address Register 16
--START_ADDR16 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address16_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address16_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
START_ADDR28 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address28_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR28;
START_ADDR29 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address29_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR29;
START_ADDR30 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address30_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR30;
START_ADDR31 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address15_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address31_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR31;
START_ADDR32 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address16_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address32_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR32;
end generate GEN_NUM_FSTORES_32;
-- Number of Fstores Generate
GEN_1 : if C_NUM_FSTORES = 1 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
end generate GEN_1;
-- Number of Fstores Generate
GEN_2 : if C_NUM_FSTORES = 2 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
end generate GEN_2;
-- Number of Fstores Generate
GEN_3 : if C_NUM_FSTORES = 3 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
end generate GEN_3;
-- Number of Fstores Generate
GEN_4 : if C_NUM_FSTORES = 4 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
end generate GEN_4;
-- Number of Fstores Generate
GEN_5 : if C_NUM_FSTORES = 5 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
end generate GEN_5;
-- Number of Fstores Generate
GEN_6 : if C_NUM_FSTORES = 6 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
end generate GEN_6;
-- Number of Fstores Generate
GEN_7 : if C_NUM_FSTORES = 7 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
end generate GEN_7;
-- Number of Fstores Generate
GEN_8 : if C_NUM_FSTORES = 8 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
end generate GEN_8;
-- Number of Fstores Generate
GEN_9 : if C_NUM_FSTORES = 9 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
end generate GEN_9;
-- Number of Fstores Generate
GEN_10 : if C_NUM_FSTORES = 10 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
end generate GEN_10;
-- Number of Fstores Generate
GEN_11 : if C_NUM_FSTORES = 11 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
end generate GEN_11;
-- Number of Fstores Generate
GEN_12 : if C_NUM_FSTORES = 12 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
end generate GEN_12;
-- Number of Fstores Generate
GEN_13 : if C_NUM_FSTORES = 13 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
end generate GEN_13;
-- Number of Fstores Generate
GEN_14 : if C_NUM_FSTORES = 14 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
end generate GEN_14;
-- Number of Fstores Generate
GEN_15 : if C_NUM_FSTORES = 15 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
end generate GEN_15;
-- Number of Fstores Generate
GEN_16 : if C_NUM_FSTORES = 16 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
end generate GEN_16;
-- Number of Fstores Generate
GEN_17 : if C_NUM_FSTORES = 17 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
end generate GEN_17;
-- Number of Fstores Generate
GEN_18 : if C_NUM_FSTORES = 18 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
end generate GEN_18;
-- Number of Fstores Generate
GEN_19 : if C_NUM_FSTORES = 19 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
end generate GEN_19;
-- Number of Fstores Generate
GEN_20 : if C_NUM_FSTORES = 20 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
end generate GEN_20;
-- Number of Fstores Generate
GEN_21 : if C_NUM_FSTORES = 21 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
end generate GEN_21;
-- Number of Fstores Generate
GEN_22 : if C_NUM_FSTORES = 22 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
end generate GEN_22;
-- Number of Fstores Generate
GEN_23 : if C_NUM_FSTORES = 23 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
end generate GEN_23;
-- Number of Fstores Generate
GEN_24 : if C_NUM_FSTORES = 24 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
end generate GEN_24;
-- Number of Fstores Generate
GEN_25 : if C_NUM_FSTORES = 25 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
end generate GEN_25;
-- Number of Fstores Generate
GEN_26 : if C_NUM_FSTORES = 26 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
end generate GEN_26;
-- Number of Fstores Generate
GEN_27 : if C_NUM_FSTORES = 27 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
end generate GEN_27;
-- Number of Fstores Generate
GEN_28 : if C_NUM_FSTORES = 28 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
reg_module_strt_addr(27) <= reg_module_start_address28_i ;
end generate GEN_28;
-- Number of Fstores Generate
GEN_29 : if C_NUM_FSTORES = 29 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
reg_module_strt_addr(27) <= reg_module_start_address28_i ;
reg_module_strt_addr(28) <= reg_module_start_address29_i ;
end generate GEN_29;
-- Number of Fstores Generate
GEN_30 : if C_NUM_FSTORES = 30 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
reg_module_strt_addr(27) <= reg_module_start_address28_i ;
reg_module_strt_addr(28) <= reg_module_start_address29_i ;
reg_module_strt_addr(29) <= reg_module_start_address30_i ;
end generate GEN_30;
-- Number of Fstores Generate
GEN_31 : if C_NUM_FSTORES = 31 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
reg_module_strt_addr(27) <= reg_module_start_address28_i ;
reg_module_strt_addr(28) <= reg_module_start_address29_i ;
reg_module_strt_addr(29) <= reg_module_start_address30_i ;
reg_module_strt_addr(30) <= reg_module_start_address31_i ;
end generate GEN_31;
-- Number of Fstores Generate
GEN_32 : if C_NUM_FSTORES = 32 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
reg_module_strt_addr(27) <= reg_module_start_address28_i ;
reg_module_strt_addr(28) <= reg_module_start_address29_i ;
reg_module_strt_addr(29) <= reg_module_start_address30_i ;
reg_module_strt_addr(30) <= reg_module_start_address31_i ;
reg_module_strt_addr(31) <= reg_module_start_address32_i ;
end generate GEN_32;
--GEN_START_ADDR_MAP : for i in 0 to C_NUM_FSTORES-1 generate
--begin
--
-- reg_module_strt_addr(i) <= reg_module_strt_addr_i(i);
--
--end generate GEN_START_ADDR_MAP;
--reg_module_strt_addr(0) <= reg_module_start_address1_i ;
--reg_module_strt_addr(1) <= reg_module_start_address2_i ;
--reg_module_strt_addr(2) <= reg_module_start_address3_i ;
--reg_module_strt_addr(3) <= reg_module_start_address4_i ;
--reg_module_strt_addr(4) <= reg_module_start_address5_i ;
--reg_module_strt_addr(5) <= reg_module_start_address6_i ;
--reg_module_strt_addr(6) <= reg_module_start_address7_i ;
--reg_module_strt_addr(7) <= reg_module_start_address8_i ;
--reg_module_strt_addr(8) <= reg_module_start_address9_i ;
--reg_module_strt_addr(9) <= reg_module_start_address10_i ;
--reg_module_strt_addr(10) <= reg_module_start_address11_i ;
--reg_module_strt_addr(11) <= reg_module_start_address12_i ;
--reg_module_strt_addr(12) <= reg_module_start_address13_i ;
--reg_module_strt_addr(13) <= reg_module_start_address14_i ;
--reg_module_strt_addr(14) <= reg_module_start_address15_i ;
--reg_module_strt_addr(15) <= reg_module_start_address16_i ;
--reg_module_strt_addr(16) <= reg_module_start_address17_i ;
--reg_module_strt_addr(17) <= reg_module_start_address18_i ;
--reg_module_strt_addr(18) <= reg_module_start_address19_i ;
--reg_module_strt_addr(19) <= reg_module_start_address20_i ;
--reg_module_strt_addr(20) <= reg_module_start_address21_i ;
--reg_module_strt_addr(21) <= reg_module_start_address22_i ;
--reg_module_strt_addr(22) <= reg_module_start_address23_i ;
--reg_module_strt_addr(23) <= reg_module_start_address24_i ;
--reg_module_strt_addr(24) <= reg_module_start_address25_i ;
--reg_module_strt_addr(25) <= reg_module_start_address26_i ;
--reg_module_strt_addr(26) <= reg_module_start_address27_i ;
--reg_module_strt_addr(27) <= reg_module_start_address28_i ;
--reg_module_strt_addr(28) <= reg_module_start_address29_i ;
--reg_module_strt_addr(29) <= reg_module_start_address30_i ;
--reg_module_strt_addr(30) <= reg_module_start_address31_i ;
--reg_module_strt_addr(31) <= reg_module_start_address32_i ;
---- Map for use in read mux.
reg_module_start_address1 <= reg_module_start_address1_i ;
reg_module_start_address2 <= reg_module_start_address2_i ;
reg_module_start_address3 <= reg_module_start_address3_i ;
reg_module_start_address4 <= reg_module_start_address4_i ;
reg_module_start_address5 <= reg_module_start_address5_i ;
reg_module_start_address6 <= reg_module_start_address6_i ;
reg_module_start_address7 <= reg_module_start_address7_i ;
reg_module_start_address8 <= reg_module_start_address8_i ;
reg_module_start_address9 <= reg_module_start_address9_i ;
reg_module_start_address10 <= reg_module_start_address10_i ;
reg_module_start_address11 <= reg_module_start_address11_i ;
reg_module_start_address12 <= reg_module_start_address12_i ;
reg_module_start_address13 <= reg_module_start_address13_i ;
reg_module_start_address14 <= reg_module_start_address14_i ;
reg_module_start_address15 <= reg_module_start_address15_i ;
reg_module_start_address16 <= reg_module_start_address16_i ;
reg_module_start_address17 <= reg_module_start_address17_i ;
reg_module_start_address18 <= reg_module_start_address18_i ;
reg_module_start_address19 <= reg_module_start_address19_i ;
reg_module_start_address20 <= reg_module_start_address20_i ;
reg_module_start_address21 <= reg_module_start_address21_i ;
reg_module_start_address22 <= reg_module_start_address22_i ;
reg_module_start_address23 <= reg_module_start_address23_i ;
reg_module_start_address24 <= reg_module_start_address24_i ;
reg_module_start_address25 <= reg_module_start_address25_i ;
reg_module_start_address26 <= reg_module_start_address26_i ;
reg_module_start_address27 <= reg_module_start_address27_i ;
reg_module_start_address28 <= reg_module_start_address28_i ;
reg_module_start_address29 <= reg_module_start_address29_i ;
reg_module_start_address30 <= reg_module_start_address30_i ;
reg_module_start_address31 <= reg_module_start_address31_i ;
reg_module_start_address32 <= reg_module_start_address32_i ;
--------*****************************************************************************
--------** START ADDRESS REGISTERS
--------*****************************************************************************
------
-------- Generate C_NUM_FSTORE start address registeres
------GEN_START_ADDR_REG : for i in 0 to MAX_FSTORES-1 generate
------begin
------
------ -- Start Address Registers
------ START_ADDR : process(prmry_aclk)
------ begin
------ if(prmry_aclk'EVENT and prmry_aclk = '1')then
------ if(prmry_resetn = '0')then
------ reg_module_strt_addr_i(i) <= (others => '0');
------ -- Write to appropriate Start Address
------ -- Index based on [(i+1)*2]+2. This gives an index increment
------ -- starting at 4 then going 6,8,10,12, etc. skipping each
------ -- reserved space between 32-bit start addresses. For
------ -- 64bit addressing this index calculation will need to be
------ -- modified.
------ elsif(i<C_NUM_FSTORES and axi2ip_wrce(((i+1)*2)+2) = '1')then
------ reg_module_strt_addr_i(i) <= axi2ip_wrdata;
------
------ -- For frames greater than fstores the vectors are reserved
------ -- and set to zero
------ elsif(i>= C_NUM_FSTORES)then
------ reg_module_strt_addr_i(i) <= (others => '0');
------
------ end if;
------ end if;
------ end process START_ADDR;
------end generate GEN_START_ADDR_REG;
------
-------- Map only C_NUM_FSTORE vectors to output port
------GEN_START_ADDR_MAP : for i in 0 to C_NUM_FSTORES-1 generate
------begin
------
------ reg_module_strt_addr(i) <= reg_module_strt_addr_i(i);
------
------end generate GEN_START_ADDR_MAP;
------
------
-------- Map for use in read mux.
------reg_module_start_address1_i <= reg_module_strt_addr_i(0);
------reg_module_start_address2_i <= reg_module_strt_addr_i(1);
------reg_module_start_address3_i <= reg_module_strt_addr_i(2);
------reg_module_start_address4_i <= reg_module_strt_addr_i(3);
------reg_module_start_address5_i <= reg_module_strt_addr_i(4);
------reg_module_start_address6_i <= reg_module_strt_addr_i(5);
------reg_module_start_address7_i <= reg_module_strt_addr_i(6);
------reg_module_start_address8_i <= reg_module_strt_addr_i(7);
------reg_module_start_address9_i <= reg_module_strt_addr_i(8);
------reg_module_start_address10_i <= reg_module_strt_addr_i(9);
------reg_module_start_address11_i <= reg_module_strt_addr_i(10);
------reg_module_start_address12_i <= reg_module_strt_addr_i(11);
------reg_module_start_address13_i <= reg_module_strt_addr_i(12);
------reg_module_start_address14_i <= reg_module_strt_addr_i(13);
------reg_module_start_address15_i <= reg_module_strt_addr_i(14);
------reg_module_start_address16_i <= reg_module_strt_addr_i(15);
------reg_module_start_address17_i <= reg_module_strt_addr_i(16);
------reg_module_start_address18_i <= reg_module_strt_addr_i(17);
------reg_module_start_address19_i <= reg_module_strt_addr_i(18);
------reg_module_start_address20_i <= reg_module_strt_addr_i(19);
------reg_module_start_address21_i <= reg_module_strt_addr_i(20);
------reg_module_start_address22_i <= reg_module_strt_addr_i(21);
------reg_module_start_address23_i <= reg_module_strt_addr_i(22);
------reg_module_start_address24_i <= reg_module_strt_addr_i(23);
------reg_module_start_address25_i <= reg_module_strt_addr_i(24);
------reg_module_start_address26_i <= reg_module_strt_addr_i(25);
------reg_module_start_address27_i <= reg_module_strt_addr_i(26);
------reg_module_start_address28_i <= reg_module_strt_addr_i(27);
------reg_module_start_address29_i <= reg_module_strt_addr_i(28);
------reg_module_start_address30_i <= reg_module_strt_addr_i(29);
------reg_module_start_address31_i <= reg_module_strt_addr_i(30);
------reg_module_start_address32_i <= reg_module_strt_addr_i(31);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_regdirect
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_regdirect.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_regdirect is
generic(
C_NUM_REGISTERS : integer := 6 ;
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
C_GENLOCK_MODE : integer range 0 to 3 := 0 ;
-----------------------------------------------------------------------
C_DYNAMIC_RESOLUTION : integer range 0 to 1 := 1 ;
-- Run time configuration of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 0 = Halt VDMA before writing new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 1 = Run time register configuration for new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE.
-----------------------------------------------------------------------
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
run_stop : in std_logic ; --
dmasr_halt : in std_logic ; --
stop : in std_logic ; --
--
reg_index : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
-- Register Direct Support --
prmtr_updt_complete : out std_logic ; --
regdir_idle : out std_logic ; --
--
-- Register Direct Mode Video Parameter In --
reg_module_vsize : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : out std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_strid : out std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : out std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_strt_addr : out STARTADDR_ARRAY_TYPE --
(0 to C_NUM_FSTORES - 1) ; --
reg_module_start_address1 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address2 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address3 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address4 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address5 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address6 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address7 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address8 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address9 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address10 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address11 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address12 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address13 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address14 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address15 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address16 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address17 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address18 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address19 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address20 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address21 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address22 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address23 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address24 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address25 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address26 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address27 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address28 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address29 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address30 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address31 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0); --
reg_module_start_address32 : out std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_regdirect;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_regdirect is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant VSYNC_INDEX : integer := 0; -- VSYNC Register index
constant HSYNC_INDEX : integer := 1; -- HSYNC Register index
constant DLY_STRIDE_INDEX : integer := 2; -- STRIDE/DLY Reg index
--constant RESERVED_INDEX3 : integer := 3; -- Reserved
constant STARTADDR1_INDEX : integer := 3; -- Start Address 1 Reg index
constant STARTADDR2_INDEX : integer := 4; -- Start Address 2 Reg index
constant STARTADDR3_INDEX : integer := 5; -- Start Address 3 Reg index
constant STARTADDR4_INDEX : integer := 6; -- Start Address 3 Reg index
constant STARTADDR5_INDEX : integer := 7; -- Start Address 3 Reg index
constant STARTADDR6_INDEX : integer := 8; -- Start Address 3 Reg index
constant STARTADDR7_INDEX : integer := 9; -- Start Address 3 Reg index
constant STARTADDR8_INDEX : integer := 10; -- Start Address 3 Reg index
constant STARTADDR9_INDEX : integer := 11; -- Start Address 3 Reg index
constant STARTADDR10_INDEX : integer := 12; -- Start Address 3 Reg index
constant STARTADDR11_INDEX : integer := 13; -- Start Address 3 Reg index
constant STARTADDR12_INDEX : integer := 14; -- Start Address 3 Reg index
constant STARTADDR13_INDEX : integer := 15; -- Start Address 3 Reg index
constant STARTADDR14_INDEX : integer := 16; -- Start Address 3 Reg index
constant STARTADDR15_INDEX : integer := 17; -- Start Address 3 Reg index
constant STARTADDR16_INDEX : integer := 18; -- Start Address 3 Reg index
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal prmtr_updt_complete_i : std_logic := '0';
signal reg_config_locked_i : std_logic := '0';
signal regdir_idle_i : std_logic := '0';
signal run_stop_d1 : std_logic := '0';
signal run_stop_re : std_logic := '0';
--signal reg_module_strt_addr_i : STARTADDR_ARRAY_TYPE(0 to MAX_FSTORES-1);
signal reg_module_start_address1_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address2_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address3_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address4_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address5_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address6_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address7_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address8_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address9_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address10_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address11_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address12_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address13_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address14_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address15_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address16_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address17_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address18_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address19_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address20_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address21_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address22_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address23_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address24_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address25_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address26_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address27_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address28_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address29_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address30_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address31_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal reg_module_start_address32_i : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Register DMACR RunStop bit to create a RE pulse
REG_RUN_RE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
run_stop_d1 <= '0';
else
run_stop_d1 <= run_stop;
end if;
end if;
end process REG_RUN_RE;
run_stop_re <= run_stop and not run_stop_d1;
-- Gen register direct idle flag to indicate when not idle.
-- Flag is asserted to NOT idle at start of run and to Idle
-- on reset, halt, or stop (i.e. error)
-- This is used to generate first fsync in free run mode.
REG_IDLE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or stop = '1')then
regdir_idle_i <= '1';
elsif(run_stop_re = '1')then
regdir_idle_i <= '0';
elsif(prmtr_updt_complete_i = '1')then
regdir_idle_i <= '1';
end if;
end if;
end process REG_IDLE;
regdir_idle <= regdir_idle_i;
-- Vertical Size Register
VSIZE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_vsize <= (others => '0');
elsif(axi2ip_wrce(VSYNC_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_vsize <= axi2ip_wrdata(VSIZE_DWIDTH-1 downto 0);
end if;
end if;
end process VSIZE_REGISTER;
VIDEO_PRMTR_UPDATE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or run_stop = '0')then
prmtr_updt_complete_i <= '0';
elsif(axi2ip_wrce(VSYNC_INDEX) = '1' and reg_config_locked_i = '0')then
prmtr_updt_complete_i <= '1';
else
prmtr_updt_complete_i <= '0';
end if;
end if;
end process VIDEO_PRMTR_UPDATE;
prmtr_updt_complete <= prmtr_updt_complete_i;
-- Horizontal Size Register
HSIZE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_hsize <= (others => '0');
elsif(axi2ip_wrce(HSYNC_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_hsize <= axi2ip_wrdata(HSIZE_DWIDTH-1 downto 0);
end if;
end if;
end process HSIZE_REGISTER;
-- Delay/Stride Register
--Genlock Slave mode
S_GEN_DLYSTRIDE_REGISTER : if C_GENLOCK_MODE = 1 generate
begin
S_DLYSTRIDE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
--reg_module_frmdly <= (others => '0');
reg_module_frmdly <= "00001"; --CR 709007
reg_module_strid <= (others => '0');
elsif(axi2ip_wrce(DLY_STRIDE_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_frmdly <= axi2ip_wrdata(FRMDLY_MSB downto FRMDLY_LSB);
reg_module_strid <= axi2ip_wrdata(STRIDE_DWIDTH-1 downto 0);
end if;
end if;
end process S_DLYSTRIDE_REGISTER;
end generate S_GEN_DLYSTRIDE_REGISTER;
--Genlock Master mode
M_GEN_DLYSTRIDE_REGISTER : if C_GENLOCK_MODE = 0 generate
begin
reg_module_frmdly <= (others => '0');
M_DLYSTRIDE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_strid <= (others => '0');
elsif(axi2ip_wrce(DLY_STRIDE_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_strid <= axi2ip_wrdata(STRIDE_DWIDTH-1 downto 0);
end if;
end if;
end process M_DLYSTRIDE_REGISTER;
end generate M_GEN_DLYSTRIDE_REGISTER;
--Dynamic Genlock Master mode
DM_GEN_DLYSTRIDE_REGISTER : if C_GENLOCK_MODE = 2 generate
begin
reg_module_frmdly <= (others => '0');
DM_DLYSTRIDE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_strid <= (others => '0');
elsif(axi2ip_wrce(DLY_STRIDE_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_strid <= axi2ip_wrdata(STRIDE_DWIDTH-1 downto 0);
end if;
end if;
end process DM_DLYSTRIDE_REGISTER;
end generate DM_GEN_DLYSTRIDE_REGISTER;
--Dynamic Genlock Slave mode
DS_GEN_DLYSTRIDE_REGISTER : if C_GENLOCK_MODE = 3 generate
begin
reg_module_frmdly <= (others => '0');
DS_DLYSTRIDE_REGISTER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_strid <= (others => '0');
elsif(axi2ip_wrce(DLY_STRIDE_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_strid <= axi2ip_wrdata(STRIDE_DWIDTH-1 downto 0);
end if;
end if;
end process DS_DLYSTRIDE_REGISTER;
end generate DS_GEN_DLYSTRIDE_REGISTER;
--No Dynamic resolution
GEN_REG_CONFIG_LOCK_BIT : if C_DYNAMIC_RESOLUTION = 0 generate
begin
REG_CONFIG_LOCKED : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
reg_config_locked_i <= '0';
elsif(axi2ip_wrce(VSYNC_INDEX) = '1')then
reg_config_locked_i <= '1';
end if;
end if;
end process REG_CONFIG_LOCKED;
end generate GEN_REG_CONFIG_LOCK_BIT;
--Dynamic resolution
GEN_NO_REG_CONFIG_LOCK_BIT : if C_DYNAMIC_RESOLUTION = 1 generate
begin
reg_config_locked_i <= '0';
end generate GEN_NO_REG_CONFIG_LOCK_BIT;
--*****************************************************************************
--** START ADDRESS REGISTERS
--*****************************************************************************
-- Generate C_NUM_FSTORE start address registeres
--GEN_START_ADDR_REG : for i in 1 to MAX_FSTORES generate
----signal j : integer := 1;
--
--begin
----j<= i;
--
-- -- Start Address Registers
-- START_ADDR : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_strt_addr_i(i-1) <= (others => '0');
-- -- Write to appropriate Start Address
--
-- elsif(i>= C_NUM_FSTORES)then
-- reg_module_strt_addr_i(i-1) <= (others => '0');
--
--
-- elsif(i<C_NUM_FSTORES and axi2ip_wrce(i+2) = '1'and C_NUM_FSTORES <17)then
-- reg_module_strt_addr_i(i-1) <= axi2ip_wrdata;
-- elsif(i<C_NUM_FSTORES and C_NUM_FSTORES >=17 and j<17 and axi2ip_wrce(i+2) = '1' and reg_index(0) = '0')then
-- --if(i<17 and axi2ip_wrce(i+2) = '1')then
-- --if(reg_index(0) = '0')then
-- reg_module_strt_addr_i(i-1) <= axi2ip_wrdata;
-- --elsif(reg_index(0) = '1')then
-- elsif(i<C_NUM_FSTORES and C_NUM_FSTORES >=17 and j<17 and axi2ip_wrce(i+2) = '1' and reg_index(0) = '1')then
-- reg_module_strt_addr_i(i+15) <= axi2ip_wrdata;
-- --end if;
-- --elsif(i>=17 and axi2ip_wrce(i-14) = '1')then
-- elsif(i<C_NUM_FSTORES and C_NUM_FSTORES >=17 and j>=17 and axi2ip_wrce(i-14) = '1' and reg_index(0) = '0')then
-- --if(reg_index(0) = '0')then
-- reg_module_strt_addr_i(i-17) <= axi2ip_wrdata;
-- --elsif(reg_index(0) = '1')then
-- elsif(i<C_NUM_FSTORES and C_NUM_FSTORES >=17 and j>=17 and axi2ip_wrce(i-14) = '1' and reg_index(0) = '1')then
-- reg_module_strt_addr_i(i-1) <= axi2ip_wrdata;
-- --end if;
-- --end if;
-- -- For frames greater than fstores the vectors are reserved
-- -- and set to zero
-- end if;
-- end if;
-- end process START_ADDR;
--end generate GEN_START_ADDR_REG;
-- Map only C_NUM_FSTORE vectors to output port
-- Number of Fstores Generate
GEN_NUM_FSTORES_1 : if C_NUM_FSTORES = 1 generate
-- Start Address Register
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
reg_module_start_address2_i <= (others => '0');
reg_module_start_address3_i <= (others => '0');
reg_module_start_address4_i <= (others => '0');
reg_module_start_address5_i <= (others => '0');
reg_module_start_address6_i <= (others => '0');
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_1;
-- Number of Fstores Generate
GEN_NUM_FSTORES_2 : if C_NUM_FSTORES = 2 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
reg_module_start_address3_i <= (others => '0');
reg_module_start_address4_i <= (others => '0');
reg_module_start_address5_i <= (others => '0');
reg_module_start_address6_i <= (others => '0');
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_2;
-- Number of Fstores Generate
GEN_NUM_FSTORES_3 : if C_NUM_FSTORES = 3 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
reg_module_start_address4_i <= (others => '0');
reg_module_start_address5_i <= (others => '0');
reg_module_start_address6_i <= (others => '0');
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_3;
-- Number of Fstores Generate
GEN_NUM_FSTORES_4 : if C_NUM_FSTORES = 4 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
reg_module_start_address5_i <= (others => '0');
reg_module_start_address6_i <= (others => '0');
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_4;
-- Number of Fstores Generate
GEN_NUM_FSTORES_5 : if C_NUM_FSTORES = 5 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
reg_module_start_address6_i <= (others => '0');
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_5;
-- Number of Fstores Generate
GEN_NUM_FSTORES_6 : if C_NUM_FSTORES = 6 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
reg_module_start_address7_i <= (others => '0');
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_6;
-- Number of Fstores Generate
GEN_NUM_FSTORES_7 : if C_NUM_FSTORES = 7 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
reg_module_start_address8_i <= (others => '0');
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_7;
-- Number of Fstores Generate
GEN_NUM_FSTORES_8 : if C_NUM_FSTORES = 8 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
reg_module_start_address9_i <= (others => '0');
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_8;
-- Number of Fstores Generate
GEN_NUM_FSTORES_9 : if C_NUM_FSTORES = 9 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
reg_module_start_address10_i <= (others => '0');
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_9;
-- Number of Fstores Generate
GEN_NUM_FSTORES_10 : if C_NUM_FSTORES = 10 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
reg_module_start_address11_i <= (others => '0');
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_10;
-- Number of Fstores Generate
GEN_NUM_FSTORES_11 : if C_NUM_FSTORES = 11 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
reg_module_start_address12_i <= (others => '0');
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_11;
-- Number of Fstores Generate
GEN_NUM_FSTORES_12 : if C_NUM_FSTORES = 12 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
reg_module_start_address13_i <= (others => '0');
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_12;
-- Number of Fstores Generate
GEN_NUM_FSTORES_13 : if C_NUM_FSTORES = 13 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
reg_module_start_address14_i <= (others => '0');
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_13;
-- Number of Fstores Generate
GEN_NUM_FSTORES_14 : if C_NUM_FSTORES = 14 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
reg_module_start_address15_i <= (others => '0');
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_14;
-- Number of Fstores Generate
GEN_NUM_FSTORES_15 : if C_NUM_FSTORES = 15 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
reg_module_start_address16_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_15;
-- Number of Fstores Generate
GEN_NUM_FSTORES_16 : if C_NUM_FSTORES = 16 generate
-- Start Address Register 1
START_ADDR1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif(axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0')then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
reg_module_start_address17_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_16;
-- Number of Fstores Generate
GEN_NUM_FSTORES_17 : if C_NUM_FSTORES = 17 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
START_ADDR2 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address2_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
reg_module_start_address18_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_17;
-- Number of Fstores Generate
GEN_NUM_FSTORES_18 : if C_NUM_FSTORES = 18 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
START_ADDR3 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address3_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
reg_module_start_address19_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_18;
-- Number of Fstores Generate
GEN_NUM_FSTORES_19 : if C_NUM_FSTORES = 19 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
START_ADDR4 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address4_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
reg_module_start_address20_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_19;
-- Number of Fstores Generate
GEN_NUM_FSTORES_20 : if C_NUM_FSTORES = 20 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
START_ADDR5 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address5_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
reg_module_start_address21_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_20;
-- Number of Fstores Generate
GEN_NUM_FSTORES_21 : if C_NUM_FSTORES = 21 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
START_ADDR6 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address6_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
reg_module_start_address22_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_21;
-- Number of Fstores Generate
GEN_NUM_FSTORES_22 : if C_NUM_FSTORES = 22 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
START_ADDR7 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address7_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
reg_module_start_address23_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_22;
-- Number of Fstores Generate
GEN_NUM_FSTORES_23 : if C_NUM_FSTORES = 23 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
START_ADDR8 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address8_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
reg_module_start_address24_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_23;
-- Number of Fstores Generate
GEN_NUM_FSTORES_24 : if C_NUM_FSTORES = 24 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
START_ADDR9 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address9_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
reg_module_start_address25_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_24;
-- Number of Fstores Generate
GEN_NUM_FSTORES_25 : if C_NUM_FSTORES = 25 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
START_ADDR10 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address10_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
reg_module_start_address26_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_25;
-- Number of Fstores Generate
GEN_NUM_FSTORES_26 : if C_NUM_FSTORES = 26 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
START_ADDR11 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address11_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
reg_module_start_address27_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_26;
-- Number of Fstores Generate
GEN_NUM_FSTORES_27 : if C_NUM_FSTORES = 27 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
START_ADDR12 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address12_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
reg_module_start_address28_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_27;
-- Number of Fstores Generate
GEN_NUM_FSTORES_28 : if C_NUM_FSTORES = 28 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
--START_ADDR12 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address12_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address12_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR12;
-- Start Address Register 13
START_ADDR13 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address13_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
START_ADDR28 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address28_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR28;
reg_module_start_address29_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_28;
-- Number of Fstores Generate
GEN_NUM_FSTORES_29 : if C_NUM_FSTORES = 29 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
--START_ADDR12 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address12_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address12_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR12;
-- Start Address Register 13
--START_ADDR13 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address13_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address13_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR13;
-- Start Address Register 14
START_ADDR14 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address14_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
START_ADDR28 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address28_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR28;
START_ADDR29 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address29_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR29;
reg_module_start_address30_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_29;
-- Number of Fstores Generate
GEN_NUM_FSTORES_30 : if C_NUM_FSTORES = 30 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
--START_ADDR12 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address12_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address12_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR12;
-- Start Address Register 13
--START_ADDR13 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address13_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address13_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR13;
-- Start Address Register 14
--START_ADDR14 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address14_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address14_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR14;
-- Start Address Register 15
START_ADDR15 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address15_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
START_ADDR28 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address28_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR28;
START_ADDR29 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address29_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR29;
START_ADDR30 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address30_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR30;
reg_module_start_address31_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_30;
-- Number of Fstores Generate
GEN_NUM_FSTORES_31 : if C_NUM_FSTORES = 31 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
--START_ADDR12 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address12_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address12_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR12;
-- Start Address Register 13
--START_ADDR13 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address13_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address13_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR13;
-- Start Address Register 14
--START_ADDR14 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address14_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address14_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR14;
-- Start Address Register 15
--START_ADDR15 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address15_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address15_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR15;
-- Start Address Register 16
START_ADDR16 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
reg_module_start_address16_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
START_ADDR28 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address28_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR28;
START_ADDR29 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address29_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR29;
START_ADDR30 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address30_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR30;
START_ADDR31 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address15_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address31_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR31;
reg_module_start_address32_i <= (others => '0');
end generate GEN_NUM_FSTORES_31;
-- Number of Fstores Generate
GEN_NUM_FSTORES_32 : if C_NUM_FSTORES = 32 generate
-- Start Address Register 1
--START_ADDR1 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address1_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address1_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR1;
-- Start Address Register 2
--START_ADDR2 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address2_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address2_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR2;
-- Start Address Register 3
--START_ADDR3 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address3_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address3_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR3;
-- Start Address Register 4
--START_ADDR4 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address4_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address4_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR4;
-- Start Address Register 5
--START_ADDR5 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address5_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address5_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR5;
-- Start Address Register 6
--START_ADDR6 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address6_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address6_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR6;
-- Start Address Register 7
--START_ADDR7 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address7_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address7_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR7;
-- Start Address Register 8
-- START_ADDR8 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address8_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address8_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR8;
-- Start Address Register 9
--START_ADDR9 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address9_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address9_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR9;
-- Start Address Register 10
--START_ADDR10 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address10_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address10_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR10;
-- Start Address Register 11
--START_ADDR11 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address11_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address11_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR11;
-- Start Address Register 12
--START_ADDR12 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address12_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address12_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR12;
-- Start Address Register 13
--START_ADDR13 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address13_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address13_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR13;
-- Start Address Register 14
--START_ADDR14 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address14_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address14_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR14;
-- Start Address Register 15
--START_ADDR15 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address15_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address15_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR15;
-- Start Address Register 16
--START_ADDR16 : process(prmry_aclk)
-- begin
-- if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- if(prmry_resetn = '0')then
-- reg_module_start_address16_i <= (others => '0');
-- elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0' )then
-- reg_module_start_address16_i <= axi2ip_wrdata;
-- end if;
-- end if;
-- end process START_ADDR16;
-- Start Address Register 17
START_ADDR17 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address1_i <= (others => '0');
reg_module_start_address17_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address1_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR1_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address17_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR17;
-- Start Address Register 17
START_ADDR18 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address2_i <= (others => '0');
reg_module_start_address18_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address2_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR2_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address18_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR18;
START_ADDR19 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address3_i <= (others => '0');
reg_module_start_address19_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address3_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR3_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address19_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR19;
START_ADDR20 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address4_i <= (others => '0');
reg_module_start_address20_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address4_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR4_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address20_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR20;
START_ADDR21 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address5_i <= (others => '0');
reg_module_start_address21_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address5_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR5_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address21_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR21;
START_ADDR22 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address6_i <= (others => '0');
reg_module_start_address22_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address6_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR6_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address22_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR22;
START_ADDR23 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address7_i <= (others => '0');
reg_module_start_address23_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address7_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR7_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address23_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR23;
START_ADDR24 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address8_i <= (others => '0');
reg_module_start_address24_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address8_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR8_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address24_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR24;
START_ADDR25 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address9_i <= (others => '0');
reg_module_start_address25_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address9_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR9_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address25_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR25;
START_ADDR26 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address10_i <= (others => '0');
reg_module_start_address26_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address10_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR10_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address26_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR26;
START_ADDR27 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address11_i <= (others => '0');
reg_module_start_address27_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address11_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR11_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address27_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR27;
START_ADDR28 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address12_i <= (others => '0');
reg_module_start_address28_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address12_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR12_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address28_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR28;
START_ADDR29 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address13_i <= (others => '0');
reg_module_start_address29_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address13_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR13_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address29_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR29;
START_ADDR30 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address14_i <= (others => '0');
reg_module_start_address30_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address14_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR14_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address30_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR30;
START_ADDR31 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address15_i <= (others => '0');
reg_module_start_address31_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address15_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR15_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address31_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR31;
START_ADDR32 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_module_start_address16_i <= (others => '0');
reg_module_start_address32_i <= (others => '0');
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '0')then
reg_module_start_address16_i <= axi2ip_wrdata;
elsif( axi2ip_wrce(STARTADDR16_INDEX) = '1' and reg_config_locked_i = '0' and reg_index(0) = '1')then
reg_module_start_address32_i <= axi2ip_wrdata;
end if;
end if;
end process START_ADDR32;
end generate GEN_NUM_FSTORES_32;
-- Number of Fstores Generate
GEN_1 : if C_NUM_FSTORES = 1 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
end generate GEN_1;
-- Number of Fstores Generate
GEN_2 : if C_NUM_FSTORES = 2 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
end generate GEN_2;
-- Number of Fstores Generate
GEN_3 : if C_NUM_FSTORES = 3 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
end generate GEN_3;
-- Number of Fstores Generate
GEN_4 : if C_NUM_FSTORES = 4 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
end generate GEN_4;
-- Number of Fstores Generate
GEN_5 : if C_NUM_FSTORES = 5 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
end generate GEN_5;
-- Number of Fstores Generate
GEN_6 : if C_NUM_FSTORES = 6 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
end generate GEN_6;
-- Number of Fstores Generate
GEN_7 : if C_NUM_FSTORES = 7 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
end generate GEN_7;
-- Number of Fstores Generate
GEN_8 : if C_NUM_FSTORES = 8 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
end generate GEN_8;
-- Number of Fstores Generate
GEN_9 : if C_NUM_FSTORES = 9 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
end generate GEN_9;
-- Number of Fstores Generate
GEN_10 : if C_NUM_FSTORES = 10 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
end generate GEN_10;
-- Number of Fstores Generate
GEN_11 : if C_NUM_FSTORES = 11 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
end generate GEN_11;
-- Number of Fstores Generate
GEN_12 : if C_NUM_FSTORES = 12 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
end generate GEN_12;
-- Number of Fstores Generate
GEN_13 : if C_NUM_FSTORES = 13 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
end generate GEN_13;
-- Number of Fstores Generate
GEN_14 : if C_NUM_FSTORES = 14 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
end generate GEN_14;
-- Number of Fstores Generate
GEN_15 : if C_NUM_FSTORES = 15 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
end generate GEN_15;
-- Number of Fstores Generate
GEN_16 : if C_NUM_FSTORES = 16 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
end generate GEN_16;
-- Number of Fstores Generate
GEN_17 : if C_NUM_FSTORES = 17 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
end generate GEN_17;
-- Number of Fstores Generate
GEN_18 : if C_NUM_FSTORES = 18 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
end generate GEN_18;
-- Number of Fstores Generate
GEN_19 : if C_NUM_FSTORES = 19 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
end generate GEN_19;
-- Number of Fstores Generate
GEN_20 : if C_NUM_FSTORES = 20 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
end generate GEN_20;
-- Number of Fstores Generate
GEN_21 : if C_NUM_FSTORES = 21 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
end generate GEN_21;
-- Number of Fstores Generate
GEN_22 : if C_NUM_FSTORES = 22 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
end generate GEN_22;
-- Number of Fstores Generate
GEN_23 : if C_NUM_FSTORES = 23 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
end generate GEN_23;
-- Number of Fstores Generate
GEN_24 : if C_NUM_FSTORES = 24 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
end generate GEN_24;
-- Number of Fstores Generate
GEN_25 : if C_NUM_FSTORES = 25 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
end generate GEN_25;
-- Number of Fstores Generate
GEN_26 : if C_NUM_FSTORES = 26 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
end generate GEN_26;
-- Number of Fstores Generate
GEN_27 : if C_NUM_FSTORES = 27 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
end generate GEN_27;
-- Number of Fstores Generate
GEN_28 : if C_NUM_FSTORES = 28 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
reg_module_strt_addr(27) <= reg_module_start_address28_i ;
end generate GEN_28;
-- Number of Fstores Generate
GEN_29 : if C_NUM_FSTORES = 29 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
reg_module_strt_addr(27) <= reg_module_start_address28_i ;
reg_module_strt_addr(28) <= reg_module_start_address29_i ;
end generate GEN_29;
-- Number of Fstores Generate
GEN_30 : if C_NUM_FSTORES = 30 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
reg_module_strt_addr(27) <= reg_module_start_address28_i ;
reg_module_strt_addr(28) <= reg_module_start_address29_i ;
reg_module_strt_addr(29) <= reg_module_start_address30_i ;
end generate GEN_30;
-- Number of Fstores Generate
GEN_31 : if C_NUM_FSTORES = 31 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
reg_module_strt_addr(27) <= reg_module_start_address28_i ;
reg_module_strt_addr(28) <= reg_module_start_address29_i ;
reg_module_strt_addr(29) <= reg_module_start_address30_i ;
reg_module_strt_addr(30) <= reg_module_start_address31_i ;
end generate GEN_31;
-- Number of Fstores Generate
GEN_32 : if C_NUM_FSTORES = 32 generate
reg_module_strt_addr(0) <= reg_module_start_address1_i ;
reg_module_strt_addr(1) <= reg_module_start_address2_i ;
reg_module_strt_addr(2) <= reg_module_start_address3_i ;
reg_module_strt_addr(3) <= reg_module_start_address4_i ;
reg_module_strt_addr(4) <= reg_module_start_address5_i ;
reg_module_strt_addr(5) <= reg_module_start_address6_i ;
reg_module_strt_addr(6) <= reg_module_start_address7_i ;
reg_module_strt_addr(7) <= reg_module_start_address8_i ;
reg_module_strt_addr(8) <= reg_module_start_address9_i ;
reg_module_strt_addr(9) <= reg_module_start_address10_i ;
reg_module_strt_addr(10) <= reg_module_start_address11_i ;
reg_module_strt_addr(11) <= reg_module_start_address12_i ;
reg_module_strt_addr(12) <= reg_module_start_address13_i ;
reg_module_strt_addr(13) <= reg_module_start_address14_i ;
reg_module_strt_addr(14) <= reg_module_start_address15_i ;
reg_module_strt_addr(15) <= reg_module_start_address16_i ;
reg_module_strt_addr(16) <= reg_module_start_address17_i ;
reg_module_strt_addr(17) <= reg_module_start_address18_i ;
reg_module_strt_addr(18) <= reg_module_start_address19_i ;
reg_module_strt_addr(19) <= reg_module_start_address20_i ;
reg_module_strt_addr(20) <= reg_module_start_address21_i ;
reg_module_strt_addr(21) <= reg_module_start_address22_i ;
reg_module_strt_addr(22) <= reg_module_start_address23_i ;
reg_module_strt_addr(23) <= reg_module_start_address24_i ;
reg_module_strt_addr(24) <= reg_module_start_address25_i ;
reg_module_strt_addr(25) <= reg_module_start_address26_i ;
reg_module_strt_addr(26) <= reg_module_start_address27_i ;
reg_module_strt_addr(27) <= reg_module_start_address28_i ;
reg_module_strt_addr(28) <= reg_module_start_address29_i ;
reg_module_strt_addr(29) <= reg_module_start_address30_i ;
reg_module_strt_addr(30) <= reg_module_start_address31_i ;
reg_module_strt_addr(31) <= reg_module_start_address32_i ;
end generate GEN_32;
--GEN_START_ADDR_MAP : for i in 0 to C_NUM_FSTORES-1 generate
--begin
--
-- reg_module_strt_addr(i) <= reg_module_strt_addr_i(i);
--
--end generate GEN_START_ADDR_MAP;
--reg_module_strt_addr(0) <= reg_module_start_address1_i ;
--reg_module_strt_addr(1) <= reg_module_start_address2_i ;
--reg_module_strt_addr(2) <= reg_module_start_address3_i ;
--reg_module_strt_addr(3) <= reg_module_start_address4_i ;
--reg_module_strt_addr(4) <= reg_module_start_address5_i ;
--reg_module_strt_addr(5) <= reg_module_start_address6_i ;
--reg_module_strt_addr(6) <= reg_module_start_address7_i ;
--reg_module_strt_addr(7) <= reg_module_start_address8_i ;
--reg_module_strt_addr(8) <= reg_module_start_address9_i ;
--reg_module_strt_addr(9) <= reg_module_start_address10_i ;
--reg_module_strt_addr(10) <= reg_module_start_address11_i ;
--reg_module_strt_addr(11) <= reg_module_start_address12_i ;
--reg_module_strt_addr(12) <= reg_module_start_address13_i ;
--reg_module_strt_addr(13) <= reg_module_start_address14_i ;
--reg_module_strt_addr(14) <= reg_module_start_address15_i ;
--reg_module_strt_addr(15) <= reg_module_start_address16_i ;
--reg_module_strt_addr(16) <= reg_module_start_address17_i ;
--reg_module_strt_addr(17) <= reg_module_start_address18_i ;
--reg_module_strt_addr(18) <= reg_module_start_address19_i ;
--reg_module_strt_addr(19) <= reg_module_start_address20_i ;
--reg_module_strt_addr(20) <= reg_module_start_address21_i ;
--reg_module_strt_addr(21) <= reg_module_start_address22_i ;
--reg_module_strt_addr(22) <= reg_module_start_address23_i ;
--reg_module_strt_addr(23) <= reg_module_start_address24_i ;
--reg_module_strt_addr(24) <= reg_module_start_address25_i ;
--reg_module_strt_addr(25) <= reg_module_start_address26_i ;
--reg_module_strt_addr(26) <= reg_module_start_address27_i ;
--reg_module_strt_addr(27) <= reg_module_start_address28_i ;
--reg_module_strt_addr(28) <= reg_module_start_address29_i ;
--reg_module_strt_addr(29) <= reg_module_start_address30_i ;
--reg_module_strt_addr(30) <= reg_module_start_address31_i ;
--reg_module_strt_addr(31) <= reg_module_start_address32_i ;
---- Map for use in read mux.
reg_module_start_address1 <= reg_module_start_address1_i ;
reg_module_start_address2 <= reg_module_start_address2_i ;
reg_module_start_address3 <= reg_module_start_address3_i ;
reg_module_start_address4 <= reg_module_start_address4_i ;
reg_module_start_address5 <= reg_module_start_address5_i ;
reg_module_start_address6 <= reg_module_start_address6_i ;
reg_module_start_address7 <= reg_module_start_address7_i ;
reg_module_start_address8 <= reg_module_start_address8_i ;
reg_module_start_address9 <= reg_module_start_address9_i ;
reg_module_start_address10 <= reg_module_start_address10_i ;
reg_module_start_address11 <= reg_module_start_address11_i ;
reg_module_start_address12 <= reg_module_start_address12_i ;
reg_module_start_address13 <= reg_module_start_address13_i ;
reg_module_start_address14 <= reg_module_start_address14_i ;
reg_module_start_address15 <= reg_module_start_address15_i ;
reg_module_start_address16 <= reg_module_start_address16_i ;
reg_module_start_address17 <= reg_module_start_address17_i ;
reg_module_start_address18 <= reg_module_start_address18_i ;
reg_module_start_address19 <= reg_module_start_address19_i ;
reg_module_start_address20 <= reg_module_start_address20_i ;
reg_module_start_address21 <= reg_module_start_address21_i ;
reg_module_start_address22 <= reg_module_start_address22_i ;
reg_module_start_address23 <= reg_module_start_address23_i ;
reg_module_start_address24 <= reg_module_start_address24_i ;
reg_module_start_address25 <= reg_module_start_address25_i ;
reg_module_start_address26 <= reg_module_start_address26_i ;
reg_module_start_address27 <= reg_module_start_address27_i ;
reg_module_start_address28 <= reg_module_start_address28_i ;
reg_module_start_address29 <= reg_module_start_address29_i ;
reg_module_start_address30 <= reg_module_start_address30_i ;
reg_module_start_address31 <= reg_module_start_address31_i ;
reg_module_start_address32 <= reg_module_start_address32_i ;
--------*****************************************************************************
--------** START ADDRESS REGISTERS
--------*****************************************************************************
------
-------- Generate C_NUM_FSTORE start address registeres
------GEN_START_ADDR_REG : for i in 0 to MAX_FSTORES-1 generate
------begin
------
------ -- Start Address Registers
------ START_ADDR : process(prmry_aclk)
------ begin
------ if(prmry_aclk'EVENT and prmry_aclk = '1')then
------ if(prmry_resetn = '0')then
------ reg_module_strt_addr_i(i) <= (others => '0');
------ -- Write to appropriate Start Address
------ -- Index based on [(i+1)*2]+2. This gives an index increment
------ -- starting at 4 then going 6,8,10,12, etc. skipping each
------ -- reserved space between 32-bit start addresses. For
------ -- 64bit addressing this index calculation will need to be
------ -- modified.
------ elsif(i<C_NUM_FSTORES and axi2ip_wrce(((i+1)*2)+2) = '1')then
------ reg_module_strt_addr_i(i) <= axi2ip_wrdata;
------
------ -- For frames greater than fstores the vectors are reserved
------ -- and set to zero
------ elsif(i>= C_NUM_FSTORES)then
------ reg_module_strt_addr_i(i) <= (others => '0');
------
------ end if;
------ end if;
------ end process START_ADDR;
------end generate GEN_START_ADDR_REG;
------
-------- Map only C_NUM_FSTORE vectors to output port
------GEN_START_ADDR_MAP : for i in 0 to C_NUM_FSTORES-1 generate
------begin
------
------ reg_module_strt_addr(i) <= reg_module_strt_addr_i(i);
------
------end generate GEN_START_ADDR_MAP;
------
------
-------- Map for use in read mux.
------reg_module_start_address1_i <= reg_module_strt_addr_i(0);
------reg_module_start_address2_i <= reg_module_strt_addr_i(1);
------reg_module_start_address3_i <= reg_module_strt_addr_i(2);
------reg_module_start_address4_i <= reg_module_strt_addr_i(3);
------reg_module_start_address5_i <= reg_module_strt_addr_i(4);
------reg_module_start_address6_i <= reg_module_strt_addr_i(5);
------reg_module_start_address7_i <= reg_module_strt_addr_i(6);
------reg_module_start_address8_i <= reg_module_strt_addr_i(7);
------reg_module_start_address9_i <= reg_module_strt_addr_i(8);
------reg_module_start_address10_i <= reg_module_strt_addr_i(9);
------reg_module_start_address11_i <= reg_module_strt_addr_i(10);
------reg_module_start_address12_i <= reg_module_strt_addr_i(11);
------reg_module_start_address13_i <= reg_module_strt_addr_i(12);
------reg_module_start_address14_i <= reg_module_strt_addr_i(13);
------reg_module_start_address15_i <= reg_module_strt_addr_i(14);
------reg_module_start_address16_i <= reg_module_strt_addr_i(15);
------reg_module_start_address17_i <= reg_module_strt_addr_i(16);
------reg_module_start_address18_i <= reg_module_strt_addr_i(17);
------reg_module_start_address19_i <= reg_module_strt_addr_i(18);
------reg_module_start_address20_i <= reg_module_strt_addr_i(19);
------reg_module_start_address21_i <= reg_module_strt_addr_i(20);
------reg_module_start_address22_i <= reg_module_strt_addr_i(21);
------reg_module_start_address23_i <= reg_module_strt_addr_i(22);
------reg_module_start_address24_i <= reg_module_strt_addr_i(23);
------reg_module_start_address25_i <= reg_module_strt_addr_i(24);
------reg_module_start_address26_i <= reg_module_strt_addr_i(25);
------reg_module_start_address27_i <= reg_module_strt_addr_i(26);
------reg_module_start_address28_i <= reg_module_strt_addr_i(27);
------reg_module_start_address29_i <= reg_module_strt_addr_i(28);
------reg_module_start_address30_i <= reg_module_strt_addr_i(29);
------reg_module_start_address31_i <= reg_module_strt_addr_i(30);
------reg_module_start_address32_i <= reg_module_strt_addr_i(31);
end implementation;
|
-- $Id: rlink_sp1c.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_sp1c - syn
-- Description: rlink_core8 + serport_1clock combo
--
-- Dependencies: rlink_core8
-- serport/serport_1clock
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
-- 2011-12-09 437 13.1 O40d xc3s1000-4 337 733 64 469 s 9.8 - -
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 437 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
entity rlink_sp1c is -- rlink_core8+serport_1clock combo
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
IFAWIDTH : natural := 5; -- input fifo address width (0=none)
OFAWIDTH : natural := 5; -- output fifo address width (0=none)
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
SER_MONI : out serport_moni_type -- serport: monitor port
);
end entity rlink_sp1c;
architecture syn of rlink_sp1c is
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
begin
CORE : rlink_core8
generic map (
ATOWIDTH => ATOWIDTH,
ITOWIDTH => ITOWIDTH,
CPREF => CPREF,
ENAPIN_RLMON => ENAPIN_RLMON,
ENAPIN_RBMON => ENAPIN_RBMON)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
SERPORT : serport_1clock
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT,
RXFAWIDTH => IFAWIDTH,
TXFAWIDTH => OFAWIDTH)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => ENAESC,
RXDATA => RLB_DI,
RXVAL => RLB_ENA,
RXHOLD => RLB_BUSY,
TXDATA => RLB_DO,
TXENA => RLB_VAL,
TXBUSY => RLB_HOLD,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
end syn;
|
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Testbench for the generic adder.
library ieee;
use ieee.std_logic_1164.all;
entity adder_tb is
end adder_tb;
architecture TB of adder_tb is
signal a, b, sum : std_logic_vector(3 downto 0);
signal c_in, c_out : std_logic;
begin
-- Instantiate the unit under test (UUT)
UUT : entity work.adder
generic map (
WIDTH => 4
)
port map (
a => a,
b => b,
c_in => c_in,
sum => sum,
c_out => c_out
);
-- Stimulus process
process
begin
a <= (others => '0');
b <= (others => '0');
c_in <= '0';
wait for 10 ns;
a <= "0010";
b <= "1000";
wait for 10 ns;
a <= "0111";
b <= "1000";
wait for 10 ns;
c_in <= '1';
wait;
end process;
end TB;
|
----------------------------------------------------------------------------------
-- Company: Digilent RO
-- Engineer: Mircea Dabacan
--
-- Create Date: 12:57:12 03/01/2008
-- Design Name:
-- Module Name: MouseRefComp - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This is the structural VHDL code of the
-- Digilent Mouse Reference Component.
-- It instantiates three components:
-- - ps2interface
-- - mouse_controller
-- - resolution_mouse_informer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.vga_mouse_pkg.all;
entity mousecomp is
port (
clk : in std_logic;
resolution : in std_logic;
rst : in std_logic;
switch : in std_logic;
left : out std_logic;
middle : out std_logic;
new_event : out std_logic;
right : out std_logic;
busy : out std_logic;
xpos : out std_logic_vector(9 downto 0);
ypos : out std_logic_vector(9 downto 0);
zpos : out std_logic_vector(3 downto 0);
ps2_clk : inout std_logic;
ps2_data : inout std_logic
);
end mousecomp;
architecture structural of mousecomp is
signal TX_DATA : std_logic_vector(7 downto 0);
signal bitSetMaxX : std_logic;
signal vecValue : std_logic_vector(9 downto 0);
signal bitRead : std_logic;
signal bitWrite : std_logic;
signal bitErr : std_logic;
signal bitSetX : std_logic;
signal bitSetY : std_logic;
signal bitSetMaxY : std_logic;
signal vecRxData : std_logic_vector(7 downto 0);
begin
MouseCtrlInst : mouse_controller
port map (
clk => clk,
rst => rst,
read => bitRead,
write => bitWrite,
err => bitErr,
setmax_x => bitSetMaxX,
setmax_y => bitSetMaxY,
setx => bitSetX,
sety => bitSetY,
value(9 downto 0) => vecValue(9 downto 0),
rx_data(7 downto 0) => vecRxData(7 downto 0),
tx_data(7 downto 0) => TX_DATA(7 downto 0),
left => left,
middle => middle,
right => right,
xpos(9 downto 0) => xpos(9 downto 0),
ypos(9 downto 0) => ypos(9 downto 0),
zpos(3 downto 0) => zpos(3 downto 0),
new_event => new_event
);
ResMouseInfInst : resolution_mouse_informer
port map (
clk => clk,
resolution => resolution,
rst => rst,
switch => switch,
setmax_x => bitSetMaxX,
setmax_y => bitSetMaxY,
setx => bitSetX,
sety => bitSetY,
value(9 downto 0) => vecValue(9 downto 0)
);
Pss2Inst : ps2interface
port map (
clk => clk,
rst => rst,
tx_data(7 downto 0) => TX_DATA(7 downto 0),
read => bitRead,
write => bitWrite,
busy => busy,
err => bitErr,
rx_data(7 downto 0) => vecRxData(7 downto 0),
ps2_clk => ps2_clk,
ps2_data => ps2_data
);
end structural;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity set_gmem_m_axi;
architecture behave of set_gmem_m_axi is
component set_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component set_gmem_m_axi_write;
component set_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component set_gmem_m_axi_read;
component set_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component set_gmem_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : set_gmem_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : set_gmem_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : set_gmem_m_axi_write
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : set_gmem_m_axi_read
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity set_gmem_m_axi_fifo;
architecture behave of set_gmem_m_axi_fifo is
signal push, pop, data_vld : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if rdreq = '1' then
full_n_tmp <= '1';
elsif push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity set_gmem_m_axi_decoder;
architecture behav of set_gmem_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity set_gmem_m_axi_throttl;
architecture behav of set_gmem_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity set_gmem_m_axi_read;
architecture behave of set_gmem_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component set_gmem_m_axi_fifo;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
fifo_rreq : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_rreq_valid,
full_n => rreq_ack,
rdreq => fifo_rreq_read,
wrreq => rreq_valid,
q => fifo_rreq_data,
data => rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : set_gmem_m_axi_fifo
generic map (
DATA_BITS => BUS_DATA_WIDTH + 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => beat_valid,
full_n => RREADY,
rdreq => next_beat,
wrreq => RVALID,
q => data_pack,
data => fifo_rresp_rdata);
fifo_rresp_rdata <= (RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity set_gmem_m_axi_write;
architecture behave of set_gmem_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal burst_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal resp_total : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal resp_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : BOOLEAN;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component set_gmem_m_axi_fifo;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
fifo_wreq : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_wreq_valid,
full_n => wreq_ack,
rdreq => fifo_wreq_read,
wrreq => wreq_valid,
q => fifo_wreq_data,
data => wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when last_sect and next_sect else '0';
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_wreq then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_sect then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_sect else '0';
burst_end <= sect_end;
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop and last_loop and last_sect_buf = '1' else '0';
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_sect and first_sect then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_loop then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
fifo_wdata : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_DW + USER_DW/8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => data_valid,
full_n => wdata_ack,
rdreq => next_data,
wrreq => wdata_valid,
q => data_pack,
data => fifo_wdata_wstrb);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component set_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component set_gmem_m_axi_decoder;
begin
-- Instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : set_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : set_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : set_gmem_m_axi_fifo
generic map (
DATA_BITS => C_M_AXI_ADDR_WIDTH - 12,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => resp_match,
wrreq => fifo_resp_w,
q => resp_total,
data => burst_cnt);
fifo_resp_to_user : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
resp_match <= '1' when (resp_cnt = resp_total and need_wrsp = '1') else '0';
next_resp <= BVALID = '1' and resp_ready = '1';
resp_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
resp_cnt <= (others => '0');
elsif (resp_match = '1' and next_resp) then
resp_cnt <= (others => '0');
resp_cnt(0) <= '1';
elsif (next_resp) then
resp_cnt <= resp_cnt + 1;
end if;
end if;
end if;
end process resp_cnt_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp) then
bresp_tmp <= BRESP;
elsif (next_resp and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity set_gmem_m_axi;
architecture behave of set_gmem_m_axi is
component set_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component set_gmem_m_axi_write;
component set_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component set_gmem_m_axi_read;
component set_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component set_gmem_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : set_gmem_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : set_gmem_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : set_gmem_m_axi_write
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : set_gmem_m_axi_read
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity set_gmem_m_axi_fifo;
architecture behave of set_gmem_m_axi_fifo is
signal push, pop, data_vld : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if rdreq = '1' then
full_n_tmp <= '1';
elsif push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity set_gmem_m_axi_decoder;
architecture behav of set_gmem_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity set_gmem_m_axi_throttl;
architecture behav of set_gmem_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity set_gmem_m_axi_read;
architecture behave of set_gmem_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component set_gmem_m_axi_fifo;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
fifo_rreq : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_rreq_valid,
full_n => rreq_ack,
rdreq => fifo_rreq_read,
wrreq => rreq_valid,
q => fifo_rreq_data,
data => rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : set_gmem_m_axi_fifo
generic map (
DATA_BITS => BUS_DATA_WIDTH + 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => beat_valid,
full_n => RREADY,
rdreq => next_beat,
wrreq => RVALID,
q => data_pack,
data => fifo_rresp_rdata);
fifo_rresp_rdata <= (RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity set_gmem_m_axi_write;
architecture behave of set_gmem_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal burst_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal resp_total : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal resp_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : BOOLEAN;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component set_gmem_m_axi_fifo;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
fifo_wreq : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_wreq_valid,
full_n => wreq_ack,
rdreq => fifo_wreq_read,
wrreq => wreq_valid,
q => fifo_wreq_data,
data => wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when last_sect and next_sect else '0';
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_wreq then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_sect then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_sect else '0';
burst_end <= sect_end;
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop and last_loop and last_sect_buf = '1' else '0';
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_sect and first_sect then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_loop then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
fifo_wdata : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_DW + USER_DW/8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => data_valid,
full_n => wdata_ack,
rdreq => next_data,
wrreq => wdata_valid,
q => data_pack,
data => fifo_wdata_wstrb);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component set_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component set_gmem_m_axi_decoder;
begin
-- Instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : set_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : set_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : set_gmem_m_axi_fifo
generic map (
DATA_BITS => C_M_AXI_ADDR_WIDTH - 12,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => resp_match,
wrreq => fifo_resp_w,
q => resp_total,
data => burst_cnt);
fifo_resp_to_user : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
resp_match <= '1' when (resp_cnt = resp_total and need_wrsp = '1') else '0';
next_resp <= BVALID = '1' and resp_ready = '1';
resp_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
resp_cnt <= (others => '0');
elsif (resp_match = '1' and next_resp) then
resp_cnt <= (others => '0');
resp_cnt(0) <= '1';
elsif (next_resp) then
resp_cnt <= resp_cnt + 1;
end if;
end if;
end if;
end process resp_cnt_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp) then
bresp_tmp <= BRESP;
elsif (next_resp and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity set_gmem_m_axi;
architecture behave of set_gmem_m_axi is
component set_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component set_gmem_m_axi_write;
component set_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component set_gmem_m_axi_read;
component set_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component set_gmem_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : set_gmem_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : set_gmem_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : set_gmem_m_axi_write
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : set_gmem_m_axi_read
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity set_gmem_m_axi_fifo;
architecture behave of set_gmem_m_axi_fifo is
signal push, pop, data_vld : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if rdreq = '1' then
full_n_tmp <= '1';
elsif push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity set_gmem_m_axi_decoder;
architecture behav of set_gmem_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity set_gmem_m_axi_throttl;
architecture behav of set_gmem_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity set_gmem_m_axi_read;
architecture behave of set_gmem_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component set_gmem_m_axi_fifo;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
fifo_rreq : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_rreq_valid,
full_n => rreq_ack,
rdreq => fifo_rreq_read,
wrreq => rreq_valid,
q => fifo_rreq_data,
data => rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : set_gmem_m_axi_fifo
generic map (
DATA_BITS => BUS_DATA_WIDTH + 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => beat_valid,
full_n => RREADY,
rdreq => next_beat,
wrreq => RVALID,
q => data_pack,
data => fifo_rresp_rdata);
fifo_rresp_rdata <= (RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity set_gmem_m_axi_write;
architecture behave of set_gmem_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal burst_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal resp_total : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal resp_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : BOOLEAN;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component set_gmem_m_axi_fifo;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
fifo_wreq : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_wreq_valid,
full_n => wreq_ack,
rdreq => fifo_wreq_read,
wrreq => wreq_valid,
q => fifo_wreq_data,
data => wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when last_sect and next_sect else '0';
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_wreq then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_sect then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_sect else '0';
burst_end <= sect_end;
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop and last_loop and last_sect_buf = '1' else '0';
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_sect and first_sect then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_loop then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
fifo_wdata : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_DW + USER_DW/8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => data_valid,
full_n => wdata_ack,
rdreq => next_data,
wrreq => wdata_valid,
q => data_pack,
data => fifo_wdata_wstrb);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component set_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component set_gmem_m_axi_decoder;
begin
-- Instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : set_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : set_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : set_gmem_m_axi_fifo
generic map (
DATA_BITS => C_M_AXI_ADDR_WIDTH - 12,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => resp_match,
wrreq => fifo_resp_w,
q => resp_total,
data => burst_cnt);
fifo_resp_to_user : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
resp_match <= '1' when (resp_cnt = resp_total and need_wrsp = '1') else '0';
next_resp <= BVALID = '1' and resp_ready = '1';
resp_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
resp_cnt <= (others => '0');
elsif (resp_match = '1' and next_resp) then
resp_cnt <= (others => '0');
resp_cnt(0) <= '1';
elsif (next_resp) then
resp_cnt <= resp_cnt + 1;
end if;
end if;
end if;
end process resp_cnt_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp) then
bresp_tmp <= BRESP;
elsif (next_resp and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity set_gmem_m_axi;
architecture behave of set_gmem_m_axi is
component set_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component set_gmem_m_axi_write;
component set_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component set_gmem_m_axi_read;
component set_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component set_gmem_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : set_gmem_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : set_gmem_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : set_gmem_m_axi_write
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : set_gmem_m_axi_read
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity set_gmem_m_axi_fifo;
architecture behave of set_gmem_m_axi_fifo is
signal push, pop, data_vld : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if rdreq = '1' then
full_n_tmp <= '1';
elsif push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity set_gmem_m_axi_decoder;
architecture behav of set_gmem_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity set_gmem_m_axi_throttl;
architecture behav of set_gmem_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity set_gmem_m_axi_read;
architecture behave of set_gmem_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component set_gmem_m_axi_fifo;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
fifo_rreq : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_rreq_valid,
full_n => rreq_ack,
rdreq => fifo_rreq_read,
wrreq => rreq_valid,
q => fifo_rreq_data,
data => rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : set_gmem_m_axi_fifo
generic map (
DATA_BITS => BUS_DATA_WIDTH + 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => beat_valid,
full_n => RREADY,
rdreq => next_beat,
wrreq => RVALID,
q => data_pack,
data => fifo_rresp_rdata);
fifo_rresp_rdata <= (RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity set_gmem_m_axi_write;
architecture behave of set_gmem_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal burst_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal resp_total : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal resp_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : BOOLEAN;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component set_gmem_m_axi_fifo;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
fifo_wreq : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_wreq_valid,
full_n => wreq_ack,
rdreq => fifo_wreq_read,
wrreq => wreq_valid,
q => fifo_wreq_data,
data => wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when last_sect and next_sect else '0';
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_wreq then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_sect then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_sect else '0';
burst_end <= sect_end;
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop and last_loop and last_sect_buf = '1' else '0';
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_sect and first_sect then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_loop then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
fifo_wdata : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_DW + USER_DW/8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => data_valid,
full_n => wdata_ack,
rdreq => next_data,
wrreq => wdata_valid,
q => data_pack,
data => fifo_wdata_wstrb);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component set_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component set_gmem_m_axi_decoder;
begin
-- Instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : set_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : set_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : set_gmem_m_axi_fifo
generic map (
DATA_BITS => C_M_AXI_ADDR_WIDTH - 12,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => resp_match,
wrreq => fifo_resp_w,
q => resp_total,
data => burst_cnt);
fifo_resp_to_user : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
resp_match <= '1' when (resp_cnt = resp_total and need_wrsp = '1') else '0';
next_resp <= BVALID = '1' and resp_ready = '1';
resp_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
resp_cnt <= (others => '0');
elsif (resp_match = '1' and next_resp) then
resp_cnt <= (others => '0');
resp_cnt(0) <= '1';
elsif (next_resp) then
resp_cnt <= resp_cnt + 1;
end if;
end if;
end if;
end process resp_cnt_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp) then
bresp_tmp <= BRESP;
elsif (next_resp and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ab
--
-- Generated
-- by: wig
-- on: Wed Nov 2 10:48:49 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ab-e.vhd,v 1.1 2005/11/02 12:53:46 wig Exp $
-- $Date: 2005/11/02 12:53:46 $
-- $Log: ent_ab-e.vhd,v $
-- Revision 1.1 2005/11/02 12:53:46 wig
-- fixed issue 20051018d and more
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.66 2005/10/24 15:43:48 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.38 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_ab
--
entity ent_ab is
-- Generics:
-- No Generated Generics for Entity ent_ab
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_ab
p_mix_sig_20051018d_go : out std_ulogic_vector(31 downto 0);
p_mix_sigrev_20051018d_go : out std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity ent_ab
);
end ent_ab;
--
-- End of Generated Entity ent_ab
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc153.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p16n01i00153pkg is
procedure P1 (a : in integer; b: inout integer);
end ch04030202_p01601_03_pkg;
package body c04s03b02x02p16n01i00153pkg is
procedure P1 (a: in integer; b: inout integer) is
begin
b := a;
end;
end c04s03b02x02p16n01i00153pkg;
use work.c04s03b02x02p16n01i00153pkg.all;
ENTITY c04s03b02x02p16n01i00153ent IS
END c04s03b02x02p16n01i00153ent;
ARCHITECTURE c04s03b02x02p16n01i00153arch OF c04s03b02x02p16n01i00153ent IS
BEGIN
TESTING: PROCESS
variable x : real := 1.0;
BEGIN
P1 (10, b => x); -- Failure_here
-- b and x have different types
assert FALSE
report "***FAILED TEST: c04s03b02x02p16n01i00153 - Type mismatch."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p16n01i00153arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc153.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p16n01i00153pkg is
procedure P1 (a : in integer; b: inout integer);
end ch04030202_p01601_03_pkg;
package body c04s03b02x02p16n01i00153pkg is
procedure P1 (a: in integer; b: inout integer) is
begin
b := a;
end;
end c04s03b02x02p16n01i00153pkg;
use work.c04s03b02x02p16n01i00153pkg.all;
ENTITY c04s03b02x02p16n01i00153ent IS
END c04s03b02x02p16n01i00153ent;
ARCHITECTURE c04s03b02x02p16n01i00153arch OF c04s03b02x02p16n01i00153ent IS
BEGIN
TESTING: PROCESS
variable x : real := 1.0;
BEGIN
P1 (10, b => x); -- Failure_here
-- b and x have different types
assert FALSE
report "***FAILED TEST: c04s03b02x02p16n01i00153 - Type mismatch."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p16n01i00153arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc153.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c04s03b02x02p16n01i00153pkg is
procedure P1 (a : in integer; b: inout integer);
end ch04030202_p01601_03_pkg;
package body c04s03b02x02p16n01i00153pkg is
procedure P1 (a: in integer; b: inout integer) is
begin
b := a;
end;
end c04s03b02x02p16n01i00153pkg;
use work.c04s03b02x02p16n01i00153pkg.all;
ENTITY c04s03b02x02p16n01i00153ent IS
END c04s03b02x02p16n01i00153ent;
ARCHITECTURE c04s03b02x02p16n01i00153arch OF c04s03b02x02p16n01i00153ent IS
BEGIN
TESTING: PROCESS
variable x : real := 1.0;
BEGIN
P1 (10, b => x); -- Failure_here
-- b and x have different types
assert FALSE
report "***FAILED TEST: c04s03b02x02p16n01i00153 - Type mismatch."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p16n01i00153arch;
|
--------------------------------------------------------------------------------
-- Entity: usb_trace_adapter
-- Date:2018-07-15
-- Author: Gideon
--
-- Description: Encodes USB data into 1480A compatible data format
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_trace_adapter is
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_cmd : in std_logic;
rx_ourdata : in std_logic;
rx_store : in std_logic;
tx_first : in std_logic;
usb_data : out std_logic_vector(7 downto 0);
usb_valid : out std_logic;
usb_rxcmd : out std_logic );
end entity;
architecture arch of usb_trace_adapter is
signal tx_latch : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if tx_first = '1' and tx_latch = '0' then
tx_latch <= '1';
elsif rx_ourdata = '1' then
tx_latch <= '0';
end if;
-- What is what?
-- Case 1: We are sending: first byte is PID, we need to translate it
usb_rxcmd <= '0';
usb_data <= rx_data;
if rx_ourdata = '1' then
usb_valid <= '1';
if tx_latch = '1' then
usb_data <= not(rx_data(3 downto 0)) & rx_data(3 downto 0);
end if;
elsif rx_cmd = '1' then
usb_rxcmd <= '1';
usb_valid <= '1';
elsif rx_store = '1' then
usb_valid <= '1';
end if;
if reset = '1' then
tx_latch <= '0';
end if;
end if;
end process;
end architecture;
|
package elide is
end package;
package body elide is
function func1(x : bit_vector) return bit_vector is
alias a : bit_vector(x'length - 1 downto 0) is x;
variable r : bit_vector(x'length - 1 downto 0);
begin
for i in r'range loop
-- The bounds check for r(i) here should be optimised away
r(i) := a(i);
end loop;
return r;
end function;
end package body;
|
package elide is
end package;
package body elide is
function func1(x : bit_vector) return bit_vector is
alias a : bit_vector(x'length - 1 downto 0) is x;
variable r : bit_vector(x'length - 1 downto 0);
begin
for i in r'range loop
-- The bounds check for r(i) here should be optimised away
r(i) := a(i);
end loop;
return r;
end function;
end package body;
|
package elide is
end package;
package body elide is
function func1(x : bit_vector) return bit_vector is
alias a : bit_vector(x'length - 1 downto 0) is x;
variable r : bit_vector(x'length - 1 downto 0);
begin
for i in r'range loop
-- The bounds check for r(i) here should be optimised away
r(i) := a(i);
end loop;
return r;
end function;
end package body;
|
package elide is
end package;
package body elide is
function func1(x : bit_vector) return bit_vector is
alias a : bit_vector(x'length - 1 downto 0) is x;
variable r : bit_vector(x'length - 1 downto 0);
begin
for i in r'range loop
-- The bounds check for r(i) here should be optimised away
r(i) := a(i);
end loop;
return r;
end function;
end package body;
|
package elide is
end package;
package body elide is
function func1(x : bit_vector) return bit_vector is
alias a : bit_vector(x'length - 1 downto 0) is x;
variable r : bit_vector(x'length - 1 downto 0);
begin
for i in r'range loop
-- The bounds check for r(i) here should be optimised away
r(i) := a(i);
end loop;
return r;
end function;
end package body;
|
-------------------------------------------------------------------------------
--! @file phyActGen-rtl-ea.vhd
--
--! @brief Phy activity generator
--
--! @details The phy activity generator generates a free-running clock-synchronous
--! packet activity signal. This signal can be used to drive an LED.
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity phyActGen is
generic (
--! Generated activity frequency of oActivity [Hz]
gActivityFreq : natural := 6;
--! Clock frequency of iClk [Hz]
gClkFreq : natural := 50e6
);
port (
--! Reset
iRst : in std_logic;
--! Clock
iClk : in std_logic;
--! MAC Tx enable signal
iTxEnable : in std_logic;
--! MAC Rx data valid signal
iRxValid : in std_logic;
--! Generated activity signal
oActivity : out std_logic
);
end phyActGen;
architecture rtl of phyActGen is
--! Obtain maximum counter value to achieve activity frequency
constant cCntMaxValue : natural := gClkFreq / gActivityFreq;
--! Obtain counter width
constant cCntWidth : natural := logDualis(cCntMaxValue);
--! The counter
signal counter : std_logic_vector(cCntWidth-1 downto 0);
--! Constant for counter value zero
constant cCntIsZero : std_logic_vector(counter'range) := (others => cInactivated);
--! Terminal counter
signal counterTc : std_logic;
--! Trigger activity in next cycle due to packet activity
signal triggerActivity : std_logic;
--! Enable activity
signal enableActivity : std_logic;
begin
oActivity <= counter(counter'high) when enableActivity = cActivated else
cInactivated;
ledCntr : process(iRst, iClk)
begin
if iRst = cActivated then
triggerActivity <= cInactivated;
enableActivity <= cInactivated;
elsif rising_edge(iClk) then
--monoflop, of course no default value!
if triggerActivity = cActivated and counterTc = cActivated then
--counter overflow and activity within last cycle
enableActivity <= cActivated;
elsif counterTc = cActivated then
--counter overflow but no activity
enableActivity <= cInactivated;
end if;
--monoflop, of course no default value!
if counterTc = cActivated then
--count cycle over, reset trigger
triggerActivity <= cInactivated;
elsif iTxEnable = cActivated or iRxValid = cActivated then
--activity within cycle
triggerActivity <= cActivated;
end if;
end if;
end process;
theFreeRunCnt : process(iClk, iRst)
begin
if iRst = cActivated then
counter <= (others => cInactivated);
elsif iClk = cActivated and iClk'event then
counter <= std_logic_vector(unsigned(counter) - 1);
end if;
end process;
counterTc <= cActivated when counter = cCntIsZero else
cInactivated;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
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