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library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1734.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s04b00x00p02n01i01734ent IS
begin
l1: assert false
report "Labeled concurrent assert OK in entity."
severity note ;
assert false
report "Unlabeled concurrent assert OK in entity."
severity note ;
END c09s04b00x00p02n01i01734ent;
ARCHITECTURE c09s04b00x00p02n01i01734arch OF c09s04b00x00p02n01i01734ent IS
BEGIN
l2: assert false
report "Labeled concurrent assert OK in architecture."
severity note ;
assert false
report "Unlabeled concurrent assert OK in architecture."
severity note ;
B : block
BEGIN
l1: assert false
report "Labeled concurrent assert OK in block."
severity note ;
assert false
report "Unlabeled concurrent assert OK in block."
severity note ;
assert FALSE
report "***PASSED TEST: c09s04b00x00p02n01i01734 - This test is passed if and only if we get other six assertion sentence."
severity NOTE;
end block B;
END c09s04b00x00p02n01i01734arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1734.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s04b00x00p02n01i01734ent IS
begin
l1: assert false
report "Labeled concurrent assert OK in entity."
severity note ;
assert false
report "Unlabeled concurrent assert OK in entity."
severity note ;
END c09s04b00x00p02n01i01734ent;
ARCHITECTURE c09s04b00x00p02n01i01734arch OF c09s04b00x00p02n01i01734ent IS
BEGIN
l2: assert false
report "Labeled concurrent assert OK in architecture."
severity note ;
assert false
report "Unlabeled concurrent assert OK in architecture."
severity note ;
B : block
BEGIN
l1: assert false
report "Labeled concurrent assert OK in block."
severity note ;
assert false
report "Unlabeled concurrent assert OK in block."
severity note ;
assert FALSE
report "***PASSED TEST: c09s04b00x00p02n01i01734 - This test is passed if and only if we get other six assertion sentence."
severity NOTE;
end block B;
END c09s04b00x00p02n01i01734arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1734.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s04b00x00p02n01i01734ent IS
begin
l1: assert false
report "Labeled concurrent assert OK in entity."
severity note ;
assert false
report "Unlabeled concurrent assert OK in entity."
severity note ;
END c09s04b00x00p02n01i01734ent;
ARCHITECTURE c09s04b00x00p02n01i01734arch OF c09s04b00x00p02n01i01734ent IS
BEGIN
l2: assert false
report "Labeled concurrent assert OK in architecture."
severity note ;
assert false
report "Unlabeled concurrent assert OK in architecture."
severity note ;
B : block
BEGIN
l1: assert false
report "Labeled concurrent assert OK in block."
severity note ;
assert false
report "Unlabeled concurrent assert OK in block."
severity note ;
assert FALSE
report "***PASSED TEST: c09s04b00x00p02n01i01734 - This test is passed if and only if we get other six assertion sentence."
severity NOTE;
end block B;
END c09s04b00x00p02n01i01734arch;
|
-------------------------------------------------------------------------------
--! @file CipherCore_Control.vhd
--! @author Ekawat (ice) Homsirikamol
--! @brief Control unit for ASCON
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CipherCore_Control is
port (
clk : in std_logic;
rst : in std_logic;
--! Input
bdi : in std_logic_vector(64 -1 downto 0);
key_ready : out std_logic;
key_valid : in std_logic;
key_update : in std_logic;
decrypt : in std_logic;
bdi_ready : out std_logic;
bdi_valid : in std_logic;
bdi_type : in std_logic_vector(3 -1 downto 0);
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_size : in std_logic_vector(4 -1 downto 0);
--! Datapath
en_key : out std_logic;
en_state : out std_logic;
en_npub : out std_logic;
en_cmp : out std_logic;
is_last_ad : out std_logic;
clr_rc : out std_logic;
en_rc : out std_logic;
sel_key_hi : out std_logic;
sel_key_lo : out std_logic;
sel_decrypt : out std_logic;
sel_state : out std_logic_vector(2 -1 downto 0);
sel_tag : out std_logic_vector(2 -1 downto 0);
--! Output
msg_auth_done : out std_logic;
bdo_ready : in std_logic;
bdo_valid : out std_logic
);
end entity CipherCore_Control;
architecture behavior of CipherCore_Control is
type state_type is (S_WAIT_KEY, S_LD_KEY, S_LD_LEN,
S_LD_NPUB0, S_LD_NPUB1,
S_PROCESS, S_WAIT, S_WAIT_OUT_TAG2);
signal state : state_type;
signal nstate : state_type;
constant TOT_ROUND_HI : integer := 12;
constant TOT_ROUND_LO : integer := 6;
signal set_compute_hi : std_logic;
signal set_compute_lo : std_logic;
signal clr_last_ad : std_logic;
signal set_last_ad : std_logic;
signal clr_round : std_logic;
signal en_round : std_logic;
signal clr_tag : std_logic;
signal set_tag : std_logic;
signal is_tag : std_logic;
signal is_decrypt : std_logic;
signal rndcmp : std_logic_vector( 4 -1 downto 0);
signal round : std_logic_vector( 4 -1 downto 0);
begin
p_reg:
process( clk )
begin
if rising_edge( clk ) then
if rst = '1' then
is_last_ad <= '0';
round <= (others => '0');
state <= S_WAIT_KEY;
is_tag <= '0';
is_last_ad <= '0';
sel_key_lo <= '0';
else
state <= nstate;
if (clr_round = '1') then
round <= (others => '0');
elsif (en_round = '1') then
round <= std_logic_vector(unsigned(round) + 1);
end if;
if (clr_last_ad = '1') then
is_last_ad <= '0';
elsif (set_last_ad = '1') then
is_last_ad <= '1';
end if;
if (set_compute_hi = '1') then
rndcmp <= std_logic_vector(to_unsigned((TOT_ROUND_HI-1), 4));
elsif (set_compute_lo = '1') then
rndcmp <= std_logic_vector(to_unsigned((TOT_ROUND_LO-1), 4));
end if;
if (clr_tag = '1' or set_tag = '1') then
sel_key_lo <= '1';
elsif (set_compute_lo = '1') then
sel_key_lo <= '0';
end if;
if (clr_tag = '1') then
is_tag <= '0';
elsif (set_tag = '1') then
is_tag <= '1';
end if;
if (state = S_LD_LEN) then
is_decrypt <= decrypt;
end if;
end if;
end if;
end process;
clr_rc <= clr_round;
en_rc <= en_round;
sel_key_hi <= set_tag;
sel_tag <= is_tag & round(0);
p_state:
process( state, bdi_valid, bdi_type, is_decrypt,
bdi_eot, bdo_ready, bdi, bdi_size,
key_valid, key_update, round, rndcmp, is_tag
)
begin
--! External
key_ready <= '0';
bdi_ready <= '0';
bdo_valid <= '0';
msg_auth_done <= '0';
--! Datapath
en_key <= '0';
en_state <= '0';
en_npub <= '0';
en_cmp <= '0';
set_compute_hi <= '0';
set_compute_lo <= '0';
sel_decrypt <= '0';
sel_state <= "00";
set_tag <= '0';
--! Internal
clr_round <= '0';
clr_tag <= '0';
clr_last_ad <= '0';
set_last_ad <= '0';
en_round <= '0';
nstate <= state;
case state is
when S_WAIT_KEY =>
clr_round <= '1';
clr_tag <= '1';
set_compute_hi <= '1';
if (key_update = '1' or bdi_valid = '1') then
if (key_update = '1') then
nstate <= S_LD_KEY;
else
nstate <= S_LD_LEN;
end if;
end if;
when S_LD_KEY =>
key_ready <= '1';
if (key_valid = '1') then
en_key <= '1';
en_round <= '1';
if (unsigned(round) = 3) then
nstate <= S_LD_LEN;
clr_round <= '1';
end if;
end if;
when S_LD_LEN =>
--! Determine if AD is empty
if (unsigned(bdi(63 downto 32)) = 0) then
set_last_ad <= '1';
else
clr_last_ad <= '1';
end if;
bdi_ready <= '1';
if (bdi_valid = '1') then
nstate <= S_LD_NPUB0;
end if;
when S_LD_NPUB0 =>
--! Store the first Npub block in the register
bdi_ready <= '1';
en_npub <= '1';
if (bdi_valid = '1') then
nstate <= S_LD_NPUB1;
end if;
when S_LD_NPUB1 =>
--! Get the second Npub and start processing
bdi_ready <= '1';
en_state <= '1';
sel_state <= "10";
if (bdi_valid = '1') then
nstate <= S_PROCESS;
end if;
when S_PROCESS =>
--! Process
en_round <= '1';
en_state <= '1';
if (round = rndcmp) then
clr_round <= '1';
nstate <= S_WAIT;
end if;
when S_WAIT =>
--! Load/Output data
sel_state <= "01";
if (is_tag = '1') then
if (is_decrypt = '0' and bdo_ready = '1') then
bdo_valid <= '1';
en_round <= '1';
nstate <= S_WAIT_OUT_TAG2;
elsif (is_decrypt = '1' and bdi_valid = '1') then
bdi_ready <= '1';
en_round <= '1';
en_cmp <= '1';
nstate <= S_WAIT_OUT_TAG2;
end if;
else
if (bdi_valid = '1'
and (bdi_type(2 downto 1) = "00"
or bdo_ready = '1'
or not unsigned(bdi_size) /= 0))
then
bdi_ready <= '1';
en_state <= '1';
if (bdi_type(2 downto 1) = "00") then
set_compute_lo <= '1';
if (bdi_eot = '1') then
set_last_ad <= '1';
end if;
else
if (unsigned(bdi_size) /= 0) then
bdo_valid <= '1';
end if;
clr_last_ad <= '1';
if (is_decrypt = '1'
and unsigned(bdi_size) /= 0)
then
sel_decrypt <= '1';
end if;
if (bdi_eot = '1') then
set_compute_hi <= '1';
set_tag <= '1';
else
set_compute_lo <= '1';
end if;
end if;
nstate <= S_PROCESS;
end if;
end if;
when S_WAIT_OUT_TAG2 =>
if (is_decrypt = '0') then
bdo_valid <= '1';
if (bdo_ready = '1') then
nstate <= S_WAIT_KEY;
end if;
else
bdi_ready <= '1';
if (bdi_valid = '1') then
msg_auth_done <= '1';
nstate <= S_WAIT_KEY;
end if;
end if;
end case;
end process;
end behavior;
|
entity gg is end entity;
architecture aa of gg is
constant foo, bar : boolean := false;
signal x, g, f : integer;
constant h : integer := 6;
type text is file of string;
file output : text open WRITE_MODE is "STD_OUTPUT";
begin
g1: if foo generate
signal x : integer;
begin
x <= 5;
end generate;
g2: if bar generate
g2a: if h < 5 generate
g <= 7;
end generate;
end generate;
g3: for i in 1 to 40 generate
signal x : integer;
begin
f <= h;
end generate;
g4: for i in natural'range generate
end generate;
g5: for i in integer'range generate
begin
end generate;
g6: for i in 1 to 3 generate
component sub_ent is
port (val: out natural);
end component sub_ent; -- OK
begin
end generate;
g7: if true generate
procedure doit is -- OK
begin
write(OUTPUT, "OK." & LF);
end procedure doit;
begin
end generate g7;
end architecture;
|
-- Generates the vga signal for a 640x480 signal
-- Copyright 2014 Erik Zachrisson - [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
entity VGAGenerator is
generic (
DataW : positive := 3;
DivideClk : boolean := true;
Offset : natural := 0
);
port (
Clk : in bit1;
RstN : in bit1;
--
PixelToDisplay : in word(DataW-1 downto 0);
DrawRect : in bit1;
InView : out bit1;
--
Red : out word(DataW-1 downto 0);
Green : out word(DataW-1 downto 0);
Blue : out word(DataW-1 downto 0);
HSync : out bit1;
VSync : out bit1
);
end entity;
architecture rtl of VGAGenerator is
signal PixelClk : bit1;
constant HSyncEnd : positive := 95;
constant HDatBegin : positive := 143;
constant HDatEnd : positive := 783;
constant HPixelEnd : positive := 799;
constant VSyncEnd : positive := 1;
constant VDatBegin : positive := 34;
constant VDatEnd : positive := 514;
constant VLineEnd : positive := 524;
signal hCount : word(bits(HPixelEnd)-1 downto 0);
signal vCount : word(bits(VLineEnd)-1 downto 0);
signal HCountOvfl : bit1;
signal VCountOvfl : bit1;
--
signal InView_i : bit1;
begin
DivClkGen : if DivideClk = true generate
ClkDiv : process (RstN, Clk)
begin
if RstN = '0' then
PixelClk <= '0';
elsif rising_edge(Clk) then
PixelClk <= not PixelClk;
end if;
end process;
end generate;
NoDivClkGen : if DivideClk = false generate
PixelClk <= Clk;
end generate;
HCountOvfl <= '1' when hcount = HPixelEnd else '0';
HCnt : process (RstN, PixelClk)
begin
if RstN = '0' then
hcount <= (others => '0');
elsif rising_edge(PixelClk) then
if (HCountOvfl = '1') then
hcount <= (others => '0');
else
hcount <= hcount + 1;
end if;
end if;
end process;
VCountOvfl <= '1' when vcount = VLineEnd else '0';
VCnt : process (RstN, PixelClk)
begin
if RstN = '0' then
vcount <= (others => '0');
elsif rising_edge(PixelClk) then
if (HCountOvfl = '1') then
if (VCountOvfl = '1') then
vcount <= (others => '0');
else
vcount <= vcount + 1;
end if;
end if;
end if;
end process;
InView_i <= '1' when ((hcount >= HDatBegin - Offset) and (hcount < HDatEnd - Offset)) and ((vcount >= VDatBegin) and (vcount < VDatEnd)) else '0';
InView <= InView_i;
Hsync <= '1' when hcount > HSyncEnd else '0';
Vsync <= '1' when vcount > VSyncEnd else '0';
DrawColorProc : process (PixelToDisplay, DrawRect, InView_i)
begin
Red <= (others => '0');
Green <= (others => '0');
Blue <= (others => '0');
if InView_i = '1' then
Red <= PixelToDisplay;
Green <= PixelToDisplay;
Blue <= PixelToDisplay;
-- Draw green rectangle overlay
if DrawRect = '1' then
Green <= (others => '1');
end if;
end if;
end process;
end architecture rtl;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for vgca_fe
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vgca_fe-e.vhd,v 1.2 2005/04/14 06:53:00 wig Exp $
-- $Date: 2005/04/14 06:53:00 $
-- $Log: vgca_fe-e.vhd,v $
-- Revision 1.2 2005/04/14 06:53:00 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity vgca_fe
--
entity vgca_fe is
-- Generics:
-- No Generated Generics for Entity vgca_fe
-- Generated Port Declaration:
-- No Generated Port for Entity vgca_fe
end vgca_fe;
--
-- End of Generated Entity vgca_fe
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 08 23:35:06 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/system_zed_vga_0_0_stub.vhdl
-- Design : system_zed_vga_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_zed_vga_0_0 is
Port (
clk : in STD_LOGIC;
active : in STD_LOGIC;
rgb565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end system_zed_vga_0_0;
architecture stub of system_zed_vga_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,active,rgb565[15:0],vga_r[3:0],vga_g[3:0],vga_b[3:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "zed_vga,Vivado 2016.4";
begin
end;
|
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use ieee.math_complex.all ;
entity lms6002d_model is
port (
-- LMS RX Interface
lms_rx_clock : in std_logic ;
lms_rx_clock_out : out std_logic ;
lms_rx_data : out signed(11 downto 0) ;
lms_rx_enable : in std_logic ;
lms_rx_iq_select : in std_logic ;
-- LMS TX Interface
lms_tx_clock : in std_logic ;
lms_tx_data : in signed(11 downto 0) ;
lms_tx_enable : in std_logic ;
lms_tx_iq_select : in std_logic ;
-- LMS SPI Interface
lms_sclk : in std_logic ;
lms_sen : in std_logic ;
lms_sdio : out std_logic ;
lms_sdo : in std_logic ;
-- LMS Control Interface
lms_pll_out : out std_logic ;
lms_reset : in std_logic
) ;
end entity ; -- lms6002d_model
architecture arch of lms6002d_model is
begin
lms_pll_out <= '0' ;
-- Write transmit samples to a file or drop them on the floor
-- Read receive samples from a file or predetermined tone
lms_rx_clock_out <= lms_rx_clock ;
drive_rx_data : process( lms_reset, lms_rx_clock )
begin
if( lms_reset = '1' ) then
lms_rx_data <= (others =>'0') ;
elsif( rising_edge(lms_rx_clock) or falling_edge(lms_rx_clock) ) then
lms_rx_data <= lms_rx_data + 1 ;
end if ;
end process ;
-- Keep track of the SPI register set
lms_sdio <= '0' ;
end architecture ; -- arch
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: instruction_memory_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : instruction_memory.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 20
-- C_READ_DEPTH_A : 20
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 20
-- C_READ_DEPTH_B : 20
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instruction_memory_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END instruction_memory_prod;
ARCHITECTURE xilinx OF instruction_memory_prod IS
COMPONENT instruction_memory_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : instruction_memory_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: instruction_memory_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : instruction_memory.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 20
-- C_READ_DEPTH_A : 20
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 20
-- C_READ_DEPTH_B : 20
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instruction_memory_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END instruction_memory_prod;
ARCHITECTURE xilinx OF instruction_memory_prod IS
COMPONENT instruction_memory_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : instruction_memory_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: instruction_memory_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : instruction_memory.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 20
-- C_READ_DEPTH_A : 20
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 20
-- C_READ_DEPTH_B : 20
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instruction_memory_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END instruction_memory_prod;
ARCHITECTURE xilinx OF instruction_memory_prod IS
COMPONENT instruction_memory_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : instruction_memory_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: instruction_memory_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : instruction_memory.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 20
-- C_READ_DEPTH_A : 20
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 20
-- C_READ_DEPTH_B : 20
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instruction_memory_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END instruction_memory_prod;
ARCHITECTURE xilinx OF instruction_memory_prod IS
COMPONENT instruction_memory_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : instruction_memory_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: instruction_memory_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : instruction_memory.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 20
-- C_READ_DEPTH_A : 20
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 20
-- C_READ_DEPTH_B : 20
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instruction_memory_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END instruction_memory_prod;
ARCHITECTURE xilinx OF instruction_memory_prod IS
COMPONENT instruction_memory_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : instruction_memory_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity computer_system is
end entity computer_system;
-- code from book
architecture abstract of computer_system is
-- not in book
subtype word is bit_vector(31 downto 0);
type word_vector is array (natural range <>) of word;
function resolve_word ( drivers : word_vector ) return word is
begin
if drivers'length > 0 then
return drivers(drivers'left);
else
return X"00000000";
end if;
end function resolve_word;
-- end not in book
-- . . .
signal address_bus : resolve_word word bus;
signal hold_req : bit;
-- . . .
-- not in book
signal clk : bit := '0';
-- end not in book
begin
cpu : block is
signal guard : boolean := false;
signal cpu_internal_address : word;
-- . . .
begin
cpu_address_driver:
address_bus <= guarded cpu_internal_address;
-- . . . -- other bus drivers
controller : process is
-- . . .
begin
-- . . .
-- . . . -- determine when to disable cpu bus drivers
guard <= false;
wait on clk until hold_req = '0' and clk = '1';
guard <= true; -- re-enable cpu bus drivers
-- . . .
-- not in book
wait until clk = '1';
-- end not in book
end process controller;
-- . . . -- cpu datapath processes
-- not in book
cpu_internal_address <= X"11111111";
-- end not in book
end block cpu;
-- . . . -- blocks for DMA and other modules
-- not in book
clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
-- end not in book
end architecture abstract;
-- end code from book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity computer_system is
end entity computer_system;
-- code from book
architecture abstract of computer_system is
-- not in book
subtype word is bit_vector(31 downto 0);
type word_vector is array (natural range <>) of word;
function resolve_word ( drivers : word_vector ) return word is
begin
if drivers'length > 0 then
return drivers(drivers'left);
else
return X"00000000";
end if;
end function resolve_word;
-- end not in book
-- . . .
signal address_bus : resolve_word word bus;
signal hold_req : bit;
-- . . .
-- not in book
signal clk : bit := '0';
-- end not in book
begin
cpu : block is
signal guard : boolean := false;
signal cpu_internal_address : word;
-- . . .
begin
cpu_address_driver:
address_bus <= guarded cpu_internal_address;
-- . . . -- other bus drivers
controller : process is
-- . . .
begin
-- . . .
-- . . . -- determine when to disable cpu bus drivers
guard <= false;
wait on clk until hold_req = '0' and clk = '1';
guard <= true; -- re-enable cpu bus drivers
-- . . .
-- not in book
wait until clk = '1';
-- end not in book
end process controller;
-- . . . -- cpu datapath processes
-- not in book
cpu_internal_address <= X"11111111";
-- end not in book
end block cpu;
-- . . . -- blocks for DMA and other modules
-- not in book
clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
-- end not in book
end architecture abstract;
-- end code from book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity computer_system is
end entity computer_system;
-- code from book
architecture abstract of computer_system is
-- not in book
subtype word is bit_vector(31 downto 0);
type word_vector is array (natural range <>) of word;
function resolve_word ( drivers : word_vector ) return word is
begin
if drivers'length > 0 then
return drivers(drivers'left);
else
return X"00000000";
end if;
end function resolve_word;
-- end not in book
-- . . .
signal address_bus : resolve_word word bus;
signal hold_req : bit;
-- . . .
-- not in book
signal clk : bit := '0';
-- end not in book
begin
cpu : block is
signal guard : boolean := false;
signal cpu_internal_address : word;
-- . . .
begin
cpu_address_driver:
address_bus <= guarded cpu_internal_address;
-- . . . -- other bus drivers
controller : process is
-- . . .
begin
-- . . .
-- . . . -- determine when to disable cpu bus drivers
guard <= false;
wait on clk until hold_req = '0' and clk = '1';
guard <= true; -- re-enable cpu bus drivers
-- . . .
-- not in book
wait until clk = '1';
-- end not in book
end process controller;
-- . . . -- cpu datapath processes
-- not in book
cpu_internal_address <= X"11111111";
-- end not in book
end block cpu;
-- . . . -- blocks for DMA and other modules
-- not in book
clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
-- end not in book
end architecture abstract;
-- end code from book
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.uart_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--=================================================================================================
entity uart_tx_vvc is
generic (
GC_DATA_WIDTH : natural := 8;
GC_INSTANCE_IDX : natural := 1;
GC_CHANNEL : t_channel := TX;
GC_UART_CONFIG : t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
uart_vvc_tx : inout std_logic := GC_UART_CONFIG.idle_state
);
end entity uart_tx_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of uart_tx_vvc is
constant C_SCOPE : string := get_scope_for_log(C_VVC_NAME, GC_INSTANCE_IDX, GC_CHANNEL);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, GC_CHANNEL);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_uart_vvc_config(TX, GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_uart_vvc_status(TX, GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_uart_transaction_info(TX, GC_INSTANCE_IDX);
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_UART_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(TX, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(TX, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd, executor_is_busy);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Set the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
v_prev_command_was_bfm_access := v_command_is_bfm_access; -- save for inter_bfm_delay
if v_cmd.operation = TRANSMIT then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_prev_command_was_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
when TRANSMIT =>
-- Normalise address and data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "uart_transmit() called with to wide data. " & add_msg_delimiter(v_cmd.msg));
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
-- Call the corresponding procedure in the BFM package.
uart_transmit(data_value => v_normalised_data,
msg => format_msg(v_cmd),
tx => uart_vvc_tx,
config => vvc_config.bfm_config,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel);
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.bit_time;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
|
-- File name: aes_rcu.vhd
-- Created: 2009-03-30
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.1 Initial Design Entry
-- Description: Rijndael RCU
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity aes_rcu is
port (
clk : in std_logic;
nrst : in std_logic;
key_done : in std_logic;
got_key : in std_logic;
got_pt : in std_logic;
send_ct : in std_logic;
p : out g_index;
subblock : out subblock_type;
current_round : out round_type;
start_key : out std_logic;
key_load : out std_logic;
aes_done : out std_logic
);
end entity aes_rcu;
architecture behavioral of aes_rcu is
type state_type is (
idle, e_idle, load_pt, load_key, sub_bytes,
mix_columns, shift_rows, add_round_key,
key_scheduler_start, key_scheduler_wait,
round_start, round_end, block_done, store_ct
);
signal state, next_state : state_type;
signal round_count, next_round_count : round_type;
signal round_count_up, round_count_clr : std_logic;
signal i, next_i : g_index;
signal i_up, i_clr : std_logic;
begin
fsm_reg : process(clk, nrst)
begin
if (nrst = '0') then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process fsm_reg;
fsm_nsl : process(state, round_count, i, key_done, got_pt, got_key, send_ct)
begin
next_state <= state;
case state is
when idle =>
if (got_key = '1') then
next_state <= load_key;
elsif (got_pt = '1') then
next_state <= load_pt;
elsif (send_ct = '1') then
next_state <= store_ct;
else
next_state <= idle;
end if;
when e_idle =>
next_state <= e_idle;
when load_key =>
if (i /= 15) then
next_state <= load_key;
else
next_state <= idle;
end if;
when load_pt =>
if (i /= 15) then
next_state <= load_pt;
else
next_state <= round_start;
end if;
when store_ct =>
if (i /= 15) then
next_state <= store_ct;
else
next_state <= idle;
end if;
when round_start =>
next_state <= key_scheduler_start;
when key_scheduler_start =>
next_state <= key_scheduler_wait;
when key_scheduler_wait =>
if (key_done = '0') then
next_state <= key_scheduler_wait;
elsif (round_count = 0) then
next_state <= add_round_key;
else
next_state <= sub_bytes;
end if;
when sub_bytes =>
if (i /= 15) then
next_state <= sub_bytes;
else
next_state <= shift_rows;
end if;
when shift_rows =>
if (i /= 3) then
next_state <= shift_rows;
elsif (round_count /= 10) then
next_state <= mix_columns;
else
next_state <= add_round_key;
end if;
when mix_columns =>
if (i /= 3) then
next_state <= mix_columns;
else
next_state <= add_round_key;
end if;
when add_round_key =>
if (i /= 15) then
next_state <= add_round_key;
else
next_state <= round_end;
end if;
when round_end =>
if (round_count /= 10) then
next_state <= round_start;
else
next_state <= block_done;
end if;
when block_done =>
next_state <= idle;
when others =>
-- nothing
end case;
end process fsm_nsl;
fsm_output : process(state, i)
begin
i_clr <= '0';
i_up <= '0';
round_count_clr <= '0';
round_count_up <= '0';
start_key <= '0';
aes_done <= '0';
key_load <= '0';
subblock <= identity;
case state is
when idle =>
subblock <= identity;
i_clr <= '1';
round_count_clr <= '1';
when e_idle =>
subblock <= identity;
i_clr <= '1';
round_count_clr <= '1';
when load_key =>
subblock <= identity;
key_load <= '1';
i_up <= '1';
when load_pt =>
subblock <= load_pt;
i_up <= '1';
when store_ct =>
subblock <= store_ct;
i_up <= '1';
when sub_bytes =>
subblock <= sub_bytes;
i_up <= '1';
when shift_rows =>
subblock <= shift_rows;
i_up <= '1';
if (i = 3) then
i_clr <= '1';
end if;
when mix_columns =>
subblock <= mix_columns;
i_up <= '1';
if (i = 3) then
i_clr <= '1';
end if;
when add_round_key =>
subblock <= add_round_key;
i_up <= '1';
when key_scheduler_start =>
subblock <= identity;
start_key <= '1';
when key_scheduler_wait =>
subblock <= identity;
when round_start =>
subblock <= identity;
when round_end =>
subblock <= identity;
round_count_up <= '1';
when block_done =>
aes_done <= '1';
when others =>
-- nothing
end case;
end process fsm_output;
-- leda C_1406 off
round_count_reg : process(clk)
begin
if rising_edge(clk) then
round_count <= next_round_count;
end if;
end process round_count_reg;
-- leda C_1406 on
round_count_nsl : process(round_count, round_count_up, round_count_clr)
variable nrc : round_type;
begin
if (round_count_clr = '1') then
next_round_count <= 0;
elsif (round_count_up = '1') then
if (round_count = 11) then
nrc := 0;
else
nrc := round_count + 1;
end if;
next_round_count <= nrc;
else
next_round_count <= round_count;
end if;
end process round_count_nsl;
-- leda C_1406 off
i_reg : process(clk)
begin
if rising_edge(clk) then
i <= next_i;
end if;
end process i_reg;
-- leda C_1406 on
i_nsl : process(i, i_up, i_clr)
begin
if (i_clr = '1') then
next_i <= 0;
elsif (i_up = '1') then
next_i <= to_integer(to_unsigned(i, 4) + 1);
else
next_i <= i;
end if;
end process i_nsl;
current_round <= round_count;
p <= i;
end architecture behavioral;
architecture behavioral_p of aes_rcu is
type state_type is (
idle, e_idle, load_pt, load_key, sub_bytes,
mix_columns, shift_rows, add_round_key,
key_scheduler_start, key_scheduler_wait,
round_start, round_end, block_done, store_ct
);
signal state, next_state : state_type;
signal round_count, next_round_count : round_type;
signal round_count_up, round_count_clr : std_logic;
signal i, next_i : g_index;
signal i_up, i_clr : std_logic;
begin
fsm_reg : process(clk, nrst)
begin
if (nrst = '0') then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process fsm_reg;
fsm_nsl : process(state, round_count, i, key_done, got_pt, got_key, send_ct)
begin
next_state <= state;
case state is
when idle =>
if (got_key = '1') then
next_state <= load_key;
elsif (got_pt = '1') then
next_state <= load_pt;
elsif (send_ct = '1') then
next_state <= store_ct;
else
next_state <= idle;
end if;
when e_idle =>
next_state <= e_idle;
when load_key =>
if (i /= 15) then
next_state <= load_key;
else
next_state <= idle;
end if;
when load_pt =>
if (i /= 15) then
next_state <= load_pt;
else
next_state <= round_start;
end if;
when store_ct =>
if (i /= 15) then
next_state <= store_ct;
else
next_state <= idle;
end if;
when round_start =>
next_state <= key_scheduler_start;
when key_scheduler_start =>
next_state <= key_scheduler_wait;
when key_scheduler_wait =>
if (key_done = '0') then
next_state <= key_scheduler_wait;
elsif (round_count = 0) then
next_state <= add_round_key;
else
next_state <= sub_bytes;
end if;
when sub_bytes =>
next_state <= shift_rows;
when shift_rows =>
if (round_count /= 10) then
next_state <= mix_columns;
else
next_state <= add_round_key;
end if;
when mix_columns =>
next_state <= add_round_key;
when add_round_key =>
next_state <= round_end;
when round_end =>
if (round_count /= 10) then
next_state <= round_start;
else
next_state <= block_done;
end if;
when block_done =>
next_state <= idle;
when others =>
-- nothing
end case;
end process fsm_nsl;
fsm_output : process(state, i)
begin
i_clr <= '0';
i_up <= '0';
round_count_clr <= '0';
round_count_up <= '0';
start_key <= '0';
aes_done <= '0';
key_load <= '0';
subblock <= identity;
case state is
when idle =>
subblock <= identity;
i_clr <= '1';
round_count_clr <= '1';
when e_idle =>
subblock <= identity;
i_clr <= '1';
round_count_clr <= '1';
when load_key =>
subblock <= identity;
key_load <= '1';
i_up <= '1';
when load_pt =>
subblock <= load_pt;
i_up <= '1';
when store_ct =>
subblock <= store_ct;
i_up <= '1';
when sub_bytes =>
subblock <= sub_bytes;
i_up <= '1';
when shift_rows =>
subblock <= shift_rows;
when mix_columns =>
subblock <= mix_columns;
when add_round_key =>
subblock <= add_round_key;
when key_scheduler_start =>
subblock <= identity;
start_key <= '1';
when key_scheduler_wait =>
subblock <= identity;
when round_start =>
subblock <= identity;
when round_end =>
subblock <= identity;
round_count_up <= '1';
when block_done =>
aes_done <= '1';
when others =>
-- nothing
end case;
end process fsm_output;
-- leda C_1406 off
round_count_reg : process(clk)
begin
if rising_edge(clk) then
round_count <= next_round_count;
end if;
end process round_count_reg;
-- leda C_1406 on
round_count_nsl : process(round_count, round_count_up, round_count_clr)
variable nrc : round_type;
begin
if (round_count_clr = '1') then
next_round_count <= 0;
elsif (round_count_up = '1') then
if (round_count = 11) then
nrc := 0;
else
nrc := round_count + 1;
end if;
next_round_count <= nrc;
else
next_round_count <= round_count;
end if;
end process round_count_nsl;
-- leda C_1406 off
i_reg : process(clk)
begin
if rising_edge(clk) then
i <= next_i;
end if;
end process i_reg;
-- leda C_1406 on
i_nsl : process(i, i_up, i_clr)
begin
if (i_clr = '1') then
next_i <= 0;
elsif (i_up = '1') then
next_i <= to_integer(to_unsigned(i, 4) + 1);
else
next_i <= i;
end if;
end process i_nsl;
current_round <= round_count;
p <= i;
end architecture behavioral_p;
|
-- $Id: opb_ipif.vhd,v 1.2 2004/05/05 23:12:12 gburch Exp $
-------------------------------------------------------------------------------
-- opb_ipif.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: opb_ipif.vhd
--
-- Description: Simple slave OPB IPIF, OPB to IPIC.
--
--
-------------------------------------------------------------------------------
-- Structure: opb_ipif
-- opb_ipif
-- -- opb_bam
-- -- reset_mir
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_Gm_SP2
--
-- Fixed problem with double clock wrce to interrupt control which caused
-- an interrupt to be generated when a user cleared an already pending
-- interrupt.
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
--
-- FLO 05/19/03
-- ^^^^^^
-- Initial version.
-- ~~~~~~
-- GAB 05/05/04
-- ^^^^^^
-- Added change log.
-- Fixed interrupt control double clock wrce
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ipif_common_v1_00_c;
use ipif_common_v1_00_c.ipif_pkg.INTEGER_ARRAY_TYPE;
use ipif_common_v1_00_c.ipif_pkg.SLV64_ARRAY_TYPE;
use ipif_common_v1_00_c.ipif_pkg.calc_num_ce;
use ipif_common_v1_00_c.ipif_pkg.calc_start_ce_index;
use ipif_common_v1_00_c.ipif_pkg.DEPENDENT_PROPS_ARRAY_TYPE;
use ipif_common_v1_00_c.ipif_pkg.get_min_dwidth;
use ipif_common_v1_00_c.ipif_pkg.IPIF_INTR;
use ipif_common_v1_00_c.ipif_pkg.IPIF_RST;
use ipif_common_v1_00_c.ipif_pkg.USER_00;
library opb_ipif_v3_00_a;
use opb_ipif_v3_00_a.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity opb_ipif is
generic
(
C_ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => IPIF_INTR, 1 => IPIF_RST, 2 => USER_00 );
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( x"0000_0000_6000_0000", x"0000_0000_6000_003F", x"0000_0000_6000_0040", x"0000_0000_6000_0043", x"0000_0000_6000_0100", x"0000_0000_6000_01FF" );
C_ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE := ( 32, 32, 32 );
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 16, 1, 8 );
C_ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE := ( 0 => (others => 0) ,1 => (others => 0) ,2 => (others => 0) );
C_PIPELINE_MODEL : integer := 7;
C_DEV_BLK_ID : INTEGER := 1;
C_DEV_MIR_ENABLE : INTEGER := 0;
C_AWIDTH : INTEGER := 32;
C_DWIDTH : INTEGER := 32;
C_FAMILY : string := "virtexe";
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := ( 5, 1 );
C_INCLUDE_DEV_ISC : INTEGER := 1;
C_INCLUDE_DEV_IID : integer := 0;
C_DEV_BURST_ENABLE : INTEGER := 0
);
port
(
OPB_select : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_DWIDTH-1);
OPB_ABus : in std_logic_vector(0 to C_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
OPB_RNW : in std_logic;
OPB_seqAddr : in std_logic;
OPB_xferAck : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_DWIDTH-1);
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
Bus2IP_CS : out std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
Bus2IP_CE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_Data : out std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_BE : out std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RNW : out std_logic;
Bus2IP_Burst : out std_logic;
IP2Bus_Data : in std_logic_vector(0 to C_DWIDTH*calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
IP2Bus_Ack : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_Error : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_Retry : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_ToutSup : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_PostedWrInh : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
OPB_Clk : in std_logic;
Bus2IP_Clk : out std_logic;
IP2Bus_Clk : in std_logic;
Reset : in std_logic;
Bus2IP_Reset : out std_logic;
IP2Bus_Intr : in std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1);
Device_Intr : out std_logic
);
end entity opb_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of opb_ipif is
component opb_bam is
generic
(
C_ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => IPIF_INTR, 1 => IPIF_RST, 2 => USER_00 );
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( x"0000_0000_6000_0000", x"0000_0000_6000_003F", x"0000_0000_6000_0040", x"0000_0000_6000_0043", x"0000_0000_6000_0100", x"0000_0000_6000_01FF" );
C_ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE := ( 32, 32, 32 );
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 16, 1, 8 );
C_ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE := ( 0 => (others => 0) ,1 => (others => 0) ,2 => (others => 0) );
C_PIPELINE_MODEL : integer := 7;
C_DEV_BLK_ID : INTEGER := 1;
C_DEV_MIR_ENABLE : INTEGER := 0;
C_AWIDTH : INTEGER := 32;
C_DWIDTH : INTEGER := 32;
C_FAMILY : string := "virtexe";
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := ( 5, 1 );
C_INCLUDE_DEV_ISC : INTEGER := 1;
C_INCLUDE_DEV_IID : integer := 0;
C_DEV_BURST_ENABLE : INTEGER := 0
);
port
(
OPB_select : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_DWIDTH-1);
OPB_ABus : in std_logic_vector(0 to C_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
OPB_RNW : in std_logic;
OPB_seqAddr : in std_logic;
OPB_xferAck : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_DWIDTH-1);
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
Bus2IP_CS : out std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
Bus2IP_CE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_Data : out std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_BE : out std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RNW : out std_logic;
Bus2IP_Burst : out std_logic;
IP2Bus_Data : in std_logic_vector(0 to C_DWIDTH*calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
IP2Bus_Ack : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_Error : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_Retry : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_ToutSup : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_PostedWrInh : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
OPB_Clk : in std_logic;
Bus2IP_Clk : out std_logic;
IP2Bus_Clk : in std_logic;
Reset : in std_logic;
Bus2IP_Reset : out std_logic;
IP2Bus_Intr : in std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1);
Device_Intr : out std_logic
);
end component opb_bam;
begin ------------------------------------------------------------------------
OPB_BAM_I : opb_bam
generic map
(
C_ARD_ID_ARRAY => C_ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => C_ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => C_ARD_DEPENDENT_PROPS_ARRAY,
C_PIPELINE_MODEL => C_PIPELINE_MODEL,
C_DEV_BLK_ID => C_DEV_BLK_ID,
C_DEV_MIR_ENABLE => C_DEV_MIR_ENABLE,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY,
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_ISC => C_INCLUDE_DEV_ISC,
C_INCLUDE_DEV_IID => C_INCLUDE_DEV_IID,
C_DEV_BURST_ENABLE => C_DEV_BURST_ENABLE
)
port map
(
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_xferAck => OPB_xferAck,
Sln_DBus => Sln_DBus,
Sln_xferAck => Sln_xferAck,
Sln_errAck => Sln_errAck,
Sln_retry => Sln_retry,
Sln_toutSup => Sln_toutSup,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_CE => Bus2IP_CE,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_Burst => Bus2IP_Burst,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_Ack => IP2Bus_Ack,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_Retry => IP2Bus_Retry,
IP2Bus_ToutSup => IP2Bus_ToutSup,
IP2Bus_PostedWrInh => IP2Bus_PostedWrInh,
OPB_Clk => OPB_Clk,
Bus2IP_Clk => Bus2IP_Clk,
IP2Bus_Clk => IP2Bus_Clk,
Reset => Reset,
Bus2IP_Reset => Bus2IP_Reset,
IP2Bus_Intr => IP2Bus_Intr,
Device_Intr => Device_Intr
);
end architecture imp;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.defs.all;
use work.irfir;
entity test_irfir is
port (q : out signed36);
end test_irfir;
architecture behavioural of test_irfir is
signal d : signed18 := (others => '0');
signal clk : std_logic := '0';
begin
uut: entity irfir
generic map (acc_width => 36, out_width => 36)
port map (d => d, q => q, clk => clk);
process
begin
loop
wait for 0.5 ns;
clk <= '0';
wait for 0.5 ns;
clk <= '1';
end loop;
end process;
process
begin
wait for 920 ns;
loop
for i in 1 to 4 loop
for j in 1 to 80 loop
wait until falling_edge(clk);
end loop;
d <= d + 1;
end loop;
end loop;
end process;
end;
|
-- wasca_rst_controller.vhd
-- Generated using ACDS version 15.1 193
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity wasca_rst_controller;
architecture rtl of wasca_rst_controller is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of wasca_rst_controller
|
library ieee;
use ieee.std_logic_1164.all;
entity dff15 is
port (q : out std_logic;
d : std_logic;
clk : std_logic);
end dff15;
architecture behav of dff15 is
begin
process (clk) is
variable m : std_logic;
begin
if rising_edge (clk) then
m := d;
end if;
q <= not m;
end process;
end behav;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Thu Jun 29 16:41:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro ../../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.2 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.2 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- modifiy vhdl_use_arch
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
typedef vhdl_use_arch_def std_ulogic_vector;
-- end of vhdl_use_arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_a
-- No Generated Generics
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic; -- Input Port
port_o_a : out std_ulogic; -- Output Port
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_i_a2 : in std_ulogic; -- Input Port
sig_o_a2 : out std_ulogic -- Output Port
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic; -- Will create p_mix_sig_1_go port
port_b_3 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 : in std_ulogic; -- Bus, single bits go to outside, will create p_mix_sig_5_2_2_go __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0); -- Conflicting definition
port_b_6o : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2) -- VHDL intermediate needed (port name)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
component ent_c
-- No Generated Generics
-- Generated Generics for Entity ent_c
-- End of Generated Generics for Entity ent_c
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
Use macro vhdl_hook_arch_body
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_c
inst_c: ent_c
;
-- End of Generated Instance Port Map for inst_c
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
architecture RTL of FIFO is
function func1 return integer is begin end function F_FUNC1_f;
FUNCTION FUNC1 RETURN INTEGER IS BEGIN END FUNCTION F_FUNC1_f;
procedure proc1 is begin end procedure Proc1;
begin
end architecture RTL;
|
library verilog;
use verilog.vl_types.all;
entity ClockGenerator is
port(
clock : out vl_logic;
reset : out vl_logic
);
end ClockGenerator;
|
library verilog;
use verilog.vl_types.all;
entity ClockGenerator is
port(
clock : out vl_logic;
reset : out vl_logic
);
end ClockGenerator;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: String related functions and types
--
-- Description:
-- -------------------------------------
-- For detailed documentation see below.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
--use PoC.FileIO.all;
package strings is
-- default fill and string termination character for fixed size strings
-- ===========================================================================
-- WORKAROUND: for Altera Quartus-II
-- Version: 15.0
-- Issue:
-- character 0 (NUL) causes Quartus-II to crash, if uses to pad STRINGs
-- characters < 32 (control characters) are not supported in Quartus-II
-- characters > 127 are not supported in VHDL files (strict ASCII files)
-- character 255 craches ISE log window (created by 'CHARACTER'val(255)')
-- Solution:
-- PoC uses backtick "`" as a fill and termination symbol, if a Quartus-II
-- synthesis environment is detected.
constant C_POC_NUL : character := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`');
-- Type declarations
-- ===========================================================================
subtype T_RAWCHAR is std_logic_vector(7 downto 0);
type T_RAWSTRING is array (natural range <>) of T_RAWCHAR;
-- testing area:
-- ===========================================================================
function to_IPStyle(str : string) return T_IPSTYLE;
-- to_char
function to_char(Value : std_logic) return character;
function to_char(rawchar : T_RAWCHAR) return character;
function to_HexChar(Value : natural) return character;
function to_HexChar(Value : unsigned) return character;
-- chr_is* function
function chr_isDigit(chr : character) return boolean;
function chr_isLowerHexDigit(chr : character) return boolean;
function chr_isUpperHexDigit(chr : character) return boolean;
function chr_isHexDigit(chr : character) return boolean;
function chr_isLower(chr : character) return boolean;
function chr_isLowerAlpha(chr : character) return boolean;
function chr_isUpper(chr : character) return boolean;
function chr_isUpperAlpha(chr : character) return boolean;
function chr_isAlpha(chr : character) return boolean;
-- raw_format_* functions
function raw_format_bool_bin(Value : boolean) return string;
function raw_format_bool_chr(Value : boolean) return string;
function raw_format_bool_str(Value : boolean) return string;
function raw_format_slv_bin(slv : std_logic_vector) return string;
function raw_format_slv_oct(slv : std_logic_vector) return string;
function raw_format_slv_dec(slv : std_logic_vector) return string;
function raw_format_slv_hex(slv : std_logic_vector) return string;
function raw_format_nat_bin(Value : natural) return string;
function raw_format_nat_oct(Value : natural) return string;
function raw_format_nat_dec(Value : natural) return string;
function raw_format_nat_hex(Value : natural) return string;
-- str_format_* functions
function str_format(Value : REAL; precision : natural := 3) return string;
-- to_string
function to_string(Value : boolean) return string;
function to_string(Value : integer; base : positive := 10) return string;
function to_string(slv : std_logic_vector; format : character; Length : natural := 0; fill : character := '0') return string;
function to_string(rawstring : T_RAWSTRING) return string;
function to_string(Value : T_BCD_VECTOR) return string;
-- to_slv
function to_slv(rawstring : T_RAWSTRING) return std_logic_vector;
-- digit subtypes incl. error Value (-1)
subtype T_DIGIT_BIN is integer range -1 to 1;
subtype T_DIGIT_OCT is integer range -1 to 7;
subtype T_DIGIT_DEC is integer range -1 to 9;
subtype T_DIGIT_HEX is integer range -1 to 15;
-- to_digit*
function to_digit_bin(chr : character) return T_DIGIT_BIN;
function to_digit_oct(chr : character) return T_DIGIT_OCT;
function to_digit_dec(chr : character) return T_DIGIT_DEC;
function to_digit_hex(chr : character) return T_DIGIT_HEX;
function to_digit(chr : character; base : character := 'd') return integer;
-- to_natural*
function to_natural_bin(str : string) return integer;
function to_natural_oct(str : string) return integer;
function to_natural_dec(str : string) return integer;
function to_natural_hex(str : string) return integer;
function to_natural(str : string; base : character := 'd') return integer;
-- to_raw*
function to_RawChar(char : character) return T_RAWCHAR;
function to_RawString(str : string) return T_RAWSTRING;
-- resize
function resize(str : string; size : positive; FillChar : character := C_POC_NUL) return string;
-- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING;
-- Character functions
function chr_toLower(chr : character) return character;
function chr_toUpper(chr : character) return character;
-- String functions
function str_length(str : string) return natural;
function str_equal(str1 : string; str2 : string) return boolean;
function str_match(str1 : string; str2 : string) return boolean;
function str_imatch(str1 : string; str2 : string) return boolean;
function str_pos(str : string; chr : character; start : natural := 0) return integer;
function str_pos(str : string; pattern : string; start : natural := 0) return integer;
function str_ipos(str : string; chr : character; start : natural := 0) return integer;
function str_ipos(str : string; pattern : string; start : natural := 0) return integer;
function str_find(str : string; chr : character) return boolean;
function str_find(str : string; pattern : string) return boolean;
function str_ifind(str : string; chr : character) return boolean;
function str_ifind(str : string; pattern : string) return boolean;
function str_replace(str : string; pattern : string; replace : string) return string;
function str_substr(str : string; start : integer := 0; Length : integer := 0) return string;
function str_ltrim(str : string; char : character := ' ') return string;
function str_rtrim(str : string; char : character := ' ') return string;
function str_trim(str : string) return string;
function str_calign(str : string; Length : natural; FillChar : character := ' ') return string;
function str_lalign(str : string; Length : natural; FillChar : character := ' ') return string;
function str_ralign(str : string; Length : natural; FillChar : character := ' ') return string;
function str_toLower(str : string) return string;
function str_toUpper(str : string) return string;
end package;
package body strings is
--
function to_IPStyle(str : string) return T_IPSTYLE is
begin
for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop
if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(i))) then
return T_IPSTYLE'val(i);
end if;
end loop;
report "Unknown IPStyle: '" & str & "'" severity FAILURE;
return IPSTYLE_UNKNOWN;
end function;
-- to_char
-- ===========================================================================
function to_char(Value : std_logic) return character is
begin
case Value is
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when others => return 'X';
end case;
end function;
function to_char(rawchar : T_RAWCHAR) return character is
begin
return character'val(to_integer(unsigned(rawchar)));
end function;
--
function to_HexChar(Value : natural) return character is
constant HEX : string := "0123456789ABCDEF";
begin
return ite(Value < 16, HEX(Value+1), 'X');
end function;
function to_HexChar(Value : unsigned) return character is
begin
return to_HexChar(to_integer(Value));
end function;
-- chr_is* function
function chr_isDigit(chr : character) return boolean is
begin
return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9'));
end function;
function chr_isLowerHexDigit(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f'));
end function;
function chr_isUpperHexDigit(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F'));
end function;
function chr_isHexDigit(chr : character) return boolean is
begin
return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr);
end function;
function chr_isLower(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr);
end function;
function chr_isLowerAlpha(chr : character) return boolean is
begin
return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z'));
end function;
function chr_isUpper(chr : character) return boolean is
begin
return chr_isUpperAlpha(chr);
end function;
function chr_isUpperAlpha(chr : character) return boolean is
begin
return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z'));
end function;
function chr_isAlpha(chr : character) return boolean is
begin
return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr);
end function;
-- raw_format_* functions
-- ===========================================================================
function raw_format_bool_bin(Value : boolean) return string is
begin
return ite(Value, "1", "0");
end function;
function raw_format_bool_chr(Value : boolean) return string is
begin
return ite(Value, "T", "F");
end function;
function raw_format_bool_str(Value : boolean) return string is
begin
return str_toUpper(boolean'image(Value));
end function;
function raw_format_slv_bin(slv : std_logic_vector) return string is
variable Value : std_logic_vector(slv'length - 1 downto 0);
variable Result : string(1 to slv'length);
variable j : natural;
begin
-- convert input slv to a downto ranged vector and normalize range to slv'low = 0
Value := movez(ite(slv'ascending, descend(slv), slv));
-- convert each bit to a character
j := 0;
for i in Result'reverse_range loop
Result(i) := to_char(Value(j));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_oct(slv : std_logic_vector) return string is
variable Value : std_logic_vector(slv'length - 1 downto 0);
variable Digit : std_logic_vector(2 downto 0);
variable Result : string(1 to div_ceil(slv'length, 3));
variable j : natural;
begin
-- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3
Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3));
-- convert 3 bit to a character
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 3) + 2 downto (j * 3));
Result(i) := to_HexChar(unsigned(Digit));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_slv_dec(slv : std_logic_vector) return string is
variable Value : std_logic_vector(slv'length - 1 downto 0);
variable Result : string(1 to div_ceil(slv'length, 3));
subtype TT_BCD is integer range 0 to 31;
type TT_BCD_VECTOR is array(natural range <>) of TT_BCD;
variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0);
variable Carry : T_UINT_8;
variable Pos : natural;
begin
Temp := (others => 0);
Pos := 0;
-- convert input slv to a downto ranged vector
Value := ite(slv'ascending, descend(slv), slv);
for i in Value'range loop
Carry := to_int(Value(i));
for j in Temp'reverse_range loop
Temp(j) := Temp(j) * 2 + Carry;
Carry := to_int(Temp(j) > 9);
Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10);
end loop;
end loop;
for i in Result'range loop
Result(i) := to_HexChar(Temp(Temp'high - i + 1));
if ((Result(i) /= '0') and (Pos = 0)) then
Pos := i;
end if;
end loop;
-- trim leading zeros, except the last
return Result(imin(Pos, Result'high) to Result'high);
end function;
function raw_format_slv_hex(slv : std_logic_vector) return string is
variable Value : std_logic_vector(4*div_ceil(slv'length, 4) - 1 downto 0);
variable Digit : std_logic_vector(3 downto 0);
variable Result : string(1 to div_ceil(slv'length, 4));
variable j : natural;
begin
Value := resize(slv, Value'length);
j := 0;
for i in Result'reverse_range loop
Digit := Value((j * 4) + 3 downto (j * 4));
Result(i) := to_HexChar(unsigned(Digit));
j := j + 1;
end loop;
return Result;
end function;
function raw_format_nat_bin(Value : natural) return string is
begin
return raw_format_slv_bin(to_slv(Value, log2ceilnz(Value+1)));
end function;
function raw_format_nat_oct(Value : natural) return string is
begin
return raw_format_slv_oct(to_slv(Value, log2ceilnz(Value+1)));
end function;
function raw_format_nat_dec(Value : natural) return string is
begin
return integer'image(Value);
end function;
function raw_format_nat_hex(Value : natural) return string is
begin
return raw_format_slv_hex(to_slv(Value, log2ceilnz(Value+1)));
end function;
-- str_format_* functions
-- ===========================================================================
function str_format(Value : REAL; precision : natural := 3) return string is
constant s : REAL := sign(Value);
constant val : REAL := Value * s;
constant int : integer := integer(floor(val));
constant frac : integer := integer(round((val - real(int)) * 10.0**precision));
constant overflow : boolean := frac >= 10**precision;
constant int2 : integer := ite(overflow, int+1, int);
constant frac2 : integer := ite(overflow, frac-10**precision, frac);
constant frac_str : string := integer'image(frac2);
constant res : string := integer'image(int2) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str;
begin
return ite ((s < 0.0), "-" & res, res);
end function;
-- to_string
-- ===========================================================================
function to_string(Value : boolean) return string is
begin
return raw_format_bool_str(Value);
end function;
-- convert an integer Value to a STRING using an arbitrary base
function to_string(Value : integer; base : positive := 10) return string is
constant absValue : natural := abs Value;
constant len : positive := log10ceilnz(absValue);
variable power : positive;
variable Result : string(1 to len);
begin
power := 1;
if base = 10 then
return integer'image(Value);
else
for i in len downto 1 loop
Result(i) := to_HexChar(absValue / power mod base);
power := power * base;
end loop;
if Value < 0 then
return '-' & Result;
else
return Result;
end if;
end if;
end function;
-- QUESTION: rename to slv_format(..) ?
function to_string(slv : std_logic_vector; format : character; Length : natural := 0; fill : character := '0') return string is
constant int : integer := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0);
constant str : string := integer'image(int);
constant bin_len : positive := slv'length;
constant dec_len : positive := str'length;--log10ceilnz(int);
constant hex_len : positive := ite(((bin_len mod 4) = 0), (bin_len / 4), (bin_len / 4) + 1);
constant len : natural := ite((format = 'b'), bin_len,
ite((format = 'd'), dec_len,
ite((format = 'h'), hex_len, 0)));
variable j : natural;
variable Result : string(1 to ite((Length = 0), len, imax(len, Length)));
begin
j := 0;
Result := (others => fill);
if (format = 'b') then
for i in Result'reverse_range loop
Result(i) := to_char(slv(j));
j := j + 1;
end loop;
elsif (format = 'd') then
-- TODO: enable big integer conversion
-- if (slv'length < 32) then
-- return INTEGER'image(int);
-- else
-- return raw_format_slv_dec(slv);
-- end if;
Result(Result'length - str'length + 1 to Result'high) := str;
elsif (format = 'h') then
for i in Result'reverse_range loop
Result(i) := to_HexChar(unsigned(slv((j * 4) + 3 downto (j * 4))));
j := j + 1;
end loop;
else
report "Unknown format character: " & format & "." severity FAILURE;
end if;
return Result;
end function;
function to_string(rawstring : T_RAWSTRING) return string is
variable Result : string(1 to rawstring'length);
begin
for i in rawstring'low to rawstring'high loop
Result(i - rawstring'low + 1) := to_char(rawstring(i));
end loop;
return Result;
end function;
function to_string(Value : T_BCD_VECTOR) return string is
variable Result : string(1 to Value'length);
begin
for i in Value'range loop
Result(Result'high - (i - Value'low)) := to_HexChar(unsigned(Value(i)));
end loop;
return Result;
end function;
-- to_slv
-- ===========================================================================
function to_slv(rawstring : T_RAWSTRING) return std_logic_vector is
variable Result : std_logic_vector((rawstring'length * 8) - 1 downto 0);
begin
for i in rawstring'range loop
Result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i);
end loop;
return Result;
end function;
-- to_digit*
-- ===========================================================================
-- convert a binary digit given as CHARACTER to a digit returned as NATURAL; return -1 on error
function to_digit_bin(chr : character) return T_DIGIT_BIN is
begin
case chr is
when '0' => return 0;
when '1' => return 1;
when others => return -1;
end case;
end function;
-- convert an octal digit given as CHARACTER to a digit returned as NATURAL; return -1 on error
function to_digit_oct(chr : character) return T_DIGIT_OCT is
variable dec : integer;
begin
dec := to_digit_dec(chr);
return ite((dec < 8), dec, -1);
end function;
-- convert a adecimal digit given as CHARACTER to a digit returned as NATURAL; return -1 on error
function to_digit_dec(chr : character) return T_DIGIT_DEC is
begin
if chr_isDigit(chr) then
return character'pos(chr) - CHARACTER'pos('0');
else
return -1;
end if;
end function;
-- convert a hexadecimal digit given as CHARACTER to a digit returned as NATURAL; return -1 on error
function to_digit_hex(chr : character) return T_DIGIT_HEX is
begin
if chr_isDigit(chr) then return character'pos(chr) - CHARACTER'pos('0');
elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - CHARACTER'pos('a') + 10;
elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - CHARACTER'pos('A') + 10;
else return -1;
end if;
end function;
-- convert a digit given as CHARACTER to a digit returned as NATURAL; return -1 on error
function to_digit(chr : character; base : character := 'd') return integer is
begin
case base is
when 'b' => return to_digit_bin(chr);
when 'o' => return to_digit_oct(chr);
when 'd' => return to_digit_dec(chr);
when 'h' => return to_digit_hex(chr);
when others => report "Unknown base character: " & base & "." severity FAILURE;
return -1;
end case;
end function;
-- to_natural*
-- ===========================================================================
-- convert a binary number given as STRING to a NATURAL; return -1 on error
function to_natural_bin(str : string) return integer is
variable Result : natural;
variable Digit : integer;
begin
for i in str'range loop
Digit := to_digit_bin(str(i));
if Digit /= -1 then
Result := Result * 2 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
-- convert an octal number given as STRING to a NATURAL; return -1 on error
function to_natural_oct(str : string) return integer is
variable Result : natural;
variable Digit : integer;
begin
for i in str'range loop
Digit := to_digit_oct(str(i));
if Digit /= -1 then
Result := Result * 8 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
-- convert a decimal number given as STRING to a NATURAL; return -1 on error
function to_natural_dec(str : string) return integer is
variable Result : natural;
variable Digit : integer;
begin
-- WORKAROUND: Xilinx Vivado Synth
-- Version: 2014.1
-- Issue:
-- INTEGER'value(...) is not supported by Vivado Synth
-- Solution:
-- implement a manual conversion using shift and multiply
for i in str'range loop
Digit := to_digit_dec(str(i));
if Digit /= -1 then
Result := Result * 10 + Digit;
else
return -1;
end if;
end loop;
return Result; -- INTEGER'value(str);
end function;
-- convert a hexadecimal number given as STRING to a NATURAL; return -1 on error
function to_natural_hex(str : string) return integer is
variable Result : natural;
variable Digit : integer;
begin
for i in str'range loop
Digit := to_digit_hex(str(i));
if Digit /= -1 then
Result := Result * 16 + Digit;
else
return -1;
end if;
end loop;
return Result;
end function;
-- convert a number given as STRING to a NATURAL; return -1 on error
function to_natural(str : string; base : character := 'd') return integer is
begin
case base is
when 'b' => return to_natural_bin(str);
when 'o' => return to_natural_oct(str);
when 'd' => return to_natural_dec(str);
when 'h' => return to_natural_hex(str);
when others => report "Unknown base character: " & base & "." severity FAILURE;
return -1;
end case;
end function;
-- to_raw*
-- ===========================================================================
-- convert a CHARACTER to a RAWCHAR
function to_RawChar(char : character) return T_RAWCHAR is
begin
return std_logic_vector(to_unsigned(character'pos(char), T_RAWCHAR'length));
end function;
-- convert a STRING to a RAWSTRING
function to_RawString(str : string) return T_RAWSTRING is
variable Result : T_RAWSTRING(0 to str'length - 1);
begin
for i in str'low to str'high loop
Result(i - str'low) := to_RawChar(str(i));
end loop;
return Result;
end function;
-- resize
-- ===========================================================================
function resize(str : string; Size : positive; FillChar : character := C_POC_NUL) return string is
constant ConstNUL : string(1 to 1) := (others => C_POC_NUL);
variable Result : string(1 to Size);
begin
Result := (others => FillChar);
if (str'length > 0) then
-- WORKAROUND: for Altera Quartus-II
-- Version: 15.0
-- Issue: array bounds are check regardless of the hierarchy and control flow
Result(1 to bound(Size, 1, str'length)) := ite((str'length > 0), str(1 to imin(Size, str'length)), ConstNUL);
end if;
return Result;
end function;
-- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is
-- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00");
-- variable Result : T_RAWSTRING(1 to size);
-- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is
-- begin
-- if cond then
-- return value1;
-- else
-- return value2;
-- end if;
-- end function;
-- begin
-- Result := (others => FillChar);
-- if (str'length > 0) then
-- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL);
-- end if;
-- return Result;
-- end function;
-- Character functions
-- ===========================================================================
-- convert an upper case CHARACTER into a lower case CHARACTER
function chr_toLower(chr : character) return character is
begin
if chr_isUpperAlpha(chr) then
return character'val(character'pos(chr) - character'pos('A') + character'pos('a'));
else
return chr;
end if;
end function;
-- convert a lower case CHARACTER into an upper case CHARACTER
function chr_toUpper(chr : character) return character is
begin
if chr_isLowerAlpha(chr) then
return character'val(character'pos(chr) - character'pos('a') + character'pos('A'));
else
return chr;
end if;
end function;
-- String functions
-- ===========================================================================
-- count the length of a POC_NUL terminated STRING
function str_length(str : string) return natural is
begin
for i in str'range loop
if str(i) = C_POC_NUL then
return i - str'low;
end if;
end loop;
return str'length;
end function;
-- compare two STRINGs for equality
-- pre-check the string lengthes to suppress warnings for unqual sized string comparisons.
-- QUESTION: overload "=" operator?
function str_equal(str1 : string; str2 : string) return boolean is
begin
if str1'length /= str2'length then
return FALSE;
else
return (str1 = str2);
end if;
end function;
-- compare two POC_NUL terminated STRINGs
function str_match(str1 : string; str2 : string) return boolean is
constant len : natural := imin(str1'length, str2'length);
begin
-- if both strings are empty
if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if;
-- compare char by char
for i in str1'low to str1'low + len - 1 loop
if (str1(i) /= str2(str2'low + (i - str1'low))) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return FALSE;
elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then
return TRUE;
end if;
end loop;
-- check special cases,
return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal
((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len
((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len
end function;
-- compare two POC_NUL terminated STRINGs; case insentitve
function str_imatch(str1 : string; str2 : string) return boolean is
begin
return str_match(str_toLower(str1), str_toLower(str2));
end function;
-- search for chr in a STRING and return the position; return -1 on error
function str_pos(str : string; chr : character; start : natural := 0) return integer is
begin
for i in imax(str'low, start) to str'high loop
exit when (str(i) = C_POC_NUL);
if str(i) = chr then
return i;
end if;
end loop;
return -1;
end function;
-- search for pattern in a STRING and return the position; return -1 on error
-- QUESTION: implement KMP algorithm?
function str_pos(str : string; pattern : string; start : natural := 0) return integer is
begin
for i in imax(str'low, start) to (str'high - pattern'length + 1) loop
exit when (str(i) = C_POC_NUL);
if (str(i to i + pattern'length - 1) = pattern) then
return i;
end if;
end loop;
return -1;
end function;
-- search for chr in a STRING and return the position; case insentitve; return -1 on error
function str_ipos(str : string; chr : character; start : natural := 0) return integer is
begin
return str_pos(str_toLower(str), chr_toLower(chr));
end function;
-- search for pattern in a STRING and return the position; case insentitve; return -1 on error
function str_ipos(str : string; pattern : string; start : natural := 0) return integer is
begin
return str_pos(str_toLower(str), str_toLower(pattern));
end function;
-- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is
-- variable PrefixTable : T_INTVEC(0 to str2'length);
-- variable j : INTEGER;
-- begin
-- -- construct prefix table for KMP algorithm
-- j := -1;
-- PrefixTable(0) := -1;
-- for i in str2'range loop
-- while ((j >= 0) and str2(j + 1) /= str2(i)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- PrefixTable(i - 1) := j + 1;
-- end loop;
--
-- -- search pattern str2 in text str1
-- j := 0;
-- for i in str1'range loop
-- while ((j >= 0) and str1(i) /= str2(j + 1)) loop
-- j := PrefixTable(j);
-- end loop;
--
-- j := j + 1;
-- if ((j + 1) = str2'high) then
-- return i - str2'length + 1;
-- end if;
-- end loop;
--
-- return -1;
-- end function;
-- check if chr exists in STRING str
function str_find(str : string; chr : character) return boolean is
begin
return (str_pos(str, chr) > 0);
end function;
-- check if pattern exists in STRING str
function str_find(str : string; pattern : string) return boolean is
begin
return (str_pos(str, pattern) > 0);
end function;
-- check if chr exists in STRING str; case insentitve
function str_ifind(str : string; chr : character) return boolean is
begin
return (str_ipos(str, chr) > 0);
end function;
-- check if pattern exists in STRING str; case insentitve
function str_ifind(str : string; pattern : string) return boolean is
begin
return (str_ipos(str, pattern) > 0);
end function;
-- replace a pattern in a STRING str by the STRING replace
function str_replace(str : string; pattern : string; replace : string) return string is
variable pos : integer;
begin
pos := str_pos(str, pattern);
if pos > 0 then
if pos = 1 then
return replace & str(pattern'length + 1 to str'length);
elsif (pos = str'length - pattern'length + 1) then
return str(1 to str'length - pattern'length) & replace;
else
return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length);
end if;
else
return str;
end if;
end function;
-- return a sub-string of STRING str
-- EXAMPLES:
-- 123456789ABC
-- input string: "Hello World."
-- low=1; high=12; length=12
--
-- str_substr("Hello World.", 0, 0) => "Hello World." - copy all
-- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string
-- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters
-- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary
function str_substr(str : string; start : integer := 0; Length : integer := 0) return string is
variable StartOfString : positive;
variable EndOfString : positive;
begin
if start < 0 then -- start is negative -> start substring at right string boundary
StartOfString := str'high + start + 1;
elsif start = 0 then -- start is zero -> start substring at left string boundary
StartOfString := str'low;
else -- start is positive -> start substring at left string boundary + offset
StartOfString := start;
end if;
if Length < 0 then -- Length is negative -> end substring at length'th character before right string boundary
EndOfString := str'high + Length;
elsif Length = 0 then -- Length is zero -> end substring at right string boundary
EndOfString := str'high;
else -- Length is positive -> end substring at StartOfString + Length
EndOfString := StartOfString + Length - 1;
end if;
if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity FAILURE; end if;
if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity FAILURE; end if;
return str(StartOfString to EndOfString);
end function;
-- left-trim the STRING str
function str_ltrim(str : string; char : character := ' ') return string is
begin
for i in str'range loop
if str(i) /= char then
return str(i to str'high);
end if;
end loop;
return "";
end function;
-- right-trim the STRING str
function str_rtrim(str : string; char : character := ' ') return string is
begin
for i in str'reverse_range loop
if str(i) /= char then
return str(str'low to i);
end if;
end loop;
return "";
end function;
-- remove POC_NUL string termination characters
function str_trim(str : string) return string is
begin
return str(str'low to str'low + str_length(str) - 1);
end function;
-- center-align a STRING str in a FillChar filled STRING of length Length
function str_calign(str : string; Length : natural; FillChar : character := ' ') return string is
constant Start : positive := (Length - str'length) / 2;
variable Result : string(1 to Length);
begin
Result := (others => FillChar);
Result(Start to (Start + str'length)) := str;
return Result;
end function;
-- left-align a STRING str in a FillChar filled STRING of length Length
function str_lalign(str : string; Length : natural; FillChar : character := ' ') return string is
variable Result : string(1 to Length);
begin
Result := (others => FillChar);
Result(1 to str'length) := str;
return Result;
end function;
-- right-align a STRING str in a FillChar filled STRING of length Length
function str_ralign(str : string; Length : natural; FillChar : character := ' ') return string is
variable Result : string(1 to Length);
begin
Result := (others => FillChar);
Result((Length - str'length + 1) to Length) := str;
return Result;
end function;
-- convert an upper case STRING into a lower case STRING
function str_toLower(str : string) return string is
variable Result : string(str'range);
begin
for i in str'range loop
Result(i) := chr_toLower(str(i));
end loop;
return Result;
end function;
-- convert a lower case STRING into an upper case STRING
function str_toUpper(str : string) return string is
variable Result : string(str'range);
begin
for i in str'range loop
Result(i) := chr_toUpper(str(i));
end loop;
return Result;
end function;
end package body;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_ab
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ab-rtl-conf-c.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_ab-rtl-conf-c.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_ab_rtl_conf / ent_ab
--
configuration ent_ab_rtl_conf of ent_ab is
for rtl
-- Generated Configuration
end for;
end ent_ab_rtl_conf;
--
-- End of Generated Configuration ent_ab_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--finally synthesis all component;
entity Input_Display is
port(adder1,adder2:in bit_vector(7 downto 0);
adder1_hex_display,adder2_hex_display:out bit_vector(15 downto 0);
sum:out bit_vector(23 downto 0)
);
end entity Input_Display;
architecture combination of Input_Display is
--bcd4-adder;
component Bcd2digitAdder
port (adder1,adder2:in bit_vector(7 downto 0);
result:out bit_vector(7 downto 0);
finalCarry:out bit);
end component;
--7segment decoder;
component Segment7Decoder is
port (bcd : in bit_vector(3 downto 0); --BCD input
segment7 : out bit_vector(6 downto 0) -- 7 bit decoded output.
);
end component;
signal result_in_bcd:bit_vector(7 downto 0);
signal HighBit:bit;
signal tower:bit_vector(3 downto 0):="0000";
signal point_value:bit:='1';
begin
tower(0)<= HighBit;
Bcdadder:Bcd2digitAdder port map(adder1,adder2,result_in_bcd,HighBit);
--display Adder1;
--lower 4
Dis7Segment_adder1_lower:Segment7Decoder port map(adder1(3 downto 0),adder1_hex_display(7 downto 1));
--higher 4
Dis7Segment_adder1_higer:Segment7Decoder port map(adder1(7 downto 4),adder1_hex_display(15 downto 9));
--point in bit 8,0
--display Adder2 ;
--lower 4
Dis7Segment_adder2_lower:Segment7Decoder port map(adder2(3 downto 0),adder2_hex_display(7 downto 1));
--higher 4
Dis7Segment_adder2_higer:Segment7Decoder port map(adder2(7 downto 4),adder2_hex_display(15 downto 9));
--display result_in_bcd
Dis7Segment_result_lower:Segment7Decoder port map(result_in_bcd(3 downto 0),sum( 7 downto 1));
Dis7Segment_result_higer:Segment7Decoder port map(result_in_bcd(7 downto 4),sum(15 downto 9));
Dis7Segment_result_tower:Segment7Decoder port map(tower ,sum(23 downto 17));
--point in bit 16,8,0;
--reset All of Point in segment ;
adder1_hex_display(0)<=point_value;
adder1_hex_display(8)<=point_value;
adder2_hex_display(0)<=point_value;
adder2_hex_display(8)<=point_value;
sum(0)<=point_value;
sum(8)<=point_value;
sum(16)<=point_value;
end architecture combination; |
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer:
--
-- Create Date: 08:51:42 09/08/2015
-- Design Name:
-- Module Name: BinaryGray_Converter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Generic Gray to Binary Converter
-- using Loops
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BinaryGray_Converter is
-- Declaration of Generics
generic (
-- n defines the number of bits to be
-- converted
n : integer := 16);
Port ( Bin : in STD_LOGIC_VECTOR (n-1 downto 0);
Gray : out STD_LOGIC_VECTOR (n-1 downto 0));
end BinaryGray_Converter;
architecture Behavioral of BinaryGray_Converter is
begin
-- Binary to Gray conversion using Dataflow
-- Gray(3) <= Bin(3);
-- Gray(2) <= Bin(3) xor Bin(2);
-- Gray(1) <= Bin(2) xor Bin(1);
-- Gray(0) <= Bin(1) xor Bin(0);
-- Binary to Gray conversion using Loops
Gray(n-1) <= Bin(n-1);
for_loop:
for i in n-2 downto 0 generate
begin
Gray(i) <= Bin(i+1) xor Bin(i);
end generate;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Generic testbench element for a specific feature set
--
-- $Id: tb_elem.vhd,v 1.7 2005-04-07 20:43:36 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_elem is
generic (
chip_type_g : string := "none";
has_sd_card_g : integer := 1
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
eos_o : out boolean
);
end tb_elem;
library ieee;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.spi_boot_pack.all;
use work.tb_pack.all;
architecture behav of tb_elem is
component chip
port (
clk_i : in std_logic;
reset_i : in std_logic;
set_sel_n_i : in std_logic_vector(3 downto 0);
spi_clk_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_data_in_i : in std_logic;
spi_data_out_o : out std_logic;
start_i : in std_logic;
mode_i : in std_logic;
config_n_o : out std_logic;
detached_o : out std_logic;
cfg_init_n_i : in std_logic;
cfg_done_i : in std_logic;
dat_done_i : in std_logic;
cfg_clk_o : out std_logic;
cfg_dat_o : out std_logic
);
end component;
component card
generic (
card_type_g : string := "none";
is_sd_card_g : integer := 1
);
port (
spi_clk_i : in std_logic;
spi_cs_n_i : in std_logic;
spi_data_i : in std_logic;
spi_data_o : out std_logic
);
end component;
signal reset_s : std_logic;
-- SPI interface signals
signal spi_clk_s : std_logic;
signal spi_data_to_card_s : std_logic;
signal spi_data_from_card_s : std_logic;
signal spi_cs_n_s : std_logic;
-- config related signals
signal start_s : std_logic;
signal mode_s : std_logic;
signal config_n_s : std_logic;
signal cfg_init_n_s : std_logic;
signal cfg_done_s : std_logic;
signal dat_done_s : std_logic;
signal cfg_clk_s : std_logic;
signal cfg_dat_s : std_logic;
signal data_s : unsigned(7 downto 0);
signal set_sel_n_s : std_logic_vector(3 downto 0);
constant verbose_c : boolean := false;
begin
-- weak pull-ups
spi_clk_s <= 'H';
spi_cs_n_s <= 'H';
spi_data_to_card_s <= 'H';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
dut_b : chip
port map (
clk_i => clk_i,
reset_i => reset_s,
set_sel_n_i => set_sel_n_s,
spi_clk_o => spi_clk_s,
spi_cs_n_o => spi_cs_n_s,
spi_data_in_i => spi_data_from_card_s,
spi_data_out_o => spi_data_to_card_s,
start_i => start_s,
mode_i => mode_s,
config_n_o => config_n_s,
detached_o => open,
cfg_init_n_i => cfg_init_n_s,
cfg_done_i => cfg_done_s,
dat_done_i => dat_done_s,
cfg_clk_o => cfg_clk_s,
cfg_dat_o => cfg_dat_s
);
card_b : card
generic map (
card_type_g => chip_type_g,
is_sd_card_g => has_sd_card_g
)
port map (
spi_clk_i => spi_clk_s,
spi_cs_n_i => spi_cs_n_s,
spi_data_i => spi_data_to_card_s,
spi_data_o => spi_data_from_card_s
);
-----------------------------------------------------------------------------
-- DUT Stimuli
--
stim: process
procedure rise_cfg_clk(num : integer) is
begin
for i in 1 to num loop
wait until cfg_clk_s'event and cfg_clk_s = '1';
end loop;
end rise_cfg_clk;
-- procedure fall_cfg_clk(num : integer) is
-- begin
-- for i in 1 to num loop
-- wait until cfg_clk_s'event and cfg_clk_s = '0';
-- end loop;
-- end fall_cfg_clk;
procedure rise_clk(num : integer) is
begin
for i in 1 to num loop
wait until clk_i'event and clk_i = '1';
end loop;
end rise_clk;
procedure read_check_byte(ref : unsigned(7 downto 0)) is
variable byte_v : unsigned(7 downto 0);
variable dump_line : line;
begin
for bit in 7 downto 0 loop
rise_cfg_clk(1);
byte_v(bit) := cfg_dat_s;
end loop;
data_s <= byte_v;
if byte_v /= ref then
write(dump_line, chip_type_g);
write(dump_line, string'(" at "));
write(dump_line, now);
write(dump_line, string'(": read_check_byte failed "));
write(dump_line, to_integer(byte_v));
write(dump_line, string'(" "));
write(dump_line, to_integer(ref));
writeline(output, dump_line);
end if;
end read_check_byte;
variable dump_line : line;
variable addr_v : unsigned(31 downto 0);
variable temp_v : unsigned( 7 downto 0);
variable set_sel_v : unsigned(3 downto 0);
begin
-- default assignments
-- these defaults show the required pull resistors
-- except start_i as this must be pulled high for automatic start
start_s <= '0';
mode_s <= '1';
cfg_init_n_s <= '1';
cfg_done_s <= '0';
dat_done_s <= '1';
data_s <= (others => '1');
addr_v := (others => '0');
eos_o <= false;
set_sel_n_s <= (others => '1');
reset_s <= '0';
-- loop through some sets
for set in 0 to 3 loop
set_sel_v := to_unsigned(set, 4);
addr_v(23 downto 20) := set_sel_v; -- must match num_bits_per_img_g
-- plus width_img_cnt_g
set_sel_n_s <= not std_logic_vector(set_sel_v);
assert not verbose_c
report chip_type_g & ": Processing set " & to_string(set)
severity note;
wait for 100 us;
reset_s <= '1';
assert not verbose_c
report chip_type_g & ": Requesting image 0"
severity note;
-- signal start
start_s <= '1';
mode_s <= '1';
cfg_done_s <= '0';
addr_v(19 downto 0) := (others => '0');
wait until config_n_s = '0';
-- run through configuration sequence
rise_clk(1);
cfg_init_n_s <= '0';
rise_clk(3);
cfg_init_n_s <= '1';
-- and receive 32 bytes from image 0
for i in 1 to 32 loop
temp_v := addr_v(0) & calc_crc(addr_v);
read_check_byte(temp_v);
addr_v := addr_v + 1;
end loop;
start_s <= '0';
cfg_done_s <= '1';
rise_clk(10);
assert not verbose_c
report chip_type_g & ": Requesting image 1"
severity note;
-- request next image
mode_s <= '0';
start_s <= '1';
addr_v(17 downto 0) := (others => '0');
addr_v(19 downto 18) := "01"; -- must match num_bits_per_img_g in chip-*-a.vhd
dat_done_s <= '0';
-- receive another 32 bytes from image 1
for i in 1 to 32 loop
temp_v := addr_v(0) & calc_crc(addr_v);
read_check_byte(temp_v);
addr_v := addr_v + 1;
end loop;
start_s <= '0';
dat_done_s <= '1';
rise_clk(10);
assert not verbose_c
report chip_type_g & ": Requesting image 2"
severity note;
-- request next image
mode_s <= '1';
start_s <= '1';
addr_v(17 downto 0) := (others => '0');
addr_v(19 downto 18) := "10"; -- must match num_bits_per_img_g in chip-*-a.vhd
wait until config_n_s = '0';
-- run through configuration sequence
rise_clk(1);
cfg_done_s <= '0';
cfg_init_n_s <= '0';
rise_clk(3);
cfg_init_n_s <= '1';
-- receive another 32 bytes from image 2
for i in 1 to 32 loop
temp_v := addr_v(0) & calc_crc(addr_v);
read_check_byte(temp_v);
addr_v := addr_v + 1;
end loop;
start_s <= '0';
cfg_done_s <= '1';
-- give dut a chance to stop current transfer
wait until spi_cs_n_s = '1';
rise_clk(10);
reset_s <= '0';
end loop;
eos_o <= true;
wait;
end process stim;
--
-----------------------------------------------------------------------------
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2005/03/09 19:48:04 arniml
-- make verbosity level switchable
--
-- Revision 1.5 2005/03/08 22:06:21 arniml
-- added set selection
--
-- Revision 1.4 2005/02/17 18:59:23 arniml
-- clarify wording for images
--
-- Revision 1.3 2005/02/16 19:34:56 arniml
-- add weak pull-ups for SPI lines
--
-- Revision 1.2 2005/02/13 17:14:03 arniml
-- change dat_done handling
--
-- Revision 1.1 2005/02/08 21:09:20 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
-- Module Name: InputGate - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
Entity test5 is pOrt (
a : in std_logic_vector(0 to 7);
d : out std_logic_vector(0 to Wsize-1);
e : out std_logic_Vector(0 to aAbB - 1);
f : in unsigned(0 to aAbB - 1);
g : in unsignEd (0 to aAbB - 1);
h : in Unsigned ( 0 to aAbB - 1 );
b : in Std_logic_Vector(0 to 3);
c : out std_Logic );
end test;
architecture Behavioral of test is
begin
c <= a and b;
end Behavioral;
|
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_aes;
use lib_aes.all;
------------------------------------------------------------------------
-- This test bench is configured with two different data sets (selectable with
-- <seltest>). Each test can be run in encryption or decryption flow.
-- Then check the signals at the output of the instantiated core.
------------------------------------------------------------------------
-- Component Declaration
entity test_core is
end test_core;
--constant C_ERROR_SIGNAL_WIDTH : integer := 2;
-- Architecture of the Component
architecture a_tb of test_core is
constant RESET_ACTIVE : std_logic := '0';
constant CLK_HT : time := 16 ns;
constant ROUND_NUMBER : integer := 8;
signal go_enc : std_logic := '0';
signal go_dec : std_logic := '1';
component aes_core is port (
data_inH : in std_logic_vector( 127 downto 0 );
input_key : in std_logic_vector( 127 downto 0 );
go_cipher, go_key, enc_command : in std_logic;
data_outH : out std_logic_vector( 127 downto 0 );
data_out_ok : out std_logic;
ready_out : out std_logic;
error : out std_logic_vector( 0 downto 0 );
rst, ck : in std_logic;
fault_aes_port : in std_logic_vector( 7 downto 0)
);
end component;
signal datain : std_logic_vector( 127 downto 0 );
signal data, edata, edata1, edata2, ddata, ddata1, ddata2, kdata1, kdata2 : std_logic_vector( 127 downto 0 );
signal input_key : std_logic_vector(127 downto 0);
signal s_broken: std_logic_vector( 0 downto 0 ); -- Verify that it is C_ERROR_SIGNAL_WIDTH bit wide!
signal seltest : integer;
signal rst, ck, s_ready, s_d_ok : std_logic;
signal dout : std_logic_vector (127 downto 0);
signal s_go_crypt, s_go_key, s_command : std_logic;
-- fault attack
signal fault_sig : std_logic_vector( 7 downto 0 );
begin
-- CHANGE THE TWO LINES BELOW ACCORDING TO THE TEST YOU WANT TO EXECUTE
-- AND WHETHER YOU NEED TO TEST ENCRYPTION OR DECRYPTION:
seltest <= 2; -- 1 for "test 1" or anything else for "test 2"
s_command <= go_dec; -- "go_enc" or "go_dec"
-- Reset and clock generation:
rst <= not( RESET_ACTIVE ), RESET_ACTIVE after 50*CLK_HT, not( RESET_ACTIVE ) after 52*CLK_HT;
clk_pr : process
begin
ck <= '1';
loop
wait for CLK_HT;
ck <= not ck;
end loop;
end process;
fault : process(ck) is
variable cycle_count : natural := 7 + ROUND_NUMBER * 6;
begin
if ck'event and ck = '1' then
cycle_count := cycle_count + 1;
if s_go_crypt = '1' then
cycle_count := 0;
end if;
if cycle_count > 0 + ROUND_NUMBER * 6 and cycle_count < 7 + ROUND_NUMBER * 6 then
fault_sig <= "11111111";
else
fault_sig <= "00000000";
end if;
end if;
end process fault;
-- Input definition
edata1 <= X"3243f6a8885a308d313198a2e0370734"; edata2 <= X"00112233445566778899aabbccddeeff";
kdata1 <= X"2b7e151628aed2a6abf7158809cf4f3c"; kdata2 <= X"000102030405060708090a0b0c0d0e0f";
ddata1 <= X"3925841d02dc09fbdc118597196a0b32"; ddata2 <= X"69c4e0d86a7b0430d8cdb78070b4c55a";
input_key <= kdata1 when ( seltest=1 ) else kdata2;
edata <= edata1 when ( seltest=1 ) else edata2;
ddata <= ddata1 when ( seltest=1 ) else ddata2;
data <= edata when ( s_command=go_enc ) else ddata;
datain <= ( others=>'0' ), data after 128*CLK_HT,
( others=>'0' ) after 130*CLK_HT, data after 280*CLK_HT,
( others=>'0' ) after 282*CLK_HT;
s_go_crypt <= '0', '1' after 128*CLK_HT, '0' after 130*CLK_HT,
'1' after 280*CLK_HT, '0' after 282*CLK_HT;
s_go_key <= '0', '1' after 58*CLK_HT, '0' after 60*CLK_HT;
UUT : aes_core port map(
data_inH => datain,
input_key => input_key,
go_cipher => s_go_crypt,
go_key => s_go_key,
enc_command => s_command,
data_outH => dout,
data_out_ok => s_d_ok,
ready_out => s_ready,
error => s_broken,
rst => rst,
ck => ck,
fault_aes_port => fault_sig
);
end a_tb;
|
entity loop1 is
end entity;
architecture test of loop1 is
begin
p1: process is
variable a, b : integer;
begin
loop
exit when a = 10;
a := a + 1;
end loop;
loop
a := a + 1;
next when (a mod 2) = 0;
b := b + 1;
exit when b = 10;
end loop;
wait;
end process;
end architecture;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY OpenSSD2_proc_sys_reset_3_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END OpenSSD2_proc_sys_reset_3_0;
ARCHITECTURE OpenSSD2_proc_sys_reset_3_0_arch OF OpenSSD2_proc_sys_reset_3_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF OpenSSD2_proc_sys_reset_3_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END OpenSSD2_proc_sys_reset_3_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY OpenSSD2_proc_sys_reset_3_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END OpenSSD2_proc_sys_reset_3_0;
ARCHITECTURE OpenSSD2_proc_sys_reset_3_0_arch OF OpenSSD2_proc_sys_reset_3_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF OpenSSD2_proc_sys_reset_3_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END OpenSSD2_proc_sys_reset_3_0_arch;
|
------------------------------------------------------------------------------
--
-- File: HandshakeData.vhd
-- Author: Elod Gyorgy
-- Original Project: Atlys2 User Demo
-- Date: 29 June 20116
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module passes parallel data from the input clock domain (InClk) to the
-- output clock domain (OutClk) by the means of handshake signals. A
-- low-to-high transition on iPush will register iData inside the module
-- and will start propagating the handshake signals towards the output domain.
-- The data will appear on oData and is valid when oValid pulses high.
-- The reception of data by the receiver on the OutClk domain is signaled
-- by a pulse on oAck. This will propagate back to the input domain and
-- assert iRdy signaling to the sender that a new data can be pushed though.
-- If oData is always read when oValid pulses, oAck may be tied permanently
-- high.
-- Only assert iPush when iRdy is high!
--
-- Changelog:
-- 2016-Jun-29: Fixed oValid not being a pulse.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity HandshakeData is
Generic (
kDataWidth : natural := 8);
Port (
InClk : in STD_LOGIC;
OutClk : in STD_LOGIC;
iData : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
oData : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
iPush : in STD_LOGIC;
iRdy : out STD_LOGIC;
oAck : in STD_LOGIC := '1';
oValid : out STD_LOGIC;
aReset : in std_logic);
end HandshakeData;
architecture Behavioral of HandshakeData is
signal iPush_q, iPushRising, iPushT, iPushTBack, iReset : std_logic;
signal iData_int : std_logic_vector(kDataWidth-1 downto 0);
signal oPushT, oPushT_q, oPushTBack, oPushTChanged : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of aReset: signal is "TRUE";
begin
DetectPush: process(aReset, InClk)
begin
if (aReset = '1') then
iPush_q <= '0';
elsif Rising_Edge(InClk) then
iPush_q <= iPush;
end if;
end process DetectPush;
iPushRising <= iPush and not iPush_q;
-- Register data when iPush is rising and toggle internal flag
LatchData: process(aReset, InClk)
begin
if (aReset = '1') then
iData_int <= (others => '0');
iPushT <= '0';
elsif Rising_Edge(InClk) then
if (iPushRising = '1') then
iData_int <= iData;
iPushT <= not iPushT;
end if;
end if;
end process;
-- Cross toggle flag through synchronizer
SyncAsyncPushT: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => aReset,
aIn => iPushT,
OutClk => OutClk,
oOut => oPushT);
-- Detect a push edge in the OutClk domain
-- If receiver acknowledges receipt, we can propagate the push signal back
-- towards the input, where it will be used to generate iRdy
DetectToggle: process(aReset, OutClk)
begin
if (aReset = '1') then
oPushT_q <= '0';
oPushTBack <= '0';
elsif Rising_Edge(OutClk) then
oPushT_q <= oPushT;
if (oAck = '1') then
oPushTBack <= oPushT_q;
end if;
end if;
end process DetectToggle;
oPushTChanged <= '1' when oPushT_q /= oPushT else '0';
-- Cross data from InClk domain reg (iData_in) to OutClk domain
-- The enable for this register is the propagated and sync'd to the OutClk domain
-- We assume here that the time it took iPush to propagate to oPushTChanged is
-- more than the time it takes iData_int to propagate to the oData register's D pin
OutputData: process (aReset, OutClk)
begin
if (aReset = '1') then
oData <= (others => '0');
oValid <= '0';
elsif Rising_Edge(OutClk) then
if (oPushTChanged = '1') then
oData <= iData_int;
end if;
oValid <= oPushTChanged;
end if;
end process OutputData;
-- Cross toggle flag back through synchronizer
SyncAsyncPushTBack: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => aReset,
aIn => oPushTBack,
OutClk => InClk,
oOut => iPushTBack);
-- Synchronize aReset into the InClk domain
-- We need it to keep iRdy low, when aReset de-asserts
SyncReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aReset,
OutClk => InClk,
oRst => iReset);
ReadySignal: process(aReset, InClk)
begin
if (aReset = '1') then
iRdy <= '0';
elsif Rising_Edge(InClk) then
iRdy <= not iPush and (iPushTBack xnor iPushT) and not iReset;
end if;
end process ReadySignal;
end Behavioral;
|
-- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
entity opa_pbus is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
p_cyc_o : out std_logic;
p_stb_o : out std_logic;
p_we_o : out std_logic;
p_stall_i : in std_logic;
p_ack_i : in std_logic;
p_err_i : in std_logic;
p_addr_o : out std_logic_vector(g_config.adr_width -1 downto 0);
p_sel_o : out std_logic_vector(g_config.reg_width/8-1 downto 0);
p_data_o : out std_logic_vector(g_config.reg_width -1 downto 0);
p_data_i : in std_logic_vector(g_config.reg_width -1 downto 0);
-- L1d requests action
l1d_stall_o : out std_logic; -- stall has an async dep on addr
l1d_req_i : in std_logic;
l1d_we_i : in std_logic;
l1d_addr_i : in std_logic_vector(f_opa_adr_wide(g_config) -1 downto 0);
l1d_sel_i : in std_logic_vector(f_opa_reg_wide(g_config)/8-1 downto 0);
l1d_dat_i : in std_logic_vector(f_opa_reg_wide(g_config) -1 downto 0);
l1d_pop_i : in std_logic;
l1d_full_o : out std_logic;
l1d_err_o : out std_logic;
l1d_dat_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0));
end opa_pbus;
architecture rtl of opa_pbus is
constant c_page_size : natural := f_opa_page_size(g_isa);
constant c_adr_wide : natural := f_opa_adr_wide(g_config);
constant c_reg_wide : natural := f_opa_reg_wide(g_config);
constant c_sel_wide : natural := c_reg_wide/8;
constant c_fifo_wide : natural := c_adr_wide + c_sel_wide + c_reg_wide;
constant c_fifo_deep : natural := 4;
constant c_device_align : natural := f_opa_log2(c_page_size);
signal s_stall : std_logic; -- We can accept the op on l1d_addr_i
signal s_push : std_logic; -- L1d delivers req into FIFO (and possibly reg)
signal s_exist : std_logic; -- There exists data to be sent
signal s_full : std_logic; -- full regs were not drained by pbus
signal s_pop : std_logic; -- regs have accepted data from L1d or FIFO
signal s_fin : std_logic; -- pbus completed IO
signal s_widx : unsigned(c_fifo_deep-1 downto 0);
signal s_ridx : unsigned(c_fifo_deep-1 downto 0);
signal s_fidx : unsigned(c_fifo_deep-1 downto 0);
signal s_fifo_in : std_logic_vector(c_fifo_wide-1 downto 0);
signal s_fifo_out: std_logic_vector(c_fifo_wide-1 downto 0);
signal r_widx : unsigned(c_fifo_deep-1 downto 0) := (others => '0');
signal r_ridx : unsigned(c_fifo_deep-1 downto 0) := (others => '0');
signal r_fidx : unsigned(c_fifo_deep-1 downto 0) := (others => '0');
signal r_stall : std_logic := '0';
signal r_cyc : std_logic := '0';
signal r_stb : std_logic := '0';
-- This cannot go into FIFO because we must tap it twice
signal r_we_q : std_logic_vector(2**c_fifo_deep-1 downto 0);
signal r_we : std_logic;
signal r_adr : std_logic_vector(c_adr_wide -1 downto 0);
signal r_sel : std_logic_vector(c_reg_wide/8-1 downto 0);
signal r_dat : std_logic_vector(c_reg_wide -1 downto 0);
signal r_lock : std_logic := '0'; -- !!! set somewhere in a CSR or so
signal r_full : std_logic := '0';
signal r_err : std_logic;
signal r_que : std_logic_vector(c_reg_wide-1 downto 0);
begin
check : process(clk_i) is
begin
if rising_edge(clk_i) then
assert (f_opa_safe(l1d_req_i) = '1') report "pbus: l1d_req_i has a metavalue" severity failure;
assert (f_opa_safe(l1d_pop_i) = '1') report "pbus: l1d_req_i has a metavalue" severity failure;
-- Internal state
assert (f_opa_safe(r_full) = '1') report "pbus: r_full has a metavalue" severity failure;
assert (f_opa_safe(r_ridx) = '1') report "pbus: r_ridx has a metavalue" severity failure;
assert (f_opa_safe(r_widx) = '1') report "pbus: r_widx has a metavalue" severity failure;
assert (f_opa_safe(r_fidx) = '1') report "pbus: r_fidx has a metavalue" severity failure;
end if;
end process;
-- We accept requests into the same wishbone cycle if they are within the same device
-- OR the user has explicitly requested the cycle line stay up (r_lock).
s_stall <=
r_stall or not
(r_lock or not r_cyc or f_opa_eq(r_adr(r_adr'high downto c_device_align), l1d_addr_i(r_adr'high downto c_device_align)));
s_push <= l1d_req_i and not s_stall;
s_full <= r_stb and p_stall_i;
s_exist <= not f_opa_eq(r_widx, r_ridx) or s_push;
s_pop <= not s_full and s_exist;
s_fin <= r_cyc and (p_ack_i or p_err_i);
l1d_stall_o <= s_stall;
p_cyc_o <= r_cyc;
p_stb_o <= r_stb;
p_we_o <= r_we;
p_sel_o <= r_sel;
p_data_o <= r_dat;
p_addr_o(p_addr_o'high downto r_adr'high) <= (others => r_adr(r_adr'high));
p_addr_o(r_adr'high-1 downto 0) <= std_logic_vector(r_adr(r_adr'high-1 downto 0));
-- !!! Consider setting g_regin=false and r_addr_i to r_ridx; ie: async read memory
fifo_out : opa_dpram
generic map(
g_width => c_fifo_wide,
g_size => 2**c_fifo_deep,
g_equal => OPA_NEW,
g_regin => true,
g_regout => false)
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
r_addr_i => std_logic_vector(s_ridx),
r_data_o => s_fifo_out,
w_en_i => '1',
w_addr_i => std_logic_vector(r_widx),
w_data_i => s_fifo_in);
s_widx <= r_widx + ("" & s_push);
s_ridx <= r_ridx + ("" & s_pop);
s_fidx <= r_fidx + ("" & s_fin);
s_fifo_in <= l1d_addr_i & l1d_sel_i & l1d_dat_i;
main : process(clk_i, rst_n_i) is
begin
if rst_n_i = '0' then
r_ridx <= (others => '0');
r_widx <= (others => '0');
r_fidx <= (others => '0');
r_stall <= '0';
r_cyc <= '0';
r_stb <= '0';
elsif rising_edge(clk_i) then
r_ridx <= s_ridx;
r_widx <= s_widx;
r_fidx <= s_fidx;
r_stall <= not f_opa_lt(r_widx - r_fidx, 2**c_fifo_deep-2);
r_cyc <= not f_opa_eq(s_widx, s_fidx) or r_lock;
r_stb <= s_exist or s_full;
end if;
end process;
we : process(clk_i) is
begin
if rising_edge(clk_i) then
r_we_q(to_integer(unsigned(r_widx))) <= l1d_we_i;
end if;
end process;
pbus : process(clk_i) is
begin
if rising_edge(clk_i) then
if s_pop = '1' then
if r_ridx = r_widx then
r_we <= l1d_we_i;
r_adr <= l1d_addr_i;
r_sel <= l1d_sel_i;
r_dat <= l1d_dat_i;
else
r_we <= r_we_q(to_integer(unsigned(r_ridx)));
r_adr <= s_fifo_out(s_fifo_out'high downto s_fifo_out'high-c_adr_wide+1);
r_sel <= s_fifo_out(c_reg_wide/8*9-1 downto c_reg_wide);
r_dat <= s_fifo_out(c_reg_wide-1 downto 0);
end if;
end if;
end if;
end process;
-- !!! add a FIFO just like the above once we have prefetch => high throughput loads
l1d_full_o <= r_full;
l1d_err_o <= r_err;
l1d_dat_o <= r_que;
qmain : process(clk_i, rst_n_i) is
begin
if rst_n_i = '0' then
r_full <= '0';
elsif rising_edge(clk_i) then
r_full <= (r_full and not l1d_pop_i) or (s_fin and not r_we_q(to_integer(unsigned(r_fidx))));
end if;
end process;
qbus : process(clk_i) is
begin
if rising_edge(clk_i) then
if r_full = '0' then
r_que <= p_data_i;
r_err <= p_err_i;
end if;
end if;
end process;
end rtl;
|
---------------------------------------------------------------------------
-- This file is part of lt24ctrl, a video controler IP core for Terrasic
-- LT24 LCD display
-- Copyright (C) 2017 Ludovic Noury <[email protected]>
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------------------------------
entity cpt_delay is
generic(system_frequency: real := 50_000_000.0;
tmin_cycles : natural := 1);
port(clk : in std_logic;
resetn : in std_logic;
clr_cptdelay: in std_logic;
tick_1ms : out std_logic;
tick_10ms : out std_logic;
tick_120ms : out std_logic;
tick_tmin : out std_logic);
end entity cpt_delay;
---------------------------------------------------------------------------
architecture rtl of cpt_delay is
constant t1ms_cycles : natural := integer(system_frequency * 1.0e-3);
constant t10ms_cycles : natural := integer(system_frequency * 10.0e-3);
constant t120ms_cycles: natural := integer(system_frequency * 120.0e-3);
begin
update_cpt: process(clk, resetn)
variable counter : natural range 0 to (t120ms_cycles - 1);
begin
if resetn = '0' then
counter := 0;
tick_tmin <= '0';
tick_1ms <= '0';
tick_10ms <= '0';
tick_120ms <= '0';
elsif rising_edge(clk) then
tick_tmin <= '0';
tick_1ms <= '0';
tick_10ms <= '0';
tick_120ms <= '0';
if counter = t120ms_cycles - 1 then
tick_120ms <= '1';
elsif counter = t10ms_cycles - 1 then
tick_10ms <= '1';
elsif counter = t1ms_cycles - 1 then
tick_1ms <= '1';
elsif counter = tmin_cycles then
tick_tmin <= '1';
else
null;
end if; -- clr_cptdelay = '1'
if (clr_cptdelay = '1') or (counter = t120ms_cycles - 1) then
counter := 0;
else
counter := counter + 1;
end if;
end if; -- resetn = '0'
end process update_cpt;
end architecture rtl;
---------------------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1162.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p02n01i01162ent IS
END c06s06b00x00p02n01i01162ent;
ARCHITECTURE c06s06b00x00p02n01i01162arch OF c06s06b00x00p02n01i01162ent IS
BEGIN
TESTING: PROCESS
type I1 is range 1 to 3;
type A1 is array (I1) of BOOLEAN;
BEGIN
if (1|2|3=>TRUE)'RIGHT = 3 then
-- SYNTAX ERROR: AGGREGATE NOT ALLOWED AS PREFIX OF
-- ATTRIBUTE NAME
-- return;
null ;
end if;
assert FALSE
report "***FAILED TEST: c06s06b00x00p02n01i01162 - Prefix of an attribute name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01162arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1162.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p02n01i01162ent IS
END c06s06b00x00p02n01i01162ent;
ARCHITECTURE c06s06b00x00p02n01i01162arch OF c06s06b00x00p02n01i01162ent IS
BEGIN
TESTING: PROCESS
type I1 is range 1 to 3;
type A1 is array (I1) of BOOLEAN;
BEGIN
if (1|2|3=>TRUE)'RIGHT = 3 then
-- SYNTAX ERROR: AGGREGATE NOT ALLOWED AS PREFIX OF
-- ATTRIBUTE NAME
-- return;
null ;
end if;
assert FALSE
report "***FAILED TEST: c06s06b00x00p02n01i01162 - Prefix of an attribute name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01162arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1162.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p02n01i01162ent IS
END c06s06b00x00p02n01i01162ent;
ARCHITECTURE c06s06b00x00p02n01i01162arch OF c06s06b00x00p02n01i01162ent IS
BEGIN
TESTING: PROCESS
type I1 is range 1 to 3;
type A1 is array (I1) of BOOLEAN;
BEGIN
if (1|2|3=>TRUE)'RIGHT = 3 then
-- SYNTAX ERROR: AGGREGATE NOT ALLOWED AS PREFIX OF
-- ATTRIBUTE NAME
-- return;
null ;
end if;
assert FALSE
report "***FAILED TEST: c06s06b00x00p02n01i01162 - Prefix of an attribute name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01162arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library accum;
use accum.OneHotAccum.all;
entity DPATH is
port(
EN: in std_logic;
-- operation type
OT: in operation;
-- operand
OP1: in operand;
RES: out operand;
-- zero flag
ZF: out std_logic
);
end DPATH;
architecture Beh of DPATH is
signal ACCUM: operand;
signal res_add: operand;
signal res_sub: operand;
signal res_shift: operand;
signal t_zf: std_logic;
Begin
res_add <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(ACCUM) + CONV_INTEGER(OP1), 16);
res_sub <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(ACCUM) - CONV_INTEGER(OP1), 16);
REGA: process (EN, OT, OP1, res_add, res_sub, res_shift)
begin
if rising_edge(EN) then
case OT is
when LOAD => ACCUM <= OP1;
when ADD => ACCUM <= res_add;
when SUBT => ACCUM <= res_sub;
when SHIFT => ACCUM <= res_shift;
when others => null;
end case;
end if;
end process;
FLAGS: process(ACCUM)
begin
if ACCUM = (ACCUM'range => '0') then
t_zf <= '1';
else
t_zf <= '0';
end if;
end process;
GRAY: process(ACCUM)
begin
for i in 0 to 14 loop
res_shift(i) <= ACCUM(i) xor ACCUM(i+1);
end loop;
res_shift(15) <= ACCUM(15);
end process;
RES <= ACCUM;
ZF <= t_zf;
End Beh; |
-- $Id: migui_core_gsim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: migui_core_gsim - sim
-- Description: MIG interface simulation core
--
-- Dependencies: sfs_gsim_core
-- Test bench: tb/tb_sramif2migui_core
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-28 1096 1.0 Initial version
-- 2018-11-10 1067 0.1 First draft
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.miglib.all;
entity migui_core_gsim is -- MIG interface simulation core
generic (
BAWIDTH : positive := 4; -- byte address width
MAWIDTH : positive := 28; -- memory address width
SAWIDTH : positive := 24; -- simulator memory address width
CLKMUI_MUL : positive := 6; -- multiplier for MIG UI clock
CLKMUI_DIV : positive := 12; -- divider for MIG UI clock
CACO_WAIT : positive := 50); -- UI_CLK cycles till CALIB_COMP = 1
port (
SYS_CLK : in slbit; -- system clock
SYS_RST : in slbit; -- system reset
UI_CLK : out slbit; -- MIGUI clock
UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : out slbit; -- MIGUI calibration done
APP_RDY : out slbit; -- MIGUI ready for cmd
APP_EN : in slbit; -- MIGUI command enable
APP_CMD : in slv3; -- MIGUI command
APP_ADDR : in slv(MAWIDTH-1 downto 0); -- MIGUI address
APP_WDF_RDY : out slbit; -- MIGUI ready for data write
APP_WDF_WREN : in slbit; -- MIGUI data write enable
APP_WDF_DATA : in slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI write data
APP_WDF_MASK : in slv((2**BAWIDTH)-1 downto 0); -- MIGUI write mask
APP_WDF_END : in slbit; -- MIGUI write end
APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
APP_RD_DATA : out slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI read data
APP_RD_DATA_END : out slbit; -- MIGUI read end
APP_REF_REQ : in slbit; -- MIGUI refresh request
APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request
APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge
APP_ZQ_ACK : out slbit -- MIGUI ZQ calibrate acknowledge
);
end migui_core_gsim;
architecture sim of migui_core_gsim is
constant mwidth : positive := 2**BAWIDTH; -- mask width (8 or 16)
constant dwidth : positive := 8*mwidth; -- data width (64 or 128)
-- row/col split only relevant for timing simulation
-- use 16kbit->2kByte column width as used in MT41K128M16 on arty board
constant colwidth : positive := 11;
constant rowwidth : positive := MAWIDTH-colwidth;
subtype addr_f_row is integer range MAWIDTH-1 downto colwidth;
subtype bv8 is bit_vector(7 downto 0);
constant memsize : positive := 2**SAWIDTH;
constant datzero : bv8 := (others=>'0');
type ram_type is array (0 to memsize-1) of bv8;
-- timing constants
constant c_rdwait_rhit : positive := 2; -- read wait row match
constant c_rdwait_rmis : positive := 5; -- read wait row miss
constant c_wrwait_rhit : positive := 2; -- write wait row match
constant c_wrwait_rmis : positive := 5; -- write wait row miss
constant c_wrwait_max : positive := c_wrwait_rmis; -- write wait maximum
-- the REF and ZQ delays are as observed for arty board
constant c_refwait : positive := 10; -- REF_REQ to REF_ACK delay
constant c_zqwait : positive := 8; -- ZQ_REQ to ZQ_ACK delay
-- the RDY pattern gives 23% busy (4 out of 13 cycles)
-- good enough for simulation; observed pattern on arty shows ~6% busy,
constant c_crdy_init : slv13 := "0001111110111"; -- block 4 of 13;
type regs_type is record
cacowait : natural; -- CACO wait down counter
enacaco : slbit; -- CACO enable
enardy : slbit; -- RDY enable
rowaddr : slv(rowwidth-1 downto 0); -- current row address
rdwait : natural; -- read wait cycles pending
wrwait : natural; -- write wait cycles pending
crdypat : slv13; -- crdy pattern
refwait : natural; -- req_ack wait counter
zqwait : natural; -- zq_ack wait counter
end record regs_type;
constant rowaddr_init : slv(rowwidth-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
CACO_WAIT,'0','0', -- cacowait,enacaco,enardy
rowaddr_init, -- rowaddr
0,0, -- rdwait,wrwait
c_crdy_init, -- crdypat
0,0 -- refwait,zqwait
);
signal CLK : slbit; -- local copy of UI_CLK
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal CLKFX : slbit;
signal MEM_EN : slbit := '0'; -- sim mem enable
signal MEM_WE : slbit := '0'; -- sim mem write enable
signal MEM_ADDR : slv(SAWIDTH-BAWIDTH-1 downto 0); -- sim mem base address
signal R_MEMDO : slv(dwidth-1 downto 0) := (others=>'0');
begin
assert BAWIDTH = 3 or BAWIDTH = 4
report "assert( BAWIDTH = 3 or 4 )"
severity failure;
UICLKGEN : sfs_gsim_core -- mig ui clock generator
generic map (
VCO_DIVIDE => 1,
VCO_MULTIPLY => CLKMUI_MUL,
OUT_DIVIDE => CLKMUI_DIV)
port map (
CLKIN => SYS_CLK,
CLKFX => CLKFX,
LOCKED => open
);
CLK <= CLKFX; -- !! copy both local CLK and exported
UI_CLK <= CLKFX; -- !! UI_CLK to avoid delta cycle diff
UI_CLK_SYNC_RST <= '0';
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if SYS_RST = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, APP_EN, APP_ADDR, APP_CMD,
APP_WDF_WREN, APP_WDF_END,
APP_REF_REQ,APP_ZQ_REQ, R_MEMDO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable iappcrdy : slbit := '0';
variable iappwrdy : slbit := '0';
variable iapprefack : slbit := '0';
variable iappzqack : slbit := '0';
variable imemen : slbit := '0';
variable imemwe : slbit := '0';
variable irdval : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
iappcrdy := '1';
iappwrdy := '1';
iapprefack := '0';
iappzqack := '0';
imemen := '0';
imemwe := '0';
irdval := '0';
n.crdypat := r.crdypat(11 downto 0) & r.crdypat(12); -- circular right shift
-- simulate CACO wait
if r.cacowait > 0 then
n.cacowait := r.cacowait - 1;
if r.cacowait <= CACO_WAIT/2 then -- half of CACO wait reached ?
n.enardy := '1'; -- enable RDY's
end if;
if r.cacowait = 1 then -- CACO wait ended ?
n.enacaco := '1'; -- assert CACO
end if;
end if;
-- process cmd requests
if r.wrwait >= c_wrwait_max then
iappcrdy := '0';
iappwrdy := '0';
elsif r.rdwait > 0 then
iappcrdy := '0';
elsif r.enardy='0' or r.crdypat(0)='0' then
iappcrdy := '0';
else
if APP_EN = '1' then
if APP_CMD = c_migui_cmd_read then
imemen := '1';
if r.rowaddr = APP_ADDR(addr_f_row) then
n.rdwait := r.rdwait + c_rdwait_rhit;
else
n.rdwait := r.rdwait + c_rdwait_rmis;
n.rowaddr := APP_ADDR(addr_f_row);
end if;
elsif APP_CMD = c_migui_cmd_write then
imemen := '1';
imemwe := '1';
if r.rowaddr = APP_ADDR(addr_f_row) then
n.wrwait := r.wrwait + c_wrwait_rhit;
else
n.wrwait := r.wrwait + c_wrwait_rmis;
n.rowaddr := APP_ADDR(addr_f_row);
end if;
else
end if;
end if;
end if;
-- handle cmd waits, issue read responses
if r.enacaco = '1' then -- process commands only after CACO
if r.wrwait > 0 then -- first wait for pending writes
n.wrwait := r.wrwait - 1;
else
if r.rdwait > 0 then -- next of for pending reads
n.rdwait := r.rdwait - 1;
if r.rdwait = 1 then
irdval := '1';
end if;
end if;
end if;
end if;
-- process ref_req requests
if APP_REF_REQ = '1' then
n.refwait := c_refwait;
else
if r.refwait > 0 then
n.refwait := r.refwait -1;
if r.refwait = 1 then
iapprefack := '1';
end if;
end if;
end if;
-- process zq_req requests
if APP_ZQ_REQ = '1' then
n.zqwait := c_zqwait;
else
if r.zqwait > 0 then
n.zqwait := r.zqwait -1;
if r.zqwait = 1 then
iappzqack := '1';
end if;
end if;
end if;
N_REGS <= n;
INIT_CALIB_COMPLETE <= r.enacaco;
APP_RDY <= iappcrdy;
APP_WDF_RDY <= iappwrdy;
APP_RD_DATA_VALID <= irdval;
APP_RD_DATA_END <= irdval;
APP_REF_ACK <= iapprefack;
APP_ZQ_ACK <= iappzqack;
if irdval = '1' then -- only in the RD_DATA_END cycle
APP_RD_DATA <= R_MEMDO; -- export the data
else -- otherwise
APP_RD_DATA <= (others=>'1'); -- send all ones
end if;
MEM_EN <= imemen;
MEM_WE <= imemwe;
MEM_ADDR <= APP_ADDR(SAWIDTH-1 downto BAWIDTH);
end process proc_next;
proc_mem: process (CLK)
variable ram : ram_type := (others=>datzero);
variable membase : integer := 0;
begin
if rising_edge(CLK) then
if MEM_EN = '1' then
membase := mwidth*to_integer(unsigned(MEM_ADDR));
-- write to memory
if APP_WDF_WREN = '1' then
for i in 0 to mwidth-1 loop
if APP_WDF_MASK(i) = '0' then -- WE = not MASK !!
ram(membase + i) :=
to_bitvector(to_x01(APP_WDF_DATA(8*i+7 downto 8*i)));
end if;
end loop;
end if;
-- read from memory
for i in 0 to mwidth-1 loop
R_MEMDO(8*i+7 downto 8*i) <= to_stdlogicvector(ram(membase + i));
end loop;
end if;
end if;
end process proc_mem;
proc_moni: process (CLK)
begin
if rising_edge(CLK) then
if SYS_RST = '0' then
if APP_EN = '1' then
assert APP_CMD = c_migui_cmd_read or
APP_CMD = c_migui_cmd_write
report "migui_core_gsim: FAIL: APP_CMD not 000 or 001"
severity error;
assert unsigned(APP_ADDR(MAWIDTH-1 downto SAWIDTH)) = 0
report "migui_core_gsim: FAIL: out of sim-memory size access"
severity error;
end if;
if APP_EN = '1' and APP_CMD = c_migui_cmd_write then
assert APP_WDF_WREN='1' and APP_WDF_END='1'
report "migui_core_gsim: FAIL: APP_WDF_(END,WREN) missed on write"
severity error;
else
assert APP_WDF_WREN='0' and APP_WDF_END='0'
report "migui_core_gsim: FAIL: spurious APP_WDF_(END,WREN)"
severity error;
end if;
end if;
end if;
end process proc_moni;
end sim;
|
-- #############################################################################
-- DE1_SoC_top_level.vhd
--
-- BOARD : DE1-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.4
-- Creation date : 04/02/2015
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE1_SoC_top_level is
port(
-- ADC
-- ADC_CS_n : out std_logic;
-- ADC_DIN : out std_logic;
-- ADC_DOUT : in std_logic;
-- ADC_SCLK : out std_logic;
-- Audio
-- AUD_ADCDAT : in std_logic;
-- AUD_ADCLRCK : inout std_logic;
-- AUD_BCLK : inout std_logic;
-- AUD_DACDAT : out std_logic;
-- AUD_DACLRCK : inout std_logic;
-- AUD_XCK : out std_logic;
-- CLOCK
CLOCK_50 : in std_logic;
-- CLOCK2_50 : in std_logic;
-- CLOCK3_50 : in std_logic;
-- CLOCK4_50 : in std_logic;
-- SDRAM
--DRAM_ADDR : out std_logic_vector(12 downto 0);
--DRAM_BA : out std_logic_vector(1 downto 0);
--DRAM_CAS_N : out std_logic;
--DRAM_CKE : out std_logic;
--DRAM_CLK : out std_logic;
--DRAM_CS_N : out std_logic;
--DRAM_DQ : inout std_logic_vector(15 downto 0);
--DRAM_LDQM : out std_logic;
--DRAM_RAS_N : out std_logic;
--DRAM_UDQM : out std_logic;
--DRAM_WE_N : out std_logic;
-- I2C for Audio and Video-In
-- FPGA_I2C_SCLK : out std_logic;
-- FPGA_I2C_SDAT : inout std_logic;
-- SEG7
-- HEX0_N : out std_logic_vector(6 downto 0);
-- HEX1_N : out std_logic_vector(6 downto 0);
-- HEX2_N : out std_logic_vector(6 downto 0);
-- HEX3_N : out std_logic_vector(6 downto 0);
-- HEX4_N : out std_logic_vector(6 downto 0);
-- HEX5_N : out std_logic_vector(6 downto 0);
-- IR
-- IRDA_RXD : in std_logic;
-- IRDA_TXD : out std_logic;
-- KEY_N
-- KEY_N : in std_logic_vector(3 downto 0);
-- LED
--LEDR : out std_logic_vector(9 downto 0);
-- PS2
-- PS2_CLK : inout std_logic;
-- PS2_CLK2 : inout std_logic;
-- PS2_DAT : inout std_logic;
-- PS2_DAT2 : inout std_logic;
-- SW
-- SW : in std_logic_vector(9 downto 0);
-- Video-In
-- TD_CLK27 : inout std_logic;
-- TD_DATA : out std_logic_vector(7 downto 0);
-- TD_HS : out std_logic;
-- TD_RESET_N : out std_logic;
-- TD_VS : out std_logic;
-- VGA
-- VGA_B : out std_logic_vector(7 downto 0);
-- VGA_BLANK_N : out std_logic;
-- VGA_CLK : out std_logic;
-- VGA_G : out std_logic_vector(7 downto 0);
-- VGA_HS : out std_logic;
-- VGA_R : out std_logic_vector(7 downto 0);
-- VGA_SYNC_N : out std_logic;
-- VGA_VS : out std_logic;
-- GPIO_0
-- GPIO_0 : inout std_logic_vector(35 downto 0);
-- GPIO_1
-- GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
--HPS_CONV_USB_N : inout std_logic;
--HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
--HPS_DDR3_BA : out std_logic_vector(2 downto 0);
--HPS_DDR3_CAS_N : out std_logic;
--HPS_DDR3_CK_N : out std_logic;
--HPS_DDR3_CK_P : out std_logic;
--HPS_DDR3_CKE : out std_logic;
--HPS_DDR3_CS_N : out std_logic;
--HPS_DDR3_DM : out std_logic_vector(3 downto 0);
--HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
--HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
--HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
--HPS_DDR3_ODT : out std_logic;
--HPS_DDR3_RAS_N : out std_logic;
--HPS_DDR3_RESET_N : out std_logic;
--HPS_DDR3_RZQ : in std_logic;
--HPS_DDR3_WE_N : out std_logic;
--HPS_ENET_GTX_CLK : out std_logic;
--HPS_ENET_INT_N : inout std_logic;
--HPS_ENET_MDC : out std_logic;
--HPS_ENET_MDIO : inout std_logic;
--HPS_ENET_RX_CLK : in std_logic;
--HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
--HPS_ENET_RX_DV : in std_logic;
--HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
--HPS_ENET_TX_EN : out std_logic;
--HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
--HPS_FLASH_DCLK : out std_logic;
--HPS_FLASH_NCSO : out std_logic;
--HPS_GSENSOR_INT : inout std_logic;
--HPS_I2C_CONTROL : inout std_logic;
--HPS_I2C1_SCLK : inout std_logic;
--HPS_I2C1_SDAT : inout std_logic;
--HPS_I2C2_SCLK : inout std_logic;
--HPS_I2C2_SDAT : inout std_logic;
--HPS_KEY_N : inout std_logic;
--HPS_LED : inout std_logic;
--HPS_LTC_GPIO : inout std_logic;
--HPS_SD_CLK : out std_logic;
--HPS_SD_CMD : inout std_logic;
--HPS_SD_DATA : inout std_logic_vector(3 downto 0);
--HPS_SPIM_CLK : out std_logic;
--HPS_SPIM_MISO : in std_logic;
--HPS_SPIM_MOSI : out std_logic;
--HPS_SPIM_SS : inout std_logic;
--HPS_UART_RX : in std_logic;
--HPS_UART_TX : out std_logic;
--HPS_USB_CLKOUT : in std_logic;
--HPS_USB_DATA : inout std_logic_vector(7 downto 0);
--HPS_USB_DIR : in std_logic;
--HPS_USB_NXT : in std_logic;
--HPS_USB_STP : out std_logic
);
end entity DE1_SoC_top_level;
|
----------------------------------------------------------------------------------
-- Block takes the clock input (or any other pulsed input) and uses that and a
-- simple counter to control the output frequency (useful for flashing LEDs)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HelloWorldVHD is
Port ( clk_in : in STD_LOGIC;
led_out : out STD_LOGIC);
end HelloWorldVHD;
architecture RTL of HelloWorldVHD is
constant max_count : natural := 48000000;
signal Rst_n : std_logic;
begin
Rst_n <= '1';
-- 0 to max_count counter
flash : process(clk_in, Rst_n)
variable count : natural range 0 to max_count;
begin
if Rst_n = '0' then
count := 0;
led_out <= '1';
elsif rising_edge(clk_in) then
if count < max_count/2 then
led_out <='1';
count := count + 1;
elsif count < max_count then
led_out <='0';
count := count + 1;
else
count := 0;
led_out <='1';
end if;
end if;
end process flash;
end RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity Adder4 is
port( a, b : in std_logic_vector(3 downto 0);
cin : in std_logic;
s : out std_logic_vector(3 downto 0);
cout : out std_logic);
end Adder4;
architecture Structural of Adder4 is
signal carryOut : std_logic_vector(2 downto 0);
begin
bit0: entity work.FullAdder(Behavioral)
port map(a => a(0),
b => b(0),
cin => cin,
s => s(0),
cout => carryOut(0));
bit1: entity work.FullAdder(Behavioral)
port map(a => a(1),
b => b(1),
cin => carryOut(0),
s => s(1),
cout => carryOut(1));
bit2: entity work.FullAdder(Behavioral)
port map(a => a(2),
b => b(2),
cin => carryOut(1),
s => s(2),
cout => carryOut(2));
bit3: entity work.FullAdder(Behavioral)
port map(a => a(3),
b => b(3),
cin => carryOut(2),
s => s(3),
cout => cout);
end Structural;
architecture Behavioral of Adder4 is
signal s_a, s_b, s_s : unsigned(4 downto 0);
begin
s_a <= '0' & unsigned(a);
s_b <= '0' & unsigned(b);
s_s <= s_a + s_b;
s <= std_logic_vector(s_s(3 downto 0));
cout <= s_s(4);
end Behavioral;
architecture Behavioral of AddSub4 is
signal s_a, s_b, s_s : unsigned(4 downto 0);
begin
s_a <= '0' & unsigned(a);
s_b <= '0' & unsigned(b);
s_s <= (s_a + s_b) when (sub = '0') else
(s_a - s_b);
s <= std_logic_vector(s_s(3 downto 0));
cout <= s_s(4);
end Behavioral; |
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity a_table is
port ( addr : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(2 downto 0));
end a_table;
architecture rtl of a_table is
begin
process(addr)
begin
case addr is
when "1110101100000000" => dout <= "001";
when "1110100100000000" => dout <= "010";
when "1111111111100000" => dout <= "000";
when "1111111100100110" => dout <= "100";
when "1111111100100000" => dout <= "000";
when "1111111101100000" => dout <= "011";
when "1111111110100000" => dout <= "100";
when "1110101000000000" => dout <= "010";
when "1111111100101110" => dout <= "100";
when "1111111100101000" => dout <= "000";
when "1111111101101000" => dout <= "011";
when "1111111110101000" => dout <= "100";
when "1110100000000000" => dout <= "010";
when "1111111111010000" => dout <= "000";
when "1111111100010110" => dout <= "100";
when "1111111100010000" => dout <= "000";
when "1111111101010000" => dout <= "011";
when "1111111110010000" => dout <= "100";
when "1001101000000000" => dout <= "010";
when "1111111100011110" => dout <= "100";
when "1111111100011000" => dout <= "000";
when "1111111101011000" => dout <= "011";
when "1111111110011000" => dout <= "100";
when "1100001100000000" => dout <= "000";
when "1100001000000000" => dout <= "000";
when "1100101100000000" => dout <= "000";
when "1100101000000000" => dout <= "000";
when "0111010000000000" => dout <= "001";
when "0111110000000000" => dout <= "001";
when "0111111000000000" => dout <= "001";
when "0111001000000000" => dout <= "001";
when "0111011000000000" => dout <= "001";
when "0111101000000000" => dout <= "001";
when "0111000000000000" => dout <= "001";
when "0111100000000000" => dout <= "001";
when "0111010100000000" => dout <= "001";
when "0111110100000000" => dout <= "001";
when "0111111100000000" => dout <= "001";
when "0111001100000000" => dout <= "001";
when "0111011100000000" => dout <= "001";
when "0111101100000000" => dout <= "001";
when "0111000100000000" => dout <= "001";
when "0111100100000000" => dout <= "001";
when "1110001100000000" => dout <= "001";
when "1110001000000000" => dout <= "001";
when "1110000100000000" => dout <= "001";
when "1110000000000000" => dout <= "001";
when "1100110100000000" => dout <= "101";
when "1100110000000000" => dout <= "110";
when "1100111000000000" => dout <= "111";
when "1100111100000000" => dout <= "000";
when "1111100000000000" => dout <= "000";
when "1111010100000000" => dout <= "000";
when "1111100100000000" => dout <= "000";
when "1111110000000000" => dout <= "000";
when "1111110100000000" => dout <= "000";
when "1111101000000000" => dout <= "000";
when "1111101100000000" => dout <= "000";
when "1111010000000000" => dout <= "000";
when "1001101100000000" => dout <= "000";
when "1111000000000000" => dout <= "000";
when "1001000000000000" => dout <= "000";
when "0010011000000000" => dout <= "000";
when "0010111000000000" => dout <= "000";
when "0011011000000000" => dout <= "000";
when "0011111000000000" => dout <= "000";
when "1000100011000000" => dout <= "000";
when "1000100000000000" => dout <= "000";
when "1000100001000000" => dout <= "011";
when "1000100010000000" => dout <= "100";
when "1000100000000110" => dout <= "100";
when "1000100111000000" => dout <= "000";
when "1000100100000000" => dout <= "000";
when "1000100101000000" => dout <= "011";
when "1000100110000000" => dout <= "100";
when "1000100100000110" => dout <= "100";
when "1000101011000000" => dout <= "000";
when "1000101000000000" => dout <= "000";
when "1000101001000000" => dout <= "011";
when "1000101010000000" => dout <= "100";
when "1000101000000110" => dout <= "100";
when "1000101111000000" => dout <= "000";
when "1000101100000000" => dout <= "000";
when "1000101101000000" => dout <= "011";
when "1000101110000000" => dout <= "100";
when "1000101100000110" => dout <= "100";
when "1100011000000000" => dout <= "000";
when "1100011001000000" => dout <= "011";
when "1100011010000000" => dout <= "100";
when "1100011000000110" => dout <= "100";
when "1100011100000000" => dout <= "000";
when "1100011101000000" => dout <= "011";
when "1100011110000000" => dout <= "100";
when "1100011100000110" => dout <= "100";
when "1011000000000000" => dout <= "000";
when "1011000100000000" => dout <= "000";
when "1011001000000000" => dout <= "000";
when "1011001100000000" => dout <= "000";
when "1011010000000000" => dout <= "000";
when "1011010100000000" => dout <= "000";
when "1011011000000000" => dout <= "000";
when "1011011100000000" => dout <= "000";
when "1011100000000000" => dout <= "000";
when "1011100100000000" => dout <= "000";
when "1011101000000000" => dout <= "000";
when "1011101100000000" => dout <= "000";
when "1011110000000000" => dout <= "000";
when "1011110100000000" => dout <= "000";
when "1011111000000000" => dout <= "000";
when "1011111100000000" => dout <= "000";
when "1010000000000000" => dout <= "010";
when "1010000100000000" => dout <= "010";
when "1010001000000000" => dout <= "010";
when "1010001100000000" => dout <= "010";
when "1000111011000000" => dout <= "000";
when "1000111000000000" => dout <= "000";
when "1000111001000000" => dout <= "011";
when "1000111010000000" => dout <= "100";
when "1000111000000110" => dout <= "100";
when "1000110011000000" => dout <= "000";
when "1000110000000000" => dout <= "000";
when "1000110001000000" => dout <= "011";
when "1000110010000000" => dout <= "100";
when "1000110000000110" => dout <= "100";
when "1111111100110000" => dout <= "000";
when "1111111101110000" => dout <= "011";
when "1111111110110000" => dout <= "100";
when "1111111100110110" => dout <= "100";
when "0101000000000000" => dout <= "000";
when "0101000100000000" => dout <= "000";
when "0101001000000000" => dout <= "000";
when "0101001100000000" => dout <= "000";
when "0101010000000000" => dout <= "000";
when "0101010100000000" => dout <= "000";
when "0101011000000000" => dout <= "000";
when "0101011100000000" => dout <= "000";
when "0000011000000000" => dout <= "000";
when "0000111000000000" => dout <= "000";
when "0001011000000000" => dout <= "000";
when "0001111000000000" => dout <= "000";
when "1000111100000000" => dout <= "000";
when "1000111101000000" => dout <= "011";
when "1000111110000000" => dout <= "100";
when "1000111100000110" => dout <= "100";
when "1000111111000000" => dout <= "000";
when "0101100000000000" => dout <= "000";
when "0101100100000000" => dout <= "000";
when "0101101000000000" => dout <= "000";
when "0101101100000000" => dout <= "000";
when "0101110000000000" => dout <= "000";
when "0101110100000000" => dout <= "000";
when "0101111000000000" => dout <= "000";
when "0101111100000000" => dout <= "000";
when "0000011100000000" => dout <= "000";
when "0001011100000000" => dout <= "000";
when "0001111100000000" => dout <= "000";
when "1000011011000000" => dout <= "000";
when "1000011000000000" => dout <= "000";
when "1000011001000000" => dout <= "011";
when "1000011010000000" => dout <= "100";
when "1000011000000110" => dout <= "100";
when "1000011111000000" => dout <= "000";
when "1000011100000000" => dout <= "000";
when "1000011101000000" => dout <= "011";
when "1000011110000000" => dout <= "100";
when "1000011100000110" => dout <= "100";
when "1001000100000000" => dout <= "000";
when "1001001000000000" => dout <= "000";
when "1001001100000000" => dout <= "000";
when "1001010000000000" => dout <= "000";
when "1001010100000000" => dout <= "000";
when "1001011000000000" => dout <= "000";
when "1001011100000000" => dout <= "000";
when "1110010000000000" => dout <= "101";
when "1110010100000000" => dout <= "101";
when "1110110000000000" => dout <= "000";
when "1110110100000000" => dout <= "000";
when "1110011000000000" => dout <= "101";
when "1110011100000000" => dout <= "101";
when "1110111100000000" => dout <= "000";
when "1110111000000000" => dout <= "000";
when "1101011100000000" => dout <= "000";
when "1001111100000000" => dout <= "000";
when "1001111000000000" => dout <= "000";
when "1001110000000000" => dout <= "000";
when "1001110100000000" => dout <= "000";
when "1000110100000110" => dout <= "100";
when "1000110111000000" => dout <= "000";
when "1000110100000000" => dout <= "000";
when "1000110101000000" => dout <= "011";
when "1000110110000000" => dout <= "100";
when "1100010100000110" => dout <= "100";
when "1100010100000000" => dout <= "000";
when "1100010101000000" => dout <= "011";
when "1100010110000000" => dout <= "100";
when "1100010000000110" => dout <= "100";
when "1100010000000000" => dout <= "000";
when "1100010001000000" => dout <= "011";
when "1100010010000000" => dout <= "100";
when "0000000011000000" => dout <= "000";
when "0000000000000110" => dout <= "100";
when "0000000000000000" => dout <= "000";
when "0000000001000000" => dout <= "011";
when "0000000010000000" => dout <= "100";
when "0000000111000000" => dout <= "000";
when "0000000100000110" => dout <= "100";
when "0000000100000000" => dout <= "000";
when "0000000101000000" => dout <= "011";
when "0000000110000000" => dout <= "100";
when "0000001011000000" => dout <= "000";
when "0000001000000110" => dout <= "100";
when "0000001000000000" => dout <= "000";
when "0000001001000000" => dout <= "011";
when "0000001010000000" => dout <= "100";
when "0000001111000000" => dout <= "000";
when "0000001100000110" => dout <= "100";
when "0000001100000000" => dout <= "000";
when "0000001101000000" => dout <= "011";
when "0000001110000000" => dout <= "100";
when "1000000011000000" => dout <= "000";
when "1000000000000110" => dout <= "100";
when "1000000000000000" => dout <= "000";
when "1000000001000000" => dout <= "011";
when "1000000010000000" => dout <= "100";
when "1000000111000000" => dout <= "000";
when "1000000100000110" => dout <= "100";
when "1000000100000000" => dout <= "000";
when "1000000101000000" => dout <= "011";
when "1000000110000000" => dout <= "100";
when "1000001111000000" => dout <= "000";
when "1000001100000110" => dout <= "100";
when "1000001100000000" => dout <= "000";
when "1000001101000000" => dout <= "011";
when "1000001110000000" => dout <= "100";
when "0000010000000000" => dout <= "000";
when "0000010100000000" => dout <= "000";
when "0001000011000000" => dout <= "000";
when "0001000000000110" => dout <= "100";
when "0001000000000000" => dout <= "000";
when "0001000001000000" => dout <= "011";
when "0001000010000000" => dout <= "100";
when "0001000111000000" => dout <= "000";
when "0001000100000110" => dout <= "100";
when "0001000100000000" => dout <= "000";
when "0001000101000000" => dout <= "011";
when "0001000110000000" => dout <= "100";
when "0001001011000000" => dout <= "000";
when "0001001000000110" => dout <= "100";
when "0001001000000000" => dout <= "000";
when "0001001001000000" => dout <= "011";
when "0001001010000000" => dout <= "100";
when "0001001111000000" => dout <= "000";
when "0001001100000110" => dout <= "100";
when "0001001100000000" => dout <= "000";
when "0001001101000000" => dout <= "011";
when "0001001110000000" => dout <= "100";
when "1000000011010000" => dout <= "000";
when "1000000000010110" => dout <= "100";
when "1000000000010000" => dout <= "000";
when "1000000001010000" => dout <= "011";
when "1000000010010000" => dout <= "100";
when "1000000111010000" => dout <= "000";
when "1000000100010110" => dout <= "100";
when "1000000100010000" => dout <= "000";
when "1000000101010000" => dout <= "011";
when "1000000110010000" => dout <= "100";
when "1000001111010000" => dout <= "000";
when "1000001100010110" => dout <= "100";
when "1000001100010000" => dout <= "000";
when "1000001101010000" => dout <= "011";
when "1000001110010000" => dout <= "100";
when "0001010000000000" => dout <= "000";
when "0001010100000000" => dout <= "000";
when "0010100011000000" => dout <= "000";
when "0010100000000110" => dout <= "100";
when "0010100000000000" => dout <= "000";
when "0010100001000000" => dout <= "011";
when "0010100010000000" => dout <= "100";
when "0010100111000000" => dout <= "000";
when "0010100100000110" => dout <= "100";
when "0010100100000000" => dout <= "000";
when "0010100101000000" => dout <= "011";
when "0010100110000000" => dout <= "100";
when "0010101011000000" => dout <= "000";
when "0010101000000110" => dout <= "100";
when "0010101000000000" => dout <= "000";
when "0010101001000000" => dout <= "011";
when "0010101010000000" => dout <= "100";
when "0010101111000000" => dout <= "000";
when "0010101100000110" => dout <= "100";
when "0010101100000000" => dout <= "000";
when "0010101101000000" => dout <= "011";
when "0010101110000000" => dout <= "100";
when "1000000011101000" => dout <= "000";
when "1000000000101110" => dout <= "100";
when "1000000000101000" => dout <= "000";
when "1000000001101000" => dout <= "011";
when "1000000010101000" => dout <= "100";
when "1000000111101000" => dout <= "000";
when "1000000100101110" => dout <= "100";
when "1000000100101000" => dout <= "000";
when "1000000101101000" => dout <= "011";
when "1000000110101000" => dout <= "100";
when "1000001111101000" => dout <= "000";
when "1000001100101110" => dout <= "100";
when "1000001100101000" => dout <= "000";
when "1000001101101000" => dout <= "011";
when "1000001110101000" => dout <= "100";
when "0010110000000000" => dout <= "000";
when "0010110100000000" => dout <= "000";
when "0001100011000000" => dout <= "000";
when "0001100000000110" => dout <= "100";
when "0001100000000000" => dout <= "000";
when "0001100001000000" => dout <= "011";
when "0001100010000000" => dout <= "100";
when "0001100111000000" => dout <= "000";
when "0001100100000110" => dout <= "100";
when "0001100100000000" => dout <= "000";
when "0001100101000000" => dout <= "011";
when "0001100110000000" => dout <= "100";
when "0001101011000000" => dout <= "000";
when "0001101000000110" => dout <= "100";
when "0001101000000000" => dout <= "000";
when "0001101001000000" => dout <= "011";
when "0001101010000000" => dout <= "100";
when "0001101111000000" => dout <= "000";
when "0001101100000110" => dout <= "100";
when "0001101100000000" => dout <= "000";
when "0001101101000000" => dout <= "011";
when "0001101110000000" => dout <= "100";
when "1000000011011000" => dout <= "000";
when "1000000000011110" => dout <= "100";
when "1000000000011000" => dout <= "000";
when "1000000001011000" => dout <= "011";
when "1000000010011000" => dout <= "100";
when "1000000111011000" => dout <= "000";
when "1000000100011110" => dout <= "100";
when "1000000100011000" => dout <= "000";
when "1000000101011000" => dout <= "011";
when "1000000110011000" => dout <= "100";
when "1000001111011000" => dout <= "000";
when "1000001100011110" => dout <= "100";
when "1000001100011000" => dout <= "000";
when "1000001101011000" => dout <= "011";
when "1000001110011000" => dout <= "100";
when "0001110000000000" => dout <= "000";
when "0001110100000000" => dout <= "000";
when "1111111011000000" => dout <= "000";
when "1111111000000110" => dout <= "100";
when "1111111000000000" => dout <= "000";
when "1111111001000000" => dout <= "011";
when "1111111010000000" => dout <= "100";
when "1111111100000110" => dout <= "100";
when "1111111100000000" => dout <= "000";
when "1111111101000000" => dout <= "011";
when "1111111110000000" => dout <= "100";
when "0100000000000000" => dout <= "000";
when "0100000100000000" => dout <= "000";
when "0100001000000000" => dout <= "000";
when "0100001100000000" => dout <= "000";
when "0100010000000000" => dout <= "000";
when "0100010100000000" => dout <= "000";
when "0100011000000000" => dout <= "000";
when "0100011100000000" => dout <= "000";
when "1111111011001000" => dout <= "000";
when "1111111000001110" => dout <= "100";
when "1111111000001000" => dout <= "000";
when "1111111001001000" => dout <= "011";
when "1111111010001000" => dout <= "100";
when "1111111100001110" => dout <= "100";
when "1111111100001000" => dout <= "000";
when "1111111101001000" => dout <= "011";
when "1111111110001000" => dout <= "100";
when "0100100000000000" => dout <= "000";
when "0100100100000000" => dout <= "000";
when "0100101000000000" => dout <= "000";
when "0100101100000000" => dout <= "000";
when "0100110000000000" => dout <= "000";
when "0100110100000000" => dout <= "000";
when "0100111000000000" => dout <= "000";
when "0100111100000000" => dout <= "000";
when "0011101011000000" => dout <= "000";
when "0011101000000110" => dout <= "100";
when "0011101000000000" => dout <= "000";
when "0011101001000000" => dout <= "011";
when "0011101010000000" => dout <= "100";
when "0011101111000000" => dout <= "000";
when "0011101100000110" => dout <= "100";
when "0011101100000000" => dout <= "000";
when "0011101101000000" => dout <= "011";
when "0011101110000000" => dout <= "100";
when "0011100000000110" => dout <= "100";
when "0011100000000000" => dout <= "000";
when "0011100001000000" => dout <= "011";
when "0011100010000000" => dout <= "100";
when "0011100011000000" => dout <= "000";
when "0011100100000110" => dout <= "100";
when "0011100100000000" => dout <= "000";
when "0011100101000000" => dout <= "011";
when "0011100110000000" => dout <= "100";
when "0011100111000000" => dout <= "000";
when "1000000011111000" => dout <= "000";
when "1000000000111110" => dout <= "100";
when "1000000000111000" => dout <= "000";
when "1000000001111000" => dout <= "011";
when "1000000010111000" => dout <= "100";
when "1000000111111000" => dout <= "000";
when "1000000100111110" => dout <= "100";
when "1000000100111000" => dout <= "000";
when "1000000101111000" => dout <= "011";
when "1000000110111000" => dout <= "100";
when "1000001111111000" => dout <= "000";
when "1000001100111110" => dout <= "100";
when "1000001100111000" => dout <= "000";
when "1000001101111000" => dout <= "011";
when "1000001110111000" => dout <= "100";
when "0011110000000000" => dout <= "000";
when "0011110100000000" => dout <= "000";
when "1111011011011000" => dout <= "000";
when "1111011000011110" => dout <= "100";
when "1111011000011000" => dout <= "000";
when "1111011001011000" => dout <= "011";
when "1111011010011000" => dout <= "100";
when "1111011111011000" => dout <= "000";
when "1111011100011110" => dout <= "100";
when "1111011100011000" => dout <= "000";
when "1111011101011000" => dout <= "011";
when "1111011110011000" => dout <= "100";
when "0011011100000000" => dout <= "001";
when "0010011100000000" => dout <= "001";
when "0011111100000000" => dout <= "001";
when "0010111100000000" => dout <= "001";
when "1111011011100000" => dout <= "000";
when "1111011000100110" => dout <= "100";
when "1111011000100000" => dout <= "000";
when "1111011001100000" => dout <= "011";
when "1111011010100000" => dout <= "100";
when "1111011111100000" => dout <= "000";
when "1111011100100110" => dout <= "100";
when "1111011100100000" => dout <= "000";
when "1111011101100000" => dout <= "011";
when "1111011110100000" => dout <= "100";
when "1111011011101000" => dout <= "000";
when "1111011000101110" => dout <= "100";
when "1111011000101000" => dout <= "000";
when "1111011001101000" => dout <= "011";
when "1111011010101000" => dout <= "100";
when "1111011111101000" => dout <= "000";
when "1111011100101110" => dout <= "100";
when "1111011100101000" => dout <= "000";
when "1111011101101000" => dout <= "011";
when "1111011110101000" => dout <= "100";
when "1111011011110000" => dout <= "000";
when "1111011000110110" => dout <= "100";
when "1111011000110000" => dout <= "000";
when "1111011001110000" => dout <= "011";
when "1111011010110000" => dout <= "100";
when "1111011111110000" => dout <= "000";
when "1111011100110110" => dout <= "100";
when "1111011100110000" => dout <= "000";
when "1111011101110000" => dout <= "011";
when "1111011110110000" => dout <= "100";
when "1111011011111000" => dout <= "000";
when "1111011000111110" => dout <= "100";
when "1111011000111000" => dout <= "000";
when "1111011001111000" => dout <= "011";
when "1111011010111000" => dout <= "100";
when "1111011111111000" => dout <= "000";
when "1111011100111110" => dout <= "100";
when "1111011100111000" => dout <= "000";
when "1111011101111000" => dout <= "011";
when "1111011110111000" => dout <= "100";
when "1101010000000000" => dout <= "000";
when "1101010100000000" => dout <= "000";
when "1001100000000000" => dout <= "000";
when "1001100100000000" => dout <= "000";
when "1101000011000000" => dout <= "000";
when "1101000000000110" => dout <= "100";
when "1101000000000000" => dout <= "000";
when "1101000001000000" => dout <= "011";
when "1101000010000000" => dout <= "100";
when "1101000111000000" => dout <= "000";
when "1101000100000110" => dout <= "100";
when "1101000100000000" => dout <= "000";
when "1101000101000000" => dout <= "011";
when "1101000110000000" => dout <= "100";
when "1101001011000000" => dout <= "000";
when "1101001000000110" => dout <= "100";
when "1101001000000000" => dout <= "000";
when "1101001001000000" => dout <= "011";
when "1101001010000000" => dout <= "100";
when "1101001111000000" => dout <= "000";
when "1101001100000110" => dout <= "100";
when "1101001100000000" => dout <= "000";
when "1101001101000000" => dout <= "011";
when "1101001110000000" => dout <= "100";
when "0010000011000000" => dout <= "000";
when "0010000000000110" => dout <= "100";
when "0010000000000000" => dout <= "000";
when "0010000001000000" => dout <= "011";
when "0010000010000000" => dout <= "100";
when "0010000111000000" => dout <= "000";
when "0010000100000110" => dout <= "100";
when "0010000100000000" => dout <= "000";
when "0010000101000000" => dout <= "011";
when "0010000110000000" => dout <= "100";
when "0010001011000000" => dout <= "000";
when "0010001000000110" => dout <= "100";
when "0010001000000000" => dout <= "000";
when "0010001001000000" => dout <= "011";
when "0010001010000000" => dout <= "100";
when "0010001111000000" => dout <= "000";
when "0010001100000110" => dout <= "100";
when "0010001100000000" => dout <= "000";
when "0010001101000000" => dout <= "011";
when "0010001110000000" => dout <= "100";
when "1000000011100000" => dout <= "000";
when "1000000000100110" => dout <= "100";
when "1000000000100000" => dout <= "000";
when "1000000001100000" => dout <= "011";
when "1000000010100000" => dout <= "100";
when "1000000111100000" => dout <= "000";
when "1000000100100110" => dout <= "100";
when "1000000100100000" => dout <= "000";
when "1000000101100000" => dout <= "011";
when "1000000110100000" => dout <= "100";
when "1000001111100000" => dout <= "000";
when "1000001100100110" => dout <= "100";
when "1000001100100000" => dout <= "000";
when "1000001101100000" => dout <= "011";
when "1000001110100000" => dout <= "100";
when "0010010000000000" => dout <= "000";
when "0010010100000000" => dout <= "000";
when "0000100000000110" => dout <= "100";
when "0000100000000000" => dout <= "000";
when "0000100001000000" => dout <= "011";
when "0000100010000000" => dout <= "100";
when "0000100011000000" => dout <= "000";
when "0000100100000110" => dout <= "100";
when "0000100100000000" => dout <= "000";
when "0000100101000000" => dout <= "011";
when "0000100110000000" => dout <= "100";
when "0000100111000000" => dout <= "000";
when "0000101011000000" => dout <= "000";
when "0000101000000110" => dout <= "100";
when "0000101000000000" => dout <= "000";
when "0000101001000000" => dout <= "011";
when "0000101010000000" => dout <= "100";
when "0000101111000000" => dout <= "000";
when "0000101100000110" => dout <= "100";
when "0000101100000000" => dout <= "000";
when "0000101101000000" => dout <= "011";
when "0000101110000000" => dout <= "100";
when "1000000011001000" => dout <= "000";
when "1000000000001110" => dout <= "100";
when "1000000000001000" => dout <= "000";
when "1000000001001000" => dout <= "011";
when "1000000010001000" => dout <= "100";
when "1000000111001000" => dout <= "000";
when "1000000100001110" => dout <= "100";
when "1000000100001000" => dout <= "000";
when "1000000101001000" => dout <= "011";
when "1000000110001000" => dout <= "100";
when "1000001111001000" => dout <= "000";
when "1000001100001110" => dout <= "100";
when "1000001100001000" => dout <= "000";
when "1000001101001000" => dout <= "011";
when "1000001110001000" => dout <= "100";
when "0000110000000000" => dout <= "000";
when "0000110100000000" => dout <= "000";
when "1000010000000110" => dout <= "100";
when "1000010000000000" => dout <= "000";
when "1000010001000000" => dout <= "011";
when "1000010010000000" => dout <= "100";
when "1000010100000110" => dout <= "100";
when "1000010100000000" => dout <= "000";
when "1000010101000000" => dout <= "011";
when "1000010110000000" => dout <= "100";
when "1000010011000000" => dout <= "000";
when "1000010111000000" => dout <= "000";
when "1111011011000000" => dout <= "000";
when "1111011000000110" => dout <= "100";
when "1111011000000000" => dout <= "000";
when "1111011001000000" => dout <= "011";
when "1111011010000000" => dout <= "100";
when "1111011111000000" => dout <= "000";
when "1111011100000110" => dout <= "100";
when "1111011100000000" => dout <= "000";
when "1111011101000000" => dout <= "011";
when "1111011110000000" => dout <= "100";
when "1010100000000000" => dout <= "000";
when "1010100100000000" => dout <= "000";
when "0011000000000110" => dout <= "100";
when "0011000000000000" => dout <= "000";
when "0011000001000000" => dout <= "011";
when "0011000010000000" => dout <= "100";
when "0011000011000000" => dout <= "000";
when "0011000100000110" => dout <= "100";
when "0011000100000000" => dout <= "000";
when "0011000101000000" => dout <= "011";
when "0011000110000000" => dout <= "100";
when "0011000111000000" => dout <= "000";
when "0011001011000000" => dout <= "000";
when "0011001000000110" => dout <= "100";
when "0011001000000000" => dout <= "000";
when "0011001001000000" => dout <= "011";
when "0011001010000000" => dout <= "100";
when "0011001111000000" => dout <= "000";
when "0011001100000110" => dout <= "100";
when "0011001100000000" => dout <= "000";
when "0011001101000000" => dout <= "011";
when "0011001110000000" => dout <= "100";
when "1000000011110000" => dout <= "000";
when "1000000000110110" => dout <= "100";
when "1000000000110000" => dout <= "000";
when "1000000001110000" => dout <= "011";
when "1000000010110000" => dout <= "100";
when "1000000111110000" => dout <= "000";
when "1000000100110110" => dout <= "100";
when "1000000100110000" => dout <= "000";
when "1000000101110000" => dout <= "011";
when "1000000110110000" => dout <= "100";
when "1000001111110000" => dout <= "000";
when "1000001100110110" => dout <= "100";
when "1000001100110000" => dout <= "000";
when "1000001101110000" => dout <= "011";
when "1000001110110000" => dout <= "100";
when "0011010000000000" => dout <= "000";
when "0011010100000000" => dout <= "000";
when "1111011011010000" => dout <= "000";
when "1111011000010110" => dout <= "100";
when "1111011000010000" => dout <= "000";
when "1111011001010000" => dout <= "011";
when "1111011010010000" => dout <= "100";
when "1111011111010000" => dout <= "000";
when "1111011100010110" => dout <= "100";
when "1111011100010000" => dout <= "000";
when "1111011101010000" => dout <= "011";
when "1111011110010000" => dout <= "100";
when "1010010000000000" => dout <= "000";
when "1010010100000000" => dout <= "000";
when "1010011000000000" => dout <= "000";
when "1010011100000000" => dout <= "000";
when "1010111000000000" => dout <= "000";
when "1010111100000000" => dout <= "000";
when "1010110000000000" => dout <= "000";
when "1010110100000000" => dout <= "000";
when "1010101000000000" => dout <= "000";
when "1010101100000000" => dout <= "000";
when "1111001000000000" => dout <= "000";
when "1111001100000000" => dout <= "000";
when "0110000000000000" => dout <= "000";
when "0110000100000000" => dout <= "000";
when "1100100000000000" => dout <= "000";
when "1100100100000000" => dout <= "000";
when "0110001000000000" => dout <= "000";
when "0110110000000000" => dout <= "000";
when "0110110100000000" => dout <= "000";
when "0110111000000000" => dout <= "000";
when "0110111100000000" => dout <= "000";
when "0000111100000000" => dout <= "000";
when "0110001100000000" => dout <= "000";
when "0110010000000000" => dout <= "000";
when "0110010100000000" => dout <= "000";
when "0110011000000000" => dout <= "000";
when "0110011100000000" => dout <= "000";
when "1000001000000000" => dout <= "000";
when "1101011000000000" => dout <= "000";
when "1111000100000000" => dout <= "000";
when "1100000000000000" => dout <= "000";
when "1100000100000000" => dout <= "000";
when others => dout <= "---";
end case;
end process;
end rtl; |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity a_table is
port ( addr : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(2 downto 0));
end a_table;
architecture rtl of a_table is
begin
process(addr)
begin
case addr is
when "1110101100000000" => dout <= "001";
when "1110100100000000" => dout <= "010";
when "1111111111100000" => dout <= "000";
when "1111111100100110" => dout <= "100";
when "1111111100100000" => dout <= "000";
when "1111111101100000" => dout <= "011";
when "1111111110100000" => dout <= "100";
when "1110101000000000" => dout <= "010";
when "1111111100101110" => dout <= "100";
when "1111111100101000" => dout <= "000";
when "1111111101101000" => dout <= "011";
when "1111111110101000" => dout <= "100";
when "1110100000000000" => dout <= "010";
when "1111111111010000" => dout <= "000";
when "1111111100010110" => dout <= "100";
when "1111111100010000" => dout <= "000";
when "1111111101010000" => dout <= "011";
when "1111111110010000" => dout <= "100";
when "1001101000000000" => dout <= "010";
when "1111111100011110" => dout <= "100";
when "1111111100011000" => dout <= "000";
when "1111111101011000" => dout <= "011";
when "1111111110011000" => dout <= "100";
when "1100001100000000" => dout <= "000";
when "1100001000000000" => dout <= "000";
when "1100101100000000" => dout <= "000";
when "1100101000000000" => dout <= "000";
when "0111010000000000" => dout <= "001";
when "0111110000000000" => dout <= "001";
when "0111111000000000" => dout <= "001";
when "0111001000000000" => dout <= "001";
when "0111011000000000" => dout <= "001";
when "0111101000000000" => dout <= "001";
when "0111000000000000" => dout <= "001";
when "0111100000000000" => dout <= "001";
when "0111010100000000" => dout <= "001";
when "0111110100000000" => dout <= "001";
when "0111111100000000" => dout <= "001";
when "0111001100000000" => dout <= "001";
when "0111011100000000" => dout <= "001";
when "0111101100000000" => dout <= "001";
when "0111000100000000" => dout <= "001";
when "0111100100000000" => dout <= "001";
when "1110001100000000" => dout <= "001";
when "1110001000000000" => dout <= "001";
when "1110000100000000" => dout <= "001";
when "1110000000000000" => dout <= "001";
when "1100110100000000" => dout <= "101";
when "1100110000000000" => dout <= "110";
when "1100111000000000" => dout <= "111";
when "1100111100000000" => dout <= "000";
when "1111100000000000" => dout <= "000";
when "1111010100000000" => dout <= "000";
when "1111100100000000" => dout <= "000";
when "1111110000000000" => dout <= "000";
when "1111110100000000" => dout <= "000";
when "1111101000000000" => dout <= "000";
when "1111101100000000" => dout <= "000";
when "1111010000000000" => dout <= "000";
when "1001101100000000" => dout <= "000";
when "1111000000000000" => dout <= "000";
when "1001000000000000" => dout <= "000";
when "0010011000000000" => dout <= "000";
when "0010111000000000" => dout <= "000";
when "0011011000000000" => dout <= "000";
when "0011111000000000" => dout <= "000";
when "1000100011000000" => dout <= "000";
when "1000100000000000" => dout <= "000";
when "1000100001000000" => dout <= "011";
when "1000100010000000" => dout <= "100";
when "1000100000000110" => dout <= "100";
when "1000100111000000" => dout <= "000";
when "1000100100000000" => dout <= "000";
when "1000100101000000" => dout <= "011";
when "1000100110000000" => dout <= "100";
when "1000100100000110" => dout <= "100";
when "1000101011000000" => dout <= "000";
when "1000101000000000" => dout <= "000";
when "1000101001000000" => dout <= "011";
when "1000101010000000" => dout <= "100";
when "1000101000000110" => dout <= "100";
when "1000101111000000" => dout <= "000";
when "1000101100000000" => dout <= "000";
when "1000101101000000" => dout <= "011";
when "1000101110000000" => dout <= "100";
when "1000101100000110" => dout <= "100";
when "1100011000000000" => dout <= "000";
when "1100011001000000" => dout <= "011";
when "1100011010000000" => dout <= "100";
when "1100011000000110" => dout <= "100";
when "1100011100000000" => dout <= "000";
when "1100011101000000" => dout <= "011";
when "1100011110000000" => dout <= "100";
when "1100011100000110" => dout <= "100";
when "1011000000000000" => dout <= "000";
when "1011000100000000" => dout <= "000";
when "1011001000000000" => dout <= "000";
when "1011001100000000" => dout <= "000";
when "1011010000000000" => dout <= "000";
when "1011010100000000" => dout <= "000";
when "1011011000000000" => dout <= "000";
when "1011011100000000" => dout <= "000";
when "1011100000000000" => dout <= "000";
when "1011100100000000" => dout <= "000";
when "1011101000000000" => dout <= "000";
when "1011101100000000" => dout <= "000";
when "1011110000000000" => dout <= "000";
when "1011110100000000" => dout <= "000";
when "1011111000000000" => dout <= "000";
when "1011111100000000" => dout <= "000";
when "1010000000000000" => dout <= "010";
when "1010000100000000" => dout <= "010";
when "1010001000000000" => dout <= "010";
when "1010001100000000" => dout <= "010";
when "1000111011000000" => dout <= "000";
when "1000111000000000" => dout <= "000";
when "1000111001000000" => dout <= "011";
when "1000111010000000" => dout <= "100";
when "1000111000000110" => dout <= "100";
when "1000110011000000" => dout <= "000";
when "1000110000000000" => dout <= "000";
when "1000110001000000" => dout <= "011";
when "1000110010000000" => dout <= "100";
when "1000110000000110" => dout <= "100";
when "1111111100110000" => dout <= "000";
when "1111111101110000" => dout <= "011";
when "1111111110110000" => dout <= "100";
when "1111111100110110" => dout <= "100";
when "0101000000000000" => dout <= "000";
when "0101000100000000" => dout <= "000";
when "0101001000000000" => dout <= "000";
when "0101001100000000" => dout <= "000";
when "0101010000000000" => dout <= "000";
when "0101010100000000" => dout <= "000";
when "0101011000000000" => dout <= "000";
when "0101011100000000" => dout <= "000";
when "0000011000000000" => dout <= "000";
when "0000111000000000" => dout <= "000";
when "0001011000000000" => dout <= "000";
when "0001111000000000" => dout <= "000";
when "1000111100000000" => dout <= "000";
when "1000111101000000" => dout <= "011";
when "1000111110000000" => dout <= "100";
when "1000111100000110" => dout <= "100";
when "1000111111000000" => dout <= "000";
when "0101100000000000" => dout <= "000";
when "0101100100000000" => dout <= "000";
when "0101101000000000" => dout <= "000";
when "0101101100000000" => dout <= "000";
when "0101110000000000" => dout <= "000";
when "0101110100000000" => dout <= "000";
when "0101111000000000" => dout <= "000";
when "0101111100000000" => dout <= "000";
when "0000011100000000" => dout <= "000";
when "0001011100000000" => dout <= "000";
when "0001111100000000" => dout <= "000";
when "1000011011000000" => dout <= "000";
when "1000011000000000" => dout <= "000";
when "1000011001000000" => dout <= "011";
when "1000011010000000" => dout <= "100";
when "1000011000000110" => dout <= "100";
when "1000011111000000" => dout <= "000";
when "1000011100000000" => dout <= "000";
when "1000011101000000" => dout <= "011";
when "1000011110000000" => dout <= "100";
when "1000011100000110" => dout <= "100";
when "1001000100000000" => dout <= "000";
when "1001001000000000" => dout <= "000";
when "1001001100000000" => dout <= "000";
when "1001010000000000" => dout <= "000";
when "1001010100000000" => dout <= "000";
when "1001011000000000" => dout <= "000";
when "1001011100000000" => dout <= "000";
when "1110010000000000" => dout <= "101";
when "1110010100000000" => dout <= "101";
when "1110110000000000" => dout <= "000";
when "1110110100000000" => dout <= "000";
when "1110011000000000" => dout <= "101";
when "1110011100000000" => dout <= "101";
when "1110111100000000" => dout <= "000";
when "1110111000000000" => dout <= "000";
when "1101011100000000" => dout <= "000";
when "1001111100000000" => dout <= "000";
when "1001111000000000" => dout <= "000";
when "1001110000000000" => dout <= "000";
when "1001110100000000" => dout <= "000";
when "1000110100000110" => dout <= "100";
when "1000110111000000" => dout <= "000";
when "1000110100000000" => dout <= "000";
when "1000110101000000" => dout <= "011";
when "1000110110000000" => dout <= "100";
when "1100010100000110" => dout <= "100";
when "1100010100000000" => dout <= "000";
when "1100010101000000" => dout <= "011";
when "1100010110000000" => dout <= "100";
when "1100010000000110" => dout <= "100";
when "1100010000000000" => dout <= "000";
when "1100010001000000" => dout <= "011";
when "1100010010000000" => dout <= "100";
when "0000000011000000" => dout <= "000";
when "0000000000000110" => dout <= "100";
when "0000000000000000" => dout <= "000";
when "0000000001000000" => dout <= "011";
when "0000000010000000" => dout <= "100";
when "0000000111000000" => dout <= "000";
when "0000000100000110" => dout <= "100";
when "0000000100000000" => dout <= "000";
when "0000000101000000" => dout <= "011";
when "0000000110000000" => dout <= "100";
when "0000001011000000" => dout <= "000";
when "0000001000000110" => dout <= "100";
when "0000001000000000" => dout <= "000";
when "0000001001000000" => dout <= "011";
when "0000001010000000" => dout <= "100";
when "0000001111000000" => dout <= "000";
when "0000001100000110" => dout <= "100";
when "0000001100000000" => dout <= "000";
when "0000001101000000" => dout <= "011";
when "0000001110000000" => dout <= "100";
when "1000000011000000" => dout <= "000";
when "1000000000000110" => dout <= "100";
when "1000000000000000" => dout <= "000";
when "1000000001000000" => dout <= "011";
when "1000000010000000" => dout <= "100";
when "1000000111000000" => dout <= "000";
when "1000000100000110" => dout <= "100";
when "1000000100000000" => dout <= "000";
when "1000000101000000" => dout <= "011";
when "1000000110000000" => dout <= "100";
when "1000001111000000" => dout <= "000";
when "1000001100000110" => dout <= "100";
when "1000001100000000" => dout <= "000";
when "1000001101000000" => dout <= "011";
when "1000001110000000" => dout <= "100";
when "0000010000000000" => dout <= "000";
when "0000010100000000" => dout <= "000";
when "0001000011000000" => dout <= "000";
when "0001000000000110" => dout <= "100";
when "0001000000000000" => dout <= "000";
when "0001000001000000" => dout <= "011";
when "0001000010000000" => dout <= "100";
when "0001000111000000" => dout <= "000";
when "0001000100000110" => dout <= "100";
when "0001000100000000" => dout <= "000";
when "0001000101000000" => dout <= "011";
when "0001000110000000" => dout <= "100";
when "0001001011000000" => dout <= "000";
when "0001001000000110" => dout <= "100";
when "0001001000000000" => dout <= "000";
when "0001001001000000" => dout <= "011";
when "0001001010000000" => dout <= "100";
when "0001001111000000" => dout <= "000";
when "0001001100000110" => dout <= "100";
when "0001001100000000" => dout <= "000";
when "0001001101000000" => dout <= "011";
when "0001001110000000" => dout <= "100";
when "1000000011010000" => dout <= "000";
when "1000000000010110" => dout <= "100";
when "1000000000010000" => dout <= "000";
when "1000000001010000" => dout <= "011";
when "1000000010010000" => dout <= "100";
when "1000000111010000" => dout <= "000";
when "1000000100010110" => dout <= "100";
when "1000000100010000" => dout <= "000";
when "1000000101010000" => dout <= "011";
when "1000000110010000" => dout <= "100";
when "1000001111010000" => dout <= "000";
when "1000001100010110" => dout <= "100";
when "1000001100010000" => dout <= "000";
when "1000001101010000" => dout <= "011";
when "1000001110010000" => dout <= "100";
when "0001010000000000" => dout <= "000";
when "0001010100000000" => dout <= "000";
when "0010100011000000" => dout <= "000";
when "0010100000000110" => dout <= "100";
when "0010100000000000" => dout <= "000";
when "0010100001000000" => dout <= "011";
when "0010100010000000" => dout <= "100";
when "0010100111000000" => dout <= "000";
when "0010100100000110" => dout <= "100";
when "0010100100000000" => dout <= "000";
when "0010100101000000" => dout <= "011";
when "0010100110000000" => dout <= "100";
when "0010101011000000" => dout <= "000";
when "0010101000000110" => dout <= "100";
when "0010101000000000" => dout <= "000";
when "0010101001000000" => dout <= "011";
when "0010101010000000" => dout <= "100";
when "0010101111000000" => dout <= "000";
when "0010101100000110" => dout <= "100";
when "0010101100000000" => dout <= "000";
when "0010101101000000" => dout <= "011";
when "0010101110000000" => dout <= "100";
when "1000000011101000" => dout <= "000";
when "1000000000101110" => dout <= "100";
when "1000000000101000" => dout <= "000";
when "1000000001101000" => dout <= "011";
when "1000000010101000" => dout <= "100";
when "1000000111101000" => dout <= "000";
when "1000000100101110" => dout <= "100";
when "1000000100101000" => dout <= "000";
when "1000000101101000" => dout <= "011";
when "1000000110101000" => dout <= "100";
when "1000001111101000" => dout <= "000";
when "1000001100101110" => dout <= "100";
when "1000001100101000" => dout <= "000";
when "1000001101101000" => dout <= "011";
when "1000001110101000" => dout <= "100";
when "0010110000000000" => dout <= "000";
when "0010110100000000" => dout <= "000";
when "0001100011000000" => dout <= "000";
when "0001100000000110" => dout <= "100";
when "0001100000000000" => dout <= "000";
when "0001100001000000" => dout <= "011";
when "0001100010000000" => dout <= "100";
when "0001100111000000" => dout <= "000";
when "0001100100000110" => dout <= "100";
when "0001100100000000" => dout <= "000";
when "0001100101000000" => dout <= "011";
when "0001100110000000" => dout <= "100";
when "0001101011000000" => dout <= "000";
when "0001101000000110" => dout <= "100";
when "0001101000000000" => dout <= "000";
when "0001101001000000" => dout <= "011";
when "0001101010000000" => dout <= "100";
when "0001101111000000" => dout <= "000";
when "0001101100000110" => dout <= "100";
when "0001101100000000" => dout <= "000";
when "0001101101000000" => dout <= "011";
when "0001101110000000" => dout <= "100";
when "1000000011011000" => dout <= "000";
when "1000000000011110" => dout <= "100";
when "1000000000011000" => dout <= "000";
when "1000000001011000" => dout <= "011";
when "1000000010011000" => dout <= "100";
when "1000000111011000" => dout <= "000";
when "1000000100011110" => dout <= "100";
when "1000000100011000" => dout <= "000";
when "1000000101011000" => dout <= "011";
when "1000000110011000" => dout <= "100";
when "1000001111011000" => dout <= "000";
when "1000001100011110" => dout <= "100";
when "1000001100011000" => dout <= "000";
when "1000001101011000" => dout <= "011";
when "1000001110011000" => dout <= "100";
when "0001110000000000" => dout <= "000";
when "0001110100000000" => dout <= "000";
when "1111111011000000" => dout <= "000";
when "1111111000000110" => dout <= "100";
when "1111111000000000" => dout <= "000";
when "1111111001000000" => dout <= "011";
when "1111111010000000" => dout <= "100";
when "1111111100000110" => dout <= "100";
when "1111111100000000" => dout <= "000";
when "1111111101000000" => dout <= "011";
when "1111111110000000" => dout <= "100";
when "0100000000000000" => dout <= "000";
when "0100000100000000" => dout <= "000";
when "0100001000000000" => dout <= "000";
when "0100001100000000" => dout <= "000";
when "0100010000000000" => dout <= "000";
when "0100010100000000" => dout <= "000";
when "0100011000000000" => dout <= "000";
when "0100011100000000" => dout <= "000";
when "1111111011001000" => dout <= "000";
when "1111111000001110" => dout <= "100";
when "1111111000001000" => dout <= "000";
when "1111111001001000" => dout <= "011";
when "1111111010001000" => dout <= "100";
when "1111111100001110" => dout <= "100";
when "1111111100001000" => dout <= "000";
when "1111111101001000" => dout <= "011";
when "1111111110001000" => dout <= "100";
when "0100100000000000" => dout <= "000";
when "0100100100000000" => dout <= "000";
when "0100101000000000" => dout <= "000";
when "0100101100000000" => dout <= "000";
when "0100110000000000" => dout <= "000";
when "0100110100000000" => dout <= "000";
when "0100111000000000" => dout <= "000";
when "0100111100000000" => dout <= "000";
when "0011101011000000" => dout <= "000";
when "0011101000000110" => dout <= "100";
when "0011101000000000" => dout <= "000";
when "0011101001000000" => dout <= "011";
when "0011101010000000" => dout <= "100";
when "0011101111000000" => dout <= "000";
when "0011101100000110" => dout <= "100";
when "0011101100000000" => dout <= "000";
when "0011101101000000" => dout <= "011";
when "0011101110000000" => dout <= "100";
when "0011100000000110" => dout <= "100";
when "0011100000000000" => dout <= "000";
when "0011100001000000" => dout <= "011";
when "0011100010000000" => dout <= "100";
when "0011100011000000" => dout <= "000";
when "0011100100000110" => dout <= "100";
when "0011100100000000" => dout <= "000";
when "0011100101000000" => dout <= "011";
when "0011100110000000" => dout <= "100";
when "0011100111000000" => dout <= "000";
when "1000000011111000" => dout <= "000";
when "1000000000111110" => dout <= "100";
when "1000000000111000" => dout <= "000";
when "1000000001111000" => dout <= "011";
when "1000000010111000" => dout <= "100";
when "1000000111111000" => dout <= "000";
when "1000000100111110" => dout <= "100";
when "1000000100111000" => dout <= "000";
when "1000000101111000" => dout <= "011";
when "1000000110111000" => dout <= "100";
when "1000001111111000" => dout <= "000";
when "1000001100111110" => dout <= "100";
when "1000001100111000" => dout <= "000";
when "1000001101111000" => dout <= "011";
when "1000001110111000" => dout <= "100";
when "0011110000000000" => dout <= "000";
when "0011110100000000" => dout <= "000";
when "1111011011011000" => dout <= "000";
when "1111011000011110" => dout <= "100";
when "1111011000011000" => dout <= "000";
when "1111011001011000" => dout <= "011";
when "1111011010011000" => dout <= "100";
when "1111011111011000" => dout <= "000";
when "1111011100011110" => dout <= "100";
when "1111011100011000" => dout <= "000";
when "1111011101011000" => dout <= "011";
when "1111011110011000" => dout <= "100";
when "0011011100000000" => dout <= "001";
when "0010011100000000" => dout <= "001";
when "0011111100000000" => dout <= "001";
when "0010111100000000" => dout <= "001";
when "1111011011100000" => dout <= "000";
when "1111011000100110" => dout <= "100";
when "1111011000100000" => dout <= "000";
when "1111011001100000" => dout <= "011";
when "1111011010100000" => dout <= "100";
when "1111011111100000" => dout <= "000";
when "1111011100100110" => dout <= "100";
when "1111011100100000" => dout <= "000";
when "1111011101100000" => dout <= "011";
when "1111011110100000" => dout <= "100";
when "1111011011101000" => dout <= "000";
when "1111011000101110" => dout <= "100";
when "1111011000101000" => dout <= "000";
when "1111011001101000" => dout <= "011";
when "1111011010101000" => dout <= "100";
when "1111011111101000" => dout <= "000";
when "1111011100101110" => dout <= "100";
when "1111011100101000" => dout <= "000";
when "1111011101101000" => dout <= "011";
when "1111011110101000" => dout <= "100";
when "1111011011110000" => dout <= "000";
when "1111011000110110" => dout <= "100";
when "1111011000110000" => dout <= "000";
when "1111011001110000" => dout <= "011";
when "1111011010110000" => dout <= "100";
when "1111011111110000" => dout <= "000";
when "1111011100110110" => dout <= "100";
when "1111011100110000" => dout <= "000";
when "1111011101110000" => dout <= "011";
when "1111011110110000" => dout <= "100";
when "1111011011111000" => dout <= "000";
when "1111011000111110" => dout <= "100";
when "1111011000111000" => dout <= "000";
when "1111011001111000" => dout <= "011";
when "1111011010111000" => dout <= "100";
when "1111011111111000" => dout <= "000";
when "1111011100111110" => dout <= "100";
when "1111011100111000" => dout <= "000";
when "1111011101111000" => dout <= "011";
when "1111011110111000" => dout <= "100";
when "1101010000000000" => dout <= "000";
when "1101010100000000" => dout <= "000";
when "1001100000000000" => dout <= "000";
when "1001100100000000" => dout <= "000";
when "1101000011000000" => dout <= "000";
when "1101000000000110" => dout <= "100";
when "1101000000000000" => dout <= "000";
when "1101000001000000" => dout <= "011";
when "1101000010000000" => dout <= "100";
when "1101000111000000" => dout <= "000";
when "1101000100000110" => dout <= "100";
when "1101000100000000" => dout <= "000";
when "1101000101000000" => dout <= "011";
when "1101000110000000" => dout <= "100";
when "1101001011000000" => dout <= "000";
when "1101001000000110" => dout <= "100";
when "1101001000000000" => dout <= "000";
when "1101001001000000" => dout <= "011";
when "1101001010000000" => dout <= "100";
when "1101001111000000" => dout <= "000";
when "1101001100000110" => dout <= "100";
when "1101001100000000" => dout <= "000";
when "1101001101000000" => dout <= "011";
when "1101001110000000" => dout <= "100";
when "0010000011000000" => dout <= "000";
when "0010000000000110" => dout <= "100";
when "0010000000000000" => dout <= "000";
when "0010000001000000" => dout <= "011";
when "0010000010000000" => dout <= "100";
when "0010000111000000" => dout <= "000";
when "0010000100000110" => dout <= "100";
when "0010000100000000" => dout <= "000";
when "0010000101000000" => dout <= "011";
when "0010000110000000" => dout <= "100";
when "0010001011000000" => dout <= "000";
when "0010001000000110" => dout <= "100";
when "0010001000000000" => dout <= "000";
when "0010001001000000" => dout <= "011";
when "0010001010000000" => dout <= "100";
when "0010001111000000" => dout <= "000";
when "0010001100000110" => dout <= "100";
when "0010001100000000" => dout <= "000";
when "0010001101000000" => dout <= "011";
when "0010001110000000" => dout <= "100";
when "1000000011100000" => dout <= "000";
when "1000000000100110" => dout <= "100";
when "1000000000100000" => dout <= "000";
when "1000000001100000" => dout <= "011";
when "1000000010100000" => dout <= "100";
when "1000000111100000" => dout <= "000";
when "1000000100100110" => dout <= "100";
when "1000000100100000" => dout <= "000";
when "1000000101100000" => dout <= "011";
when "1000000110100000" => dout <= "100";
when "1000001111100000" => dout <= "000";
when "1000001100100110" => dout <= "100";
when "1000001100100000" => dout <= "000";
when "1000001101100000" => dout <= "011";
when "1000001110100000" => dout <= "100";
when "0010010000000000" => dout <= "000";
when "0010010100000000" => dout <= "000";
when "0000100000000110" => dout <= "100";
when "0000100000000000" => dout <= "000";
when "0000100001000000" => dout <= "011";
when "0000100010000000" => dout <= "100";
when "0000100011000000" => dout <= "000";
when "0000100100000110" => dout <= "100";
when "0000100100000000" => dout <= "000";
when "0000100101000000" => dout <= "011";
when "0000100110000000" => dout <= "100";
when "0000100111000000" => dout <= "000";
when "0000101011000000" => dout <= "000";
when "0000101000000110" => dout <= "100";
when "0000101000000000" => dout <= "000";
when "0000101001000000" => dout <= "011";
when "0000101010000000" => dout <= "100";
when "0000101111000000" => dout <= "000";
when "0000101100000110" => dout <= "100";
when "0000101100000000" => dout <= "000";
when "0000101101000000" => dout <= "011";
when "0000101110000000" => dout <= "100";
when "1000000011001000" => dout <= "000";
when "1000000000001110" => dout <= "100";
when "1000000000001000" => dout <= "000";
when "1000000001001000" => dout <= "011";
when "1000000010001000" => dout <= "100";
when "1000000111001000" => dout <= "000";
when "1000000100001110" => dout <= "100";
when "1000000100001000" => dout <= "000";
when "1000000101001000" => dout <= "011";
when "1000000110001000" => dout <= "100";
when "1000001111001000" => dout <= "000";
when "1000001100001110" => dout <= "100";
when "1000001100001000" => dout <= "000";
when "1000001101001000" => dout <= "011";
when "1000001110001000" => dout <= "100";
when "0000110000000000" => dout <= "000";
when "0000110100000000" => dout <= "000";
when "1000010000000110" => dout <= "100";
when "1000010000000000" => dout <= "000";
when "1000010001000000" => dout <= "011";
when "1000010010000000" => dout <= "100";
when "1000010100000110" => dout <= "100";
when "1000010100000000" => dout <= "000";
when "1000010101000000" => dout <= "011";
when "1000010110000000" => dout <= "100";
when "1000010011000000" => dout <= "000";
when "1000010111000000" => dout <= "000";
when "1111011011000000" => dout <= "000";
when "1111011000000110" => dout <= "100";
when "1111011000000000" => dout <= "000";
when "1111011001000000" => dout <= "011";
when "1111011010000000" => dout <= "100";
when "1111011111000000" => dout <= "000";
when "1111011100000110" => dout <= "100";
when "1111011100000000" => dout <= "000";
when "1111011101000000" => dout <= "011";
when "1111011110000000" => dout <= "100";
when "1010100000000000" => dout <= "000";
when "1010100100000000" => dout <= "000";
when "0011000000000110" => dout <= "100";
when "0011000000000000" => dout <= "000";
when "0011000001000000" => dout <= "011";
when "0011000010000000" => dout <= "100";
when "0011000011000000" => dout <= "000";
when "0011000100000110" => dout <= "100";
when "0011000100000000" => dout <= "000";
when "0011000101000000" => dout <= "011";
when "0011000110000000" => dout <= "100";
when "0011000111000000" => dout <= "000";
when "0011001011000000" => dout <= "000";
when "0011001000000110" => dout <= "100";
when "0011001000000000" => dout <= "000";
when "0011001001000000" => dout <= "011";
when "0011001010000000" => dout <= "100";
when "0011001111000000" => dout <= "000";
when "0011001100000110" => dout <= "100";
when "0011001100000000" => dout <= "000";
when "0011001101000000" => dout <= "011";
when "0011001110000000" => dout <= "100";
when "1000000011110000" => dout <= "000";
when "1000000000110110" => dout <= "100";
when "1000000000110000" => dout <= "000";
when "1000000001110000" => dout <= "011";
when "1000000010110000" => dout <= "100";
when "1000000111110000" => dout <= "000";
when "1000000100110110" => dout <= "100";
when "1000000100110000" => dout <= "000";
when "1000000101110000" => dout <= "011";
when "1000000110110000" => dout <= "100";
when "1000001111110000" => dout <= "000";
when "1000001100110110" => dout <= "100";
when "1000001100110000" => dout <= "000";
when "1000001101110000" => dout <= "011";
when "1000001110110000" => dout <= "100";
when "0011010000000000" => dout <= "000";
when "0011010100000000" => dout <= "000";
when "1111011011010000" => dout <= "000";
when "1111011000010110" => dout <= "100";
when "1111011000010000" => dout <= "000";
when "1111011001010000" => dout <= "011";
when "1111011010010000" => dout <= "100";
when "1111011111010000" => dout <= "000";
when "1111011100010110" => dout <= "100";
when "1111011100010000" => dout <= "000";
when "1111011101010000" => dout <= "011";
when "1111011110010000" => dout <= "100";
when "1010010000000000" => dout <= "000";
when "1010010100000000" => dout <= "000";
when "1010011000000000" => dout <= "000";
when "1010011100000000" => dout <= "000";
when "1010111000000000" => dout <= "000";
when "1010111100000000" => dout <= "000";
when "1010110000000000" => dout <= "000";
when "1010110100000000" => dout <= "000";
when "1010101000000000" => dout <= "000";
when "1010101100000000" => dout <= "000";
when "1111001000000000" => dout <= "000";
when "1111001100000000" => dout <= "000";
when "0110000000000000" => dout <= "000";
when "0110000100000000" => dout <= "000";
when "1100100000000000" => dout <= "000";
when "1100100100000000" => dout <= "000";
when "0110001000000000" => dout <= "000";
when "0110110000000000" => dout <= "000";
when "0110110100000000" => dout <= "000";
when "0110111000000000" => dout <= "000";
when "0110111100000000" => dout <= "000";
when "0000111100000000" => dout <= "000";
when "0110001100000000" => dout <= "000";
when "0110010000000000" => dout <= "000";
when "0110010100000000" => dout <= "000";
when "0110011000000000" => dout <= "000";
when "0110011100000000" => dout <= "000";
when "1000001000000000" => dout <= "000";
when "1101011000000000" => dout <= "000";
when "1111000100000000" => dout <= "000";
when "1100000000000000" => dout <= "000";
when "1100000100000000" => dout <= "000";
when others => dout <= "---";
end case;
end process;
end rtl; |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity a_table is
port ( addr : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(2 downto 0));
end a_table;
architecture rtl of a_table is
begin
process(addr)
begin
case addr is
when "1110101100000000" => dout <= "001";
when "1110100100000000" => dout <= "010";
when "1111111111100000" => dout <= "000";
when "1111111100100110" => dout <= "100";
when "1111111100100000" => dout <= "000";
when "1111111101100000" => dout <= "011";
when "1111111110100000" => dout <= "100";
when "1110101000000000" => dout <= "010";
when "1111111100101110" => dout <= "100";
when "1111111100101000" => dout <= "000";
when "1111111101101000" => dout <= "011";
when "1111111110101000" => dout <= "100";
when "1110100000000000" => dout <= "010";
when "1111111111010000" => dout <= "000";
when "1111111100010110" => dout <= "100";
when "1111111100010000" => dout <= "000";
when "1111111101010000" => dout <= "011";
when "1111111110010000" => dout <= "100";
when "1001101000000000" => dout <= "010";
when "1111111100011110" => dout <= "100";
when "1111111100011000" => dout <= "000";
when "1111111101011000" => dout <= "011";
when "1111111110011000" => dout <= "100";
when "1100001100000000" => dout <= "000";
when "1100001000000000" => dout <= "000";
when "1100101100000000" => dout <= "000";
when "1100101000000000" => dout <= "000";
when "0111010000000000" => dout <= "001";
when "0111110000000000" => dout <= "001";
when "0111111000000000" => dout <= "001";
when "0111001000000000" => dout <= "001";
when "0111011000000000" => dout <= "001";
when "0111101000000000" => dout <= "001";
when "0111000000000000" => dout <= "001";
when "0111100000000000" => dout <= "001";
when "0111010100000000" => dout <= "001";
when "0111110100000000" => dout <= "001";
when "0111111100000000" => dout <= "001";
when "0111001100000000" => dout <= "001";
when "0111011100000000" => dout <= "001";
when "0111101100000000" => dout <= "001";
when "0111000100000000" => dout <= "001";
when "0111100100000000" => dout <= "001";
when "1110001100000000" => dout <= "001";
when "1110001000000000" => dout <= "001";
when "1110000100000000" => dout <= "001";
when "1110000000000000" => dout <= "001";
when "1100110100000000" => dout <= "101";
when "1100110000000000" => dout <= "110";
when "1100111000000000" => dout <= "111";
when "1100111100000000" => dout <= "000";
when "1111100000000000" => dout <= "000";
when "1111010100000000" => dout <= "000";
when "1111100100000000" => dout <= "000";
when "1111110000000000" => dout <= "000";
when "1111110100000000" => dout <= "000";
when "1111101000000000" => dout <= "000";
when "1111101100000000" => dout <= "000";
when "1111010000000000" => dout <= "000";
when "1001101100000000" => dout <= "000";
when "1111000000000000" => dout <= "000";
when "1001000000000000" => dout <= "000";
when "0010011000000000" => dout <= "000";
when "0010111000000000" => dout <= "000";
when "0011011000000000" => dout <= "000";
when "0011111000000000" => dout <= "000";
when "1000100011000000" => dout <= "000";
when "1000100000000000" => dout <= "000";
when "1000100001000000" => dout <= "011";
when "1000100010000000" => dout <= "100";
when "1000100000000110" => dout <= "100";
when "1000100111000000" => dout <= "000";
when "1000100100000000" => dout <= "000";
when "1000100101000000" => dout <= "011";
when "1000100110000000" => dout <= "100";
when "1000100100000110" => dout <= "100";
when "1000101011000000" => dout <= "000";
when "1000101000000000" => dout <= "000";
when "1000101001000000" => dout <= "011";
when "1000101010000000" => dout <= "100";
when "1000101000000110" => dout <= "100";
when "1000101111000000" => dout <= "000";
when "1000101100000000" => dout <= "000";
when "1000101101000000" => dout <= "011";
when "1000101110000000" => dout <= "100";
when "1000101100000110" => dout <= "100";
when "1100011000000000" => dout <= "000";
when "1100011001000000" => dout <= "011";
when "1100011010000000" => dout <= "100";
when "1100011000000110" => dout <= "100";
when "1100011100000000" => dout <= "000";
when "1100011101000000" => dout <= "011";
when "1100011110000000" => dout <= "100";
when "1100011100000110" => dout <= "100";
when "1011000000000000" => dout <= "000";
when "1011000100000000" => dout <= "000";
when "1011001000000000" => dout <= "000";
when "1011001100000000" => dout <= "000";
when "1011010000000000" => dout <= "000";
when "1011010100000000" => dout <= "000";
when "1011011000000000" => dout <= "000";
when "1011011100000000" => dout <= "000";
when "1011100000000000" => dout <= "000";
when "1011100100000000" => dout <= "000";
when "1011101000000000" => dout <= "000";
when "1011101100000000" => dout <= "000";
when "1011110000000000" => dout <= "000";
when "1011110100000000" => dout <= "000";
when "1011111000000000" => dout <= "000";
when "1011111100000000" => dout <= "000";
when "1010000000000000" => dout <= "010";
when "1010000100000000" => dout <= "010";
when "1010001000000000" => dout <= "010";
when "1010001100000000" => dout <= "010";
when "1000111011000000" => dout <= "000";
when "1000111000000000" => dout <= "000";
when "1000111001000000" => dout <= "011";
when "1000111010000000" => dout <= "100";
when "1000111000000110" => dout <= "100";
when "1000110011000000" => dout <= "000";
when "1000110000000000" => dout <= "000";
when "1000110001000000" => dout <= "011";
when "1000110010000000" => dout <= "100";
when "1000110000000110" => dout <= "100";
when "1111111100110000" => dout <= "000";
when "1111111101110000" => dout <= "011";
when "1111111110110000" => dout <= "100";
when "1111111100110110" => dout <= "100";
when "0101000000000000" => dout <= "000";
when "0101000100000000" => dout <= "000";
when "0101001000000000" => dout <= "000";
when "0101001100000000" => dout <= "000";
when "0101010000000000" => dout <= "000";
when "0101010100000000" => dout <= "000";
when "0101011000000000" => dout <= "000";
when "0101011100000000" => dout <= "000";
when "0000011000000000" => dout <= "000";
when "0000111000000000" => dout <= "000";
when "0001011000000000" => dout <= "000";
when "0001111000000000" => dout <= "000";
when "1000111100000000" => dout <= "000";
when "1000111101000000" => dout <= "011";
when "1000111110000000" => dout <= "100";
when "1000111100000110" => dout <= "100";
when "1000111111000000" => dout <= "000";
when "0101100000000000" => dout <= "000";
when "0101100100000000" => dout <= "000";
when "0101101000000000" => dout <= "000";
when "0101101100000000" => dout <= "000";
when "0101110000000000" => dout <= "000";
when "0101110100000000" => dout <= "000";
when "0101111000000000" => dout <= "000";
when "0101111100000000" => dout <= "000";
when "0000011100000000" => dout <= "000";
when "0001011100000000" => dout <= "000";
when "0001111100000000" => dout <= "000";
when "1000011011000000" => dout <= "000";
when "1000011000000000" => dout <= "000";
when "1000011001000000" => dout <= "011";
when "1000011010000000" => dout <= "100";
when "1000011000000110" => dout <= "100";
when "1000011111000000" => dout <= "000";
when "1000011100000000" => dout <= "000";
when "1000011101000000" => dout <= "011";
when "1000011110000000" => dout <= "100";
when "1000011100000110" => dout <= "100";
when "1001000100000000" => dout <= "000";
when "1001001000000000" => dout <= "000";
when "1001001100000000" => dout <= "000";
when "1001010000000000" => dout <= "000";
when "1001010100000000" => dout <= "000";
when "1001011000000000" => dout <= "000";
when "1001011100000000" => dout <= "000";
when "1110010000000000" => dout <= "101";
when "1110010100000000" => dout <= "101";
when "1110110000000000" => dout <= "000";
when "1110110100000000" => dout <= "000";
when "1110011000000000" => dout <= "101";
when "1110011100000000" => dout <= "101";
when "1110111100000000" => dout <= "000";
when "1110111000000000" => dout <= "000";
when "1101011100000000" => dout <= "000";
when "1001111100000000" => dout <= "000";
when "1001111000000000" => dout <= "000";
when "1001110000000000" => dout <= "000";
when "1001110100000000" => dout <= "000";
when "1000110100000110" => dout <= "100";
when "1000110111000000" => dout <= "000";
when "1000110100000000" => dout <= "000";
when "1000110101000000" => dout <= "011";
when "1000110110000000" => dout <= "100";
when "1100010100000110" => dout <= "100";
when "1100010100000000" => dout <= "000";
when "1100010101000000" => dout <= "011";
when "1100010110000000" => dout <= "100";
when "1100010000000110" => dout <= "100";
when "1100010000000000" => dout <= "000";
when "1100010001000000" => dout <= "011";
when "1100010010000000" => dout <= "100";
when "0000000011000000" => dout <= "000";
when "0000000000000110" => dout <= "100";
when "0000000000000000" => dout <= "000";
when "0000000001000000" => dout <= "011";
when "0000000010000000" => dout <= "100";
when "0000000111000000" => dout <= "000";
when "0000000100000110" => dout <= "100";
when "0000000100000000" => dout <= "000";
when "0000000101000000" => dout <= "011";
when "0000000110000000" => dout <= "100";
when "0000001011000000" => dout <= "000";
when "0000001000000110" => dout <= "100";
when "0000001000000000" => dout <= "000";
when "0000001001000000" => dout <= "011";
when "0000001010000000" => dout <= "100";
when "0000001111000000" => dout <= "000";
when "0000001100000110" => dout <= "100";
when "0000001100000000" => dout <= "000";
when "0000001101000000" => dout <= "011";
when "0000001110000000" => dout <= "100";
when "1000000011000000" => dout <= "000";
when "1000000000000110" => dout <= "100";
when "1000000000000000" => dout <= "000";
when "1000000001000000" => dout <= "011";
when "1000000010000000" => dout <= "100";
when "1000000111000000" => dout <= "000";
when "1000000100000110" => dout <= "100";
when "1000000100000000" => dout <= "000";
when "1000000101000000" => dout <= "011";
when "1000000110000000" => dout <= "100";
when "1000001111000000" => dout <= "000";
when "1000001100000110" => dout <= "100";
when "1000001100000000" => dout <= "000";
when "1000001101000000" => dout <= "011";
when "1000001110000000" => dout <= "100";
when "0000010000000000" => dout <= "000";
when "0000010100000000" => dout <= "000";
when "0001000011000000" => dout <= "000";
when "0001000000000110" => dout <= "100";
when "0001000000000000" => dout <= "000";
when "0001000001000000" => dout <= "011";
when "0001000010000000" => dout <= "100";
when "0001000111000000" => dout <= "000";
when "0001000100000110" => dout <= "100";
when "0001000100000000" => dout <= "000";
when "0001000101000000" => dout <= "011";
when "0001000110000000" => dout <= "100";
when "0001001011000000" => dout <= "000";
when "0001001000000110" => dout <= "100";
when "0001001000000000" => dout <= "000";
when "0001001001000000" => dout <= "011";
when "0001001010000000" => dout <= "100";
when "0001001111000000" => dout <= "000";
when "0001001100000110" => dout <= "100";
when "0001001100000000" => dout <= "000";
when "0001001101000000" => dout <= "011";
when "0001001110000000" => dout <= "100";
when "1000000011010000" => dout <= "000";
when "1000000000010110" => dout <= "100";
when "1000000000010000" => dout <= "000";
when "1000000001010000" => dout <= "011";
when "1000000010010000" => dout <= "100";
when "1000000111010000" => dout <= "000";
when "1000000100010110" => dout <= "100";
when "1000000100010000" => dout <= "000";
when "1000000101010000" => dout <= "011";
when "1000000110010000" => dout <= "100";
when "1000001111010000" => dout <= "000";
when "1000001100010110" => dout <= "100";
when "1000001100010000" => dout <= "000";
when "1000001101010000" => dout <= "011";
when "1000001110010000" => dout <= "100";
when "0001010000000000" => dout <= "000";
when "0001010100000000" => dout <= "000";
when "0010100011000000" => dout <= "000";
when "0010100000000110" => dout <= "100";
when "0010100000000000" => dout <= "000";
when "0010100001000000" => dout <= "011";
when "0010100010000000" => dout <= "100";
when "0010100111000000" => dout <= "000";
when "0010100100000110" => dout <= "100";
when "0010100100000000" => dout <= "000";
when "0010100101000000" => dout <= "011";
when "0010100110000000" => dout <= "100";
when "0010101011000000" => dout <= "000";
when "0010101000000110" => dout <= "100";
when "0010101000000000" => dout <= "000";
when "0010101001000000" => dout <= "011";
when "0010101010000000" => dout <= "100";
when "0010101111000000" => dout <= "000";
when "0010101100000110" => dout <= "100";
when "0010101100000000" => dout <= "000";
when "0010101101000000" => dout <= "011";
when "0010101110000000" => dout <= "100";
when "1000000011101000" => dout <= "000";
when "1000000000101110" => dout <= "100";
when "1000000000101000" => dout <= "000";
when "1000000001101000" => dout <= "011";
when "1000000010101000" => dout <= "100";
when "1000000111101000" => dout <= "000";
when "1000000100101110" => dout <= "100";
when "1000000100101000" => dout <= "000";
when "1000000101101000" => dout <= "011";
when "1000000110101000" => dout <= "100";
when "1000001111101000" => dout <= "000";
when "1000001100101110" => dout <= "100";
when "1000001100101000" => dout <= "000";
when "1000001101101000" => dout <= "011";
when "1000001110101000" => dout <= "100";
when "0010110000000000" => dout <= "000";
when "0010110100000000" => dout <= "000";
when "0001100011000000" => dout <= "000";
when "0001100000000110" => dout <= "100";
when "0001100000000000" => dout <= "000";
when "0001100001000000" => dout <= "011";
when "0001100010000000" => dout <= "100";
when "0001100111000000" => dout <= "000";
when "0001100100000110" => dout <= "100";
when "0001100100000000" => dout <= "000";
when "0001100101000000" => dout <= "011";
when "0001100110000000" => dout <= "100";
when "0001101011000000" => dout <= "000";
when "0001101000000110" => dout <= "100";
when "0001101000000000" => dout <= "000";
when "0001101001000000" => dout <= "011";
when "0001101010000000" => dout <= "100";
when "0001101111000000" => dout <= "000";
when "0001101100000110" => dout <= "100";
when "0001101100000000" => dout <= "000";
when "0001101101000000" => dout <= "011";
when "0001101110000000" => dout <= "100";
when "1000000011011000" => dout <= "000";
when "1000000000011110" => dout <= "100";
when "1000000000011000" => dout <= "000";
when "1000000001011000" => dout <= "011";
when "1000000010011000" => dout <= "100";
when "1000000111011000" => dout <= "000";
when "1000000100011110" => dout <= "100";
when "1000000100011000" => dout <= "000";
when "1000000101011000" => dout <= "011";
when "1000000110011000" => dout <= "100";
when "1000001111011000" => dout <= "000";
when "1000001100011110" => dout <= "100";
when "1000001100011000" => dout <= "000";
when "1000001101011000" => dout <= "011";
when "1000001110011000" => dout <= "100";
when "0001110000000000" => dout <= "000";
when "0001110100000000" => dout <= "000";
when "1111111011000000" => dout <= "000";
when "1111111000000110" => dout <= "100";
when "1111111000000000" => dout <= "000";
when "1111111001000000" => dout <= "011";
when "1111111010000000" => dout <= "100";
when "1111111100000110" => dout <= "100";
when "1111111100000000" => dout <= "000";
when "1111111101000000" => dout <= "011";
when "1111111110000000" => dout <= "100";
when "0100000000000000" => dout <= "000";
when "0100000100000000" => dout <= "000";
when "0100001000000000" => dout <= "000";
when "0100001100000000" => dout <= "000";
when "0100010000000000" => dout <= "000";
when "0100010100000000" => dout <= "000";
when "0100011000000000" => dout <= "000";
when "0100011100000000" => dout <= "000";
when "1111111011001000" => dout <= "000";
when "1111111000001110" => dout <= "100";
when "1111111000001000" => dout <= "000";
when "1111111001001000" => dout <= "011";
when "1111111010001000" => dout <= "100";
when "1111111100001110" => dout <= "100";
when "1111111100001000" => dout <= "000";
when "1111111101001000" => dout <= "011";
when "1111111110001000" => dout <= "100";
when "0100100000000000" => dout <= "000";
when "0100100100000000" => dout <= "000";
when "0100101000000000" => dout <= "000";
when "0100101100000000" => dout <= "000";
when "0100110000000000" => dout <= "000";
when "0100110100000000" => dout <= "000";
when "0100111000000000" => dout <= "000";
when "0100111100000000" => dout <= "000";
when "0011101011000000" => dout <= "000";
when "0011101000000110" => dout <= "100";
when "0011101000000000" => dout <= "000";
when "0011101001000000" => dout <= "011";
when "0011101010000000" => dout <= "100";
when "0011101111000000" => dout <= "000";
when "0011101100000110" => dout <= "100";
when "0011101100000000" => dout <= "000";
when "0011101101000000" => dout <= "011";
when "0011101110000000" => dout <= "100";
when "0011100000000110" => dout <= "100";
when "0011100000000000" => dout <= "000";
when "0011100001000000" => dout <= "011";
when "0011100010000000" => dout <= "100";
when "0011100011000000" => dout <= "000";
when "0011100100000110" => dout <= "100";
when "0011100100000000" => dout <= "000";
when "0011100101000000" => dout <= "011";
when "0011100110000000" => dout <= "100";
when "0011100111000000" => dout <= "000";
when "1000000011111000" => dout <= "000";
when "1000000000111110" => dout <= "100";
when "1000000000111000" => dout <= "000";
when "1000000001111000" => dout <= "011";
when "1000000010111000" => dout <= "100";
when "1000000111111000" => dout <= "000";
when "1000000100111110" => dout <= "100";
when "1000000100111000" => dout <= "000";
when "1000000101111000" => dout <= "011";
when "1000000110111000" => dout <= "100";
when "1000001111111000" => dout <= "000";
when "1000001100111110" => dout <= "100";
when "1000001100111000" => dout <= "000";
when "1000001101111000" => dout <= "011";
when "1000001110111000" => dout <= "100";
when "0011110000000000" => dout <= "000";
when "0011110100000000" => dout <= "000";
when "1111011011011000" => dout <= "000";
when "1111011000011110" => dout <= "100";
when "1111011000011000" => dout <= "000";
when "1111011001011000" => dout <= "011";
when "1111011010011000" => dout <= "100";
when "1111011111011000" => dout <= "000";
when "1111011100011110" => dout <= "100";
when "1111011100011000" => dout <= "000";
when "1111011101011000" => dout <= "011";
when "1111011110011000" => dout <= "100";
when "0011011100000000" => dout <= "001";
when "0010011100000000" => dout <= "001";
when "0011111100000000" => dout <= "001";
when "0010111100000000" => dout <= "001";
when "1111011011100000" => dout <= "000";
when "1111011000100110" => dout <= "100";
when "1111011000100000" => dout <= "000";
when "1111011001100000" => dout <= "011";
when "1111011010100000" => dout <= "100";
when "1111011111100000" => dout <= "000";
when "1111011100100110" => dout <= "100";
when "1111011100100000" => dout <= "000";
when "1111011101100000" => dout <= "011";
when "1111011110100000" => dout <= "100";
when "1111011011101000" => dout <= "000";
when "1111011000101110" => dout <= "100";
when "1111011000101000" => dout <= "000";
when "1111011001101000" => dout <= "011";
when "1111011010101000" => dout <= "100";
when "1111011111101000" => dout <= "000";
when "1111011100101110" => dout <= "100";
when "1111011100101000" => dout <= "000";
when "1111011101101000" => dout <= "011";
when "1111011110101000" => dout <= "100";
when "1111011011110000" => dout <= "000";
when "1111011000110110" => dout <= "100";
when "1111011000110000" => dout <= "000";
when "1111011001110000" => dout <= "011";
when "1111011010110000" => dout <= "100";
when "1111011111110000" => dout <= "000";
when "1111011100110110" => dout <= "100";
when "1111011100110000" => dout <= "000";
when "1111011101110000" => dout <= "011";
when "1111011110110000" => dout <= "100";
when "1111011011111000" => dout <= "000";
when "1111011000111110" => dout <= "100";
when "1111011000111000" => dout <= "000";
when "1111011001111000" => dout <= "011";
when "1111011010111000" => dout <= "100";
when "1111011111111000" => dout <= "000";
when "1111011100111110" => dout <= "100";
when "1111011100111000" => dout <= "000";
when "1111011101111000" => dout <= "011";
when "1111011110111000" => dout <= "100";
when "1101010000000000" => dout <= "000";
when "1101010100000000" => dout <= "000";
when "1001100000000000" => dout <= "000";
when "1001100100000000" => dout <= "000";
when "1101000011000000" => dout <= "000";
when "1101000000000110" => dout <= "100";
when "1101000000000000" => dout <= "000";
when "1101000001000000" => dout <= "011";
when "1101000010000000" => dout <= "100";
when "1101000111000000" => dout <= "000";
when "1101000100000110" => dout <= "100";
when "1101000100000000" => dout <= "000";
when "1101000101000000" => dout <= "011";
when "1101000110000000" => dout <= "100";
when "1101001011000000" => dout <= "000";
when "1101001000000110" => dout <= "100";
when "1101001000000000" => dout <= "000";
when "1101001001000000" => dout <= "011";
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when "1101001111000000" => dout <= "000";
when "1101001100000110" => dout <= "100";
when "1101001100000000" => dout <= "000";
when "1101001101000000" => dout <= "011";
when "1101001110000000" => dout <= "100";
when "0010000011000000" => dout <= "000";
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when "0010000000000000" => dout <= "000";
when "0010000001000000" => dout <= "011";
when "0010000010000000" => dout <= "100";
when "0010000111000000" => dout <= "000";
when "0010000100000110" => dout <= "100";
when "0010000100000000" => dout <= "000";
when "0010000101000000" => dout <= "011";
when "0010000110000000" => dout <= "100";
when "0010001011000000" => dout <= "000";
when "0010001000000110" => dout <= "100";
when "0010001000000000" => dout <= "000";
when "0010001001000000" => dout <= "011";
when "0010001010000000" => dout <= "100";
when "0010001111000000" => dout <= "000";
when "0010001100000110" => dout <= "100";
when "0010001100000000" => dout <= "000";
when "0010001101000000" => dout <= "011";
when "0010001110000000" => dout <= "100";
when "1000000011100000" => dout <= "000";
when "1000000000100110" => dout <= "100";
when "1000000000100000" => dout <= "000";
when "1000000001100000" => dout <= "011";
when "1000000010100000" => dout <= "100";
when "1000000111100000" => dout <= "000";
when "1000000100100110" => dout <= "100";
when "1000000100100000" => dout <= "000";
when "1000000101100000" => dout <= "011";
when "1000000110100000" => dout <= "100";
when "1000001111100000" => dout <= "000";
when "1000001100100110" => dout <= "100";
when "1000001100100000" => dout <= "000";
when "1000001101100000" => dout <= "011";
when "1000001110100000" => dout <= "100";
when "0010010000000000" => dout <= "000";
when "0010010100000000" => dout <= "000";
when "0000100000000110" => dout <= "100";
when "0000100000000000" => dout <= "000";
when "0000100001000000" => dout <= "011";
when "0000100010000000" => dout <= "100";
when "0000100011000000" => dout <= "000";
when "0000100100000110" => dout <= "100";
when "0000100100000000" => dout <= "000";
when "0000100101000000" => dout <= "011";
when "0000100110000000" => dout <= "100";
when "0000100111000000" => dout <= "000";
when "0000101011000000" => dout <= "000";
when "0000101000000110" => dout <= "100";
when "0000101000000000" => dout <= "000";
when "0000101001000000" => dout <= "011";
when "0000101010000000" => dout <= "100";
when "0000101111000000" => dout <= "000";
when "0000101100000110" => dout <= "100";
when "0000101100000000" => dout <= "000";
when "0000101101000000" => dout <= "011";
when "0000101110000000" => dout <= "100";
when "1000000011001000" => dout <= "000";
when "1000000000001110" => dout <= "100";
when "1000000000001000" => dout <= "000";
when "1000000001001000" => dout <= "011";
when "1000000010001000" => dout <= "100";
when "1000000111001000" => dout <= "000";
when "1000000100001110" => dout <= "100";
when "1000000100001000" => dout <= "000";
when "1000000101001000" => dout <= "011";
when "1000000110001000" => dout <= "100";
when "1000001111001000" => dout <= "000";
when "1000001100001110" => dout <= "100";
when "1000001100001000" => dout <= "000";
when "1000001101001000" => dout <= "011";
when "1000001110001000" => dout <= "100";
when "0000110000000000" => dout <= "000";
when "0000110100000000" => dout <= "000";
when "1000010000000110" => dout <= "100";
when "1000010000000000" => dout <= "000";
when "1000010001000000" => dout <= "011";
when "1000010010000000" => dout <= "100";
when "1000010100000110" => dout <= "100";
when "1000010100000000" => dout <= "000";
when "1000010101000000" => dout <= "011";
when "1000010110000000" => dout <= "100";
when "1000010011000000" => dout <= "000";
when "1000010111000000" => dout <= "000";
when "1111011011000000" => dout <= "000";
when "1111011000000110" => dout <= "100";
when "1111011000000000" => dout <= "000";
when "1111011001000000" => dout <= "011";
when "1111011010000000" => dout <= "100";
when "1111011111000000" => dout <= "000";
when "1111011100000110" => dout <= "100";
when "1111011100000000" => dout <= "000";
when "1111011101000000" => dout <= "011";
when "1111011110000000" => dout <= "100";
when "1010100000000000" => dout <= "000";
when "1010100100000000" => dout <= "000";
when "0011000000000110" => dout <= "100";
when "0011000000000000" => dout <= "000";
when "0011000001000000" => dout <= "011";
when "0011000010000000" => dout <= "100";
when "0011000011000000" => dout <= "000";
when "0011000100000110" => dout <= "100";
when "0011000100000000" => dout <= "000";
when "0011000101000000" => dout <= "011";
when "0011000110000000" => dout <= "100";
when "0011000111000000" => dout <= "000";
when "0011001011000000" => dout <= "000";
when "0011001000000110" => dout <= "100";
when "0011001000000000" => dout <= "000";
when "0011001001000000" => dout <= "011";
when "0011001010000000" => dout <= "100";
when "0011001111000000" => dout <= "000";
when "0011001100000110" => dout <= "100";
when "0011001100000000" => dout <= "000";
when "0011001101000000" => dout <= "011";
when "0011001110000000" => dout <= "100";
when "1000000011110000" => dout <= "000";
when "1000000000110110" => dout <= "100";
when "1000000000110000" => dout <= "000";
when "1000000001110000" => dout <= "011";
when "1000000010110000" => dout <= "100";
when "1000000111110000" => dout <= "000";
when "1000000100110110" => dout <= "100";
when "1000000100110000" => dout <= "000";
when "1000000101110000" => dout <= "011";
when "1000000110110000" => dout <= "100";
when "1000001111110000" => dout <= "000";
when "1000001100110110" => dout <= "100";
when "1000001100110000" => dout <= "000";
when "1000001101110000" => dout <= "011";
when "1000001110110000" => dout <= "100";
when "0011010000000000" => dout <= "000";
when "0011010100000000" => dout <= "000";
when "1111011011010000" => dout <= "000";
when "1111011000010110" => dout <= "100";
when "1111011000010000" => dout <= "000";
when "1111011001010000" => dout <= "011";
when "1111011010010000" => dout <= "100";
when "1111011111010000" => dout <= "000";
when "1111011100010110" => dout <= "100";
when "1111011100010000" => dout <= "000";
when "1111011101010000" => dout <= "011";
when "1111011110010000" => dout <= "100";
when "1010010000000000" => dout <= "000";
when "1010010100000000" => dout <= "000";
when "1010011000000000" => dout <= "000";
when "1010011100000000" => dout <= "000";
when "1010111000000000" => dout <= "000";
when "1010111100000000" => dout <= "000";
when "1010110000000000" => dout <= "000";
when "1010110100000000" => dout <= "000";
when "1010101000000000" => dout <= "000";
when "1010101100000000" => dout <= "000";
when "1111001000000000" => dout <= "000";
when "1111001100000000" => dout <= "000";
when "0110000000000000" => dout <= "000";
when "0110000100000000" => dout <= "000";
when "1100100000000000" => dout <= "000";
when "1100100100000000" => dout <= "000";
when "0110001000000000" => dout <= "000";
when "0110110000000000" => dout <= "000";
when "0110110100000000" => dout <= "000";
when "0110111000000000" => dout <= "000";
when "0110111100000000" => dout <= "000";
when "0000111100000000" => dout <= "000";
when "0110001100000000" => dout <= "000";
when "0110010000000000" => dout <= "000";
when "0110010100000000" => dout <= "000";
when "0110011000000000" => dout <= "000";
when "0110011100000000" => dout <= "000";
when "1000001000000000" => dout <= "000";
when "1101011000000000" => dout <= "000";
when "1111000100000000" => dout <= "000";
when "1100000000000000" => dout <= "000";
when "1100000100000000" => dout <= "000";
when others => dout <= "---";
end case;
end process;
end rtl; |
-- Reduced test case, bug originally found in 4DSP's fmc110_ctrl.vhd
library ieee;
use ieee.std_logic_1164.all;
entity bug3 is
port (
clk1_i : in std_logic;
clk1_ib : in std_logic;
clk1_o : out std_logic
);
end bug3;
architecture bug3_syn of bug3 is
component IBUFDS generic (
DIFF_TERM : boolean := FALSE
); port(
O : out std_logic;
I : in std_logic;
IB : in std_logic
); end component;
begin
ibufds1 : ibufds
generic map (
DIFF_TERM => TRUE -- change to "1" and vhdlpp is happy
)
port map (
i => clk1_i,
ib => clk1_ib,
o => clk1_o
);
end bug3_syn;
entity ibufds is
generic (
DIFF_TERM : boolean := FALSE
);
port (
i : in std_logic;
ib : in std_logic;
o : out std_logic
);
end ibufds;
architecture ibufds_sim of ibufds is
begin
o <= i;
end ibufds_sim;
|
-- Reduced test case, bug originally found in 4DSP's fmc110_ctrl.vhd
library ieee;
use ieee.std_logic_1164.all;
entity bug3 is
port (
clk1_i : in std_logic;
clk1_ib : in std_logic;
clk1_o : out std_logic
);
end bug3;
architecture bug3_syn of bug3 is
component IBUFDS generic (
DIFF_TERM : boolean := FALSE
); port(
O : out std_logic;
I : in std_logic;
IB : in std_logic
); end component;
begin
ibufds1 : ibufds
generic map (
DIFF_TERM => TRUE -- change to "1" and vhdlpp is happy
)
port map (
i => clk1_i,
ib => clk1_ib,
o => clk1_o
);
end bug3_syn;
entity ibufds is
generic (
DIFF_TERM : boolean := FALSE
);
port (
i : in std_logic;
ib : in std_logic;
o : out std_logic
);
end ibufds;
architecture ibufds_sim of ibufds is
begin
o <= i;
end ibufds_sim;
|
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