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library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity shr_141 is
port (
output : out std_logic_vector(31 downto 0);
input : in std_logic_vector(31 downto 0);
shift : in std_logic_vector(5 downto 0);
padding : in std_logic
);
end shr_141;
architecture augh of shr_141 is
signal tmp_padding : std_logic;
signal tmp_result : std_logic_vector(32 downto 0);
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Temporary signals
tmp_padding <= padding;
tmp_result <= std_logic_vector(shift_right( unsigned(padding & input), to_integer(shift) ));
-- The output
output <= tmp_result(31 downto 0);
end architecture;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_04.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity counter is
port ( clk, reset : in bit; count : out natural );
end entity counter;
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
loop
wait until clk = '1' or reset = '1';
exit when reset = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
-- at this point, reset = '1'
count_value := 0;
count <= count_value;
wait until reset = '0';
end loop;
end process incrementer;
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_04.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity counter is
port ( clk, reset : in bit; count : out natural );
end entity counter;
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
loop
wait until clk = '1' or reset = '1';
exit when reset = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
-- at this point, reset = '1'
count_value := 0;
count <= count_value;
wait until reset = '0';
end loop;
end process incrementer;
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_fg_03_04.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity counter is
port ( clk, reset : in bit; count : out natural );
end entity counter;
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
loop
wait until clk = '1' or reset = '1';
exit when reset = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
-- at this point, reset = '1'
count_value := 0;
count <= count_value;
wait until reset = '0';
end loop;
end process incrementer;
end architecture behavior;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY MultBcd_1xN_TEST IS
END MultBcd_1xN_TEST;
ARCHITECTURE behavior OF MultBcd_1xN_TEST IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MultBcd_1xNDig
PORT(
A : IN unsigned(3 downto 0);
B : IN unsigned(19 downto 0);
Z : OUT unsigned(23 downto 0)
);
END COMPONENT;
--Inputs
signal A : unsigned(3 downto 0) := (others => '0');
signal B : unsigned(19 downto 0) := (others => '0');
--Outputs
signal Z : unsigned(23 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MultBcd_1xNDig PORT MAP (
A => A,
B => B,
Z => Z
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- Entrada 1 = 2
--------------------------------- MSB
-- a(19 downto 16) <= "0000";
-- a(15 downto 12) <= "0010";
-- a(11 downto 8) <= "0000";
-- a(7 downto 4) <= "0000";
a(3 downto 0) <= "0101";
--------------------------------- LSB
-- Entrada 2 = 11.111
--------------------------------- MSB
B(19 downto 16) <= "0000";
B(15 downto 12) <= "0000";
B(11 downto 8) <= "0000";
B(7 downto 4) <= "0001";
B(3 downto 0) <= "0101";
--------------------------------- LSB
wait;
end process;
END;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
use work.procedures.all;
entity tb_mp_indirect_fetch is
end tb_mp_indirect_fetch;
architecture behav of tb_mp_indirect_fetch is
signal rst : std_logic := '1';
signal clk : std_logic := '0';
signal start : std_logic := '0';
signal cmd_in : t_vliw := empty_vliw;
signal arg_in : t_data_array(4 downto 0) := (others => (others => '0'));
signal mem_addr : std_logic_vector(9 downto 0) := (others => '0');
signal mem_rd : std_logic := '0';
signal mem_data : t_data := (others => '0');
signal arg_out : t_data_array(4 downto 0) := (others => (others => '0'));
signal val_out : t_data_array(4 downto 0) := (others => (others => '0'));
signal cmd_out : t_vliw := empty_vliw;
signal busy : std_logic := '0';
signal finished : std_logic := '0';
begin
clock: process
begin
clk <= '0', '1' after 10 ns;
wait for 20 ns;
end process clock;
process(clk)
variable i : unsigned(7 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if rst = '1' then
i := (others => '0');
else
i := i + 1;
mem_data <= std_logic_vector(i);
end if;
end if;
end process;
process
variable l : line;
begin
wait for 10 ns;
wait for 40 ns;
rst <= '0';
cmd_in.last_val <= '0';
cmd_in.arg_assign <= (0 => "000", 1 => "001", 2 => "010", 3 => "011", 4 => "100");
cmd_in.mem_fetch <= (others => '0');
cmd_in.mem_memchunk <= (others => "00");
arg_in <= ( X"01", X"02", X"03", X"04", X"05");
start <= '1';
wait for 20 ns;
start <= '0';
wait for 40 ns;
arg_in <= ( X"02", X"03", X"04", X"05", X"06");
start <= '1';
wait for 20 ns;
arg_in <= ( X"03", X"04", X"05", X"06", X"07");
wait for 20 ns;
start <= '0';
wait for 80 ns;
cmd_in.last_val <= '0';
cmd_in.arg_assign <= (0 => "000", 1 => "001", 2 => "010", 3 => "011", 4 => "100");
cmd_in.mem_fetch <= (others => '1');
cmd_in.mem_memchunk <= (0 => "00", 1 => "01", 2 => "10", 3 => "11", 4 => "00");
arg_in <= ( X"01", X"02", X"03", X"04", X"05");
start <= '1';
wait for 20 ns;
start <= '0';
wait for 160 ns;
cmd_in.last_val <= '1';
cmd_in.arg_assign <= (0 => "000", 1 => "001", 2 => "010", 3 => "011", 4 => "100");
cmd_in.mem_fetch <= (others => '0');
cmd_in.mem_memchunk <= (others => "00");
arg_in <= ( X"01", X"02", X"03", X"04", X"05");
start <= '1';
wait for 20 ns;
start <= '0';
wait for 160 ns;
cmd_in.last_val <= '0';
cmd_in.arg_assign <= (3 => "000", 0 => "001", 2 => "010", 1 => "011", 4 => "100");
cmd_in.mem_fetch <= (0 => '1', 1 => '1', others => '0');
cmd_in.mem_memchunk <= (0 => "00", 1 => "01", others => "00");
arg_in <= ( X"01", X"02", X"03", X"04", X"05");
start <= '1';
wait for 20 ns;
start <= '0';
wait for 160 ns;
assert false report "stop" severity failure;
end process;
mp_indirect_fetch_i: entity work.mp_indirect_fetch
port map(
rst => rst,
clk => clk,
start => start,
cmd_in => cmd_in,
arg_in => arg_in,
mem_addr => mem_addr,
mem_rd => mem_rd,
mem_data => mem_data,
arg_out => arg_out,
val_out => val_out,
cmd_out => cmd_out,
busy => busy,
finished => finished
);
end behav;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr1spax_ddr
-- File: ddr1spax_ddr.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Merged 16/32/64-bit DDR/mobile-DDR backend
-- Based on ddrsp*a and ddr2spax_ddr
--------------------------------------------------------------------------------
-- Added features from the original ddrspa:
-- * Separated AHB,DDR parts of controller like for DDR2SPA
-- * 64/32/16 bit interfaces in the same entity
-- * Checkbit support for use with ft_ddr2spax_ahb front-end.
-- * Extended timing fields plus tRAS setting to meet DDR400 timing.
-- * Configurable burst length
-- * Support for PHY:s with read data valid signaling and extra latency
-- Incompatibility/differences to the original ddrspa:
-- * The mobile DDR had an undocumented feature that tRFC was extended with 8
-- cycles if the TRP bit was set. This is replaced by the extended
-- timing fields.
-- * ddrsp16a used a separate read-clock supplied only from the Spartan PHY.
-- * Reads/writes are made as multiple length-2 burst commands.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ddr1spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
hasdqvalid : integer := 0;
readdly : integer := 0;
regoutput : integer := 1;
ddr400 : integer := 1;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end ddr1spax_ddr;
architecture rtl of ddr1spax_ddr is
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(ddrbits*2);
constant l2ddr_burstlen: integer := l2blen-l2ddrw;
-- constant oepols: std_logic := tosl(oepol);
-- Write buffer dimensions
-- Write buffer is addressable down to 32-bit level on write (AHB) side.
constant wbuf_rabits: integer := 1+l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant wbuf_rdbits: integer := 2*ddrbits;
-- Read buffer dimensions
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := 2*(ddrbits+chkbits);
type ddrstate is (dsidle,dsact1,dsact2,dsact3,dswr1,dswr2,dswr3,dswr4,dswr5,dswr6,
dsrd1,dsrd2,dsrd3,dsrd4,dsreg1,dsreg2,dscmd1,dscmd2,dspdown1,dspdown2,dsref1,
dssrr1,dssrr2);
type ddrinitstate is (disrstdel,disidle,disrun,disfinished);
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(4 downto 0);
trp : std_logic_vector(1 downto 0); -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
ds : std_logic_vector(5 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
mobileen : std_logic; -- Mobile SD support, Mobile SD enabled
txsr : std_logic_vector(5 downto 0); -- Exit Self Refresh timing
txp : std_logic_vector(1 downto 0); -- Exit Power-Down timing
tcke : std_logic; -- Clock enable timing
cl : std_logic; -- CAS latency 2/3 (0/1)
conf : std_logic_vector(63 downto 0); -- PHY control
tras : std_logic_vector(1 downto 0); -- tRAS minimum (6-9 cycles)
twr : std_logic; -- tWR write recovery, 2/3 cycles
end record;
type ddr_reg_type is record
s : ddrstate;
initstate : ddrinitstate;
cfg : sdram_cfg_type;
resp,resp2 : ddr_response_type;
req1,req2 : ddr_request_type;
start1,start2 : std_logic;
start3 : std_logic;
ramaddr : std_logic_vector(rbuf_wabits-1 downto 0);
readpipe : std_logic_vector(4+readdly downto 0);
initpos : std_logic_vector(2 downto 0);
cmdctr : std_logic_vector(7 downto 0);
readdone : std_logic;
refctr : std_logic_vector(17 downto 0);
refpend : std_logic;
idlectr : std_logic_vector(3 downto 0);
pdowns : std_logic_vector(1 downto 0);
sdo_casn : std_logic;
sdo_rasn : std_logic;
sdo_wen : std_logic;
sdo_csn : std_logic_vector(1 downto 0);
sdo_ba : std_logic_vector(1 downto 0);
sdo_address : std_logic_vector(14 downto 0);
sdo_data : std_logic_vector(2*ddrbits-1 downto 0);
sdo_dqm : std_logic_vector(ddrbits/4-1 downto 0);
sdo_cb : std_logic_vector(2*chkbits downto 0);
sdo_ck : std_logic_vector(2 downto 0);
sdo_bdrive : std_logic;
sdo_qdrive : std_logic;
end record;
signal dr,ndr: ddr_reg_type;
constant onev: std_logic_vector(15 downto 0) := x"FFFF";
constant zerov: std_logic_vector(15 downto 0) := x"0000";
signal arst : std_ulogic;
begin
arst <= testrst when (scantest/=0 and ddr_syncrst=0) and testen='1' else ddr_rst;
ddrcomb: process(ddr_rst,sdi,request,frequest,start_tog,dr,wbrdata,testen,testoen)
variable dv: ddr_reg_type;
variable o: ddrctrl_out_type;
variable rbw: std_logic;
variable rbwd: std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
variable vstart, vstartd, vdone, incdone: std_logic;
variable vrctr: std_logic_vector(3 downto 0);
variable vreq,vreqf: ddr_request_type;
variable regsd1 : std_logic_vector(31 downto 0);
variable regsd2 : std_logic_vector(31 downto 0);
variable regsd3 : std_logic_vector(31 downto 0);
variable lastreadcmd: std_logic;
variable lastwrite : std_logic;
variable vmaskfirst, vmasklast: std_logic_vector(ddrbits/4-1 downto 0);
variable ea: std_logic_vector(3 downto 2);
variable inc_sdoaddr, inc_ramaddr: std_logic;
variable datavalid: std_logic;
variable vcsf: std_logic_vector(1 downto 0);
variable vrowf: std_logic_vector(14 downto 0);
variable vbankf: std_logic_vector(1 downto 0);
variable vcol,vcoladdr: std_logic_vector(14 downto 1);
variable seqin,seqout: std_logic_vector(3 downto 0);
variable regrdata: std_logic_vector(2*ddrbits-1 downto 0);
variable regad: std_logic_vector(2 downto 0);
variable wrdreg1,wrdreg2,wrdreg3: std_logic_vector(31 downto 0);
variable reqselv: std_logic_vector(3 downto 0);
begin
---------------------------------------------------------------------------
-- Init vars
---------------------------------------------------------------------------
dv := dr;
o := ddrctrl_out_none;
o.bdrive := '1'; o.qdrive := '1';
vdone := dr.resp.done_tog or dr.resp2.done_tog;
vrctr := dr.resp.rctr_gray or dr.resp2.rctr_gray;
incdone := '0';
lastreadcmd := '0';
lastwrite := '0';
reqselv := reqsel & reqsel & reqsel & reqsel;
-- Config registers
regsd1 := (others => '0');
regsd1(31 downto 15) := dr.cfg.refon & dr.cfg.trp(0) & dr.cfg.trfc(2 downto 0) &
dr.cfg.trcd & dr.cfg.bsize & dr.cfg.csize & dr.cfg.command &
dr.cfg.dllrst & dr.cfg.renable & dr.cfg.cke;
regsd1(11 downto 0) := dr.cfg.refresh;
regsd2 := (others => '0');
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd2(14 downto 12) := conv_std_logic_vector(log2(ddrbits/8),3);
if mobile/=0 then regsd2(15):='1'; end if;-- Mobile DDR support
regsd2(19 downto 16) := conv_std_logic_vector(confapi, 4);
regsd3 := (others => '0');
regsd3(31) := dr.cfg.mobileen; -- Mobile DDR enable
regsd3(30) := dr.cfg.cl;
regsd3(24 downto 19) := dr.cfg.tcke & dr.cfg.txsr(3 downto 0) & dr.cfg.txp(0);
regsd3(18 downto 16) := dr.cfg.pmode;
regsd3( 7 downto 0) := dr.cfg.ds(2 downto 0) & dr.cfg.tcsr(1 downto 0)
& dr.cfg.pasr(2 downto 0);
-- Extended timing fields for DDR400
if ddr400 /= 0 then
regsd2(20) := '1'; -- Ext. fields available
regsd3(29 downto 28) := dr.cfg.tras;
regsd3(27 downto 26) := dr.cfg.txsr(5 downto 4);
regsd3(25) := dr.cfg.txp(1);
regsd3(11) := dr.cfg.twr;
regsd3(10) := dr.cfg.trp(1);
regsd3(9 downto 8) := dr.cfg.trfc(4 downto 3);
end if;
-- Data path
rbw := '0';
rbwd := (others => '0');
rbwd(ddrbits-1 downto 0) := sdi.data(ddrbits-1 downto 0);
rbwd(2*ddrbits+chkbits-1 downto ddrbits+chkbits) :=
sdi.data(2*ddrbits-1 downto ddrbits);
if chkbits > 0 then
rbwd(ddrbits+chkbits-1 downto ddrbits) := sdi.cb(chkbits-1 downto 0);
rbwd(2*(ddrbits+chkbits)-1 downto 2*ddrbits+chkbits) :=
sdi.cb(2*chkbits-1 downto chkbits);
end if;
dv.sdo_data(ddrbits-1 downto 0) := wbrdata(ddrbits-1 downto 0);
dv.sdo_data(2*ddrbits-1 downto ddrbits) :=
wbrdata(2*ddrbits+chkbits-1 downto ddrbits+chkbits);
dv.sdo_cb(chkbits) := '0'; -- dummy bit just to ensure length>0
if chkbits > 0 then
dv.sdo_cb(chkbits-1 downto 0) := wbrdata(ddrbits+chkbits-1 downto ddrbits);
dv.sdo_cb(2*chkbits-1 downto chkbits) :=
wbrdata(2*(ddrbits+chkbits)-1 downto 2*ddrbits+chkbits);
end if;
---------------------------------------------------------------------------
-- Request handling logic
---------------------------------------------------------------------------
-- Sync request inputs
dv.req1 := request;
dv.req2 := dr.req1;
dv.start1 := start_tog;
dv.start2 := dr.start1;
dv.start3 := dr.start2;
vstart := dr.start2;
vstartd := dr.start3;
vreq := dr.req2;
vreqf := dr.req1;
if nosync/=0 then
vstart:=start_tog;
vstartd:=start_tog;
vreq:=request;
vreqf:=request;
end if;
if nosync > 1 then
vreqf := frequest;
end if;
-- Address muxing
vcsf(0) := genmux(dr.cfg.bsize, vreqf.startaddr(30 downto 23));
vcsf(1) := not vcsf(0);
vbankf := genmux(dr.cfg.bsize, vreqf.startaddr(29 downto 22)) &
genmux(dr.cfg.bsize, vreqf.startaddr(28 downto 21));
case dr.cfg.csize is
when "00" => vrowf := vreqf.startaddr(19+l2ddrw downto 5+l2ddrw);
when "01" => vrowf := vreqf.startaddr(20+l2ddrw downto 6+l2ddrw);
when "10" => vrowf := vreqf.startaddr(21+l2ddrw downto 7+l2ddrw);
when others => vrowf := vreqf.startaddr(22+l2ddrw downto 8+l2ddrw);
end case;
vcol := vreq.startaddr(l2ddrw+10 downto l2ddrw-3);
-- vcoladdr==vcol when dr.ramaddr==lsb of vcol
vcoladdr := vcol(14 downto rbuf_wabits+1) & dr.ramaddr;
-- Generate data mask
-- Mask for 32-bit and larger bursts and single access
vmaskfirst := (others => '0');
vmasklast := (others => '0');
ea := vreq.endaddr(3 downto 2);
if vreq.hsize(1 downto 0)="11" then ea(2):='1'; end if;
if vreq.hsize(2)='1' then ea(3 downto 2):="11"; end if;
case ddrbits is
when 64 =>
-- 64-bit DDR width
case vreq.startaddr(3 downto 2) is
when "11" => vmaskfirst := "1111111111110000";
when "10" => vmaskfirst := "1111111100000000";
when "01" => vmaskfirst := "1111000000000000";
when others => vmaskfirst := "0000000000000000";
end case;
case ea(3 downto 2) is
when "11" => vmasklast := "0000000000000000";
when "10" => vmasklast := "0000000000001111";
when "01" => vmasklast := "0000000011111111";
when others => vmasklast := "0000111111111111";
end case;
if vreq.hsize(2 downto 1)="00" then
if vreq.startaddr(1)='1' then
vmaskfirst := vmaskfirst or "1100110011001100";
else
vmaskfirst := vmaskfirst or "0011001100110011";
end if;
end if;
if vreq.hsize="000" then
if vreq.startaddr(0)='1' then
vmaskfirst := vmaskfirst or "1010101010101010";
else
vmaskfirst := vmaskfirst or "0101010101010101";
end if;
end if;
when 32 =>
-- 32-bit DDR width
case vreq.startaddr(2) is
when '1' => vmaskfirst := "11110000";
when others => vmaskfirst := "00000000";
end case;
case ea(2) is
when '1' => vmasklast := "00000000";
when others => vmasklast := "00001111";
end case;
if vreq.hsize(2 downto 1)="00" then
if vreq.startaddr(1)='1' then
vmaskfirst := vmaskfirst or "11001100";
else
vmaskfirst := vmaskfirst or "00110011";
end if;
end if;
if vreq.hsize="000" then
if vreq.startaddr(0)='1' then
vmaskfirst := vmaskfirst or "10101010";
else
vmaskfirst := vmaskfirst or "01010101";
end if;
end if;
when others =>
-- 16-bit DDR width
if vreq.hsize(2 downto 1)="00" then
if vreq.startaddr(1)='1' then
vmaskfirst := vmaskfirst or "1100";
else
vmaskfirst := vmaskfirst or "0011";
end if;
end if;
if vreq.hsize="000" then
if vreq.startaddr(0)='1' then
vmaskfirst := vmaskfirst or "1010";
else
vmaskfirst := vmaskfirst or "0101";
end if;
end if;
end case;
-- Register read/write data muxing
regrdata := (others => '0');
case ddrbits is
when 64 =>
regad := vreq.startaddr(4 downto 2);
regrdata := regsd1 & regsd2 & regsd3 & x"00000000";
if confapi /= 0 and regad(2)='1' then
regrdata(95 downto 32) := dr.cfg.conf(31 downto 0) & dr.cfg.conf(63 downto 32);
end if;
wrdreg1 := wbrdata(128+chkbits-1 downto 96+chkbits);
wrdreg2 := wbrdata(96+chkbits-1 downto 64+chkbits);
wrdreg3 := wbrdata(63 downto 32);
when 32 =>
regad := dr.ramaddr(1 downto 0) & vreq.startaddr(2);
if regad(1)='0' then
regrdata := regsd1 & regsd2;
if confapi /= 0 and regad(2)='1' then
regrdata := regsd1 & dr.cfg.conf(31 downto 0);
end if;
else
regrdata := regsd3 & regsd2;
if confapi /= 0 and regad(2)='1' then
regrdata := dr.cfg.conf(63 downto 0);
end if;
end if;
wrdreg1 := wbrdata(64+chkbits-1 downto 32+chkbits);
wrdreg2 := wbrdata(31 downto 0);
wrdreg3 := wbrdata(64+chkbits-1 downto 32+chkbits);
when others =>
regad := dr.ramaddr(2 downto 0);
case regad is
when "000"|"100" => regrdata := regsd1;
when "001" => regrdata := regsd2;
when "010" => regrdata := regsd3;
when "101" =>
if confapi /= 0 then
regrdata := dr.cfg.conf(31 downto 0);
else
regrdata := regsd2;
end if;
when "110" =>
if confapi /= 0 then
regrdata := dr.cfg.conf(63 downto 32);
else
regrdata := regsd3;
end if;
when others => regrdata := regsd3;
end case;
wrdreg1 := wbrdata(31+chkbits downto 16+chkbits) & wbrdata(15 downto 0);
wrdreg2 := wbrdata(31+chkbits downto 16+chkbits) & wbrdata(15 downto 0);
wrdreg3 := wbrdata(31+chkbits downto 16+chkbits) & wbrdata(15 downto 0);
end case;
---------------------------------------------------------------------------
-- Main DDR-SDRAM access FSM
---------------------------------------------------------------------------
dv.sdo_ck := "111";
dv.sdo_rasn := '1';
dv.sdo_casn := '1';
dv.sdo_wen := '1';
dv.sdo_dqm := (others => '1');
dv.sdo_bdrive := '1';
dv.sdo_qdrive := '1';
inc_sdoaddr := '0';
inc_ramaddr := '0';
dv.readpipe := dr.readpipe(3+readdly downto 0) & '0';
datavalid := '0';
if hasdqvalid/=0 then
datavalid := sdi.datavalid;
if dr.s/=dsrd1 and dr.s/=dsrd2 and dr.s/=dsrd3 and dr.s/=dsrd4 and dr.s/=dssrr2 then
datavalid := '0';
end if;
end if;
if hasdqvalid=0 then
if dr.cfg.cl='0' then
datavalid := dr.readpipe(3+readdly);
else
datavalid := dr.readpipe(4+readdly);
end if;
end if;
if datavalid='1' and dr.s/=dsidle then
inc_ramaddr := '1';
rbw := '1';
vrctr(l2ddr_burstlen-1 downto 0) :=
nextgray(vrctr(l2ddr_burstlen-1 downto 0));
if dr.ramaddr=onev(dr.ramaddr'length-1 downto 0) then
dv.readdone := '1';
incdone:='1';
vrctr := "0000";
end if;
end if;
if dr.sdo_address((l2blen-l2ddrw) downto 1)=onev((l2blen-l2ddrw) downto 1) then
lastreadcmd := '1';
end if;
if dr.ramaddr=vreq.endaddr((l2blen-3)-1 downto (l2ddrw-3)) then
lastwrite := '1';
end if;
-- Update EMR when ds, tcsr or pasr change
if dr.cfg.command="000" and
( dr.cfg.ds(2 downto 0) /= dr.cfg.ds(5 downto 3) or
dr.cfg.tcsr(1 downto 0) /= dr.cfg.tcsr(3 downto 2) or
dr.cfg.pasr(2 downto 0) /= dr.cfg.pasr(5 downto 3) ) then
dv.cfg.command := "111";
end if;
-- Auto-refresh counter
dv.refctr := std_logic_vector(unsigned(dr.refctr)+1);
if (dr.refctr(11 downto 0)=dr.cfg.refresh and dr.cfg.refon='1') then
dv.refpend := '1';
dv.refctr := (others => '0');
end if;
if dr.initstate/=disrstdel and (dr.cfg.refon='0' or dr.cfg.pmode(1)='1') then
dv.refpend := '0';
dv.refctr := (others => '0');
end if;
dv.idlectr := "0000";
dv.pdowns(0) := '0';
if not (dr.cmdctr=(dr.cmdctr'range => '0')) and dr.pdowns(0)='0' then
dv.cmdctr := std_logic_vector(unsigned(dr.cmdctr)-1);
end if;
case dr.s is
when dsidle =>
vrctr := "0000";
dv.sdo_ck := "111";
if dr.cfg.pmode /= "000" then
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
end if;
dv.sdo_csn := "11";
if dr.refpend='1' then
dv.sdo_csn := "00";
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.s := dsref1;
dv.refpend := '0';
elsif vstart /= vdone and dr.cfg.renable='0' then
-- Transfer
dv.sdo_csn := vcsf;
dv.sdo_address := vrowf;
dv.sdo_ba := vbankf;
dv.sdo_rasn := '0' or vreqf.hio;
dv.s := dsact1;
elsif dr.cfg.command /= "000" then
dv.s := dscmd1;
elsif dr.idlectr="1111" then
dv.s := dspdown1;
end if;
when dsact1 =>
dv.ramaddr := vcol(rbuf_wabits downto 1);
if ddr400 /= 0 then
dv.cmdctr(2 downto 0) := "1" & dr.cfg.tras; -- t(RAS)-2t(CK) = TRAS+6-2 = TRAS+4
else
dv.cmdctr(2 downto 0) := "10" & dr.cfg.trcd;
end if;
dv.readdone := '0';
if dr.cfg.trcd='1' then
dv.s := dsact2;
else
dv.s := dsact3;
end if;
if vreq.hio='1' then
dv.s := dsreg1;
end if;
when dsact2 =>
dv.s := dsact3;
when dsact3 =>
dv.sdo_casn := '0';
dv.sdo_wen := not vreq.hwrite;
dv.sdo_qdrive := not vreq.hwrite;
-- dv.sdo_address := vcol(12 downto 10) & '0' & vcol(9 downto 1) & '0';
-- Since part of column is stored in ramaddr in dsact1, use that to
-- reduce fanout on vreq.startaddr
dv.sdo_address := vcoladdr(13 downto 10) & '0' & vcoladdr(9 downto 1) & '0';
if vreq.hwrite='1' then
dv.s := dswr1;
else
dv.s := dsrd1;
dv.readpipe(0) := '1';
end if;
when dswr1 =>
-- NOP,NOP,[WR]: issue either WR+D or NOP+D
dv.sdo_bdrive := '0';
dv.sdo_qdrive := '0';
inc_sdoaddr := '1';
inc_ramaddr := '1';
if lastwrite='1' then
dv.sdo_dqm := vmaskfirst or vmasklast;
dv.s := dswr3;
else
dv.sdo_casn := '0';
dv.sdo_wen := '0';
dv.sdo_dqm := vmaskfirst;
dv.s := dswr2;
end if;
when dswr2 =>
dv.sdo_dqm := (others => '0');
dv.sdo_bdrive := '0';
dv.sdo_qdrive := '0';
inc_sdoaddr := '1';
inc_ramaddr := '1';
if lastwrite='0' then
dv.sdo_casn := '0';
dv.sdo_wen := '0';
else
dv.s := dswr3;
dv.sdo_dqm := vmasklast;
end if;
when dswr3 =>
-- ...,WR+D,WR+D,[NOP+D]: issue NOP
dv.sdo_qdrive := '0';
dv.sdo_dqm := (others => '1');
dv.s := dswr4;
incdone := '1';
when dswr4 =>
-- Issue more NOP:s to meet tWR
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
if dr.idlectr(0)=dr.cfg.twr then
dv.s := dswr5;
end if;
when dswr5 =>
-- Issue NOP:s until tRAS met.
if dr.cmdctr(2 downto 0)="000" then
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.s := dswr6;
end if;
when dswr6 =>
-- PRE: issue one or two NOP:s depending on trp setting
if dr.idlectr(1 downto 0)=dr.cfg.trp then
dv.s := dsidle;
else
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
end if;
when dsrd1 =>
inc_sdoaddr := '1';
if lastreadcmd='0' then
dv.sdo_casn := '0';
dv.readpipe(0):='1';
elsif dr.cmdctr(2 downto 0)="000" then
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.s := dsrd3;
else
dv.s := dsrd2;
end if;
when dsrd2 =>
if dr.cmdctr(2 downto 0)="000" then
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.s := dsrd3;
end if;
when dsrd3 =>
if dr.idlectr(1 downto 0)=dr.cfg.trp then
if dv.readdone='1' then
dv.s := dsidle;
else
dv.s := dsrd4;
end if;
else
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
end if;
when dsrd4 =>
if dv.readdone='1' then
dv.s := dsidle;
end if;
when dsreg1 =>
rbw := '1';
rbwd(2*ddrbits+chkbits-1 downto ddrbits+chkbits) := regrdata(2*ddrbits-1 downto ddrbits);
rbwd(ddrbits-1 downto 0) := regrdata(ddrbits-1 downto 0);
if vreq.hwrite='1' then
dv.s := dsreg2;
elsif regad="100" and dr.cfg.mobileen='1' then
dv.sdo_address := (others => '0');
dv.sdo_ba := "01";
dv.sdo_csn := "10";
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.sdo_wen := '0';
dv.s := dssrr1;
dv.cmdctr(0) := '1';
null;
else
incdone := '1';
dv.s := dsidle;
end if;
when dsreg2 =>
case regad is
when "000" =>
dv.cfg.refon := wrdreg1(31);
dv.cfg.trp(0) := wrdreg1(30);
dv.cfg.trfc(2 downto 0) := wrdreg1(29 downto 27);
dv.cfg.trcd := wrdreg1(26);
dv.cfg.bsize := wrdreg1(25 downto 23);
dv.cfg.csize := wrdreg1(22 downto 21);
dv.cfg.command := wrdreg1(20 downto 18);
dv.cfg.dllrst := wrdreg1(17);
dv.cfg.renable := wrdreg1(16);
dv.cfg.cke := wrdreg1(15);
dv.cfg.refresh := wrdreg1(11 downto 0);
when "010" =>
dv.cfg.mobileen := wrdreg3(31);
dv.cfg.cl := wrdreg3(30);
dv.cfg.tcke := wrdreg3(24);
dv.cfg.txsr(3 downto 0) := wrdreg3(23 downto 20);
dv.cfg.txp(0) := wrdreg3(19);
dv.cfg.pmode := wrdreg3(18 downto 16);
dv.cfg.ds (5 downto 3) := wrdreg3(7 downto 5);
dv.cfg.tcsr(3 downto 2) := wrdreg3(4 downto 3);
dv.cfg.pasr(5 downto 3) := wrdreg3(2 downto 0);
-- Extended DDR400 fields
dv.cfg.tras := wrdreg3(29 downto 28);
dv.cfg.txsr(5 downto 4) := wrdreg3(27 downto 26);
dv.cfg.txp(1) := wrdreg3(25);
dv.cfg.twr := wrdreg3(11);
dv.cfg.trp(1) := wrdreg3(10);
dv.cfg.trfc(4 downto 3) := wrdreg3(9 downto 8);
when "101" =>
if confapi /= 0 then
dv.cfg.conf(31 downto 0) := wrdreg2;
end if;
when "110" =>
if confapi /= 0 then
dv.cfg.conf(63 downto 32) := wrdreg3;
end if;
when others =>
null;
end case;
incdone := '1';
dv.s := dsidle;
when dscmd1 =>
dv.sdo_csn := (others => '0');
dv.sdo_address(10) := '1';
dv.cfg.command := "000";
dv.s := dscmd2;
case dr.cfg.command is
when "010" => -- PRECHARGE ALL
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.cmdctr(1 downto 0) := "11";
when "100" => -- AUTO-REFRESH
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.cmdctr(4 downto 0) := dr.cfg.trfc;
when "110" => -- MODE REGISTER
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.sdo_wen := '0';
dv.sdo_ba := "00";
dv.sdo_address := "00000000" & "01" & dr.cfg.cl & "0001";
if dr.cfg.mobileen='0' then
dv.sdo_address(8) := dr.cfg.dllrst;
end if;
if dr.cfg.dllrst='1' then
dv.cmdctr := std_logic_vector(to_unsigned(200,dr.cmdctr'length));
end if;
when "111" => -- EXT. MODE REGISTER
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.sdo_wen := '0';
if dr.cfg.mobileen='1' then
dv.sdo_ba := "10";
dv.sdo_address := "0000000" & dr.cfg.ds(5 downto 3) & dr.cfg.tcsr(3 downto 2)
& dr.cfg.pasr(5 downto 3);
else
dv.sdo_ba := "01";
dv.sdo_address := "000000000000000"; -- bit0=0 -> DLL enable
end if;
dv.cfg.pasr(2 downto 0) := dr.cfg.pasr(5 downto 3);
dv.cfg.ds(2 downto 0) := dr.cfg.ds(5 downto 3);
dv.cfg.tcsr(1 downto 0) := dr.cfg.tcsr(3 downto 2);
when others => null;
end case;
when dscmd2 =>
if dr.cmdctr=(dr.cmdctr'range => '0') then
dv.s := dsidle;
end if;
when dspdown1 =>
dv.sdo_csn := "00";
if dr.cfg.pmode(0)='1' or dr.cfg.pmode(1)='1' then
dv.cfg.cke := '0';
end if;
if dr.cfg.pmode(1)='1' then
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
end if;
if dr.cfg.pmode(2)='1' and dr.cfg.pmode(0)='1' then
dv.sdo_wen := '0';
end if;
if dr.cfg.pmode(0)='1' then
dv.cmdctr(1 downto 0) := dr.cfg.txp;
end if;
if dr.cfg.pmode(1)='1' then
if dr.cfg.mobileen='1' then
dv.cmdctr(5 downto 0) := dr.cfg.txsr;
else
dv.cmdctr(7 downto 0) := std_logic_vector(to_unsigned(200,8));
end if;
end if;
dv.pdowns(1) := '0';
dv.s := dspdown2;
when dspdown2 =>
dv.pdowns(0) := '1';
if dr.pdowns(0)='0' and dr.cmdctr=(dr.cmdctr'range => '0') then
dv.pdowns(1):='1';
end if;
if dr.cfg.pmode(2)='1' and dr.cfg.pmode(0)='0' then
dv.sdo_ck := "000";
end if;
if dr.cfg.pmode(1)='1' then
dv.refpend := '1';
end if;
if (dr.refpend='1' and dr.cfg.pmode(1)='0') or vstart /= vdone then
if (dr.pdowns(0) or not dr.cfg.tcke)='1' then
dv.cfg.cke := '1';
if dr.pdowns(1)='1' then
dv.s := dsidle;
else
dv.s := dscmd2;
dv.pdowns(0) := '0';
end if;
end if;
end if;
when dsref1 =>
dv.s := dscmd2;
dv.cmdctr(4 downto 0) := dr.cfg.trfc;
when dssrr1 =>
if dr.cmdctr(0)='0' then
dv.sdo_casn := '0';
dv.readpipe(0):='1';
dv.s := dssrr2;
end if;
when dssrr2 =>
if datavalid='1' then
incdone := '1';
dv.s := dsidle;
end if;
end case;
if inc_sdoaddr='1' then
dv.sdo_address(l2blen-l2ddrw downto 1) :=
std_logic_vector(unsigned(dr.sdo_address(l2blen-l2ddrw downto 1))+1);
end if;
if inc_ramaddr='1' then
dv.ramaddr := std_logic_vector(unsigned(dr.ramaddr)+1);
end if;
-- Update the done flags
dv.resp.done_tog := (dr.resp.done_tog xor incdone) and (not reqsel);
dv.resp.rctr_gray := vrctr and (not reqselv);
dv.resp2.done_tog := (dr.resp2.done_tog xor incdone) and reqsel;
dv.resp2.rctr_gray := vrctr and reqselv;
---------------------------------------------------------------------------
-- DDR Init Sequence FSM
---------------------------------------------------------------------------
-- Command sequence lookup table
seqin := dr.cfg.mobileen & dr.initpos;
case seqin is
-- Mobile DDR
when "1100" => seqout := "0010"; -- PRECHARGE ALL
when "1011" => seqout := "0100"; -- AUTO REFRESH #1
when "1010" => seqout := "0100"; -- AUTO REFRESH #2
when "1001" => seqout := "0110"; -- MODE REG
when "1000" => seqout := "0111"; -- EXT MODE REG
-- Normal DDR
when "0110" => seqout := "0010"; -- PRECHARGE ALL
when "0101" => seqout := "0111"; -- EXT MODE REG En DLL
when "0100" => seqout := "1110"; -- MODE REG Rst DLL
when "0011" => seqout := "0010"; -- PRECHARGE ALL
when "0010" => seqout := "0100"; -- AUTO REFRESH #1
when "0001" => seqout := "0100"; -- AUTO REFRESH #2
when "0000" => seqout := "0110"; -- MODE REG NoRst DLL
when others => seqout := "0000";
end case;
case dr.initstate is
when disrstdel =>
if dr.refctr=std_logic_vector(to_unsigned(MHz*rstdel,dr.refctr'length)) then
dv.initstate := disidle;
if pwron=0 then dv.cfg.renable:='0'; end if;
end if;
-- Bypass reset delay by writing anything to regsd2
if vstartd='1' and (vreq.hio='1' and vreq.hwrite='1' and vreq.endaddr(4 downto 2)="001") then
dv.initstate := disidle;
if pwron=0 then dv.cfg.renable:='0'; end if;
end if;
when disidle =>
if dr.cfg.renable='1' then
dv.cfg.cke := '1';
if dr.cfg.cke='1' then
dv.initpos := "111";
dv.initstate := disrun;
end if;
end if;
when disrun =>
if dr.cfg.command="000" then
dv.cfg.dllrst := seqout(3);
dv.cfg.command := seqout(2 downto 0);
dv.initpos := std_logic_vector(unsigned(dr.initpos)-1);
if dr.initpos="000" then
dv.initstate := disfinished;
end if;
end if;
when disfinished =>
if dr.cfg.command="000" then
dv.cfg.renable := '0';
dv.cfg.refon := '1';
dv.initstate := disidle;
end if;
end case;
---------------------------------------------------------------------------
-- Reset
---------------------------------------------------------------------------
if ddr_rst='0' then
dv.s := dsidle;
dv.cmdctr := (others => '0');
dv.refctr := (others => '0');
dv.resp := ddr_response_none;
dv.resp2 := ddr_response_none;
dv.initstate := disrstdel;
dv.refpend := '0';
-- Reset cfg record
dv.cfg.command := "000";
dv.cfg.csize := conv_std_logic_vector(col-9, 2);
dv.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
dv.cfg.refon := '0';
dv.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
dv.cfg.dllrst := '0';
dv.cfg.pasr := (others => '0');
dv.cfg.tcsr := (others => '0');
dv.cfg.ds := (others => '0');
dv.cfg.pmode := (others => '0');
dv.cfg.txsr := conv_std_logic_vector(120*MHz/1000, 6);
dv.cfg.txp := "01";
dv.cfg.cl := '0'; -- CL = 3/2 -- ****
dv.cfg.tcke := '1';
if MHz > 100 then
dv.cfg.trcd := '1';
else dv.cfg.trcd := '0';
end if;
if MHz > 100 then
dv.cfg.trp := "01";
else dv.cfg.trp := "00";
end if;
dv.cfg.renable := '1'; -- Updated in disrstdel state
if mobile >= 2 then
dv.cfg.mobileen := '1'; -- Default: Mobile DDR
else dv.cfg.mobileen := '0';
end if;
if mobile >= 2 then
dv.cfg.trfc := conv_std_logic_vector(98*MHz/1000-2, 5);
else dv.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 5);
end if;
if ddr_syncrst /= 0 then
dv.sdo_ck := "000";
if mobile >= 2 then
dv.cfg.cke := '1';
else dv.cfg.cke := '0';
end if;
end if;
if confapi /= 0 then
dv.cfg.conf(31 downto 0) := conv_std_logic_vector(conf0, 32); --x"0000A0A0";
dv.cfg.conf(63 downto 32) := conv_std_logic_vector(conf1, 32); --x"00060606";
else
dv.cfg.conf := (others => '0');
end if;
if MHz > 175 then
dv.cfg.tras := "10";
elsif MHz > 150 then
dv.cfg.tras := "01";
else
dv.cfg.tras := "00";
end if;
if MHz > 133 then
dv.cfg.twr := '1';
else
dv.cfg.twr := '0';
end if;
dv.sdo_csn := "11";
dv.sdo_dqm := (others => '1');
dv.sdo_wen := '1';
dv.sdo_rasn := '1';
dv.sdo_casn := '1';
-- Extra reset for X-sensitive techs
dv.ramaddr := (others => '0');
end if;
---------------------------------------------------------------------------
-- Static logic/forced regs, etc
---------------------------------------------------------------------------
-- Force mobile disable/enabled
if mobile=0 then dv.cfg.mobileen := '0'; end if;
if mobile=3 then dv.cfg.mobileen := '1'; end if;
if mobile=0 then
dv.cfg.pasr := (others => '0');
dv.cfg.tcsr := (others => '0');
dv.cfg.ds := (others => '0');
dv.cfg.pmode := (others => '0');
dv.cfg.txp := "00";
dv.cfg.txsr := (others => '0');
dv.cfg.tcke := '0';
end if;
if ddr400=0 then
dv.cfg.tras := "00";
dv.cfg.txsr(5 downto 4) := "00";
dv.cfg.txp(1) := '0';
dv.cfg.trp(1) := '0';
dv.cfg.trfc(4 downto 3) := "00";
dv.cfg.twr := '0';
end if;
-- Assign sdo
o.bdrive := '1'; o.qdrive := '1'; --Temp.
o.sdck := dr.sdo_ck;
if ddr_syncrst/=0 and phyptctrl/=0 then
o.sdck := o.sdck and (o.sdck'range => ddr_rst);
end if;
if regoutput /= 0 then
o.casn := dr.sdo_casn;
o.rasn := dr.sdo_rasn;
o.sdwen := dr.sdo_wen;
o.sdcsn := dr.sdo_csn;
o.ba := '0' & dr.sdo_ba;
o.address := dr.sdo_address;
o.sdcke := (others => dr.cfg.cke);
if ddr_syncrst /= 0 and phyptctrl /= 0 then
if ddr_rst='0' then
if mobile >= 2 then o.sdcke := (others => '1');
else o.sdcke := (others => '0');
end if;
end if;
end if;
o.data(2*ddrbits-1 downto 0) := dr.sdo_data;
o.dqm(ddrbits/4-1 downto 0) := dr.sdo_dqm;
if chkbits > 0 then
o.cb(2*chkbits-1 downto 0) := dr.sdo_cb(2*chkbits-1 downto 0);
end if;
o.bdrive := dr.sdo_bdrive;
o.qdrive := dr.sdo_qdrive;
else
o.casn := dv.sdo_casn;
o.rasn := dv.sdo_rasn;
o.sdwen := dv.sdo_wen;
o.sdcsn := dv.sdo_csn;
o.ba := '0' & dv.sdo_ba;
o.address := dv.sdo_address;
o.sdcke := (others => dv.cfg.cke);
o.data(2*ddrbits-1 downto 0) := dv.sdo_data;
o.dqm(ddrbits/4-1 downto 0) := dv.sdo_dqm;
if chkbits > 0 then
o.cb(2*chkbits-1 downto 0) := dv.sdo_cb(2*chkbits-1 downto 0);
end if;
o.bdrive := dv.sdo_bdrive;
o.qdrive := dv.sdo_qdrive;
end if;
for x in 7 downto 0 loop
o.cbdqm(x) := o.dqm(2*x);
end loop;
-- Diag access
if vreq.maskcb='1' then
o.cbdqm := (others => '1');
end if;
if vreq.maskdata='1' then
o.dqm := (others => '1');
end if;
if scantest/=0 and phyptctrl/=0 then
if testen='1' then
o.bdrive := testoen;
o.qdrive := testoen;
end if;
end if;
---------------------------------------------------------------------------
-- Drive outputs
---------------------------------------------------------------------------
ndr <= dv;
sdo <= o;
response <= dr.resp;
response2 <= dr.resp2;
rbwrite <= rbw;
rbwaddr <= dr.ramaddr;
rbwdata <= rbwd;
wbraddr <= vdone & dv.ramaddr;
end process;
ddrregs: process(clk_ddr,arst)
begin
if rising_edge(clk_ddr) then
dr <= ndr;
end if;
if ddr_syncrst=0 and arst='0' then
dr.sdo_ck <= "000";
if mobile >= 2 then
dr.cfg.cke <= '1';
else dr.cfg.cke <= '0';
end if;
end if;
end process;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc308.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p04n01i00308ent IS
END c03s01b04x00p04n01i00308ent;
ARCHITECTURE c03s01b04x00p04n01i00308arch OF c03s01b04x00p04n01i00308ent IS
type REAL1 is range 1.0 to 10.0;
type REAL2 is range 10.0 to 20.0;
constant V1: REAL1 := 1.0;
constant V2: REAL2 := 20.0;
type REAL5 is range V1 to V2;
BEGIN
TESTING: PROCESS
variable k : REAL5 := 6.0;
BEGIN
k := 5.0;
assert NOT(k=5.0)
report "***PASSED TEST: c03s01b04x00p04n01i00308"
severity NOTE;
assert (k=5.0)
report "***FAILED TEST: c03s01b04x00p04n01i00308 - Expressions in floating point constraints in floating point type definitions need not be of the same floating point type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p04n01i00308arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc308.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p04n01i00308ent IS
END c03s01b04x00p04n01i00308ent;
ARCHITECTURE c03s01b04x00p04n01i00308arch OF c03s01b04x00p04n01i00308ent IS
type REAL1 is range 1.0 to 10.0;
type REAL2 is range 10.0 to 20.0;
constant V1: REAL1 := 1.0;
constant V2: REAL2 := 20.0;
type REAL5 is range V1 to V2;
BEGIN
TESTING: PROCESS
variable k : REAL5 := 6.0;
BEGIN
k := 5.0;
assert NOT(k=5.0)
report "***PASSED TEST: c03s01b04x00p04n01i00308"
severity NOTE;
assert (k=5.0)
report "***FAILED TEST: c03s01b04x00p04n01i00308 - Expressions in floating point constraints in floating point type definitions need not be of the same floating point type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p04n01i00308arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc308.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p04n01i00308ent IS
END c03s01b04x00p04n01i00308ent;
ARCHITECTURE c03s01b04x00p04n01i00308arch OF c03s01b04x00p04n01i00308ent IS
type REAL1 is range 1.0 to 10.0;
type REAL2 is range 10.0 to 20.0;
constant V1: REAL1 := 1.0;
constant V2: REAL2 := 20.0;
type REAL5 is range V1 to V2;
BEGIN
TESTING: PROCESS
variable k : REAL5 := 6.0;
BEGIN
k := 5.0;
assert NOT(k=5.0)
report "***PASSED TEST: c03s01b04x00p04n01i00308"
severity NOTE;
assert (k=5.0)
report "***FAILED TEST: c03s01b04x00p04n01i00308 - Expressions in floating point constraints in floating point type definitions need not be of the same floating point type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p04n01i00308arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity psl_test_cover3 is
end entity psl_test_cover3;
architecture test of psl_test_cover3 is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 20 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING PSL_TEST_COVER test case";
report "================================";
s_write <= '0';
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '0'; -- no hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait;
end process TestP;
--- psl statements
-- psl default clock is rising_edge(s_clk);
-- cover directive seems not supported (ignored by GHDL)
-- psl cover always (s_write -> not(s_read));
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Create and synchronize the main internal clock (LVDS bit clock) with the
-- rising edge between bits 0 and 1 of the LVDS packet.
entity car_clock_gen is
port(
hr_clk, reset: in std_logic;
main_clk, seq_reset, i2s_ws: out std_logic
);
end entity;
architecture a of car_clock_gen is
signal divider: unsigned(1 downto 0);
signal lvds_ctr: unsigned(7 downto 0);
begin
process(hr_clk, reset) is begin
if reset = '1' then
-- Initialize internal signals
divider <= (others => '1');
lvds_ctr <= (others => '1');
elsif rising_edge(hr_clk) then
if divider = "11" then
lvds_ctr <= lvds_ctr + 1;
end if;
divider <= divider + 1;
end if;
end process;
-- Inverted divide by 4 counter
main_clk <= not divider(1);
-- I2S spec has left channel LRCLK be low
i2s_ws <= lvds_ctr(7);
--Create virtual seq_reset
process(reset, divider(1)) is begin
if reset = '1' then
seq_reset <= '0';
elsif rising_edge(divider(1)) then --falling_edge(main_clk)
-- seq_reset should be high during rising_edge(main_clk)
-- of bit 2 out of every LVDS packet (32 main clocks)
if lvds_ctr(4 downto 0) = "00001" then
seq_reset <= '1';
else
seq_reset <= '0';
end if;
end if;
end process;
end architecture; |
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk); -- but also exit on a bad read
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
if (readOk = FALSE) then
good := FALSE;
else
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk);
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
read(l, s, readOk);
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out std_ulogic_vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'Z' => result(0) := 'Z'; result(1) := 'Z'; result(2) := 'Z'; result(3) := 'Z'; good := TRUE;
when 'X' => result(0) := 'X'; result(1) := 'X'; result(2) := 'X'; result(3) := 'X'; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in std_ulogic_vector;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: std_ulogic_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := To_X01Z(bv(4*i to 4*i+3));
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
when others =>
if (quad = "ZZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in std_ulogic_vector;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: std_ulogic_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := To_X01Z(bv(3*i to 3*i+2));
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
when others =>
if (tri = "ZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD:out BOOLEAN) is
variable tmp: std_ulogic_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_BitVector(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable tmp: std_ulogic_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_BitVector(tmp);
end HREAD;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
|
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk); -- but also exit on a bad read
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
if (readOk = FALSE) then
good := FALSE;
else
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk);
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
read(l, s, readOk);
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out std_ulogic_vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'Z' => result(0) := 'Z'; result(1) := 'Z'; result(2) := 'Z'; result(3) := 'Z'; good := TRUE;
when 'X' => result(0) := 'X'; result(1) := 'X'; result(2) := 'X'; result(3) := 'X'; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in std_ulogic_vector;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: std_ulogic_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := To_X01Z(bv(4*i to 4*i+3));
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
when others =>
if (quad = "ZZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in std_ulogic_vector;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: std_ulogic_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := To_X01Z(bv(3*i to 3*i+2));
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
when others =>
if (tri = "ZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD:out BOOLEAN) is
variable tmp: std_ulogic_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_BitVector(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable tmp: std_ulogic_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_BitVector(tmp);
end HREAD;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
|
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk); -- but also exit on a bad read
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
if (readOk = FALSE) then
good := FALSE;
else
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk);
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
read(l, s, readOk);
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out std_ulogic_vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'Z' => result(0) := 'Z'; result(1) := 'Z'; result(2) := 'Z'; result(3) := 'Z'; good := TRUE;
when 'X' => result(0) := 'X'; result(1) := 'X'; result(2) := 'X'; result(3) := 'X'; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in std_ulogic_vector;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: std_ulogic_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := To_X01Z(bv(4*i to 4*i+3));
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
when others =>
if (quad = "ZZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in std_ulogic_vector;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: std_ulogic_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := To_X01Z(bv(3*i to 3*i+2));
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
when others =>
if (tri = "ZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD:out BOOLEAN) is
variable tmp: std_ulogic_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_BitVector(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable tmp: std_ulogic_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_BitVector(tmp);
end HREAD;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
|
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk); -- but also exit on a bad read
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
if (readOk = FALSE) then
good := FALSE;
else
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk);
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
read(l, s, readOk);
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out std_ulogic_vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'Z' => result(0) := 'Z'; result(1) := 'Z'; result(2) := 'Z'; result(3) := 'Z'; good := TRUE;
when 'X' => result(0) := 'X'; result(1) := 'X'; result(2) := 'X'; result(3) := 'X'; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in std_ulogic_vector;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: std_ulogic_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := To_X01Z(bv(4*i to 4*i+3));
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
when others =>
if (quad = "ZZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in std_ulogic_vector;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: std_ulogic_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := To_X01Z(bv(3*i to 3*i+2));
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
when others =>
if (tri = "ZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD:out BOOLEAN) is
variable tmp: std_ulogic_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_BitVector(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable tmp: std_ulogic_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_BitVector(tmp);
end HREAD;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
|
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk); -- but also exit on a bad read
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
if (readOk = FALSE) then
good := FALSE;
else
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk);
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
read(l, s, readOk);
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out std_ulogic_vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'Z' => result(0) := 'Z'; result(1) := 'Z'; result(2) := 'Z'; result(3) := 'Z'; good := TRUE;
when 'X' => result(0) := 'X'; result(1) := 'X'; result(2) := 'X'; result(3) := 'X'; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in std_ulogic_vector;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: std_ulogic_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := To_X01Z(bv(4*i to 4*i+3));
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
when others =>
if (quad = "ZZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in std_ulogic_vector;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: std_ulogic_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := To_X01Z(bv(3*i to 3*i+2));
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
when others =>
if (tri = "ZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD:out BOOLEAN) is
variable tmp: std_ulogic_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_BitVector(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable tmp: std_ulogic_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_BitVector(tmp);
end HREAD;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_pkg.ALL;
ENTITY fifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fifo_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: MemoTableTLRUCounter.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any LRUCounter files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
use work.Constants.all;
use work.DefTypes.all;
ENTITY MemoTableTLRUCounterWay IS
--ENTITY TraceMemory IS
PORT
(
Clock : IN STD_LOGIC := '1';
WAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
WData : IN MemoTableTLRUCounterEntry;
--WData : IN STD_LOGIC_VECTOR (MemoTableTLRUCounterEntryWidth-1 DOWNTO 0);
WEnable : IN STD_LOGIC := '0';
RAddress : IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
RData : OUT MemoTableTLRUCounterEntry
--RData : OUT STD_LOGIC_VECTOR (MemoTableTLRUCounterEntryWidth-1 DOWNTO 0)
);
END MemoTableTLRUCounterWay;
--END TraceMemory;
ARCHITECTURE SYN OF MemoTableTLRUCounterWay IS
--ARCHITECTURE SYN OF TraceMemory IS
SIGNAL RAuxVector : STD_LOGIC_VECTOR (MemoTableTLRUCounterEntryWidth-1 DOWNTO 0);
SIGNAL WAuxObject : MemoTableTLRUCounterEntry;
SIGNAL WAuxVector : STD_LOGIC_VECTOR (MemoTableTLRUCounterEntryWidth-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_b : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_mixed_ports : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a: IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0);
clock0 : IN STD_LOGIC;
data_a : IN STD_LOGIC_VECTOR (MemoTableTLRUCounterEntryWidth-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (MemoTableTLRUCounterEntryWidth-1 DOWNTO 0);
wren_a : IN STD_LOGIC;
address_b: IN STD_LOGIC_VECTOR (MemoTableTWayAddressLenght-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
--RData <= RAuxVector;
RData <= StdLogicToLRUCounter(RAuxVector);
--WAuxVector <= WData;
WAuxObject <= WData;
WAuxVector <= LRUCounterToStdLogic(WAuxObject);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => MemoTableTWayLenght,
numwords_b => MemoTableTWayLenght,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "DONT_CARE",
widthad_a => MemoTableTWayAddressLenght,
widthad_b => MemoTableTWayAddressLenght,
width_a => MemoTableTLRUCounterEntryWidth,
width_b => MemoTableTLRUCounterEntryWidth,
width_byteena_a => 1
)
PORT MAP (
address_a => WAddress,
clock0 => Clock,
data_a => WAuxVector,
wren_a => WEnable,
address_b => RAddress,
q_b => RAuxVector
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_LRUCounter_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_LRUCounter_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "1"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_LRUCounter_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_LRUCounter_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[MemoTableTLRUCounterEntryWidth-1..0]"
-- Retrieval info: USED_PORT: q 0 0 64 0 LRUCounter NODEFVAL "q[MemoTableTLRUCounterEntryWidth-1..0]"
-- Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL "rdaddress[MemoTableTWayAddressLenght-1..0]"
-- Retrieval info: USED_PORT: wraddress 0 0 6 0 INPUT NODEFVAL "wraddress[MemoTableTWayAddressLenght-1..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
-- Retrieval info: CONNECT: @address_a 0 0 6 0 wraddress 0 0 6 0
-- Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 64 0 data 0 0 64 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTLRUCounter.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTLRUCounter.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTLRUCounter.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTLRUCounter.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTLRUCounter_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MemoTableTLRUCounter_syn.v TRUE
-- Retrieval info: LIB_FILE: altera_mf
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_fg_09_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity DMA_controller is
end entity DMA_controller;
-- end not in book
architecture behavioral of DMA_controller is
use work.DMA_controller_types_and_utilities.all;
begin
behavior : process is
variable address_reg0, address_reg1 : address;
variable count_reg0, count_reg1 : word;
-- . . .
begin
-- . . .
address_reg0 := address_reg0 + X"0000_0004";
-- . . .
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_fg_09_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity DMA_controller is
end entity DMA_controller;
-- end not in book
architecture behavioral of DMA_controller is
use work.DMA_controller_types_and_utilities.all;
begin
behavior : process is
variable address_reg0, address_reg1 : address;
variable count_reg0, count_reg1 : word;
-- . . .
begin
-- . . .
address_reg0 := address_reg0 + X"0000_0004";
-- . . .
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_fg_09_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity DMA_controller is
end entity DMA_controller;
-- end not in book
architecture behavioral of DMA_controller is
use work.DMA_controller_types_and_utilities.all;
begin
behavior : process is
variable address_reg0, address_reg1 : address;
variable count_reg0, count_reg1 : word;
-- . . .
begin
-- . . .
address_reg0 := address_reg0 + X"0000_0004";
-- . . .
end process behavior;
end architecture behavioral;
|
-------------------------------------------------------------------------------
--
-- Title : summ1
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : summ1.vhd
-- Generated : Fri Oct 3 18:01:09 2014
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {summ1} architecture {summ1}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity summ1 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
N : in STD_LOGIC;
S : out STD_LOGIC;
P : out STD_LOGIC
);
end summ1;
--}} End of automatically maintained section
architecture structural of summ1 is
component and2
Port(
A,B:in std_logic;
Z:out std_logic
);
end component;
component or2
Port(
A,B:in std_logic;
Z:out std_logic
);
end component;
component xor2
Port(
A,B:in std_logic;
Z:out std_logic
);
end component;
component inv
Port(
A:in std_logic;
Z:out std_logic
);
end component;
signal x1, x2, x3: std_logic;
begin
u1: xor2 port map (A, B, X1);
u2: xor2 port map (X1, N, S);
u3: and2 port map (A, B, X2);
u4: and2 port map (X1, N, X3);
u5: or2 port map (X2, X3, P);
end structural;
architecture behavioral of summ1 is
signal temp: std_logic;
begin
temp <= A xor B;
S <= temp xor N;
P <= (A and B) or (temp and N);
end behavioral; |
-------------------------------------------------------------------------------
--
-- Title : summ1
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : summ1.vhd
-- Generated : Fri Oct 3 18:01:09 2014
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {summ1} architecture {summ1}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity summ1 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
N : in STD_LOGIC;
S : out STD_LOGIC;
P : out STD_LOGIC
);
end summ1;
--}} End of automatically maintained section
architecture structural of summ1 is
component and2
Port(
A,B:in std_logic;
Z:out std_logic
);
end component;
component or2
Port(
A,B:in std_logic;
Z:out std_logic
);
end component;
component xor2
Port(
A,B:in std_logic;
Z:out std_logic
);
end component;
component inv
Port(
A:in std_logic;
Z:out std_logic
);
end component;
signal x1, x2, x3: std_logic;
begin
u1: xor2 port map (A, B, X1);
u2: xor2 port map (X1, N, S);
u3: and2 port map (A, B, X2);
u4: and2 port map (X1, N, X3);
u5: or2 port map (X2, X3, P);
end structural;
architecture behavioral of summ1 is
signal temp: std_logic;
begin
temp <= A xor B;
S <= temp xor N;
P <= (A and B) or (temp and N);
end behavioral; |
architecture RTL of FIFO is
begin
PROC_LABEL : process is
begin
end process proc_label;
-- Violations below
PROC_LABEL : process is
begin
end process proc_label;
end architecture RTL;
|
LIBRARY ieee;
USE iee.std_logic_1164.all;
USE iee.numeric_std.all;
ENTITY outputsTest IS
PORT (
outputBit: out std_logic;
bitTesting: out std_logic;
outputInteger: out integer;
outputVector: out std_logic_vector( 2 downto 0 ) );
END outputsTest
|
LIBRARY ieee;
USE iee.std_logic_1164.all;
USE iee.numeric_std.all;
ENTITY outputsTest IS
PORT (
outputBit: out std_logic;
bitTesting: out std_logic;
outputInteger: out integer;
outputVector: out std_logic_vector( 2 downto 0 ) );
END outputsTest
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DEL.VHD ***
--*** ***
--*** Function: Multiple Clock Bus Delay ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_del_var IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_del_var ;
ARCHITECTURE rtl OF fp_del_var IS
type delfftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : delfftype;
BEGIN
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
delff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO pipes LOOP
delff(k)(width DOWNTO 1) <= delff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delff(pipes)(width DOWNTO 1);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DEL.VHD ***
--*** ***
--*** Function: Multiple Clock Bus Delay ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_del_var IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_del_var ;
ARCHITECTURE rtl OF fp_del_var IS
type delfftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : delfftype;
BEGIN
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
delff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO pipes LOOP
delff(k)(width DOWNTO 1) <= delff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delff(pipes)(width DOWNTO 1);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DEL.VHD ***
--*** ***
--*** Function: Multiple Clock Bus Delay ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_del_var IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_del_var ;
ARCHITECTURE rtl OF fp_del_var IS
type delfftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : delfftype;
BEGIN
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
delff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO pipes LOOP
delff(k)(width DOWNTO 1) <= delff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delff(pipes)(width DOWNTO 1);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DEL.VHD ***
--*** ***
--*** Function: Multiple Clock Bus Delay ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_del_var IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_del_var ;
ARCHITECTURE rtl OF fp_del_var IS
type delfftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : delfftype;
BEGIN
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
delff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO pipes LOOP
delff(k)(width DOWNTO 1) <= delff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delff(pipes)(width DOWNTO 1);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DEL.VHD ***
--*** ***
--*** Function: Multiple Clock Bus Delay ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_del_var IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_del_var ;
ARCHITECTURE rtl OF fp_del_var IS
type delfftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : delfftype;
BEGIN
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
delff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO pipes LOOP
delff(k)(width DOWNTO 1) <= delff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delff(pipes)(width DOWNTO 1);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DEL.VHD ***
--*** ***
--*** Function: Multiple Clock Bus Delay ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_del_var IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_del_var ;
ARCHITECTURE rtl OF fp_del_var IS
type delfftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : delfftype;
BEGIN
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
delff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO pipes LOOP
delff(k)(width DOWNTO 1) <= delff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delff(pipes)(width DOWNTO 1);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DEL.VHD ***
--*** ***
--*** Function: Multiple Clock Bus Delay ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_del_var IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_del_var ;
ARCHITECTURE rtl OF fp_del_var IS
type delfftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : delfftype;
BEGIN
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
delff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO pipes LOOP
delff(k)(width DOWNTO 1) <= delff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delff(pipes)(width DOWNTO 1);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DEL.VHD ***
--*** ***
--*** Function: Multiple Clock Bus Delay ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_del_var IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_del_var ;
ARCHITECTURE rtl OF fp_del_var IS
type delfftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : delfftype;
BEGIN
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
delff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO pipes LOOP
delff(k)(width DOWNTO 1) <= delff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delff(pipes)(width DOWNTO 1);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DEL.VHD ***
--*** ***
--*** Function: Multiple Clock Bus Delay ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_del_var IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_del_var ;
ARCHITECTURE rtl OF fp_del_var IS
type delfftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : delfftype;
BEGIN
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
delff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO pipes LOOP
delff(k)(width DOWNTO 1) <= delff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delff(pipes)(width DOWNTO 1);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DEL.VHD ***
--*** ***
--*** Function: Multiple Clock Bus Delay ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_del_var IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_del_var ;
ARCHITECTURE rtl OF fp_del_var IS
type delfftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : delfftype;
BEGIN
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
delff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO pipes LOOP
delff(k)(width DOWNTO 1) <= delff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delff(pipes)(width DOWNTO 1);
END rtl;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cmdsts_if is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
C_ENABLE_QUEUE : integer range 0 to 1 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
mm2s_cmnd_wr : in std_logic ; --
mm2s_cmnd_data : in std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : out std_logic ; --
mm2s_sts_received_clr : in std_logic ; --
mm2s_sts_received : out std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
mm2s_done : out std_logic ; --
mm2s_error : out std_logic ; --
mm2s_interr : out std_logic ; --
mm2s_slverr : out std_logic ; --
mm2s_decerr : out std_logic ; --
mm2s_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_mm2s_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal mm2s_slverr_i : std_logic := '0';
signal mm2s_decerr_i : std_logic := '0';
signal mm2s_interr_i : std_logic := '0';
signal mm2s_error_or : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_slverr <= mm2s_slverr_i;
mm2s_decerr <= mm2s_decerr_i;
mm2s_interr <= mm2s_interr_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when mm2s_desc_cmplt = '1' and mm2s_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_NO_HOLD_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_NO_HOLD_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
-- De-assert tready on acceptance of status to prevent
-- over writing current status
elsif(sts_tready = '1' and m_axis_mm2s_sts_tvalid = '1')then
sts_tready <= '0';
-- If not status received assert ready to datamover
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_mm2s_sts_tready <= sts_tready;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
log_status <= '1' when m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0'
else '0';
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(log_status = '1')then
mm2s_done <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
mm2s_slverr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
mm2s_decerr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_DECERR_BIT);
mm2s_interr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_INTERR_BIT);
mm2s_tag <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- Clear flag on reset or sg_if status clear
if(m_axi_sg_aresetn = '0' or mm2s_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
mm2s_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error_or <= mm2s_slverr_i or mm2s_decerr_i or mm2s_interr_i;
-- Log errors into a global error output
MM2S_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((mm2s_error_or = '1')
or (stale_desc = '1' and mm2s_cmnd_wr='1'))then
mm2s_error <= '1';
end if;
end if;
end process MM2S_ERROR_PROCESS;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cmdsts_if is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
C_ENABLE_QUEUE : integer range 0 to 1 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
mm2s_cmnd_wr : in std_logic ; --
mm2s_cmnd_data : in std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : out std_logic ; --
mm2s_sts_received_clr : in std_logic ; --
mm2s_sts_received : out std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
mm2s_done : out std_logic ; --
mm2s_error : out std_logic ; --
mm2s_interr : out std_logic ; --
mm2s_slverr : out std_logic ; --
mm2s_decerr : out std_logic ; --
mm2s_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_mm2s_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal mm2s_slverr_i : std_logic := '0';
signal mm2s_decerr_i : std_logic := '0';
signal mm2s_interr_i : std_logic := '0';
signal mm2s_error_or : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_slverr <= mm2s_slverr_i;
mm2s_decerr <= mm2s_decerr_i;
mm2s_interr <= mm2s_interr_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when mm2s_desc_cmplt = '1' and mm2s_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_NO_HOLD_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_NO_HOLD_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
-- De-assert tready on acceptance of status to prevent
-- over writing current status
elsif(sts_tready = '1' and m_axis_mm2s_sts_tvalid = '1')then
sts_tready <= '0';
-- If not status received assert ready to datamover
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_mm2s_sts_tready <= sts_tready;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
log_status <= '1' when m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0'
else '0';
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(log_status = '1')then
mm2s_done <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
mm2s_slverr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
mm2s_decerr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_DECERR_BIT);
mm2s_interr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_INTERR_BIT);
mm2s_tag <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- Clear flag on reset or sg_if status clear
if(m_axi_sg_aresetn = '0' or mm2s_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
mm2s_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error_or <= mm2s_slverr_i or mm2s_decerr_i or mm2s_interr_i;
-- Log errors into a global error output
MM2S_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((mm2s_error_or = '1')
or (stale_desc = '1' and mm2s_cmnd_wr='1'))then
mm2s_error <= '1';
end if;
end if;
end process MM2S_ERROR_PROCESS;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cmdsts_if is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
C_ENABLE_QUEUE : integer range 0 to 1 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
mm2s_cmnd_wr : in std_logic ; --
mm2s_cmnd_data : in std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : out std_logic ; --
mm2s_sts_received_clr : in std_logic ; --
mm2s_sts_received : out std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
mm2s_done : out std_logic ; --
mm2s_error : out std_logic ; --
mm2s_interr : out std_logic ; --
mm2s_slverr : out std_logic ; --
mm2s_decerr : out std_logic ; --
mm2s_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_mm2s_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal mm2s_slverr_i : std_logic := '0';
signal mm2s_decerr_i : std_logic := '0';
signal mm2s_interr_i : std_logic := '0';
signal mm2s_error_or : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_slverr <= mm2s_slverr_i;
mm2s_decerr <= mm2s_decerr_i;
mm2s_interr <= mm2s_interr_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when mm2s_desc_cmplt = '1' and mm2s_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_NO_HOLD_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_NO_HOLD_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
-- De-assert tready on acceptance of status to prevent
-- over writing current status
elsif(sts_tready = '1' and m_axis_mm2s_sts_tvalid = '1')then
sts_tready <= '0';
-- If not status received assert ready to datamover
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_mm2s_sts_tready <= sts_tready;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
log_status <= '1' when m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0'
else '0';
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(log_status = '1')then
mm2s_done <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
mm2s_slverr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
mm2s_decerr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_DECERR_BIT);
mm2s_interr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_INTERR_BIT);
mm2s_tag <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- Clear flag on reset or sg_if status clear
if(m_axi_sg_aresetn = '0' or mm2s_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
mm2s_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error_or <= mm2s_slverr_i or mm2s_decerr_i or mm2s_interr_i;
-- Log errors into a global error output
MM2S_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((mm2s_error_or = '1')
or (stale_desc = '1' and mm2s_cmnd_wr='1'))then
mm2s_error <= '1';
end if;
end if;
end process MM2S_ERROR_PROCESS;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cmdsts_if is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
C_ENABLE_QUEUE : integer range 0 to 1 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
mm2s_cmnd_wr : in std_logic ; --
mm2s_cmnd_data : in std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : out std_logic ; --
mm2s_sts_received_clr : in std_logic ; --
mm2s_sts_received : out std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
mm2s_done : out std_logic ; --
mm2s_error : out std_logic ; --
mm2s_interr : out std_logic ; --
mm2s_slverr : out std_logic ; --
mm2s_decerr : out std_logic ; --
mm2s_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_mm2s_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal mm2s_slverr_i : std_logic := '0';
signal mm2s_decerr_i : std_logic := '0';
signal mm2s_interr_i : std_logic := '0';
signal mm2s_error_or : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_slverr <= mm2s_slverr_i;
mm2s_decerr <= mm2s_decerr_i;
mm2s_interr <= mm2s_interr_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when mm2s_desc_cmplt = '1' and mm2s_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_NO_HOLD_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_NO_HOLD_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
-- De-assert tready on acceptance of status to prevent
-- over writing current status
elsif(sts_tready = '1' and m_axis_mm2s_sts_tvalid = '1')then
sts_tready <= '0';
-- If not status received assert ready to datamover
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_mm2s_sts_tready <= sts_tready;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
log_status <= '1' when m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0'
else '0';
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(log_status = '1')then
mm2s_done <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
mm2s_slverr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
mm2s_decerr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_DECERR_BIT);
mm2s_interr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_INTERR_BIT);
mm2s_tag <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- Clear flag on reset or sg_if status clear
if(m_axi_sg_aresetn = '0' or mm2s_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
mm2s_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error_or <= mm2s_slverr_i or mm2s_decerr_i or mm2s_interr_i;
-- Log errors into a global error output
MM2S_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((mm2s_error_or = '1')
or (stale_desc = '1' and mm2s_cmnd_wr='1'))then
mm2s_error <= '1';
end if;
end if;
end process MM2S_ERROR_PROCESS;
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
entity alu is
port (
A,B : in std_logic_vector(7 downto 0);
S : in std_logic_vector(3 downto 0);
Cin : in std_logic;
F : out std_logic_vector(7 downto 0);
Cout : out std_logic
);
end alu;
architecture arch of alu is
component N_add_sub is
generic(
size:integer := 8
);
port (
A,B : in std_logic_vector(size-1 downto 0);
Cin : in std_logic;
mode : in std_logic;
sum : out std_logic_vector(size-1 downto 0);
Cout : out std_logic
);
end component;
component logic_unit is
port (
A,B : in std_logic_vector(7 downto 0);
Cin : in std_logic;
mode : in std_logic_vector(1 downto 0);
F : out std_logic_vector(7 downto 0)
);
end component;
component sr_unit is
port (
A : in std_logic_vector(7 downto 0);
Cin : in std_logic;
mode : in std_logic_vector(1 downto 0);
F : out std_logic_vector(7 downto 0);
Cout : out std_logic
);
end component;
signal A_val, B_val: std_logic_vector (7 downto 0);
signal U1_F :std_logic_vector(7 downto 0);
signal U1_cout : std_logic;
signal U1_mode : std_logic;
signal U2_F :std_logic_vector(7 downto 0);
signal U3_F :std_logic_vector(7 downto 0);
signal U3_mode : std_logic_vector(1 downto 0);
signal U3_cout : std_logic;
begin
U1 : N_add_sub port map(A_val,B_val,Cin,U1_mode,U1_F,U1_cout);
U2 : logic_unit port map(A_val,B_val,Cin,S(1 downto 0),U2_F);
U3 : sr_unit port map(A_val,Cin,U3_mode,U3_F,U3_cout);
U3_mode <= S(1 downto 0);
with S(3 downto 2) select
F <= U3_F when "10",
U2_F when "11",
U1_F when others;
with S(3 downto 2) select
Cout <= '0' when "10",
U3_Cout when "11",
U1_Cout when others;
mode: process(A,B,S,Cin) begin
-- swizzle inputs
if(S(3) = '0')then
case S(2 downto 0) is
when "000" =>
A_val <= (others=>'0');
B_val <= (others=>'0');
U1_mode <= '0';
when "001" =>
A_val <= (others=>'0');
B_val <= (others=>'0');
U1_mode <= '1';
when "010" =>
A_val <= A;
B_val <= (others=>'0');
U1_mode <= '0';
when "011" =>
A_val <= A;
B_val <= (others=>'0');
U1_mode <= '1';
when "100" =>
A_val <= A;
B_val <= B;
U1_mode <= '0';
when "101" =>
A_val <= A;
B_val <= A;
U1_mode <= '0';
when "110" =>
A_val <= A;
B_val <= B;
U1_mode <= '1';
when others =>
A_val <= B;
B_val <= A;
U1_mode <= '1';
end case;
else
A_val <= A;
B_val <= B;
end if;
end process mode;
end arch;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: dist_mem_gen_v7_2_tb_rng.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dist_mem_gen_v7_2_TB_RNG IS
GENERIC (
WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END dist_mem_gen_v7_2_TB_RNG;
ARCHITECTURE BEHAVIORAL OF dist_mem_gen_v7_2_TB_RNG IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2016, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : asynchronous fifo - Fall through mode
-------------------------------------------------------------------------------
-- Description: Asynchronous fifo for transfer of data between 2 clock domains
-- This is a simple fifo without "almost full" and count outputs.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
entity async_fifo_ft is
generic(
g_data_width : integer := 36;
g_depth_bits : integer := 9 -- depth = 2^depth_bits (9 == 512 words)
);
port (
-- write port signals (synchronized to write clock)
wr_clock : in std_logic;
wr_reset : in std_logic;
wr_en : in std_logic;
wr_din : in std_logic_vector(g_data_width-1 downto 0);
wr_full : out std_logic;
-- read port signals (synchronized to read clock)
rd_clock : in std_logic;
rd_reset : in std_logic;
rd_next : in std_logic;
rd_dout : out std_logic_vector(g_data_width-1 downto 0);
rd_count : out unsigned(g_depth_bits downto 0);
rd_valid : out std_logic );
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of async_fifo_ft : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of async_fifo_ft : entity is true;
end entity;
architecture altera of async_fifo_ft is
signal aclr : std_logic;
signal rdempty : std_logic;
signal rdusedw : std_logic_vector(g_depth_bits downto 0);
constant c_num_words : natural := 2 ** g_depth_bits;
COMPONENT dcfifo
GENERIC (
add_usedw_msb_bit : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (g_data_width-1 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (g_data_width-1 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR(g_depth_bits DOWNTO 0);
wrfull : OUT STD_LOGIC
);
END COMPONENT;
begin
aclr <= wr_reset or rd_reset;
dcfifo_component : dcfifo
generic map (
add_usedw_msb_bit => "ON",
intended_device_family => "Cyclone IV E",
lpm_numwords => c_num_words,
lpm_showahead => "ON",
lpm_type => "dcfifo",
lpm_width => g_data_width,
lpm_widthu => g_depth_bits+1,
overflow_checking => "ON",
rdsync_delaypipe => 4,
read_aclr_synch => "ON",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 4
)
port map (
aclr => aclr,
wrclk => wr_clock,
wrreq => wr_en,
data => wr_din,
wrfull => wr_full,
rdclk => rd_clock,
rdreq => rd_next,
q => rd_dout,
rdempty => rdempty,
rdusedw => rdusedw
);
rd_valid <= not rdempty;
rd_count <= unsigned(rdusedw);
end architecture;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2016, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : asynchronous fifo - Fall through mode
-------------------------------------------------------------------------------
-- Description: Asynchronous fifo for transfer of data between 2 clock domains
-- This is a simple fifo without "almost full" and count outputs.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
entity async_fifo_ft is
generic(
g_data_width : integer := 36;
g_depth_bits : integer := 9 -- depth = 2^depth_bits (9 == 512 words)
);
port (
-- write port signals (synchronized to write clock)
wr_clock : in std_logic;
wr_reset : in std_logic;
wr_en : in std_logic;
wr_din : in std_logic_vector(g_data_width-1 downto 0);
wr_full : out std_logic;
-- read port signals (synchronized to read clock)
rd_clock : in std_logic;
rd_reset : in std_logic;
rd_next : in std_logic;
rd_dout : out std_logic_vector(g_data_width-1 downto 0);
rd_count : out unsigned(g_depth_bits downto 0);
rd_valid : out std_logic );
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of async_fifo_ft : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of async_fifo_ft : entity is true;
end entity;
architecture altera of async_fifo_ft is
signal aclr : std_logic;
signal rdempty : std_logic;
signal rdusedw : std_logic_vector(g_depth_bits downto 0);
constant c_num_words : natural := 2 ** g_depth_bits;
COMPONENT dcfifo
GENERIC (
add_usedw_msb_bit : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (g_data_width-1 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (g_data_width-1 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR(g_depth_bits DOWNTO 0);
wrfull : OUT STD_LOGIC
);
END COMPONENT;
begin
aclr <= wr_reset or rd_reset;
dcfifo_component : dcfifo
generic map (
add_usedw_msb_bit => "ON",
intended_device_family => "Cyclone IV E",
lpm_numwords => c_num_words,
lpm_showahead => "ON",
lpm_type => "dcfifo",
lpm_width => g_data_width,
lpm_widthu => g_depth_bits+1,
overflow_checking => "ON",
rdsync_delaypipe => 4,
read_aclr_synch => "ON",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 4
)
port map (
aclr => aclr,
wrclk => wr_clock,
wrreq => wr_en,
data => wr_din,
wrfull => wr_full,
rdclk => rd_clock,
rdreq => rd_next,
q => rd_dout,
rdempty => rdempty,
rdusedw => rdusedw
);
rd_valid <= not rdempty;
rd_count <= unsigned(rdusedw);
end architecture;
|
----------------------------------------------------------------------------------------------
--
-- Input file : config_Pkg.vhd
-- Design name : config_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Configuration parameters for the design
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
PACKAGE config_Pkg IS
----------------------------------------------------------------------------------------------
-- CORE PARAMETERS
----------------------------------------------------------------------------------------------
-- Implement external interrupt
CONSTANT CFG_INTERRUPT : boolean := true; -- Disable or enable external interrupt [0,1]
-- Implement hardware multiplier
CONSTANT CFG_USE_HW_MUL : boolean := false; -- Disable or enable multiplier [0,1]
-- Implement hardware barrel shifter
CONSTANT CFG_USE_BARREL : boolean := false; -- Disable or enable barrel shifter [0,1]
-- Debug mode
CONSTANT CFG_DEBUG : boolean := false; -- Resets some extra registers for better readability
-- and enables feedback (report) [0,1]
-- Set CFG_DEBUG to zero to obtain best performance.
-- Memory parameters
CONSTANT CFG_DMEM_SIZE : positive := 32; -- Data memory bus size in 2LOG # elements
CONSTANT CFG_IMEM_SIZE : positive := 16; -- Instruction memory bus size in 2LOG # elements
CONSTANT CFG_BYTE_ORDER : boolean := true; -- Switch between MSB (1, default) and LSB (0) byte order policy
-- Register parameters
CONSTANT CFG_REG_FORCE_ZERO : boolean := true; -- Force data to zero if register address is zero [0,1]
CONSTANT CFG_REG_FWD_WB : boolean := true; -- Forward writeback to loosen register memory requirements [0,1]
CONSTANT CFG_MEM_FWD_WB : boolean := true; -- Forward memory result in stead of introducing stalls [0,1]
----------------------------------------------------------------------------------------------
-- CONSTANTS (currently not configurable / not tested)
----------------------------------------------------------------------------------------------
CONSTANT CFG_DMEM_WIDTH : positive := 32; -- Data memory width in bits
CONSTANT CFG_IMEM_WIDTH : positive := 32; -- Instruction memory width in bits
CONSTANT CFG_GPRF_SIZE : positive := 5; -- General Purpose Register File Size in 2LOG # elements
----------------------------------------------------------------------------------------------
-- BUS PARAMETERS
----------------------------------------------------------------------------------------------
TYPE memory_map_type IS ARRAY(natural RANGE <>) OF std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
CONSTANT CFG_NUM_SLAVES : positive := 2;
CONSTANT CFG_MEMORY_MAP : memory_map_type(0 TO CFG_NUM_SLAVES) := (X"00000000", X"00FFFFFF", X"FFFFFFFF");
END config_Pkg;
|
----------------------------------------------------------------------------------------------
--
-- Input file : config_Pkg.vhd
-- Design name : config_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Configuration parameters for the design
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
PACKAGE config_Pkg IS
----------------------------------------------------------------------------------------------
-- CORE PARAMETERS
----------------------------------------------------------------------------------------------
-- Implement external interrupt
CONSTANT CFG_INTERRUPT : boolean := true; -- Disable or enable external interrupt [0,1]
-- Implement hardware multiplier
CONSTANT CFG_USE_HW_MUL : boolean := false; -- Disable or enable multiplier [0,1]
-- Implement hardware barrel shifter
CONSTANT CFG_USE_BARREL : boolean := false; -- Disable or enable barrel shifter [0,1]
-- Debug mode
CONSTANT CFG_DEBUG : boolean := false; -- Resets some extra registers for better readability
-- and enables feedback (report) [0,1]
-- Set CFG_DEBUG to zero to obtain best performance.
-- Memory parameters
CONSTANT CFG_DMEM_SIZE : positive := 32; -- Data memory bus size in 2LOG # elements
CONSTANT CFG_IMEM_SIZE : positive := 16; -- Instruction memory bus size in 2LOG # elements
CONSTANT CFG_BYTE_ORDER : boolean := true; -- Switch between MSB (1, default) and LSB (0) byte order policy
-- Register parameters
CONSTANT CFG_REG_FORCE_ZERO : boolean := true; -- Force data to zero if register address is zero [0,1]
CONSTANT CFG_REG_FWD_WB : boolean := true; -- Forward writeback to loosen register memory requirements [0,1]
CONSTANT CFG_MEM_FWD_WB : boolean := true; -- Forward memory result in stead of introducing stalls [0,1]
----------------------------------------------------------------------------------------------
-- CONSTANTS (currently not configurable / not tested)
----------------------------------------------------------------------------------------------
CONSTANT CFG_DMEM_WIDTH : positive := 32; -- Data memory width in bits
CONSTANT CFG_IMEM_WIDTH : positive := 32; -- Instruction memory width in bits
CONSTANT CFG_GPRF_SIZE : positive := 5; -- General Purpose Register File Size in 2LOG # elements
----------------------------------------------------------------------------------------------
-- BUS PARAMETERS
----------------------------------------------------------------------------------------------
TYPE memory_map_type IS ARRAY(natural RANGE <>) OF std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
CONSTANT CFG_NUM_SLAVES : positive := 2;
CONSTANT CFG_MEMORY_MAP : memory_map_type(0 TO CFG_NUM_SLAVES) := (X"00000000", X"00FFFFFF", X"FFFFFFFF");
END config_Pkg;
|
----------------------------------------------------------------------------------------------
--
-- Input file : config_Pkg.vhd
-- Design name : config_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Configuration parameters for the design
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
PACKAGE config_Pkg IS
----------------------------------------------------------------------------------------------
-- CORE PARAMETERS
----------------------------------------------------------------------------------------------
-- Implement external interrupt
CONSTANT CFG_INTERRUPT : boolean := true; -- Disable or enable external interrupt [0,1]
-- Implement hardware multiplier
CONSTANT CFG_USE_HW_MUL : boolean := false; -- Disable or enable multiplier [0,1]
-- Implement hardware barrel shifter
CONSTANT CFG_USE_BARREL : boolean := false; -- Disable or enable barrel shifter [0,1]
-- Debug mode
CONSTANT CFG_DEBUG : boolean := false; -- Resets some extra registers for better readability
-- and enables feedback (report) [0,1]
-- Set CFG_DEBUG to zero to obtain best performance.
-- Memory parameters
CONSTANT CFG_DMEM_SIZE : positive := 32; -- Data memory bus size in 2LOG # elements
CONSTANT CFG_IMEM_SIZE : positive := 16; -- Instruction memory bus size in 2LOG # elements
CONSTANT CFG_BYTE_ORDER : boolean := true; -- Switch between MSB (1, default) and LSB (0) byte order policy
-- Register parameters
CONSTANT CFG_REG_FORCE_ZERO : boolean := true; -- Force data to zero if register address is zero [0,1]
CONSTANT CFG_REG_FWD_WB : boolean := true; -- Forward writeback to loosen register memory requirements [0,1]
CONSTANT CFG_MEM_FWD_WB : boolean := true; -- Forward memory result in stead of introducing stalls [0,1]
----------------------------------------------------------------------------------------------
-- CONSTANTS (currently not configurable / not tested)
----------------------------------------------------------------------------------------------
CONSTANT CFG_DMEM_WIDTH : positive := 32; -- Data memory width in bits
CONSTANT CFG_IMEM_WIDTH : positive := 32; -- Instruction memory width in bits
CONSTANT CFG_GPRF_SIZE : positive := 5; -- General Purpose Register File Size in 2LOG # elements
----------------------------------------------------------------------------------------------
-- BUS PARAMETERS
----------------------------------------------------------------------------------------------
TYPE memory_map_type IS ARRAY(natural RANGE <>) OF std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
CONSTANT CFG_NUM_SLAVES : positive := 2;
CONSTANT CFG_MEMORY_MAP : memory_map_type(0 TO CFG_NUM_SLAVES) := (X"00000000", X"00FFFFFF", X"FFFFFFFF");
END config_Pkg;
|
-------------------------------------------------------------------------------
-- Package with constants, types & functions for mean.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package mean_pkg is
constant DATA_WIDTH : natural := 6;
subtype t_data is unsigned(DATA_WIDTH-1 downto 0);
type t_data_array is array (natural range <>) of t_data;
function clog2(n : positive) return natural;
end package;
package body mean_pkg is
function clog2(n : positive) return natural is
begin
return integer(ceil(log2(real(n))));
end function;
end package body;
|
-------------------------------------------------------------------------------
-- Package with constants, types & functions for mean.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package mean_pkg is
constant DATA_WIDTH : natural := 6;
subtype t_data is unsigned(DATA_WIDTH-1 downto 0);
type t_data_array is array (natural range <>) of t_data;
function clog2(n : positive) return natural;
end package;
package body mean_pkg is
function clog2(n : positive) return natural is
begin
return integer(ceil(log2(real(n))));
end function;
end package body;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_MUX
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mux unit
-- Output what ALU operation requested
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Mux is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ARITH : in STD_LOGIC_VECTOR (7 downto 0);
LOGIC : in STD_LOGIC_VECTOR (7 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
MEMORY : in STD_LOGIC_VECTOR (7 downto 0);
CCR_ARITH : in STD_LOGIC_VECTOR (3 downto 0);
CCR_LOGIC : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
CCR_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ALU_Mux;
architecture Combinational of ALU_Mux is
begin
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD
ARITH when "0001", -- SUB
LOGIC when "0010", -- AND
LOGIC when "0011", -- OR
LOGIC when "0100", -- CMP
ARITH when "0101", -- ADDI
LOGIC when "0110", -- ANDI
SHIFT when "0111", -- SL
SHIFT when "1000", -- SR
MEMORY when "1001", -- LW
MEMORY when OTHERS; -- SW
with OP select
CCR_OUT <=
CCR_ARITH when "0000", -- ADD
CCR_ARITH when "0001", -- SUB
CCR_LOGIC when "0010", -- AND
CCR_LOGIC when "0011", -- OR
CCR_LOGIC when "0100", -- CMP
CCR_ARITH when "0101", -- ADDI
CCR_LOGIC when "0110", -- ANDI
"0000" when OTHERS; -- All flags cleared for other LOGIC operations
end Combinational;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_MUX
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mux unit
-- Output what ALU operation requested
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Mux is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ARITH : in STD_LOGIC_VECTOR (7 downto 0);
LOGIC : in STD_LOGIC_VECTOR (7 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
MEMORY : in STD_LOGIC_VECTOR (7 downto 0);
CCR_ARITH : in STD_LOGIC_VECTOR (3 downto 0);
CCR_LOGIC : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
CCR_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ALU_Mux;
architecture Combinational of ALU_Mux is
begin
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD
ARITH when "0001", -- SUB
LOGIC when "0010", -- AND
LOGIC when "0011", -- OR
LOGIC when "0100", -- CMP
ARITH when "0101", -- ADDI
LOGIC when "0110", -- ANDI
SHIFT when "0111", -- SL
SHIFT when "1000", -- SR
MEMORY when "1001", -- LW
MEMORY when OTHERS; -- SW
with OP select
CCR_OUT <=
CCR_ARITH when "0000", -- ADD
CCR_ARITH when "0001", -- SUB
CCR_LOGIC when "0010", -- AND
CCR_LOGIC when "0011", -- OR
CCR_LOGIC when "0100", -- CMP
CCR_ARITH when "0101", -- ADDI
CCR_LOGIC when "0110", -- ANDI
"0000" when OTHERS; -- All flags cleared for other LOGIC operations
end Combinational;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_MUX
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mux unit
-- Output what ALU operation requested
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Mux is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ARITH : in STD_LOGIC_VECTOR (7 downto 0);
LOGIC : in STD_LOGIC_VECTOR (7 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
MEMORY : in STD_LOGIC_VECTOR (7 downto 0);
CCR_ARITH : in STD_LOGIC_VECTOR (3 downto 0);
CCR_LOGIC : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
CCR_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ALU_Mux;
architecture Combinational of ALU_Mux is
begin
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD
ARITH when "0001", -- SUB
LOGIC when "0010", -- AND
LOGIC when "0011", -- OR
LOGIC when "0100", -- CMP
ARITH when "0101", -- ADDI
LOGIC when "0110", -- ANDI
SHIFT when "0111", -- SL
SHIFT when "1000", -- SR
MEMORY when "1001", -- LW
MEMORY when OTHERS; -- SW
with OP select
CCR_OUT <=
CCR_ARITH when "0000", -- ADD
CCR_ARITH when "0001", -- SUB
CCR_LOGIC when "0010", -- AND
CCR_LOGIC when "0011", -- OR
CCR_LOGIC when "0100", -- CMP
CCR_ARITH when "0101", -- ADDI
CCR_LOGIC when "0110", -- ANDI
"0000" when OTHERS; -- All flags cleared for other LOGIC operations
end Combinational;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_MUX
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mux unit
-- Output what ALU operation requested
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Mux is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ARITH : in STD_LOGIC_VECTOR (7 downto 0);
LOGIC : in STD_LOGIC_VECTOR (7 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
MEMORY : in STD_LOGIC_VECTOR (7 downto 0);
CCR_ARITH : in STD_LOGIC_VECTOR (3 downto 0);
CCR_LOGIC : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
CCR_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ALU_Mux;
architecture Combinational of ALU_Mux is
begin
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD
ARITH when "0001", -- SUB
LOGIC when "0010", -- AND
LOGIC when "0011", -- OR
LOGIC when "0100", -- CMP
ARITH when "0101", -- ADDI
LOGIC when "0110", -- ANDI
SHIFT when "0111", -- SL
SHIFT when "1000", -- SR
MEMORY when "1001", -- LW
MEMORY when OTHERS; -- SW
with OP select
CCR_OUT <=
CCR_ARITH when "0000", -- ADD
CCR_ARITH when "0001", -- SUB
CCR_LOGIC when "0010", -- AND
CCR_LOGIC when "0011", -- OR
CCR_LOGIC when "0100", -- CMP
CCR_ARITH when "0101", -- ADDI
CCR_LOGIC when "0110", -- ANDI
"0000" when OTHERS; -- All flags cleared for other LOGIC operations
end Combinational;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_MUX
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mux unit
-- Output what ALU operation requested
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Mux is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ARITH : in STD_LOGIC_VECTOR (7 downto 0);
LOGIC : in STD_LOGIC_VECTOR (7 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
MEMORY : in STD_LOGIC_VECTOR (7 downto 0);
CCR_ARITH : in STD_LOGIC_VECTOR (3 downto 0);
CCR_LOGIC : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
CCR_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ALU_Mux;
architecture Combinational of ALU_Mux is
begin
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD
ARITH when "0001", -- SUB
LOGIC when "0010", -- AND
LOGIC when "0011", -- OR
LOGIC when "0100", -- CMP
ARITH when "0101", -- ADDI
LOGIC when "0110", -- ANDI
SHIFT when "0111", -- SL
SHIFT when "1000", -- SR
MEMORY when "1001", -- LW
MEMORY when OTHERS; -- SW
with OP select
CCR_OUT <=
CCR_ARITH when "0000", -- ADD
CCR_ARITH when "0001", -- SUB
CCR_LOGIC when "0010", -- AND
CCR_LOGIC when "0011", -- OR
CCR_LOGIC when "0100", -- CMP
CCR_ARITH when "0101", -- ADDI
CCR_LOGIC when "0110", -- ANDI
"0000" when OTHERS; -- All flags cleared for other LOGIC operations
end Combinational;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_MUX
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mux unit
-- Output what ALU operation requested
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Mux is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ARITH : in STD_LOGIC_VECTOR (7 downto 0);
LOGIC : in STD_LOGIC_VECTOR (7 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
MEMORY : in STD_LOGIC_VECTOR (7 downto 0);
CCR_ARITH : in STD_LOGIC_VECTOR (3 downto 0);
CCR_LOGIC : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
CCR_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ALU_Mux;
architecture Combinational of ALU_Mux is
begin
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD
ARITH when "0001", -- SUB
LOGIC when "0010", -- AND
LOGIC when "0011", -- OR
LOGIC when "0100", -- CMP
ARITH when "0101", -- ADDI
LOGIC when "0110", -- ANDI
SHIFT when "0111", -- SL
SHIFT when "1000", -- SR
MEMORY when "1001", -- LW
MEMORY when OTHERS; -- SW
with OP select
CCR_OUT <=
CCR_ARITH when "0000", -- ADD
CCR_ARITH when "0001", -- SUB
CCR_LOGIC when "0010", -- AND
CCR_LOGIC when "0011", -- OR
CCR_LOGIC when "0100", -- CMP
CCR_ARITH when "0101", -- ADDI
CCR_LOGIC when "0110", -- ANDI
"0000" when OTHERS; -- All flags cleared for other LOGIC operations
end Combinational;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_MUX
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mux unit
-- Output what ALU operation requested
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Mux is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ARITH : in STD_LOGIC_VECTOR (7 downto 0);
LOGIC : in STD_LOGIC_VECTOR (7 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
MEMORY : in STD_LOGIC_VECTOR (7 downto 0);
CCR_ARITH : in STD_LOGIC_VECTOR (3 downto 0);
CCR_LOGIC : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
CCR_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ALU_Mux;
architecture Combinational of ALU_Mux is
begin
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD
ARITH when "0001", -- SUB
LOGIC when "0010", -- AND
LOGIC when "0011", -- OR
LOGIC when "0100", -- CMP
ARITH when "0101", -- ADDI
LOGIC when "0110", -- ANDI
SHIFT when "0111", -- SL
SHIFT when "1000", -- SR
MEMORY when "1001", -- LW
MEMORY when OTHERS; -- SW
with OP select
CCR_OUT <=
CCR_ARITH when "0000", -- ADD
CCR_ARITH when "0001", -- SUB
CCR_LOGIC when "0010", -- AND
CCR_LOGIC when "0011", -- OR
CCR_LOGIC when "0100", -- CMP
CCR_ARITH when "0101", -- ADDI
CCR_LOGIC when "0110", -- ANDI
"0000" when OTHERS; -- All flags cleared for other LOGIC operations
end Combinational;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_MUX
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mux unit
-- Output what ALU operation requested
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Mux is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ARITH : in STD_LOGIC_VECTOR (7 downto 0);
LOGIC : in STD_LOGIC_VECTOR (7 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
MEMORY : in STD_LOGIC_VECTOR (7 downto 0);
CCR_ARITH : in STD_LOGIC_VECTOR (3 downto 0);
CCR_LOGIC : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
CCR_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ALU_Mux;
architecture Combinational of ALU_Mux is
begin
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD
ARITH when "0001", -- SUB
LOGIC when "0010", -- AND
LOGIC when "0011", -- OR
LOGIC when "0100", -- CMP
ARITH when "0101", -- ADDI
LOGIC when "0110", -- ANDI
SHIFT when "0111", -- SL
SHIFT when "1000", -- SR
MEMORY when "1001", -- LW
MEMORY when OTHERS; -- SW
with OP select
CCR_OUT <=
CCR_ARITH when "0000", -- ADD
CCR_ARITH when "0001", -- SUB
CCR_LOGIC when "0010", -- AND
CCR_LOGIC when "0011", -- OR
CCR_LOGIC when "0100", -- CMP
CCR_ARITH when "0101", -- ADDI
CCR_LOGIC when "0110", -- ANDI
"0000" when OTHERS; -- All flags cleared for other LOGIC operations
end Combinational;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_MUX
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mux unit
-- Output what ALU operation requested
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Mux is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ARITH : in STD_LOGIC_VECTOR (7 downto 0);
LOGIC : in STD_LOGIC_VECTOR (7 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
MEMORY : in STD_LOGIC_VECTOR (7 downto 0);
CCR_ARITH : in STD_LOGIC_VECTOR (3 downto 0);
CCR_LOGIC : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
CCR_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ALU_Mux;
architecture Combinational of ALU_Mux is
begin
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD
ARITH when "0001", -- SUB
LOGIC when "0010", -- AND
LOGIC when "0011", -- OR
LOGIC when "0100", -- CMP
ARITH when "0101", -- ADDI
LOGIC when "0110", -- ANDI
SHIFT when "0111", -- SL
SHIFT when "1000", -- SR
MEMORY when "1001", -- LW
MEMORY when OTHERS; -- SW
with OP select
CCR_OUT <=
CCR_ARITH when "0000", -- ADD
CCR_ARITH when "0001", -- SUB
CCR_LOGIC when "0010", -- AND
CCR_LOGIC when "0011", -- OR
CCR_LOGIC when "0100", -- CMP
CCR_ARITH when "0101", -- ADDI
CCR_LOGIC when "0110", -- ANDI
"0000" when OTHERS; -- All flags cleared for other LOGIC operations
end Combinational;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_MUX
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mux unit
-- Output what ALU operation requested
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Mux is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ARITH : in STD_LOGIC_VECTOR (7 downto 0);
LOGIC : in STD_LOGIC_VECTOR (7 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
MEMORY : in STD_LOGIC_VECTOR (7 downto 0);
CCR_ARITH : in STD_LOGIC_VECTOR (3 downto 0);
CCR_LOGIC : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
CCR_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ALU_Mux;
architecture Combinational of ALU_Mux is
begin
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD
ARITH when "0001", -- SUB
LOGIC when "0010", -- AND
LOGIC when "0011", -- OR
LOGIC when "0100", -- CMP
ARITH when "0101", -- ADDI
LOGIC when "0110", -- ANDI
SHIFT when "0111", -- SL
SHIFT when "1000", -- SR
MEMORY when "1001", -- LW
MEMORY when OTHERS; -- SW
with OP select
CCR_OUT <=
CCR_ARITH when "0000", -- ADD
CCR_ARITH when "0001", -- SUB
CCR_LOGIC when "0010", -- AND
CCR_LOGIC when "0011", -- OR
CCR_LOGIC when "0100", -- CMP
CCR_ARITH when "0101", -- ADDI
CCR_LOGIC when "0110", -- ANDI
"0000" when OTHERS; -- All flags cleared for other LOGIC operations
end Combinational;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_MUX
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mux unit
-- Output what ALU operation requested
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Mux is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ARITH : in STD_LOGIC_VECTOR (7 downto 0);
LOGIC : in STD_LOGIC_VECTOR (7 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
MEMORY : in STD_LOGIC_VECTOR (7 downto 0);
CCR_ARITH : in STD_LOGIC_VECTOR (3 downto 0);
CCR_LOGIC : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
CCR_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ALU_Mux;
architecture Combinational of ALU_Mux is
begin
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD
ARITH when "0001", -- SUB
LOGIC when "0010", -- AND
LOGIC when "0011", -- OR
LOGIC when "0100", -- CMP
ARITH when "0101", -- ADDI
LOGIC when "0110", -- ANDI
SHIFT when "0111", -- SL
SHIFT when "1000", -- SR
MEMORY when "1001", -- LW
MEMORY when OTHERS; -- SW
with OP select
CCR_OUT <=
CCR_ARITH when "0000", -- ADD
CCR_ARITH when "0001", -- SUB
CCR_LOGIC when "0010", -- AND
CCR_LOGIC when "0011", -- OR
CCR_LOGIC when "0100", -- CMP
CCR_ARITH when "0101", -- ADDI
CCR_LOGIC when "0110", -- ANDI
"0000" when OTHERS; -- All flags cleared for other LOGIC operations
end Combinational;
|
------------------------------------------------------------------------
-- Title : GMII Testbench
-- Project : Xilinx LogiCORE Virtex-6 Embedded Tri-Mode Ethernet MAC
-- File : phy_tb.vhd
-- Version : 2.2
-------------------------------------------------------------------------------
--
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------
-- Description: This testbench will exercise the PHY ports of the EMAC
-- to demonstrate the functionality.
------------------------------------------------------------------------
--
-- This testbench performs the following operations on the EMAC
-- and its design example:
-- - Four frames are pushed into the receiver from the PHY
-- interface (GMII/MII):
-- The first is of minimum length (Length/Type = Length = 46 bytes).
-- The second frame sets Length/Type to Type = 0x8000.
-- The third frame has an error inserted.
-- The fourth frame only sends 4 bytes of data: the remainder of the
-- data field is padded up to the minimum frame length i.e. 46 bytes.
-- - These frames are then parsed from the MAC into the MAC's design
-- example. The design example provides a MAC client loopback
-- function so that frames which are received without error will be
-- looped back to the MAC transmitter and transmitted back to the
-- testbench. The testbench verifies that this data matches that
-- previously injected into the receiver.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_xilinx_mac is
port(
------------------------------------------------------------------
-- GMII Interface
------------------------------------------------------------------
gmii_txd : in std_logic_vector(7 downto 0);
gmii_tx_en : in std_logic;
gmii_tx_er : in std_logic;
gmii_tx_clk : in std_logic;
gmii_rxd : out std_logic_vector(7 downto 0);
gmii_rx_dv : out std_logic;
gmii_rx_er : out std_logic;
gmii_rx_clk : out std_logic;
gmii_col : out std_logic;
gmii_crs : out std_logic;
mii_tx_clk : out std_logic;
------------------------------------------------------------------
-- Test Bench Semaphores
------------------------------------------------------------------
configuration_busy : in boolean;
monitor_finished_1g : out boolean;
monitor_finished_100m : out boolean;
monitor_finished_10m : out boolean
);
end tb_xilinx_mac;
architecture behavioral of tb_xilinx_mac is
-- run first 0 .. C_PAUSE_AFTER_FRAME frames then pause for C_PAUSE_CYCLES
constant C_PAUSE_AFTER_FRAME : Natural := 12;
constant C_PAUSE2_AFTER_FRAME : Natural := C_PAUSE_AFTER_FRAME + 7;
constant C_PAUSE3_AFTER_FRAME : Natural := C_PAUSE2_AFTER_FRAME + 1;
constant C_PAUSE_CYCLES : Natural := 1800;
constant C_PAUSE2_CYCLES : Natural := 2800;
constant C_PAUSE3_CYCLES : Natural := 29800;
----------------------------------------------------------------------
-- Types to support frame data
----------------------------------------------------------------------
-- Tx Data and Data_valid record
type data_typ is record
data : bit_vector(7 downto 0); -- data
valid : bit; -- data_valid
error : bit; -- data_error
end record;
type frame_of_data_typ is array (natural range <>) of data_typ;
-- Tx Data, Data_valid and underrun record
type frame_typ is record
columns : frame_of_data_typ(0 to 65);-- data field
bad_frame : boolean; -- does this frame contain an error?
end record;
type frame_typ_ary is array (natural range <>) of frame_typ;
----------------------------------------------------------------------
-- Stimulus - Frame data
----------------------------------------------------------------------
-- The following constant holds the stimulus for the testbench. It is
-- an ordered array of frames, with frame 0 the first to be injected
-- into the core receiver PHY interface by the testbench.
----------------------------------------------------------------------
constant frame_data : frame_typ_ary := (
-------------
-- Frame 0
-- Send an ARP request: who has 192.168.5.9? Tell 192.168.5.1
-------------
0 => (
columns => (
0 => ( DATA => x"ff", VALID => '1', ERROR => '0'), --dest adr
1 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
2 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
3 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
4 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
5 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- src adr
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), -- type 0806 arp
13 => ( DATA => x"06", VALID => '1', ERROR => '0'),
14 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- hw adr type
15 => ( DATA => x"01", VALID => '1', ERROR => '0'),
16 => ( DATA => x"08", VALID => '1', ERROR => '0'), -- proto type
17 => ( DATA => x"00", VALID => '1', ERROR => '0'),
18 => ( DATA => x"06", VALID => '1', ERROR => '0'), -- MAC size
19 => ( DATA => x"04", VALID => '1', ERROR => '0'), -- IP size
20 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- arp req
21 => ( DATA => x"01", VALID => '1', ERROR => '0'),
22 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- src mac
23 => ( DATA => x"23", VALID => '1', ERROR => '0'),
24 => ( DATA => x"18", VALID => '1', ERROR => '0'),
25 => ( DATA => x"29", VALID => '1', ERROR => '0'),
26 => ( DATA => x"26", VALID => '1', ERROR => '0'),
27 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
28 => ( DATA => x"c0", VALID => '1', ERROR => '0'), --src ip
29 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
30 => ( DATA => x"05", VALID => '1', ERROR => '0'),
31 => ( DATA => x"01", VALID => '1', ERROR => '0'),
32 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- dest mac
33 => ( DATA => x"00", VALID => '1', ERROR => '0'),
34 => ( DATA => x"00", VALID => '1', ERROR => '0'),
35 => ( DATA => x"00", VALID => '1', ERROR => '0'),
36 => ( DATA => x"00", VALID => '1', ERROR => '0'),
37 => ( DATA => x"00", VALID => '1', ERROR => '0'),
38 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- dest ip
39 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
40 => ( DATA => x"04", VALID => '1', ERROR => '0'),
41 => ( DATA => x"17", VALID => '1', ERROR => '0'),
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
43 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
45 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
47 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 1
-- Send read HW_CFG with malformed header
-------------
1 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"21", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=HW_CFG
43 => ( DATA => x"03", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=1
45 => ( DATA => x"01", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 2
-- Send read HW_CFG
-------------
2 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=HW_CFG
43 => ( DATA => x"03", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=2
45 => ( DATA => x"02", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 2
-- Send UDP IP pkt dst ip_address C0A80417, from port f49a to port 2694
-------------
3 => (
columns => (
0 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => X"23", VALID => '1', ERROR => '0'),
2 => ( DATA => X"20", VALID => '1', ERROR => '0'),
3 => ( DATA => X"21", VALID => '1', ERROR => '0'),
4 => ( DATA => X"22", VALID => '1', ERROR => '0'),
5 => ( DATA => X"23", VALID => '1', ERROR => '0'),
6 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => X"23", VALID => '1', ERROR => '0'),
8 => ( DATA => X"18", VALID => '1', ERROR => '0'),
9 => ( DATA => X"29", VALID => '1', ERROR => '0'),
10 => ( DATA => X"26", VALID => '1', ERROR => '0'),
11 => ( DATA => X"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => X"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => X"00", VALID => '1', ERROR => '0'),
14 => ( DATA => X"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => X"00", VALID => '1', ERROR => '0'),
16 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => X"21", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => X"00", VALID => '1', ERROR => '0'),
19 => ( DATA => X"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => X"00", VALID => '1', ERROR => '0'),
21 => ( DATA => X"00", VALID => '1', ERROR => '0'),
22 => ( DATA => X"80", VALID => '1', ERROR => '0'),
23 => ( DATA => X"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => X"00", VALID => '1', ERROR => '0'),
26 => ( DATA => X"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => X"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => X"05", VALID => '1', ERROR => '0'),
29 => ( DATA => X"01", VALID => '1', ERROR => '0'),
30 => ( DATA => X"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => X"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => X"04", VALID => '1', ERROR => '0'),
33 => ( DATA => X"17", VALID => '1', ERROR => '0'),
34 => ( DATA => X"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => X"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => X"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => X"20", VALID => '1', ERROR => '0'),
38 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => X"0d", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => X"8b", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => X"79", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => X"68", VALID => '1', ERROR => '0'), -- Type=HW_CFG
43 => ( DATA => X"65", VALID => '1', ERROR => '0'),
44 => ( DATA => X"6c", VALID => '1', ERROR => '0'), -- ID=6c6c
45 => ( DATA => X"6c", VALID => '1', ERROR => '0'),
46 => ( DATA => X"6f", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => X"00", VALID => '1', ERROR => '0'),
48 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- Error this frame
bad_frame => false),
-------------
-- Frame 3
-- Send start stimuli=0x0
-------------
4 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"28", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"15", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=STRStim
43 => ( DATA => x"05", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=4
45 => ( DATA => x"04", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=6
47 => ( DATA => x"02", VALID => '1', ERROR => '0'), -- DATA_LENGTH
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- strstim
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- strstim
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- strstim
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- strstim
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- strstim
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- strstim
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 5
-- Send end stimuli=fff...
-------------
5 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"28", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"15", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=ENDStim
43 => ( DATA => x"06", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=5
45 => ( DATA => x"05", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=6
47 => ( DATA => x"02", VALID => '1', ERROR => '0'),
48 => ( DATA => x"ff", VALID => '1', ERROR => '0'), -- PAD + Stim
49 => ( DATA => x"ff", VALID => '1', ERROR => '0'), -- Stim
50 => ( DATA => x"ff", VALID => '1', ERROR => '0'), -- Stim
51 => ( DATA => x"ff", VALID => '1', ERROR => '0'), -- Stim
52 => ( DATA => x"ff", VALID => '1', ERROR => '0'), -- Stim
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Stim
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 6
-- Send write restart
-------------
6 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=RESET
43 => ( DATA => x"07", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=6
45 => ( DATA => x"06", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 7
-- Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694
-------------
7 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Adr
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'),
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'),
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'),
17 => ( DATA => x"21", VALID => '1', ERROR => '0'),
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'),
24 => ( DATA => x"00", VALID => '1', ERROR => '0'),
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'),
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"26", VALID => '1', ERROR => '0'),
37 => ( DATA => x"94", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'),
39 => ( DATA => x"0d", VALID => '1', ERROR => '0'),
40 => ( DATA => x"8b", VALID => '1', ERROR => '0'),
41 => ( DATA => x"79", VALID => '1', ERROR => '0'),
42 => ( DATA => x"68", VALID => '1', ERROR => '0'),
43 => ( DATA => x"65", VALID => '1', ERROR => '0'),
44 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
45 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
46 => ( DATA => x"6f", VALID => '1', ERROR => '0'),
47 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 8
-- Send UDP IP pkt dst ip_address C0A80417, from port f49a to port 2694
-------------
8 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Adr
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'),
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'),
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'),
17 => ( DATA => x"21", VALID => '1', ERROR => '0'),
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'),
24 => ( DATA => x"00", VALID => '1', ERROR => '0'),
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'),
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"26", VALID => '1', ERROR => '0'),
37 => ( DATA => x"94", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'),
39 => ( DATA => x"0d", VALID => '1', ERROR => '0'),
40 => ( DATA => x"8b", VALID => '1', ERROR => '0'),
41 => ( DATA => x"79", VALID => '1', ERROR => '0'),
42 => ( DATA => x"42", VALID => '1', ERROR => '0'),
43 => ( DATA => x"65", VALID => '1', ERROR => '0'),
44 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
45 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
46 => ( DATA => x"6f", VALID => '1', ERROR => '0'),
47 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 9
-- Send UDP IP pkt dst ip_address bc, from port f49a to port 2694
-------------
9 => (
columns => (
0 => ( DATA => x"ff", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
2 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
3 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
4 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
5 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Adr
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'),
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'),
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'),
17 => ( DATA => x"21", VALID => '1', ERROR => '0'),
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'),
24 => ( DATA => x"00", VALID => '1', ERROR => '0'),
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
31 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
32 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
33 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'),
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"26", VALID => '1', ERROR => '0'),
37 => ( DATA => x"94", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'),
39 => ( DATA => x"0d", VALID => '1', ERROR => '0'),
40 => ( DATA => x"8b", VALID => '1', ERROR => '0'),
41 => ( DATA => x"79", VALID => '1', ERROR => '0'),
42 => ( DATA => x"68", VALID => '1', ERROR => '0'),
43 => ( DATA => x"65", VALID => '1', ERROR => '0'),
44 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
45 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
46 => ( DATA => x"6f", VALID => '1', ERROR => '0'),
47 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 10
-- Send UDP IP pkt dst ip_address C0A80417, from port f49a to port 2694 with data x43 to trig tx to unknown IP";
-------------
10 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Adr
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'),
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'),
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'),
17 => ( DATA => x"21", VALID => '1', ERROR => '0'),
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'),
24 => ( DATA => x"00", VALID => '1', ERROR => '0'),
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'),
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"26", VALID => '1', ERROR => '0'),
37 => ( DATA => x"94", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'),
39 => ( DATA => x"0d", VALID => '1', ERROR => '0'),
40 => ( DATA => x"8b", VALID => '1', ERROR => '0'),
41 => ( DATA => x"79", VALID => '1', ERROR => '0'),
42 => ( DATA => x"43", VALID => '1', ERROR => '0'),
43 => ( DATA => x"65", VALID => '1', ERROR => '0'),
44 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
45 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
46 => ( DATA => x"6f", VALID => '1', ERROR => '0'),
47 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 12
-- Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694
-------------
11 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Adr
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'),
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'),
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'),
17 => ( DATA => x"21", VALID => '1', ERROR => '0'),
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'),
24 => ( DATA => x"00", VALID => '1', ERROR => '0'),
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'),
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"26", VALID => '1', ERROR => '0'),
37 => ( DATA => x"94", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'),
39 => ( DATA => x"0d", VALID => '1', ERROR => '0'),
40 => ( DATA => x"8b", VALID => '1', ERROR => '0'),
41 => ( DATA => x"79", VALID => '1', ERROR => '0'),
42 => ( DATA => x"68", VALID => '1', ERROR => '0'),
43 => ( DATA => x"65", VALID => '1', ERROR => '0'),
44 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
45 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
46 => ( DATA => x"6f", VALID => '1', ERROR => '0'),
47 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 13
-- Send cntrd
-------------
12 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=RESET
43 => ( DATA => x"0d", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=7
45 => ( DATA => x"07", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 1 after Pause
-- Send read ERROR_COUNT
-------------
C_PAUSE_AFTER_FRAME + 1 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=ERRORCNT
43 => ( DATA => x"08", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=7
45 => ( DATA => x"07", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 2 after pause
-- Send read ERROR_STORED
-------------
C_PAUSE_AFTER_FRAME + 2 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=ERRORstr
43 => ( DATA => x"09", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=8
45 => ( DATA => x"08", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 3
-- Send read ERRORS_DROPED
-------------
C_PAUSE_AFTER_FRAME + 3 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=ERRORDRP
43 => ( DATA => x"0a", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=9
45 => ( DATA => x"09", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 4 after pause
-- Send read next error
-------------
C_PAUSE_AFTER_FRAME + 4 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=getERR
43 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=10
45 => ( DATA => x"0a", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 5 after pause
-- Send read next error
-------------
C_PAUSE_AFTER_FRAME + 5 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=getERR
43 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=10
45 => ( DATA => x"0a", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 6 after pause
-- Send read next error
-------------
C_PAUSE_AFTER_FRAME + 6 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=ERR_RD
43 => ( DATA => x"0c", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=11
45 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 7 after pause
-- Send read next error
-------------
C_PAUSE_AFTER_FRAME + 7 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=getERR
43 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=12
45 => ( DATA => x"0c", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 1 after 1. pause
-- Send write restart
-------------
C_PAUSE2_AFTER_FRAME + 1 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=RESET
43 => ( DATA => x"07", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=6
45 => ( DATA => x"06", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 1 after 2. pause
-- Send read next error
-------------
C_PAUSE3_AFTER_FRAME + 1 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=getERR
43 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=10
45 => ( DATA => x"0a", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 2 after 2. pause
-- Send read next error
-------------
C_PAUSE3_AFTER_FRAME + 2 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=ERR_RD
43 => ( DATA => x"0c", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=11
45 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 2 after 3. pause
-- Send read next error
-------------
C_PAUSE3_AFTER_FRAME + 3 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=getERR
43 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=10
45 => ( DATA => x"0a", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 4 after 2. pause
-- Send read next error
-------------
C_PAUSE3_AFTER_FRAME + 4 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=ERR_RD
43 => ( DATA => x"0c", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=11
45 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 5 after pause2
-- Send read next error
-------------
C_PAUSE3_AFTER_FRAME + 5 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=getERR
43 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=12
45 => ( DATA => x"0c", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false)
);
----------------------------------------------------------------------
-- CRC engine
----------------------------------------------------------------------
function calc_crc (data : in std_logic_vector;
fcs : in std_logic_vector)
return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable crc_feedback : std_logic;
begin
crc := not fcs;
for I in 0 to 7 loop
crc_feedback := crc(0) xor data(I);
crc(4 downto 0) := crc(5 downto 1);
crc(5) := crc(6) xor crc_feedback;
crc(7 downto 6) := crc(8 downto 7);
crc(8) := crc(9) xor crc_feedback;
crc(9) := crc(10) xor crc_feedback;
crc(14 downto 10) := crc(15 downto 11);
crc(15) := crc(16) xor crc_feedback;
crc(18 downto 16) := crc(19 downto 17);
crc(19) := crc(20) xor crc_feedback;
crc(20) := crc(21) xor crc_feedback;
crc(21) := crc(22) xor crc_feedback;
crc(22) := crc(23);
crc(23) := crc(24) xor crc_feedback;
crc(24) := crc(25) xor crc_feedback;
crc(25) := crc(26);
crc(26) := crc(27) xor crc_feedback;
crc(27) := crc(28) xor crc_feedback;
crc(28) := crc(29);
crc(29) := crc(30) xor crc_feedback;
crc(30) := crc(31) xor crc_feedback;
crc(31) := crc_feedback;
end loop;
-- return the CRC result
return not crc;
end calc_crc;
-- Delay to provide setup and hold timing at the GMII/MII.
constant dly : time := 2 ns;
-- Testbench signals
signal mii_tx_clk_int : std_logic := '0';
signal mii_tx_clk100 : std_logic := '0';
signal mii_tx_clk10 : std_logic := '0';
signal gmii_rx_clk_int : std_logic := '0';
signal gmii_rx_clk1000 : std_logic := '0';
signal gmii_rx_clk100 : std_logic := '0';
signal gmii_rx_clk10 : std_logic := '0';
-- Testbench control signals
signal current_speed : string(1 to 6);
signal clkmux_en_100 : std_logic := '0';
signal clkmux_en_10 : std_logic := '0';
begin -- behavioral
-- Currently not used in this testbench.
gmii_col <= '0';
gmii_crs <= '0';
mii_tx_clk <= mii_tx_clk_int;
----------------------------------------------------------------------
-- gmii_rx_clk clock driver
----------------------------------------------------------------------
-- Drives gmii_rx_clk at 125 MHz for 1000Mb/s operation
p_gmii_rx_clk1000 : process
begin
gmii_rx_clk_int <= '0';
wait for 20 ns;
loop
wait for 4 ns;
gmii_rx_clk_int <= '1';
wait for 4 ns;
gmii_rx_clk_int <= '0';
end loop;
end process p_gmii_rx_clk1000;
gmii_rx_clk <= gmii_rx_clk_int;
----------------------------------------------------------------------
-- Simulus process
------------------
-- Send four frames through the MAC and Design Example
-- -- frame 0 = minimum length frame
-- -- frame 1 = type frame
-- -- frame 2 = errored frame
-- -- frame 3 = padded frame
----------------------------------------------------------------------
p_stimulus : process
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
variable frm_high : natural;
variable frm_low : natural;
begin
-- Initialise GMII
gmii_rxd <= "00000000";
gmii_rx_dv <= '0';
gmii_rx_er <= '0';
-- Initialize clock mux enables
clkmux_en_100 <= '0';
clkmux_en_10 <= '0';
-- Wait for the configuration to initialise the MAC
wait until configuration_busy;
wait until not configuration_busy;
current_speed <= "1gig ";
clkmux_en_100 <= '0';
clkmux_en_10 <= '0';
------------------------------------
-- Send frames at 1Gb/s speed
------------------------------------
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
frm_low := 0;
frm_high := C_PAUSE_AFTER_FRAME;
for i in 1 to 4 loop
for current_frame in frm_low to frm_high loop
assert false
report "EMAC: Sending Frame " & integer'image(current_frame) & " at 1Gb/s" & cr
severity note;
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd <= "01010101" after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd <= "11010101" after dly;
gmii_rx_dv <= '1' after dly;
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
-- Sending the MAC frame
fcs := (others => '0'); -- reset the FCS field
current_col := 0;
gmii_rxd <= to_stdlogicvector(frame_data(current_frame).columns(current_col).data) after dly;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after dly;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after dly;
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data(current_frame).columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd <= to_stdlogicvector(frame_data(current_frame).columns(current_col).data) after dly;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after dly;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after dly;
current_col := current_col + 1;
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1'; -- wait for next clock tick
end loop;
-- Send the FCS.
for j in 0 to 3 loop
gmii_rxd <= fcs(((8*j)+7) downto (8*j)) after dly;
--gmii_rxd <= x"00" after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1'; -- wait for next clock tick
end loop;
-- Clear the data lines.
gmii_rxd <= (others => '0') after dly;
gmii_rx_dv <= '0' after dly;
gmii_rx_er <= '0' after dly;
-- Adding the minimum Interframe gap for a receiver (8 idles)
for j in 0 to 7 loop
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
end loop;
end loop; -- current_frame
-- wait for next frame burst
if i = 1 then
for j in 0 to C_PAUSE_CYCLES loop
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
end loop;
frm_low := C_PAUSE_AFTER_FRAME + 1;
frm_high := C_PAUSE2_AFTER_FRAME;
elsif i = 2 then
for j in 0 to C_PAUSE2_CYCLES loop
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
end loop;
frm_low := C_PAUSE2_AFTER_FRAME + 1;
frm_high := C_PAUSE3_AFTER_FRAME;
else
for j in 0 to C_PAUSE3_CYCLES loop
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
end loop;
frm_low := C_PAUSE3_AFTER_FRAME + 1;
frm_high := frame_data'high;
end if;
end loop; -- second frame burst
-- Our work here is done
wait;
end process p_stimulus;
----------------------------------------------------------------------
-- Monitor process
------------------
-- This process checks the data coming out of the
-- transmitter to make sure that it matches that inserted into the
-- receiver.
-- -- frame 0 = minimum length frame
-- -- frame 1 = type frame
-- -- frame 2 = errored frame
-- -- frame 3 = padded frame
--
-- Repeated for all 3 speeds.
----------------------------------------------------------------------
p_monitor : process
variable f : frame_typ; -- temporary frame variable
variable current_col : natural := 0; -- Column counter
variable current_frame : natural := 0;
variable fcs : std_logic_vector(31 downto 0);
begin -- process p_monitor
monitor_finished_1g <= false;
monitor_finished_100m <= false;
monitor_finished_10m <= false;
-- first, get synced up with the TX clock
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
------------------------------------
-- Compare the frames at 1Gb/s speed
------------------------------------
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
-- loop over all the frames in the stimulus vector
loop
current_col := 0;
-- If the current frame had an error inserted then it would have been
-- dropped by the FIFO in the design example. Therefore move
-- immediately on to the next frame.
while frame_data(current_frame).bad_frame loop
current_frame := current_frame + 1;
if current_frame = frame_data'high + 1 then
exit;
end if;
end loop;
-- There are only 4 frames in this test.
if current_frame = frame_data'high + 1 then
exit;
end if;
-- Parse over the preamble field
while gmii_tx_en /= '1' or gmii_txd = "01010101" loop
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop;
assert false
report "EMAC: Comparing Frame " & integer'image(current_frame) & " at 1Gb/s" & cr
severity note;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd /= "11010101") then
assert false
report "EMAC: SFD not present" & cr
severity error;
end if;
fcs := (others => '0'); -- reset the FCS field
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
-- frame has started, loop over columns of frame
while ((frame_data(current_frame).columns(current_col).valid)='1') loop
assert (gmii_tx_en = to_stdulogic(frame_data(current_frame).columns(current_col).valid))
report "EMAC: gmii_tx_en incorrect" & cr
severity error;
if gmii_tx_en = '1' then
-- The transmitted Destination Address was the Source Address of the injected frame
if current_col < 6 then
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col+6).data), fcs);
assert (gmii_txd(7 downto 0) =
to_stdlogicvector(frame_data(current_frame).columns(current_col+6).data(7 downto 0)))
report "EMAC: gmii_txd incorrect" & cr
severity error;
-- The transmitted Source Address was the Destination Address of the injected frame
elsif current_col >= 6 and current_col < 12 then
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col-6).data), fcs);
assert (gmii_txd(7 downto 0) =
to_stdlogicvector(frame_data(current_frame).columns(current_col-6).data(7 downto 0)))
report "EMAC: gmii_txd incorrect" & cr
severity error;
-- for remainder of frame
else
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
assert (gmii_txd(7 downto 0) =
to_stdlogicvector(frame_data(current_frame).columns(current_col).data(7 downto 0)))
report "EMAC: gmii_txd incorrect" & cr
severity error;
end if;
end if;
-- wait for next column of data
current_col := current_col + 1;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- while data valid
-- Check the FCS
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
assert (gmii_txd = fcs(((8*j)+7) downto (8*j)))
report "EMAC: gmii_txd incorrect during FCS field" & cr
severity error;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- j
-- move to the next frame
if current_frame = frame_data'high then
exit;
else
current_frame := current_frame + 1;
end if;
end loop;
monitor_finished_1g <= true;
-- Our work here is done
wait;
end process p_monitor;
end behavioral;
|
-- Test case from Brian Padalino
--
library ieee;
use ieee.std_logic_1164.all;
package abc is
type Parameters_t is record
BW : natural;
PAIRS : natural;
end record;
type Indices_t is array (natural range <>) of std_logic_vector;
type Bus_t is record
Indices : Indices_t;
end record;
function Test(
abc_bus : Bus_t
) return Bus_t;
function Test(
abc_bus : Bus_t;
indices : Indices_t
) return Bus_t;
end package;
package body abc is
function Test(
abc_bus : Bus_t;
indices : Indices_t
) return Bus_t is
variable result : Bus_t(
Indices(abc_bus.Indices'range)(abc_bus.Indices'element'range)
) := Test(abc_bus);
begin
return result;
end function;
function Test(
abc_bus : Bus_t
) return Bus_t is
variable result : Bus_t(
Indices(abc_bus.Indices'range)(abc_bus.Indices'element'range)
) := abc_bus;
begin
return result;
end function;
end package body;
library ieee;
use ieee.std_logic_1164.all;
use work.abc;
use work.abc.all;
use std.env.finish;
entity record35 is
end entity;
architecture sim of record35 is
constant CLK_PERIOD : time := 10 ns;
signal clk : std_ulogic := '0';
constant abc_BUS_SETTINGS : abc.Parameters_t := (
BW => 8,
PAIRS => 2
);
signal abc_bus : abc.Bus_t(
Indices(abc_BUS_SETTINGS.PAIRS - 1 downto 0)(abc_BUS_SETTINGS.BW - 1 downto 0)
);
begin
clk <= not clk after CLK_PERIOD / 2;
test_runner : process
begin
abc_bus <= abc.Test(
abc_bus,
(
0 => std_logic_vector'(x"00"),
1 => std_logic_vector'(x"01")
)
);
wait for CLK_PERIOD;
finish;
end process test_runner;
end architecture sim;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.custom_pkg.all;
entity prediction is
port (clk : in std_logic;
enable : in std_logic;
output_hid : in eight_bit(num_neurons-1 downto 0);
predict : out std_logic_vector(7 downto 0)
);
end prediction;
architecture Behavioral of prediction is
begin
process (clk, enable, output_hid)
variable biggest : std_logic_vector(7 downto 0);
variable count : Integer;
begin
if enable = '0' then
biggest := (others=>'0');
count := 0;
else
if rising_edge(clk) then
if count < num_neurons then
if signed(output_hid(count)) > signed(biggest) then
biggest := output_hid(count);
end if;
count := count + 1;
end if;
end if;
end if;
predict <= biggest;
end process;
end Behavioral;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:47:17 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_iic_0_0/system_axi_iic_0_0_stub.vhdl
-- Design : system_axi_iic_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_axi_iic_0_0 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
iic2intc_irpt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
sda_t : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
scl_t : out STD_LOGIC;
gpo : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_axi_iic_0_0;
architecture stub of system_axi_iic_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,iic2intc_irpt,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,sda_i,sda_o,sda_t,scl_i,scl_o,scl_t,gpo[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_iic,Vivado 2016.4";
begin
end;
|
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP2X.VHD ***
--*** ***
--*** Function: Double Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp2x IS
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp2x;
ARCHITECTURE rtl OF hcc_alufp2x IS
type expbasefftype IS ARRAY (3+shiftspeed+doublespeed DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type manfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal manleftff, manrightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manleftdelff, manleftdeldelff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manalignff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expbaseff : expbasefftype;
signal expshiftff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal subexpone, subexptwo : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed+doublespeed DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal alunode, aluff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (64 DOWNTO 1);
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
FOR j IN 1 TO 3+shiftspeed+doublespeed LOOP
expbaseff(j)(k) <= '0';
END LOOP;
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed+doublespeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO 64 LOOP
manleftff(k) <= (aaff(k+13) AND NOT(switch)) OR (bbff(k+13) AND switch);
manrightff(k) <= (bbff(k+13) AND NOT(switch)) OR (aaff(k+13) AND switch);
END LOOP;
FOR k IN 1 TO 13 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
expbaseff(k)(13 DOWNTO 1) <= expbaseff(k-1)(13 DOWNTO 1); -- level 3 to 4/5/6
END LOOP;
FOR k IN 1 TO 13 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
-- once through add/sub, output can only be ieee754"0" if both inputs are ieee754"0"
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
ccsatff(k) <= ccsatff(k-1); -- level 3 to 4/5/6
cczipff(k) <= cczipff(k-1); -- level 3 to 4/5/6
END LOOP;
END IF;
END IF;
END PROCESS;
subexpone <= aaff(13 DOWNTO 1) - bbff(13 DOWNTO 1);
subexptwo <= bbff(13 DOWNTO 1) - aaff(13 DOWNTO 1);
switch <= subexpone(13);
expzerochk <= expshiftff - "0000001000000"; -- 63 ok, 64 not
gsa: IF (shiftspeed = 0) GENERATE
sftslow: hcc_rsftcomb64
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= manleftff(k) XOR invertleftff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightff) AND expzerochk(13);
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdelff;
alurightnode <= manalignff;
END GENERATE;
gsb: IF (shiftspeed = 1) GENERATE
sftfast: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manleftdeldelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
manleftdelff <= manleftff;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(13);
--*** LEVEL 4 ***
FOR k IN 1 TO 64 LOOP
manleftdeldelff(k) <= manleftdelff(k) XOR invertleftdelff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightdelff) AND expzerochkff;
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdeldelff;
alurightnode <= manalignff;
END GENERATE;
gaa: IF (doublespeed = 0) GENERATE
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aluleftnode + alurightnode + addsubff(3+shiftspeed);
END IF;
END IF;
END PROCESS;
alunode <= aluff;
--*** OUTPUTS ***
cc <= alunode & expbaseff(3+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
END GENERATE;
gab: IF (doublespeed = 1) GENERATE
gac: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
gad: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
cc <= alunode & expbaseff(4+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed+doublespeed)(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
bbman <= bb(77 DOWNTO 14);
ccman <= alunode;
END rtl;
|
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP2X.VHD ***
--*** ***
--*** Function: Double Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp2x IS
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp2x;
ARCHITECTURE rtl OF hcc_alufp2x IS
type expbasefftype IS ARRAY (3+shiftspeed+doublespeed DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type manfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal manleftff, manrightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manleftdelff, manleftdeldelff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manalignff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expbaseff : expbasefftype;
signal expshiftff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal subexpone, subexptwo : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed+doublespeed DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal alunode, aluff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (64 DOWNTO 1);
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
FOR j IN 1 TO 3+shiftspeed+doublespeed LOOP
expbaseff(j)(k) <= '0';
END LOOP;
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed+doublespeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO 64 LOOP
manleftff(k) <= (aaff(k+13) AND NOT(switch)) OR (bbff(k+13) AND switch);
manrightff(k) <= (bbff(k+13) AND NOT(switch)) OR (aaff(k+13) AND switch);
END LOOP;
FOR k IN 1 TO 13 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
expbaseff(k)(13 DOWNTO 1) <= expbaseff(k-1)(13 DOWNTO 1); -- level 3 to 4/5/6
END LOOP;
FOR k IN 1 TO 13 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
-- once through add/sub, output can only be ieee754"0" if both inputs are ieee754"0"
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
ccsatff(k) <= ccsatff(k-1); -- level 3 to 4/5/6
cczipff(k) <= cczipff(k-1); -- level 3 to 4/5/6
END LOOP;
END IF;
END IF;
END PROCESS;
subexpone <= aaff(13 DOWNTO 1) - bbff(13 DOWNTO 1);
subexptwo <= bbff(13 DOWNTO 1) - aaff(13 DOWNTO 1);
switch <= subexpone(13);
expzerochk <= expshiftff - "0000001000000"; -- 63 ok, 64 not
gsa: IF (shiftspeed = 0) GENERATE
sftslow: hcc_rsftcomb64
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= manleftff(k) XOR invertleftff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightff) AND expzerochk(13);
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdelff;
alurightnode <= manalignff;
END GENERATE;
gsb: IF (shiftspeed = 1) GENERATE
sftfast: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manleftdeldelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
manleftdelff <= manleftff;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(13);
--*** LEVEL 4 ***
FOR k IN 1 TO 64 LOOP
manleftdeldelff(k) <= manleftdelff(k) XOR invertleftdelff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightdelff) AND expzerochkff;
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdeldelff;
alurightnode <= manalignff;
END GENERATE;
gaa: IF (doublespeed = 0) GENERATE
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aluleftnode + alurightnode + addsubff(3+shiftspeed);
END IF;
END IF;
END PROCESS;
alunode <= aluff;
--*** OUTPUTS ***
cc <= alunode & expbaseff(3+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
END GENERATE;
gab: IF (doublespeed = 1) GENERATE
gac: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
gad: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
cc <= alunode & expbaseff(4+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed+doublespeed)(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
bbman <= bb(77 DOWNTO 14);
ccman <= alunode;
END rtl;
|
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP2X.VHD ***
--*** ***
--*** Function: Double Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp2x IS
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp2x;
ARCHITECTURE rtl OF hcc_alufp2x IS
type expbasefftype IS ARRAY (3+shiftspeed+doublespeed DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type manfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal manleftff, manrightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manleftdelff, manleftdeldelff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manalignff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expbaseff : expbasefftype;
signal expshiftff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal subexpone, subexptwo : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed+doublespeed DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal alunode, aluff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (64 DOWNTO 1);
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
FOR j IN 1 TO 3+shiftspeed+doublespeed LOOP
expbaseff(j)(k) <= '0';
END LOOP;
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed+doublespeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO 64 LOOP
manleftff(k) <= (aaff(k+13) AND NOT(switch)) OR (bbff(k+13) AND switch);
manrightff(k) <= (bbff(k+13) AND NOT(switch)) OR (aaff(k+13) AND switch);
END LOOP;
FOR k IN 1 TO 13 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
expbaseff(k)(13 DOWNTO 1) <= expbaseff(k-1)(13 DOWNTO 1); -- level 3 to 4/5/6
END LOOP;
FOR k IN 1 TO 13 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
-- once through add/sub, output can only be ieee754"0" if both inputs are ieee754"0"
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
ccsatff(k) <= ccsatff(k-1); -- level 3 to 4/5/6
cczipff(k) <= cczipff(k-1); -- level 3 to 4/5/6
END LOOP;
END IF;
END IF;
END PROCESS;
subexpone <= aaff(13 DOWNTO 1) - bbff(13 DOWNTO 1);
subexptwo <= bbff(13 DOWNTO 1) - aaff(13 DOWNTO 1);
switch <= subexpone(13);
expzerochk <= expshiftff - "0000001000000"; -- 63 ok, 64 not
gsa: IF (shiftspeed = 0) GENERATE
sftslow: hcc_rsftcomb64
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= manleftff(k) XOR invertleftff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightff) AND expzerochk(13);
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdelff;
alurightnode <= manalignff;
END GENERATE;
gsb: IF (shiftspeed = 1) GENERATE
sftfast: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manleftdeldelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
manleftdelff <= manleftff;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(13);
--*** LEVEL 4 ***
FOR k IN 1 TO 64 LOOP
manleftdeldelff(k) <= manleftdelff(k) XOR invertleftdelff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightdelff) AND expzerochkff;
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdeldelff;
alurightnode <= manalignff;
END GENERATE;
gaa: IF (doublespeed = 0) GENERATE
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aluleftnode + alurightnode + addsubff(3+shiftspeed);
END IF;
END IF;
END PROCESS;
alunode <= aluff;
--*** OUTPUTS ***
cc <= alunode & expbaseff(3+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
END GENERATE;
gab: IF (doublespeed = 1) GENERATE
gac: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
gad: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
cc <= alunode & expbaseff(4+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed+doublespeed)(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
bbman <= bb(77 DOWNTO 14);
ccman <= alunode;
END rtl;
|
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP2X.VHD ***
--*** ***
--*** Function: Double Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp2x IS
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp2x;
ARCHITECTURE rtl OF hcc_alufp2x IS
type expbasefftype IS ARRAY (3+shiftspeed+doublespeed DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type manfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal manleftff, manrightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manleftdelff, manleftdeldelff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manalignff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expbaseff : expbasefftype;
signal expshiftff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal subexpone, subexptwo : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed+doublespeed DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal alunode, aluff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (64 DOWNTO 1);
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
FOR j IN 1 TO 3+shiftspeed+doublespeed LOOP
expbaseff(j)(k) <= '0';
END LOOP;
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed+doublespeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO 64 LOOP
manleftff(k) <= (aaff(k+13) AND NOT(switch)) OR (bbff(k+13) AND switch);
manrightff(k) <= (bbff(k+13) AND NOT(switch)) OR (aaff(k+13) AND switch);
END LOOP;
FOR k IN 1 TO 13 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
expbaseff(k)(13 DOWNTO 1) <= expbaseff(k-1)(13 DOWNTO 1); -- level 3 to 4/5/6
END LOOP;
FOR k IN 1 TO 13 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
-- once through add/sub, output can only be ieee754"0" if both inputs are ieee754"0"
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
ccsatff(k) <= ccsatff(k-1); -- level 3 to 4/5/6
cczipff(k) <= cczipff(k-1); -- level 3 to 4/5/6
END LOOP;
END IF;
END IF;
END PROCESS;
subexpone <= aaff(13 DOWNTO 1) - bbff(13 DOWNTO 1);
subexptwo <= bbff(13 DOWNTO 1) - aaff(13 DOWNTO 1);
switch <= subexpone(13);
expzerochk <= expshiftff - "0000001000000"; -- 63 ok, 64 not
gsa: IF (shiftspeed = 0) GENERATE
sftslow: hcc_rsftcomb64
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= manleftff(k) XOR invertleftff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightff) AND expzerochk(13);
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdelff;
alurightnode <= manalignff;
END GENERATE;
gsb: IF (shiftspeed = 1) GENERATE
sftfast: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manleftdeldelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
manleftdelff <= manleftff;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(13);
--*** LEVEL 4 ***
FOR k IN 1 TO 64 LOOP
manleftdeldelff(k) <= manleftdelff(k) XOR invertleftdelff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightdelff) AND expzerochkff;
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdeldelff;
alurightnode <= manalignff;
END GENERATE;
gaa: IF (doublespeed = 0) GENERATE
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aluleftnode + alurightnode + addsubff(3+shiftspeed);
END IF;
END IF;
END PROCESS;
alunode <= aluff;
--*** OUTPUTS ***
cc <= alunode & expbaseff(3+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
END GENERATE;
gab: IF (doublespeed = 1) GENERATE
gac: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
gad: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
cc <= alunode & expbaseff(4+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed+doublespeed)(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
bbman <= bb(77 DOWNTO 14);
ccman <= alunode;
END rtl;
|
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP2X.VHD ***
--*** ***
--*** Function: Double Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp2x IS
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp2x;
ARCHITECTURE rtl OF hcc_alufp2x IS
type expbasefftype IS ARRAY (3+shiftspeed+doublespeed DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type manfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal manleftff, manrightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manleftdelff, manleftdeldelff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manalignff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expbaseff : expbasefftype;
signal expshiftff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal subexpone, subexptwo : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed+doublespeed DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal alunode, aluff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (64 DOWNTO 1);
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
FOR j IN 1 TO 3+shiftspeed+doublespeed LOOP
expbaseff(j)(k) <= '0';
END LOOP;
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed+doublespeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO 64 LOOP
manleftff(k) <= (aaff(k+13) AND NOT(switch)) OR (bbff(k+13) AND switch);
manrightff(k) <= (bbff(k+13) AND NOT(switch)) OR (aaff(k+13) AND switch);
END LOOP;
FOR k IN 1 TO 13 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
expbaseff(k)(13 DOWNTO 1) <= expbaseff(k-1)(13 DOWNTO 1); -- level 3 to 4/5/6
END LOOP;
FOR k IN 1 TO 13 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
-- once through add/sub, output can only be ieee754"0" if both inputs are ieee754"0"
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
ccsatff(k) <= ccsatff(k-1); -- level 3 to 4/5/6
cczipff(k) <= cczipff(k-1); -- level 3 to 4/5/6
END LOOP;
END IF;
END IF;
END PROCESS;
subexpone <= aaff(13 DOWNTO 1) - bbff(13 DOWNTO 1);
subexptwo <= bbff(13 DOWNTO 1) - aaff(13 DOWNTO 1);
switch <= subexpone(13);
expzerochk <= expshiftff - "0000001000000"; -- 63 ok, 64 not
gsa: IF (shiftspeed = 0) GENERATE
sftslow: hcc_rsftcomb64
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= manleftff(k) XOR invertleftff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightff) AND expzerochk(13);
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdelff;
alurightnode <= manalignff;
END GENERATE;
gsb: IF (shiftspeed = 1) GENERATE
sftfast: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manleftdeldelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
manleftdelff <= manleftff;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(13);
--*** LEVEL 4 ***
FOR k IN 1 TO 64 LOOP
manleftdeldelff(k) <= manleftdelff(k) XOR invertleftdelff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightdelff) AND expzerochkff;
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdeldelff;
alurightnode <= manalignff;
END GENERATE;
gaa: IF (doublespeed = 0) GENERATE
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aluleftnode + alurightnode + addsubff(3+shiftspeed);
END IF;
END IF;
END PROCESS;
alunode <= aluff;
--*** OUTPUTS ***
cc <= alunode & expbaseff(3+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
END GENERATE;
gab: IF (doublespeed = 1) GENERATE
gac: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
gad: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
cc <= alunode & expbaseff(4+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed+doublespeed)(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
bbman <= bb(77 DOWNTO 14);
ccman <= alunode;
END rtl;
|
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP2X.VHD ***
--*** ***
--*** Function: Double Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp2x IS
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp2x;
ARCHITECTURE rtl OF hcc_alufp2x IS
type expbasefftype IS ARRAY (3+shiftspeed+doublespeed DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type manfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal manleftff, manrightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manleftdelff, manleftdeldelff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manalignff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expbaseff : expbasefftype;
signal expshiftff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal subexpone, subexptwo : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed+doublespeed DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal alunode, aluff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (64 DOWNTO 1);
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
FOR j IN 1 TO 3+shiftspeed+doublespeed LOOP
expbaseff(j)(k) <= '0';
END LOOP;
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed+doublespeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO 64 LOOP
manleftff(k) <= (aaff(k+13) AND NOT(switch)) OR (bbff(k+13) AND switch);
manrightff(k) <= (bbff(k+13) AND NOT(switch)) OR (aaff(k+13) AND switch);
END LOOP;
FOR k IN 1 TO 13 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
expbaseff(k)(13 DOWNTO 1) <= expbaseff(k-1)(13 DOWNTO 1); -- level 3 to 4/5/6
END LOOP;
FOR k IN 1 TO 13 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
-- once through add/sub, output can only be ieee754"0" if both inputs are ieee754"0"
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
ccsatff(k) <= ccsatff(k-1); -- level 3 to 4/5/6
cczipff(k) <= cczipff(k-1); -- level 3 to 4/5/6
END LOOP;
END IF;
END IF;
END PROCESS;
subexpone <= aaff(13 DOWNTO 1) - bbff(13 DOWNTO 1);
subexptwo <= bbff(13 DOWNTO 1) - aaff(13 DOWNTO 1);
switch <= subexpone(13);
expzerochk <= expshiftff - "0000001000000"; -- 63 ok, 64 not
gsa: IF (shiftspeed = 0) GENERATE
sftslow: hcc_rsftcomb64
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= manleftff(k) XOR invertleftff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightff) AND expzerochk(13);
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdelff;
alurightnode <= manalignff;
END GENERATE;
gsb: IF (shiftspeed = 1) GENERATE
sftfast: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manleftdeldelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
manleftdelff <= manleftff;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(13);
--*** LEVEL 4 ***
FOR k IN 1 TO 64 LOOP
manleftdeldelff(k) <= manleftdelff(k) XOR invertleftdelff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightdelff) AND expzerochkff;
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdeldelff;
alurightnode <= manalignff;
END GENERATE;
gaa: IF (doublespeed = 0) GENERATE
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aluleftnode + alurightnode + addsubff(3+shiftspeed);
END IF;
END IF;
END PROCESS;
alunode <= aluff;
--*** OUTPUTS ***
cc <= alunode & expbaseff(3+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
END GENERATE;
gab: IF (doublespeed = 1) GENERATE
gac: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
gad: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
cc <= alunode & expbaseff(4+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed+doublespeed)(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
bbman <= bb(77 DOWNTO 14);
ccman <= alunode;
END rtl;
|
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP2X.VHD ***
--*** ***
--*** Function: Double Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp2x IS
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp2x;
ARCHITECTURE rtl OF hcc_alufp2x IS
type expbasefftype IS ARRAY (3+shiftspeed+doublespeed DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type manfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal manleftff, manrightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manleftdelff, manleftdeldelff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manalignff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expbaseff : expbasefftype;
signal expshiftff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal subexpone, subexptwo : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed+doublespeed DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal alunode, aluff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (64 DOWNTO 1);
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
FOR j IN 1 TO 3+shiftspeed+doublespeed LOOP
expbaseff(j)(k) <= '0';
END LOOP;
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed+doublespeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO 64 LOOP
manleftff(k) <= (aaff(k+13) AND NOT(switch)) OR (bbff(k+13) AND switch);
manrightff(k) <= (bbff(k+13) AND NOT(switch)) OR (aaff(k+13) AND switch);
END LOOP;
FOR k IN 1 TO 13 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
expbaseff(k)(13 DOWNTO 1) <= expbaseff(k-1)(13 DOWNTO 1); -- level 3 to 4/5/6
END LOOP;
FOR k IN 1 TO 13 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
-- once through add/sub, output can only be ieee754"0" if both inputs are ieee754"0"
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
ccsatff(k) <= ccsatff(k-1); -- level 3 to 4/5/6
cczipff(k) <= cczipff(k-1); -- level 3 to 4/5/6
END LOOP;
END IF;
END IF;
END PROCESS;
subexpone <= aaff(13 DOWNTO 1) - bbff(13 DOWNTO 1);
subexptwo <= bbff(13 DOWNTO 1) - aaff(13 DOWNTO 1);
switch <= subexpone(13);
expzerochk <= expshiftff - "0000001000000"; -- 63 ok, 64 not
gsa: IF (shiftspeed = 0) GENERATE
sftslow: hcc_rsftcomb64
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= manleftff(k) XOR invertleftff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightff) AND expzerochk(13);
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdelff;
alurightnode <= manalignff;
END GENERATE;
gsb: IF (shiftspeed = 1) GENERATE
sftfast: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manleftdeldelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
manleftdelff <= manleftff;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(13);
--*** LEVEL 4 ***
FOR k IN 1 TO 64 LOOP
manleftdeldelff(k) <= manleftdelff(k) XOR invertleftdelff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightdelff) AND expzerochkff;
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdeldelff;
alurightnode <= manalignff;
END GENERATE;
gaa: IF (doublespeed = 0) GENERATE
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aluleftnode + alurightnode + addsubff(3+shiftspeed);
END IF;
END IF;
END PROCESS;
alunode <= aluff;
--*** OUTPUTS ***
cc <= alunode & expbaseff(3+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
END GENERATE;
gab: IF (doublespeed = 1) GENERATE
gac: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
gad: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
cc <= alunode & expbaseff(4+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed+doublespeed)(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
bbman <= bb(77 DOWNTO 14);
ccman <= alunode;
END rtl;
|
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP2X.VHD ***
--*** ***
--*** Function: Double Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp2x IS
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp2x;
ARCHITECTURE rtl OF hcc_alufp2x IS
type expbasefftype IS ARRAY (3+shiftspeed+doublespeed DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type manfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal manleftff, manrightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manleftdelff, manleftdeldelff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manalignff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expbaseff : expbasefftype;
signal expshiftff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal subexpone, subexptwo : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed+doublespeed DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal alunode, aluff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (64 DOWNTO 1);
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
FOR j IN 1 TO 3+shiftspeed+doublespeed LOOP
expbaseff(j)(k) <= '0';
END LOOP;
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed+doublespeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO 64 LOOP
manleftff(k) <= (aaff(k+13) AND NOT(switch)) OR (bbff(k+13) AND switch);
manrightff(k) <= (bbff(k+13) AND NOT(switch)) OR (aaff(k+13) AND switch);
END LOOP;
FOR k IN 1 TO 13 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
expbaseff(k)(13 DOWNTO 1) <= expbaseff(k-1)(13 DOWNTO 1); -- level 3 to 4/5/6
END LOOP;
FOR k IN 1 TO 13 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
-- once through add/sub, output can only be ieee754"0" if both inputs are ieee754"0"
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
ccsatff(k) <= ccsatff(k-1); -- level 3 to 4/5/6
cczipff(k) <= cczipff(k-1); -- level 3 to 4/5/6
END LOOP;
END IF;
END IF;
END PROCESS;
subexpone <= aaff(13 DOWNTO 1) - bbff(13 DOWNTO 1);
subexptwo <= bbff(13 DOWNTO 1) - aaff(13 DOWNTO 1);
switch <= subexpone(13);
expzerochk <= expshiftff - "0000001000000"; -- 63 ok, 64 not
gsa: IF (shiftspeed = 0) GENERATE
sftslow: hcc_rsftcomb64
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= manleftff(k) XOR invertleftff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightff) AND expzerochk(13);
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdelff;
alurightnode <= manalignff;
END GENERATE;
gsb: IF (shiftspeed = 1) GENERATE
sftfast: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manleftdeldelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
manleftdelff <= manleftff;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(13);
--*** LEVEL 4 ***
FOR k IN 1 TO 64 LOOP
manleftdeldelff(k) <= manleftdelff(k) XOR invertleftdelff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightdelff) AND expzerochkff;
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdeldelff;
alurightnode <= manalignff;
END GENERATE;
gaa: IF (doublespeed = 0) GENERATE
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aluleftnode + alurightnode + addsubff(3+shiftspeed);
END IF;
END IF;
END PROCESS;
alunode <= aluff;
--*** OUTPUTS ***
cc <= alunode & expbaseff(3+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
END GENERATE;
gab: IF (doublespeed = 1) GENERATE
gac: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
gad: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
cc <= alunode & expbaseff(4+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed+doublespeed)(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
bbman <= bb(77 DOWNTO 14);
ccman <= alunode;
END rtl;
|
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP2X.VHD ***
--*** ***
--*** Function: Double Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp2x IS
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp2x;
ARCHITECTURE rtl OF hcc_alufp2x IS
type expbasefftype IS ARRAY (3+shiftspeed+doublespeed DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type manfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal manleftff, manrightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manleftdelff, manleftdeldelff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manalignff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expbaseff : expbasefftype;
signal expshiftff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal subexpone, subexptwo : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed+doublespeed DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal alunode, aluff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (64 DOWNTO 1);
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
FOR j IN 1 TO 3+shiftspeed+doublespeed LOOP
expbaseff(j)(k) <= '0';
END LOOP;
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed+doublespeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO 64 LOOP
manleftff(k) <= (aaff(k+13) AND NOT(switch)) OR (bbff(k+13) AND switch);
manrightff(k) <= (bbff(k+13) AND NOT(switch)) OR (aaff(k+13) AND switch);
END LOOP;
FOR k IN 1 TO 13 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
expbaseff(k)(13 DOWNTO 1) <= expbaseff(k-1)(13 DOWNTO 1); -- level 3 to 4/5/6
END LOOP;
FOR k IN 1 TO 13 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
-- once through add/sub, output can only be ieee754"0" if both inputs are ieee754"0"
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
ccsatff(k) <= ccsatff(k-1); -- level 3 to 4/5/6
cczipff(k) <= cczipff(k-1); -- level 3 to 4/5/6
END LOOP;
END IF;
END IF;
END PROCESS;
subexpone <= aaff(13 DOWNTO 1) - bbff(13 DOWNTO 1);
subexptwo <= bbff(13 DOWNTO 1) - aaff(13 DOWNTO 1);
switch <= subexpone(13);
expzerochk <= expshiftff - "0000001000000"; -- 63 ok, 64 not
gsa: IF (shiftspeed = 0) GENERATE
sftslow: hcc_rsftcomb64
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= manleftff(k) XOR invertleftff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightff) AND expzerochk(13);
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdelff;
alurightnode <= manalignff;
END GENERATE;
gsb: IF (shiftspeed = 1) GENERATE
sftfast: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manleftdeldelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
manleftdelff <= manleftff;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(13);
--*** LEVEL 4 ***
FOR k IN 1 TO 64 LOOP
manleftdeldelff(k) <= manleftdelff(k) XOR invertleftdelff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightdelff) AND expzerochkff;
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdeldelff;
alurightnode <= manalignff;
END GENERATE;
gaa: IF (doublespeed = 0) GENERATE
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aluleftnode + alurightnode + addsubff(3+shiftspeed);
END IF;
END IF;
END PROCESS;
alunode <= aluff;
--*** OUTPUTS ***
cc <= alunode & expbaseff(3+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
END GENERATE;
gab: IF (doublespeed = 1) GENERATE
gac: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
gad: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
cc <= alunode & expbaseff(4+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed+doublespeed)(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
bbman <= bb(77 DOWNTO 14);
ccman <= alunode;
END rtl;
|
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP2X.VHD ***
--*** ***
--*** Function: Double Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp2x IS
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp2x;
ARCHITECTURE rtl OF hcc_alufp2x IS
type expbasefftype IS ARRAY (3+shiftspeed+doublespeed DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type manfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal manleftff, manrightff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manleftdelff, manleftdeldelff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal manalignff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal expbaseff : expbasefftype;
signal expshiftff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal subexpone, subexptwo : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed+doublespeed DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal alunode, aluff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (64 DOWNTO 1);
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
FOR j IN 1 TO 3+shiftspeed+doublespeed LOOP
expbaseff(j)(k) <= '0';
END LOOP;
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed+doublespeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO 64 LOOP
manleftff(k) <= (aaff(k+13) AND NOT(switch)) OR (bbff(k+13) AND switch);
manrightff(k) <= (bbff(k+13) AND NOT(switch)) OR (aaff(k+13) AND switch);
END LOOP;
FOR k IN 1 TO 13 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
expbaseff(k)(13 DOWNTO 1) <= expbaseff(k-1)(13 DOWNTO 1); -- level 3 to 4/5/6
END LOOP;
FOR k IN 1 TO 13 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
-- once through add/sub, output can only be ieee754"0" if both inputs are ieee754"0"
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO (3+shiftspeed+doublespeed) LOOP
ccsatff(k) <= ccsatff(k-1); -- level 3 to 4/5/6
cczipff(k) <= cczipff(k-1); -- level 3 to 4/5/6
END LOOP;
END IF;
END IF;
END PROCESS;
subexpone <= aaff(13 DOWNTO 1) - bbff(13 DOWNTO 1);
subexptwo <= bbff(13 DOWNTO 1) - aaff(13 DOWNTO 1);
switch <= subexpone(13);
expzerochk <= expshiftff - "0000001000000"; -- 63 ok, 64 not
gsa: IF (shiftspeed = 0) GENERATE
sftslow: hcc_rsftcomb64
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= manleftff(k) XOR invertleftff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightff) AND expzerochk(13);
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdelff;
alurightnode <= manalignff;
END GENERATE;
gsb: IF (shiftspeed = 1) GENERATE
sftfast: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
manleftdelff(k) <= '0';
manleftdeldelff(k) <= '0';
manalignff(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 3 ***
manleftdelff <= manleftff;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(13);
--*** LEVEL 4 ***
FOR k IN 1 TO 64 LOOP
manleftdeldelff(k) <= manleftdelff(k) XOR invertleftdelff;
manalignff(k) <= (shiftbusnode(k) XOR invertrightdelff) AND expzerochkff;
END LOOP;
END IF;
END IF;
END PROCESS;
aluleftnode <= manleftdeldelff;
alurightnode <= manalignff;
END GENERATE;
gaa: IF (doublespeed = 0) GENERATE
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aluff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluff <= aluleftnode + alurightnode + addsubff(3+shiftspeed);
END IF;
END IF;
END PROCESS;
alunode <= aluff;
--*** OUTPUTS ***
cc <= alunode & expbaseff(3+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
END GENERATE;
gab: IF (doublespeed = 1) GENERATE
gac: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
gad: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aluleftnode,bb=>alurightnode,carryin=>addsubff(3+shiftspeed),
cc=>alunode);
END GENERATE;
cc <= alunode & expbaseff(4+shiftspeed)(13 DOWNTO 1);
ccsat <= ccsatff(4+shiftspeed);
cczip <= cczipff(4+shiftspeed);
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed+doublespeed)(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
bbman <= bb(77 DOWNTO 14);
ccman <= alunode;
END rtl;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "ir_rx_module"
-- Project :
-------------------------------------------------------------------------------
-- File : ir_rx_module_tb.vhd
-- Author : strongly-typed
-- Created : 2012-04-15
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.adc_ltc2351_pkg.all;
use work.ir_rx_module_pkg.all;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity ir_rx_module_tb is
end ir_rx_module_tb;
-------------------------------------------------------------------------------
architecture tb of ir_rx_module_tb is
-- component generics
constant BASE_ADDRESS_RESULTS : integer := 16#0800#;
constant BASE_ADDRESS_COEFS : integer := 16#0010#;
constant BASE_ADDRESS_TIMESTAMP : integer := 16#0100#;
-- component ports
signal adc_out_p : ir_rx_module_spi_out_type;
signal adc_in_p : ir_rx_module_spi_in_type := (others => (others => '0'));
signal sync_p : std_logic := '0';
signal bus_o : busdevice_out_type := (data => (others => '0'));
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal done_p : std_logic := '0';
signal ack_p : std_logic := '0';
signal clk_sample_en : std_logic := '0';
signal adc_values_test : std_logic_vector(13 downto 0) := (others => '0');
signal adc_values_test_signed : signed(13 downto 0) := (others => '0');
signal offset : signed(13 downto 0) := "10000000000000";
signal timestamp_s : timestamp_type := (others => '0');
-- clock
signal clk : std_logic := '1';
begin -- tb
ir_rx_module_1 : entity work.ir_rx_module
generic map (
BASE_ADDRESS_COEFS => BASE_ADDRESS_COEFS,
BASE_ADDRESS_RESULTS => BASE_ADDRESS_RESULTS,
BASE_ADDRESS_TIMESTAMP => BASE_ADDRESS_TIMESTAMP)
port map (
adc_o_p => adc_out_p,
adc_i_p => adc_in_p,
adc_values_o_p => open,
sync_o_p => sync_p,
bus_o_p => bus_o,
bus_i_p => bus_i,
done_o_p => done_p,
ack_i_p => ack_p,
clk_sample_en_i_p => clk_sample_en,
timestamp_i_p => timestamp_s,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
wait until clk = '1';
clk_sample_en <= '1';
wait until clk = '1';
-- do not repeat
wait;
end process WaveGen_Proc;
adc_values_test_signed <= signed(adc_values_test) - offset;
adc_proc : process
begin -- process adc_proc
wait until clk = '1';
adc_values_test <= "00000000000000";
wait until clk = '1';
adc_values_test <= "11111111111111";
wait until clk = '1';
adc_values_test <= "01111111111111";
wait until clk = '1';
adc_values_test <= "10000000000000";
-- do not repeat
wait;
end process adc_proc;
ack_proc : process
begin -- process ack_proc
ack_p <= '0';
wait for 90 us;
ack_p <= '1';
wait for 5 us;
ack_p <= '0';
end process ack_proc;
end tb;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "ir_rx_module"
-- Project :
-------------------------------------------------------------------------------
-- File : ir_rx_module_tb.vhd
-- Author : strongly-typed
-- Created : 2012-04-15
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.adc_ltc2351_pkg.all;
use work.ir_rx_module_pkg.all;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity ir_rx_module_tb is
end ir_rx_module_tb;
-------------------------------------------------------------------------------
architecture tb of ir_rx_module_tb is
-- component generics
constant BASE_ADDRESS_RESULTS : integer := 16#0800#;
constant BASE_ADDRESS_COEFS : integer := 16#0010#;
constant BASE_ADDRESS_TIMESTAMP : integer := 16#0100#;
-- component ports
signal adc_out_p : ir_rx_module_spi_out_type;
signal adc_in_p : ir_rx_module_spi_in_type := (others => (others => '0'));
signal sync_p : std_logic := '0';
signal bus_o : busdevice_out_type := (data => (others => '0'));
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal done_p : std_logic := '0';
signal ack_p : std_logic := '0';
signal clk_sample_en : std_logic := '0';
signal adc_values_test : std_logic_vector(13 downto 0) := (others => '0');
signal adc_values_test_signed : signed(13 downto 0) := (others => '0');
signal offset : signed(13 downto 0) := "10000000000000";
signal timestamp_s : timestamp_type := (others => '0');
-- clock
signal clk : std_logic := '1';
begin -- tb
ir_rx_module_1 : entity work.ir_rx_module
generic map (
BASE_ADDRESS_COEFS => BASE_ADDRESS_COEFS,
BASE_ADDRESS_RESULTS => BASE_ADDRESS_RESULTS,
BASE_ADDRESS_TIMESTAMP => BASE_ADDRESS_TIMESTAMP)
port map (
adc_o_p => adc_out_p,
adc_i_p => adc_in_p,
adc_values_o_p => open,
sync_o_p => sync_p,
bus_o_p => bus_o,
bus_i_p => bus_i,
done_o_p => done_p,
ack_i_p => ack_p,
clk_sample_en_i_p => clk_sample_en,
timestamp_i_p => timestamp_s,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
wait until clk = '1';
clk_sample_en <= '1';
wait until clk = '1';
-- do not repeat
wait;
end process WaveGen_Proc;
adc_values_test_signed <= signed(adc_values_test) - offset;
adc_proc : process
begin -- process adc_proc
wait until clk = '1';
adc_values_test <= "00000000000000";
wait until clk = '1';
adc_values_test <= "11111111111111";
wait until clk = '1';
adc_values_test <= "01111111111111";
wait until clk = '1';
adc_values_test <= "10000000000000";
-- do not repeat
wait;
end process adc_proc;
ack_proc : process
begin -- process ack_proc
ack_p <= '0';
wait for 90 us;
ack_p <= '1';
wait for 5 us;
ack_p <= '0';
end process ack_proc;
end tb;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use WORK.useful_functions_pkg.all;
entity regfile is
generic (
NWP : integer := 1;
NRP : integer := 2;
AW : integer := 10;
DW : integer := 16
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
we_v : in std_logic_vector(NWP-1 downto 0);
re_v : in std_logic_vector(NRP-1 downto 0);
waddr_v : in std_logic_vector(NWP*AW-1 downto 0);
raddr_v : in std_logic_vector(NRP*AW-1 downto 0);
input_data_v : in std_logic_vector(NWP*DW-1 downto 0);
ram_output_v : out std_logic_vector(NRP*DW-1 downto 0)
);
end regfile;
architecture rtl of regfile is
component regfile_core
generic (
AW : integer := 5;
DW : integer := 32
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
we : in std_logic;
re : in std_logic;
waddr : in std_logic_vector(AW-1 downto 0);
raddr : in std_logic_vector(AW-1 downto 0);
input_data : in std_logic_vector(DW-1 downto 0);
ram_output : out std_logic_vector(DW-1 downto 0)
);
end component;
constant NREGS : integer := 2**AW;
type banksel_type is array (NRP-1 downto 0) of std_logic_vector(log2c(NWP)-1 downto 0);
signal ram_output_i : std_logic_vector((NRP*NWP*DW)-1 downto 0);
begin
nwp_nrp_bram_instance_0 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(0),
re => re_v(0),
waddr => waddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
raddr => raddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
input_data => input_data_v(DW*(0+1)-1 downto DW*0),
ram_output => ram_output_i(DW*((0*NRP+0)+1)-1 downto DW*(0*NRP+0))
);
nwp_nrp_bram_instance_1 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(0),
re => re_v(1),
waddr => waddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
raddr => raddr_v(AW*(1+1)-log2c(NWP)-1 downto AW*1),
input_data => input_data_v(DW*(0+1)-1 downto DW*0),
ram_output => ram_output_i(DW*((0*NRP+1)+1)-1 downto DW*(0*NRP+1))
);
ram_output_v(DW*(0+1)-1 downto DW*0) <= ram_output_i(DW*(0+1)-1 downto DW*0);
ram_output_v(DW*(1+1)-1 downto DW*1) <= ram_output_i(DW*(1+1)-1 downto DW*1);
end rtl;
|
-- arduinointerface.vhd
--
-- takes 8-bit parallel data and sends frame
-- Frame ends when data value is written with "rxLast" set.
-- connect data to low 4 bits of port
-- connect strb to b4 of port (configured as output)
-- connect RnW to b5 of port (configured as output)
-- to read this peripheral:
-- (assuming strb is left high between accesses)
-- set port low bits to input
-- set RmW, strb to 1, 0 (10 = command "read low-nibble")
-- read the value
-- set strb 1 (11 = command "read high-nibble)
-- read the value
-- for multi-byte reads, repeat last four steps
-- to write this peripheral:
-- (assuming strb is left high between accesses)
-- set RnW to 0 (strb no change, so no write yet; output buffers now disabled)
-- set port low bits to output
-- write the lo-nibble value, with b5, b4 = 00
-- write the hi-nibble value, with b5, b4 = 01
-- for multi-byte writes, repeat last two steps
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
-- debug libraries
use std.textio.all;
use ieee.std_logic_textio.all;
entity arduinointerface_tb is
end entity arduinointerface_tb;
architecture behavioural of arduinointerface_tb is
signal RnW : Std_Logic := '1';
signal strb : Std_Logic := '1';
signal clock: Std_Logic;
signal rst: Std_Logic :='1';
signal bidir : Std_Logic_Vector (3 downto 0) := "ZZZZ"; -- the databus
signal rd, wr: Std_Logic;
signal q, i : Std_Logic_Vector (7 downto 0) := x"A5"; -- i is the values read on input, q is values output by write
signal cycle : integer :=0;
component arduinointerface is
port (
-- arduino pins
data: inout Std_Logic_Vector (3 downto 0);
strb: in Std_Logic;
RnW: in Std_Logic;
clk: in Std_Logic;
rst: in Std_Logic;
-- io pins
rd, wr: out Std_Logic;
q: out Std_Logic_Vector (7 downto 0);
i: in Std_Logic_Vector (7 downto 0)
);
end component arduinointerface;
subtype nibble is Std_Logic_Vector(3 downto 0);
type tDataItem is record
d: nibble;
RnW, strb: Std_Logic;
end record tDataItem;
type tDataList is array (0 to 5) of tDataItem;
constant dataList : tDataList := (
-- d, RnW, strb
-- read cycle
("ZZZZ", '1', '1'),
("ZZZZ", '1', '0'),
("ZZZZ", '1', '1'),
-- write cycle
("ZZZZ", '0', '1'),
("0001", '0', '0'),
("0010", '0', '1')
);
begin
iface : arduinointerface
port map (
data => bidir,
strb => strb,
RnW => RnW,
clk => clock,
rst => rst,
rd => rd,
wr => wr,
q => q,
i => i
);
rst <= '1' after 0 ns, '0' after 100 ns;
process
-- drive the txClock
begin
clock <= '0';
wait for 62 ns;
clock <= '1';
wait for 63 ns;
end process;
process (clock)
begin
if rising_edge(clock) then
cycle <= (cycle + 1) mod (10 * dataList'length);
if cycle = 0 then
i <= (i(0) & i(7 downto 1)) xor "0" & i(0) & "00" & i(0) & "0" & i(0) & "0";
end if;
if (cycle mod 10) = 0 then
bidir <= dataList(cycle/10).d;
RnW <= dataList(cycle/10).RnW;
strb <= dataList(cycle/10).strb;
end if;
end if;
end process;
end behavioural; |
architecture RTL of FIFO is
procedure proc1 is
begin
end procedure proc1;
procedure proc1 is
begin
end procedure;
procedure proc1 is
begin
end proc1;
procedure proc1 is
begin
end;
-- Fixes follow
procedure proc1 is
begin
end procedure proc1;
procedure proc1 is
begin
end procedure proc1;
procedure proc1 is
begin
end procedure proc1;
procedure proc1 is
begin
end procedure;
procedure proc1 is
begin
end proc1;
begin
end architecture RTL;
|
-- Version: v11.8 11.8.0.26
-- File used only for Simulation
library ieee;
use ieee.std_logic_1164.all;
library proasic3;
use proasic3.all;
entity CU_Main is
port( CLK : in std_logic;
BEACON_PWR : out std_logic;
CUTTER_EN : out std_logic;
LDO_FRONTEND_PWR : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
PR_OP_PWR : out std_logic;
STX_PWR : out std_logic;
V3_LINEAR_PWR : out std_logic
);
end CU_Main;
architecture DEF_ARCH of CU_Main is
component DFN1
port( D : in std_logic := 'U';
CLK : in std_logic := 'U';
Q : out std_logic
);
end component;
component XOR2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component DFN0
port( D : in std_logic := 'U';
CLK : in std_logic := 'U';
Q : out std_logic
);
end component;
component NOR3C
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component OR2A
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component OR3B
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component CLKINT
port( A : in std_logic := 'U';
Y : out std_logic
);
end component;
component AX1C
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component AND3
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component IOTRI_OB_EB
port( D : in std_logic := 'U';
E : in std_logic := 'U';
DOUT : out std_logic;
EOUT : out std_logic
);
end component;
component INV
port( A : in std_logic := 'U';
Y : out std_logic
);
end component;
component DFN0E0
port( D : in std_logic := 'U';
CLK : in std_logic := 'U';
E : in std_logic := 'U';
Q : out std_logic
);
end component;
component AOI1B
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component DFN0E1
port( D : in std_logic := 'U';
CLK : in std_logic := 'U';
E : in std_logic := 'U';
Q : out std_logic
);
end component;
component AX1
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component NOR2A
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component NOR2B
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component IOPAD_TRI
port( D : in std_logic := 'U';
E : in std_logic := 'U';
PAD : out std_logic
);
end component;
component OR3C
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component IOIN_IB
port( YIN : in std_logic := 'U';
Y : out std_logic
);
end component;
component XNOR2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component IOPAD_IN
port( PAD : in std_logic := 'U';
Y : out std_logic
);
end component;
component AND2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component GND
port(Y : out std_logic);
end component;
component VCC
port(Y : out std_logic);
end component;
signal CLKINT_0_Y, CLK_c, LED1_c, LED2_c,
\system_clock_0/s_time[1]_net_1\,
\system_clock_0/s_time[0]_net_1\,
\system_clock_0/s_time[3]_net_1\,
\system_clock_0/DWACT_FINC_E[0]\,
\system_clock_0/m_time_i[11]\,
\system_clock_0/m_time[11]\,
\system_clock_0/m_time_i[12]\,
\system_clock_0/m_time[12]\,
\system_clock_0/m_time_i[13]\,
\system_clock_0/m_time[13]\,
\system_clock_0/m_time_i[14]\,
\system_clock_0/m_time[14]\,
\system_clock_0/m_time_i[15]\,
\system_clock_0/m_time[15]\,
\system_clock_0/m_time_i[16]\,
\system_clock_0/m_time[16]\,
\system_clock_0/m_time_i[17]\,
\system_clock_0/m_time[17]\, \system_clock_0/m_time_i[1]\,
\system_clock_0/m_time[1]\, \system_clock_0/m_time_i[7]\,
\system_clock_0/m_time[7]\, \system_clock_0/m_time_i[9]\,
\system_clock_0/m_time[9]\, \system_clock_0/m_time_i[10]\,
\system_clock_0/m_time[10]\, \system_clock_0/l_m6_0_a2_7\,
\system_clock_0/l_m6_0_a2_2\,
\system_clock_0/l_m6_0_a2_1\,
\system_clock_0/l_m6_0_a2_6\,
\system_clock_0/l_m6_0_a2_4\, \system_clock_0/m_time[8]\,
\system_clock_0/un14_flag_3\,
\system_clock_0/s_time[6]_net_1\,
\system_clock_0/un14_flag_1\,
\system_clock_0/un14_flag_2\,
\system_clock_0/s_time[4]_net_1\,
\system_clock_0/l_N_13_mux\, \system_clock_0/N_25\,
\system_clock_0/N_39_i\, \system_clock_0/N_23\,
\system_clock_0/m_time[6]\, \system_clock_0/N_38_i\,
\system_clock_0/N_21\, \system_clock_0/m_time[4]\,
\system_clock_0/m_time[5]\, \system_clock_0/N_37_i\,
\system_clock_0/N_36_i\, \system_clock_0/m_time[2]\,
\system_clock_0/m_time[3]\, \system_clock_0/N_35_i\,
\system_clock_0/l_time_RNO_0[16]_net_1\,
\system_clock_0/l_time_RNIUEA34[14]_net_1\,
\system_clock_0/l_time_RNIQEBK3[13]_net_1\,
\system_clock_0/l_time_RNINFC53[12]_net_1\,
\system_clock_0/l_time_RNILHDM2[11]_net_1\,
\system_clock_0/l_time_RNIKKE72[10]_net_1\,
\system_clock_0/N_27\, \system_clock_0/N_26\,
\system_clock_0/N_24\, \system_clock_0/l_time_n7\,
\system_clock_0/un14_l_time\,
\system_clock_0/s_time_3[7]\, \system_clock_0/I_20\,
\system_clock_0/s_time_3[6]\, \system_clock_0/I_17\,
\system_clock_0/s_time_3[5]\, \system_clock_0/I_14\,
\system_clock_0/s_time_3[4]\, \system_clock_0/I_12\,
\system_clock_0/s_time_3[3]\, \system_clock_0/I_9\,
\system_clock_0/s_time_3[2]\, \system_clock_0/I_7\,
\system_clock_0/s_time_3[1]\, \system_clock_0/I_5\,
\system_clock_0/flag_net_1\, \system_clock_0/I_4\,
\system_clock_0/s_time[2]_net_1\, \system_clock_0/N_2\,
\system_clock_0/DWACT_FINC_E[2]\, \system_clock_0/N_3\,
\system_clock_0/DWACT_FINC_E[1]\, \system_clock_0/N_4\,
\system_clock_0/N_6\, \STX_PWR_pad/U0/NET1\,
\STX_PWR_pad/U0/NET2\, \V3_LINEAR_PWR_pad/U0/NET1\,
\V3_LINEAR_PWR_pad/U0/NET2\, \LED2_pad/U0/NET1\,
\LED2_pad/U0/NET2\, \LDO_FRONTEND_PWR_pad/U0/NET1\,
\LDO_FRONTEND_PWR_pad/U0/NET2\, \PR_OP_PWR_pad/U0/NET1\,
\PR_OP_PWR_pad/U0/NET2\, \BEACON_PWR_pad/U0/NET1\,
\BEACON_PWR_pad/U0/NET2\, \LED1_pad/U0/NET1\,
\LED1_pad/U0/NET2\, \CUTTER_EN_pad/U0/NET1\,
\CUTTER_EN_pad/U0/NET2\, \VCC\, \CLK_pad/U0/NET1\, \GND\,
AFLSDF_VCC, AFLSDF_GND : std_logic;
signal GND_power_net1 : std_logic;
signal VCC_power_net1 : std_logic;
begin
AFLSDF_GND <= GND_power_net1;
\GND\ <= GND_power_net1;
\VCC\ <= VCC_power_net1;
AFLSDF_VCC <= VCC_power_net1;
\system_clock_0/flag\ : DFN1
port map(D => \system_clock_0/un14_l_time\, CLK =>
CLKINT_0_Y, Q => \system_clock_0/flag_net_1\);
\system_clock_0/l_time_RNO[2]\ : XOR2
port map(A => \system_clock_0/m_time[1]\, B =>
\system_clock_0/m_time[2]\, Y => \system_clock_0/N_35_i\);
\system_clock_0/l_time[3]\ : DFN0
port map(D => \system_clock_0/N_36_i\, CLK => CLKINT_0_Y, Q
=> \system_clock_0/m_time[3]\);
\system_clock_0/l_time_RNINQEP1[9]\ : NOR3C
port map(A => \system_clock_0/m_time[9]\, B =>
\system_clock_0/m_time[10]\, C =>
\system_clock_0/l_m6_0_a2_4\, Y =>
\system_clock_0/l_m6_0_a2_6\);
\system_clock_0/l_time_RNIKKE72[10]\ : OR2A
port map(A => \system_clock_0/m_time[10]\, B =>
\system_clock_0/N_27\, Y =>
\system_clock_0/l_time_RNIKKE72[10]_net_1\);
\system_clock_0/l_time_RNIFSK51[6]\ : OR2A
port map(A => \system_clock_0/m_time[6]\, B =>
\system_clock_0/N_23\, Y => \system_clock_0/N_24\);
\system_clock_0/l_time_RNIQVBV[5]\ : OR3B
port map(A => \system_clock_0/m_time[4]\, B =>
\system_clock_0/m_time[5]\, C => \system_clock_0/N_21\, Y
=> \system_clock_0/N_23\);
CLKINT_0 : CLKINT
port map(A => CLK_c, Y => CLKINT_0_Y);
\system_clock_0/l_time_RNO[3]\ : AX1C
port map(A => \system_clock_0/m_time[2]\, B =>
\system_clock_0/m_time[1]\, C =>
\system_clock_0/m_time[3]\, Y => \system_clock_0/N_36_i\);
\system_clock_0/un1_s_time_I_18\ : AND3
port map(A => \system_clock_0/s_time[3]_net_1\, B =>
\system_clock_0/s_time[4]_net_1\, C => LED2_c, Y =>
\system_clock_0/DWACT_FINC_E[2]\);
\BEACON_PWR_pad/U0/U1\ : IOTRI_OB_EB
port map(D => \GND\, E => \VCC\, DOUT =>
\BEACON_PWR_pad/U0/NET1\, EOUT =>
\BEACON_PWR_pad/U0/NET2\);
\system_clock_0/un1_s_time_I_9\ : XOR2
port map(A => \system_clock_0/N_6\, B =>
\system_clock_0/s_time[3]_net_1\, Y =>
\system_clock_0/I_9\);
\system_clock_0/un1_s_time_I_14\ : XOR2
port map(A => \system_clock_0/N_4\, B => LED2_c, Y =>
\system_clock_0/I_14\);
\system_clock_0/l_time_RNO[11]\ : INV
port map(A => \system_clock_0/m_time[11]\, Y =>
\system_clock_0/m_time_i[11]\);
\system_clock_0/un1_s_time_I_8\ : AND3
port map(A => \system_clock_0/s_time[0]_net_1\, B =>
\system_clock_0/s_time[1]_net_1\, C =>
\system_clock_0/s_time[2]_net_1\, Y =>
\system_clock_0/N_6\);
\system_clock_0/l_time_RNIVU641[16]\ : NOR3C
port map(A => \system_clock_0/m_time[12]\, B =>
\system_clock_0/m_time[16]\, C =>
\system_clock_0/m_time[8]\, Y =>
\system_clock_0/l_m6_0_a2_4\);
\system_clock_0/l_time[9]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[9]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/N_26\, Q =>
\system_clock_0/m_time[9]\);
\system_clock_0/s_time_RNO[5]\ : AOI1B
port map(A => \system_clock_0/un14_flag_3\, B =>
\system_clock_0/un14_flag_2\, C => \system_clock_0/I_14\,
Y => \system_clock_0/s_time_3[5]\);
\system_clock_0/l_time_RNO[9]\ : INV
port map(A => \system_clock_0/m_time[9]\, Y =>
\system_clock_0/m_time_i[9]\);
\system_clock_0/l_time[7]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[7]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/N_24\, Q =>
\system_clock_0/m_time[7]\);
\system_clock_0/l_time[5]\ : DFN0
port map(D => \system_clock_0/N_38_i\, CLK => CLKINT_0_Y, Q
=> \system_clock_0/m_time[5]\);
\V3_LINEAR_PWR_pad/U0/U1\ : IOTRI_OB_EB
port map(D => \GND\, E => \VCC\, DOUT =>
\V3_LINEAR_PWR_pad/U0/NET1\, EOUT =>
\V3_LINEAR_PWR_pad/U0/NET2\);
\system_clock_0/l_time_RNO[12]\ : INV
port map(A => \system_clock_0/m_time[12]\, Y =>
\system_clock_0/m_time_i[12]\);
\system_clock_0/un1_s_time_I_5\ : XOR2
port map(A => \system_clock_0/s_time[0]_net_1\, B =>
\system_clock_0/s_time[1]_net_1\, Y =>
\system_clock_0/I_5\);
\system_clock_0/s_time[1]\ : DFN0E1
port map(D => \system_clock_0/s_time_3[1]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/flag_net_1\, Q =>
\system_clock_0/s_time[1]_net_1\);
\system_clock_0/l_time[12]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[12]\, CLK =>
CLKINT_0_Y, E =>
\system_clock_0/l_time_RNILHDM2[11]_net_1\, Q =>
\system_clock_0/m_time[12]\);
\system_clock_0/l_time_RNO[5]\ : AX1
port map(A => \system_clock_0/N_21\, B =>
\system_clock_0/m_time[4]\, C =>
\system_clock_0/m_time[5]\, Y => \system_clock_0/N_38_i\);
\system_clock_0/s_time[3]\ : DFN0E1
port map(D => \system_clock_0/s_time_3[3]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/flag_net_1\, Q =>
\system_clock_0/s_time[3]_net_1\);
\system_clock_0/l_time_RNI9I815[7]\ : NOR2A
port map(A => \system_clock_0/l_m6_0_a2_7\, B =>
\system_clock_0/N_25\, Y => \system_clock_0/l_N_13_mux\);
\system_clock_0/l_time_RNI91UT[14]\ : NOR2B
port map(A => \system_clock_0/m_time[15]\, B =>
\system_clock_0/m_time[14]\, Y =>
\system_clock_0/l_m6_0_a2_1\);
\system_clock_0/l_time[4]\ : DFN0
port map(D => \system_clock_0/N_37_i\, CLK => CLKINT_0_Y, Q
=> \system_clock_0/m_time[4]\);
\system_clock_0/un1_s_time_I_20\ : XOR2
port map(A => \system_clock_0/N_2\, B => LED1_c, Y =>
\system_clock_0/I_20\);
\V3_LINEAR_PWR_pad/U0/U0\ : IOPAD_TRI
port map(D => \V3_LINEAR_PWR_pad/U0/NET1\, E =>
\V3_LINEAR_PWR_pad/U0/NET2\, PAD => V3_LINEAR_PWR);
\system_clock_0/s_time_RNIF0T8[0]\ : NOR2B
port map(A => \system_clock_0/s_time[3]_net_1\, B =>
\system_clock_0/s_time[0]_net_1\, Y =>
\system_clock_0/un14_flag_2\);
\LED2_pad/U0/U1\ : IOTRI_OB_EB
port map(D => LED2_c, E => \VCC\, DOUT =>
\LED2_pad/U0/NET1\, EOUT => \LED2_pad/U0/NET2\);
\CUTTER_EN_pad/U0/U1\ : IOTRI_OB_EB
port map(D => \GND\, E => \VCC\, DOUT =>
\CUTTER_EN_pad/U0/NET1\, EOUT => \CUTTER_EN_pad/U0/NET2\);
\system_clock_0/l_time_RNIKOFO1[9]\ : OR2A
port map(A => \system_clock_0/m_time[9]\, B =>
\system_clock_0/N_26\, Y => \system_clock_0/N_27\);
\system_clock_0/l_time_RNIJ9QI[3]\ : OR3C
port map(A => \system_clock_0/m_time[2]\, B =>
\system_clock_0/m_time[1]\, C =>
\system_clock_0/m_time[3]\, Y => \system_clock_0/N_21\);
\system_clock_0/l_time_RNI4STT[11]\ : NOR2B
port map(A => \system_clock_0/m_time[13]\, B =>
\system_clock_0/m_time[11]\, Y =>
\system_clock_0/l_m6_0_a2_2\);
\system_clock_0/un1_s_time_I_4\ : INV
port map(A => \system_clock_0/s_time[0]_net_1\, Y =>
\system_clock_0/I_4\);
\CUTTER_EN_pad/U0/U0\ : IOPAD_TRI
port map(D => \CUTTER_EN_pad/U0/NET1\, E =>
\CUTTER_EN_pad/U0/NET2\, PAD => CUTTER_EN);
\LDO_FRONTEND_PWR_pad/U0/U0\ : IOPAD_TRI
port map(D => \LDO_FRONTEND_PWR_pad/U0/NET1\, E =>
\LDO_FRONTEND_PWR_pad/U0/NET2\, PAD => LDO_FRONTEND_PWR);
\system_clock_0/un1_s_time_I_10\ : AND3
port map(A => \system_clock_0/s_time[0]_net_1\, B =>
\system_clock_0/s_time[1]_net_1\, C =>
\system_clock_0/s_time[2]_net_1\, Y =>
\system_clock_0/DWACT_FINC_E[0]\);
\system_clock_0/l_time_RNIQEBK3[13]\ : OR2A
port map(A => \system_clock_0/m_time[13]\, B =>
\system_clock_0/l_time_RNINFC53[12]_net_1\, Y =>
\system_clock_0/l_time_RNIQEBK3[13]_net_1\);
\system_clock_0/s_time_RNIL6T8[4]\ : NOR2B
port map(A => LED2_c, B => \system_clock_0/s_time[4]_net_1\,
Y => \system_clock_0/un14_flag_1\);
\LED1_pad/U0/U0\ : IOPAD_TRI
port map(D => \LED1_pad/U0/NET1\, E => \LED1_pad/U0/NET2\,
PAD => LED1);
\system_clock_0/l_time[10]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[10]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/N_27\, Q =>
\system_clock_0/m_time[10]\);
\system_clock_0/un1_s_time_I_7\ : AX1C
port map(A => \system_clock_0/s_time[1]_net_1\, B =>
\system_clock_0/s_time[0]_net_1\, C =>
\system_clock_0/s_time[2]_net_1\, Y =>
\system_clock_0/I_7\);
\system_clock_0/s_time[7]\ : DFN0E1
port map(D => \system_clock_0/s_time_3[7]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/flag_net_1\, Q => LED1_c);
\system_clock_0/s_time[5]\ : DFN0E1
port map(D => \system_clock_0/s_time_3[5]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/flag_net_1\, Q => LED2_c);
\BEACON_PWR_pad/U0/U0\ : IOPAD_TRI
port map(D => \BEACON_PWR_pad/U0/NET1\, E =>
\BEACON_PWR_pad/U0/NET2\, PAD => BEACON_PWR);
\system_clock_0/l_time[2]\ : DFN0
port map(D => \system_clock_0/N_35_i\, CLK => CLKINT_0_Y, Q
=> \system_clock_0/m_time[2]\);
\system_clock_0/l_time[13]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[13]\, CLK =>
CLKINT_0_Y, E =>
\system_clock_0/l_time_RNINFC53[12]_net_1\, Q =>
\system_clock_0/m_time[13]\);
\CLK_pad/U0/U1\ : IOIN_IB
port map(YIN => \CLK_pad/U0/NET1\, Y => CLK_c);
\system_clock_0/l_time_RNIUEA34[14]\ : OR2A
port map(A => \system_clock_0/m_time[14]\, B =>
\system_clock_0/l_time_RNIQEBK3[13]_net_1\, Y =>
\system_clock_0/l_time_RNIUEA34[14]_net_1\);
\system_clock_0/l_time[8]\ : DFN0
port map(D => \system_clock_0/l_time_n7\, CLK => CLKINT_0_Y,
Q => \system_clock_0/m_time[8]\);
\system_clock_0/l_time[17]\ : DFN0E1
port map(D => \system_clock_0/m_time_i[17]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/l_N_13_mux\, Q =>
\system_clock_0/m_time[17]\);
\LED1_pad/U0/U1\ : IOTRI_OB_EB
port map(D => LED1_c, E => \VCC\, DOUT =>
\LED1_pad/U0/NET1\, EOUT => \LED1_pad/U0/NET2\);
\system_clock_0/s_time_RNO[1]\ : AOI1B
port map(A => \system_clock_0/un14_flag_3\, B =>
\system_clock_0/un14_flag_2\, C => \system_clock_0/I_5\,
Y => \system_clock_0/s_time_3[1]\);
\system_clock_0/l_time_RNO[15]\ : INV
port map(A => \system_clock_0/m_time[15]\, Y =>
\system_clock_0/m_time_i[15]\);
\system_clock_0/s_time_RNO[6]\ : AOI1B
port map(A => \system_clock_0/un14_flag_3\, B =>
\system_clock_0/un14_flag_2\, C => \system_clock_0/I_17\,
Y => \system_clock_0/s_time_3[6]\);
\system_clock_0/s_time_RNO[4]\ : AOI1B
port map(A => \system_clock_0/un14_flag_3\, B =>
\system_clock_0/un14_flag_2\, C => \system_clock_0/I_12\,
Y => \system_clock_0/s_time_3[4]\);
\system_clock_0/s_time[4]\ : DFN0E1
port map(D => \system_clock_0/s_time_3[4]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/flag_net_1\, Q =>
\system_clock_0/s_time[4]_net_1\);
\system_clock_0/un1_s_time_I_12\ : AX1C
port map(A => \system_clock_0/s_time[3]_net_1\, B =>
\system_clock_0/DWACT_FINC_E[0]\, C =>
\system_clock_0/s_time[4]_net_1\, Y =>
\system_clock_0/I_12\);
\PR_OP_PWR_pad/U0/U1\ : IOTRI_OB_EB
port map(D => \GND\, E => \VCC\, DOUT =>
\PR_OP_PWR_pad/U0/NET1\, EOUT => \PR_OP_PWR_pad/U0/NET2\);
\system_clock_0/s_time_RNO[7]\ : AOI1B
port map(A => \system_clock_0/un14_flag_3\, B =>
\system_clock_0/un14_flag_2\, C => \system_clock_0/I_20\,
Y => \system_clock_0/s_time_3[7]\);
\system_clock_0/l_time_RNO[8]\ : XNOR2
port map(A => \system_clock_0/m_time[8]\, B =>
\system_clock_0/N_25\, Y => \system_clock_0/l_time_n7\);
\system_clock_0/l_time[6]\ : DFN0
port map(D => \system_clock_0/N_39_i\, CLK => CLKINT_0_Y, Q
=> \system_clock_0/m_time[6]\);
\system_clock_0/l_time[11]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[11]\, CLK =>
CLKINT_0_Y, E =>
\system_clock_0/l_time_RNIKKE72[10]_net_1\, Q =>
\system_clock_0/m_time[11]\);
\LDO_FRONTEND_PWR_pad/U0/U1\ : IOTRI_OB_EB
port map(D => \GND\, E => \VCC\, DOUT =>
\LDO_FRONTEND_PWR_pad/U0/NET1\, EOUT =>
\LDO_FRONTEND_PWR_pad/U0/NET2\);
\system_clock_0/l_time_RNI5QTB1[7]\ : OR2A
port map(A => \system_clock_0/m_time[7]\, B =>
\system_clock_0/N_24\, Y => \system_clock_0/N_25\);
\PR_OP_PWR_pad/U0/U0\ : IOPAD_TRI
port map(D => \PR_OP_PWR_pad/U0/NET1\, E =>
\PR_OP_PWR_pad/U0/NET2\, PAD => PR_OP_PWR);
\system_clock_0/l_time_RNO[1]\ : INV
port map(A => \system_clock_0/m_time[1]\, Y =>
\system_clock_0/m_time_i[1]\);
\system_clock_0/l_time[15]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[15]\, CLK =>
CLKINT_0_Y, E =>
\system_clock_0/l_time_RNIUEA34[14]_net_1\, Q =>
\system_clock_0/m_time[15]\);
\system_clock_0/l_time_RNO[6]\ : XNOR2
port map(A => \system_clock_0/N_23\, B =>
\system_clock_0/m_time[6]\, Y => \system_clock_0/N_39_i\);
\system_clock_0/l_time_RNO[4]\ : XNOR2
port map(A => \system_clock_0/N_21\, B =>
\system_clock_0/m_time[4]\, Y => \system_clock_0/N_37_i\);
\CLK_pad/U0/U0\ : IOPAD_IN
port map(PAD => CLK, Y => \CLK_pad/U0/NET1\);
\system_clock_0/l_time_RNO[10]\ : INV
port map(A => \system_clock_0/m_time[10]\, Y =>
\system_clock_0/m_time_i[10]\);
\system_clock_0/un1_s_time_I_16\ : AND3
port map(A => \system_clock_0/DWACT_FINC_E[0]\, B =>
\system_clock_0/DWACT_FINC_E[1]\, C => LED2_c, Y =>
\system_clock_0/N_3\);
\system_clock_0/l_time_RNO[7]\ : INV
port map(A => \system_clock_0/m_time[7]\, Y =>
\system_clock_0/m_time_i[7]\);
\system_clock_0/l_time_RNO[17]\ : INV
port map(A => \system_clock_0/m_time[17]\, Y =>
\system_clock_0/m_time_i[17]\);
\system_clock_0/l_time[14]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[14]\, CLK =>
CLKINT_0_Y, E =>
\system_clock_0/l_time_RNIQEBK3[13]_net_1\, Q =>
\system_clock_0/m_time[14]\);
\system_clock_0/flag_RNO\ : NOR2B
port map(A => \system_clock_0/l_N_13_mux\, B =>
\system_clock_0/m_time[17]\, Y =>
\system_clock_0/un14_l_time\);
\system_clock_0/s_time[2]\ : DFN0E1
port map(D => \system_clock_0/s_time_3[2]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/flag_net_1\, Q =>
\system_clock_0/s_time[2]_net_1\);
\system_clock_0/l_time_RNO[13]\ : INV
port map(A => \system_clock_0/m_time[13]\, Y =>
\system_clock_0/m_time_i[13]\);
\system_clock_0/l_time[16]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[16]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/l_time_RNO_0[16]_net_1\,
Q => \system_clock_0/m_time[16]\);
\LED2_pad/U0/U0\ : IOPAD_TRI
port map(D => \LED2_pad/U0/NET1\, E => \LED2_pad/U0/NET2\,
PAD => LED2);
\system_clock_0/l_time_RNILHDM2[11]\ : OR2A
port map(A => \system_clock_0/m_time[11]\, B =>
\system_clock_0/l_time_RNIKKE72[10]_net_1\, Y =>
\system_clock_0/l_time_RNILHDM2[11]_net_1\);
\system_clock_0/l_time_RNO[14]\ : INV
port map(A => \system_clock_0/m_time[14]\, Y =>
\system_clock_0/m_time_i[14]\);
\system_clock_0/l_time_RNI4OAL3[9]\ : NOR3C
port map(A => \system_clock_0/l_m6_0_a2_2\, B =>
\system_clock_0/l_m6_0_a2_1\, C =>
\system_clock_0/l_m6_0_a2_6\, Y =>
\system_clock_0/l_m6_0_a2_7\);
\system_clock_0/un1_s_time_I_17\ : XOR2
port map(A => \system_clock_0/N_3\, B =>
\system_clock_0/s_time[6]_net_1\, Y =>
\system_clock_0/I_17\);
\system_clock_0/l_time_RNINFC53[12]\ : OR2A
port map(A => \system_clock_0/m_time[12]\, B =>
\system_clock_0/l_time_RNILHDM2[11]_net_1\, Y =>
\system_clock_0/l_time_RNINFC53[12]_net_1\);
\system_clock_0/un1_s_time_I_13\ : AND3
port map(A => \system_clock_0/DWACT_FINC_E[0]\, B =>
\system_clock_0/s_time[3]_net_1\, C =>
\system_clock_0/s_time[4]_net_1\, Y =>
\system_clock_0/N_4\);
\system_clock_0/s_time_RNIEHQH[6]\ : NOR3C
port map(A => \system_clock_0/s_time[6]_net_1\, B => LED1_c,
C => \system_clock_0/un14_flag_1\, Y =>
\system_clock_0/un14_flag_3\);
\system_clock_0/s_time[0]\ : DFN0E1
port map(D => \system_clock_0/I_4\, CLK => CLKINT_0_Y, E
=> \system_clock_0/flag_net_1\, Q =>
\system_clock_0/s_time[0]_net_1\);
\system_clock_0/l_time_RNO[16]\ : INV
port map(A => \system_clock_0/m_time[16]\, Y =>
\system_clock_0/m_time_i[16]\);
\system_clock_0/un1_s_time_I_15\ : AND2
port map(A => \system_clock_0/s_time[3]_net_1\, B =>
\system_clock_0/s_time[4]_net_1\, Y =>
\system_clock_0/DWACT_FINC_E[1]\);
\system_clock_0/s_time[6]\ : DFN0E1
port map(D => \system_clock_0/s_time_3[6]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/flag_net_1\, Q =>
\system_clock_0/s_time[6]_net_1\);
\system_clock_0/l_time_RNISO6I1[8]\ : OR2A
port map(A => \system_clock_0/m_time[8]\, B =>
\system_clock_0/N_25\, Y => \system_clock_0/N_26\);
\system_clock_0/s_time_RNO[2]\ : AOI1B
port map(A => \system_clock_0/un14_flag_3\, B =>
\system_clock_0/un14_flag_2\, C => \system_clock_0/I_7\,
Y => \system_clock_0/s_time_3[2]\);
\system_clock_0/un1_s_time_I_19\ : AND3
port map(A => \system_clock_0/DWACT_FINC_E[0]\, B =>
\system_clock_0/DWACT_FINC_E[2]\, C =>
\system_clock_0/s_time[6]_net_1\, Y =>
\system_clock_0/N_2\);
\STX_PWR_pad/U0/U1\ : IOTRI_OB_EB
port map(D => \GND\, E => \VCC\, DOUT =>
\STX_PWR_pad/U0/NET1\, EOUT => \STX_PWR_pad/U0/NET2\);
\system_clock_0/l_time[1]\ : DFN0
port map(D => \system_clock_0/m_time_i[1]\, CLK =>
CLKINT_0_Y, Q => \system_clock_0/m_time[1]\);
\system_clock_0/s_time_RNO[3]\ : AOI1B
port map(A => \system_clock_0/un14_flag_3\, B =>
\system_clock_0/un14_flag_2\, C => \system_clock_0/I_9\,
Y => \system_clock_0/s_time_3[3]\);
\STX_PWR_pad/U0/U0\ : IOPAD_TRI
port map(D => \STX_PWR_pad/U0/NET1\, E =>
\STX_PWR_pad/U0/NET2\, PAD => STX_PWR);
\system_clock_0/l_time_RNO_0[16]\ : OR2A
port map(A => \system_clock_0/m_time[15]\, B =>
\system_clock_0/l_time_RNIUEA34[14]_net_1\, Y =>
\system_clock_0/l_time_RNO_0[16]_net_1\);
GND_power_inst1 : GND
port map( Y => GND_power_net1);
VCC_power_inst1 : VCC
port map( Y => VCC_power_net1);
end DEF_ARCH;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: serdes_stratixiii
-- File: serdes_stratixiii.vhd
-- Author: Andrea Gianarro - Aeroflex Gaisler AB
-- Description: Stratix III and IV SGMII Gigabit Ethernet Serdes
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity serdes_stratixiii is
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out : out std_logic; -- SER OUT
bitslip : in std_logic
);
end entity;
architecture rtl of serdes_stratixiii is
signal rx_clk_int, rx_pll_clk_int, tx_pll_clk_int, rst_int, pll_areset_int, rx_locked_int, rx_rstn_int_0, tx_locked_int : std_logic;
signal rx_cda_reset_int, bitslip_int, rx_in_int, rx_rst_int, rx_divfwdclk_int, tx_out_int : std_logic_vector(0 downto 0) ;
signal rx_clk_rstn_int, rx_pll_rstn_int, tx_pll_rstn_int, rx_cda_reset_int_0 : std_logic;
signal rx_out_int, tx_in_int : std_logic_vector(9 downto 0) ;
signal r0, r1, r2 : std_logic_vector(4 downto 0);
signal r3 : std_logic_vector(5 downto 0);
signal r4 : std_logic_vector(1 downto 0);
begin
bitslip_int(0) <= bitslip;
rx_in_int(0) <= rx_in;
tx_in_int <= tx_in;
rx_out <= rx_out_int;
tx_out <= tx_out_int(0);
-- output clocks
rx_clk <= rx_clk_int;
rx_pll_clk <= rx_pll_clk_int;
tx_pll_clk <= tx_pll_clk_int;
-- output synchronized resets
rx_rstn <= rx_clk_rstn_int;
rx_pll_rstn <= rx_pll_rstn_int;
tx_pll_rstn <= tx_pll_rstn_int;
--rx_cda_reset_int(0) <= rx_cda_reset_int_0;
rx_rst_int(0) <= not rx_rstn_int_0;
rx_clk_int <= rx_divfwdclk_int(0);
-- reset synchronizers
rst0 : process (rx_clk_int, rst_125) begin
if rising_edge(rx_clk_int) then
r0 <= r0(3 downto 0) & rx_locked_int;
rx_clk_rstn_int <= r0(4) and r0(3) and r0(2);
end if;
if (rst_125 = '1') then r0 <= "00000"; rx_clk_rstn_int <= '0'; end if;
end process;
rst1 : process (rx_pll_clk_int, rx_clk_rstn_int) begin
if rising_edge(rx_pll_clk_int) then
r1 <= r1(3 downto 0) & rx_locked_int;
rx_pll_rstn_int <= r1(4) and r1(3) and r1(2);
end if;
if (rx_clk_rstn_int = '0') then r1 <= "00000"; rx_pll_rstn_int <= '0'; end if;
end process;
rst2 : process (tx_pll_clk_int, rx_clk_rstn_int) begin
if rising_edge(tx_pll_clk_int) then
r2 <= r2(3 downto 0) & tx_locked_int;
tx_pll_rstn_int <= r2(4) and r2(3) and r2(2);
end if;
if (rx_clk_rstn_int = '0') then r2 <= "00000"; tx_pll_rstn_int <= '0'; end if;
end process;
-- 6 stages reset synchronizer
rst3 : process (clk_125, rst_125) begin
if rising_edge(clk_125) then
r3 <= r3(4 downto 0) & rx_locked_int;
rx_rstn_int_0 <= r3(5) and r3(4) and r3(3);
end if;
if (rst_125 = '1') then r3 <= "000000"; rx_rstn_int_0 <= '0'; end if;
end process;
lvds_rx0: altlvds_rx
generic map (
buffer_implementation => "RAM",
cds_mode => "UNUSED",
--clk_src_is_pll => "off",
common_rx_tx_pll => "ON",
data_align_rollover => 10,
--data_rate => "1250.0 Mbps",
deserialization_factor => 10,
dpa_initial_phase_value => 0,
dpll_lock_count => 0,
dpll_lock_window => 0,
--enable_clock_pin_mode => "UNUSED",
enable_dpa_align_to_rising_edge_only => "OFF",
enable_dpa_calibration => "ON",
enable_dpa_fifo => "UNUSED",
enable_dpa_initial_phase_selection => "OFF",
enable_dpa_mode => "ON",
enable_dpa_pll_calibration => "OFF",
enable_soft_cdr_mode => "ON",
implement_in_les => "OFF",
inclock_boost => 0,
inclock_data_alignment => "EDGE_ALIGNED",
inclock_period => 8000,
inclock_phase_shift => 0,
input_data_rate => 1250,
intended_device_family => "Stratix IV",
lose_lock_on_one_change => "UNUSED",
lpm_hint => "UNUSED",
lpm_type => "altlvds_rx",
number_of_channels => 1,
outclock_resource => "AUTO",
pll_operation_mode => "UNUSED",
pll_self_reset_on_loss_lock => "UNUSED",
port_rx_channel_data_align => "PORT_USED",
port_rx_data_align => "PORT_UNUSED",
--refclk_frequency => "125.000000 MHz",
registered_data_align_input => "UNUSED",
registered_output => "ON",
reset_fifo_at_first_lock => "UNUSED",
rx_align_data_reg => "UNUSED",
sim_dpa_is_negative_ppm_drift => "OFF",
sim_dpa_net_ppm_variation => 0,
sim_dpa_output_clock_phase_shift => 0,
use_coreclock_input => "OFF",
use_dpll_rawperror => "OFF",
use_external_pll => "OFF",
use_no_phase_shift => "ON",
x_on_bitslip => "ON"
)
port map (
pll_areset => rst_125, --pll_areset_int,
rx_channel_data_align => bitslip_int,
rx_in => rx_in_int,
rx_inclock => clk_125,
rx_reset => rx_rst_int,
rx_divfwdclk => rx_divfwdclk_int,
rx_locked => rx_locked_int,
rx_out => rx_out_int,
rx_outclock => rx_pll_clk_int,
dpa_pll_cal_busy => open,
dpa_pll_recal => '0',
pll_phasecounterselect => open,
pll_phasedone => '1',
pll_phasestep => open,
pll_phaseupdown => open,
pll_scanclk => open,
rx_cda_max => open,
rx_cda_reset => (others => '0'),
rx_coreclk => (others => '1'),
rx_data_align => '0',
rx_data_align_reset => '0',
--rx_data_reset => '0',
rx_deskew => '0',
rx_dpa_lock_reset => (others => '0'),
rx_dpa_locked => open,
--rx_dpaclock => '0',
rx_dpll_enable => (others => '1'),
rx_dpll_hold => (others => '0'),
rx_dpll_reset => (others => '0'),
rx_enable => '1',
rx_fifo_reset => (others => '0'),
rx_pll_enable => '1',
rx_readclock => '0',
rx_syncclock => '0'
);
lvds_tx0: altlvds_tx
generic map (
center_align_msb => "UNUSED",
--clk_src_is_pll => "off",
common_rx_tx_pll => "ON",
coreclock_divide_by => 1,
--data_rate => "1250.0 Mbps",
deserialization_factor => 10,
differential_drive => 0,
implement_in_les => "OFF",
inclock_boost => 0,
inclock_data_alignment => "EDGE_ALIGNED",
inclock_period => 8000,
inclock_phase_shift => 0,
intended_device_family => "Stratix IV",
lpm_hint => "UNUSED",
lpm_type => "altlvds_tx",
multi_clock => "OFF",
number_of_channels => 1,
outclock_alignment => "EDGE_ALIGNED",
outclock_divide_by => 10,
outclock_duty_cycle => 50,
outclock_multiply_by => 1,
outclock_phase_shift => 0,
outclock_resource => "AUTO",
output_data_rate => 1250,
pll_self_reset_on_loss_lock => "OFF",
preemphasis_setting => 0,
--refclk_frequency => "125.00 MHz",
registered_input => "TX_CORECLK",
use_external_pll => "OFF",
use_no_phase_shift => "ON",
vod_setting => 0
)
port map (
pll_areset => rst_125, --pll_areset_int,
tx_in => tx_in_int,
tx_inclock => clk_125,
tx_out => tx_out_int,
tx_locked => tx_locked_int,
tx_coreclock => tx_pll_clk_int,
sync_inclock => '0',
--tx_data_reset => '0',
tx_enable => '1',
tx_outclock => open,
tx_pll_enable => '1',
tx_syncclock => '0'
);
end architecture ; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: ga69kaw, Tolga Sel
--
-- Create Date: 09:51:37 11/03/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_mulop.vhd
-- Project Name: direct_implementation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: mulop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_mulop IS
END tb_mulop;
ARCHITECTURE behavior OF tb_mulop IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal X : std_logic_vector(15 downto 0) := (others => '0');
signal Y : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT) (43241*63743) mod (65537)
uut: mulop PORT MAP (
X => X,
Y => Y,
O => O
);
X <= "0000000000000000", "1000000000000000" after 200ns, "1111111111111111" after 400ns, "1010100011101001" after 800ns;
Y <= "0000000000000000", "1000000000000000" after 200ns, "1111111111111111" after 400ns, "1111100011111111" after 800ns;
end behavior; |
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mem_ctrl_pkg.all;
entity mem_pipe is
port(
clk_in : in std_logic;
reset_in : in std_logic;
-- Command & write data pipe
cmdData_in : in std_logic_vector(15 downto 0);
cmdValid_in : in std_logic;
cmdReady_out : out std_logic;
-- Read data response pipe
rspData_out : out std_logic_vector(15 downto 0);
rspValid_out : out std_logic;
rspReady_in : in std_logic;
-- Memory controller interface
--mcAutoMode_out : out std_logic;
mcReady_in : in std_logic;
mcCmd_out : out MCCmdType;
mcAddr_out : out std_logic_vector(22 downto 0);
mcData_out : out std_logic_vector(15 downto 0);
mcData_in : in std_logic_vector(15 downto 0);
mcRDV_in : in std_logic
);
end entity;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbctrl
-- File: apbctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AMBA AHB/APB bridge with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
-- pragma translate_off
use grlib.devices.all;
use std.textio.all;
-- pragma translate_on
entity apbctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
nslaves : integer range 1 to NAPBSLV := NAPBSLV;
debug : integer range 0 to 2 := 2;
icheck : integer range 0 to 1 := 1;
enbusmon : integer range 0 to 1 := 0;
asserterr : integer range 0 to 1 := 0;
assertwarn : integer range 0 to 1 := 0;
pslvdisable : integer := 0;
mcheck : integer range 0 to 1 := 1;
ccheck : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_slv_in_type;
ahbo : out ahb_slv_out_type;
apbi : out apb_slv_in_type;
apbo : in apb_slv_out_vector
);
end;
architecture rtl of apbctrl is
constant apbmax : integer := 19;
constant VERSION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( 1, 6, 0, VERSION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
others => zero32);
constant IOAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(haddr, 12);
constant IOMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(hmask, 12);
type reg_type is record
haddr : std_logic_vector(apbmax downto 0); -- address bus
hwrite : std_logic; -- read/write
hready : std_logic; -- ready
penable : std_logic;
psel : std_logic;
prdata : std_logic_vector(31 downto 0); -- read data
pwdata : std_logic_vector(31 downto 0); -- write data
state : std_logic_vector(1 downto 0); -- state
cfgsel : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type :=
(haddr => (others => '0'), hwrite => '0', hready => '1', penable => '0',
psel => '0', prdata => (others => '0'), pwdata => (others => '0'),
state => (others => '0'), cfgsel => '0');
signal r, rin : reg_type;
--pragma translate_off
signal lapbi : apb_slv_in_type;
--pragma translate_on
begin
comb : process(ahbi, apbo, r, rst)
variable v : reg_type;
variable psel : std_logic_vector(0 to 31);
variable pwdata : std_logic_vector(31 downto 0);
variable apbaddr : std_logic_vector(apbmax downto 0);
variable apbaddr2 : std_logic_vector(31 downto 0);
variable pirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable nslave : integer range 0 to nslaves-1;
variable bnslave : std_logic_vector(3 downto 0);
begin
v := r; v.psel := '0'; v.penable := '0'; psel := (others => '0');
pirq := (others => '0');
-- detect start of cycle
if (ahbi.hready = '1') then
if ((ahbi.htrans = HTRANS_NONSEQ) or (ahbi.htrans = HTRANS_SEQ)) and
(ahbi.hsel(hindex) = '1')
then
v.hready := '0'; v.hwrite := ahbi.hwrite;
v.haddr(apbmax downto 0) := ahbi.haddr(apbmax downto 0);
v.state := "01"; v.psel := not ahbi.hwrite;
end if;
end if;
case r.state is
when "00" => null; -- idle
when "01" =>
if r.hwrite = '0' then v.penable := '1';
else v.pwdata := ahbreadword(ahbi.hwdata, r.haddr(4 downto 2)); end if;
v.psel := '1'; v.state := "10";
when others =>
if r.penable = '0' then v.psel := '1'; v.penable := '1'; end if;
v.state := "00"; v.hready := '1';
end case;
psel := (others => '0');
for i in 0 to nslaves-1 loop
if ((apbo(i).pconfig(1)(1 downto 0) = "01") and
((apbo(i).pconfig(1)(31 downto 20) and apbo(i).pconfig(1)(15 downto 4)) =
(r.haddr(19 downto 8) and apbo(i).pconfig(1)(15 downto 4))))
then psel(i) := '1'; end if;
end loop;
bnslave(0) := psel(1) or psel(3) or psel(5) or psel(7) or
psel(9) or psel(11) or psel(13) or psel(15);
bnslave(1) := psel(2) or psel(3) or psel(6) or psel(7) or
psel(10) or psel(11) or psel(14) or psel(15);
bnslave(2) := psel(4) or psel(5) or psel(6) or psel(7) or
psel(12) or psel(13) or psel(14) or psel(15);
bnslave(3) := psel(8) or psel(9) or psel(10) or psel(11) or
psel(12) or psel(13) or psel(14) or psel(15);
nslave := conv_integer(bnslave);
if (r.haddr(19 downto 12) = "11111111") then
v.cfgsel := '1'; psel := (others => '0'); v.penable := '0';
else v.cfgsel := '0'; end if;
v.prdata := apbo(nslave).prdata;
if r.cfgsel = '1' then
v.prdata := apbo(conv_integer(r.haddr(6 downto 3))).pconfig(conv_integer(r.haddr(2 downto 2)));
if nslaves <= conv_integer(r.haddr(6 downto 3)) then
v.prdata := (others => '0');
end if;
end if;
for i in 0 to nslaves-1 loop pirq := pirq or apbo(i).pirq; end loop;
-- AHB respons
ahbo.hready <= r.hready;
ahbo.hrdata <= ahbdrivedata(r.prdata);
ahbo.hirq <= pirq;
if (not RESET_ALL) and (rst = '0') then
v.penable := RES.penable; v.hready := RES.hready;
v.psel := RES.psel; v.state := RES.state;
v.hwrite := RES.hwrite;
-- pragma translate_off
v.haddr := RES.haddr;
-- pragma translate_on
end if;
rin <= v;
-- drive APB bus
apbaddr2 := (others => '0');
apbaddr2(apbmax downto 0) := r.haddr(apbmax downto 0);
apbi.paddr <= apbaddr2;
apbi.pwdata <= r.pwdata;
apbi.pwrite <= r.hwrite;
apbi.penable <= r.penable;
apbi.pirq <= ahbi.hirq;
apbi.testen <= ahbi.testen;
apbi.testoen <= ahbi.testoen;
apbi.scanen <= ahbi.scanen;
apbi.testrst <= ahbi.testrst;
apbi.testin <= ahbi.testin;
apbi.psel <= (others => '0');
for i in 0 to nslaves-1 loop apbi.psel(i) <= psel(i) and r.psel; end loop;
--pragma translate_off
lapbi.paddr <= apbaddr2;
lapbi.pwdata <= r.pwdata;
lapbi.pwrite <= r.hwrite;
lapbi.penable <= r.penable;
lapbi.pirq <= ahbi.hirq;
for i in 0 to nslaves-1 loop lapbi.psel(i) <= psel(i) and r.psel; end loop;
--pragma translate_on
end process;
ahbo.hindex <= hindex;
ahbo.hconfig <= hconfig;
ahbo.hsplit <= (others => '0');
ahbo.hresp <= HRESP_OKAY;
reg : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
-- pragma translate_off
mon0 : if enbusmon /= 0 generate
mon : apbmon
generic map(
asserterr => asserterr,
assertwarn => assertwarn,
pslvdisable => pslvdisable,
napb => nslaves)
port map(
rst => rst,
clk => clk,
apbi => lapbi,
apbo => apbo,
err => open);
end generate;
diag : process
type apb_memarea_type is record
start : std_logic_vector(31 downto 20);
stop : std_logic_vector(31 downto 20);
end record;
type memmap_type is array (0 to nslaves-1) of apb_memarea_type;
variable k : integer;
variable mask : std_logic_vector(11 downto 0);
variable device : std_logic_vector(11 downto 0);
variable devicei : integer;
variable vendor : std_logic_vector( 7 downto 0);
variable vendori : integer;
variable iosize : integer;
variable iounit : string(1 to 5) := "byte ";
variable memstart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
variable L1 : line := new string'("");
variable memmap : memmap_type;
begin
wait for 3 ns;
if debug > 0 then
print("apbctrl: APB Bridge at " & tost(memstart) & "00000 rev 1");
end if;
for i in 0 to nslaves-1 loop
vendor := apbo(i).pconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
if debug > 1 then
device := apbo(i).pconfig(0)(23 downto 12);
devicei := conv_integer(device);
std.textio.write(L1, "apbctrl: slv" & tost(i) & ": " &
iptable(vendori).vendordesc & iptable(vendori).device_table(devicei));
std.textio.writeline(OUTPUT, L1);
mask := apbo(i).pconfig(1)(15 downto 4);
k := 0;
while (k<15) and (mask(k) = '0') loop k := k+1; end loop;
iosize := 256 * 2**k; iounit := "byte ";
if (iosize > 1023) then iosize := iosize/1024; iounit := "kbyte"; end if;
print("apbctrl: I/O ports at " &
tost(memstart & (apbo(i).pconfig(1)(31 downto 20) and
apbo(i).pconfig(1)(15 downto 4))) &
"00, size " & tost(iosize) & " " & iounit);
if mcheck /= 0 then
memmap(i).start := (apbo(i).pconfig(1)(31 downto 20) and
apbo(i).pconfig(1)(15 downto 4));
memmap(i).stop := memmap(i).start + 2**k;
end if;
end if;
assert (apbo(i).pindex = i) or (icheck = 0)
report "APB slave index error on slave " & tost(i) &
". Detected index value " & tost(apbo(i).pindex) severity failure;
if mcheck /= 0 then
for j in 0 to i loop
if memmap(i).start /= memmap(i).stop then
assert ((memmap(i).start >= memmap(j).stop) or
(memmap(i).stop <= memmap(j).start) or (i = j))
report "APB slave " & tost(i) & " memory area" &
" intersects with APB slave " & tost(j) & " memory area."
severity failure;
end if;
end loop;
end if;
else
for j in 0 to NAPBCFG-1 loop
assert (apbo(i).pconfig(j) = zx or ccheck = 0)
report "APB slave " & tost(i) & " appears to be disabled, " &
"but the config record is not driven to zero"
severity warning;
end loop;
end if;
end loop;
if nslaves < NAPBSLV then
for i in nslaves to NAPBSLV-1 loop
for j in 0 to NAPBCFG-1 loop
assert (apbo(i).pconfig(j) = zx or ccheck = 0)
report "APB slave " & tost(i) & " is outside the range of decoded " &
"slave indexes but the config record is not driven to zero"
severity warning;
end loop; -- j
end loop; -- i
end if;
wait;
end process;
-- pragma translate_on
end;
|
entity signal20 is
end entity;
architecture test of signal20 is
signal x : integer_vector(4 downto 0);
signal y : integer_vector(1 downto 0);
signal z : integer_vector(2 downto 0);
signal i0, i1 : integer;
begin
main: process is
begin
x <= (1, 2, 3, 4, 5);
wait for 1 ns;
(y, z) <= x;
wait for 1 ns;
assert y = (1, 2);
assert z = (3, 4, 5);
wait for 1 ns;
(i0, z, i1) <= x;
wait for 1 ns;
assert i0 = 1;
assert z = (2, 3, 4);
assert i1 = 5;
wait;
end process;
end architecture;
|
------------------------------------------------------------------------
-- image_capture component
------------------------------------------------------------------------
-- This component is used to save an image in memory. It uses one
-- buffer in processor memory at address 'buff'.
-- When 'start_capture' is asserted the component waits for the next
-- positive flank of 'frame_valid' for synchronizing and starting at the
-- beginning of a new image. Then, every time 'data_valid' is
-- asserted the component packs the {R,G,B,Gray} components into a
-- 32-bit (when components are 8-bit) or 64-bit (when
-- components are 16-bit) word and writes it to the avalon bus.
-- It is assumed that the bus can react in a single clock cycle to the
-- writings because 'waitrequest' signal of avalon specification is not
-- implemented.
-- In case the slave bus cannot react in a single cycle, an
-- Avalon FIFO should be implemented in between the master of this
-- component and the slave where data is being written. In this case,
-- the component behaviour would be the following:
-- The component starts writing in buff0.
-- When a line from the image is acquired buff0full signal is
-- asserted during 1 clock cycle. Next line is written into buff1.
-- When a line from the image is acquired again the bus asserts
-- buff1full line for 1 cycle. Next line is saved in buff0 again.
-- So the component goes writing odd lines in buff0 and even lines
-- in buff1 until all lines in one image (image_height) are acquired.
-- The processor (or whatever component processes acquired lines)
-- should empty one buffer before this component finishes
-- filling the other one so data is not lost.
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all; -- For using ceil and log2.
use IEEE.NUMERIC_STD.all; -- For using to_unsigned.
use ieee.std_logic_unsigned.all; -- Needed for the sum used in counter.
entity image_capture is
generic (
-- Size of each color component in bits (8 or 16).
COMPONENT_SIZE : integer := 8;
-- Number of pixels per write in the output avalon bus (>=1)
PIX_WR : integer := 4
);
port (
-- Clock and reset.
clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
-- Signals from the video stream representing one pixel in RGB and grey
R : in STD_LOGIC_VECTOR((COMPONENT_SIZE - 1) downto 0);
G : in STD_LOGIC_VECTOR((COMPONENT_SIZE - 1) downto 0);
B : in STD_LOGIC_VECTOR((COMPONENT_SIZE - 1) downto 0);
Gray : in STD_LOGIC_VECTOR((COMPONENT_SIZE - 1) downto 0);
-- Signals to control the component
-- When frame_valid is 1, the image from camera is being acquired.
frame_valid : in STD_LOGIC;
data_valid : in STD_LOGIC; -- Valid pixel in R,G,B,Gray inputs.
-- Signals to control this component (usually coming from avalon_camera)
-- When start_capture is 1, start getting a new image.
start_capture : in STD_LOGIC;
-- Number of columns and rows in the input image array.
image_size : in STD_LOGIC_VECTOR(23 downto 0);
-- Image buffer address.
buff : in STD_LOGIC_VECTOR(31 downto 0);
-- Flag that indicates that the image has been captured
-- (Active 1 clock cycle only).
image_captured : out STD_LOGIC;
-- Signal indicating standby state
--(outside of reset, waiting for flank in start_capture)
standby : out STD_LOGIC;
-- Avalon MM Master port to save data into a memory.
-- Byte addresses are multiples of 4 when accessing 32-bit data.
address : out STD_LOGIC_VECTOR(31 downto 0);
write : out STD_LOGIC;
byteenable : out STD_LOGIC_VECTOR((PIX_WR*COMPONENT_SIZE/2 - 1)
downto 0);
writedata : out STD_LOGIC_VECTOR((PIX_WR*COMPONENT_SIZE*4 - 1)
downto 0);
waitrequest : in STD_LOGIC;
burstcount : out STD_LOGIC_VECTOR(6 downto 0)
);
end image_capture;
architecture arch of image_capture is
type array_of_std_logic_vector is array(natural range <>)
of STD_LOGIC_VECTOR;
constant NUMBER_OF_STATES : INTEGER := 6;
--signals for the evolution of the state machine
signal current_state : INTEGER range 0 to (NUMBER_OF_STATES - 1);
signal next_state : INTEGER range 0 to (NUMBER_OF_STATES - 1);
-- Conditions to change next state.
-- State_condition(x) condition to go from x to x+1.
signal state_condition : STD_LOGIC_VECTOR((NUMBER_OF_STATES - 2)
downto 0);
signal condition_5_to_1 : STD_LOGIC;
--counters.
signal pix_counter : STD_LOGIC_VECTOR(23 downto 0);
signal image_end_reached : STD_LOGIC;
signal pix_wr_counter : STD_LOGIC_VECTOR(integer(
ceil(log2(real(PIX_WR+1)))) downto 0);
-- Write_buff saves the address where the next pixel will be saved.
signal write_buff : STD_LOGIC_VECTOR(31 downto 0);
-- Internal copy of the write output signal
signal av_write : STD_LOGIC;
-- Extra buffers to pack the pixels and reduce the number of writes in bus
signal output_buff : array_of_std_logic_vector((PIX_WR - 1)
downto 0) ((COMPONENT_SIZE*4-1) downto 0);
signal out_buff_EN :STD_LOGIC_VECTOR((PIX_WR - 1) downto 0);
--Packs input components into a single variable
signal input_data :STD_LOGIC_VECTOR((COMPONENT_SIZE*4 - 1)
downto 0);
-- captures a flank in start capture that comes from other clock region.
signal start_capture_reg : STD_LOGIC;
begin
-- FSM (Finite State Machine) clocking and reset.
fsm_mem: process (clk,reset_n)
begin
if rising_edge(clk) then
if reset_n = '0' then
current_state <= 0;
else
current_state <= next_state;
end if;
end if;
end process fsm_mem;
-- Evolution of FSM.
comb_fsm: process (current_state, state_condition, condition_5_to_1)
begin
case current_state is
when 0 =>
if state_condition(0) = '1' then
next_state <= 1;
else
next_state <= 0;
end if;
when 1 =>
if state_condition(1) = '1' then
next_state <= 2;
else
next_state<=1;
end if;
when 2 =>
if state_condition(2) = '1' then
next_state <= 3;
else
next_state<=2;
end if;
when 3 =>
if state_condition(3) = '1' then
next_state <= 4;
else
next_state<=3;
end if;
when 4 =>
if state_condition(4) = '1' then
next_state <= 5;
else
next_state<=4;
end if;
when 5 =>
if condition_5_to_1 = '1' then
next_state <= 1;
else
next_state<=5;
end if;
when others =>
next_state <= 0;
end case;
end process comb_fsm;
-- Conditions of FSM.
state_condition(0) <= '1';
state_condition(1) <= start_capture_reg;
state_condition(2) <= not(frame_valid);
state_condition(3) <= frame_valid;
state_condition(4) <= image_end_reached;
condition_5_to_1 <= '1';
-- Evaluation and update pix_counter.
pix_counter_proc:process (clk, current_state, data_valid)
begin
if rising_edge(clk) then
if (current_state = 1) then
-- reset the pixel counter
pix_counter <= (others => '0');
elsif (current_state = 4) and (data_valid = '1') then
-- Increment the pixel counter
pix_counter <= pix_counter + 1;
end if;
end if;
if pix_counter = image_size(23 downto 0) then
image_end_reached <= '1';
else
image_end_reached <= '0';
end if;
end process;
-- Evaluation and update pix_wr_counter.
pix_wr_counter_proc:process (clk)
begin
if rising_edge(clk) then
if (current_state = 1) then
-- reset the pixel write counter
pix_wr_counter <= (others => '0');
elsif (current_state = 4) and (data_valid = '1') then
-- Increment the pixel write counter
if pix_wr_counter = (PIX_WR-1) then
pix_wr_counter <= (others => '0');
else
pix_wr_counter <= pix_wr_counter + 1;
end if;
end if;
end if;
end process;
-- Generate standby signal
with current_state select standby <=
'1' when 1,
'0' when others;
-- Generate image_captured signal
with current_state select image_captured <=
'1' when 5,
'0' when others;
-- Save data in extra output buffers
input_data <= Gray & B & G & R;
out_buff_generate: for I in 0 to (PIX_WR-1) generate
output_buff_proc: process (clk)
begin
if rising_edge(clk) then
if current_state = 0 or current_state = 1 then
output_buff(I) <= (others => '0');
elsif (out_buff_EN(I)='1') then
output_buff(I) <= input_data;
end if;
end if;
end process;
out_buff_EN_proc: process (clk, data_valid, pix_wr_counter,
current_state)
begin
if (data_valid = '1') and (pix_wr_counter = I)
and (current_state = 4) then
out_buff_EN(I) <= '1';
else
out_buff_EN(I) <= '0';
end if;
end process;
end generate out_buff_generate;
--Generate Avalon signals
--write data
write_data_generate : for I in 0 to (PIX_WR-1) generate
writedata(((I+1)*4*COMPONENT_SIZE - 1) downto (I*4*COMPONENT_SIZE)) <=
output_buff(I);
end generate write_data_generate;
--byteenable
byteenable <= (others => '1');
--burstcount
-- Always single transactions (no burst)
burstcount <= "0000001";
-- write
write_proc : process (clk)
begin
if rising_edge(clk) then
if current_state = 0 or current_state = 1 then
av_write <= '0';
elsif out_buff_EN(PIX_WR-1) = '1' then
av_write <= '1';
else
av_write <= '0';
end if;
end if;
end process;
write <= av_write;
-- address
buff_proc:process (clk)
begin
if rising_edge(clk) then
if current_state = 1 then --reset signals to initial values
write_buff <= buff;
elsif av_write = '1' then
write_buff <= write_buff + (PIX_WR*COMPONENT_SIZE/2);
end if;
end if;
end process;
address <= write_buff;
-- Detection of a flank in start_capture. This signal is coming from the
-- processor and could have different clock. That's why flank is detected
-- instead of level.
start_capture_reg_proc:process(start_capture, current_state)
begin
if (current_state = 2 or current_state = 0) then
start_capture_reg <= '0';
elsif rising_edge(start_capture) then
start_capture_reg <= '1';
end if;
end process;
end arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity SM_mem_init_test is
Port (clock : in STD_LOGIC;
reset : in STD_LOGIC;
RAM_wait : in STD_LOGIC;
memory_data_bus : inout STD_LOGIC_VECTOR(15 downto 0);
memory_address_bus : out STD_LOGIC_VECTOR(22 downto 0);
anodes : out STD_LOGIC_VECTOR(3 downto 0);
decoder_out : out STD_LOGIC_VECTOR(6 downto 0);
SM_reset : out STD_LOGIC;
RAM_ce : out STD_LOGIC;
RAM_we : out STD_LOGIC;
RAM_oe : out STD_LOGIC;
RAM_lb : out STD_LOGIC;
RAM_ub : out STD_LOGIC;
RAM_cre : out STD_LOGIC;
RAM_adv : out STD_LOGIC;
RAM_clk : out STD_LOGIC);
end entity;
architecture Behavioral of SM_mem_init_test is
component four_dig_7seg is
Port ( clock : in STD_LOGIC;
display_data : in STD_LOGIC_VECTOR (15 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0);
to_display : out STD_LOGIC_VECTOR (6 downto 0));
end component;
signal state : STD_LOGIC_VECTOR(4 downto 0);
signal SM_wait_counter : STD_LOGIC_VECTOR(2 downto 0);
signal clk_100MHz : STD_LOGIC;
signal RAM_clk_en : STD_LOGIC;
signal output_enable : STD_LOGIC;
signal memory_data_bus_in : STD_LOGIC_VECTOR(15 downto 0);
signal memory_data_bus_out : STD_LOGIC_VECTOR(15 downto 0);
signal collected_data : STD_LOGIC_VECTOR(15 downto 0);
begin
DCM_1 : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 2, -- Can be any interger from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 20.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "HIGH", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
CLKFX => clk_100MHz, -- DCM CLK synthesis out (M/D)
CLKIN => clock
);
--The state machine
process (clk_100MHz, reset)
begin
if reset = '1' then
state <= "00000";
SM_reset <= '1';
SM_wait_counter <= "000";
output_enable <= '0';
RAM_ce <= '1';
RAM_we <= '1';
RAM_oe <= '0';
RAM_adv <= '1';
RAM_lb <= '0';
RAM_ub <= '0';
RAM_cre <= '0';
RAM_clk_en <= '0';
elsif falling_edge(clk_100MHz) then
case state is
--These first states put the memory into synchronous mode
--Read cycle one
when "00000" =>
SM_reset <= '1';
RAM_ce <= '0';
RAM_we <= '1';
RAM_oe <= '0';
RAM_lb <= '0';
RAM_ub <= '0';
RAM_clk_en <= '0';
RAM_cre <= '0';
memory_address_bus <= (others => '1');
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00001";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00000";
end if;
when "00001" =>
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00010";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00001";
end if;
--Read cycle two
when "00010" =>
RAM_ce <= '0';
memory_address_bus <= (others => '1');
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00011";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00010";
end if;
when "00011" =>
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00100";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00011";
end if;
--Write cycle one
when "00100" =>
--Setup state for the first write cycle
RAM_oe <= '1';
RAM_ce <= '0';
memory_address_bus <= (others => '1');
output_enable <= '1';
memory_data_bus_out <= x"0001";
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00101";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00100";
end if;
when "00101" =>
--Second half of the first write cycle
RAM_we <= '0';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00110";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00101";
end if;
when "00110" =>
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00111";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00110";
end if;
--Second write cycle
when "00111" =>
RAM_ce <= '0';
memory_data_bus_out <= b"0001110101001111"; --BCR data
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "01000";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00111";
end if;
when "01000" =>
output_enable <= '0';
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "01001";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "01000";
end if;
--End of initialization, begin normal operation
--Wait state, also enable RAM_clk
when "01001" =>
RAM_clk_en <= '1';
output_enable <= '1';
state <= "01010";
--Set up the signals for a write
when "01010" =>
RAM_ce <= '0';
RAM_adv <= '0';
RAM_we <= '0';
RAM_oe <= '1';
memory_address_bus <= b"00000000000000000000001";
state <= "01011";
--Wait for RAM_wait
when "01100" =>
RAM_adv <= '0';
if RAM_wait = '1' then
state <= "01101";
else
state <= "01100";
end if;
--Begin the writes
when "01101" =>
memory_data_bus_out <= x"000F";
state <= "01110";
when "01110" =>
memory_data_bus_out <= x"000E";
state <= "01111";
when "01111" =>
memory_data_bus_out <= x"000D";
state <= "10000";
when "10000" =>
memory_data_bus_out <= x"000C";
state <= "10001";
--End the write
when "10001" =>
RAM_ce <= '1';
state <= "10010";
--A wait cycle
when "10010" =>
state <= "10011";
--Set up the signals for a read
when "10011" =>
RAM_ce <= '0';
RAM_adv <= '0';
RAM_oe <= '0';
RAM_we <= '1';
output_enable <= '0';
memory_address_bus <= b"00000000000000000000001";
state <= "10100";
--Read into a register
when "10100" =>
collected_data(3 downto 0) <= memory_data_bus_in(3 downto 0);
state <= "10101";
when "10101" =>
collected_data(7 downto 4) <= memory_data_bus_in(3 downto 0);
state <= "10110";
when "10110" =>
collected_data(11 downto 8) <= memory_data_bus_in(3 downto 0);
state <= "10111";
when "10111" =>
collected_data(15 downto 12) <= memory_data_bus_in(3 downto 0);
state <= "11000";
--End the read and wait here
when "11000" =>
RAM_ce <= '1';
RAM_oe <= '1';
RAM_we <= '1';
state <= "11000";
when others =>
state <= "00000";
end case;
end if;
end process;
--A tristate buffer for the memory data bus
tristate : process (output_enable, memory_data_bus_in)
begin
if output_enable = '1' then
memory_data_bus <= memory_data_bus_out;
else
memory_data_bus <= (others => 'Z');
end if;
memory_data_bus_in <= memory_data_bus;
end process;
--Handles the enabling of the RAM clock
RAM_clock : process (clk_100MHz, RAM_clk_en)
begin
if RAM_clk_en = '1' then
RAM_clk <= clk_100MHz;
else
RAM_clk <= 'Z';
end if;
end process;
display: four_dig_7seg port map (clock => clock,
display_data => collected_data,
anodes => anodes,
to_display => decoder_out);
end Behavioral; |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_2_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_2_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:system_axi_dma_0_wrapper_fifo_generator_v9_3_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
-- Fully pipelined complex AXI stream multiplier with generic widths
--
-- Original author Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ComplexMultiplier is
generic (
A_WIDTH : natural := 16;
B_WIDTH : natural := 16;
PROD_WIDTH : natural := 16;
-- normally complex multiplication grows by one bit e.g. -1-1im * -1-1im = 0 + 2im
-- divide output by BIT_SHIFT if overflow not a concern e.g. multplying by e^i\theta
BIT_SHIFT : natural := 0
);
port (
clk : in std_logic;
rst : in std_logic;
a_data_re : in std_logic_vector(A_WIDTH-1 downto 0);
a_data_im : in std_logic_vector(A_WIDTH-1 downto 0);
a_vld : in std_logic;
a_last : in std_logic;
b_data_re : in std_logic_vector(B_WIDTH-1 downto 0);
b_data_im : in std_logic_vector(B_WIDTH-1 downto 0);
b_vld : in std_logic;
b_last : in std_logic;
prod_data_re : out std_logic_vector(PROD_WIDTH-1 downto 0);
prod_data_im : out std_logic_vector(PROD_WIDTH-1 downto 0);
prod_vld : out std_logic;
prod_last : out std_logic
);
end entity;
architecture arch of ComplexMultiplier is
signal a_reg_re, a_reg_im : signed(A_WIDTH-1 downto 0);
signal b_reg_re, b_reg_im : signed(B_WIDTH-1 downto 0);
constant PROD_WIDTH_INT : natural := A_WIDTH + B_WIDTH;
signal prod1, prod2, prod3, prod4 : signed(PROD_WIDTH_INT-1 downto 0);
signal sum_re, sum_im : signed(PROD_WIDTH_INT-1 downto 0);
--How to slice the output sum
subtype OUTPUT_SLICE is natural range (PROD_WIDTH_INT - 1 - BIT_SHIFT) downto (PROD_WIDTH_INT - BIT_SHIFT - PROD_WIDTH);
begin
main : process( clk )
begin
if rising_edge(clk) then
if rst = '1' then
a_reg_re <= (others => '0');
a_reg_im <= (others => '0');
b_reg_re <= (others => '0');
b_reg_im <= (others => '0');
prod1 <= (others => '0');
prod2 <= (others => '0');
prod3 <= (others => '0');
prod4 <= (others => '0');
sum_re <= (others => '0');
sum_im <= (others => '0');
prod_data_re <= (others => '0');
prod_data_im <= (others => '0');
else
--Register inputs
a_reg_re <= signed(a_data_re);
a_reg_im <= signed(a_data_im);
b_reg_re <= signed(b_data_re);
b_reg_im <= signed(b_data_im);
--Pipeline intermediate products
prod1 <= a_reg_re * b_reg_re;
prod2 <= a_reg_re * b_reg_im;
prod3 <= a_reg_im * b_reg_re;
prod4 <= a_reg_im * b_reg_im;
--don't have to worry about overflow because signed multiplication already has extra bit
sum_re <= prod1 - prod4;
sum_im <= prod2 + prod3;
--Slice output to truncate
prod_data_re <= std_logic_vector( sum_re(OUTPUT_SLICE) );
prod_data_im <= std_logic_vector( sum_im(OUTPUT_SLICE) );
end if;
end if;
end process; -- main
--Delay the valid and last for the pipelining through the multiplier
--Currently this is 4 clocks: input register; products; additions; output register
--Both inputs have to be valid
delayLine_vld : entity work.DelayLine
generic map(DELAY_TAPS => 4)
port map(clk => clk, rst => rst, data_in(0) => (a_vld and b_vld), data_out(0) => prod_vld);
--Either last -- unaligned lasts is not defined behaviour
delayLine_last : entity work.DelayLine
generic map(DELAY_TAPS => 4)
port map(clk => clk, rst => rst, data_in(0) => (a_last or b_last), data_out(0) => prod_last);
end architecture;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : CSP_DRP_ILA.vhd
-- /___/ /\ Timestamp : Wed Nov 12 20:38:34 Mitteleuropäische Zeit 2014
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CSP_DRP_ILA IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
DATA: in std_logic_vector(69 downto 0);
TRIG0: in std_logic_vector(9 downto 0);
TRIG1: in std_logic_vector(11 downto 0);
TRIG_OUT: out std_logic);
END CSP_DRP_ILA;
ARCHITECTURE CSP_DRP_ILA_a OF CSP_DRP_ILA IS
BEGIN
END CSP_DRP_ILA_a;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:55:26 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "system_processing_system7_0_0.hwdef";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
attribute POWER : string;
attribute POWER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={125} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
end system_processing_system7_0_0_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_processing_system7_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_processing_system7_0_0 : entity is "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_processing_system7_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
end system_processing_system7_0_0;
architecture STRUCTURE of system_processing_system7_0_0 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "system_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={125} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
pullup_MIO_0inst: unisim.vcomponents.PULLUP
port map (
O => MIO(0)
);
pullup_MIO_9inst: unisim.vcomponents.PULLUP
port map (
O => MIO(9)
);
pullup_MIO_10inst: unisim.vcomponents.PULLUP
port map (
O => MIO(10)
);
pullup_MIO_11inst: unisim.vcomponents.PULLUP
port map (
O => MIO(11)
);
pullup_MIO_12inst: unisim.vcomponents.PULLUP
port map (
O => MIO(12)
);
pullup_MIO_13inst: unisim.vcomponents.PULLUP
port map (
O => MIO(13)
);
pullup_MIO_14inst: unisim.vcomponents.PULLUP
port map (
O => MIO(14)
);
pullup_MIO_15inst: unisim.vcomponents.PULLUP
port map (
O => MIO(15)
);
pullup_MIO_46inst: unisim.vcomponents.PULLUP
port map (
O => MIO(46)
);
inst: entity work.system_processing_system7_0_0_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => SDIO0_WP,
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
|
entity wait17 is
end entity;
architecture test of wait17 is
function func (x : bit) return bit_vector is
begin
return (0 to 7 => x);
end function;
signal result, x : bit;
begin
p1: result <= func(x)(0);
p2: process is
begin
assert result = '0';
x <= '1';
wait for 1 ns;
assert result = '1';
wait;
end process;
end architecture;
|
architecture rtl of fifo is
variable sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0)
,
elementB(3 downto 0)
),
element3(3 downto 0)(elementC(4 downto 1), elementD(1 downto 0)),
element5(
elementE(3 downto 0)(6 downto 0)
,
elementF(7 downto 0)
),
element6(4 downto 0),
element7(7 downto 0));
variable sig9 : t_data_struct(data(7 downto 0));
variable sig9 : t_data_struct(
data(7 downto 0)
);
begin
end architecture rtl;
|
long_ent17y_n4m3_with_numbers4567: entity lib.deep.E4
2numbers_should_not_start: entity comp
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity execute_block is
generic (
SIZE : integer := 32
);
port (
IMM_i : in std_logic_vector(SIZE - 1 downto 0);
A_i : in std_logic_vector(SIZE - 1 downto 0);
rB_i : in std_logic_vector(4 downto 0);
rC_i : in std_logic_vector(4 downto 0);
MUXED_B_i : in std_logic_vector(SIZE - 1 downto 0);
S_MUX_ALUIN_i : in std_logic;
FW_X_i : in std_logic_vector(SIZE - 1 downto 0);
FW_W_i : in std_logic_vector(SIZE - 1 downto 0);
S_FW_A_i : in std_logic_vector(1 downto 0);
S_FW_B_i : in std_logic_vector(1 downto 0);
muxed_dest : out std_logic_vector(4 downto 0);
muxed_B : out std_logic_vector(SIZE -1 downto 0);
S_MUX_DEST_i : in std_logic_vector(1 downto 0);
OP : in AluOp;
ALUW_i : in std_logic_vector(12 downto 0);
DOUT : out std_logic_vector(SIZE - 1 downto 0);
stall_o : out std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end execute_block;
architecture struct of execute_block is
component mux21
port (
IN0 : in std_logic_vector(SIZE - 1 downto 0);
IN1 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic;
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
component mux41
generic (
MUX_SIZE : integer := 5
);
port (
IN0 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN1 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN2 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN3 : in std_logic_vector(MUX_SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(MUX_SIZE - 1 downto 0)
);
end component;
component real_alu
generic (
DATA_SIZE : integer := 32);
port (
IN1 : in std_logic_vector(DATA_SIZE - 1 downto 0);
IN2 : in std_logic_vector(DATA_SIZE - 1 downto 0);
--OP : in AluOp;
ALUW_i : in std_logic_vector(12 downto 0);
DOUT : out std_logic_vector(DATA_SIZE - 1 downto 0);
stall_o : out std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end component;
signal FWB2mux : std_logic_vector(SIZE - 1 downto 0);
signal FWA2alu : std_logic_vector(SIZE - 1 downto 0);
signal FWB2alu : std_logic_vector(SIZE - 1 downto 0);
begin
ALUIN_MUX: mux21 port map(
IN0 => FWB2mux,
IN1 => IMM_i,
CTRL => S_MUX_ALUIN_i,
OUT1 => FWB2alu);
ALU: real_alu generic map (
DATA_SIZE => 32
)
port map (
IN1 => FWA2alu,
IN2 => FWB2alu,
-- OP => OP,
ALUW_i => ALUW_i,
DOUT => DOUT,
stall_o => stall_o,
Clock => Clock,
Reset => Reset
);
MUXDEST: mux41 generic map(
MUX_SIZE => 5
)
port map(
IN0 => "00000", -- THIS VALUE SHOULD NEVER APPEAR!!
IN1 => rC_i,
IN2 => rB_i,
IN3 => "11111",
CTRL => S_MUX_DEST_i,
OUT1 => muxed_dest
);
MUX_FWA: mux41 generic map(
MUX_SIZE => 32
)
port map(
IN0 => A_i,
IN1 => FW_X_i,
IN2 => FW_W_i,
IN3 => "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX", -- TODO: remove this, avoid meta state during synth
CTRL => S_FW_A_i,
OUT1 => FWA2alu
);
MUX_FWB: mux41 generic map(
MUX_SIZE => 32
)
port map(
IN0 => MUXED_B_i,
IN1 => FW_X_i,
IN2 => FW_W_i,
IN3 => "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX", -- TODO: remove this, avoid meta state during synth
CTRL => S_FW_B_i,
OUT1 => FWB2mux
);
muxed_B <= FWB2mux;
end struct;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity mux4x1 is
port (w, x, y, z: in std_logic_vector(7 downto 0);
s: in std_logic_vector(1 downto 0);
m: out std_logic_vector(7 downto 0)
);
end mux4x1;
architecture mux_estr of mux4x1 is
begin
m <= w when s = "00" else
x when s = "01" else
y when s = "10" else
z;
end mux_estr; |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Module Name: adau1761_configuraiton_data - Behavioral
-- Description: A script for the I3C2, which sends out I2c transactions to configure
-- the ADAU1761 codec.
--
-- See i3c2program for original source for script
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adau1761_configuraiton_data is
Port ( clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (9 downto 0);
data : out STD_LOGIC_VECTOR (8 downto 0));
end adau1761_configuraiton_data;
architecture Behavioral of adau1761_configuraiton_data is
begin
process(clk)
begin
if rising_edge(clk) then
case address is
when "0000000000" => data <= "011101111";
when "0000000001" => data <= "101110110";
when "0000000010" => data <= "101000000";
when "0000000011" => data <= "100000000";
when "0000000100" => data <= "100001110";
when "0000000101" => data <= "011111111";
when "0000000110" => data <= "101110110";
when "0000000111" => data <= "101000000";
when "0000001000" => data <= "100000010";
when "0000001001" => data <= "100000000";
when "0000001010" => data <= "101111101";
when "0000001011" => data <= "100000000";
when "0000001100" => data <= "100001100";
when "0000001101" => data <= "100100011";
when "0000001110" => data <= "100000001";
when "0000001111" => data <= "011111111";
when "0000010000" => data <= "011101111";
when "0000010001" => data <= "101110110";
when "0000010010" => data <= "101000000";
when "0000010011" => data <= "100000000";
when "0000010100" => data <= "100001111";
when "0000010101" => data <= "011111111";
when "0000010110" => data <= "011101111";
when "0000010111" => data <= "101110110";
when "0000011000" => data <= "101000000";
when "0000011001" => data <= "100010101";
when "0000011010" => data <= "100000001";
when "0000011011" => data <= "011111111";
when "0000011100" => data <= "101110110";
when "0000011101" => data <= "101000000";
when "0000011110" => data <= "100001010";
when "0000011111" => data <= "100000001";
when "0000100000" => data <= "011111111";
when "0000100001" => data <= "101110110";
when "0000100010" => data <= "101000000";
when "0000100011" => data <= "100001011";
when "0000100100" => data <= "100000101";
when "0000100101" => data <= "011111111";
when "0000100110" => data <= "101110110";
when "0000100111" => data <= "101000000";
when "0000101000" => data <= "100001100";
when "0000101001" => data <= "100000001";
when "0000101010" => data <= "011111111";
when "0000101011" => data <= "101110110";
when "0000101100" => data <= "101000000";
when "0000101101" => data <= "100001101";
when "0000101110" => data <= "100000101";
when "0000101111" => data <= "011111111";
when "0000110000" => data <= "101110110";
when "0000110001" => data <= "101000000";
when "0000110010" => data <= "100011100";
when "0000110011" => data <= "100100001";
when "0000110100" => data <= "011111111";
when "0000110101" => data <= "101110110";
when "0000110110" => data <= "101000000";
when "0000110111" => data <= "100011110";
when "0000111000" => data <= "101000001";
when "0000111001" => data <= "011111111";
when "0000111010" => data <= "101110110";
when "0000111011" => data <= "101000000";
when "0000111100" => data <= "100100011";
when "0000111101" => data <= "111100111";
when "0000111110" => data <= "011111111";
when "0000111111" => data <= "101110110";
when "0001000000" => data <= "101000000";
when "0001000001" => data <= "100100100";
when "0001000010" => data <= "111100111";
when "0001000011" => data <= "011111111";
when "0001000100" => data <= "101110110";
when "0001000101" => data <= "101000000";
when "0001000110" => data <= "100100101";
when "0001000111" => data <= "111100111";
when "0001001000" => data <= "011111111";
when "0001001001" => data <= "101110110";
when "0001001010" => data <= "101000000";
when "0001001011" => data <= "100100110";
when "0001001100" => data <= "111100111";
when "0001001101" => data <= "011111111";
when "0001001110" => data <= "101110110";
when "0001001111" => data <= "101000000";
when "0001010000" => data <= "100011001";
when "0001010001" => data <= "100000011";
when "0001010010" => data <= "011111111";
when "0001010011" => data <= "101110110";
when "0001010100" => data <= "101000000";
when "0001010101" => data <= "100101001";
when "0001010110" => data <= "100000011";
when "0001010111" => data <= "011111111";
when "0001011000" => data <= "101110110";
when "0001011001" => data <= "101000000";
when "0001011010" => data <= "100101010";
when "0001011011" => data <= "100000011";
when "0001011100" => data <= "011111111";
when "0001011101" => data <= "101110110";
when "0001011110" => data <= "101000000";
when "0001011111" => data <= "111110010";
when "0001100000" => data <= "100000001";
when "0001100001" => data <= "011111111";
when "0001100010" => data <= "101110110";
when "0001100011" => data <= "101000000";
when "0001100100" => data <= "111110011";
when "0001100101" => data <= "100000001";
when "0001100110" => data <= "011111111";
when "0001100111" => data <= "101110110";
when "0001101000" => data <= "101000000";
when "0001101001" => data <= "111111001";
when "0001101010" => data <= "101111111";
when "0001101011" => data <= "011111111";
when "0001101100" => data <= "101110110";
when "0001101101" => data <= "101000000";
when "0001101110" => data <= "111111010";
when "0001101111" => data <= "100000011";
when "0001110000" => data <= "011111111";
when "0001110001" => data <= "011111110";
when "0001110010" => data <= "011111110";
when "0001110011" => data <= "011111110";
when "0001110100" => data <= "011111110";
when "0001110101" => data <= "011111110";
when "0001110110" => data <= "011111110";
when "0001110111" => data <= "011111110";
when "0001111000" => data <= "011101111";
when "0001111001" => data <= "000001111";
when others => data <= (others =>'0');
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Module Name: adau1761_configuraiton_data - Behavioral
-- Description: A script for the I3C2, which sends out I2c transactions to configure
-- the ADAU1761 codec.
--
-- See i3c2program for original source for script
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adau1761_configuraiton_data is
Port ( clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (9 downto 0);
data : out STD_LOGIC_VECTOR (8 downto 0));
end adau1761_configuraiton_data;
architecture Behavioral of adau1761_configuraiton_data is
begin
process(clk)
begin
if rising_edge(clk) then
case address is
when "0000000000" => data <= "011101111";
when "0000000001" => data <= "101110110";
when "0000000010" => data <= "101000000";
when "0000000011" => data <= "100000000";
when "0000000100" => data <= "100001110";
when "0000000101" => data <= "011111111";
when "0000000110" => data <= "101110110";
when "0000000111" => data <= "101000000";
when "0000001000" => data <= "100000010";
when "0000001001" => data <= "100000000";
when "0000001010" => data <= "101111101";
when "0000001011" => data <= "100000000";
when "0000001100" => data <= "100001100";
when "0000001101" => data <= "100100011";
when "0000001110" => data <= "100000001";
when "0000001111" => data <= "011111111";
when "0000010000" => data <= "011101111";
when "0000010001" => data <= "101110110";
when "0000010010" => data <= "101000000";
when "0000010011" => data <= "100000000";
when "0000010100" => data <= "100001111";
when "0000010101" => data <= "011111111";
when "0000010110" => data <= "011101111";
when "0000010111" => data <= "101110110";
when "0000011000" => data <= "101000000";
when "0000011001" => data <= "100010101";
when "0000011010" => data <= "100000001";
when "0000011011" => data <= "011111111";
when "0000011100" => data <= "101110110";
when "0000011101" => data <= "101000000";
when "0000011110" => data <= "100001010";
when "0000011111" => data <= "100000001";
when "0000100000" => data <= "011111111";
when "0000100001" => data <= "101110110";
when "0000100010" => data <= "101000000";
when "0000100011" => data <= "100001011";
when "0000100100" => data <= "100000101";
when "0000100101" => data <= "011111111";
when "0000100110" => data <= "101110110";
when "0000100111" => data <= "101000000";
when "0000101000" => data <= "100001100";
when "0000101001" => data <= "100000001";
when "0000101010" => data <= "011111111";
when "0000101011" => data <= "101110110";
when "0000101100" => data <= "101000000";
when "0000101101" => data <= "100001101";
when "0000101110" => data <= "100000101";
when "0000101111" => data <= "011111111";
when "0000110000" => data <= "101110110";
when "0000110001" => data <= "101000000";
when "0000110010" => data <= "100011100";
when "0000110011" => data <= "100100001";
when "0000110100" => data <= "011111111";
when "0000110101" => data <= "101110110";
when "0000110110" => data <= "101000000";
when "0000110111" => data <= "100011110";
when "0000111000" => data <= "101000001";
when "0000111001" => data <= "011111111";
when "0000111010" => data <= "101110110";
when "0000111011" => data <= "101000000";
when "0000111100" => data <= "100100011";
when "0000111101" => data <= "111100111";
when "0000111110" => data <= "011111111";
when "0000111111" => data <= "101110110";
when "0001000000" => data <= "101000000";
when "0001000001" => data <= "100100100";
when "0001000010" => data <= "111100111";
when "0001000011" => data <= "011111111";
when "0001000100" => data <= "101110110";
when "0001000101" => data <= "101000000";
when "0001000110" => data <= "100100101";
when "0001000111" => data <= "111100111";
when "0001001000" => data <= "011111111";
when "0001001001" => data <= "101110110";
when "0001001010" => data <= "101000000";
when "0001001011" => data <= "100100110";
when "0001001100" => data <= "111100111";
when "0001001101" => data <= "011111111";
when "0001001110" => data <= "101110110";
when "0001001111" => data <= "101000000";
when "0001010000" => data <= "100011001";
when "0001010001" => data <= "100000011";
when "0001010010" => data <= "011111111";
when "0001010011" => data <= "101110110";
when "0001010100" => data <= "101000000";
when "0001010101" => data <= "100101001";
when "0001010110" => data <= "100000011";
when "0001010111" => data <= "011111111";
when "0001011000" => data <= "101110110";
when "0001011001" => data <= "101000000";
when "0001011010" => data <= "100101010";
when "0001011011" => data <= "100000011";
when "0001011100" => data <= "011111111";
when "0001011101" => data <= "101110110";
when "0001011110" => data <= "101000000";
when "0001011111" => data <= "111110010";
when "0001100000" => data <= "100000001";
when "0001100001" => data <= "011111111";
when "0001100010" => data <= "101110110";
when "0001100011" => data <= "101000000";
when "0001100100" => data <= "111110011";
when "0001100101" => data <= "100000001";
when "0001100110" => data <= "011111111";
when "0001100111" => data <= "101110110";
when "0001101000" => data <= "101000000";
when "0001101001" => data <= "111111001";
when "0001101010" => data <= "101111111";
when "0001101011" => data <= "011111111";
when "0001101100" => data <= "101110110";
when "0001101101" => data <= "101000000";
when "0001101110" => data <= "111111010";
when "0001101111" => data <= "100000011";
when "0001110000" => data <= "011111111";
when "0001110001" => data <= "011111110";
when "0001110010" => data <= "011111110";
when "0001110011" => data <= "011111110";
when "0001110100" => data <= "011111110";
when "0001110101" => data <= "011111110";
when "0001110110" => data <= "011111110";
when "0001110111" => data <= "011111110";
when "0001111000" => data <= "011101111";
when "0001111001" => data <= "000001111";
when others => data <= (others =>'0');
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Module Name: adau1761_configuraiton_data - Behavioral
-- Description: A script for the I3C2, which sends out I2c transactions to configure
-- the ADAU1761 codec.
--
-- See i3c2program for original source for script
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adau1761_configuraiton_data is
Port ( clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (9 downto 0);
data : out STD_LOGIC_VECTOR (8 downto 0));
end adau1761_configuraiton_data;
architecture Behavioral of adau1761_configuraiton_data is
begin
process(clk)
begin
if rising_edge(clk) then
case address is
when "0000000000" => data <= "011101111";
when "0000000001" => data <= "101110110";
when "0000000010" => data <= "101000000";
when "0000000011" => data <= "100000000";
when "0000000100" => data <= "100001110";
when "0000000101" => data <= "011111111";
when "0000000110" => data <= "101110110";
when "0000000111" => data <= "101000000";
when "0000001000" => data <= "100000010";
when "0000001001" => data <= "100000000";
when "0000001010" => data <= "101111101";
when "0000001011" => data <= "100000000";
when "0000001100" => data <= "100001100";
when "0000001101" => data <= "100100011";
when "0000001110" => data <= "100000001";
when "0000001111" => data <= "011111111";
when "0000010000" => data <= "011101111";
when "0000010001" => data <= "101110110";
when "0000010010" => data <= "101000000";
when "0000010011" => data <= "100000000";
when "0000010100" => data <= "100001111";
when "0000010101" => data <= "011111111";
when "0000010110" => data <= "011101111";
when "0000010111" => data <= "101110110";
when "0000011000" => data <= "101000000";
when "0000011001" => data <= "100010101";
when "0000011010" => data <= "100000001";
when "0000011011" => data <= "011111111";
when "0000011100" => data <= "101110110";
when "0000011101" => data <= "101000000";
when "0000011110" => data <= "100001010";
when "0000011111" => data <= "100000001";
when "0000100000" => data <= "011111111";
when "0000100001" => data <= "101110110";
when "0000100010" => data <= "101000000";
when "0000100011" => data <= "100001011";
when "0000100100" => data <= "100000101";
when "0000100101" => data <= "011111111";
when "0000100110" => data <= "101110110";
when "0000100111" => data <= "101000000";
when "0000101000" => data <= "100001100";
when "0000101001" => data <= "100000001";
when "0000101010" => data <= "011111111";
when "0000101011" => data <= "101110110";
when "0000101100" => data <= "101000000";
when "0000101101" => data <= "100001101";
when "0000101110" => data <= "100000101";
when "0000101111" => data <= "011111111";
when "0000110000" => data <= "101110110";
when "0000110001" => data <= "101000000";
when "0000110010" => data <= "100011100";
when "0000110011" => data <= "100100001";
when "0000110100" => data <= "011111111";
when "0000110101" => data <= "101110110";
when "0000110110" => data <= "101000000";
when "0000110111" => data <= "100011110";
when "0000111000" => data <= "101000001";
when "0000111001" => data <= "011111111";
when "0000111010" => data <= "101110110";
when "0000111011" => data <= "101000000";
when "0000111100" => data <= "100100011";
when "0000111101" => data <= "111100111";
when "0000111110" => data <= "011111111";
when "0000111111" => data <= "101110110";
when "0001000000" => data <= "101000000";
when "0001000001" => data <= "100100100";
when "0001000010" => data <= "111100111";
when "0001000011" => data <= "011111111";
when "0001000100" => data <= "101110110";
when "0001000101" => data <= "101000000";
when "0001000110" => data <= "100100101";
when "0001000111" => data <= "111100111";
when "0001001000" => data <= "011111111";
when "0001001001" => data <= "101110110";
when "0001001010" => data <= "101000000";
when "0001001011" => data <= "100100110";
when "0001001100" => data <= "111100111";
when "0001001101" => data <= "011111111";
when "0001001110" => data <= "101110110";
when "0001001111" => data <= "101000000";
when "0001010000" => data <= "100011001";
when "0001010001" => data <= "100000011";
when "0001010010" => data <= "011111111";
when "0001010011" => data <= "101110110";
when "0001010100" => data <= "101000000";
when "0001010101" => data <= "100101001";
when "0001010110" => data <= "100000011";
when "0001010111" => data <= "011111111";
when "0001011000" => data <= "101110110";
when "0001011001" => data <= "101000000";
when "0001011010" => data <= "100101010";
when "0001011011" => data <= "100000011";
when "0001011100" => data <= "011111111";
when "0001011101" => data <= "101110110";
when "0001011110" => data <= "101000000";
when "0001011111" => data <= "111110010";
when "0001100000" => data <= "100000001";
when "0001100001" => data <= "011111111";
when "0001100010" => data <= "101110110";
when "0001100011" => data <= "101000000";
when "0001100100" => data <= "111110011";
when "0001100101" => data <= "100000001";
when "0001100110" => data <= "011111111";
when "0001100111" => data <= "101110110";
when "0001101000" => data <= "101000000";
when "0001101001" => data <= "111111001";
when "0001101010" => data <= "101111111";
when "0001101011" => data <= "011111111";
when "0001101100" => data <= "101110110";
when "0001101101" => data <= "101000000";
when "0001101110" => data <= "111111010";
when "0001101111" => data <= "100000011";
when "0001110000" => data <= "011111111";
when "0001110001" => data <= "011111110";
when "0001110010" => data <= "011111110";
when "0001110011" => data <= "011111110";
when "0001110100" => data <= "011111110";
when "0001110101" => data <= "011111110";
when "0001110110" => data <= "011111110";
when "0001110111" => data <= "011111110";
when "0001111000" => data <= "011101111";
when "0001111001" => data <= "000001111";
when others => data <= (others =>'0');
end case;
end if;
end process;
end Behavioral;
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