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-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant0.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant0 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END lpm_constant0;
ARCHITECTURE SYN OF lpm_constant0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(0 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I3",
lpm_type => "LPM_CONSTANT",
lpm_width => 1
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "I3"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I3"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]"
-- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- Courtesy of Brian Padalino
--
library ieee ;
use ieee.std_logic_1164.all ;
entity memory is
generic (
DEPTH : positive
) ;
port (
clock : in std_logic ;
write_addr : in natural range 0 to DEPTH-1 ;
write_data : in std_logic_vector ;
write_valid : in std_logic ;
read_addr : in natural range 0 to DEPTH-1 ;
read_data : out std_logic_vector ;
read_valid : in std_logic
) ;
end entity ;
architecture arch of memory is
type mem_t is array(natural range 0 to DEPTH-1) of std_logic_vector(write_data'range) ;
signal mem : mem_t := (others =>(others =>'0')) ;
begin
process(all)
begin
if( rising_edge(clock) ) then
if( write_valid = '1' ) then
mem(write_addr) <= write_data ;
end if ;
if( read_valid = '1' ) then
read_data <= mem(read_addr) ;
end if ;
end if ;
end process ;
end architecture ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.math_real.all ;
entity traffic_gen is
generic (
WIDTH : positive ;
DEPTH : positive ;
SEED : positive
) ;
port (
clock : in std_logic ;
write_addr : out natural range 0 to DEPTH-1 ;
write_data : out std_logic_vector(WIDTH-1 downto 0) ;
write_valid : out std_logic ;
read_addr : out natural range 0 to DEPTH-1 ;
read_valid : out std_logic
) ;
end entity ;
architecture arch of traffic_gen is
type rng_t is record
s1 : positive ;
s2 : positive ;
end record ;
procedure rand_std_logic(variable rng : inout rng_t ; signal y : out std_logic) is
variable r : real ;
begin
uniform(rng.s1, rng.s2, r) ;
y <= '1' when r > 0.5 else '0' ;
end procedure ;
procedure rand_slv(variable rng : inout rng_t ; signal y : out std_logic_vector) is
variable r : real ;
begin
for i in y'range loop
uniform(rng.s1, rng.s2, r) ;
y(i) <= '1' when r > 0.5 else '0' ;
end loop ;
end procedure ;
procedure rand_natural(variable rng : inout rng_t ; max : in positive ; signal y : out natural) is
variable r : real ;
begin
uniform(rng.s1, rng.s2, r) ;
y <= natural(real(max) * r) ;
end procedure ;
procedure randomize_write(variable rng : inout rng_t ; signal addr : out natural range 0 to DEPTH-1 ; signal data : out std_logic_vector(WIDTH-1 downto 0) ; signal valid : out std_logic ) is
begin
rand_natural(rng, DEPTH-1, addr) ;
rand_slv(rng, data) ;
rand_std_logic(rng, valid) ;
end procedure ;
procedure randomize_read(variable rng : inout rng_t ; signal addr : out natural range 0 to DEPTH-1 ; signal valid : out std_logic ) is
begin
rand_natural(rng, DEPTH-1, addr) ;
rand_std_logic(rng, valid) ;
end procedure ;
function create_rng(s1, s2 : in positive) return rng_t is
variable rv : rng_t ;
begin
rv.s1 := s1 ;
rv.s2 := s2 ;
return rv ;
end function ;
begin
process(all)
variable write_rng : rng_t := create_rng(SEED+WIDTH+DEPTH, SEED*WIDTH*DEPTH) ;
variable read_rng : rng_t := create_rng(SEED+WIDTH*DEPTH, SEED*WIDTH+DEPTH) ;
begin
if( rising_edge(clock) ) then
randomize_write(write_rng, write_addr, write_data, write_valid) ;
randomize_read(read_rng, read_addr, read_valid) ;
end if ;
end process ;
end architecture ;
library ieee ;
use ieee.std_logic_1164.all ;
entity grind is
generic (
MEMORY_WIDTH : positive := 256 ;
MEMORY_DEPTH : positive := 32768 ;
NUM_INSTANCES : positive := 128
) ;
end entity ;
architecture arch of grind is
subtype data_t is std_logic_vector(MEMORY_WIDTH-1 downto 0) ;
subtype addr_t is natural range 0 to MEMORY_DEPTH-1 ;
type datas_t is array(natural range 0 to NUM_INSTANCES-1) of data_t ;
type addrs_t is array(natural range 0 to NUM_INSTANCES-1) of addr_t ;
signal clock : std_logic := '0' ;
signal write_addrs : addrs_t ;
signal write_datas : datas_t ;
signal write_valids : std_logic_vector(0 to NUM_INSTANCES-1) ;
signal read_addrs : addrs_t ;
signal read_datas : datas_t ;
signal read_valids : std_logic_vector(0 to NUM_INSTANCES-1) ;
begin
clock <= not clock after 1 ns ;
create_memories : for i in write_addrs'range generate
U_traffic_gen : entity work.traffic_gen
generic map (
WIDTH => data_t'length,
DEPTH => MEMORY_DEPTH,
SEED => i+1
) port map (
clock => clock,
write_addr => write_addrs(i),
write_data => write_datas(i),
write_valid => write_valids(i),
read_addr => read_addrs(i),
read_valid => read_valids(i)
) ;
U_mem : entity work.memory
generic map (
DEPTH => MEMORY_DEPTH
) port map (
clock => clock,
write_addr => write_addrs(i),
write_data => write_datas(i),
write_valid => write_valids(i),
read_addr => read_addrs(i),
read_data => read_datas(i),
read_valid => read_valids(i)
) ;
end generate ;
tb : process
variable t : time := 35 us ;
begin
report "Starting testbench for " & time'image(t) ;
wait for t ;
report "Finished" ;
std.env.stop ;
end process ;
end architecture ;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity keyb_jed is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(1 downto 0)
);
end keyb_jed;
architecture behaviour of keyb_jed is
constant st0: std_logic_vector(4 downto 0) := "10100";
constant st1: std_logic_vector(4 downto 0) := "10111";
constant st2: std_logic_vector(4 downto 0) := "10110";
constant st3: std_logic_vector(4 downto 0) := "10010";
constant st4: std_logic_vector(4 downto 0) := "11000";
constant st5: std_logic_vector(4 downto 0) := "10000";
constant st6: std_logic_vector(4 downto 0) := "00000";
constant st7: std_logic_vector(4 downto 0) := "11110";
constant st8: std_logic_vector(4 downto 0) := "11100";
constant st9: std_logic_vector(4 downto 0) := "11001";
constant st10: std_logic_vector(4 downto 0) := "11101";
constant st11: std_logic_vector(4 downto 0) := "10101";
constant st12: std_logic_vector(4 downto 0) := "10001";
constant st13: std_logic_vector(4 downto 0) := "00101";
constant st14: std_logic_vector(4 downto 0) := "00100";
constant st15: std_logic_vector(4 downto 0) := "01000";
constant st16: std_logic_vector(4 downto 0) := "01100";
constant st17: std_logic_vector(4 downto 0) := "11010";
constant st18: std_logic_vector(4 downto 0) := "00110";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "---0000") then next_state <= st1; output <= "1-";
elsif std_match(input, "---0100") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0010") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0001") then next_state <= st2; output <= "1-";
elsif std_match(input, "---1100") then next_state <= st3; output <= "1-";
elsif std_match(input, "---1000") then next_state <= st3; output <= "1-";
elsif std_match(input, "---011-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---01-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---101-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---10-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---111-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st1 =>
if std_match(input, "0000000") then next_state <= st4; output <= "1-";
elsif std_match(input, "1000000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0100000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0010000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0001000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "11-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1--1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "1---1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "1----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st2 =>
if std_match(input, "0000000") then next_state <= st5; output <= "--";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st3 =>
if std_match(input, "0000000") then next_state <= st6; output <= "1-";
elsif std_match(input, "0011000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st4 =>
if std_match(input, "-000000") then next_state <= st7; output <= "1-";
elsif std_match(input, "-100000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-010000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-001000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st5 =>
if std_match(input, "-000000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st6 =>
if std_match(input, "-011000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000000") then next_state <= st9; output <= "1-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st7 =>
if std_match(input, "--00000") then next_state <= st10; output <= "1-";
elsif std_match(input, "--10000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st8 =>
if std_match(input, "--00000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st9 =>
if std_match(input, "--00000") then next_state <= st12; output <= "--";
elsif std_match(input, "--11000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st10 =>
if std_match(input, "----000") then next_state <= st13; output <= "1-";
elsif std_match(input, "----100") then next_state <= st14; output <= "0-";
elsif std_match(input, "----010") then next_state <= st14; output <= "0-";
elsif std_match(input, "----001") then next_state <= st14; output <= "0-";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st11 =>
if std_match(input, "----000") then next_state <= st14; output <= "0-";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st12 =>
if std_match(input, "-----00") then next_state <= st14; output <= "--";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st13 =>
if std_match(input, "-----00") then next_state <= st15; output <= "1-";
elsif std_match(input, "-----10") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----01") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st14 =>
if std_match(input, "-----00") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st15 =>
if std_match(input, "------0") then next_state <= st17; output <= "--";
elsif std_match(input, "------1") then next_state <= st18; output <= "0-";
end if;
when st16 =>
if std_match(input, "------0") then next_state <= st18; output <= "0-";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st17 =>
if std_match(input, "-------") then next_state <= st0; output <= "-0";
end if;
when st18 =>
if std_match(input, "-------") then next_state <= st0; output <= "-1";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_04.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity processor is
end entity processor;
-- code from book
architecture rtl of processor is
component latch is
generic ( width : positive );
port ( d : in std_ulogic_vector(0 to width - 1);
q : out std_ulogic_vector(0 to width - 1);
-- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component latch;
component ROM is
port ( d_out : out std_ulogic_vector; -- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component ROM;
subtype std_logic_word is std_logic_vector(0 to 31);
signal source1, source2, destination : std_logic_word;
-- . . .
begin
temp_register : component latch
generic map ( width => 32 )
port map ( d => std_ulogic_vector(destination),
std_logic_vector(q) => source1, -- . . . );
-- not in book
other_port => open );
-- end not in book
constant_ROM : component ROM
port map ( std_logic_word(d_out) => source2, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture rtl;
-- end code from book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_04.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity processor is
end entity processor;
-- code from book
architecture rtl of processor is
component latch is
generic ( width : positive );
port ( d : in std_ulogic_vector(0 to width - 1);
q : out std_ulogic_vector(0 to width - 1);
-- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component latch;
component ROM is
port ( d_out : out std_ulogic_vector; -- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component ROM;
subtype std_logic_word is std_logic_vector(0 to 31);
signal source1, source2, destination : std_logic_word;
-- . . .
begin
temp_register : component latch
generic map ( width => 32 )
port map ( d => std_ulogic_vector(destination),
std_logic_vector(q) => source1, -- . . . );
-- not in book
other_port => open );
-- end not in book
constant_ROM : component ROM
port map ( std_logic_word(d_out) => source2, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture rtl;
-- end code from book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_fg_21_04.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity processor is
end entity processor;
-- code from book
architecture rtl of processor is
component latch is
generic ( width : positive );
port ( d : in std_ulogic_vector(0 to width - 1);
q : out std_ulogic_vector(0 to width - 1);
-- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component latch;
component ROM is
port ( d_out : out std_ulogic_vector; -- . . . );
-- not in book
other_port : in std_ulogic := '-' );
-- end not in book
end component ROM;
subtype std_logic_word is std_logic_vector(0 to 31);
signal source1, source2, destination : std_logic_word;
-- . . .
begin
temp_register : component latch
generic map ( width => 32 )
port map ( d => std_ulogic_vector(destination),
std_logic_vector(q) => source1, -- . . . );
-- not in book
other_port => open );
-- end not in book
constant_ROM : component ROM
port map ( std_logic_word(d_out) => source2, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture rtl;
-- end code from book
|
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|
---------------------------------------------------------------------------------------------------
--
-- Title : ethrx_task
-- Design : eth_new
-- Author : dove
-- Company : google
--
---------------------------------------------------------------------------------------------------
--
-- File : ethrx_task.vhd
-- Generated : Sun Sep 3 10:52:10 2006
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description :
--
---------------------------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {ethrx_task} architecture {arch_ethrx_task}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ethrx_task is
generic(
TASKFIFO_DWIDTH : natural := 8;
TASKFIFO_BLOCK_DEPTH : natural := 16;
TASKFIFO_BLOCK_AWIDTH : natural := 4;
TASKFIFO_DEPTH : natural := 16;
TASKFIFO_AWIDTH : natural := 4;
TASKFIFO_RAM_TYPE : string := "DIS_RAM"
);
port(
reset : in std_logic;
-- Task Input
RxFIFO_R_Clk : in std_logic;
RxFIFO_R_Block : in std_logic;
RxFIFO_RAddr : in std_logic_vector( TASKFIFO_BLOCK_AWIDTH - 1 downto 0 );
RxFIFO_RData : out std_logic_vector( TASKFIFO_DWIDTH - 1 downto 0 );
RxFIFO_Full : out std_logic;
RxFIFO_Empty : out std_logic;
fifo_wr_block : in std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end ethrx_task;
--}} End of automatically maintained section
architecture arch_ethrx_task of ethrx_task is
component fifo_block
generic(
DWIDTH : INTEGER;
BLOCK_AWIDTH : INTEGER;
FIFO_AWIDTH : INTEGER;
RAM_TYPE : STRING
);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
wr_block : in std_logic;
wr_clk : in std_logic;
wren : in std_logic;
waddr : in std_logic_vector((BLOCK_AWIDTH-1) downto 0);
wdata : in std_logic_vector((DWIDTH-1) downto 0);
rd_block : in std_logic;
rd_clk : in std_logic;
raddr : in std_logic_vector((BLOCK_AWIDTH-1) downto 0);
rdata : out std_logic_vector((DWIDTH-1) downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
component zcpsm2fifo
generic(
BLOCK_AWIDTH : INTEGER;
DWIDTH : INTEGER
);
port(
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0);
fifo_wr_block : out std_logic;
fifo_wren : out std_logic;
fifo_waddr : out std_logic_vector((BLOCK_AWIDTH-1) downto 0);
fifo_wdata : out std_logic_vector((DWIDTH-1) downto 0);
fifo_full : in std_logic;
fifo_empty : in std_logic
);
end component;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_wren : std_logic;
signal fifo_waddr : std_logic_vector(TASKFIFO_BLOCK_AWIDTH - 1 downto 0);
signal fifo_wdata : std_logic_vector(TASKFIFO_DWIDTH - 1 downto 0);
signal fifo_db_wr_block : std_logic;
signal fifo_rxtask_wr_block : std_logic;
-- signal fifo_wr_block : std_logic;
begin
fifo_rxtask_wr_block <= fifo_db_wr_block or fifo_wr_block;
u_rx_task_fifo : fifo_block
generic map(
DWIDTH => TASKFIFO_DWIDTH,
BLOCK_AWIDTH => TASKFIFO_BLOCK_AWIDTH,
FIFO_AWIDTH => TASKFIFO_AWIDTH,
RAM_TYPE => TASKFIFO_RAM_TYPE
)
port map(
clk => RxFIFO_R_Clk,
reset => reset,
clr => '0',
wr_block => fifo_rxtask_wr_block,
wr_clk => zcpsm_clk,
wren => fifo_wren,
waddr => fifo_waddr,
wdata => fifo_wdata,
rd_block => RxFIFO_R_Block,
rd_clk => RxFIFO_R_Clk,
raddr => RxFIFO_RAddr,
rdata => RxFIFO_RData,
empty => fifo_empty,
full => fifo_full
);
u_rx_zcpsm_task : zcpsm2fifo
generic map(
BLOCK_AWIDTH => TASKFIFO_BLOCK_AWIDTH,
DWIDTH => TASKFIFO_DWIDTH
)
port map(
clk => RxFIFO_R_Clk,
reset => reset,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => zcpsm_ce,
zcpsm_port_id => zcpsm_port_id,
zcpsm_write_strobe => zcpsm_write_strobe,
zcpsm_out_port => zcpsm_out_port,
zcpsm_read_strobe => zcpsm_read_strobe,
zcpsm_in_port => zcpsm_in_port,
-- fifo_wr_block => open,
fifo_wr_block => fifo_db_wr_block,
fifo_wren => fifo_wren,
fifo_waddr => fifo_waddr,
fifo_wdata => fifo_wdata,
fifo_full => fifo_full,
fifo_empty => fifo_empty
);
RxFIFO_Empty <= fifo_empty;
RxFIFO_Full <= fifo_full;
-- enter your statements here --
end arch_ethrx_task;
|
--
-- Author: Pawel Szostek ([email protected])
-- Date: 28.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity dummy is
port (
input : in std_logic_vector(7 downto 0);
output : out std_logic_vector(7 downto 0)
);
end;
architecture behaviour of dummy is
begin
L: process(input)
variable tmp : std_logic_vector(7 downto 0);
begin
tmp := input; -- use multiple assignments to the same variable
tmp := (7 => input(7), others => '1'); -- inluding slices in a process
output <= tmp;
end process;
end;
|
--
-- Author: Pawel Szostek ([email protected])
-- Date: 28.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity dummy is
port (
input : in std_logic_vector(7 downto 0);
output : out std_logic_vector(7 downto 0)
);
end;
architecture behaviour of dummy is
begin
L: process(input)
variable tmp : std_logic_vector(7 downto 0);
begin
tmp := input; -- use multiple assignments to the same variable
tmp := (7 => input(7), others => '1'); -- inluding slices in a process
output <= tmp;
end process;
end;
|
-------------------------------------------------------------------------------
-- $Id: upcnt_n.vhd,v 1.1.2.1 2010/03/25 15:33:04 sanjayk Exp $
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
|
-------------------------------------------------------------------------------
-- $Id: upcnt_n.vhd,v 1.1.2.1 2010/03/25 15:33:04 sanjayk Exp $
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
|
-------------------------------------------------------------------------------
-- $Id: upcnt_n.vhd,v 1.1.2.1 2010/03/25 15:33:04 sanjayk Exp $
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
|
-------------------------------------------------------------------------------
-- $Id: upcnt_n.vhd,v 1.1.2.1 2010/03/25 15:33:04 sanjayk Exp $
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
|
-------------------------------------------------------------------------------
-- $Id: upcnt_n.vhd,v 1.1.2.1 2010/03/25 15:33:04 sanjayk Exp $
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
|
-------------------------------------------------------------------------------
-- $Id: upcnt_n.vhd,v 1.1.2.1 2010/03/25 15:33:04 sanjayk Exp $
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
|
-------------------------------------------------------------------------------
-- $Id: upcnt_n.vhd,v 1.1.2.1 2010/03/25 15:33:04 sanjayk Exp $
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
|
library verilog;
use verilog.vl_types.all;
entity projeto is
port(
SW : in vl_logic_vector(7 downto 0);
HEX0 : out vl_logic_vector(6 downto 0);
HEX1 : out vl_logic_vector(6 downto 0)
);
end projeto;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_bb_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:44:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_bb_e-rtl-a.vhd,v 1.2 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_bb_e-rtl-a.vhd,v $
-- Revision 1.2 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
udc: HEAD HOOK inst_bb_i
--
--
-- Start of Generated Architecture rtl of inst_bb_e
--
architecture rtl of inst_bb_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
udc: DECL HOOK VHDL inst_bb_i
begin
udc: BODY BOOK VHDL inst_bb_i
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
udc: FOOT HOOK two lines inst_bb_i
second line inst_bb_i, config here inst_bb_e_rtl_conf and description bb instance
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MC6808CpuMonLX9.vhd
-- /___/ /\ Timestamp : 24/10/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MC6808CpuMonLX9
--Device: XC3S250E/XC3S500E
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MC6809CpuMonLX9 is
generic (
num_comparators : integer := 8; -- default value correct for LX9
avr_prog_mem_size : integer := 1024 * 9 -- default value correct for LX9
);
port (
clock : in std_logic;
-- A locally generated test clock
-- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
-- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
clock_test : out std_logic;
-- 6809/6809E mode selection
-- Jumper is between pins B1 and D1
-- Jumper off is 6809 mode, where a 4x clock should be fed into EXTAL (PIN38)
-- Jumper on is 6909E mode, where a 1x clock should be fed into E (PIN34)
EMode_n : in std_logic;
--6809 Signals
PIN33 : inout std_logic;
PIN34 : inout std_logic;
PIN35 : inout std_logic;
PIN36 : inout std_logic;
PIN38 : inout std_logic;
PIN39 : in std_logic;
-- Signals common to both 6809 and 6809E
RES_n : in std_logic;
NMI_n : in std_logic;
IRQ_n : in std_logic;
FIRQ_n : in std_logic;
HALT_n : in std_logic;
BS : out std_logic;
BA : out std_logic;
R_W_n : out std_logic;
Addr : out std_logic_vector(15 downto 0);
Data : inout std_logic_vector(7 downto 0);
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- LX9 Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- LX9 LEDs
led3 : out std_logic;
led6 : out std_logic;
led8 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic;
-- Debugging signals
test1 : out std_logic;
test2 : out std_logic
);
end MC6809CpuMonLX9;
architecture behavioral of MC6809CpuMonLX9 is
signal clk_count : std_logic_vector(1 downto 0);
signal quadrature : std_logic_vector(1 downto 0);
signal clock7_3728 : std_logic;
signal sw_reset_avr : std_logic;
signal sw_reset_cpu : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
signal E : std_logic;
signal Q : std_logic;
signal DMA_n_BREQ_n : std_logic;
signal MRDY : std_logic;
signal TSC : std_logic;
signal LIC : std_logic;
signal AVMA : std_logic;
signal BUSY : std_logic;
signal XTAL : std_logic;
signal EXTAL : std_logic;
begin
sw_reset_cpu <= sw1;
sw_reset_avr <= sw2;
led3 <= led_trig0;
led6 <= led_trig1;
led8 <= led_bkpt;
wrapper : entity work.MC6809CpuMon
generic map (
ClkMult => 8,
ClkDiv => 25,
ClkPer => 20.000,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
-- Fast clock
clock => clock,
-- Quadrature clocks
E => E,
Q => Q,
--6809 Signals
DMA_n_BREQ_n => DMA_n_BREQ_n,
-- 6809E Sig
TSC => TSC,
LIC => LIC,
AVMA => AVMA,
BUSY => BUSY,
-- Signals common to both 6809 and 6809E
RES_n => RES_n,
NMI_n => NMI_n,
IRQ_n => IRQ_n,
FIRQ_n => FIRQ_n,
HALT_n => HALT_n,
BS => BS,
BA => BA,
R_W_n => R_W_n,
Addr => Addr,
Data => Data,
-- External trigger inputs
trig => trig,
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 connected to test connector
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
-- Debugging signals
test1 => test1,
test2 => test2
);
-- Pins whose functions are dependent on "E" mode
PIN33 <= BUSY when EMode_n = '0' else 'Z';
DMA_n_BREQ_n <= '1' when EMode_n = '0' else PIN33;
PIN34 <= 'Z' when EMode_n = '0' else E;
E <= PIN34 when EMode_n = '0' else quadrature(1);
PIN35 <= 'Z' when EMode_n = '0' else Q;
Q <= PIN35 when EMode_n = '0' else quadrature(0);
PIN36 <= AVMA when EMode_n = '0' else 'Z';
MRDY <= '1' when EMode_n = '0' else PIN36;
PIN38 <= LIC when EMode_n = '0' else 'Z';
EXTAL <= '0' when EMode_n = '0' else PIN38;
TSC <= PIN39 when EMode_n = '0' else '0';
XTAL <= '0' when EMode_n = '0' else PIN39;
-- A locally generated test clock
-- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
-- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
clock_test <= clk_count(1) when EMode_n = '0' else clock7_3728;
-- Quadrature clock generator, unused in 6809E mode
quadrature_gen : process(EXTAL)
begin
if rising_edge(EXTAL) then
if (MRDY = '1') then
if (quadrature = "00") then
quadrature <= "01";
elsif (quadrature = "01") then
quadrature <= "11";
elsif (quadrature = "11") then
quadrature <= "10";
else
quadrature <= "00";
end if;
end if;
end if;
end process;
-- Seperate piece of circuitry that emits a 7.3728MHz clock
inst_dcm1 : entity work.DCM1 port map(
CLKIN_IN => clock,
CLK0_OUT => clock7_3728,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
clk_gen : process(clock7_3728)
begin
if rising_edge(clock7_3728) then
clk_count <= clk_count + 1;
end if;
end process;
end behavioral;
|
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MC6808CpuMonLX9.vhd
-- /___/ /\ Timestamp : 24/10/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MC6808CpuMonLX9
--Device: XC3S250E/XC3S500E
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MC6809CpuMonLX9 is
generic (
num_comparators : integer := 8; -- default value correct for LX9
avr_prog_mem_size : integer := 1024 * 9 -- default value correct for LX9
);
port (
clock : in std_logic;
-- A locally generated test clock
-- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
-- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
clock_test : out std_logic;
-- 6809/6809E mode selection
-- Jumper is between pins B1 and D1
-- Jumper off is 6809 mode, where a 4x clock should be fed into EXTAL (PIN38)
-- Jumper on is 6909E mode, where a 1x clock should be fed into E (PIN34)
EMode_n : in std_logic;
--6809 Signals
PIN33 : inout std_logic;
PIN34 : inout std_logic;
PIN35 : inout std_logic;
PIN36 : inout std_logic;
PIN38 : inout std_logic;
PIN39 : in std_logic;
-- Signals common to both 6809 and 6809E
RES_n : in std_logic;
NMI_n : in std_logic;
IRQ_n : in std_logic;
FIRQ_n : in std_logic;
HALT_n : in std_logic;
BS : out std_logic;
BA : out std_logic;
R_W_n : out std_logic;
Addr : out std_logic_vector(15 downto 0);
Data : inout std_logic_vector(7 downto 0);
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- LX9 Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- LX9 LEDs
led3 : out std_logic;
led6 : out std_logic;
led8 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic;
-- Debugging signals
test1 : out std_logic;
test2 : out std_logic
);
end MC6809CpuMonLX9;
architecture behavioral of MC6809CpuMonLX9 is
signal clk_count : std_logic_vector(1 downto 0);
signal quadrature : std_logic_vector(1 downto 0);
signal clock7_3728 : std_logic;
signal sw_reset_avr : std_logic;
signal sw_reset_cpu : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
signal E : std_logic;
signal Q : std_logic;
signal DMA_n_BREQ_n : std_logic;
signal MRDY : std_logic;
signal TSC : std_logic;
signal LIC : std_logic;
signal AVMA : std_logic;
signal BUSY : std_logic;
signal XTAL : std_logic;
signal EXTAL : std_logic;
begin
sw_reset_cpu <= sw1;
sw_reset_avr <= sw2;
led3 <= led_trig0;
led6 <= led_trig1;
led8 <= led_bkpt;
wrapper : entity work.MC6809CpuMon
generic map (
ClkMult => 8,
ClkDiv => 25,
ClkPer => 20.000,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
-- Fast clock
clock => clock,
-- Quadrature clocks
E => E,
Q => Q,
--6809 Signals
DMA_n_BREQ_n => DMA_n_BREQ_n,
-- 6809E Sig
TSC => TSC,
LIC => LIC,
AVMA => AVMA,
BUSY => BUSY,
-- Signals common to both 6809 and 6809E
RES_n => RES_n,
NMI_n => NMI_n,
IRQ_n => IRQ_n,
FIRQ_n => FIRQ_n,
HALT_n => HALT_n,
BS => BS,
BA => BA,
R_W_n => R_W_n,
Addr => Addr,
Data => Data,
-- External trigger inputs
trig => trig,
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 connected to test connector
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
-- Debugging signals
test1 => test1,
test2 => test2
);
-- Pins whose functions are dependent on "E" mode
PIN33 <= BUSY when EMode_n = '0' else 'Z';
DMA_n_BREQ_n <= '1' when EMode_n = '0' else PIN33;
PIN34 <= 'Z' when EMode_n = '0' else E;
E <= PIN34 when EMode_n = '0' else quadrature(1);
PIN35 <= 'Z' when EMode_n = '0' else Q;
Q <= PIN35 when EMode_n = '0' else quadrature(0);
PIN36 <= AVMA when EMode_n = '0' else 'Z';
MRDY <= '1' when EMode_n = '0' else PIN36;
PIN38 <= LIC when EMode_n = '0' else 'Z';
EXTAL <= '0' when EMode_n = '0' else PIN38;
TSC <= PIN39 when EMode_n = '0' else '0';
XTAL <= '0' when EMode_n = '0' else PIN39;
-- A locally generated test clock
-- 1.8457 MHz in E Mode (6809E) so it can drive E (PIN34)
-- 7.3728 MHz in Normal Mode (6809) so it can drive EXTAL (PIN38)
clock_test <= clk_count(1) when EMode_n = '0' else clock7_3728;
-- Quadrature clock generator, unused in 6809E mode
quadrature_gen : process(EXTAL)
begin
if rising_edge(EXTAL) then
if (MRDY = '1') then
if (quadrature = "00") then
quadrature <= "01";
elsif (quadrature = "01") then
quadrature <= "11";
elsif (quadrature = "11") then
quadrature <= "10";
else
quadrature <= "00";
end if;
end if;
end if;
end process;
-- Seperate piece of circuitry that emits a 7.3728MHz clock
inst_dcm1 : entity work.DCM1 port map(
CLKIN_IN => clock,
CLK0_OUT => clock7_3728,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
clk_gen : process(clock7_3728)
begin
if rising_edge(clock7_3728) then
clk_count <= clk_count + 1;
end if;
end process;
end behavioral;
|
library verilog;
use verilog.vl_types.all;
entity counter_max10 is
port(
clk : in vl_logic;
reset : in vl_logic;
limit : in vl_logic;
carry : out vl_logic;
CountedNumber : out vl_logic_vector(3 downto 0)
);
end counter_max10;
|
-- Copyright (c) 2014 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for expression concatenation in VHDL.
library ieee;
use ieee.std_logic_1164.all;
entity concat is
end concat;
architecture test of concat is
signal concat1 : std_logic_vector(1 downto 0);
signal concat2 : std_logic_vector(0 to 4);
begin
concat1 <= '1' & '0';
concat2 <= '1' & "10" & concat1;
end test;
|
-- Copyright (c) 2014 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for expression concatenation in VHDL.
library ieee;
use ieee.std_logic_1164.all;
entity concat is
end concat;
architecture test of concat is
signal concat1 : std_logic_vector(1 downto 0);
signal concat2 : std_logic_vector(0 to 4);
begin
concat1 <= '1' & '0';
concat2 <= '1' & "10" & concat1;
end test;
|
-- Copyright (c) 2014 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for expression concatenation in VHDL.
library ieee;
use ieee.std_logic_1164.all;
entity concat is
end concat;
architecture test of concat is
signal concat1 : std_logic_vector(1 downto 0);
signal concat2 : std_logic_vector(0 to 4);
begin
concat1 <= '1' & '0';
concat2 <= '1' & "10" & concat1;
end test;
|
-------------------------------------------------------------------------------
-- axi_lite.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: axi_lite.vhd
--
-- Description: This file is the top level module for the AXI-Lite
-- instantiation of the BRAM controller interface.
--
-- Responsible for shared address pipelining between the
-- write address (AW) and read address (AR) channels.
-- Controls (seperately) the data flows for the write data
-- (W), write response (B), and read data (R) channels.
--
-- Creates a shared port to BRAM (for all read and write
-- transactions) or dual BRAM port utilization based on a
-- generic parameter setting.
--
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- ecc_gen.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Update BRAM address mapping to lite_ecc_reg module. Corrected
-- signal size for XST detected unused bits in vector.
-- Plus minor code cleanup.
--
-- Add top level parameter, C_ECC_TYPE for Hsiao ECC algorithm.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Add Hsiao ECC algorithm logic (similar to full_axi module HDL).
-- ^^^^^^
-- JLJ 2/24/2011 v1.03a
-- ~~~~~~
-- Move REG_RDATA register process out from C_ECC_TYPE generate block
-- to C_ECC generate block.
-- ^^^^^^
-- JLJ 3/22/2011 v1.03a
-- ~~~~~~
-- Add LUT level with reset signal to combinatorial outputs, AWREADY
-- and WREADY. This will ensure that the output remains LOW during reset,
-- regardless of AWVALID or WVALID input signals.
-- ^^^^^^
-- JLJ 3/28/2011 v1.03a
-- ~~~~~~
-- Remove combinatorial output paths on AWREADY and WREADY.
-- Combine AWREADY and WREADY registers.
-- Remove combinatorial output path on ARREADY. Can pre-assert ARREADY
-- (but only for non ECC configurations).
-- Create 3-bit counter for BVALID response, seperate from AW/W channels.
--
-- Delay assertion of WREADY in ECC configurations to minimize register
-- resource utilization.
-- No pre-assertion of ARREADY in ECC configurations (due to write latency
-- with ECC enabled).
--
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Update Sl_CE and Sl_UE flag assertions to a single clock cycle.
-- Clean up comments.
-- ^^^^^^
-- JLJ 4/19/2011 v1.03a
-- ~~~~~~
-- Update BVALID assertion when ECC is enabled to match the implementation
-- when C_ECC = 0. Optimize back to back write performance when C_ECC = 1.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Modify FaultInjectClr signal assertion. With BVALID counter, delay
-- when fault inject register gets cleared.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Hard code C_USE_LUT6 constant.
-- ^^^^^^
-- JLJ 7/7/2011 v1.03a
-- ~~~~~~
-- Fix DV regression failure with reset.
-- Hold off BRAM enable output with active reset signal.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.lite_ecc_reg;
use work.parity;
use work.checkbit_handler;
use work.correct_one_bit;
use work.ecc_gen;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity axi_lite is
generic (
C_S_AXI_PROTOCOL : string := "AXI4LITE";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_SINGLE_PORT_BRAM : integer := 1;
-- Enable single port usage of BRAM
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_TYPE : integer := 0; -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
C_ECC_ONOFF_RESET_VALUE : integer := 1;
-- By default, ECC checking is on (can disable ECC @ reset by setting this to 0)
-- Hard coded parameters at top level.
-- Note: Kept in design for future enhancement.
C_ENABLE_AXI_CTRL_REG_IF : integer := 0;
-- By default the ECC AXI-Lite register interface is enabled
C_CE_FAILING_REGISTERS : integer := 0;
-- Enable CE (correctable error) failing registers
C_UE_FAILING_REGISTERS : integer := 0;
-- Enable UE (uncorrectable error) failing registers
C_ECC_STATUS_REGISTERS : integer := 0;
-- Enable ECC status registers
C_ECC_ONOFF_REGISTER : integer := 0;
-- Enable ECC on/off control register
C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
ECC_Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic;
-- Unused AW AXI-Lite Signals
-- AXI_AWID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
-- AXI_AWLEN : in std_logic_vector(7 downto 0);
-- AXI_AWSIZE : in std_logic_vector(2 downto 0);
-- AXI_AWBURST : in std_logic_vector(1 downto 0);
-- AXI_AWLOCK : in std_logic; -- Currently unused
-- AXI_AWCACHE : in std_logic_vector(3 downto 0); -- Currently unused
-- AXI_AWPROT : in std_logic_vector(2 downto 0); -- Currently unused
-- *** AXI Write Data Channel Signals (W) ***
AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
AXI_WVALID : in std_logic;
AXI_WREADY : out std_logic;
-- Unused W AXI-Lite Signals
-- AXI_WLAST : in std_logic;
-- *** AXI Write Data Response Channel Signals (B) ***
AXI_BRESP : out std_logic_vector(1 downto 0);
AXI_BVALID : out std_logic;
AXI_BREADY : in std_logic;
-- Unused B AXI-Lite Signals
-- AXI_BID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic;
-- *** AXI Read Data Channel Signals (R) ***
AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
AXI_RRESP : out std_logic_vector(1 downto 0);
AXI_RLAST : out std_logic;
AXI_RVALID : out std_logic;
AXI_RREADY : in std_logic;
-- *** AXI-Lite ECC Register Interface Signals ***
-- AXI-Lite Clock and Reset
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_AClk : in std_logic;
-- S_AXI_CTRL_AResetn : in std_logic;
-- AXI-Lite Write Address Channel Signals (AW)
AXI_CTRL_AWVALID : in std_logic;
AXI_CTRL_AWREADY : out std_logic;
AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_WVALID : in std_logic;
AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_BVALID : out std_logic;
AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
AXI_CTRL_ARVALID : in std_logic;
AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_RVALID : out std_logic;
AXI_CTRL_RREADY : in std_logic;
-- *** BRAM Port A Interface Signals ***
-- Note: Clock handled at top level (axi_bram_ctrl module)
BRAM_En_A : out std_logic;
BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0);
BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC
BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC
-- Note: Remove BRAM_RdData_A port (unused in dual port mode)
-- Platgen will keep port open on BRAM block
-- *** BRAM Port B Interface Signals ***
-- Note: Clock handled at top level (axi_bram_ctrl module)
BRAM_En_B : out std_logic;
BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0);
BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); -- @ port level = 8-bits wide ECC
BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) -- @ port level = 8-bits wide ECC
);
end entity axi_lite;
-------------------------------------------------------------------------------
architecture implementation of axi_lite is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response
constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error
-- For future implementation.
-- constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response
-- constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8);
constant C_BRAM_ADDR_ADJUST : integer := C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR;
constant C_AXI_DATA_WIDTH_BYTES : integer := C_S_AXI_DATA_WIDTH/8;
-- Internal data width based on C_S_AXI_DATA_WIDTH.
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH);
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
-- Remove usage of C_FAMILY.
-- All architectures supporting AXI will support a LUT6.
-- Hard code this internal constant used in ECC algorithm.
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
constant C_USE_LUT6 : boolean := TRUE;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal axi_aresetn_d1 : std_logic := '0';
signal axi_aresetn_re : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type LITE_SM_TYPE is ( IDLE,
SNG_WR_DATA,
RD_DATA,
RMW_RD_DATA,
RMW_MOD_DATA,
RMW_WR_DATA
);
signal lite_sm_cs, lite_sm_ns : LITE_SM_TYPE;
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_reg : std_logic := '0';
signal axi_arready_int : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write Data Channel Signals
-------------------------------------------------------------------------------
signal axi_wready_cmb : std_logic := '0';
signal axi_wready_int : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write Response Channel Signals
-------------------------------------------------------------------------------
signal axi_bresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_bvalid_int : std_logic := '0';
signal bvalid_cnt_inc : std_logic := '0';
signal bvalid_cnt_inc_d1 : std_logic := '0';
signal bvalid_cnt_dec : std_logic := '0';
signal bvalid_cnt : std_logic_vector (2 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- AXI Read Data Channel Signals
-------------------------------------------------------------------------------
signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_rvalid_set : std_logic := '0';
signal axi_rvalid_set_r : std_logic := '0';
signal axi_rvalid_int : std_logic := '0';
signal axi_rlast_set : std_logic := '0';
signal axi_rlast_set_r : std_logic := '0';
signal axi_rlast_int : std_logic := '0';
signal axi_rdata_int : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int_corr : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Internal BRAM Signals
-------------------------------------------------------------------------------
signal bram_we_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH/8+(C_ECC_WIDTH+7)/8-1 downto 0) := (others => '0');
signal bram_en_a_cmb : std_logic := '0';
signal bram_en_b_cmb : std_logic := '0';
signal bram_en_a_int : std_logic := '0';
signal bram_en_b_int : std_logic := '0';
signal bram_addr_a_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_a_int_q : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_b_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal bram_wrdata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Port level signal, 8-bits ECC
-------------------------------------------------------------------------------
-- Internal ECC Signals
-------------------------------------------------------------------------------
signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers
signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register
signal Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal Sl_CE_i : std_logic := '0';
signal Sl_UE_i : std_logic := '0';
signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal FaultInjectECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal CorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
signal UnCorrectedRdData : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
signal CE_Q : std_logic := '0';
signal UE_Q : std_logic := '0';
signal Enable_ECC : std_logic := '0';
signal RdModifyWr_Read : std_logic := '0'; -- Read cycle in read modify write sequence
signal RdModifyWr_Check : std_logic := '0'; -- Read cycle in read modify write sequence
signal RdModifyWr_Modify : std_logic := '0'; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic := '0'; -- Write cycle in read modify write sequence
signal WrData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal WrData_cmb : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal Active_Wr : std_logic := '0';
signal BRAM_Addr_En : std_logic := '0';
signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width
signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Specific to 32-bit ECC
signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to 32-bit ECC
signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- Specific to BRAM data width
signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Specific for 32-bit ECC
signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC
signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI-Lite ECC Register Output Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_REGS
-- Purpose: Generate default values if ECC registers are disabled (or when
-- ECC is disabled).
-- Include both AXI-Lite default signal values & internal
-- core signal values.
---------------------------------------------------------------------------
-- For future implementation.
-- GEN_NO_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) or (C_ECC = 0) generate
GEN_NO_REGS: if (C_ECC = 0) generate
begin
AXI_CTRL_AWREADY <= '0';
AXI_CTRL_WREADY <= '0';
AXI_CTRL_BRESP <= (others => '0');
AXI_CTRL_BVALID <= '0';
AXI_CTRL_ARREADY <= '0';
AXI_CTRL_RDATA <= (others => '0');
AXI_CTRL_RRESP <= (others => '0');
AXI_CTRL_RVALID <= '0';
-- No fault injection
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
-- Interrupt only enabled when ECC status/interrupt registers enabled
ECC_Interrupt <= '0';
ECC_UE <= '0';
BRAM_Addr_En <= '0';
-----------------------------------------------------------------------
-- Generate: GEN_DIS_ECC
-- Purpose: Disable ECC in read path when ECC is disabled in core.
-----------------------------------------------------------------------
GEN_DIS_ECC: if C_ECC = 0 generate
Enable_ECC <= '0';
end generate GEN_DIS_ECC;
-- For future implementation.
--
-- -----------------------------------------------------------------------
-- -- Generate: GEN_EN_ECC
-- -- Purpose: Enable ECC when C_ECC = 1 and no ECC registers are available.
-- -- ECC on/off control register is not accessible (so ECC is always
-- -- enabled in this configuraiton).
-- -----------------------------------------------------------------------
-- GEN_EN_ECC: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 0) generate
-- Enable_ECC <= '1'; -- ECC ON/OFF register can not be enabled (as no ECC
-- -- ECC registers are available. Therefore, ECC
-- -- is always enabled.
-- end generate GEN_EN_ECC;
end generate GEN_NO_REGS;
---------------------------------------------------------------------------
-- Generate: GEN_REGS
-- Purpose: Generate ECC register module when ECC is enabled and
-- ECC registers are enabled.
---------------------------------------------------------------------------
-- For future implementation.
-- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate
GEN_REGS: if (C_ECC = 1) generate
begin
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
-- Description: This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
---------------------------------------------------------------------------
I_LITE_ECC_REG : entity work.lite_ecc_reg
generic map (
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width
C_FAULT_INJECT => C_FAULT_INJECT ,
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk , -- AXI clock
S_AXI_AResetn => S_AXI_AResetn ,
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock
-- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn ,
Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
AXI_CTRL_AWVALID => AXI_CTRL_AWVALID ,
AXI_CTRL_AWREADY => AXI_CTRL_AWREADY ,
AXI_CTRL_AWADDR => AXI_CTRL_AWADDR ,
AXI_CTRL_WDATA => AXI_CTRL_WDATA ,
AXI_CTRL_WVALID => AXI_CTRL_WVALID ,
AXI_CTRL_WREADY => AXI_CTRL_WREADY ,
AXI_CTRL_BRESP => AXI_CTRL_BRESP ,
AXI_CTRL_BVALID => AXI_CTRL_BVALID ,
AXI_CTRL_BREADY => AXI_CTRL_BREADY ,
AXI_CTRL_ARADDR => AXI_CTRL_ARADDR ,
AXI_CTRL_ARVALID => AXI_CTRL_ARVALID ,
AXI_CTRL_ARREADY => AXI_CTRL_ARREADY ,
AXI_CTRL_RDATA => AXI_CTRL_RDATA ,
AXI_CTRL_RRESP => AXI_CTRL_RRESP ,
AXI_CTRL_RVALID => AXI_CTRL_RVALID ,
AXI_CTRL_RREADY => AXI_CTRL_RREADY ,
Enable_ECC => Enable_ECC ,
FaultInjectClr => FaultInjectClr ,
CE_Failing_We => CE_Failing_We ,
CE_CounterReg_Inc => CE_Failing_We ,
Sl_CE => Sl_CE ,
Sl_UE => Sl_UE ,
BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_En => BRAM_Addr_En ,
Active_Wr => Active_Wr ,
FaultInjectData => FaultInjectData ,
FaultInjectECC => FaultInjectECC
);
FaultInjectClr <= '1' when (bvalid_cnt_inc_d1 = '1') else '0';
CE_Failing_We <= '1' when Enable_ECC = '1' and CE_Q = '1' else '0';
Active_Wr <= '1' when (RdModifyWr_Read = '1' or RdModifyWr_Check = '1' or RdModifyWr_Modify = '1' or RdModifyWr_Write = '1') else '0';
-----------------------------------------------------------------------
-- Add register delay on BVALID counter increment
-- Used to clear fault inject register.
REG_BVALID_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bvalid_cnt_inc_d1 <= '0';
else
bvalid_cnt_inc_d1 <= bvalid_cnt_inc;
end if;
end if;
end process REG_BVALID_CNT;
-----------------------------------------------------------------------
end generate GEN_REGS;
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
-- AXI_AWREADY <= axi_awready_cmb;
-- AXI_AWREADY <= '0' when (S_AXI_AResetn = '0') else axi_awready_cmb; -- v1.03a
AXI_AWREADY <= axi_wready_int; -- v1.03a
-- AXI Write Data Channel Output Signals
-- AXI_WREADY <= axi_wready_cmb;
-- AXI_WREADY <= '0' when (S_AXI_AResetn = '0') else axi_wready_cmb; -- v1.03a
AXI_WREADY <= axi_wready_int; -- v1.03a
-- AXI Write Response Channel Output Signals
AXI_BRESP <= axi_bresp_int;
AXI_BVALID <= axi_bvalid_int;
-- AXI Read Address Channel Output Signals
-- AXI_ARREADY <= axi_arready_cmb; -- v1.03a
AXI_ARREADY <= axi_arready_int; -- v1.03a
-- AXI Read Data Channel Output Signals
-- AXI_RRESP <= axi_rresp_int;
AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int;
-- AXI_RDATA <= axi_rdata_int;
-- Move assignment of RDATA to generate statements based on C_ECC.
AXI_RVALID <= axi_rvalid_int;
AXI_RLAST <= axi_rlast_int;
----------------------------------------------------------------------------
-- Need to detect end of reset cycle to assert AWREADY on AXI bus
REG_ARESETN: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
axi_aresetn_d1 <= S_AXI_AResetn;
end if;
end process REG_ARESETN;
-- Create combinatorial RE detect of S_AXI_AResetn
axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0';
----------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
-- Notes:
-- No address pipelining for AXI-Lite.
-- PDR feedback.
-- Remove address register stage to BRAM.
-- Rely on registers in AXI Interconnect.
---------------------------------------------------------------------------
-- Generate: GEN_ADDR
-- Purpose: Generate all valid bits in the address(es) to BRAM.
-- If dual port, generate Port B address signal.
---------------------------------------------------------------------------
GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_SNG_PORT
-- Purpose: Generate BRAM address when a single port to BRAM.
-- Mux read and write addresses from AXI AW and AR channels.
---------------------------------------------------------------------------
GEN_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
-- Read takes priority over AWADDR
-- bram_addr_a_int (i) <= AXI_ARADDR (i) when (AXI_ARVALID = '1') else AXI_AWADDR (i);
-- ISE should optimize away this mux when connected to the AXI Interconnect
-- as the AXI Interconnect duplicates the write or read address on both channels.
-- v1.03a
-- ARVALID may get asserted while handling ECC read-modify-write.
-- With the delay in assertion of AWREADY/WREADY, must add some logic to the
-- control on this mux select.
bram_addr_a_int (i) <= AXI_ARADDR (i) when ((AXI_ARVALID = '1' and
(lite_sm_cs = IDLE or lite_sm_cs = SNG_WR_DATA)) or
(lite_sm_cs = RD_DATA))
else AXI_AWADDR (i);
end generate GEN_ADDR_SNG_PORT;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_DUAL_PORT
-- Purpose: Generate BRAM address when a single port to BRAM.
-- Mux read and write addresses from AXI AW and AR channels.
---------------------------------------------------------------------------
GEN_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
bram_addr_a_int (i) <= AXI_AWADDR (i);
bram_addr_b_int (i) <= AXI_ARADDR (i);
end generate GEN_ADDR_DUAL_PORT;
end generate GEN_ADDR;
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY
-- Purpose: Only pre-assert ARREADY for non ECC designs.
-- With ECC, a write requires a read-modify-write and
-- will miss the address associated with the ARVALID
-- (due to the # of clock cycles).
---------------------------------------------------------------------------
GEN_ARREADY: if (C_ECC = 0) generate
begin
REG_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- ARREADY is asserted until we detect the ARVALID.
-- Check for back-to-back ARREADY assertions (add axi_arready_int).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(AXI_ARVALID = '1' and axi_arready_int = '1') then
axi_arready_int <= '0';
-- Then ARREADY is asserted again when the read operation completes.
elsif (axi_aresetn_re = '1') or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_arready_int <= '1';
else
axi_arready_int <= axi_arready_int;
end if;
end if;
end process REG_ARREADY;
end generate GEN_ARREADY;
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_ECC
-- Purpose: Generate ARREADY from SM logic. ARREADY is not pre-asserted
-- as in the non ECC configuration.
---------------------------------------------------------------------------
GEN_ARREADY_ECC: if (C_ECC = 1) generate
begin
axi_arready_int <= axi_arready_reg;
end generate GEN_ARREADY_ECC;
---------------------------------------------------------------------------
-- *** AXI Write Data Channel Interface ***
---------------------------------------------------------------------------
-- No AXI_WLAST
---------------------------------------------------------------------------
-- Generate: GEN_WRDATA
-- Purpose: Generate BRAM port A write data. For AXI-Lite, pass
-- through from AXI bus. If ECC is enabled, merge with fault
-- inject vector.
-- Write data bits are in lower order bit lanes.
-- (31:0) or (63:0)
---------------------------------------------------------------------------
GEN_WRDATA: for i in C_S_AXI_DATA_WIDTH-1 downto 0 generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Generate output write data when ECC is disabled.
-- Remove write data path register to BRAM
---------------------------------------------------------------------------
GEN_NO_ECC : if C_ECC = 0 generate
begin
bram_wrdata_a_int (i) <= AXI_WDATA (i);
end generate GEN_NO_ECC;
---------------------------------------------------------------------------
-- Generate: GEN_W_ECC
-- Purpose: Generate output write data when ECC is enable
-- (use fault vector).
-- (N:0)
---------------------------------------------------------------------------
GEN_W_ECC : if C_ECC = 1 generate
begin
bram_wrdata_a_int (i) <= WrData (i) xor FaultInjectData (i);
end generate GEN_W_ECC;
end generate GEN_WRDATA;
---------------------------------------------------------------------------
-- *** AXI Write Response Channel Interface ***
---------------------------------------------------------------------------
-- No BID support (wrap around in Interconnect)
-- In AXI-Lite, no WLAST assertion
-- Drive constant value out on BRESP
-- axi_bresp_int <= RESP_OKAY;
axi_bresp_int <= RESP_SLVERR when (C_ECC = 1 and UE_Q = '1') else RESP_OKAY;
---------------------------------------------------------------------------
-- Implement BVALID with counter regardless of IP configuration.
--
-- BVALID counter to track the # of required BVALID/BREADY handshakes
-- needed to occur on the AXI interface. Based on early and seperate
-- AWVALID/AWREADY and WVALID/WREADY handshake exchanges.
REG_BVALID_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bvalid_cnt <= (others => '0');
-- Ensure we only increment counter wyhen BREADY is not asserted
elsif (bvalid_cnt_inc = '1') and (bvalid_cnt_dec = '0') then
bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) + 1);
-- Ensure that we only decrement when SM is not incrementing
elsif (bvalid_cnt_dec = '1') and (bvalid_cnt_inc = '0') then
bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) - 1);
else
bvalid_cnt <= bvalid_cnt;
end if;
end if;
end process REG_BVALID_CNT;
bvalid_cnt_dec <= '1' when (AXI_BREADY = '1' and axi_bvalid_int = '1' and bvalid_cnt /= "000") else '0';
-- Replace BVALID output register
-- Assert BVALID as long as BVALID counter /= zero
REG_BVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(bvalid_cnt = "001" and bvalid_cnt_dec = '1') then
axi_bvalid_int <= '0';
elsif (bvalid_cnt /= "000") then
axi_bvalid_int <= '1';
else
axi_bvalid_int <= '0';
end if;
end if;
end process REG_BVALID;
---------------------------------------------------------------------------
-- *** AXI Read Data Channel Interface ***
---------------------------------------------------------------------------
-- For reductions on AXI-Lite, drive constant value on RESP
axi_rresp_int <= RESP_OKAY;
---------------------------------------------------------------------------
-- Generate: GEN_R
-- Purpose: Generate AXI R channel outputs when ECC is disabled.
-- No register delay on AXI_RVALID and AXI_RLAST.
---------------------------------------------------------------------------
GEN_R: if C_ECC = 0 generate
begin
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rvalid_int <= '0';
elsif (axi_rvalid_set = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rlast_int <= '0';
elsif (axi_rlast_set = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
end generate GEN_R;
---------------------------------------------------------------------------
-- Generate: GEN_R_ECC
-- Purpose: Generate AXI R channel outputs when ECC is enabled.
-- Must use registered delayed control signals for RLAST
-- and RVALID to align with register inclusion for corrected
-- read data in ECC logic.
---------------------------------------------------------------------------
GEN_R_ECC: if C_ECC = 1 generate
begin
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rvalid_int <= '0';
elsif (axi_rvalid_set_r = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
-- Code coverage is hitting this condition and axi_rvalid_int is ALWAYS = '1'
-- May be able to remove from this if clause (and simplify logic)
axi_rlast_int <= '0';
elsif (axi_rlast_set_r = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
end generate GEN_R_ECC;
---------------------------------------------------------------------------
--
-- Generate AXI bus read data. No register. Pass through
-- read data from BRAM. Determine source on single port
-- vs. dual port configuration.
--
---------------------------------------------------------------------------
-----------------------------------------------------------------------
-- Generate: RDATA_NO_ECC
-- Purpose: Define port A/B from BRAM on AXI_RDATA when ECC disabled.
-----------------------------------------------------------------------
RDATA_NO_ECC: if (C_ECC = 0) generate
begin
AXI_RDATA <= axi_rdata_int;
-----------------------------------------------------------------------
-- Generate: GEN_RDATA_SNG_PORT
-- Purpose: Source of read data: Port A in single port configuration.
-----------------------------------------------------------------------
GEN_RDATA_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_A(C_S_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_RDATA_SNG_PORT;
-----------------------------------------------------------------------
-- Generate: GEN_RDATA_DUAL_PORT
-- Purpose: Source of read data: Port B in dual port configuration.
-----------------------------------------------------------------------
GEN_RDATA_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_RDATA_DUAL_PORT;
end generate RDATA_NO_ECC;
-----------------------------------------------------------------------
-- Generate: RDATA_W_ECC
-- Purpose: Connect AXI_RDATA from ECC module when ECC enabled.
-----------------------------------------------------------------------
RDATA_W_ECC: if (C_ECC = 1) generate
subtype syndrome_bits is std_logic_vector (0 to 6);
type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
begin
-- Logic common to either type of ECC encoding/decoding
-- Renove bit reversal on AXI_RDATA output.
AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr;
CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0);
-- Remove GEN_RDATA that was doing bit reversal.
-- Read back data is registered prior to any single bit error correction.
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rdata_int <= (others => '0');
else
axi_rdata_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1);
end if;
end if;
end process REG_RDATA;
---------------------------------------------------------------------------
-- Generate: RDATA_W_HAMMING
-- Purpose: Add generate statement for Hamming Code ECC algorithm
-- specific logic.
---------------------------------------------------------------------------
RDATA_W_HAMMING: if C_ECC_TYPE = 0 generate
begin
-- Move correct_one_bit logic to output side of AXI_RDATA output register.
-- Improves timing by balancing logic on both sides of pipeline stage.
-- Utilizing registers in AXI interconnect makes this feasible.
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_reg <= Syndrome;
syndrome_4_reg <= Syndrome_4;
syndrome_6_reg <= Syndrome_6;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on select syndrome bits outside of checkbit_handler (to match rd_chnl
-- w/ balanced pipeline stage) before correct_one_bit module.
syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3);
PARITY_CHK4: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (4) ); -- [out std_logic]
syndrome_reg_i (5) <= syndrome_reg (5);
PARITY_CHK6: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (6) ); -- [out std_logic]
---------------------------------------------------------------------------
-- Generate: GEN_CORR_32
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_32: for i in 0 to C_S_AXI_DATA_WIDTH-1 generate
begin
---------------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_32
-- Description: Generate ECC bits for checking data read from BRAM.
---------------------------------------------------------------------------
CORR_ONE_BIT_32: entity work.correct_one_bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table (i))
port map (
DIn => axi_rdata_int (i),
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (i));
end generate GEN_CORR_32;
end generate RDATA_W_HAMMING;
-- Hsiao ECC done in seperate generate statement (GEN_HSIAO_ECC)
end generate RDATA_W_ECC;
---------------------------------------------------------------------------
-- Main AXI-Lite State Machine
--
-- Description: Central processing unit for AXI-Lite write and read address
-- channel interface handling and handshaking.
-- Handles all arbitration between write and read channels
-- to utilize single port to BRAM
--
-- Outputs: axi_wready_int Registered
-- axi_arready_reg Registered (used in ECC configurations)
-- bvalid_cnt_inc Combinatorial
-- axi_rvalid_set Combinatorial
-- axi_rlast_set Combinatorial
-- bram_en_a_cmb Combinatorial
-- bram_en_b_cmb Combinatorial
-- bram_we_a_int Combinatorial
--
--
-- LITE_SM_CMB_PROCESS: Combinational process to determine next state.
-- LITE_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
LITE_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_WVALID,
AXI_WSTRB,
AXI_ARVALID,
AXI_RREADY,
bvalid_cnt,
axi_rvalid_int,
lite_sm_cs )
begin
-- assign default values for state machine outputs
lite_sm_ns <= lite_sm_cs;
axi_wready_cmb <= '0';
axi_arready_cmb <= '0';
bvalid_cnt_inc <= '0';
axi_rvalid_set <= '0';
axi_rlast_set <= '0';
bram_en_a_cmb <= '0';
bram_en_b_cmb <= '0';
bram_we_a_int <= (others => '0');
case lite_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- AXI Interconnect will only issue AWVALID OR ARVALID
-- at a time. In the case when the core is attached
-- to another AXI master IP, arbitrate between read
-- and write operation. Read operation will always win.
if (AXI_ARVALID = '1') then
lite_sm_ns <= RD_DATA;
-- Initiate BRAM read transfer
-- For single port BRAM, use Port A
-- For dual port BRAM, use Port B
if (C_SINGLE_PORT_BRAM = 1) then
bram_en_a_cmb <= '1';
else
bram_en_b_cmb <= '1';
end if;
bram_we_a_int <= (others => '0');
-- RVALID to be asserted in next clock cycle
-- Only 1 clock cycle latency on reading data from BRAM
axi_rvalid_set <= '1';
-- Due to single data beat with AXI-Lite
-- Assert RLAST on AXI
axi_rlast_set <= '1';
-- Only in ECC configurations
-- Must assert ARREADY here (no pre-assertion)
if (C_ECC = 1) then
axi_arready_cmb <= '1';
end if;
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
elsif (AXI_AWVALID = '1') and (AXI_WVALID = '1') and
(bvalid_cnt /= "111") then
-- Initiate BRAM write transfer
bram_en_a_cmb <= '1';
-- Always perform a read-modify-write sequence with ECC is enabled.
if (C_ECC = 1) then
lite_sm_ns <= RMW_RD_DATA;
-- Disable Port A write enables
bram_we_a_int <= (others => '0');
else
-- Non ECC operation or an ECC full 32-bit word write
-- Assert acknowledge of data & address on AXI.
-- Wait to assert AWREADY and WREADY in ECC designs.
axi_wready_cmb <= '1';
-- Increment counter to track # of required BVALID responses.
bvalid_cnt_inc <= '1';
lite_sm_ns <= SNG_WR_DATA;
bram_we_a_int <= AXI_WSTRB;
end if;
end if;
------------------------- SNG_WR_DATA State -------------------------
when SNG_WR_DATA =>
-- With early assertion of ARREADY, the SM
-- must be able to accept a read address at any clock cycle.
-- Check here for active ARVALID and directly handle read
-- and do not proceed back to IDLE (no empty clock cycle in which
-- read address may be missed).
if (AXI_ARVALID = '1') and (C_ECC = 0) then
lite_sm_ns <= RD_DATA;
-- Initiate BRAM read transfer
-- For single port BRAM, use Port A
-- For dual port BRAM, use Port B
if (C_SINGLE_PORT_BRAM = 1) then
bram_en_a_cmb <= '1';
else
bram_en_b_cmb <= '1';
end if;
bram_we_a_int <= (others => '0');
-- RVALID to be asserted in next clock cycle
-- Only 1 clock cycle latency on reading data from BRAM
axi_rvalid_set <= '1';
-- Due to single data beat with AXI-Lite
-- Assert RLAST on AXI
axi_rlast_set <= '1';
-- Only in ECC configurations
-- Must assert ARREADY here (no pre-assertion)
-- Pre-assertion of ARREADY is only for non ECC configurations.
if (C_ECC = 1) then
axi_arready_cmb <= '1';
end if;
else
lite_sm_ns <= IDLE;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Data is presented to AXI bus
-- Wait for acknowledgment to process any next transfers
-- RVALID may not be asserted as we transition into this state.
if (AXI_RREADY = '1') and (axi_rvalid_int = '1') then
lite_sm_ns <= IDLE;
end if;
------------------------- RMW_RD_DATA State -------------------------
when RMW_RD_DATA =>
lite_sm_ns <= RMW_MOD_DATA;
------------------------- RMW_MOD_DATA State -------------------------
when RMW_MOD_DATA =>
lite_sm_ns <= RMW_WR_DATA;
-- Hold off on assertion of WREADY and AWREADY until
-- here, so no pipeline registers necessary.
-- Assert acknowledge of data & address on AXI
axi_wready_cmb <= '1';
-- Increment counter to track # of required BVALID responses.
-- Able to assert this signal early, then BVALID counter
-- will get incremented in the next clock cycle when WREADY
-- is asserted.
bvalid_cnt_inc <= '1';
------------------------- RMW_WR_DATA State -------------------------
when RMW_WR_DATA =>
-- Initiate BRAM write transfer
bram_en_a_cmb <= '1';
-- Enable all WEs to BRAM
bram_we_a_int <= (others => '1');
-- Complete write operation
lite_sm_ns <= IDLE;
--coverage off
------------------------------ Default ----------------------------
when others =>
lite_sm_ns <= IDLE;
--coverage on
end case;
end process LITE_SM_CMB_PROCESS;
---------------------------------------------------------------------------
LITE_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
lite_sm_cs <= IDLE;
axi_wready_int <= '0';
axi_arready_reg <= '0';
axi_rvalid_set_r <= '0';
axi_rlast_set_r <= '0';
else
lite_sm_cs <= lite_sm_ns;
axi_wready_int <= axi_wready_cmb;
axi_arready_reg <= axi_arready_cmb;
axi_rvalid_set_r <= axi_rvalid_set;
axi_rlast_set_r <= axi_rlast_set;
end if;
end if;
end process LITE_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** ECC Logic ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_ECC
-- Purpose: Generate BRAM ECC write data and check ECC on read operations.
-- Create signals to update ECC registers (lite_ecc_reg module interface).
--
---------------------------------------------------------------------------
GEN_ECC: if C_ECC = 1 generate
constant null7 : std_logic_vector(0 to 6) := "0000000"; -- Specific to 32-bit data width (AXI-Lite)
signal WrECC : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0); -- Specific to BRAM data width
signal WrECC_i : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0');
signal wrdata_i : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0);
signal AXI_WDATA_Q : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0);
signal AXI_WSTRB_Q : std_logic_vector ((C_S_AXI_DATA_WIDTH/8 - 1) downto 0);
signal bram_din_a_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width
signal bram_rddata_in : std_logic_vector (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0) := (others => '0');
subtype syndrome_bits is std_logic_vector (0 to 6);
type correct_data_table_type is array (natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
begin
-- Read on Port A
-- or any operation on Port B (it will be read only).
BRAM_Addr_En <= '1' when (bram_en_a_int = '1' and bram_we_a_int = "00000") or
(bram_en_b_int = '1')
else '0';
-- BRAM_WE generated from SM
-- Remember byte write enables one clock cycle to properly mux bytes to write,
-- with read data in read/modify write operation
-- Write in Read/Write always 1 cycle after Read
REG_RMW_SIGS : process (S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Add reset values
if (S_AXI_AResetn = C_RESET_ACTIVE) then
RdModifyWr_Check <= '0';
RdModifyWr_Modify <= '0';
RdModifyWr_Write <= '0';
else
RdModifyWr_Check <= RdModifyWr_Read;
RdModifyWr_Modify <= RdModifyWr_Check;
RdModifyWr_Write <= RdModifyWr_Modify;
end if;
end if;
end process REG_RMW_SIGS;
-- v1.03a
-- Delay assertion of WREADY to minimize registers in core.
-- Use SM transition to RMW "read" to assert this signal.
RdModifyWr_Read <= '1' when (lite_sm_ns = RMW_RD_DATA) else '0';
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation
STORE_WRITE_DBUS : process (S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
AXI_WDATA_Q <= (others => '0');
AXI_WSTRB_Q <= (others => '0');
-- v1.03a
-- With the delay assertion of WREADY, use WVALID
-- to register in WDATA and WSTRB signals.
elsif (AXI_WVALID = '1') then
AXI_WDATA_Q <= AXI_WDATA;
AXI_WSTRB_Q <= AXI_WSTRB;
end if;
end if;
end process STORE_WRITE_DBUS;
wrdata_i <= AXI_WDATA_Q when RdModifyWr_Modify = '1' else AXI_WDATA;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_WRDATA_CMB
-- Purpose: Replace manual signal assignment for WrData_cmb with
-- generate funtion.
--
-- Ensure correct byte swapping occurs with
-- CorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) assignment
-- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0).
--
-- AXI_WSTRB_Q (C_S_AXI_DATA_WIDTH_BYTES-1 downto 0) matches
-- to WrData_cmb (C_S_AXI_DATA_WIDTH-1 downto 0).
--
------------------------------------------------------------------------
GEN_WRDATA_CMB: for i in C_AXI_DATA_WIDTH_BYTES-1 downto 0 generate
begin
WrData_cmb ( (((i+1)*8)-1) downto i*8 ) <= wrdata_i ((((i+1)*8)-1) downto i*8) when
(RdModifyWr_Modify = '1' and AXI_WSTRB_Q(i) = '1')
else CorrectedRdData ( (C_S_AXI_DATA_WIDTH - ((i+1)*8)) to
(C_S_AXI_DATA_WIDTH - (i*8) - 1) );
end generate GEN_WRDATA_CMB;
REG_WRDATA : process (S_AXI_AClk) is
begin
-- Remove reset value to minimize resources & improve timing
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
WrData <= WrData_cmb;
end if;
end process REG_WRDATA;
------------------------------------------------------------------------
-- New assignment of ECC bits to BRAM write data outside generate
-- blocks. Same signal assignment regardless of ECC type.
bram_wrdata_a_int (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) <= '0';
bram_wrdata_a_int ((C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH - 1) downto C_S_AXI_DATA_WIDTH)
<= WrECC xor FaultInjectECC;
------------------------------------------------------------------------
-- No need to use RdModifyWr_Write in the data path.
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
------------------------------------------------------------------------
GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_WR_32
-- Description: Generate ECC bits for writing into BRAM.
-- WrData (N:0)
---------------------------------------------------------------------------
CHK_HANDLER_WR_32: entity work.checkbit_handler
generic map (
C_ENCODE => true, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => open, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => open, -- [out std_logic_vector(0 to 5)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
Syndrome_Chk => null7, -- [in std_logic_vector(0 to 6)]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open ); -- [out std_logic]
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_RD_32
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
CHK_HANDLER_RD_32: entity work.checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
-- DataIn (8:39)
-- CheckIn (1:7)
-- Bit swapping done at port level on checkbit_handler (31:0) & (6:0)
DataIn => bram_din_a_i (C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_S_AXI_DATA_WIDTH), -- [in std_logic_vector(8 to 39)]
CheckIn => bram_din_a_i (1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(1 to 7)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)]
Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 6)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic to use registered syndrome value.
end generate GEN_HAMMING_ECC;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
------------------------------------------------------------------------
GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate
constant CODE_WIDTH : integer := C_S_AXI_DATA_WIDTH + C_INT_ECC_WIDTH;
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
type type_int0 is array (C_S_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0);
signal syndrome_ns : std_logic_vector(ECC_WIDTH - 1 downto 0);
signal syndrome_r : std_logic_vector(ECC_WIDTH - 1 downto 0);
signal ecc_rddata_r : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
signal h_matrix : type_int0;
signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0);
signal flip_bits : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
begin
---------------------- Hsiao ECC Write Logic ----------------------
-- Instantiate ecc_gen module, generated from MIG
ECC_GEN_HSIAO: entity work.ecc_gen
generic map (
code_width => CODE_WIDTH,
ecc_width => ECC_WIDTH,
data_width => C_S_AXI_DATA_WIDTH
)
port map (
-- Output
h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
-- Merge muxed rd/write data to gen
HSIAO_ECC: process (h_rows, WrData)
constant DQ_WIDTH : integer := CODE_WIDTH;
variable ecc_wrdata_tmp : std_logic_vector(DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
begin
-- Loop to generate all ECC bits
for k in 0 to ECC_WIDTH - 1 loop
ecc_wrdata_tmp (CODE_WIDTH - k - 1) := REDUCTION_XOR ( (WrData (C_S_AXI_DATA_WIDTH - 1 downto 0)
and h_rows (k * CODE_WIDTH + C_S_AXI_DATA_WIDTH - 1 downto k * CODE_WIDTH)));
end loop;
WrECC (C_INT_ECC_WIDTH-1 downto 0) <= ecc_wrdata_tmp (DQ_WIDTH-1 downto C_S_AXI_DATA_WIDTH);
end process HSIAO_ECC;
---------------------- Hsiao ECC Read Logic -----------------------
GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate
begin
syndrome_ns (m) <= REDUCTION_XOR ( bram_rddata_in (CODE_WIDTH-1 downto 0)
and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH)));
end generate GEN_RD_ECC;
-- Insert register stage for syndrome
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_r <= syndrome_ns;
-- Replicate BRAM read back data register for Hamming ECC
ecc_rddata_r <= bram_rddata_in (C_S_AXI_DATA_WIDTH-1 downto 0);
end if;
end process REG_SYNDROME;
-- Reconstruct H-matrix
H_COL: for n in 0 to C_S_AXI_DATA_WIDTH - 1 generate
begin
H_BIT: for p in 0 to ECC_WIDTH - 1 generate
begin
h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n);
end generate H_BIT;
end generate H_COL;
GEN_FLIP_BIT: for r in 0 to C_S_AXI_DATA_WIDTH - 1 generate
begin
flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r);
end generate GEN_FLIP_BIT;
axi_rdata_int_corr (C_S_AXI_DATA_WIDTH-1 downto 0) <= ecc_rddata_r (C_S_AXI_DATA_WIDTH-1 downto 0) xor
flip_bits (C_S_AXI_DATA_WIDTH-1 downto 0);
Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
end generate GEN_HSIAO_ECC;
-- Capture correctable/uncorrectable error from BRAM read.
-- Either during RMW of write operation or during BRAM read.
CORR_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if RdModifyWr_Modify = '1' or
((Enable_ECC = '1') and
(axi_rvalid_int = '1' and AXI_RREADY = '1')) then -- Capture error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CORR_REG;
-- Register CE and UE flags to register block.
Sl_CE <= CE_Q;
Sl_UE <= UE_Q;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_A
-- Purpose: Generate BRAM read data vector assignment to always be from Port A
-- in a single port BRAM configuration.
-- Map BRAM_RdData_A (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
---------------------------------------------------------------------------
GEN_DIN_A: if C_SINGLE_PORT_BRAM = 1 generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_DIN_A_HAMMING
-- Purpose: Standard input for Hamming ECC code generation.
-- MSB '0' is removed in port mapping to checkbit_handler module.
---------------------------------------------------------------------------
GEN_DIN_A_HAMMING: if C_ECC_TYPE = 1 generate
begin
bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_A_HAMMING;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_A_HSIAO
-- Purpose: For Hsiao ECC implementation configurations.
-- Remove MSB '0' on 32-bit implementation with fixed
-- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix).
---------------------------------------------------------------------------
GEN_DIN_A_HSIAO: if C_ECC_TYPE = 1 generate
begin
bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_A_HSIAO;
end generate GEN_DIN_A;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_B
-- Purpose: Generate BRAM read data vector assignment in a dual port
-- configuration to be either from Port B, or from Port A in a
-- read-modify-write sequence.
-- Map BRAM_RdData_A/B (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
---------------------------------------------------------------------------
GEN_DIN_B: if C_SINGLE_PORT_BRAM = 0 generate
begin
---------------------------------------------------------------------------
-- Generate: GEN_DIN_B_HAMMING
-- Purpose: Standard input for Hamming ECC code generation.
-- MSB '0' is removed in port mapping to checkbit_handler module.
---------------------------------------------------------------------------
GEN_DIN_B_HAMMING: if C_ECC_TYPE = 1 generate
begin
bram_din_a_i (0 to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
when (RdModifyWr_Check = '1')
else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_B_HAMMING;
---------------------------------------------------------------------------
-- Generate: GEN_DIN_B_HSIAO
-- Purpose: For Hsiao ECC implementation configurations.
-- Remove MSB '0' on 32-bit implementation with fixed
-- '0' in (8-bit wide) ECC data bits (only need 7-bits in h-matrix).
---------------------------------------------------------------------------
GEN_DIN_B_HSIAO: if C_ECC_TYPE = 1 generate
begin
bram_rddata_in <= BRAM_RdData_A (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0)
when (RdModifyWr_Check = '1')
else BRAM_RdData_B (C_S_AXI_DATA_WIDTH+C_INT_ECC_WIDTH-1 downto 0);
end generate GEN_DIN_B_HSIAO;
end generate GEN_DIN_B;
-- Map data vector from BRAM to use in correct_one_bit module with
-- register syndrome (post AXI RDATA register).
UnCorrectedRdData (0 to C_S_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_S_AXI_DATA_WIDTH-1);
end generate GEN_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** BRAM Interface Signals ***
---------------------------------------------------------------------------
-- With AXI-LITE no narrow operations are allowed.
-- AXI_WSTRB is ignored and all byte lanes are written.
bram_en_a_int <= bram_en_a_cmb;
-- BRAM_En_A <= bram_en_a_int;
-- DV regression failure with reset
-- 7/7/11
BRAM_En_A <= '0' when (S_AXI_AResetn = C_RESET_ACTIVE) else bram_en_a_int;
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_EN_DUAL_PORT
-- Purpose: Only generate Port B BRAM enable signal when
-- configured for dual port BRAM.
-----------------------------------------------------------------------
GEN_BRAM_EN_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
bram_en_b_int <= bram_en_b_cmb;
BRAM_En_B <= bram_en_b_int;
end generate GEN_BRAM_EN_DUAL_PORT;
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_EN_SNG_PORT
-- Purpose: Drive default for unused BRAM Port B in single
-- port BRAM configuration.
-----------------------------------------------------------------------
GEN_BRAM_EN_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_En_B <= '0';
end generate GEN_BRAM_EN_SNG_PORT;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_WE
-- Purpose: BRAM WE generate process
-- One WE per 8-bits of BRAM data.
---------------------------------------------------------------------------
GEN_BRAM_WE: for i in (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH)/8-1 downto 0 generate
begin
BRAM_WE_A (i) <= bram_we_a_int (i);
end generate GEN_BRAM_WE;
---------------------------------------------------------------------------
BRAM_Addr_A <= BRAM_Addr_A_i;
BRAM_Addr_B <= BRAM_Addr_B_i;
---------------------------------------------------------------------------
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr_A_i (i) <= '0';
BRAM_Addr_B_i (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
---------------------------------------------------------------------------
GEN_U_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr_A_i (i) <= bram_addr_a_int (i);
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR_DUAL_PORT
-- Purpose: Only generate Port B BRAM address when
-- configured for dual port BRAM.
-----------------------------------------------------------------------
GEN_BRAM_ADDR_DUAL_PORT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
BRAM_Addr_B_i (i) <= bram_addr_b_int (i);
end generate GEN_BRAM_ADDR_DUAL_PORT;
-----------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR_SNG_PORT
-- Purpose: Drive default for unused BRAM Port B in single
-- port BRAM configuration.
-----------------------------------------------------------------------
GEN_BRAM_ADDR_SNG_PORT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
BRAM_Addr_B_i (i) <= '0';
end generate GEN_BRAM_ADDR_SNG_PORT;
end generate GEN_U_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_WRDATA
-- Purpose: Generate BRAM Write Data for Port A.
---------------------------------------------------------------------------
-- When C_ECC = 0, C_ECC_WIDTH = 0 (at top level HDL)
GEN_BRAM_WRDATA: for i in (C_S_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) downto 0 generate
begin
BRAM_WrData_A (i) <= bram_wrdata_a_int (i);
end generate GEN_BRAM_WRDATA;
BRAM_WrData_B <= (others => '0');
BRAM_WE_B <= (others => '0');
---------------------------------------------------------------------------
end architecture implementation;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Ethertype is
port( data_in : in std_logic_vector(7 downto 0);
enable : in std_logic;
reset : in std_logic;
clk : in std_logic;
ethertype : out std_logic_vector(15 downto 0)
);
end Ethertype;
architecture Behavioral of Ethertype is
signal address_counter : std_logic_vector(10 downto 0) := (others=>'0');
begin
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
address_counter <= (others=>'0');
elsif enable = '1' then
address_counter <= address_counter+1;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
ethertype <= (others=>'0');
elsif address_counter = 13 then
ethertype(15 downto 8) <= data_in;
elsif address_counter = 14 then
ethertype(7 downto 0) <= data_in;
end if;
end if;
end process;
end Behavioral; |
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 65248)
`protect data_block
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X2KLxxvC5dV/EYuxuz3k1hN7mTHK1hCNj4EoIBGVHrRGMEAwnOu3lAPtLnlhecLnd7aVaSoSjXcL
nPkUbdkOYK3ha8KTI7W0AMi6FmqAgVfpzO1KLI+meHNOaTyieP93gQeNgEu13gILHGN1Ak4MUeNp
gQoMxWJ7nDPcQfhR78ObMSdgMw28Xk9pRyeFXjgpE/FrjJR+i5osbR0SaLImJ2Rkj5Ni5ZiNwQ3x
3PJ5wgarrm2wQdfAIEdx0ssAttvG9wE3AacWKnHIy1gXkAArpPRbwCPiIwJE4g5+E5KkS4c1irG6
41ZYNNFhNWwXw0+Qwf6xKIAkYuGCEVTuL6EI9Mykuypka0QD3P1YedtGdb7TNot8GiGOcjbJFdRx
KyQzJKJF78qgHIENCJxr02Qp34tM/qKhoDeR4jw2LXHHPzbHNpMWLISwlwqTlDOzm1D+Alrarbr8
2+vSptroF5ScYH2qkL0XQ9pzJM25NP0iuv+5UfzV8Gb0roAjqqozlA==
`protect end_protected
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 0;
begin -- process
x := 1;
assert x = 1 report "TEST FAILED - x does not equal 1" severity failure;
assert x /= 1 report "TEST PASSED" severity note;
wait;
end process;
end only;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 0;
begin -- process
x := 1;
assert x = 1 report "TEST FAILED - x does not equal 1" severity failure;
assert x /= 1 report "TEST PASSED" severity note;
wait;
end process;
end only;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 0;
begin -- process
x := 1;
assert x = 1 report "TEST FAILED - x does not equal 1" severity failure;
assert x /= 1 report "TEST PASSED" severity note;
wait;
end process;
end only;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 0;
begin -- process
x := 1;
assert x = 1 report "TEST FAILED - x does not equal 1" severity failure;
assert x /= 1 report "TEST PASSED" severity note;
wait;
end process;
end only;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 0;
begin -- process
x := 1;
assert x = 1 report "TEST FAILED - x does not equal 1" severity failure;
assert x /= 1 report "TEST PASSED" severity note;
wait;
end process;
end only;
|
entity foo is
end foo;
use std.textio.all;
architecture only of foo is
begin -- only
process
variable x : integer := 0;
begin -- process
x := 1;
assert x = 1 report "TEST FAILED - x does not equal 1" severity failure;
assert x /= 1 report "TEST PASSED" severity note;
wait;
end process;
end only;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
this is not a genuine template ;-)
|
entity FIFO is
end entity;
entity FIFO is
end entity;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_1541_700a is
generic (
g_version : unsigned(7 downto 0) := X"F9" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate_1541_700a;
architecture structural of ultimate_1541_700a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => false,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => true,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => false,
g_usb_host => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sampler => true,
g_analyzer => false )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
vid_active => open,
vid_opaque => open,
vid_data => open,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
architecture rtl of fifo is
begin
procedure_call_label : postponed wr_en(a, b);
procedure_call_label : postponed wr_en(a, b);
process_label : process
begin
procedure_call_label : wr_en(a, b);
procedure_call_label : wr_en(a, b);
end process;
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1354.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p02n01i01354ent IS
END c08s05b00x00p02n01i01354ent;
ARCHITECTURE c08s05b00x00p02n01i01354arch OF c08s05b00x00p02n01i01354ent IS
BEGIN
TESTING: PROCESS
variable a : integer := 1;
BEGIN
a := 10;
assert NOT(a = 10)
report "***PASSED TEST: c08s05b00x00p02n01i01354"
severity NOTE;
assert (a = 10)
report "***FAILED TEST: c08s05b00x00p02n01i01354 - Target of a variable assignment can only be a name or an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p02n01i01354arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1354.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p02n01i01354ent IS
END c08s05b00x00p02n01i01354ent;
ARCHITECTURE c08s05b00x00p02n01i01354arch OF c08s05b00x00p02n01i01354ent IS
BEGIN
TESTING: PROCESS
variable a : integer := 1;
BEGIN
a := 10;
assert NOT(a = 10)
report "***PASSED TEST: c08s05b00x00p02n01i01354"
severity NOTE;
assert (a = 10)
report "***FAILED TEST: c08s05b00x00p02n01i01354 - Target of a variable assignment can only be a name or an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p02n01i01354arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1354.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p02n01i01354ent IS
END c08s05b00x00p02n01i01354ent;
ARCHITECTURE c08s05b00x00p02n01i01354arch OF c08s05b00x00p02n01i01354ent IS
BEGIN
TESTING: PROCESS
variable a : integer := 1;
BEGIN
a := 10;
assert NOT(a = 10)
report "***PASSED TEST: c08s05b00x00p02n01i01354"
severity NOTE;
assert (a = 10)
report "***FAILED TEST: c08s05b00x00p02n01i01354 - Target of a variable assignment can only be a name or an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p02n01i01354arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_65c102_banner is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of tuberom_65c102_banner is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(10 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"A2";
when x"001" => DATA <= x"00";
when x"002" => DATA <= x"BD";
when x"003" => DATA <= x"00";
when x"004" => DATA <= x"FF";
when x"005" => DATA <= x"9D";
when x"006" => DATA <= x"00";
when x"007" => DATA <= x"FF";
when x"008" => DATA <= x"CA";
when x"009" => DATA <= x"D0";
when x"00A" => DATA <= x"F7";
when x"00B" => DATA <= x"A2";
when x"00C" => DATA <= x"36";
when x"00D" => DATA <= x"BD";
when x"00E" => DATA <= x"80";
when x"00F" => DATA <= x"FF";
when x"010" => DATA <= x"9D";
when x"011" => DATA <= x"00";
when x"012" => DATA <= x"02";
when x"013" => DATA <= x"CA";
when x"014" => DATA <= x"10";
when x"015" => DATA <= x"F7";
when x"016" => DATA <= x"9A";
when x"017" => DATA <= x"A2";
when x"018" => DATA <= x"F0";
when x"019" => DATA <= x"BD";
when x"01A" => DATA <= x"FF";
when x"01B" => DATA <= x"FD";
when x"01C" => DATA <= x"9D";
when x"01D" => DATA <= x"FF";
when x"01E" => DATA <= x"FD";
when x"01F" => DATA <= x"CA";
when x"020" => DATA <= x"D0";
when x"021" => DATA <= x"F7";
when x"022" => DATA <= x"A0";
when x"023" => DATA <= x"00";
when x"024" => DATA <= x"84";
when x"025" => DATA <= x"F8";
when x"026" => DATA <= x"A9";
when x"027" => DATA <= x"F8";
when x"028" => DATA <= x"85";
when x"029" => DATA <= x"F9";
when x"02A" => DATA <= x"B1";
when x"02B" => DATA <= x"F8";
when x"02C" => DATA <= x"91";
when x"02D" => DATA <= x"F8";
when x"02E" => DATA <= x"C8";
when x"02F" => DATA <= x"D0";
when x"030" => DATA <= x"F9";
when x"031" => DATA <= x"E6";
when x"032" => DATA <= x"F9";
when x"033" => DATA <= x"A5";
when x"034" => DATA <= x"F9";
when x"035" => DATA <= x"C9";
when x"036" => DATA <= x"FE";
when x"037" => DATA <= x"D0";
when x"038" => DATA <= x"F1";
when x"039" => DATA <= x"A2";
when x"03A" => DATA <= x"10";
when x"03B" => DATA <= x"BD";
when x"03C" => DATA <= x"59";
when x"03D" => DATA <= x"F8";
when x"03E" => DATA <= x"9D";
when x"03F" => DATA <= x"00";
when x"040" => DATA <= x"01";
when x"041" => DATA <= x"CA";
when x"042" => DATA <= x"10";
when x"043" => DATA <= x"F7";
when x"044" => DATA <= x"A5";
when x"045" => DATA <= x"EE";
when x"046" => DATA <= x"85";
when x"047" => DATA <= x"F6";
when x"048" => DATA <= x"A5";
when x"049" => DATA <= x"EF";
when x"04A" => DATA <= x"85";
when x"04B" => DATA <= x"F7";
when x"04C" => DATA <= x"A9";
when x"04D" => DATA <= x"00";
when x"04E" => DATA <= x"85";
when x"04F" => DATA <= x"FF";
when x"050" => DATA <= x"85";
when x"051" => DATA <= x"F2";
when x"052" => DATA <= x"A9";
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when x"054" => DATA <= x"85";
when x"055" => DATA <= x"F3";
when x"056" => DATA <= x"4C";
when x"057" => DATA <= x"00";
when x"058" => DATA <= x"01";
when x"059" => DATA <= x"AD";
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when x"05B" => DATA <= x"FE";
when x"05C" => DATA <= x"58";
when x"05D" => DATA <= x"4C";
when x"05E" => DATA <= x"60";
when x"05F" => DATA <= x"F8";
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when x"061" => DATA <= x"A5";
when x"062" => DATA <= x"FE";
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when x"064" => DATA <= x"41";
when x"065" => DATA <= x"63";
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when x"067" => DATA <= x"72";
when x"068" => DATA <= x"6E";
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when x"06A" => DATA <= x"54";
when x"06B" => DATA <= x"55";
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when x"06D" => DATA <= x"45";
when x"06E" => DATA <= x"20";
when x"06F" => DATA <= x"3F";
when x"070" => DATA <= x"3F";
when x"071" => DATA <= x"4D";
when x"072" => DATA <= x"48";
when x"073" => DATA <= x"7A";
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when x"075" => DATA <= x"36";
when x"076" => DATA <= x"35";
when x"077" => DATA <= x"43";
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when x"079" => DATA <= x"30";
when x"07A" => DATA <= x"32";
when x"07B" => DATA <= x"20";
when x"07C" => DATA <= x"43";
when x"07D" => DATA <= x"6F";
when x"07E" => DATA <= x"2D";
when x"07F" => DATA <= x"50";
when x"080" => DATA <= x"72";
when x"081" => DATA <= x"6F";
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when x"083" => DATA <= x"0A";
when x"084" => DATA <= x"0D";
when x"085" => DATA <= x"00";
when x"086" => DATA <= x"EA";
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when x"088" => DATA <= x"98";
when x"089" => DATA <= x"8D";
when x"08A" => DATA <= x"5E";
when x"08B" => DATA <= x"F8";
when x"08C" => DATA <= x"A9";
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when x"08E" => DATA <= x"8D";
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when x"090" => DATA <= x"F8";
when x"091" => DATA <= x"20";
when x"092" => DATA <= x"80";
when x"093" => DATA <= x"F9";
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when x"095" => DATA <= x"80";
when x"096" => DATA <= x"F0";
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when x"098" => DATA <= x"A9";
when x"099" => DATA <= x"2A";
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when x"09B" => DATA <= x"EE";
when x"09C" => DATA <= x"FF";
when x"09D" => DATA <= x"A2";
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when x"09F" => DATA <= x"A0";
when x"0A0" => DATA <= x"F9";
when x"0A1" => DATA <= x"A9";
when x"0A2" => DATA <= x"00";
when x"0A3" => DATA <= x"20";
when x"0A4" => DATA <= x"F1";
when x"0A5" => DATA <= x"FF";
when x"0A6" => DATA <= x"B0";
when x"0A7" => DATA <= x"0A";
when x"0A8" => DATA <= x"A2";
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when x"0AA" => DATA <= x"A0";
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when x"0AC" => DATA <= x"20";
when x"0AD" => DATA <= x"F7";
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when x"0AF" => DATA <= x"4C";
when x"0B0" => DATA <= x"98";
when x"0B1" => DATA <= x"F8";
when x"0B2" => DATA <= x"A9";
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when x"0B5" => DATA <= x"F4";
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when x"0B7" => DATA <= x"00";
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when x"0BA" => DATA <= x"73";
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when x"0BD" => DATA <= x"70";
when x"0BE" => DATA <= x"65";
when x"0BF" => DATA <= x"00";
when x"0C0" => DATA <= x"A5";
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when x"0C2" => DATA <= x"85";
when x"0C3" => DATA <= x"EE";
when x"0C4" => DATA <= x"85";
when x"0C5" => DATA <= x"F2";
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when x"0C8" => DATA <= x"85";
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when x"0CA" => DATA <= x"85";
when x"0CB" => DATA <= x"F3";
when x"0CC" => DATA <= x"A0";
when x"0CD" => DATA <= x"07";
when x"0CE" => DATA <= x"B1";
when x"0CF" => DATA <= x"EE";
when x"0D0" => DATA <= x"D8";
when x"0D1" => DATA <= x"18";
when x"0D2" => DATA <= x"65";
when x"0D3" => DATA <= x"EE";
when x"0D4" => DATA <= x"85";
when x"0D5" => DATA <= x"FD";
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when x"0D8" => DATA <= x"65";
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when x"0DC" => DATA <= x"A0";
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when x"0E0" => DATA <= x"D0";
when x"0E1" => DATA <= x"23";
when x"0E2" => DATA <= x"C8";
when x"0E3" => DATA <= x"B1";
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when x"0E5" => DATA <= x"C9";
when x"0E6" => DATA <= x"28";
when x"0E7" => DATA <= x"D0";
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when x"0EA" => DATA <= x"B1";
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when x"0EC" => DATA <= x"C9";
when x"0ED" => DATA <= x"43";
when x"0EE" => DATA <= x"D0";
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when x"0F0" => DATA <= x"C8";
when x"0F1" => DATA <= x"B1";
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when x"0F3" => DATA <= x"C9";
when x"0F4" => DATA <= x"29";
when x"0F5" => DATA <= x"D0";
when x"0F6" => DATA <= x"0E";
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when x"0F8" => DATA <= x"06";
when x"0F9" => DATA <= x"B1";
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when x"0FB" => DATA <= x"29";
when x"0FC" => DATA <= x"4F";
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when x"0FF" => DATA <= x"90";
when x"100" => DATA <= x"09";
when x"101" => DATA <= x"29";
when x"102" => DATA <= x"0D";
when x"103" => DATA <= x"D0";
when x"104" => DATA <= x"28";
when x"105" => DATA <= x"A9";
when x"106" => DATA <= x"01";
when x"107" => DATA <= x"6C";
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when x"109" => DATA <= x"00";
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when x"10E" => DATA <= x"02";
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when x"113" => DATA <= x"02";
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when x"117" => DATA <= x"68";
when x"118" => DATA <= x"69";
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when x"11B" => DATA <= x"69";
when x"11C" => DATA <= x"73";
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when x"11E" => DATA <= x"6E";
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when x"120" => DATA <= x"74";
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when x"127" => DATA <= x"67";
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when x"135" => DATA <= x"03";
when x"136" => DATA <= x"02";
when x"137" => DATA <= x"00";
when x"138" => DATA <= x"00";
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when x"13A" => DATA <= x"20";
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when x"13C" => DATA <= x"61";
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when x"13F" => DATA <= x"6F";
when x"140" => DATA <= x"74";
when x"141" => DATA <= x"20";
when x"142" => DATA <= x"72";
when x"143" => DATA <= x"75";
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when x"148" => DATA <= x"69";
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when x"14E" => DATA <= x"65";
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when x"150" => DATA <= x"A2";
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when x"155" => DATA <= x"FF";
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when x"157" => DATA <= x"01";
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when x"15A" => DATA <= x"F0";
when x"15B" => DATA <= x"06";
when x"15C" => DATA <= x"20";
when x"15D" => DATA <= x"EE";
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when x"15F" => DATA <= x"C8";
when x"160" => DATA <= x"D0";
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when x"162" => DATA <= x"20";
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when x"168" => DATA <= x"36";
when x"169" => DATA <= x"02";
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when x"16B" => DATA <= x"20";
when x"16C" => DATA <= x"FF";
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when x"16F" => DATA <= x"FE";
when x"170" => DATA <= x"EA";
when x"171" => DATA <= x"50";
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when x"175" => DATA <= x"FE";
when x"176" => DATA <= x"60";
when x"177" => DATA <= x"A9";
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when x"180" => DATA <= x"2C";
when x"181" => DATA <= x"FA";
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when x"187" => DATA <= x"FE";
when x"188" => DATA <= x"60";
when x"189" => DATA <= x"C8";
when x"18A" => DATA <= x"B1";
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when x"190" => DATA <= x"60";
when x"191" => DATA <= x"A2";
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when x"195" => DATA <= x"86";
when x"196" => DATA <= x"F1";
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when x"198" => DATA <= x"F8";
when x"199" => DATA <= x"C9";
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when x"19B" => DATA <= x"90";
when x"19C" => DATA <= x"1F";
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when x"19E" => DATA <= x"3A";
when x"19F" => DATA <= x"90";
when x"1A0" => DATA <= x"0A";
when x"1A1" => DATA <= x"29";
when x"1A2" => DATA <= x"DF";
when x"1A3" => DATA <= x"E9";
when x"1A4" => DATA <= x"07";
when x"1A5" => DATA <= x"90";
when x"1A6" => DATA <= x"15";
when x"1A7" => DATA <= x"C9";
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when x"1A9" => DATA <= x"B0";
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when x"1AB" => DATA <= x"0A";
when x"1AC" => DATA <= x"0A";
when x"1AD" => DATA <= x"0A";
when x"1AE" => DATA <= x"0A";
when x"1AF" => DATA <= x"A2";
when x"1B0" => DATA <= x"03";
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when x"1B2" => DATA <= x"26";
when x"1B3" => DATA <= x"F0";
when x"1B4" => DATA <= x"26";
when x"1B5" => DATA <= x"F1";
when x"1B6" => DATA <= x"CA";
when x"1B7" => DATA <= x"10";
when x"1B8" => DATA <= x"F8";
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when x"1BA" => DATA <= x"D0";
when x"1BB" => DATA <= x"DB";
when x"1BC" => DATA <= x"60";
when x"1BD" => DATA <= x"86";
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when x"1BF" => DATA <= x"84";
when x"1C0" => DATA <= x"F9";
when x"1C1" => DATA <= x"A0";
when x"1C2" => DATA <= x"00";
when x"1C3" => DATA <= x"2C";
when x"1C4" => DATA <= x"FA";
when x"1C5" => DATA <= x"FE";
when x"1C6" => DATA <= x"50";
when x"1C7" => DATA <= x"FB";
when x"1C8" => DATA <= x"B1";
when x"1C9" => DATA <= x"F8";
when x"1CA" => DATA <= x"8D";
when x"1CB" => DATA <= x"FB";
when x"1CC" => DATA <= x"FE";
when x"1CD" => DATA <= x"C8";
when x"1CE" => DATA <= x"C9";
when x"1CF" => DATA <= x"0D";
when x"1D0" => DATA <= x"D0";
when x"1D1" => DATA <= x"F1";
when x"1D2" => DATA <= x"A4";
when x"1D3" => DATA <= x"F9";
when x"1D4" => DATA <= x"60";
when x"1D5" => DATA <= x"48";
when x"1D6" => DATA <= x"86";
when x"1D7" => DATA <= x"F8";
when x"1D8" => DATA <= x"84";
when x"1D9" => DATA <= x"F9";
when x"1DA" => DATA <= x"A0";
when x"1DB" => DATA <= x"00";
when x"1DC" => DATA <= x"20";
when x"1DD" => DATA <= x"8A";
when x"1DE" => DATA <= x"F9";
when x"1DF" => DATA <= x"C8";
when x"1E0" => DATA <= x"C9";
when x"1E1" => DATA <= x"2A";
when x"1E2" => DATA <= x"F0";
when x"1E3" => DATA <= x"F8";
when x"1E4" => DATA <= x"29";
when x"1E5" => DATA <= x"DF";
when x"1E6" => DATA <= x"AA";
when x"1E7" => DATA <= x"B1";
when x"1E8" => DATA <= x"F8";
when x"1E9" => DATA <= x"E0";
when x"1EA" => DATA <= x"47";
when x"1EB" => DATA <= x"F0";
when x"1EC" => DATA <= x"5E";
when x"1ED" => DATA <= x"E0";
when x"1EE" => DATA <= x"48";
when x"1EF" => DATA <= x"D0";
when x"1F0" => DATA <= x"49";
when x"1F1" => DATA <= x"C9";
when x"1F2" => DATA <= x"2E";
when x"1F3" => DATA <= x"F0";
when x"1F4" => DATA <= x"2D";
when x"1F5" => DATA <= x"29";
when x"1F6" => DATA <= x"DF";
when x"1F7" => DATA <= x"C9";
when x"1F8" => DATA <= x"45";
when x"1F9" => DATA <= x"D0";
when x"1FA" => DATA <= x"3F";
when x"1FB" => DATA <= x"C8";
when x"1FC" => DATA <= x"B1";
when x"1FD" => DATA <= x"F8";
when x"1FE" => DATA <= x"C9";
when x"1FF" => DATA <= x"2E";
when x"200" => DATA <= x"F0";
when x"201" => DATA <= x"20";
when x"202" => DATA <= x"29";
when x"203" => DATA <= x"DF";
when x"204" => DATA <= x"C9";
when x"205" => DATA <= x"4C";
when x"206" => DATA <= x"D0";
when x"207" => DATA <= x"32";
when x"208" => DATA <= x"C8";
when x"209" => DATA <= x"B1";
when x"20A" => DATA <= x"F8";
when x"20B" => DATA <= x"C9";
when x"20C" => DATA <= x"2E";
when x"20D" => DATA <= x"F0";
when x"20E" => DATA <= x"13";
when x"20F" => DATA <= x"29";
when x"210" => DATA <= x"DF";
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when x"212" => DATA <= x"50";
when x"213" => DATA <= x"D0";
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when x"215" => DATA <= x"C8";
when x"216" => DATA <= x"B1";
when x"217" => DATA <= x"F8";
when x"218" => DATA <= x"29";
when x"219" => DATA <= x"DF";
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when x"21B" => DATA <= x"41";
when x"21C" => DATA <= x"90";
when x"21D" => DATA <= x"04";
when x"21E" => DATA <= x"C9";
when x"21F" => DATA <= x"5B";
when x"220" => DATA <= x"90";
when x"221" => DATA <= x"18";
when x"222" => DATA <= x"20";
when x"223" => DATA <= x"A5";
when x"224" => DATA <= x"FE";
when x"225" => DATA <= x"0A";
when x"226" => DATA <= x"0D";
when x"227" => DATA <= x"36";
when x"228" => DATA <= x"35";
when x"229" => DATA <= x"43";
when x"22A" => DATA <= x"31";
when x"22B" => DATA <= x"30";
when x"22C" => DATA <= x"32";
when x"22D" => DATA <= x"20";
when x"22E" => DATA <= x"54";
when x"22F" => DATA <= x"55";
when x"230" => DATA <= x"42";
when x"231" => DATA <= x"45";
when x"232" => DATA <= x"20";
when x"233" => DATA <= x"31";
when x"234" => DATA <= x"2E";
when x"235" => DATA <= x"31";
when x"236" => DATA <= x"30";
when x"237" => DATA <= x"0A";
when x"238" => DATA <= x"0D";
when x"239" => DATA <= x"EA";
when x"23A" => DATA <= x"A9";
when x"23B" => DATA <= x"02";
when x"23C" => DATA <= x"20";
when x"23D" => DATA <= x"57";
when x"23E" => DATA <= x"FC";
when x"23F" => DATA <= x"20";
when x"240" => DATA <= x"C1";
when x"241" => DATA <= x"F9";
when x"242" => DATA <= x"20";
when x"243" => DATA <= x"80";
when x"244" => DATA <= x"F9";
when x"245" => DATA <= x"C9";
when x"246" => DATA <= x"80";
when x"247" => DATA <= x"F0";
when x"248" => DATA <= x"20";
when x"249" => DATA <= x"68";
when x"24A" => DATA <= x"60";
when x"24B" => DATA <= x"29";
when x"24C" => DATA <= x"DF";
when x"24D" => DATA <= x"C9";
when x"24E" => DATA <= x"4F";
when x"24F" => DATA <= x"D0";
when x"250" => DATA <= x"E9";
when x"251" => DATA <= x"20";
when x"252" => DATA <= x"89";
when x"253" => DATA <= x"F9";
when x"254" => DATA <= x"20";
when x"255" => DATA <= x"91";
when x"256" => DATA <= x"F9";
when x"257" => DATA <= x"20";
when x"258" => DATA <= x"8A";
when x"259" => DATA <= x"F9";
when x"25A" => DATA <= x"C9";
when x"25B" => DATA <= x"0D";
when x"25C" => DATA <= x"D0";
when x"25D" => DATA <= x"DC";
when x"25E" => DATA <= x"8A";
when x"25F" => DATA <= x"F0";
when x"260" => DATA <= x"08";
when x"261" => DATA <= x"A5";
when x"262" => DATA <= x"F0";
when x"263" => DATA <= x"85";
when x"264" => DATA <= x"F6";
when x"265" => DATA <= x"A5";
when x"266" => DATA <= x"F1";
when x"267" => DATA <= x"85";
when x"268" => DATA <= x"F7";
when x"269" => DATA <= x"A5";
when x"26A" => DATA <= x"EF";
when x"26B" => DATA <= x"48";
when x"26C" => DATA <= x"A5";
when x"26D" => DATA <= x"EE";
when x"26E" => DATA <= x"48";
when x"26F" => DATA <= x"20";
when x"270" => DATA <= x"C0";
when x"271" => DATA <= x"F8";
when x"272" => DATA <= x"68";
when x"273" => DATA <= x"85";
when x"274" => DATA <= x"EE";
when x"275" => DATA <= x"85";
when x"276" => DATA <= x"F2";
when x"277" => DATA <= x"68";
when x"278" => DATA <= x"85";
when x"279" => DATA <= x"EF";
when x"27A" => DATA <= x"85";
when x"27B" => DATA <= x"F3";
when x"27C" => DATA <= x"68";
when x"27D" => DATA <= x"60";
when x"27E" => DATA <= x"F0";
when x"27F" => DATA <= x"C2";
when x"280" => DATA <= x"C9";
when x"281" => DATA <= x"80";
when x"282" => DATA <= x"B0";
when x"283" => DATA <= x"25";
when x"284" => DATA <= x"48";
when x"285" => DATA <= x"A9";
when x"286" => DATA <= x"04";
when x"287" => DATA <= x"2C";
when x"288" => DATA <= x"FA";
when x"289" => DATA <= x"FE";
when x"28A" => DATA <= x"50";
when x"28B" => DATA <= x"FB";
when x"28C" => DATA <= x"8D";
when x"28D" => DATA <= x"FB";
when x"28E" => DATA <= x"FE";
when x"28F" => DATA <= x"2C";
when x"290" => DATA <= x"FA";
when x"291" => DATA <= x"FE";
when x"292" => DATA <= x"50";
when x"293" => DATA <= x"FB";
when x"294" => DATA <= x"8E";
when x"295" => DATA <= x"FB";
when x"296" => DATA <= x"FE";
when x"297" => DATA <= x"68";
when x"298" => DATA <= x"2C";
when x"299" => DATA <= x"FA";
when x"29A" => DATA <= x"FE";
when x"29B" => DATA <= x"50";
when x"29C" => DATA <= x"FB";
when x"29D" => DATA <= x"8D";
when x"29E" => DATA <= x"FB";
when x"29F" => DATA <= x"FE";
when x"2A0" => DATA <= x"2C";
when x"2A1" => DATA <= x"FA";
when x"2A2" => DATA <= x"FE";
when x"2A3" => DATA <= x"10";
when x"2A4" => DATA <= x"FB";
when x"2A5" => DATA <= x"AE";
when x"2A6" => DATA <= x"FB";
when x"2A7" => DATA <= x"FE";
when x"2A8" => DATA <= x"60";
when x"2A9" => DATA <= x"C9";
when x"2AA" => DATA <= x"82";
when x"2AB" => DATA <= x"F0";
when x"2AC" => DATA <= x"5A";
when x"2AD" => DATA <= x"C9";
when x"2AE" => DATA <= x"83";
when x"2AF" => DATA <= x"F0";
when x"2B0" => DATA <= x"51";
when x"2B1" => DATA <= x"C9";
when x"2B2" => DATA <= x"84";
when x"2B3" => DATA <= x"F0";
when x"2B4" => DATA <= x"48";
when x"2B5" => DATA <= x"48";
when x"2B6" => DATA <= x"A9";
when x"2B7" => DATA <= x"06";
when x"2B8" => DATA <= x"2C";
when x"2B9" => DATA <= x"FA";
when x"2BA" => DATA <= x"FE";
when x"2BB" => DATA <= x"50";
when x"2BC" => DATA <= x"FB";
when x"2BD" => DATA <= x"8D";
when x"2BE" => DATA <= x"FB";
when x"2BF" => DATA <= x"FE";
when x"2C0" => DATA <= x"2C";
when x"2C1" => DATA <= x"FA";
when x"2C2" => DATA <= x"FE";
when x"2C3" => DATA <= x"50";
when x"2C4" => DATA <= x"FB";
when x"2C5" => DATA <= x"8E";
when x"2C6" => DATA <= x"FB";
when x"2C7" => DATA <= x"FE";
when x"2C8" => DATA <= x"2C";
when x"2C9" => DATA <= x"FA";
when x"2CA" => DATA <= x"FE";
when x"2CB" => DATA <= x"50";
when x"2CC" => DATA <= x"FB";
when x"2CD" => DATA <= x"8C";
when x"2CE" => DATA <= x"FB";
when x"2CF" => DATA <= x"FE";
when x"2D0" => DATA <= x"68";
when x"2D1" => DATA <= x"2C";
when x"2D2" => DATA <= x"FA";
when x"2D3" => DATA <= x"FE";
when x"2D4" => DATA <= x"50";
when x"2D5" => DATA <= x"FB";
when x"2D6" => DATA <= x"8D";
when x"2D7" => DATA <= x"FB";
when x"2D8" => DATA <= x"FE";
when x"2D9" => DATA <= x"C9";
when x"2DA" => DATA <= x"8E";
when x"2DB" => DATA <= x"F0";
when x"2DC" => DATA <= x"A1";
when x"2DD" => DATA <= x"C9";
when x"2DE" => DATA <= x"9D";
when x"2DF" => DATA <= x"F0";
when x"2E0" => DATA <= x"1B";
when x"2E1" => DATA <= x"48";
when x"2E2" => DATA <= x"2C";
when x"2E3" => DATA <= x"FA";
when x"2E4" => DATA <= x"FE";
when x"2E5" => DATA <= x"10";
when x"2E6" => DATA <= x"FB";
when x"2E7" => DATA <= x"AD";
when x"2E8" => DATA <= x"FB";
when x"2E9" => DATA <= x"FE";
when x"2EA" => DATA <= x"0A";
when x"2EB" => DATA <= x"68";
when x"2EC" => DATA <= x"2C";
when x"2ED" => DATA <= x"FA";
when x"2EE" => DATA <= x"FE";
when x"2EF" => DATA <= x"10";
when x"2F0" => DATA <= x"FB";
when x"2F1" => DATA <= x"AC";
when x"2F2" => DATA <= x"FB";
when x"2F3" => DATA <= x"FE";
when x"2F4" => DATA <= x"2C";
when x"2F5" => DATA <= x"FA";
when x"2F6" => DATA <= x"FE";
when x"2F7" => DATA <= x"10";
when x"2F8" => DATA <= x"FB";
when x"2F9" => DATA <= x"AE";
when x"2FA" => DATA <= x"FB";
when x"2FB" => DATA <= x"FE";
when x"2FC" => DATA <= x"60";
when x"2FD" => DATA <= x"A6";
when x"2FE" => DATA <= x"F2";
when x"2FF" => DATA <= x"A4";
when x"300" => DATA <= x"F3";
when x"301" => DATA <= x"60";
when x"302" => DATA <= x"A2";
when x"303" => DATA <= x"00";
when x"304" => DATA <= x"A0";
when x"305" => DATA <= x"08";
when x"306" => DATA <= x"60";
when x"307" => DATA <= x"A2";
when x"308" => DATA <= x"00";
when x"309" => DATA <= x"A0";
when x"30A" => DATA <= x"00";
when x"30B" => DATA <= x"60";
when x"30C" => DATA <= x"86";
when x"30D" => DATA <= x"F8";
when x"30E" => DATA <= x"84";
when x"30F" => DATA <= x"F9";
when x"310" => DATA <= x"A8";
when x"311" => DATA <= x"F0";
when x"312" => DATA <= x"71";
when x"313" => DATA <= x"48";
when x"314" => DATA <= x"A0";
when x"315" => DATA <= x"08";
when x"316" => DATA <= x"2C";
when x"317" => DATA <= x"FA";
when x"318" => DATA <= x"FE";
when x"319" => DATA <= x"50";
when x"31A" => DATA <= x"FB";
when x"31B" => DATA <= x"8C";
when x"31C" => DATA <= x"FB";
when x"31D" => DATA <= x"FE";
when x"31E" => DATA <= x"2C";
when x"31F" => DATA <= x"FA";
when x"320" => DATA <= x"FE";
when x"321" => DATA <= x"50";
when x"322" => DATA <= x"FB";
when x"323" => DATA <= x"8D";
when x"324" => DATA <= x"FB";
when x"325" => DATA <= x"FE";
when x"326" => DATA <= x"AA";
when x"327" => DATA <= x"10";
when x"328" => DATA <= x"08";
when x"329" => DATA <= x"A0";
when x"32A" => DATA <= x"00";
when x"32B" => DATA <= x"B1";
when x"32C" => DATA <= x"F8";
when x"32D" => DATA <= x"A8";
when x"32E" => DATA <= x"4C";
when x"32F" => DATA <= x"3A";
when x"330" => DATA <= x"FB";
when x"331" => DATA <= x"BC";
when x"332" => DATA <= x"C9";
when x"333" => DATA <= x"FC";
when x"334" => DATA <= x"E0";
when x"335" => DATA <= x"15";
when x"336" => DATA <= x"90";
when x"337" => DATA <= x"02";
when x"338" => DATA <= x"A0";
when x"339" => DATA <= x"10";
when x"33A" => DATA <= x"2C";
when x"33B" => DATA <= x"FA";
when x"33C" => DATA <= x"FE";
when x"33D" => DATA <= x"50";
when x"33E" => DATA <= x"FB";
when x"33F" => DATA <= x"8C";
when x"340" => DATA <= x"FB";
when x"341" => DATA <= x"FE";
when x"342" => DATA <= x"88";
when x"343" => DATA <= x"30";
when x"344" => DATA <= x"0D";
when x"345" => DATA <= x"2C";
when x"346" => DATA <= x"FA";
when x"347" => DATA <= x"FE";
when x"348" => DATA <= x"50";
when x"349" => DATA <= x"FB";
when x"34A" => DATA <= x"B1";
when x"34B" => DATA <= x"F8";
when x"34C" => DATA <= x"8D";
when x"34D" => DATA <= x"FB";
when x"34E" => DATA <= x"FE";
when x"34F" => DATA <= x"88";
when x"350" => DATA <= x"10";
when x"351" => DATA <= x"F3";
when x"352" => DATA <= x"8A";
when x"353" => DATA <= x"10";
when x"354" => DATA <= x"08";
when x"355" => DATA <= x"A0";
when x"356" => DATA <= x"01";
when x"357" => DATA <= x"B1";
when x"358" => DATA <= x"F8";
when x"359" => DATA <= x"A8";
when x"35A" => DATA <= x"4C";
when x"35B" => DATA <= x"66";
when x"35C" => DATA <= x"FB";
when x"35D" => DATA <= x"BC";
when x"35E" => DATA <= x"DD";
when x"35F" => DATA <= x"FC";
when x"360" => DATA <= x"E0";
when x"361" => DATA <= x"15";
when x"362" => DATA <= x"90";
when x"363" => DATA <= x"02";
when x"364" => DATA <= x"A0";
when x"365" => DATA <= x"10";
when x"366" => DATA <= x"2C";
when x"367" => DATA <= x"FA";
when x"368" => DATA <= x"FE";
when x"369" => DATA <= x"50";
when x"36A" => DATA <= x"FB";
when x"36B" => DATA <= x"8C";
when x"36C" => DATA <= x"FB";
when x"36D" => DATA <= x"FE";
when x"36E" => DATA <= x"88";
when x"36F" => DATA <= x"30";
when x"370" => DATA <= x"0D";
when x"371" => DATA <= x"2C";
when x"372" => DATA <= x"FA";
when x"373" => DATA <= x"FE";
when x"374" => DATA <= x"10";
when x"375" => DATA <= x"FB";
when x"376" => DATA <= x"AD";
when x"377" => DATA <= x"FB";
when x"378" => DATA <= x"FE";
when x"379" => DATA <= x"91";
when x"37A" => DATA <= x"F8";
when x"37B" => DATA <= x"88";
when x"37C" => DATA <= x"10";
when x"37D" => DATA <= x"F3";
when x"37E" => DATA <= x"A4";
when x"37F" => DATA <= x"F9";
when x"380" => DATA <= x"A6";
when x"381" => DATA <= x"F8";
when x"382" => DATA <= x"68";
when x"383" => DATA <= x"60";
when x"384" => DATA <= x"A9";
when x"385" => DATA <= x"0A";
when x"386" => DATA <= x"20";
when x"387" => DATA <= x"57";
when x"388" => DATA <= x"FC";
when x"389" => DATA <= x"A0";
when x"38A" => DATA <= x"04";
when x"38B" => DATA <= x"2C";
when x"38C" => DATA <= x"FA";
when x"38D" => DATA <= x"FE";
when x"38E" => DATA <= x"50";
when x"38F" => DATA <= x"FB";
when x"390" => DATA <= x"B1";
when x"391" => DATA <= x"F8";
when x"392" => DATA <= x"8D";
when x"393" => DATA <= x"FB";
when x"394" => DATA <= x"FE";
when x"395" => DATA <= x"88";
when x"396" => DATA <= x"C0";
when x"397" => DATA <= x"01";
when x"398" => DATA <= x"D0";
when x"399" => DATA <= x"F1";
when x"39A" => DATA <= x"A9";
when x"39B" => DATA <= x"07";
when x"39C" => DATA <= x"20";
when x"39D" => DATA <= x"57";
when x"39E" => DATA <= x"FC";
when x"39F" => DATA <= x"B1";
when x"3A0" => DATA <= x"F8";
when x"3A1" => DATA <= x"48";
when x"3A2" => DATA <= x"88";
when x"3A3" => DATA <= x"2C";
when x"3A4" => DATA <= x"FA";
when x"3A5" => DATA <= x"FE";
when x"3A6" => DATA <= x"50";
when x"3A7" => DATA <= x"FB";
when x"3A8" => DATA <= x"8C";
when x"3A9" => DATA <= x"FB";
when x"3AA" => DATA <= x"FE";
when x"3AB" => DATA <= x"B1";
when x"3AC" => DATA <= x"F8";
when x"3AD" => DATA <= x"48";
when x"3AE" => DATA <= x"A2";
when x"3AF" => DATA <= x"FF";
when x"3B0" => DATA <= x"20";
when x"3B1" => DATA <= x"80";
when x"3B2" => DATA <= x"F9";
when x"3B3" => DATA <= x"C9";
when x"3B4" => DATA <= x"80";
when x"3B5" => DATA <= x"B0";
when x"3B6" => DATA <= x"1D";
when x"3B7" => DATA <= x"68";
when x"3B8" => DATA <= x"85";
when x"3B9" => DATA <= x"F8";
when x"3BA" => DATA <= x"68";
when x"3BB" => DATA <= x"85";
when x"3BC" => DATA <= x"F9";
when x"3BD" => DATA <= x"A0";
when x"3BE" => DATA <= x"00";
when x"3BF" => DATA <= x"2C";
when x"3C0" => DATA <= x"FA";
when x"3C1" => DATA <= x"FE";
when x"3C2" => DATA <= x"10";
when x"3C3" => DATA <= x"FB";
when x"3C4" => DATA <= x"AD";
when x"3C5" => DATA <= x"FB";
when x"3C6" => DATA <= x"FE";
when x"3C7" => DATA <= x"91";
when x"3C8" => DATA <= x"F8";
when x"3C9" => DATA <= x"C8";
when x"3CA" => DATA <= x"C9";
when x"3CB" => DATA <= x"0D";
when x"3CC" => DATA <= x"D0";
when x"3CD" => DATA <= x"F1";
when x"3CE" => DATA <= x"A9";
when x"3CF" => DATA <= x"00";
when x"3D0" => DATA <= x"88";
when x"3D1" => DATA <= x"18";
when x"3D2" => DATA <= x"E8";
when x"3D3" => DATA <= x"60";
when x"3D4" => DATA <= x"68";
when x"3D5" => DATA <= x"68";
when x"3D6" => DATA <= x"A9";
when x"3D7" => DATA <= x"00";
when x"3D8" => DATA <= x"60";
when x"3D9" => DATA <= x"48";
when x"3DA" => DATA <= x"A9";
when x"3DB" => DATA <= x"0C";
when x"3DC" => DATA <= x"20";
when x"3DD" => DATA <= x"57";
when x"3DE" => DATA <= x"FC";
when x"3DF" => DATA <= x"2C";
when x"3E0" => DATA <= x"FA";
when x"3E1" => DATA <= x"FE";
when x"3E2" => DATA <= x"50";
when x"3E3" => DATA <= x"FB";
when x"3E4" => DATA <= x"8C";
when x"3E5" => DATA <= x"FB";
when x"3E6" => DATA <= x"FE";
when x"3E7" => DATA <= x"B5";
when x"3E8" => DATA <= x"03";
when x"3E9" => DATA <= x"20";
when x"3EA" => DATA <= x"57";
when x"3EB" => DATA <= x"FC";
when x"3EC" => DATA <= x"B5";
when x"3ED" => DATA <= x"02";
when x"3EE" => DATA <= x"20";
when x"3EF" => DATA <= x"57";
when x"3F0" => DATA <= x"FC";
when x"3F1" => DATA <= x"B5";
when x"3F2" => DATA <= x"01";
when x"3F3" => DATA <= x"20";
when x"3F4" => DATA <= x"57";
when x"3F5" => DATA <= x"FC";
when x"3F6" => DATA <= x"B5";
when x"3F7" => DATA <= x"00";
when x"3F8" => DATA <= x"20";
when x"3F9" => DATA <= x"57";
when x"3FA" => DATA <= x"FC";
when x"3FB" => DATA <= x"68";
when x"3FC" => DATA <= x"20";
when x"3FD" => DATA <= x"57";
when x"3FE" => DATA <= x"FC";
when x"3FF" => DATA <= x"20";
when x"400" => DATA <= x"80";
when x"401" => DATA <= x"F9";
when x"402" => DATA <= x"48";
when x"403" => DATA <= x"20";
when x"404" => DATA <= x"80";
when x"405" => DATA <= x"F9";
when x"406" => DATA <= x"95";
when x"407" => DATA <= x"03";
when x"408" => DATA <= x"20";
when x"409" => DATA <= x"80";
when x"40A" => DATA <= x"F9";
when x"40B" => DATA <= x"95";
when x"40C" => DATA <= x"02";
when x"40D" => DATA <= x"20";
when x"40E" => DATA <= x"80";
when x"40F" => DATA <= x"F9";
when x"410" => DATA <= x"95";
when x"411" => DATA <= x"01";
when x"412" => DATA <= x"20";
when x"413" => DATA <= x"80";
when x"414" => DATA <= x"F9";
when x"415" => DATA <= x"95";
when x"416" => DATA <= x"00";
when x"417" => DATA <= x"68";
when x"418" => DATA <= x"60";
when x"419" => DATA <= x"48";
when x"41A" => DATA <= x"A9";
when x"41B" => DATA <= x"12";
when x"41C" => DATA <= x"20";
when x"41D" => DATA <= x"57";
when x"41E" => DATA <= x"FC";
when x"41F" => DATA <= x"68";
when x"420" => DATA <= x"20";
when x"421" => DATA <= x"57";
when x"422" => DATA <= x"FC";
when x"423" => DATA <= x"C9";
when x"424" => DATA <= x"00";
when x"425" => DATA <= x"D0";
when x"426" => DATA <= x"0A";
when x"427" => DATA <= x"48";
when x"428" => DATA <= x"98";
when x"429" => DATA <= x"20";
when x"42A" => DATA <= x"57";
when x"42B" => DATA <= x"FC";
when x"42C" => DATA <= x"20";
when x"42D" => DATA <= x"80";
when x"42E" => DATA <= x"F9";
when x"42F" => DATA <= x"68";
when x"430" => DATA <= x"60";
when x"431" => DATA <= x"20";
when x"432" => DATA <= x"BD";
when x"433" => DATA <= x"F9";
when x"434" => DATA <= x"4C";
when x"435" => DATA <= x"80";
when x"436" => DATA <= x"F9";
when x"437" => DATA <= x"A9";
when x"438" => DATA <= x"0E";
when x"439" => DATA <= x"20";
when x"43A" => DATA <= x"57";
when x"43B" => DATA <= x"FC";
when x"43C" => DATA <= x"98";
when x"43D" => DATA <= x"20";
when x"43E" => DATA <= x"57";
when x"43F" => DATA <= x"FC";
when x"440" => DATA <= x"4C";
when x"441" => DATA <= x"7C";
when x"442" => DATA <= x"F9";
when x"443" => DATA <= x"48";
when x"444" => DATA <= x"A9";
when x"445" => DATA <= x"10";
when x"446" => DATA <= x"20";
when x"447" => DATA <= x"57";
when x"448" => DATA <= x"FC";
when x"449" => DATA <= x"98";
when x"44A" => DATA <= x"20";
when x"44B" => DATA <= x"57";
when x"44C" => DATA <= x"FC";
when x"44D" => DATA <= x"68";
when x"44E" => DATA <= x"20";
when x"44F" => DATA <= x"57";
when x"450" => DATA <= x"FC";
when x"451" => DATA <= x"48";
when x"452" => DATA <= x"20";
when x"453" => DATA <= x"80";
when x"454" => DATA <= x"F9";
when x"455" => DATA <= x"68";
when x"456" => DATA <= x"60";
when x"457" => DATA <= x"2C";
when x"458" => DATA <= x"FA";
when x"459" => DATA <= x"FE";
when x"45A" => DATA <= x"50";
when x"45B" => DATA <= x"FB";
when x"45C" => DATA <= x"8D";
when x"45D" => DATA <= x"FB";
when x"45E" => DATA <= x"FE";
when x"45F" => DATA <= x"60";
when x"460" => DATA <= x"84";
when x"461" => DATA <= x"FB";
when x"462" => DATA <= x"86";
when x"463" => DATA <= x"FA";
when x"464" => DATA <= x"48";
when x"465" => DATA <= x"A9";
when x"466" => DATA <= x"14";
when x"467" => DATA <= x"20";
when x"468" => DATA <= x"57";
when x"469" => DATA <= x"FC";
when x"46A" => DATA <= x"A0";
when x"46B" => DATA <= x"11";
when x"46C" => DATA <= x"B1";
when x"46D" => DATA <= x"FA";
when x"46E" => DATA <= x"20";
when x"46F" => DATA <= x"57";
when x"470" => DATA <= x"FC";
when x"471" => DATA <= x"88";
when x"472" => DATA <= x"C0";
when x"473" => DATA <= x"01";
when x"474" => DATA <= x"D0";
when x"475" => DATA <= x"F6";
when x"476" => DATA <= x"88";
when x"477" => DATA <= x"B1";
when x"478" => DATA <= x"FA";
when x"479" => DATA <= x"AA";
when x"47A" => DATA <= x"C8";
when x"47B" => DATA <= x"B1";
when x"47C" => DATA <= x"FA";
when x"47D" => DATA <= x"A8";
when x"47E" => DATA <= x"20";
when x"47F" => DATA <= x"BD";
when x"480" => DATA <= x"F9";
when x"481" => DATA <= x"68";
when x"482" => DATA <= x"20";
when x"483" => DATA <= x"57";
when x"484" => DATA <= x"FC";
when x"485" => DATA <= x"20";
when x"486" => DATA <= x"80";
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when x"488" => DATA <= x"48";
when x"489" => DATA <= x"A0";
when x"48A" => DATA <= x"11";
when x"48B" => DATA <= x"20";
when x"48C" => DATA <= x"80";
when x"48D" => DATA <= x"F9";
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when x"48F" => DATA <= x"FA";
when x"490" => DATA <= x"88";
when x"491" => DATA <= x"C0";
when x"492" => DATA <= x"01";
when x"493" => DATA <= x"D0";
when x"494" => DATA <= x"F6";
when x"495" => DATA <= x"A4";
when x"496" => DATA <= x"FB";
when x"497" => DATA <= x"A6";
when x"498" => DATA <= x"FA";
when x"499" => DATA <= x"68";
when x"49A" => DATA <= x"60";
when x"49B" => DATA <= x"84";
when x"49C" => DATA <= x"FB";
when x"49D" => DATA <= x"86";
when x"49E" => DATA <= x"FA";
when x"49F" => DATA <= x"48";
when x"4A0" => DATA <= x"A9";
when x"4A1" => DATA <= x"16";
when x"4A2" => DATA <= x"20";
when x"4A3" => DATA <= x"57";
when x"4A4" => DATA <= x"FC";
when x"4A5" => DATA <= x"A0";
when x"4A6" => DATA <= x"0C";
when x"4A7" => DATA <= x"B1";
when x"4A8" => DATA <= x"FA";
when x"4A9" => DATA <= x"20";
when x"4AA" => DATA <= x"57";
when x"4AB" => DATA <= x"FC";
when x"4AC" => DATA <= x"88";
when x"4AD" => DATA <= x"10";
when x"4AE" => DATA <= x"F8";
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when x"4B0" => DATA <= x"20";
when x"4B1" => DATA <= x"57";
when x"4B2" => DATA <= x"FC";
when x"4B3" => DATA <= x"A0";
when x"4B4" => DATA <= x"0C";
when x"4B5" => DATA <= x"20";
when x"4B6" => DATA <= x"80";
when x"4B7" => DATA <= x"F9";
when x"4B8" => DATA <= x"91";
when x"4B9" => DATA <= x"FA";
when x"4BA" => DATA <= x"88";
when x"4BB" => DATA <= x"10";
when x"4BC" => DATA <= x"F8";
when x"4BD" => DATA <= x"A4";
when x"4BE" => DATA <= x"FB";
when x"4BF" => DATA <= x"A6";
when x"4C0" => DATA <= x"FA";
when x"4C1" => DATA <= x"4C";
when x"4C2" => DATA <= x"7C";
when x"4C3" => DATA <= x"F9";
when x"4C4" => DATA <= x"00";
when x"4C5" => DATA <= x"FF";
when x"4C6" => DATA <= x"42";
when x"4C7" => DATA <= x"61";
when x"4C8" => DATA <= x"64";
when x"4C9" => DATA <= x"00";
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when x"4CB" => DATA <= x"05";
when x"4CC" => DATA <= x"00";
when x"4CD" => DATA <= x"05";
when x"4CE" => DATA <= x"04";
when x"4CF" => DATA <= x"05";
when x"4D0" => DATA <= x"08";
when x"4D1" => DATA <= x"0E";
when x"4D2" => DATA <= x"04";
when x"4D3" => DATA <= x"01";
when x"4D4" => DATA <= x"01";
when x"4D5" => DATA <= x"05";
when x"4D6" => DATA <= x"00";
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when x"4D9" => DATA <= x"10";
when x"4DA" => DATA <= x"0D";
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when x"4DC" => DATA <= x"04";
when x"4DD" => DATA <= x"80";
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when x"4DF" => DATA <= x"00";
when x"4E0" => DATA <= x"05";
when x"4E1" => DATA <= x"00";
when x"4E2" => DATA <= x"05";
when x"4E3" => DATA <= x"00";
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when x"4E5" => DATA <= x"00";
when x"4E6" => DATA <= x"05";
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when x"4E8" => DATA <= x"05";
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when x"4EA" => DATA <= x"08";
when x"4EB" => DATA <= x"18";
when x"4EC" => DATA <= x"00";
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when x"4EE" => DATA <= x"0D";
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when x"4F0" => DATA <= x"04";
when x"4F1" => DATA <= x"80";
when x"4F2" => DATA <= x"85";
when x"4F3" => DATA <= x"FC";
when x"4F4" => DATA <= x"68";
when x"4F5" => DATA <= x"48";
when x"4F6" => DATA <= x"29";
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when x"4F8" => DATA <= x"D0";
when x"4F9" => DATA <= x"10";
when x"4FA" => DATA <= x"6C";
when x"4FB" => DATA <= x"04";
when x"4FC" => DATA <= x"02";
when x"4FD" => DATA <= x"2C";
when x"4FE" => DATA <= x"FE";
when x"4FF" => DATA <= x"FE";
when x"500" => DATA <= x"30";
when x"501" => DATA <= x"4A";
when x"502" => DATA <= x"2C";
when x"503" => DATA <= x"F8";
when x"504" => DATA <= x"FE";
when x"505" => DATA <= x"30";
when x"506" => DATA <= x"1E";
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when x"508" => DATA <= x"06";
when x"509" => DATA <= x"02";
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when x"50C" => DATA <= x"BA";
when x"50D" => DATA <= x"BD";
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when x"50F" => DATA <= x"01";
when x"510" => DATA <= x"D8";
when x"511" => DATA <= x"38";
when x"512" => DATA <= x"E9";
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when x"514" => DATA <= x"85";
when x"515" => DATA <= x"FD";
when x"516" => DATA <= x"BD";
when x"517" => DATA <= x"04";
when x"518" => DATA <= x"01";
when x"519" => DATA <= x"E9";
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when x"51B" => DATA <= x"85";
when x"51C" => DATA <= x"FE";
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when x"51E" => DATA <= x"AA";
when x"51F" => DATA <= x"A5";
when x"520" => DATA <= x"FC";
when x"521" => DATA <= x"58";
when x"522" => DATA <= x"6C";
when x"523" => DATA <= x"02";
when x"524" => DATA <= x"02";
when x"525" => DATA <= x"AD";
when x"526" => DATA <= x"F9";
when x"527" => DATA <= x"FE";
when x"528" => DATA <= x"30";
when x"529" => DATA <= x"1C";
when x"52A" => DATA <= x"98";
when x"52B" => DATA <= x"48";
when x"52C" => DATA <= x"8A";
when x"52D" => DATA <= x"48";
when x"52E" => DATA <= x"20";
when x"52F" => DATA <= x"8D";
when x"530" => DATA <= x"FE";
when x"531" => DATA <= x"A8";
when x"532" => DATA <= x"20";
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when x"534" => DATA <= x"FE";
when x"535" => DATA <= x"AA";
when x"536" => DATA <= x"20";
when x"537" => DATA <= x"8D";
when x"538" => DATA <= x"FE";
when x"539" => DATA <= x"20";
when x"53A" => DATA <= x"43";
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when x"53C" => DATA <= x"68";
when x"53D" => DATA <= x"AA";
when x"53E" => DATA <= x"68";
when x"53F" => DATA <= x"A8";
when x"540" => DATA <= x"A5";
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when x"542" => DATA <= x"40";
when x"543" => DATA <= x"6C";
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when x"545" => DATA <= x"02";
when x"546" => DATA <= x"0A";
when x"547" => DATA <= x"85";
when x"548" => DATA <= x"FF";
when x"549" => DATA <= x"A5";
when x"54A" => DATA <= x"FC";
when x"54B" => DATA <= x"40";
when x"54C" => DATA <= x"AD";
when x"54D" => DATA <= x"FF";
when x"54E" => DATA <= x"FE";
when x"54F" => DATA <= x"10";
when x"550" => DATA <= x"21";
when x"551" => DATA <= x"58";
when x"552" => DATA <= x"2C";
when x"553" => DATA <= x"FA";
when x"554" => DATA <= x"FE";
when x"555" => DATA <= x"10";
when x"556" => DATA <= x"FB";
when x"557" => DATA <= x"AD";
when x"558" => DATA <= x"FB";
when x"559" => DATA <= x"FE";
when x"55A" => DATA <= x"A9";
when x"55B" => DATA <= x"00";
when x"55C" => DATA <= x"8D";
when x"55D" => DATA <= x"36";
when x"55E" => DATA <= x"02";
when x"55F" => DATA <= x"A8";
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when x"561" => DATA <= x"80";
when x"562" => DATA <= x"F9";
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when x"565" => DATA <= x"02";
when x"566" => DATA <= x"C8";
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when x"568" => DATA <= x"80";
when x"569" => DATA <= x"F9";
when x"56A" => DATA <= x"99";
when x"56B" => DATA <= x"37";
when x"56C" => DATA <= x"02";
when x"56D" => DATA <= x"D0";
when x"56E" => DATA <= x"F7";
when x"56F" => DATA <= x"4C";
when x"570" => DATA <= x"36";
when x"571" => DATA <= x"02";
when x"572" => DATA <= x"8D";
when x"573" => DATA <= x"FA";
when x"574" => DATA <= x"FF";
when x"575" => DATA <= x"98";
when x"576" => DATA <= x"48";
when x"577" => DATA <= x"AC";
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when x"579" => DATA <= x"FF";
when x"57A" => DATA <= x"B9";
when x"57B" => DATA <= x"7D";
when x"57C" => DATA <= x"FE";
when x"57D" => DATA <= x"8D";
when x"57E" => DATA <= x"FA";
when x"57F" => DATA <= x"FF";
when x"580" => DATA <= x"B9";
when x"581" => DATA <= x"85";
when x"582" => DATA <= x"FE";
when x"583" => DATA <= x"8D";
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when x"585" => DATA <= x"FF";
when x"586" => DATA <= x"B9";
when x"587" => DATA <= x"6D";
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when x"589" => DATA <= x"85";
when x"58A" => DATA <= x"F4";
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when x"58C" => DATA <= x"75";
when x"58D" => DATA <= x"FE";
when x"58E" => DATA <= x"85";
when x"58F" => DATA <= x"F5";
when x"590" => DATA <= x"2C";
when x"591" => DATA <= x"FE";
when x"592" => DATA <= x"FE";
when x"593" => DATA <= x"10";
when x"594" => DATA <= x"FB";
when x"595" => DATA <= x"AD";
when x"596" => DATA <= x"FF";
when x"597" => DATA <= x"FE";
when x"598" => DATA <= x"C0";
when x"599" => DATA <= x"05";
when x"59A" => DATA <= x"F0";
when x"59B" => DATA <= x"58";
when x"59C" => DATA <= x"98";
when x"59D" => DATA <= x"48";
when x"59E" => DATA <= x"A0";
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when x"5A0" => DATA <= x"2C";
when x"5A1" => DATA <= x"FE";
when x"5A2" => DATA <= x"FE";
when x"5A3" => DATA <= x"10";
when x"5A4" => DATA <= x"FB";
when x"5A5" => DATA <= x"AD";
when x"5A6" => DATA <= x"FF";
when x"5A7" => DATA <= x"FE";
when x"5A8" => DATA <= x"2C";
when x"5A9" => DATA <= x"FE";
when x"5AA" => DATA <= x"FE";
when x"5AB" => DATA <= x"10";
when x"5AC" => DATA <= x"FB";
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when x"5AE" => DATA <= x"FF";
when x"5AF" => DATA <= x"FE";
when x"5B0" => DATA <= x"2C";
when x"5B1" => DATA <= x"FE";
when x"5B2" => DATA <= x"FE";
when x"5B3" => DATA <= x"10";
when x"5B4" => DATA <= x"FB";
when x"5B5" => DATA <= x"AD";
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when x"5B7" => DATA <= x"FE";
when x"5B8" => DATA <= x"91";
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when x"5BB" => DATA <= x"2C";
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when x"5BD" => DATA <= x"FE";
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when x"5BF" => DATA <= x"FB";
when x"5C0" => DATA <= x"AD";
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when x"5C2" => DATA <= x"FE";
when x"5C3" => DATA <= x"91";
when x"5C4" => DATA <= x"F4";
when x"5C5" => DATA <= x"2C";
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when x"5C7" => DATA <= x"FE";
when x"5C8" => DATA <= x"2C";
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when x"5CA" => DATA <= x"FE";
when x"5CB" => DATA <= x"2C";
when x"5CC" => DATA <= x"FE";
when x"5CD" => DATA <= x"FE";
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when x"5CF" => DATA <= x"FB";
when x"5D0" => DATA <= x"AD";
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when x"5D2" => DATA <= x"FE";
when x"5D3" => DATA <= x"68";
when x"5D4" => DATA <= x"C9";
when x"5D5" => DATA <= x"06";
when x"5D6" => DATA <= x"90";
when x"5D7" => DATA <= x"1C";
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when x"5D9" => DATA <= x"1F";
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when x"5DB" => DATA <= x"00";
when x"5DC" => DATA <= x"AD";
when x"5DD" => DATA <= x"FC";
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when x"5DF" => DATA <= x"29";
when x"5E0" => DATA <= x"80";
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when x"5E2" => DATA <= x"F9";
when x"5E3" => DATA <= x"B9";
when x"5E4" => DATA <= x"FF";
when x"5E5" => DATA <= x"FF";
when x"5E6" => DATA <= x"8D";
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when x"5E8" => DATA <= x"FE";
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when x"5EA" => DATA <= x"D0";
when x"5EB" => DATA <= x"F0";
when x"5EC" => DATA <= x"2C";
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when x"5EE" => DATA <= x"FE";
when x"5EF" => DATA <= x"10";
when x"5F0" => DATA <= x"FB";
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when x"5F2" => DATA <= x"FD";
when x"5F3" => DATA <= x"FE";
when x"5F4" => DATA <= x"68";
when x"5F5" => DATA <= x"A8";
when x"5F6" => DATA <= x"A5";
when x"5F7" => DATA <= x"FC";
when x"5F8" => DATA <= x"40";
when x"5F9" => DATA <= x"A0";
when x"5FA" => DATA <= x"00";
when x"5FB" => DATA <= x"AD";
when x"5FC" => DATA <= x"FC";
when x"5FD" => DATA <= x"FE";
when x"5FE" => DATA <= x"29";
when x"5FF" => DATA <= x"80";
when x"600" => DATA <= x"10";
when x"601" => DATA <= x"F9";
when x"602" => DATA <= x"AD";
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when x"604" => DATA <= x"FE";
when x"605" => DATA <= x"99";
when x"606" => DATA <= x"FF";
when x"607" => DATA <= x"FF";
when x"608" => DATA <= x"C8";
when x"609" => DATA <= x"D0";
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when x"60B" => DATA <= x"F0";
when x"60C" => DATA <= x"E7";
when x"60D" => DATA <= x"48";
when x"60E" => DATA <= x"AD";
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when x"610" => DATA <= x"FF";
when x"611" => DATA <= x"8D";
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when x"613" => DATA <= x"FE";
when x"614" => DATA <= x"EE";
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when x"616" => DATA <= x"FE";
when x"617" => DATA <= x"D0";
when x"618" => DATA <= x"03";
when x"619" => DATA <= x"EE";
when x"61A" => DATA <= x"10";
when x"61B" => DATA <= x"FE";
when x"61C" => DATA <= x"68";
when x"61D" => DATA <= x"40";
when x"61E" => DATA <= x"48";
when x"61F" => DATA <= x"AD";
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when x"621" => DATA <= x"FE";
when x"622" => DATA <= x"8D";
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when x"624" => DATA <= x"FF";
when x"625" => DATA <= x"EE";
when x"626" => DATA <= x"23";
when x"627" => DATA <= x"FE";
when x"628" => DATA <= x"D0";
when x"629" => DATA <= x"03";
when x"62A" => DATA <= x"EE";
when x"62B" => DATA <= x"24";
when x"62C" => DATA <= x"FE";
when x"62D" => DATA <= x"68";
when x"62E" => DATA <= x"40";
when x"62F" => DATA <= x"48";
when x"630" => DATA <= x"98";
when x"631" => DATA <= x"48";
when x"632" => DATA <= x"A0";
when x"633" => DATA <= x"00";
when x"634" => DATA <= x"B1";
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when x"636" => DATA <= x"8D";
when x"637" => DATA <= x"FD";
when x"638" => DATA <= x"FE";
when x"639" => DATA <= x"E6";
when x"63A" => DATA <= x"F6";
when x"63B" => DATA <= x"D0";
when x"63C" => DATA <= x"02";
when x"63D" => DATA <= x"E6";
when x"63E" => DATA <= x"F7";
when x"63F" => DATA <= x"B1";
when x"640" => DATA <= x"F6";
when x"641" => DATA <= x"8D";
when x"642" => DATA <= x"FD";
when x"643" => DATA <= x"FE";
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when x"645" => DATA <= x"F6";
when x"646" => DATA <= x"D0";
when x"647" => DATA <= x"02";
when x"648" => DATA <= x"E6";
when x"649" => DATA <= x"F7";
when x"64A" => DATA <= x"68";
when x"64B" => DATA <= x"A8";
when x"64C" => DATA <= x"68";
when x"64D" => DATA <= x"40";
when x"64E" => DATA <= x"48";
when x"64F" => DATA <= x"98";
when x"650" => DATA <= x"48";
when x"651" => DATA <= x"A0";
when x"652" => DATA <= x"00";
when x"653" => DATA <= x"AD";
when x"654" => DATA <= x"FD";
when x"655" => DATA <= x"FE";
when x"656" => DATA <= x"91";
when x"657" => DATA <= x"F6";
when x"658" => DATA <= x"E6";
when x"659" => DATA <= x"F6";
when x"65A" => DATA <= x"D0";
when x"65B" => DATA <= x"02";
when x"65C" => DATA <= x"E6";
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when x"65E" => DATA <= x"AD";
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when x"660" => DATA <= x"FE";
when x"661" => DATA <= x"91";
when x"662" => DATA <= x"F6";
when x"663" => DATA <= x"E6";
when x"664" => DATA <= x"F6";
when x"665" => DATA <= x"D0";
when x"666" => DATA <= x"02";
when x"667" => DATA <= x"E6";
when x"668" => DATA <= x"F7";
when x"669" => DATA <= x"68";
when x"66A" => DATA <= x"A8";
when x"66B" => DATA <= x"68";
when x"66C" => DATA <= x"40";
when x"66D" => DATA <= x"0F";
when x"66E" => DATA <= x"23";
when x"66F" => DATA <= x"F6";
when x"670" => DATA <= x"F6";
when x"671" => DATA <= x"F6";
when x"672" => DATA <= x"F6";
when x"673" => DATA <= x"E4";
when x"674" => DATA <= x"06";
when x"675" => DATA <= x"FE";
when x"676" => DATA <= x"FE";
when x"677" => DATA <= x"00";
when x"678" => DATA <= x"00";
when x"679" => DATA <= x"00";
when x"67A" => DATA <= x"00";
when x"67B" => DATA <= x"FD";
when x"67C" => DATA <= x"FE";
when x"67D" => DATA <= x"0D";
when x"67E" => DATA <= x"1E";
when x"67F" => DATA <= x"2F";
when x"680" => DATA <= x"4E";
when x"681" => DATA <= x"C0";
when x"682" => DATA <= x"C0";
when x"683" => DATA <= x"C0";
when x"684" => DATA <= x"C0";
when x"685" => DATA <= x"FE";
when x"686" => DATA <= x"FE";
when x"687" => DATA <= x"FE";
when x"688" => DATA <= x"FE";
when x"689" => DATA <= x"FE";
when x"68A" => DATA <= x"FE";
when x"68B" => DATA <= x"FE";
when x"68C" => DATA <= x"FE";
when x"68D" => DATA <= x"2C";
when x"68E" => DATA <= x"F8";
when x"68F" => DATA <= x"FE";
when x"690" => DATA <= x"30";
when x"691" => DATA <= x"0F";
when x"692" => DATA <= x"2C";
when x"693" => DATA <= x"FE";
when x"694" => DATA <= x"FE";
when x"695" => DATA <= x"10";
when x"696" => DATA <= x"F6";
when x"697" => DATA <= x"A5";
when x"698" => DATA <= x"FC";
when x"699" => DATA <= x"08";
when x"69A" => DATA <= x"58";
when x"69B" => DATA <= x"28";
when x"69C" => DATA <= x"85";
when x"69D" => DATA <= x"FC";
when x"69E" => DATA <= x"4C";
when x"69F" => DATA <= x"8D";
when x"6A0" => DATA <= x"FE";
when x"6A1" => DATA <= x"AD";
when x"6A2" => DATA <= x"F9";
when x"6A3" => DATA <= x"FE";
when x"6A4" => DATA <= x"60";
when x"6A5" => DATA <= x"68";
when x"6A6" => DATA <= x"85";
when x"6A7" => DATA <= x"FA";
when x"6A8" => DATA <= x"68";
when x"6A9" => DATA <= x"85";
when x"6AA" => DATA <= x"FB";
when x"6AB" => DATA <= x"A0";
when x"6AC" => DATA <= x"00";
when x"6AD" => DATA <= x"E6";
when x"6AE" => DATA <= x"FA";
when x"6AF" => DATA <= x"D0";
when x"6B0" => DATA <= x"02";
when x"6B1" => DATA <= x"E6";
when x"6B2" => DATA <= x"FB";
when x"6B3" => DATA <= x"B1";
when x"6B4" => DATA <= x"FA";
when x"6B5" => DATA <= x"30";
when x"6B6" => DATA <= x"06";
when x"6B7" => DATA <= x"20";
when x"6B8" => DATA <= x"EE";
when x"6B9" => DATA <= x"FF";
when x"6BA" => DATA <= x"4C";
when x"6BB" => DATA <= x"AD";
when x"6BC" => DATA <= x"FE";
when x"6BD" => DATA <= x"6C";
when x"6BE" => DATA <= x"FA";
when x"6BF" => DATA <= x"00";
when x"6C0" => DATA <= x"8D";
when x"6C1" => DATA <= x"FD";
when x"6C2" => DATA <= x"FE";
when x"6C3" => DATA <= x"40";
when x"6C4" => DATA <= x"FF";
when x"6C5" => DATA <= x"FF";
when x"6C6" => DATA <= x"FF";
when x"6C7" => DATA <= x"FF";
when x"6C8" => DATA <= x"FF";
when x"6C9" => DATA <= x"FF";
when x"6CA" => DATA <= x"FF";
when x"6CB" => DATA <= x"FF";
when x"6CC" => DATA <= x"FF";
when x"6CD" => DATA <= x"FF";
when x"6CE" => DATA <= x"FF";
when x"6CF" => DATA <= x"FF";
when x"6D0" => DATA <= x"FF";
when x"6D1" => DATA <= x"FF";
when x"6D2" => DATA <= x"FF";
when x"6D3" => DATA <= x"FF";
when x"6D4" => DATA <= x"FF";
when x"6D5" => DATA <= x"FF";
when x"6D6" => DATA <= x"FF";
when x"6D7" => DATA <= x"FF";
when x"6D8" => DATA <= x"FF";
when x"6D9" => DATA <= x"FF";
when x"6DA" => DATA <= x"FF";
when x"6DB" => DATA <= x"FF";
when x"6DC" => DATA <= x"FF";
when x"6DD" => DATA <= x"FF";
when x"6DE" => DATA <= x"FF";
when x"6DF" => DATA <= x"FF";
when x"6E0" => DATA <= x"FF";
when x"6E1" => DATA <= x"FF";
when x"6E2" => DATA <= x"FF";
when x"6E3" => DATA <= x"FF";
when x"6E4" => DATA <= x"FF";
when x"6E5" => DATA <= x"FF";
when x"6E6" => DATA <= x"FF";
when x"6E7" => DATA <= x"FF";
when x"6E8" => DATA <= x"FF";
when x"6E9" => DATA <= x"FF";
when x"6EA" => DATA <= x"FF";
when x"6EB" => DATA <= x"FF";
when x"6EC" => DATA <= x"FF";
when x"6ED" => DATA <= x"FF";
when x"6EE" => DATA <= x"FF";
when x"6EF" => DATA <= x"FF";
when x"6F0" => DATA <= x"00";
when x"6F1" => DATA <= x"00";
when x"6F2" => DATA <= x"00";
when x"6F3" => DATA <= x"00";
when x"6F4" => DATA <= x"00";
when x"6F5" => DATA <= x"00";
when x"6F6" => DATA <= x"00";
when x"6F7" => DATA <= x"00";
when x"6F8" => DATA <= x"00";
when x"6F9" => DATA <= x"00";
when x"6FA" => DATA <= x"00";
when x"6FB" => DATA <= x"00";
when x"6FC" => DATA <= x"00";
when x"6FD" => DATA <= x"00";
when x"6FE" => DATA <= x"00";
when x"6FF" => DATA <= x"00";
when x"700" => DATA <= x"FF";
when x"701" => DATA <= x"FF";
when x"702" => DATA <= x"FF";
when x"703" => DATA <= x"FF";
when x"704" => DATA <= x"FF";
when x"705" => DATA <= x"FF";
when x"706" => DATA <= x"FF";
when x"707" => DATA <= x"FF";
when x"708" => DATA <= x"FF";
when x"709" => DATA <= x"FF";
when x"70A" => DATA <= x"FF";
when x"70B" => DATA <= x"FF";
when x"70C" => DATA <= x"FF";
when x"70D" => DATA <= x"FF";
when x"70E" => DATA <= x"FF";
when x"70F" => DATA <= x"FF";
when x"710" => DATA <= x"FF";
when x"711" => DATA <= x"FF";
when x"712" => DATA <= x"FF";
when x"713" => DATA <= x"FF";
when x"714" => DATA <= x"FF";
when x"715" => DATA <= x"FF";
when x"716" => DATA <= x"FF";
when x"717" => DATA <= x"FF";
when x"718" => DATA <= x"FF";
when x"719" => DATA <= x"FF";
when x"71A" => DATA <= x"FF";
when x"71B" => DATA <= x"FF";
when x"71C" => DATA <= x"FF";
when x"71D" => DATA <= x"FF";
when x"71E" => DATA <= x"FF";
when x"71F" => DATA <= x"FF";
when x"720" => DATA <= x"FF";
when x"721" => DATA <= x"FF";
when x"722" => DATA <= x"FF";
when x"723" => DATA <= x"FF";
when x"724" => DATA <= x"FF";
when x"725" => DATA <= x"FF";
when x"726" => DATA <= x"FF";
when x"727" => DATA <= x"FF";
when x"728" => DATA <= x"FF";
when x"729" => DATA <= x"FF";
when x"72A" => DATA <= x"FF";
when x"72B" => DATA <= x"FF";
when x"72C" => DATA <= x"FF";
when x"72D" => DATA <= x"FF";
when x"72E" => DATA <= x"FF";
when x"72F" => DATA <= x"FF";
when x"730" => DATA <= x"FF";
when x"731" => DATA <= x"FF";
when x"732" => DATA <= x"FF";
when x"733" => DATA <= x"FF";
when x"734" => DATA <= x"FF";
when x"735" => DATA <= x"FF";
when x"736" => DATA <= x"FF";
when x"737" => DATA <= x"FF";
when x"738" => DATA <= x"FF";
when x"739" => DATA <= x"FF";
when x"73A" => DATA <= x"FF";
when x"73B" => DATA <= x"FF";
when x"73C" => DATA <= x"FF";
when x"73D" => DATA <= x"FF";
when x"73E" => DATA <= x"FF";
when x"73F" => DATA <= x"FF";
when x"740" => DATA <= x"FF";
when x"741" => DATA <= x"FF";
when x"742" => DATA <= x"FF";
when x"743" => DATA <= x"FF";
when x"744" => DATA <= x"FF";
when x"745" => DATA <= x"FF";
when x"746" => DATA <= x"FF";
when x"747" => DATA <= x"FF";
when x"748" => DATA <= x"FF";
when x"749" => DATA <= x"FF";
when x"74A" => DATA <= x"FF";
when x"74B" => DATA <= x"FF";
when x"74C" => DATA <= x"FF";
when x"74D" => DATA <= x"FF";
when x"74E" => DATA <= x"FF";
when x"74F" => DATA <= x"FF";
when x"750" => DATA <= x"FF";
when x"751" => DATA <= x"FF";
when x"752" => DATA <= x"FF";
when x"753" => DATA <= x"FF";
when x"754" => DATA <= x"FF";
when x"755" => DATA <= x"FF";
when x"756" => DATA <= x"FF";
when x"757" => DATA <= x"FF";
when x"758" => DATA <= x"FF";
when x"759" => DATA <= x"FF";
when x"75A" => DATA <= x"FF";
when x"75B" => DATA <= x"FF";
when x"75C" => DATA <= x"FF";
when x"75D" => DATA <= x"FF";
when x"75E" => DATA <= x"FF";
when x"75F" => DATA <= x"FF";
when x"760" => DATA <= x"FF";
when x"761" => DATA <= x"FF";
when x"762" => DATA <= x"FF";
when x"763" => DATA <= x"FF";
when x"764" => DATA <= x"FF";
when x"765" => DATA <= x"FF";
when x"766" => DATA <= x"FF";
when x"767" => DATA <= x"FF";
when x"768" => DATA <= x"FF";
when x"769" => DATA <= x"FF";
when x"76A" => DATA <= x"FF";
when x"76B" => DATA <= x"FF";
when x"76C" => DATA <= x"FF";
when x"76D" => DATA <= x"FF";
when x"76E" => DATA <= x"FF";
when x"76F" => DATA <= x"FF";
when x"770" => DATA <= x"FF";
when x"771" => DATA <= x"FF";
when x"772" => DATA <= x"FF";
when x"773" => DATA <= x"FF";
when x"774" => DATA <= x"FF";
when x"775" => DATA <= x"FF";
when x"776" => DATA <= x"FF";
when x"777" => DATA <= x"FF";
when x"778" => DATA <= x"FF";
when x"779" => DATA <= x"FF";
when x"77A" => DATA <= x"FF";
when x"77B" => DATA <= x"FF";
when x"77C" => DATA <= x"FF";
when x"77D" => DATA <= x"FF";
when x"77E" => DATA <= x"FF";
when x"77F" => DATA <= x"FF";
when x"780" => DATA <= x"C4";
when x"781" => DATA <= x"FC";
when x"782" => DATA <= x"50";
when x"783" => DATA <= x"F9";
when x"784" => DATA <= x"FD";
when x"785" => DATA <= x"FC";
when x"786" => DATA <= x"C4";
when x"787" => DATA <= x"FC";
when x"788" => DATA <= x"D5";
when x"789" => DATA <= x"F9";
when x"78A" => DATA <= x"80";
when x"78B" => DATA <= x"FA";
when x"78C" => DATA <= x"0C";
when x"78D" => DATA <= x"FB";
when x"78E" => DATA <= x"6D";
when x"78F" => DATA <= x"F9";
when x"790" => DATA <= x"77";
when x"791" => DATA <= x"F9";
when x"792" => DATA <= x"60";
when x"793" => DATA <= x"FC";
when x"794" => DATA <= x"D9";
when x"795" => DATA <= x"FB";
when x"796" => DATA <= x"37";
when x"797" => DATA <= x"FC";
when x"798" => DATA <= x"43";
when x"799" => DATA <= x"FC";
when x"79A" => DATA <= x"9B";
when x"79B" => DATA <= x"FC";
when x"79C" => DATA <= x"19";
when x"79D" => DATA <= x"FC";
when x"79E" => DATA <= x"C4";
when x"79F" => DATA <= x"FC";
when x"7A0" => DATA <= x"88";
when x"7A1" => DATA <= x"F9";
when x"7A2" => DATA <= x"C4";
when x"7A3" => DATA <= x"FC";
when x"7A4" => DATA <= x"C4";
when x"7A5" => DATA <= x"FC";
when x"7A6" => DATA <= x"C4";
when x"7A7" => DATA <= x"FC";
when x"7A8" => DATA <= x"C4";
when x"7A9" => DATA <= x"FC";
when x"7AA" => DATA <= x"C4";
when x"7AB" => DATA <= x"FC";
when x"7AC" => DATA <= x"C4";
when x"7AD" => DATA <= x"FC";
when x"7AE" => DATA <= x"C4";
when x"7AF" => DATA <= x"FC";
when x"7B0" => DATA <= x"88";
when x"7B1" => DATA <= x"F9";
when x"7B2" => DATA <= x"88";
when x"7B3" => DATA <= x"F9";
when x"7B4" => DATA <= x"88";
when x"7B5" => DATA <= x"F9";
when x"7B6" => DATA <= x"36";
when x"7B7" => DATA <= x"80";
when x"7B8" => DATA <= x"FF";
when x"7B9" => DATA <= x"4C";
when x"7BA" => DATA <= x"C4";
when x"7BB" => DATA <= x"FC";
when x"7BC" => DATA <= x"4C";
when x"7BD" => DATA <= x"C4";
when x"7BE" => DATA <= x"FC";
when x"7BF" => DATA <= x"4C";
when x"7C0" => DATA <= x"C4";
when x"7C1" => DATA <= x"FC";
when x"7C2" => DATA <= x"4C";
when x"7C3" => DATA <= x"C4";
when x"7C4" => DATA <= x"FC";
when x"7C5" => DATA <= x"4C";
when x"7C6" => DATA <= x"C4";
when x"7C7" => DATA <= x"FC";
when x"7C8" => DATA <= x"4C";
when x"7C9" => DATA <= x"77";
when x"7CA" => DATA <= x"F9";
when x"7CB" => DATA <= x"4C";
when x"7CC" => DATA <= x"6D";
when x"7CD" => DATA <= x"F9";
when x"7CE" => DATA <= x"6C";
when x"7CF" => DATA <= x"1C";
when x"7D0" => DATA <= x"02";
when x"7D1" => DATA <= x"6C";
when x"7D2" => DATA <= x"1A";
when x"7D3" => DATA <= x"02";
when x"7D4" => DATA <= x"6C";
when x"7D5" => DATA <= x"18";
when x"7D6" => DATA <= x"02";
when x"7D7" => DATA <= x"6C";
when x"7D8" => DATA <= x"16";
when x"7D9" => DATA <= x"02";
when x"7DA" => DATA <= x"6C";
when x"7DB" => DATA <= x"14";
when x"7DC" => DATA <= x"02";
when x"7DD" => DATA <= x"6C";
when x"7DE" => DATA <= x"12";
when x"7DF" => DATA <= x"02";
when x"7E0" => DATA <= x"6C";
when x"7E1" => DATA <= x"10";
when x"7E2" => DATA <= x"02";
when x"7E3" => DATA <= x"C9";
when x"7E4" => DATA <= x"0D";
when x"7E5" => DATA <= x"D0";
when x"7E6" => DATA <= x"07";
when x"7E7" => DATA <= x"A9";
when x"7E8" => DATA <= x"0A";
when x"7E9" => DATA <= x"20";
when x"7EA" => DATA <= x"EE";
when x"7EB" => DATA <= x"FF";
when x"7EC" => DATA <= x"A9";
when x"7ED" => DATA <= x"0D";
when x"7EE" => DATA <= x"6C";
when x"7EF" => DATA <= x"0E";
when x"7F0" => DATA <= x"02";
when x"7F1" => DATA <= x"6C";
when x"7F2" => DATA <= x"0C";
when x"7F3" => DATA <= x"02";
when x"7F4" => DATA <= x"6C";
when x"7F5" => DATA <= x"0A";
when x"7F6" => DATA <= x"02";
when x"7F7" => DATA <= x"6C";
when x"7F8" => DATA <= x"08";
when x"7F9" => DATA <= x"02";
when x"7FA" => DATA <= x"0D";
when x"7FB" => DATA <= x"FE";
when x"7FC" => DATA <= x"00";
when x"7FD" => DATA <= x"F8";
when x"7FE" => DATA <= x"F2";
when x"7FF" => DATA <= x"FC";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
|
architecture RTL of ENT is
begin
end ARCHITECTURE RTL;
architecture RTL of ENT is
begin
end rtl;
architecture RTL of ENT is
begin
end architecture Rtl;
architecture RTL of ENT is
begin
end;
architecture RTL of ENT is
begin
end Architecture;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: dpr_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY dpr_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE dpr_synth_ARCH OF dpr_synth IS
COMPONENT dpr_exdes
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ENA: STD_LOGIC := '0';
SIGNAL ENA_R: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ENB: STD_LOGIC := '0';
SIGNAL ENB_R: STD_LOGIC := '0';
SIGNAL WEB: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEB_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB: STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB: STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_R: STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_ENB_R : STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECK_DATA_TDP(0) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => CHECKER_ENB_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(1)
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(RSTB='1') THEN
CHECKER_ENB_R <= '0';
ELSE
CHECKER_ENB_R <= CHECK_DATA_TDP(1) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => CLKA,
CLKB => CLKB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
ENA => ENA,
WEA => WEA,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
ENB => ENB,
CHECK_DATA => CHECK_DATA_TDP
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ENA_R <= '0' AFTER 50 ns;
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ENB_R <= '0' AFTER 50 ns;
WEB_R <= (OTHERS=>'0') AFTER 50 ns;
DINB_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
ENA_R <= ENA AFTER 50 ns;
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
ENB_R <= ENB AFTER 50 ns;
WEB_R <= WEB AFTER 50 ns;
DINB_R <= DINB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: dpr_exdes PORT MAP (
--Port A
ENA => ENA_R,
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
ENB => ENB_R,
WEB => WEB_R,
ADDRB => ADDRB_R,
DINB => DINB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
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rog=
`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity poolV is
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE - 1 downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out std_logic_vector (PIXEL_SIZE - 1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end entity;
architecture rtl of poolV is
--------------------------------------------------------------------------
-- Signals
--------------------------------------------------------------------------
type buffer_data_type is array ( integer range <> ) of signed (PIXEL_SIZE-1 downto 0);
signal buffer_line : buffer_data_type (IMAGE_WIDTH - 1 downto 0);
signal buffer_data : buffer_data_type (KERNEL_SIZE - 1 downto 0);
signal max_value_signal : signed (PIXEL_SIZE - 1 downto 0);
signal buffer_fv : std_logic_vector(KERNEL_SIZE downto 0);
signal delay_fv : std_logic := '0';
signal tmp_dv : std_logic := '0';
begin
even_frameWidth : if (IMAGE_WIDTH mod 2 = 0) generate
process (clk)
variable x_cmp : unsigned (15 downto 0);
begin
if (reset_n = '0') then
tmp_dv <='0';
buffer_data <= (others=>(others=>'0'));
buffer_line <= (others=>(others=>'0'));
max_value_signal <= (others=>'0');
x_cmp := (others=>'0');
elsif (rising_edge(clk)) then
if (enable = '1') then
if (in_fv = '1') then
if (in_dv = '1') then
-- Bufferize line --------------------------------------------------------
buffer_line(IMAGE_WIDTH - 1) <= signed(in_data);
BUFFER_LOOP : for i in (IMAGE_WIDTH - 1) downto 1 loop
buffer_line(i-1) <= buffer_line(i);
end loop;
buffer_data(0) <= signed(in_data);
buffer_data(1) <= buffer_line(0);
-- Compute max : Case2 , just a comparator --------------------------------
if (buffer_data(0) > buffer_data(1)) then
max_value_signal <= buffer_data(0);
else
max_value_signal <= buffer_data(1);
end if;
-- V Subsample -------------------------------------------------------------
if (x_cmp < to_unsigned(IMAGE_WIDTH+1, 16)) then
tmp_dv <= '0';
x_cmp := x_cmp + to_unsigned(1,16);
elsif (x_cmp > to_unsigned(IMAGE_WIDTH + IMAGE_WIDTH,16)) then
tmp_dv <= '0';
x_cmp := to_unsigned(2,16);
else
tmp_dv <= '1';
x_cmp := x_cmp + to_unsigned(1,16);
end if;
--------------------------------------------------------------------------
else
-- Data is not valid
tmp_dv <= '0';
end if;
else
buffer_data <= (others=>(others=>'0'));
buffer_line <= (others=>(others=>'0'));
max_value_signal <= (others=>'0');
x_cmp := (others=>'0');
end if;
end if;
end if;
end process;
out_dv <= tmp_dv;
end generate;
----------------------------------------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------
odd_frameWidth : if (IMAGE_WIDTH mod 2 = 1) generate
process (clk)
variable x_cmp : unsigned (15 downto 0);
variable v_buff_data : buffer_data_type (KERNEL_SIZE - 1 downto 0);
begin
if (reset_n = '0') then
tmp_dv <='0';
v_buff_data := (others=>(others=>'0'));
buffer_line <= (others=>(others=>'0'));
max_value_signal <= (others=>'0');
x_cmp := (others=>'0');
elsif (rising_edge(clk)) then
if (enable = '1') then
if (in_fv = '1') then
if (in_dv = '1') then
-- Bufferize line --------------------------------------------------------
buffer_line(IMAGE_WIDTH - 1) <= signed(in_data);
BUFFER_LOOP : for i in (IMAGE_WIDTH - 1) downto 1 loop
buffer_line(i-1) <= buffer_line(i);
end loop;
v_buff_data(0) := signed(in_data);
v_buff_data(1) := buffer_line(0);
-- Compute max : Case2 , just a comparator --------------------------------
if (v_buff_data(0) > v_buff_data(1)) then
max_value_signal <= v_buff_data(0);
else
max_value_signal <= v_buff_data(1);
end if;
-- V Subsample -------------------------------------------------------------
if (x_cmp < to_unsigned(IMAGE_WIDTH, 16)) then
tmp_dv <= '0';
x_cmp := x_cmp + to_unsigned(1,16);
elsif (x_cmp = to_unsigned(IMAGE_WIDTH + IMAGE_WIDTH,16)) then
tmp_dv <= '0';
x_cmp := to_unsigned(1,16);
else
tmp_dv <= '1';
x_cmp := x_cmp + to_unsigned(1,16);
end if;
--------------------------------------------------------------------------
else
-- Data is not valid
tmp_dv <= '0';
end if;
else
v_buff_data := (others=>(others=>'0'));
buffer_line <= (others=>(others=>'0'));
max_value_signal <= (others=>'0');
x_cmp := (others=>'0');
end if;
end if;
end if;
out_dv <= tmp_dv;
end process;
--------------------------------------------------------------------------
end generate;
--------------------------------------------------------------------------
--------------------------------------------------------------------------
--------------------------------------------------------------------------
delay : process(clk)
begin
if (reset_n = '0') then
delay_fv <= '0';
buffer_fv <= (others=>'0');
elsif (rising_edge(clk)) then
if (enable = '1') then
buffer_fv <= buffer_fv(buffer_fv'HIGH -1 downto 0) & in_fv;
delay_fv <= buffer_fv(buffer_fv'HIGH);
end if;
end if;
end process;
out_data <= std_logic_vector(max_value_signal);
out_fv <= delay_fv;
end architecture;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net4,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net3,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net1,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net1,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:27:08 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_color_test_0_0 -prefix
-- system_vga_color_test_0_0_ system_vga_color_test_0_0_sim_netlist.vhdl
-- Design : system_vga_color_test_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_color_test_0_0_vga_color_test is
port (
rgb : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
clk_25 : in STD_LOGIC
);
end system_vga_color_test_0_0_vga_color_test;
architecture STRUCTURE of system_vga_color_test_0_0_vga_color_test is
signal \rgb[13]_i_1_n_0\ : STD_LOGIC;
signal \rgb[14]_i_1_n_0\ : STD_LOGIC;
signal \rgb[14]_i_2_n_0\ : STD_LOGIC;
signal \rgb[14]_i_3_n_0\ : STD_LOGIC;
signal \rgb[14]_i_4_n_0\ : STD_LOGIC;
signal \rgb[14]_i_5_n_0\ : STD_LOGIC;
signal \rgb[14]_i_6_n_0\ : STD_LOGIC;
signal \rgb[15]_i_1_n_0\ : STD_LOGIC;
signal \rgb[15]_i_2_n_0\ : STD_LOGIC;
signal \rgb[15]_i_3_n_0\ : STD_LOGIC;
signal \rgb[15]_i_4_n_0\ : STD_LOGIC;
signal \rgb[15]_i_5_n_0\ : STD_LOGIC;
signal \rgb[15]_i_6_n_0\ : STD_LOGIC;
signal \rgb[15]_i_7_n_0\ : STD_LOGIC;
signal \rgb[21]_i_1_n_0\ : STD_LOGIC;
signal \rgb[22]_i_10_n_0\ : STD_LOGIC;
signal \rgb[22]_i_11_n_0\ : STD_LOGIC;
signal \rgb[22]_i_1_n_0\ : STD_LOGIC;
signal \rgb[22]_i_2_n_0\ : STD_LOGIC;
signal \rgb[22]_i_3_n_0\ : STD_LOGIC;
signal \rgb[22]_i_4_n_0\ : STD_LOGIC;
signal \rgb[22]_i_5_n_0\ : STD_LOGIC;
signal \rgb[22]_i_6_n_0\ : STD_LOGIC;
signal \rgb[22]_i_7_n_0\ : STD_LOGIC;
signal \rgb[22]_i_8_n_0\ : STD_LOGIC;
signal \rgb[22]_i_9_n_0\ : STD_LOGIC;
signal \rgb[23]_i_10_n_0\ : STD_LOGIC;
signal \rgb[23]_i_11_n_0\ : STD_LOGIC;
signal \rgb[23]_i_12_n_0\ : STD_LOGIC;
signal \rgb[23]_i_13_n_0\ : STD_LOGIC;
signal \rgb[23]_i_14_n_0\ : STD_LOGIC;
signal \rgb[23]_i_15_n_0\ : STD_LOGIC;
signal \rgb[23]_i_16_n_0\ : STD_LOGIC;
signal \rgb[23]_i_17_n_0\ : STD_LOGIC;
signal \rgb[23]_i_18_n_0\ : STD_LOGIC;
signal \rgb[23]_i_1_n_0\ : STD_LOGIC;
signal \rgb[23]_i_2_n_0\ : STD_LOGIC;
signal \rgb[23]_i_3_n_0\ : STD_LOGIC;
signal \rgb[23]_i_4_n_0\ : STD_LOGIC;
signal \rgb[23]_i_5_n_0\ : STD_LOGIC;
signal \rgb[23]_i_6_n_0\ : STD_LOGIC;
signal \rgb[23]_i_7_n_0\ : STD_LOGIC;
signal \rgb[23]_i_8_n_0\ : STD_LOGIC;
signal \rgb[23]_i_9_n_0\ : STD_LOGIC;
signal \rgb[4]_i_1_n_0\ : STD_LOGIC;
signal \rgb[4]_i_2_n_0\ : STD_LOGIC;
signal \rgb[5]_i_1_n_0\ : STD_LOGIC;
signal \rgb[5]_i_2_n_0\ : STD_LOGIC;
signal \rgb[6]_i_1_n_0\ : STD_LOGIC;
signal \rgb[6]_i_2_n_0\ : STD_LOGIC;
signal \rgb[6]_i_3_n_0\ : STD_LOGIC;
signal \rgb[6]_i_4_n_0\ : STD_LOGIC;
signal \rgb[6]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_1_n_0\ : STD_LOGIC;
signal \rgb[7]_i_2_n_0\ : STD_LOGIC;
signal \rgb[7]_i_3_n_0\ : STD_LOGIC;
signal \rgb[7]_i_4_n_0\ : STD_LOGIC;
signal \rgb[7]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_6_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rgb[14]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[14]_i_5\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[15]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[15]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[15]_i_5\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb[15]_i_6\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb[15]_i_7\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[22]_i_10\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb[22]_i_11\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb[23]_i_10\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[23]_i_11\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[23]_i_14\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb[23]_i_15\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[23]_i_17\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb[23]_i_18\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb[23]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[5]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[6]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rgb[6]_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[6]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[7]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb[7]_i_4\ : label is "soft_lutpair5";
begin
\rgb[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5555FF02"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => \rgb[14]_i_2_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[22]_i_2_n_0\,
I4 => \rgb[23]_i_6_n_0\,
O => \rgb[13]_i_1_n_0\
);
\rgb[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFF02"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => \rgb[14]_i_2_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[22]_i_3_n_0\,
I4 => \rgb[22]_i_2_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[14]_i_1_n_0\
);
\rgb[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"02F20202"
)
port map (
I0 => \rgb[14]_i_4_n_0\,
I1 => \rgb[23]_i_11_n_0\,
I2 => xaddr(9),
I3 => \rgb[14]_i_5_n_0\,
I4 => \rgb[23]_i_10_n_0\,
O => \rgb[14]_i_2_n_0\
);
\rgb[14]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb[14]_i_6_n_0\,
I1 => yaddr(6),
O => \rgb[14]_i_3_n_0\
);
\rgb[14]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFEFEFEFEEE"
)
port map (
I0 => xaddr(4),
I1 => xaddr(5),
I2 => xaddr(3),
I3 => xaddr(0),
I4 => xaddr(1),
I5 => xaddr(2),
O => \rgb[14]_i_4_n_0\
);
\rgb[14]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFF8"
)
port map (
I0 => xaddr(2),
I1 => xaddr(5),
I2 => xaddr(7),
I3 => xaddr(6),
I4 => xaddr(8),
O => \rgb[14]_i_5_n_0\
);
\rgb[14]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888A888A8888888"
)
port map (
I0 => yaddr(5),
I1 => yaddr(4),
I2 => yaddr(2),
I3 => yaddr(3),
I4 => yaddr(1),
I5 => yaddr(0),
O => \rgb[14]_i_6_n_0\
);
\rgb[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF55455545"
)
port map (
I0 => \rgb[23]_i_4_n_0\,
I1 => \rgb[22]_i_2_n_0\,
I2 => \rgb[15]_i_2_n_0\,
I3 => \rgb[15]_i_3_n_0\,
I4 => \rgb[15]_i_4_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[15]_i_1_n_0\
);
\rgb[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \rgb[22]_i_8_n_0\,
I1 => \rgb[23]_i_12_n_0\,
O => \rgb[15]_i_2_n_0\
);
\rgb[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA88888"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => xaddr(9),
I2 => xaddr(6),
I3 => xaddr(7),
I4 => xaddr(8),
O => \rgb[15]_i_3_n_0\
);
\rgb[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"ECEEEEEEECECECEC"
)
port map (
I0 => xaddr(8),
I1 => xaddr(9),
I2 => xaddr(7),
I3 => \rgb[15]_i_5_n_0\,
I4 => \rgb[15]_i_6_n_0\,
I5 => \rgb[15]_i_7_n_0\,
O => \rgb[15]_i_4_n_0\
);
\rgb[15]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xaddr(0),
I1 => xaddr(1),
I2 => xaddr(2),
O => \rgb[15]_i_5_n_0\
);
\rgb[15]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => xaddr(5),
I1 => xaddr(4),
O => \rgb[15]_i_6_n_0\
);
\rgb[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => xaddr(6),
I1 => xaddr(5),
I2 => xaddr(4),
I3 => xaddr(3),
O => \rgb[15]_i_7_n_0\
);
\rgb[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFBF0FB"
)
port map (
I0 => \rgb[22]_i_2_n_0\,
I1 => \rgb[22]_i_4_n_0\,
I2 => \rgb[23]_i_2_n_0\,
I3 => \rgb[23]_i_6_n_0\,
I4 => \rgb[23]_i_7_n_0\,
O => \rgb[21]_i_1_n_0\
);
\rgb[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFFF00FFEF"
)
port map (
I0 => \rgb[22]_i_2_n_0\,
I1 => \rgb[22]_i_3_n_0\,
I2 => \rgb[22]_i_4_n_0\,
I3 => \rgb[23]_i_2_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_7_n_0\,
O => \rgb[22]_i_1_n_0\
);
\rgb[22]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => xaddr(9),
I1 => xaddr(6),
I2 => xaddr(7),
O => \rgb[22]_i_10_n_0\
);
\rgb[22]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"0070"
)
port map (
I0 => xaddr(3),
I1 => xaddr(4),
I2 => xaddr(8),
I3 => xaddr(5),
O => \rgb[22]_i_11_n_0\
);
\rgb[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAABABAB"
)
port map (
I0 => \rgb[22]_i_5_n_0\,
I1 => xaddr(8),
I2 => xaddr(9),
I3 => xaddr(6),
I4 => xaddr(7),
I5 => \rgb[22]_i_6_n_0\,
O => \rgb[22]_i_2_n_0\
);
\rgb[22]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000FD0000"
)
port map (
I0 => \rgb[23]_i_15_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[22]_i_7_n_0\,
I4 => xaddr(9),
I5 => \rgb[22]_i_6_n_0\,
O => \rgb[22]_i_3_n_0\
);
\rgb[22]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFAE"
)
port map (
I0 => \rgb[23]_i_7_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[23]_i_8_n_0\,
I3 => \rgb[14]_i_3_n_0\,
O => \rgb[22]_i_4_n_0\
);
\rgb[22]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200030003"
)
port map (
I0 => \rgb[15]_i_5_n_0\,
I1 => xaddr(9),
I2 => xaddr(8),
I3 => xaddr(5),
I4 => xaddr(3),
I5 => xaddr(4),
O => \rgb[22]_i_5_n_0\
);
\rgb[22]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"111111111111111F"
)
port map (
I0 => \rgb[14]_i_6_n_0\,
I1 => yaddr(6),
I2 => \rgb[22]_i_9_n_0\,
I3 => xaddr(7),
I4 => xaddr(8),
I5 => xaddr(9),
O => \rgb[22]_i_6_n_0\
);
\rgb[22]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFEFEFFFFFFFF"
)
port map (
I0 => xaddr(8),
I1 => xaddr(6),
I2 => xaddr(7),
I3 => xaddr(5),
I4 => xaddr(2),
I5 => \rgb[23]_i_10_n_0\,
O => \rgb[22]_i_7_n_0\
);
\rgb[22]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"5515551555151515"
)
port map (
I0 => \rgb[23]_i_14_n_0\,
I1 => \rgb[22]_i_10_n_0\,
I2 => \rgb[22]_i_11_n_0\,
I3 => xaddr(4),
I4 => xaddr(1),
I5 => xaddr(2),
O => \rgb[22]_i_8_n_0\
);
\rgb[22]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCC000088800000"
)
port map (
I0 => xaddr(3),
I1 => xaddr(6),
I2 => xaddr(2),
I3 => xaddr(1),
I4 => xaddr(5),
I5 => xaddr(4),
O => \rgb[22]_i_9_n_0\
);
\rgb[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAAEAAAEAAAE"
)
port map (
I0 => \rgb[23]_i_2_n_0\,
I1 => \rgb[23]_i_3_n_0\,
I2 => \rgb[23]_i_4_n_0\,
I3 => \rgb[23]_i_5_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_7_n_0\,
O => \rgb[23]_i_1_n_0\
);
\rgb[23]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xaddr(3),
I1 => xaddr(4),
I2 => xaddr(5),
O => \rgb[23]_i_10_n_0\
);
\rgb[23]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => xaddr(8),
I1 => xaddr(6),
I2 => xaddr(7),
O => \rgb[23]_i_11_n_0\
);
\rgb[23]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => yaddr(6),
I1 => \rgb[14]_i_6_n_0\,
O => \rgb[23]_i_12_n_0\
);
\rgb[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0515555515155555"
)
port map (
I0 => \rgb[23]_i_18_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[23]_i_17_n_0\,
I4 => xaddr(6),
I5 => xaddr(3),
O => \rgb[23]_i_13_n_0\
);
\rgb[23]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => xaddr(9),
I1 => xaddr(8),
O => \rgb[23]_i_14_n_0\
);
\rgb[23]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => xaddr(3),
I1 => xaddr(1),
I2 => xaddr(2),
O => \rgb[23]_i_15_n_0\
);
\rgb[23]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => xaddr(7),
I1 => xaddr(6),
O => \rgb[23]_i_16_n_0\
);
\rgb[23]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => xaddr(2),
I1 => xaddr(1),
O => \rgb[23]_i_17_n_0\
);
\rgb[23]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => xaddr(7),
I1 => xaddr(8),
I2 => xaddr(9),
O => \rgb[23]_i_18_n_0\
);
\rgb[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000022222"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => yaddr(6),
I2 => yaddr(4),
I3 => yaddr(3),
I4 => yaddr(5),
I5 => \rgb[23]_i_8_n_0\,
O => \rgb[23]_i_2_n_0\
);
\rgb[23]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAFFFB"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => \rgb[15]_i_4_n_0\,
I2 => \rgb[23]_i_9_n_0\,
I3 => xaddr(9),
I4 => \rgb[23]_i_7_n_0\,
O => \rgb[23]_i_3_n_0\
);
\rgb[23]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004440"
)
port map (
I0 => xaddr(9),
I1 => \rgb[23]_i_9_n_0\,
I2 => \rgb[23]_i_10_n_0\,
I3 => \rgb[23]_i_11_n_0\,
I4 => \rgb[23]_i_12_n_0\,
O => \rgb[23]_i_4_n_0\
);
\rgb[23]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0057FFFF00570057"
)
port map (
I0 => yaddr(5),
I1 => yaddr(3),
I2 => yaddr(4),
I3 => yaddr(6),
I4 => \rgb[23]_i_12_n_0\,
I5 => \rgb[23]_i_13_n_0\,
O => \rgb[23]_i_5_n_0\
);
\rgb[23]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"0155"
)
port map (
I0 => yaddr(6),
I1 => yaddr(4),
I2 => yaddr(3),
I3 => yaddr(5),
O => \rgb[23]_i_6_n_0\
);
\rgb[23]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"40CC44CC44CC44CC"
)
port map (
I0 => xaddr(6),
I1 => \rgb[23]_i_14_n_0\,
I2 => \rgb[23]_i_15_n_0\,
I3 => xaddr(7),
I4 => xaddr(4),
I5 => xaddr(5),
O => \rgb[23]_i_7_n_0\
);
\rgb[23]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFD500000000"
)
port map (
I0 => \rgb[23]_i_10_n_0\,
I1 => xaddr(2),
I2 => xaddr(5),
I3 => \rgb[23]_i_16_n_0\,
I4 => xaddr(8),
I5 => xaddr(9),
O => \rgb[23]_i_8_n_0\
);
\rgb[23]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFFFE0"
)
port map (
I0 => \rgb[23]_i_17_n_0\,
I1 => xaddr(0),
I2 => xaddr(3),
I3 => xaddr(5),
I4 => xaddr(4),
I5 => \rgb[23]_i_11_n_0\,
O => \rgb[23]_i_9_n_0\
);
\rgb[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"04770404"
)
port map (
I0 => \rgb[6]_i_2_n_0\,
I1 => \rgb[23]_i_6_n_0\,
I2 => \rgb[23]_i_7_n_0\,
I3 => \rgb[4]_i_2_n_0\,
I4 => \rgb[5]_i_2_n_0\,
O => \rgb[4]_i_1_n_0\
);
\rgb[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF2F2FFFFF202F"
)
port map (
I0 => \rgb[22]_i_8_n_0\,
I1 => \rgb[15]_i_4_n_0\,
I2 => \rgb[23]_i_12_n_0\,
I3 => \rgb[6]_i_5_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_13_n_0\,
O => \rgb[4]_i_2_n_0\
);
\rgb[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAFEAAAAAAAA"
)
port map (
I0 => \rgb[7]_i_4_n_0\,
I1 => \rgb[15]_i_2_n_0\,
I2 => \rgb[15]_i_4_n_0\,
I3 => \rgb[15]_i_3_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[5]_i_2_n_0\,
O => \rgb[5]_i_1_n_0\
);
\rgb[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F7F0F7F"
)
port map (
I0 => \rgb[14]_i_2_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[23]_i_12_n_0\,
I3 => \rgb[23]_i_7_n_0\,
I4 => \rgb[7]_i_3_n_0\,
O => \rgb[5]_i_2_n_0\
);
\rgb[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000FFFFF0045"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => \rgb[7]_i_3_n_0\,
I2 => \rgb[23]_i_7_n_0\,
I3 => \rgb[6]_i_2_n_0\,
I4 => \rgb[6]_i_3_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[6]_i_1_n_0\
);
\rgb[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \rgb[14]_i_2_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[7]_i_6_n_0\,
O => \rgb[6]_i_2_n_0\
);
\rgb[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF0002"
)
port map (
I0 => xaddr(9),
I1 => \rgb[22]_i_7_n_0\,
I2 => \rgb[6]_i_4_n_0\,
I3 => \rgb[22]_i_6_n_0\,
I4 => \rgb[6]_i_5_n_0\,
O => \rgb[6]_i_3_n_0\
);
\rgb[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000007"
)
port map (
I0 => xaddr(2),
I1 => xaddr(1),
I2 => xaddr(3),
I3 => xaddr(4),
I4 => xaddr(5),
O => \rgb[6]_i_4_n_0\
);
\rgb[6]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0057"
)
port map (
I0 => xaddr(8),
I1 => xaddr(7),
I2 => xaddr(6),
I3 => xaddr(9),
O => \rgb[6]_i_5_n_0\
);
\rgb[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222A"
)
port map (
I0 => \rgb[7]_i_3_n_0\,
I1 => yaddr(5),
I2 => yaddr(3),
I3 => yaddr(4),
I4 => yaddr(6),
O => \rgb[7]_i_1_n_0\
);
\rgb[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000000FB"
)
port map (
I0 => \rgb[7]_i_3_n_0\,
I1 => \rgb[23]_i_7_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[23]_i_4_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[7]_i_4_n_0\,
O => \rgb[7]_i_2_n_0\
);
\rgb[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000000D"
)
port map (
I0 => xaddr(6),
I1 => \rgb[7]_i_5_n_0\,
I2 => xaddr(9),
I3 => xaddr(8),
I4 => xaddr(7),
O => \rgb[7]_i_3_n_0\
);
\rgb[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000444"
)
port map (
I0 => \rgb[23]_i_7_n_0\,
I1 => \rgb[23]_i_6_n_0\,
I2 => \rgb[7]_i_6_n_0\,
I3 => \rgb[22]_i_8_n_0\,
I4 => \rgb[14]_i_2_n_0\,
O => \rgb[7]_i_4_n_0\
);
\rgb[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"1515155515155555"
)
port map (
I0 => xaddr(5),
I1 => xaddr(3),
I2 => xaddr(4),
I3 => xaddr(0),
I4 => xaddr(2),
I5 => xaddr(1),
O => \rgb[7]_i_5_n_0\
);
\rgb[7]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000007F55"
)
port map (
I0 => \rgb[15]_i_7_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[15]_i_5_n_0\,
I4 => xaddr(7),
I5 => xaddr(9),
O => \rgb[7]_i_6_n_0\
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[13]_i_1_n_0\,
Q => rgb(4),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[14]_i_1_n_0\,
Q => rgb(5),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[15]_i_1_n_0\,
Q => rgb(6),
R => '0'
);
\rgb_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[21]_i_1_n_0\,
Q => rgb(7),
R => '0'
);
\rgb_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[22]_i_1_n_0\,
Q => rgb(8),
R => '0'
);
\rgb_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[23]_i_1_n_0\,
Q => rgb(9),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[4]_i_1_n_0\,
Q => rgb(0),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[5]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[5]_i_1_n_0\,
Q => rgb(1),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[6]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[6]_i_1_n_0\,
Q => rgb(2),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[7]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[7]_i_2_n_0\,
Q => rgb(3),
S => \rgb[7]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_color_test_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_color_test_0_0 : entity is "system_vga_color_test_0_0,vga_color_test,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_color_test_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_color_test_0_0 : entity is "vga_color_test,Vivado 2016.4";
end system_vga_color_test_0_0;
architecture STRUCTURE of system_vga_color_test_0_0 is
signal \^rgb\ : STD_LOGIC_VECTOR ( 23 downto 3 );
begin
rgb(23 downto 22) <= \^rgb\(23 downto 22);
rgb(21) <= \^rgb\(20);
rgb(20) <= \^rgb\(20);
rgb(19) <= \^rgb\(20);
rgb(18) <= \^rgb\(20);
rgb(17) <= \^rgb\(20);
rgb(16) <= \^rgb\(20);
rgb(15 downto 14) <= \^rgb\(15 downto 14);
rgb(13) <= \^rgb\(12);
rgb(12) <= \^rgb\(12);
rgb(11) <= \^rgb\(12);
rgb(10) <= \^rgb\(12);
rgb(9) <= \^rgb\(12);
rgb(8) <= \^rgb\(12);
rgb(7 downto 5) <= \^rgb\(7 downto 5);
rgb(4) <= \^rgb\(3);
rgb(3) <= \^rgb\(3);
rgb(2) <= \^rgb\(3);
rgb(1) <= \^rgb\(3);
rgb(0) <= \^rgb\(3);
U0: entity work.system_vga_color_test_0_0_vga_color_test
port map (
clk_25 => clk_25,
rgb(9 downto 8) => \^rgb\(23 downto 22),
rgb(7) => \^rgb\(20),
rgb(6 downto 5) => \^rgb\(15 downto 14),
rgb(4) => \^rgb\(12),
rgb(3 downto 1) => \^rgb\(7 downto 5),
rgb(0) => \^rgb\(3),
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(6 downto 0) => yaddr(9 downto 3)
);
end STRUCTURE;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.NUMERIC_STD.all;
LIBRARY unisim;
USE unisim.vcomponents.all;
ENTITY adc_data_channel IS
PORT(
LVDS_ADC_D0_N : IN std_logic;
LVDS_ADC_D0_P : IN std_logic;
LVDS_ADC_D1_N : IN std_logic;
LVDS_ADC_D1_P : IN std_logic;
adc_clk : IN std_logic;
adc_clk_div : IN std_logic;
bitslip : IN std_logic;
reset : IN std_logic;
adc_data : OUT std_logic_vector (15 DOWNTO 0)
);
END ENTITY adc_data_channel ;
ARCHITECTURE struct OF adc_data_channel IS
-- Internal signal declarations
SIGNAL D0_delay_const_0 : std_logic_vector(4 DOWNTO 0);
SIGNAL adc_clk_n : std_logic;
SIGNAL adc_d0 : std_logic;
SIGNAL adc_d0_dly : std_logic;
SIGNAL adc_d1 : std_logic;
SIGNAL adc_d1_dly : std_logic;
SIGNAL d0_n_serdes_low : std_logic;
SIGNAL d0_p_serdes_low : std_logic;
SIGNAL d0_par : std_logic_vector(7 DOWNTO 0);
SIGNAL d1_par : std_logic_vector(7 DOWNTO 0);
COMPONENT ISERDESE2
GENERIC (
DATA_RATE : string;
DATA_WIDTH : integer;
DYN_CLKDIV_INV_EN : string;
DYN_CLK_INV_EN : string;
INIT_Q1 : bit;
INIT_Q2 : bit;
INIT_Q3 : bit;
INIT_Q4 : bit;
INTERFACE_TYPE : string;
IOBDELAY : string;
NUM_CE : integer;
OFB_USED : string;
SERDES_MODE : string;
SRVAL_Q1 : bit;
SRVAL_Q2 : bit;
SRVAL_Q3 : bit;
SRVAL_Q4 : bit
);
PORT (
BITSLIP : IN std_ulogic;
CE1 : IN std_ulogic;
CE2 : IN std_ulogic;
CLK : IN std_ulogic;
CLKB : IN std_ulogic;
CLKDIV : IN std_ulogic;
CLKDIVP : IN std_ulogic;
D : IN std_ulogic;
DDLY : IN std_ulogic;
DYNCLKDIVSEL : IN std_ulogic;
DYNCLKSEL : IN std_ulogic;
OCLK : IN std_ulogic;
OCLKB : IN std_ulogic;
OFB : IN std_ulogic;
RST : IN std_ulogic;
SHIFTIN1 : IN std_ulogic;
SHIFTIN2 : IN std_ulogic;
O : OUT std_ulogic;
Q1 : OUT std_ulogic;
Q2 : OUT std_ulogic;
Q3 : OUT std_ulogic;
Q4 : OUT std_ulogic;
Q5 : OUT std_ulogic;
Q6 : OUT std_ulogic;
Q7 : OUT std_ulogic;
Q8 : OUT std_ulogic;
SHIFTOUT1 : OUT std_ulogic;
SHIFTOUT2 : OUT std_ulogic
);
END COMPONENT ISERDESE2;
COMPONENT IBUFDS_LVDS_25
PORT (
I : IN std_ulogic;
IB : IN std_ulogic;
O : OUT std_ulogic
);
END COMPONENT IBUFDS_LVDS_25;
COMPONENT IDELAYE2
GENERIC (
CINVCTRL_SEL : string := "FALSE";
DELAY_SRC : string := "IDATAIN";
HIGH_PERFORMANCE_MODE : string := "FALSE";
IDELAY_TYPE : string := "FIXED";
IDELAY_VALUE : integer := 0;
PIPE_SEL : string := "FALSE";
REFCLK_FREQUENCY : real := 200.0;
SIGNAL_PATTERN : string := "DATA"
);
PORT (
C : IN std_ulogic;
CE : IN std_ulogic;
CINVCTRL : IN std_ulogic;
CNTVALUEIN : IN std_logic_vector (4 DOWNTO 0);
DATAIN : IN std_ulogic;
IDATAIN : IN std_ulogic;
INC : IN std_ulogic;
LD : IN std_ulogic;
LDPIPEEN : IN std_ulogic;
REGRST : IN std_ulogic;
CNTVALUEOUT : OUT std_logic_vector (4 DOWNTO 0);
DATAOUT : OUT std_ulogic
);
END COMPONENT IDELAYE2;
BEGIN
adc_data <= d1_par & d0_par;
d0_n_serdes_low <= '0';
d0_p_serdes_low <= '0';
D0_delay_const_0 <= (OTHERS => '0');
D0_delay_const_0 <= (OTHERS => '0');
adc_clk_n <= NOT(adc_clk);
ISERDESE2_d0 : ISERDESE2
GENERIC MAP (
DATA_RATE => "DDR",
DATA_WIDTH => 8,
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "NETWORKING",
IOBDELAY => "BOTH",
NUM_CE => 2,
OFB_USED => "FALSE",
SERDES_MODE => "MASTER",
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0'
)
PORT MAP (
O => OPEN,
Q1 => d0_par(0),
Q2 => d0_par(1),
Q3 => d0_par(2),
Q4 => d0_par(3),
Q5 => d0_par(4),
Q6 => d0_par(5),
Q7 => d0_par(6),
Q8 => d0_par(7),
SHIFTOUT1 => OPEN,
SHIFTOUT2 => OPEN,
BITSLIP => bitslip,
CE1 => '1',
CE2 => '1',
CLK => adc_clk,
CLKB => adc_clk_n,
CLKDIV => adc_clk_div,
CLKDIVP => d0_p_serdes_low,
D => adc_d0,
DDLY => adc_d0_dly,
DYNCLKDIVSEL => d0_p_serdes_low,
DYNCLKSEL => d0_p_serdes_low,
OCLK => d0_p_serdes_low,
OCLKB => d0_p_serdes_low,
OFB => d0_p_serdes_low,
RST => not reset,
SHIFTIN1 => d0_p_serdes_low,
SHIFTIN2 => d0_p_serdes_low
);
ISERDESE2_d1 : ISERDESE2
GENERIC MAP (
DATA_RATE => "DDR",
DATA_WIDTH => 8,
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "NETWORKING",
IOBDELAY => "BOTH",
NUM_CE => 2,
OFB_USED => "FALSE",
SERDES_MODE => "MASTER",
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0'
)
PORT MAP (
O => OPEN,
Q1 => d1_par(0),
Q2 => d1_par(1),
Q3 => d1_par(2),
Q4 => d1_par(3),
Q5 => d1_par(4),
Q6 => d1_par(5),
Q7 => d1_par(6),
Q8 => d1_par(7),
SHIFTOUT1 => OPEN,
SHIFTOUT2 => OPEN,
BITSLIP => bitslip,
CE1 => '1',
CE2 => '1',
CLK => adc_clk,
CLKB => adc_clk_n,
CLKDIV => adc_clk_div,
CLKDIVP => d0_n_serdes_low,
D => adc_d1,
DDLY => adc_d1_dly,
DYNCLKDIVSEL => d0_n_serdes_low,
DYNCLKSEL => d0_n_serdes_low,
OCLK => d0_n_serdes_low,
OCLKB => d0_n_serdes_low,
OFB => d0_n_serdes_low,
RST => not reset,
SHIFTIN1 => d0_n_serdes_low,
SHIFTIN2 => d0_n_serdes_low
);
D0_buf : IBUFDS_LVDS_25
PORT MAP (
O => adc_d0,
I => LVDS_ADC_D0_P,
IB => LVDS_ADC_D0_N
);
D1_buf : IBUFDS_LVDS_25
PORT MAP (
O => adc_d1,
I => LVDS_ADC_D1_P,
IB => LVDS_ADC_D1_N
);
D0_delay : IDELAYE2
GENERIC MAP (
CINVCTRL_SEL => "FALSE",
DELAY_SRC => "IDATAIN",
HIGH_PERFORMANCE_MODE => "FALSE",
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
PIPE_SEL => "FALSE",
REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "CLOCK"
)
PORT MAP (
CNTVALUEOUT => OPEN,
DATAOUT => adc_d0_dly,
C => adc_clk_div,
CE => D0_delay_const_0(0),
CINVCTRL => D0_delay_const_0(0),
CNTVALUEIN => D0_delay_const_0,
DATAIN => D0_delay_const_0(0),
IDATAIN => adc_d0,
INC => D0_delay_const_0(0),
LD => D0_delay_const_0(0),
LDPIPEEN => D0_delay_const_0(0),
REGRST => D0_delay_const_0(0)
);
D1_delay : IDELAYE2
GENERIC MAP (
CINVCTRL_SEL => "FALSE",
DELAY_SRC => "IDATAIN",
HIGH_PERFORMANCE_MODE => "FALSE",
IDELAY_TYPE => "VARIABLE",
IDELAY_VALUE => 0,
PIPE_SEL => "FALSE",
REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "CLOCK"
)
PORT MAP (
CNTVALUEOUT => OPEN,
DATAOUT => adc_d1_dly,
C => adc_clk_div,
CE => D0_delay_const_0(0),
CINVCTRL => D0_delay_const_0(0),
CNTVALUEIN => D0_delay_const_0,
DATAIN => D0_delay_const_0(0),
IDATAIN => adc_d1,
INC => D0_delay_const_0(0),
LD => D0_delay_const_0(0),
LDPIPEEN => D0_delay_const_0(0),
REGRST => D0_delay_const_0(0)
);
END ARCHITECTURE struct;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.types_pkg.all;
package io_pkg is
procedure write (l: inout line;
value: in std_ulogic_vector;
justified: in side := right;
field: in width := 0);
procedure write (l: inout line;
value: in std_ulogic;
justified: in side := right;
field: in width := 0);
procedure write (l: inout line;
value: in std_logic_vector;
justified: in side := right;
field: in width := 0);
procedure hread(l:inout line; value:out bit_vector);
procedure hread(l:inout line; value:out std_ulogic_vector);
procedure hread(l:inout line; value:out std_logic_vector);
procedure hwrite(l:inout line; value:in bit_vector; justified:in side := right; field:in width := 0);
procedure hwrite(l:inout line; value:in std_ulogic_vector; justified:in side := right; field:in width := 0);
procedure hwrite(l:inout line; value:in std_logic_vector; justified:in side := right; field:in width := 0);
end package;
package body io_pkg is
procedure write (l: inout line;
value: in std_ulogic;
justified: in side := right;
field: in width := 0) is
variable str : string(1 to 1);
begin
str(1) := std_ulogic_to_character(value);
write (l, str, justified, field);
end procedure;
procedure write (l: inout line;
value: in std_ulogic_vector;
justified: in side := right;
field: in width := 0) is
constant length : natural := value'length;
alias n_value : std_ulogic_vector (1 to value'length) is value;
variable str : string (1 to length);
begin
for i in str'range loop
str (i) := std_ulogic_to_character (n_value (i));
end loop;
write (l, str, justified, field);
end procedure;
procedure write (l: inout line;
value: in std_logic_vector;
justified: in side := right;
field: in width := 0) is
constant length : natural := value'length;
alias n_value : std_logic_vector (1 to value'length) is value;
variable str : string (1 to length);
begin
for i in str'range loop
str (i) := std_logic_to_character (n_value (i));
end loop;
write (l, str, justified, field);
end procedure;
-- applies to char2quadbits and hread
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
procedure char2quadbits(c: character;
result: out bit_vector(3 downto 0);
good: out boolean;
issue_error: in boolean) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' => result := x"A"; good := true;
when 'B' => result := x"B"; good := true;
when 'C' => result := x"C"; good := true;
when 'D' => result := x"D"; good := true;
when 'E' => result := x"E"; good := true;
when 'F' => result := x"F"; good := true;
when 'a' => result := x"A"; good := true;
when 'b' => result := x"B"; good := true;
when 'c' => result := x"C"; good := true;
when 'd' => result := x"D"; good := true;
when 'e' => result := x"E"; good := true;
when 'f' => result := x"F"; good := true;
when others =>
if issue_error then
assert false report
"hread error: read a '" & c &
"', expected a hex character (0-f).";
end if;
good := false;
end case;
end;
procedure hread(l:inout line; value:out bit_vector) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert false report
"hread error: trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= cr) and (c /= ht));
end loop;
char2quadbits(c, bv(0 to 3), ok, true);
if not ok then
return;
end if;
read(l, s, ok);
if not ok then
assert false
report "hread error: failed to read the string";
return;
end if;
for i in 1 to ne-1 loop
char2quadbits(s(i), bv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
end loop;
value := bv;
end hread;
procedure hread(l:inout line; value:out std_ulogic_vector) is
variable tmp: bit_vector(value'length-1 downto 0);
begin
hread(l, tmp);
value := to_x01(tmp);
end hread;
procedure hread(l:inout line; value:out std_logic_vector) is
variable tmp: bit_vector(value'length-1 downto 0);
begin
hread(l, tmp);
value := to_x01(tmp);
end hread;
procedure hwrite(l:inout line; value:in bit_vector; justified:in side := right; field:in width := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert false report
"hwrite error: trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"a" => s(i+1) := 'a';
when x"b" => s(i+1) := 'b';
when x"c" => s(i+1) := 'c';
when x"d" => s(i+1) := 'd';
when x"e" => s(i+1) := 'e';
when x"f" => s(i+1) := 'f';
end case;
end loop;
write(l, s, justified, field);
end hwrite;
procedure hwrite(l:inout line; value:in std_ulogic_vector;
justified:in side := right; field:in width := 0) is
begin
hwrite(l, to_bitvector(value),justified, field);
end hwrite;
procedure hwrite(l:inout line; value:in std_logic_vector;
justified:in side := right; field:in width := 0) is
begin
hwrite(l, to_bitvector(value), justified, field);
end hwrite;
end package body;
|
-- cb20_gpio_block_0_avalon_slave_0_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_gpio_block_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 4;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(3 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_gpio_block_0_avalon_slave_0_translator;
architecture rtl of cb20_gpio_block_0_avalon_slave_0_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(3 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
gpio_block_0_avalon_slave_0_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_gpio_block_0_avalon_slave_0_translator
|
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Implements an adder of variable width with carry signals.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is
generic (
WIDTH : positive := 8
);
port (
a : in std_logic_vector(WIDTH-1 downto 0);
b : in std_logic_vector(WIDTH-1 downto 0);
c_in : in std_logic;
sum : out std_logic_vector(WIDTH-1 downto 0);
c_out : out std_logic
);
end;
architecture BHV of adder is
signal full_sum : std_logic_vector(WIDTH downto 0);
signal c_in_vec : std_logic_vector(0 downto 0);
begin
c_in_vec(0) <= c_in;
full_sum <= std_logic_vector( resize(unsigned(a), WIDTH+1) + resize(unsigned(b), WIDTH+1) + resize(unsigned(c_in_vec), WIDTH+1) );
sum <= full_sum(WIDTH-1 downto 0);
c_out <= full_sum(WIDTH);
end BHV;
|
library ieee;
use ieee.std_logic_unsigned;
entity tb is
end tb;
|
library ieee;
use ieee.std_logic_unsigned;
entity tb is
end tb;
|
--==============================================================================
-- File: ctrl_fsm.vhd
-- Author: Pietro Lorefice
--==============================================================================
-- Description:
-- FSM portion of the FSMD processor architecture. It keeps track of the
-- internal state and provides the datapath with the correct signals.
--
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_fsm is
port (
clk : in std_logic; -- Clock
rst : in std_logic; -- Reset
opcode : in std_logic_vector(3 downto 0); -- Instruction opcode
alu_op_b_sel : out std_logic; -- ALU operand B select
alu_ctrl_op : out std_logic_vector(1 downto 0); -- ALU control unit operation
pc_en : out std_logic; -- Program counter register enable
ir_en : out std_logic; -- Instruction register enable
reg_we_l : out std_logic; -- Register file write enable
reg_op_a_sel : out std_logic; -- Register file operand A select
reg_op_b_sel : out std_logic; -- Register file operand B select
reg_wr_d_sel : out std_logic; -- Register file write data select
mem_sel_l : out std_logic; -- Data memory select
mem_we_l : out std_logic -- Data memory write enable
);
end entity ctrl_fsm;
architecture RTL of ctrl_fsm is
-- ==================
-- | State register |
-- ==================
type state_t is (fetch, fetch_w,
decode,
read_dab, read_dai, read_d_b, read_d_i,
add, sub, addi, log, logi, ld, st,
write_reg_alu, write_reg_mem, write_reg_mem_w, write_mem,
hlt
);
signal state_q, state_n : state_t;
-- ====================
-- | Output registers |
-- ====================
signal alu_op_b_sel_q, alu_op_b_sel_n : std_logic;
signal alu_ctrl_op_q, alu_ctrl_op_n : std_logic_vector(1 downto 0);
signal pc_en_q, pc_en_n : std_logic;
signal ir_en_q, ir_en_n : std_logic;
signal reg_we_l_q, reg_we_l_n : std_logic;
signal reg_op_a_sel_q, reg_op_a_sel_n : std_logic;
signal reg_op_b_sel_q, reg_op_b_sel_n : std_logic;
signal reg_wr_d_sel_q, reg_wr_d_sel_n : std_logic;
signal mem_sel_l_q, mem_sel_l_n : std_logic;
signal mem_we_l_q, mem_we_l_n : std_logic;
begin
-- ==================
-- | State register |
-- ==================
star : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
state_q <= fetch;
alu_ctrl_op_q <= "00";
alu_op_b_sel_q <= '0';
pc_en_q <= '0';
ir_en_q <= '0';
reg_we_l_q <= '1';
reg_op_a_sel_q <= '0';
reg_op_b_sel_q <= '0';
reg_wr_d_sel_q <= '0';
mem_sel_l_q <= '1';
mem_we_l_q <= '1';
else
state_q <= state_n;
alu_ctrl_op_q <= alu_ctrl_op_n;
alu_op_b_sel_q <= alu_op_b_sel_n;
pc_en_q <= pc_en_n;
ir_en_q <= ir_en_n;
reg_we_l_q <= reg_we_l_n;
reg_op_a_sel_q <= reg_op_a_sel_n;
reg_op_b_sel_q <= reg_op_b_sel_n;
reg_wr_d_sel_q <= reg_wr_d_sel_n;
mem_sel_l_q <= mem_sel_l_n;
mem_we_l_q <= mem_we_l_n;
end if;
end if;
end process star;
-- =============
-- | FSM logic |
-- =============
fsm : process(state_q, opcode,
alu_ctrl_op_q, alu_op_b_sel_q,
ir_en_q, pc_en_q,
mem_sel_l_q, mem_we_l_q,
reg_op_a_sel_q, reg_op_b_sel_q, reg_we_l_q, reg_wr_d_sel_q
) is
begin
state_n <= state_q;
alu_ctrl_op_n <= alu_ctrl_op_q;
alu_op_b_sel_n <= alu_op_b_sel_q;
pc_en_n <= pc_en_q;
ir_en_n <= ir_en_q;
reg_we_l_n <= reg_we_l_q;
reg_op_a_sel_n <= reg_op_a_sel_q;
reg_op_b_sel_n <= reg_op_b_sel_q;
reg_wr_d_sel_n <= reg_wr_d_sel_q;
mem_sel_l_n <= mem_sel_l_q;
mem_we_l_n <= mem_we_l_q;
case state_q is
-- ===============
-- | Fetch phase |
-- ===============
when fetch =>
reg_we_l_n <= '1';
mem_sel_l_n <= '1';
mem_we_l_n <= '1';
pc_en_n <= '1';
ir_en_n <= '1';
state_n <= fetch_w;
when fetch_w =>
pc_en_n <= '0';
state_n <= decode;
-- ================
-- | Decode phase |
-- ================
when decode =>
ir_en_n <= '0';
case opcode is
when X"0" | X"1" =>
state_n <= read_dab;
when X"2" | X"5" | X"6" | X"8" | X"9" =>
state_n <= read_dai;
when X"3" =>
state_n <= read_d_b;
when X"4" =>
state_n <= read_d_i;
when others =>
null;
end case;
-- ==============
-- | Read phase |
-- ==============
when read_dab =>
reg_op_a_sel_n <= '1'; -- 1st operand = Ra
reg_op_b_sel_n <= '1'; -- 2nd operand = Rb
alu_op_b_sel_n <= '0'; -- 2nd ALU operand = Rb
case opcode is
when X"0" =>
state_n <= add;
when X"1" =>
state_n <= sub;
when others =>
state_n <= hlt;
end case;
when read_dai =>
reg_op_a_sel_n <= '1'; -- 1st operand = Ra
reg_op_b_sel_n <= '0'; -- 2nd operand = Rd
alu_op_b_sel_n <= '1'; -- 2nd ALU operand = Immediate
case opcode is
when X"2" =>
state_n <= addi;
when X"5" | X"6" =>
state_n <= ld;
when X"8" | X"9" =>
state_n <= st;
when others =>
state_n <= hlt;
end case;
when read_d_b =>
reg_op_a_sel_n <= '0'; -- 1st operand = Rd
reg_op_b_sel_n <= '1'; -- 2nd operand = Rb
alu_op_b_sel_n <= '0'; -- 2nd ALU operand = Rb
state_n <= log;
when read_d_i =>
reg_op_a_sel_n <= '0'; -- 1st operand = Rd
reg_op_b_sel_n <= '0'; -- 2nd operand = Don't care
alu_op_b_sel_n <= '1'; -- 2nd ALU operand = Immediate
state_n <= logi;
-- ===================
-- | Execution phase |
-- ===================
when add =>
alu_ctrl_op_n <= "10"; -- Ra + Rb
state_n <= write_reg_alu;
when sub =>
alu_ctrl_op_n <= "11"; -- Ra - Rb
state_n <= write_reg_alu;
when addi =>
alu_ctrl_op_n <= "10"; -- Ra + imm
state_n <= write_reg_alu;
when log =>
alu_ctrl_op_n <= "00"; -- Rd {&|!x} Rb
state_n <= write_reg_alu;
when logi =>
alu_ctrl_op_n <= "00"; -- Rd {&|!x} imm
state_n <= write_reg_alu;
when ld =>
alu_ctrl_op_n <= "10"; -- Ra + imm
state_n <= write_reg_mem;
when st =>
alu_ctrl_op_n <= "10"; -- Ra + imm
state_n <= write_mem;
-- ===============
-- | Write phase |
-- ===============
when write_reg_alu =>
reg_wr_d_sel_n <= '1'; -- Result = ALU
reg_we_l_n <= '0';
state_n <= fetch;
when write_reg_mem =>
reg_wr_d_sel_n <= '0'; -- Result = Memory
reg_we_l_n <= '0';
mem_sel_l_n <= '0';
state_n <= write_reg_mem_w;
when write_reg_mem_w =>
state_n <= fetch;
when write_mem =>
mem_sel_l_n <= '0';
mem_we_l_n <= '0';
state_n <= fetch;
-- ================
-- | !! HALTED !! |
-- ================
when hlt =>
state_n <= hlt;
end case;
end process fsm;
-- ======================
-- | Output assignments |
-- ======================
alu_op_b_sel <= alu_op_b_sel_q;
alu_ctrl_op <= alu_ctrl_op_q;
pc_en <= pc_en_q;
ir_en <= ir_en_q;
reg_we_l <= reg_we_l_q;
reg_op_a_sel <= reg_op_a_sel_q;
reg_op_b_sel <= reg_op_b_sel_q;
reg_wr_d_sel <= reg_wr_d_sel_q;
mem_sel_l <= mem_sel_l_q;
mem_we_l <= mem_we_l_q;
end architecture RTL;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_2_block3.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block3
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_2_block3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_9 : IN std_logic; -- ufix1
dout_2_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_2_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_10_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_10_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_9_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_10_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_10_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block3;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block3 IS
-- Signals
SIGNAL dout_2_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din1_re : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_2_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din1_im : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_10_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din2_re : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_10_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din2_im : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_9_re_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_9_im_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_10_re_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_10_im_tmp : signed(18 DOWNTO 0); -- sfix19
BEGIN
dout_2_re_signed <= signed(dout_2_re);
din1_re <= resize(dout_2_re_signed, 19);
dout_2_im_signed <= signed(dout_2_im);
din1_im <= resize(dout_2_im_signed, 19);
dout_10_re_signed <= signed(dout_10_re);
din2_re <= resize(dout_10_re_signed, 19);
dout_10_im_signed <= signed(dout_10_im);
din2_im <= resize(dout_10_im_signed, 19);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_9)
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_9 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 20) + resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 20) - resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 20) + resize(din2_re, 20);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 20) - resize(din2_re, 20);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 20) + resize(din2_re, 20);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 20) - resize(din2_re, 20);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 20) + resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 20) - resize(din2_im, 20);
END IF;
dout_9_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(18 DOWNTO 0);
dout_9_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(18 DOWNTO 0);
dout_10_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(18 DOWNTO 0);
dout_10_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(18 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_9_re <= std_logic_vector(dout_9_re_tmp);
dout_9_im <= std_logic_vector(dout_9_im_tmp);
dout_10_re_1 <= std_logic_vector(dout_10_re_tmp);
dout_10_im_1 <= std_logic_vector(dout_10_im_tmp);
END rtl;
|
-- $Id: rbd_tst_rlink.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rbd_tst_rlink - syn
-- Description: rbus device for tst_rlink
--
-- Dependencies: rbus/rbd_tester
-- rbus/rbd_bram
-- rbus/rbd_rbmon
-- rbus/rbd_eyemon
-- rbus/rbd_timer
-- rbus/rb_sres_or_3
-- rbus/rb_sres_or_4
--
-- Test bench: nexys3/tb/tb_tst_rlink_n3
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-11-09 603 4.0 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2011-11-11 351 1.0 Initial version (derived from tst_rlink)
------------------------------------------------------------------------------
-- Usage of STAT signal:
-- STAT(0): timer 0 busy
-- STAT(1): timer 1 busy
-- STAT(2:3): unused
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rbdlib.all;
-- ----------------------------------------------------------------------------
entity rbd_tst_rlink is -- rbus device for tst_rlink
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_USEC : in slbit; -- usec pulse
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv4; -- rbus: status flags
RB_SRES_TOP : in rb_sres_type; -- top-level rb_sres, for rbd_mon
RXSD : in slbit; -- serport rxsd, for rbd_eyemon
RXACT : in slbit; -- serport rxact, for rbd_eyemon
STAT : out slv8 -- status flags
);
end rbd_tst_rlink;
architecture syn of rbd_tst_rlink is
signal RB_SRES_TEST : rb_sres_type := rb_sres_init;
signal RB_SRES_BRAM : rb_sres_type := rb_sres_init;
signal RB_SRES_MON : rb_sres_type := rb_sres_init;
signal RB_SRES_EMON : rb_sres_type := rb_sres_init;
signal RB_SRES_TIM0 : rb_sres_type := rb_sres_init;
signal RB_SRES_TIM1 : rb_sres_type := rb_sres_init;
signal RB_SRES_SUM1 : rb_sres_type := rb_sres_init;
signal RB_LAM_TEST : slv16 := (others=>'0');
signal TIM0_DONE : slbit := '0';
signal TIM0_BUSY : slbit := '0';
signal TIM1_DONE : slbit := '0';
signal TIM1_BUSY : slbit := '0';
-- rbaddr_rbmon -- default addr - ffe8/8: 1111 1111 1110 1xxx
-- rbaddr_tester -- default addr - ffe0/8: 1111 1111 1110 0xxx
constant rbaddr_eyemon : slv16 := x"ffd0"; -- ffd0/4: 1111 1111 1101 00xx
constant rbaddr_tim1 : slv16 := x"fe11"; -- fe11/1: 1111 1110 0001 0001
constant rbaddr_tim0 : slv16 := x"fe10"; -- fe10/1: 1111 1110 0001 0000
constant rbaddr_bram : slv16 := x"fe00"; -- fe00/2: 1111 1110 0000 00xx
begin
TEST : rbd_tester
generic map (
RB_ADDR => rbaddr_tester)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TEST,
RB_LAM => RB_LAM_TEST,
RB_STAT => RB_STAT
);
BRAM : rbd_bram
generic map (
RB_ADDR => rbaddr_bram)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_BRAM
);
MON : rbd_rbmon
generic map (
RB_ADDR => rbaddr_rbmon,
AWIDTH => 9)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_MON,
RB_SRES_SUM => RB_SRES_TOP
);
EMON : rbd_eyemon
generic map (
RB_ADDR => rbaddr_eyemon,
RDIV => slv(to_unsigned(0,8)))
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_EMON,
RXSD => RXSD,
RXACT => RXACT
);
TIM0 : rbd_timer
generic map (
RB_ADDR => rbaddr_tim0)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TIM0,
DONE => TIM0_DONE,
BUSY => TIM0_BUSY
);
TIM1 : rbd_timer
generic map (
RB_ADDR => rbaddr_tim1)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TIM1,
DONE => TIM1_DONE,
BUSY => TIM1_BUSY
);
RB_SRES_OR1 : rb_sres_or_3
port map (
RB_SRES_1 => RB_SRES_TEST,
RB_SRES_2 => RB_SRES_BRAM,
RB_SRES_3 => RB_SRES_MON,
RB_SRES_OR => RB_SRES_SUM1
);
RB_SRES_OR : rb_sres_or_4
port map (
RB_SRES_1 => RB_SRES_SUM1,
RB_SRES_2 => RB_SRES_EMON,
RB_SRES_3 => RB_SRES_TIM0,
RB_SRES_4 => RB_SRES_TIM1,
RB_SRES_OR => RB_SRES
);
RB_LAM(15 downto 2) <= RB_LAM_TEST(15 downto 2);
RB_LAM(1) <= TIM1_DONE;
RB_LAM(0) <= TIM0_DONE;
STAT(0) <= TIM0_BUSY;
STAT(1) <= TIM1_BUSY;
STAT(7 downto 2) <= (others=>'0');
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_215 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_215;
architecture augh of cmp_215 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_215 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_215;
architecture augh of cmp_215 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
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ASOrMDu949T7Ni5RLwuF/zor3Z4AolEYqli0q7d8o2nnsa2SF2mz6o/2oTKa36YIA/mlrF8v+fNc
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lGB+tbrZQo667aBA6nUvF8ZxNfAwXaHDseHj5Vc=
`protect end_protected
|
-- $Id: tb_w11a_n3.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_w11a_n3
-- Description: Configuration for tb_w11a_n3 for tb_nexys3_fusp_cuff
--
-- Dependencies: sys_w11a_n3
--
-- To test: sys_w11a_n3
--
-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat
-- (#2) ../../tb/tb_pdp11_core_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2011-11-25 295 - -.-- - - -:--
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.1 now based on tb_nexys3_fusp_cuff
-- 2011-11-25 432 1.0 Initial version (cloned from _n2)
------------------------------------------------------------------------------
configuration tb_w11a_n3 of tb_nexys3_fusp_cuff is
for sim
for all : nexys3_fusp_cuff_aif
use entity work.sys_w11a_n3;
end for;
end for;
end tb_w11a_n3;
|
entity bounds13 is
end entity;
architecture test of bounds13 is
begin
process is
type myint is range 1 to 3;
begin
assert myint'value(" 3 ") = 3;
assert myint'value("4") = 1 or true; -- Error
wait;
end process;
end architecture;
|
entity bounds13 is
end entity;
architecture test of bounds13 is
begin
process is
type myint is range 1 to 3;
begin
assert myint'value(" 3 ") = 3;
assert myint'value("4") = 1 or true; -- Error
wait;
end process;
end architecture;
|
entity bounds13 is
end entity;
architecture test of bounds13 is
begin
process is
type myint is range 1 to 3;
begin
assert myint'value(" 3 ") = 3;
assert myint'value("4") = 1 or true; -- Error
wait;
end process;
end architecture;
|
entity bounds13 is
end entity;
architecture test of bounds13 is
begin
process is
type myint is range 1 to 3;
begin
assert myint'value(" 3 ") = 3;
assert myint'value("4") = 1 or true; -- Error
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2613.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02613ent IS
END c13s03b01x00p02n01i02613ent;
ARCHITECTURE c13s03b01x00p02n01i02613arch OF c13s03b01x00p02n01i02613ent IS
BEGIN
TESTING: PROCESS
variable k%k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02613 - Identifier can not contain '%'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02613arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2613.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02613ent IS
END c13s03b01x00p02n01i02613ent;
ARCHITECTURE c13s03b01x00p02n01i02613arch OF c13s03b01x00p02n01i02613ent IS
BEGIN
TESTING: PROCESS
variable k%k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02613 - Identifier can not contain '%'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02613arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2613.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02613ent IS
END c13s03b01x00p02n01i02613ent;
ARCHITECTURE c13s03b01x00p02n01i02613arch OF c13s03b01x00p02n01i02613ent IS
BEGIN
TESTING: PROCESS
variable k%k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02613 - Identifier can not contain '%'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02613arch;
|
-- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity test_processor is
End Entity test_processor;
Architecture test_general of test_processor is
Component Mips8B is
Port(Reset_n: In Std_Logic;
Clock: In Std_Logic;
MAddr: Out Std_Logic_Vector(7 downto 0);
MCmd: Out Std_Logic_Vector(1 downto 0);
MData: Out Std_Logic_Vector(7 downto 0);
SData: In Std_Logic_Vector(7 downto 0);
SCmdAccept: In Std_Logic);
End Component Mips8B;
Type Memory_Array is Array(Natural Range <>) of Std_Logic_Vector(7 downto 0);
Use Work.MIPS8B_Base.ocpIDLE_little;
Use Work.MIPS8B_Base.ocpWR_little;
Use Work.MIPS8B_Base.ocpRD_little;
Use Work.MIPS8B_Base.ocpNULL_little;
Use Work.MIPS8B_Base.ocpDVA_little;
Signal Reset_n: Std_Logic;
Signal Clock: Std_Logic := '0';
Signal Clock_Mem: Std_Logic := '0';
Signal MAddr: Std_Logic_Vector(7 downto 0);
Signal MCmd: Std_Logic_Vector(1 downto 0);
Signal MData: Std_Logic_Vector(7 downto 0);
Signal SData: Std_Logic_Vector(7 downto 0);
Signal SCmdAccept: Std_Logic;
Begin
Reset_n <= '1', '0' after 20 ns, '1' after 40 ns;
Clock <= not Clock after 10 ns;
Clock_Mem <= not Clock_Mem after 15 ns;
Memory: Process
Variable int_SCmdAccept: Std_Logic;
Variable address: Unsigned(7 downto 0);
Variable mem_int: Memory_Array(0 to 255) := (
"00100000", "00000001", "00000000", "11001000",
"00100000", "00000010", "00000000", "10001001",
"00100000", "00000011", "00000000", "11001101",
"10100000", "00100010", "00000000", "00000000",
"00100000", "00100001", "00000000", "00000001",
"00100000", "01000010", "00000000", "11101111",
"00010000", "01100001", "00000000", "00000010",
"00010000", "00000000", "00000000", "11111100",
"00000000", "00000000", "00001000", "00100101",
"00100000", "00000110", "00000000", "11001000",
"00100000", "11000111", "00000000", "00000001",
"00100000", "00000101", "00000000", "11001101",
"00010000", "10100111", "00000000", "00001011",
"10000000", "11000011", "00000000", "00000000",
"10000000", "11100100", "00000000", "00000000",
"00000000", "10000011", "00010000", "00101010",
"00010000", "01000000", "00000000", "00000100",
"00100000", "00100001", "00000000", "00000001",
"10100000", "11000100", "00000000", "00000000",
"10100000", "11100011", "00000000", "00000000",
"00000000", "11100000", "00110000", "00100000",
"00100000", "11100111", "00000000", "00000001",
"00010000", "00000000", "00000000", "11110110",
"00010000", "00000001", "00000000", "00000010",
"00010000", "00000000", "00000000", "11110000",
"00100000", "00000011", "00000000", "11001101",
"00100000", "00000001", "00000000", "11001000",
"10000000", "00100010", "00000000", "00000000",
"10100000", "00100010", "00000000", "00000000",
"00100000", "00100001", "00000000", "00000001",
"00010000", "01100001", "00000000", "11111100",
"00010000", "00000000", "00000000", "11111100",
Others => "00000000");
Begin
Wait Until Clock_Mem'Event and Clock_Mem='1';
Case MCmd is
When ocpWR_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
mem_int(to_integer(address)) := MData;
Else
int_SCmdAccept := ocpNULL_little;
End If;
SData <= "ZZZZZZZZ";
When ocpRD_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
SData <= mem_int(to_integer(address));
Else
int_SCmdAccept := ocpNULL_little;
End If;
When Others =>
int_SCmdAccept := ocpNULL_little;
SData <= "ZZZZZZZZ";
End Case;
SCmdAccept <= int_SCmdAccept;
End Process Memory;
DUV: Mips8B
Port Map( Reset_n => Reset_n,
Clock => Clock,
MAddr => MAddr,
MCmd => MCmd,
MData => MData,
SData => SData,
SCmdAccept => SCmdAccept);
End Architecture test_general;
Configuration general_test of test_processor is
For test_general
For DUV: Mips8B Use Configuration Work.Mips8B_struct_conf;
End For;
End For;
End Configuration general_test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library gaisler;
use gaisler.pci.all;
use work.pcilib2.all;
entity grpci2_phy_wrapper is
generic(
tech : integer := DEFMEMTECH;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0;
scantest: integer := 0;
iotest : integer := 0
);
port(
pciclk : in std_logic;
pcii : in pci_in_type;
phyi : in grpci2_phy_in_type;
pcio : out pci_out_type;
phyo : out grpci2_phy_out_type;
iotmact : in std_ulogic;
iotmoe : in std_ulogic;
iotdout : in std_logic_vector(44 downto 0);
iotdin : out std_logic_vector(45 downto 0)
);
end;
architecture wrapper of grpci2_phy_wrapper is
attribute dont_touch : boolean;
attribute dont_touch of net : label is true;
begin
rtl : if netlist = 0 generate
phy0 : grpci2_phy
generic map( tech => tech, oepol => oepol,
bypass => bypass, netlist => netlist,
scantest => scantest, iotest => iotest)
port map(
pciclk => pciclk,
pcii => pcii,
phyi => phyi,
pcio => pcio,
phyo => phyo,
iotmact => iotmact,
iotmoe => iotmoe,
iotdout => iotdout,
iotdin => iotdin
);
end generate;
net : if netlist /= 0 generate
phy0 : grpci2_phy_net
generic map( tech => tech, oepol => oepol,
bypass => bypass, netlist => netlist)
port map(
pciclk => pciclk,
--pcii : in pci_in_type,
pcii_rst => pcii.rst,
pcii_gnt => pcii.gnt,
pcii_idsel => pcii.idsel,
pcii_ad => pcii.ad,
pcii_cbe => pcii.cbe,
pcii_frame => pcii.frame,
pcii_irdy => pcii.irdy,
pcii_trdy => pcii.trdy,
pcii_devsel => pcii.devsel,
pcii_stop => pcii.stop,
pcii_lock => pcii.lock,
pcii_perr => pcii.perr,
pcii_serr => pcii.serr,
pcii_par => pcii.par,
pcii_host => pcii.host,
pcii_pci66 => pcii.pci66,
pcii_pme_status => pcii.pme_status,
pcii_int => pcii.int,
--phyi : in grpci2_phy_in_type,
phyi_pcirstout => phyi.pcirstout,
phyi_pciasyncrst => phyi.pciasyncrst,
phyi_pcisoftrst => phyi.pcisoftrst,
phyi_pciinten => phyi.pciinten,
phyi_m_request => phyi.m_request,
phyi_m_mabort => phyi.m_mabort,
phyi_pr_m_fstate => phyi.pr_m_fstate,
phyi_pr_m_cfifo_0_data => phyi.pr_m_cfifo(0).data,
phyi_pr_m_cfifo_0_last => phyi.pr_m_cfifo(0).last,
phyi_pr_m_cfifo_0_stlast => phyi.pr_m_cfifo(0).stlast,
phyi_pr_m_cfifo_0_hold => phyi.pr_m_cfifo(0).hold,
phyi_pr_m_cfifo_0_valid => phyi.pr_m_cfifo(0).valid,
phyi_pr_m_cfifo_0_err => phyi.pr_m_cfifo(0).err,
phyi_pr_m_cfifo_1_data => phyi.pr_m_cfifo(1).data,
phyi_pr_m_cfifo_1_last => phyi.pr_m_cfifo(1).last,
phyi_pr_m_cfifo_1_stlast => phyi.pr_m_cfifo(1).stlast,
phyi_pr_m_cfifo_1_hold => phyi.pr_m_cfifo(1).hold,
phyi_pr_m_cfifo_1_valid => phyi.pr_m_cfifo(1).valid,
phyi_pr_m_cfifo_1_err => phyi.pr_m_cfifo(1).err,
phyi_pr_m_cfifo_2_data => phyi.pr_m_cfifo(2).data,
phyi_pr_m_cfifo_2_last => phyi.pr_m_cfifo(2).last,
phyi_pr_m_cfifo_2_stlast => phyi.pr_m_cfifo(2).stlast,
phyi_pr_m_cfifo_2_hold => phyi.pr_m_cfifo(2).hold,
phyi_pr_m_cfifo_2_valid => phyi.pr_m_cfifo(2).valid,
phyi_pr_m_cfifo_2_err => phyi.pr_m_cfifo(2).err,
phyi_pv_m_cfifo_0_data => phyi.pv_m_cfifo(0).data,
phyi_pv_m_cfifo_0_last => phyi.pv_m_cfifo(0).last,
phyi_pv_m_cfifo_0_stlast => phyi.pv_m_cfifo(0).stlast,
phyi_pv_m_cfifo_0_hold => phyi.pv_m_cfifo(0).hold,
phyi_pv_m_cfifo_0_valid => phyi.pv_m_cfifo(0).valid,
phyi_pv_m_cfifo_0_err => phyi.pv_m_cfifo(0).err,
phyi_pv_m_cfifo_1_data => phyi.pv_m_cfifo(1).data,
phyi_pv_m_cfifo_1_last => phyi.pv_m_cfifo(1).last,
phyi_pv_m_cfifo_1_stlast => phyi.pv_m_cfifo(1).stlast,
phyi_pv_m_cfifo_1_hold => phyi.pv_m_cfifo(1).hold,
phyi_pv_m_cfifo_1_valid => phyi.pv_m_cfifo(1).valid,
phyi_pv_m_cfifo_1_err => phyi.pv_m_cfifo(1).err,
phyi_pv_m_cfifo_2_data => phyi.pv_m_cfifo(2).data,
phyi_pv_m_cfifo_2_last => phyi.pv_m_cfifo(2).last,
phyi_pv_m_cfifo_2_stlast => phyi.pv_m_cfifo(2).stlast,
phyi_pv_m_cfifo_2_hold => phyi.pv_m_cfifo(2).hold,
phyi_pv_m_cfifo_2_valid => phyi.pv_m_cfifo(2).valid,
phyi_pv_m_cfifo_2_err => phyi.pv_m_cfifo(2).err,
phyi_pr_m_addr => phyi.pr_m_addr,
phyi_pr_m_cbe_data => phyi.pr_m_cbe_data,
phyi_pr_m_cbe_cmd => phyi.pr_m_cbe_cmd,
phyi_pr_m_first => phyi.pr_m_first,
phyi_pv_m_term => phyi.pv_m_term,
phyi_pr_m_ltimer => phyi.pr_m_ltimer,
phyi_pr_m_burst => phyi.pr_m_burst,
phyi_pr_m_abort => phyi.pr_m_abort,
phyi_pr_m_perren => phyi.pr_m_perren,
phyi_pr_m_done_fifo => phyi.pr_m_done_fifo,
phyi_t_abort => phyi.t_abort,
phyi_t_ready => phyi.t_ready,
phyi_t_retry => phyi.t_retry,
phyi_pr_t_state => phyi.pr_t_state,
phyi_pv_t_state => phyi.pv_t_state,
phyi_pr_t_fstate => phyi.pr_t_fstate,
phyi_pr_t_cfifo_0_data => phyi.pr_t_cfifo(0).data,
phyi_pr_t_cfifo_0_last => phyi.pr_t_cfifo(0).last,
phyi_pr_t_cfifo_0_stlast => phyi.pr_t_cfifo(0).stlast,
phyi_pr_t_cfifo_0_hold => phyi.pr_t_cfifo(0).hold,
phyi_pr_t_cfifo_0_valid => phyi.pr_t_cfifo(0).valid,
phyi_pr_t_cfifo_0_err => phyi.pr_t_cfifo(0).err,
phyi_pr_t_cfifo_1_data => phyi.pr_t_cfifo(1).data,
phyi_pr_t_cfifo_1_last => phyi.pr_t_cfifo(1).last,
phyi_pr_t_cfifo_1_stlast => phyi.pr_t_cfifo(1).stlast,
phyi_pr_t_cfifo_1_hold => phyi.pr_t_cfifo(1).hold,
phyi_pr_t_cfifo_1_valid => phyi.pr_t_cfifo(1).valid,
phyi_pr_t_cfifo_1_err => phyi.pr_t_cfifo(1).err,
phyi_pr_t_cfifo_2_data => phyi.pr_t_cfifo(2).data,
phyi_pr_t_cfifo_2_last => phyi.pr_t_cfifo(2).last,
phyi_pr_t_cfifo_2_stlast => phyi.pr_t_cfifo(2).stlast,
phyi_pr_t_cfifo_2_hold => phyi.pr_t_cfifo(2).hold,
phyi_pr_t_cfifo_2_valid => phyi.pr_t_cfifo(2).valid,
phyi_pr_t_cfifo_2_err => phyi.pr_t_cfifo(2).err,
phyi_pv_t_diswithout => phyi.pv_t_diswithout,
phyi_pr_t_stoped => phyi.pr_t_stoped,
phyi_pr_t_lcount => phyi.pr_t_lcount,
phyi_pr_t_first_word => phyi.pr_t_first_word,
phyi_pr_t_cur_acc_0_read => phyi.pr_t_cur_acc_0_read,
phyi_pv_t_hold_write => phyi.pv_t_hold_write,
phyi_pv_t_hold_reset => phyi.pv_t_hold_reset,
phyi_pr_conf_comm_perren => phyi.pr_conf_comm_perren,
phyi_pr_conf_comm_serren => phyi.pr_conf_comm_serren,
--pcio : out pci_out_type,
pcio_aden => pcio.aden,
pcio_vaden => pcio.vaden,
pcio_cbeen => pcio.cbeen,
pcio_frameen => pcio.frameen,
pcio_irdyen => pcio.irdyen,
pcio_trdyen => pcio.trdyen,
pcio_devselen => pcio.devselen,
pcio_stopen => pcio.stopen,
pcio_ctrlen => pcio.ctrlen,
pcio_perren => pcio.perren,
pcio_paren => pcio.paren,
pcio_reqen => pcio.reqen,
pcio_locken => pcio.locken,
pcio_serren => pcio.serren,
pcio_inten => pcio.inten,
pcio_vinten => pcio.vinten,
pcio_req => pcio.req,
pcio_ad => pcio.ad,
pcio_cbe => pcio.cbe,
pcio_frame => pcio.frame,
pcio_irdy => pcio.irdy,
pcio_trdy => pcio.trdy,
pcio_devsel => pcio.devsel,
pcio_stop => pcio.stop,
pcio_perr => pcio.perr,
pcio_serr => pcio.serr,
pcio_par => pcio.par,
pcio_lock => pcio.lock,
pcio_power_state => pcio.power_state,
pcio_pme_enable => pcio.pme_enable,
pcio_pme_clear => pcio.pme_clear,
pcio_int => pcio.int,
pcio_rst => pcio.rst,
--phyo : out grpci2_phy_out_type
phyo_pciv_rst => phyo.pciv.rst,
phyo_pciv_gnt => phyo.pciv.gnt,
phyo_pciv_idsel => phyo.pciv.idsel,
phyo_pciv_ad => phyo.pciv.ad,
phyo_pciv_cbe => phyo.pciv.cbe,
phyo_pciv_frame => phyo.pciv.frame,
phyo_pciv_irdy => phyo.pciv.irdy,
phyo_pciv_trdy => phyo.pciv.trdy,
phyo_pciv_devsel => phyo.pciv.devsel,
phyo_pciv_stop => phyo.pciv.stop,
phyo_pciv_lock => phyo.pciv.lock,
phyo_pciv_perr => phyo.pciv.perr,
phyo_pciv_serr => phyo.pciv.serr,
phyo_pciv_par => phyo.pciv.par,
phyo_pciv_host => phyo.pciv.host,
phyo_pciv_pci66 => phyo.pciv.pci66,
phyo_pciv_pme_status => phyo.pciv.pme_status,
phyo_pciv_int => phyo.pciv.int,
phyo_pr_m_state => phyo.pr_m_state,
phyo_pr_m_last => phyo.pr_m_last,
phyo_pr_m_hold => phyo.pr_m_hold,
phyo_pr_m_term => phyo.pr_m_term,
phyo_pr_t_hold => phyo.pr_t_hold,
phyo_pr_t_stop => phyo.pr_t_stop,
phyo_pr_t_abort => phyo.pr_t_abort,
phyo_pr_t_diswithout => phyo.pr_t_diswithout,
phyo_pr_t_addr_perr => phyo.pr_t_addr_perr,
phyo_pcirsto => phyo.pcirsto,
phyo_pr_po_ad => phyo.pr_po.ad,
phyo_pr_po_aden => phyo.pr_po.aden,
phyo_pr_po_cbe => phyo.pr_po.cbe,
phyo_pr_po_cbeen => phyo.pr_po.cbeen,
phyo_pr_po_frame => phyo.pr_po.frame,
phyo_pr_po_frameen => phyo.pr_po.frameen,
phyo_pr_po_irdy => phyo.pr_po.irdy,
phyo_pr_po_irdyen => phyo.pr_po.irdyen,
phyo_pr_po_trdy => phyo.pr_po.trdy,
phyo_pr_po_trdyen => phyo.pr_po.trdyen,
phyo_pr_po_stop => phyo.pr_po.stop,
phyo_pr_po_stopen => phyo.pr_po.stopen,
phyo_pr_po_devsel => phyo.pr_po.devsel,
phyo_pr_po_devselen => phyo.pr_po.devselen,
phyo_pr_po_par => phyo.pr_po.par,
phyo_pr_po_paren => phyo.pr_po.paren,
phyo_pr_po_perr => phyo.pr_po.perr,
phyo_pr_po_perren => phyo.pr_po.perren,
phyo_pr_po_lock => phyo.pr_po.lock,
phyo_pr_po_locken => phyo.pr_po.locken,
phyo_pr_po_req => phyo.pr_po.req,
phyo_pr_po_reqen => phyo.pr_po.reqen,
phyo_pr_po_serren => phyo.pr_po.serren,
phyo_pr_po_inten => phyo.pr_po.inten,
phyo_pr_po_vinten => phyo.pr_po.vinten,
phyo_pio_rst => phyo.pio.rst,
phyo_pio_gnt => phyo.pio.gnt,
phyo_pio_idsel => phyo.pio.idsel,
phyo_pio_ad => phyo.pio.ad,
phyo_pio_cbe => phyo.pio.cbe,
phyo_pio_frame => phyo.pio.frame,
phyo_pio_irdy => phyo.pio.irdy,
phyo_pio_trdy => phyo.pio.trdy,
phyo_pio_devsel => phyo.pio.devsel,
phyo_pio_stop => phyo.pio.stop,
phyo_pio_lock => phyo.pio.lock,
phyo_pio_perr => phyo.pio.perr,
phyo_pio_serr => phyo.pio.serr,
phyo_pio_par => phyo.pio.par,
phyo_pio_host => phyo.pio.host,
phyo_pio_pci66 => phyo.pio.pci66,
phyo_pio_pme_status => phyo.pio.pme_status,
phyo_pio_int => phyo.pio.int,
phyo_poo_ad => phyo.poo.ad,
phyo_poo_aden => phyo.poo.aden,
phyo_poo_cbe => phyo.poo.cbe,
phyo_poo_cbeen => phyo.poo.cbeen,
phyo_poo_frame => phyo.poo.frame,
phyo_poo_frameen => phyo.poo.frameen,
phyo_poo_irdy => phyo.poo.irdy,
phyo_poo_irdyen => phyo.poo.irdyen,
phyo_poo_trdy => phyo.poo.trdy,
phyo_poo_trdyen => phyo.poo.trdyen,
phyo_poo_stop => phyo.poo.stop,
phyo_poo_stopen => phyo.poo.stopen,
phyo_poo_devsel => phyo.poo.devsel,
phyo_poo_devselen => phyo.poo.devselen,
phyo_poo_par => phyo.poo.par,
phyo_poo_paren => phyo.poo.paren,
phyo_poo_perr => phyo.poo.perr,
phyo_poo_perren => phyo.poo.perren,
phyo_poo_lock => phyo.poo.lock,
phyo_poo_locken => phyo.poo.locken,
phyo_poo_req => phyo.poo.req,
phyo_poo_reqen => phyo.poo.reqen,
phyo_poo_serren => phyo.poo.serren,
phyo_poo_inten => phyo.poo.inten,
phyo_poo_vinten => phyo.poo.vinten
);
end generate;
end;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_10 is
-- code from book
attribute foreign : string;
-- end code from book
end package inline_10;
entity and2 is
end entity and2;
-- code from book
architecture accelerated of and2 is
attribute foreign of accelerated : architecture is
"accelerate/function:and_2in/nocheck";
begin
end architecture accelerated;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_10 is
-- code from book
attribute foreign : string;
-- end code from book
end package inline_10;
entity and2 is
end entity and2;
-- code from book
architecture accelerated of and2 is
attribute foreign of accelerated : architecture is
"accelerate/function:and_2in/nocheck";
begin
end architecture accelerated;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package inline_10 is
-- code from book
attribute foreign : string;
-- end code from book
end package inline_10;
entity and2 is
end entity and2;
-- code from book
architecture accelerated of and2 is
attribute foreign of accelerated : architecture is
"accelerate/function:and_2in/nocheck";
begin
end architecture accelerated;
-- end code from book
|
architecture ARCH of ENTITY1 is
begin
-- Passing wo default
assert boolean
report "Something something something" &
"Something else and this other thing"
severity FAILURE;
assert boolean
report "Something something something" &
"Something else and this other thing";
-- Passing w default
assert boolean
report "Something something something" &
"Something else and this other thing"
severity FAILURE;
assert boolean
report "Something something something" &
"Something else and this other thing";
-- Failing
assert boolean
report "Something something something" &
"Something else and this other thing"
severity FAILURE;
assert boolean
report "Something something something" &
"Something else and this other thing";
end architecture ARCH;
|
--
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity DisplayCounter is
port(
-- main clock
clock: in std_logic;
-- rotary push button
A, B, PB: in std_logic;
-- 4-digit 7-segment display
segments: out std_logic_vector(6 downto 0);
dp: out std_logic;
sel: out std_logic_vector(3 downto 0)
);
end DisplayCounter;
architecture Behavioral of DisplayCounter is
-- component for rotary-only support of rotary switch
component Rotary is
port(
clock: in std_logic;
A: in std_logic;
B: in std_logic;
inc: out std_logic;
dec: out std_logic
);
end component;
-- component to display 4 7-segment digits
component Display4 is
generic(
DIGIT_COUNT: positive
);
port(
clock: in std_logic;
data_write_enable: in std_logic;
data: in std_logic_vector(DIGIT_COUNT * 4 - 1 downto 0);
dps: in std_logic_vector(DIGIT_COUNT - 1 downto 0);
segments: out std_logic_vector(6 downto 0);
dp: out std_logic;
sel: out std_logic_vector(DIGIT_COUNT - 1 downto 0)
);
end component;
-- component to debounce rotary push button
component Debouncer is
port(
clock: in std_logic;
reset: in std_logic;
d_in: in std_logic;
d_out: out std_logic
);
end component;
-- individual digit data and an aggregate of those values
subtype digitType is std_logic_vector(3 downto 0);
type digitTypes is array(0 to 3) of digitType;
signal digits: digitTypes;
signal display_data: std_logic_vector(15 downto 0);
-- signals from rotary indicating rotation direction
signal up, down: std_logic;
-- signals to write current display data
signal enable_write: std_logic := '1';
signal active_digit: std_logic_vector(3 downto 0) := (others => '0');
-- state tracking to detect push button edges
signal last_debounced: std_logic := '0';
signal current_debounced: std_logic := '0';
signal PB_debounced: std_logic := '0';
begin
-- create rotary decoder
r: Rotary
port map(
clock => clock,
A => A,
B => B,
inc => up,
dec => down
);
-- create 4-digit display
d4: Display4
generic map(
DIGIT_COUNT => 4
)
port map(
clock => clock,
data_write_enable => enable_write,
data => display_data,
dps => active_digit,
segments => segments,
dp => dp,
sel => sel
);
-- create button debouncer
db: Debouncer
port map(
clock => clock,
reset => PB,
d_in => not PB,
d_out => PB_debounced
);
-- concatenate individual digits into a single 16-bit value
update_display: process(clock, digits)
begin
if clock'event and clock = '1' then
display_data <= digits(0) & digits(1) & digits(2) & digits(3);
end if;
end process;
-- update current digit based on rotary output
-- update active digit which turns on that digits decimal point. Normally,
-- I would separate the logic for rotary and the push button into separate
-- processes, but since both require activation of enable_write, I decided
-- to combine both into a single process
update_counter: process(clock, up, down, PB, active_digit)
variable digit_index: integer range 0 to 3 := 0;
begin
if clock'event and clock = '1' then
-- shift last value and current value for edge detection
last_debounced <= current_debounced;
current_debounced <= PB_debounced;
-- handle increment/decrement if a digit is active; otherwise,
-- handle possible postive edge of push button
if down = '1' and active_digit /= "0000" then
digits(digit_index) <= digits(digit_index) - 1;
enable_write <= '1';
elsif up = '1' and active_digit /= "0000" then
digits(digit_index) <= digits(digit_index) + 1;
enable_write <= '1';
elsif last_debounced = '0' and current_debounced = '1' then
case active_digit is
when "0000" => active_digit <= "0001"; digit_index := 0;
when "0001" => active_digit <= "0010"; digit_index := 1;
when "0010" => active_digit <= "0100"; digit_index := 2;
when "0100" => active_digit <= "1000"; digit_index := 3;
when "1000" => active_digit <= "0000"; digit_index := 0;
when others => active_digit <= "0000"; digit_index := 0;
end case;
enable_write <= '1';
else
enable_write <= '0';
end if;
end if;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- ZIPPY routing element (8 inputs, 1 output, 3 tristate outputs)
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/routel.vhd $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/09/06
-- $Id: routel.vhd 241 2005-04-07 08:50:55Z plessl $
------------------------------------------------------------------------------
-- Routing element in engine. Route input data from interconnect to
-- processing element.
-- Each routing element has 8 inputs (local interconect and bus taps) and
-- 1 output that can be connected to the neighbor cells direct inputs as well
-- as 3 outputs with tristate buffers (that are used to drive the south buses).
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
entity RoutEl is
generic (
DATAWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ConfigxI : in routConfigRec;
-- access to routing
InputxDI : in cellInputRec;
OutputxZO : out CellOutputRec;
-- access to processing element
ProcElInxDO : out procelInputArray; -- inputs to processing element
ProcElOutxDI : in std_logic_vector(DATAWIDTH-1 downto 0)); -- output of PE
end RoutEl;
architecture simple of RoutEl is
begin -- simple
-----------------------------------------------------------------------------
-- INPUT DRIVERS to processing element
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Generate input drivers that drive the cell inputs signals to the
-- processing element inputs. The desired input for a procel input is
-- selected by enabling tristate buffers on a bus (not with a multiplexer, as
-- used in the initial versions of the code)
-----------------------------------------------------------------------------
gen_inputdrivers : for inp in ConfigxI.i'range generate
-- generate drivers for local interconnect inputs
gen_local : for localcon in ConfigxI.i(inp).LocalxE'range generate
localcondrvin : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => InputxDI.LocalxDI(localcon),
OExEI => ConfigxI.i(inp).LocalxE(localcon),
OutxZO => ProcelInxDO(inp)
);
end generate gen_local;
-- generate drivers for HBusN inputs
gen_hbusn : for hbusn in ConfigxI.i(inp).HBusNxE'range generate
hbusndrvin : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => InputxDI.HBusNxDI(hbusn),
OExEI => ConfigxI.i(inp).HBusNxE(hbusn),
OutxZO => ProcelInxDO(inp)
);
end generate gen_hbusn;
-- generate drivers for HBusS inputs
gen_hbuss : for hbuss in ConfigxI.i(inp).HBusSxE'range generate
hbussdrvin : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => InputxDI.HBusSxDI(hbuss),
OExEI => ConfigxI.i(inp).HBusSxE(hbuss),
OutxZO => ProcelInxDO(inp)
);
end generate gen_hbuss;
-- generate drivers for VBusE inputs
gen_vbuse : for vbuse in ConfigxI.i(inp).VBusExE'range generate
vbusedrvin : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => InputxDI.VBusExDI(vbuse),
OExEI => ConfigxI.i(inp).VBusExE(vbuse),
OutxZO => ProcelInxDO(inp)
);
end generate gen_vbuse;
end generate gen_inputdrivers;
-----------------------------------------------------------------------------
-- OUTPUT DRIVERS from processing elements
-----------------------------------------------------------------------------
-- direct output path
OutputxZO.LocalxDO <= ProcElOutxDI;
-- generate drivers for HBusN outputs
gen_drvouthbusn : for hbusn in ConfigxI.o.HBusNxE'range generate
hbusndrvout : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => ProcElOutxDI,
OExEI => ConfigxI.o.HBusNxE(hbusn),
OutxZO => OutputxZO.HBusNxDZ(hbusn)
);
end generate gen_drvouthbusn;
-- generate drivers for HBusS outputs
gen_drvouthbuss : for hbuss in ConfigxI.o.HBusSxE'range generate
hbussdrvout : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => ProcElOUtxDI,
OExEI => ConfigxI.o.HBusSxE(hbuss),
OutxZO => OutputxZO.HBusSxDZ(hbuss)
);
end generate gen_drvouthbuss;
-- generate drivers for VBusE inputs
gen_drvoutvbuse : for vbuse in ConfigxI.o.VBusExE'range generate
vbusedrvout : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => ProcElOUtxDI,
OExEI => ConfigxI.o.VBusExE(vbuse),
OutxZO => OutputxZO.VBusExDZ(vbuse)
);
end generate gen_drvoutvbuse;
end simple;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.09:04:04)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END mpegmv_ibea_entity;
ARCHITECTURE mpegmv_ibea_description OF mpegmv_ibea_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register3 := input3 * 3;
register1 := register1 + 5;
register4 := input4 * 6;
register2 := register2 + 8;
WHEN "00000011" =>
register1 := register4 + register1;
register4 := input5 * 9;
WHEN "00000100" =>
register1 := register4 + register1;
register4 := input6 * 10;
register5 := input7 * 11;
register2 := register3 + register2;
WHEN "00000101" =>
register3 := input8 * 12;
register5 := register5 + 14;
register6 := input9 * 15;
register1 := ((NOT register1) + 1) XOR register1;
register2 := register4 + register2;
WHEN "00000110" =>
register3 := register3 + 19;
register4 := input10 * 20;
register7 := input11 * 21;
WHEN "00000111" =>
register4 := register4 + register5;
register5 := input12 * 22;
output1 <= register7 + register3;
WHEN "00001000" =>
register3 := register5 + 25;
register4 := register6 + register4;
register5 := input13 * 26;
register2 := ((NOT register2) + 1) XOR register2;
register6 := input14 * 29;
WHEN "00001001" =>
register3 := register6 + register3;
output2 <= register1(0 TO 15) & register4(0 TO 15);
WHEN "00001010" =>
register1 := register5 + register3;
WHEN "00001011" =>
output3 <= register2(0 TO 15) & register1(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_ibea_description; |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5808)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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9s0qEeMi9k4HxMVPc9k=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5808)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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V2+V1FG8hw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5808)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5808)
`protect data_block
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`protect end_protected
|
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