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------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: fir
-- File: fir_v1.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: FIR filter core (version 1) -- for dprc demo
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity fir is
port (
clk : in std_ulogic;
rst : in std_ulogic;
start : in std_ulogic;
in_data : in std_logic_vector(31 downto 0);
in_data_read : out std_ulogic;
out_data : out std_logic_vector (31 downto 0);
out_data_write : out std_ulogic);
end fir;
architecture fir_rtl of fir is
type fsm_state is (idle, running);
signal pstate, nstate : fsm_state;
type sh_reg_type is array (0 to 8) of unsigned(7 downto 0);
signal sh_reg, rsh_reg : sh_reg_type;
type mul_type is array (0 to 9) of unsigned(15 downto 0);
signal mul, rmul : mul_type;
signal rout_data : std_logic_vector(21 downto 0);
signal dcount, rdcount : std_logic_vector(8 downto 0);
type coeffT is array (0 to 9) of unsigned(7 downto 0);
constant coeff : coeffT := (to_unsigned(21,8),to_unsigned(23,8),to_unsigned(21,8),to_unsigned(19,8),to_unsigned(13,8),to_unsigned(9,8),to_unsigned(13,8),to_unsigned(15,8),to_unsigned(21,8),to_unsigned(17,8));
begin
comb: process(rsh_reg, rmul, start, pstate, rdcount, in_data)
variable vsh_reg : sh_reg_type;
variable vout_data : unsigned(21 downto 0);
variable start_flag : std_ulogic;
variable vdcount : std_logic_vector(8 downto 0);
begin
vdcount := rdcount;
vout_data := to_unsigned(0,22);
for i in 8 downto 1 loop
vsh_reg(i) := rsh_reg(i-1);
end loop;
vsh_reg(0) := unsigned(in_data(7 downto 0));
for i in 0 to 9 loop
vout_data := vout_data + rmul(i);
end loop;
in_data_read <= '0';
out_data_write <= '0';
case pstate is
when idle =>
if start='1' then
nstate <= running;
else
nstate <= idle;
vdcount := (others=>'0');
end if;
when running =>
if vdcount=std_logic_vector(to_unsigned(102,9)) then
nstate<=idle;
in_data_read <= '0';
else
nstate<=running;
in_data_read <= '1';
end if;
if vdcount>=std_logic_vector(to_unsigned(12,9)) then --9+2latency
out_data_write <= '1';
end if;
end case;
if pstate/= idle then
vdcount := vdcount+1;
end if;
sh_reg <= vsh_reg;
rout_data(21 downto 0) <= std_logic_vector(vout_data);
dcount <= vdcount;
end process;
reg: process(clk,rst)
begin
if (rst='1') then
for i in 0 to 8 loop
rsh_reg(i) <= (others=>'0');
end loop;
for i in 0 to 9 loop
rmul(i) <= (others=>'0');
end loop;
out_data <= (others=>'0');
rdcount <= (others=>'0');
pstate <= idle;
elsif rising_edge(clk) then
rsh_reg <= sh_reg;
rmul <= mul;
out_data <= "0000000000"&rout_data;
rdcount <= dcount;
pstate <= nstate;
end if;
end process;
mul_gen: for i in 1 to 9 generate
mul(i) <= rsh_reg(i-1) * coeff(i);
end generate;
mul(0) <= unsigned(in_data(7 downto 0))*coeff(0);
end fir_rtl;
|
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: fir
-- File: fir_v1.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: FIR filter core (version 1) -- for dprc demo
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity fir is
port (
clk : in std_ulogic;
rst : in std_ulogic;
start : in std_ulogic;
in_data : in std_logic_vector(31 downto 0);
in_data_read : out std_ulogic;
out_data : out std_logic_vector (31 downto 0);
out_data_write : out std_ulogic);
end fir;
architecture fir_rtl of fir is
type fsm_state is (idle, running);
signal pstate, nstate : fsm_state;
type sh_reg_type is array (0 to 8) of unsigned(7 downto 0);
signal sh_reg, rsh_reg : sh_reg_type;
type mul_type is array (0 to 9) of unsigned(15 downto 0);
signal mul, rmul : mul_type;
signal rout_data : std_logic_vector(21 downto 0);
signal dcount, rdcount : std_logic_vector(8 downto 0);
type coeffT is array (0 to 9) of unsigned(7 downto 0);
constant coeff : coeffT := (to_unsigned(21,8),to_unsigned(23,8),to_unsigned(21,8),to_unsigned(19,8),to_unsigned(13,8),to_unsigned(9,8),to_unsigned(13,8),to_unsigned(15,8),to_unsigned(21,8),to_unsigned(17,8));
begin
comb: process(rsh_reg, rmul, start, pstate, rdcount, in_data)
variable vsh_reg : sh_reg_type;
variable vout_data : unsigned(21 downto 0);
variable start_flag : std_ulogic;
variable vdcount : std_logic_vector(8 downto 0);
begin
vdcount := rdcount;
vout_data := to_unsigned(0,22);
for i in 8 downto 1 loop
vsh_reg(i) := rsh_reg(i-1);
end loop;
vsh_reg(0) := unsigned(in_data(7 downto 0));
for i in 0 to 9 loop
vout_data := vout_data + rmul(i);
end loop;
in_data_read <= '0';
out_data_write <= '0';
case pstate is
when idle =>
if start='1' then
nstate <= running;
else
nstate <= idle;
vdcount := (others=>'0');
end if;
when running =>
if vdcount=std_logic_vector(to_unsigned(102,9)) then
nstate<=idle;
in_data_read <= '0';
else
nstate<=running;
in_data_read <= '1';
end if;
if vdcount>=std_logic_vector(to_unsigned(12,9)) then --9+2latency
out_data_write <= '1';
end if;
end case;
if pstate/= idle then
vdcount := vdcount+1;
end if;
sh_reg <= vsh_reg;
rout_data(21 downto 0) <= std_logic_vector(vout_data);
dcount <= vdcount;
end process;
reg: process(clk,rst)
begin
if (rst='1') then
for i in 0 to 8 loop
rsh_reg(i) <= (others=>'0');
end loop;
for i in 0 to 9 loop
rmul(i) <= (others=>'0');
end loop;
out_data <= (others=>'0');
rdcount <= (others=>'0');
pstate <= idle;
elsif rising_edge(clk) then
rsh_reg <= sh_reg;
rmul <= mul;
out_data <= "0000000000"&rout_data;
rdcount <= dcount;
pstate <= nstate;
end if;
end process;
mul_gen: for i in 1 to 9 generate
mul(i) <= rsh_reg(i-1) * coeff(i);
end generate;
mul(0) <= unsigned(in_data(7 downto 0))*coeff(0);
end fir_rtl;
|
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: fir
-- File: fir_v1.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: FIR filter core (version 1) -- for dprc demo
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity fir is
port (
clk : in std_ulogic;
rst : in std_ulogic;
start : in std_ulogic;
in_data : in std_logic_vector(31 downto 0);
in_data_read : out std_ulogic;
out_data : out std_logic_vector (31 downto 0);
out_data_write : out std_ulogic);
end fir;
architecture fir_rtl of fir is
type fsm_state is (idle, running);
signal pstate, nstate : fsm_state;
type sh_reg_type is array (0 to 8) of unsigned(7 downto 0);
signal sh_reg, rsh_reg : sh_reg_type;
type mul_type is array (0 to 9) of unsigned(15 downto 0);
signal mul, rmul : mul_type;
signal rout_data : std_logic_vector(21 downto 0);
signal dcount, rdcount : std_logic_vector(8 downto 0);
type coeffT is array (0 to 9) of unsigned(7 downto 0);
constant coeff : coeffT := (to_unsigned(21,8),to_unsigned(23,8),to_unsigned(21,8),to_unsigned(19,8),to_unsigned(13,8),to_unsigned(9,8),to_unsigned(13,8),to_unsigned(15,8),to_unsigned(21,8),to_unsigned(17,8));
begin
comb: process(rsh_reg, rmul, start, pstate, rdcount, in_data)
variable vsh_reg : sh_reg_type;
variable vout_data : unsigned(21 downto 0);
variable start_flag : std_ulogic;
variable vdcount : std_logic_vector(8 downto 0);
begin
vdcount := rdcount;
vout_data := to_unsigned(0,22);
for i in 8 downto 1 loop
vsh_reg(i) := rsh_reg(i-1);
end loop;
vsh_reg(0) := unsigned(in_data(7 downto 0));
for i in 0 to 9 loop
vout_data := vout_data + rmul(i);
end loop;
in_data_read <= '0';
out_data_write <= '0';
case pstate is
when idle =>
if start='1' then
nstate <= running;
else
nstate <= idle;
vdcount := (others=>'0');
end if;
when running =>
if vdcount=std_logic_vector(to_unsigned(102,9)) then
nstate<=idle;
in_data_read <= '0';
else
nstate<=running;
in_data_read <= '1';
end if;
if vdcount>=std_logic_vector(to_unsigned(12,9)) then --9+2latency
out_data_write <= '1';
end if;
end case;
if pstate/= idle then
vdcount := vdcount+1;
end if;
sh_reg <= vsh_reg;
rout_data(21 downto 0) <= std_logic_vector(vout_data);
dcount <= vdcount;
end process;
reg: process(clk,rst)
begin
if (rst='1') then
for i in 0 to 8 loop
rsh_reg(i) <= (others=>'0');
end loop;
for i in 0 to 9 loop
rmul(i) <= (others=>'0');
end loop;
out_data <= (others=>'0');
rdcount <= (others=>'0');
pstate <= idle;
elsif rising_edge(clk) then
rsh_reg <= sh_reg;
rmul <= mul;
out_data <= "0000000000"&rout_data;
rdcount <= dcount;
pstate <= nstate;
end if;
end process;
mul_gen: for i in 1 to 9 generate
mul(i) <= rsh_reg(i-1) * coeff(i);
end generate;
mul(0) <= unsigned(in_data(7 downto 0))*coeff(0);
end fir_rtl;
|
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: fir
-- File: fir_v1.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: FIR filter core (version 1) -- for dprc demo
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity fir is
port (
clk : in std_ulogic;
rst : in std_ulogic;
start : in std_ulogic;
in_data : in std_logic_vector(31 downto 0);
in_data_read : out std_ulogic;
out_data : out std_logic_vector (31 downto 0);
out_data_write : out std_ulogic);
end fir;
architecture fir_rtl of fir is
type fsm_state is (idle, running);
signal pstate, nstate : fsm_state;
type sh_reg_type is array (0 to 8) of unsigned(7 downto 0);
signal sh_reg, rsh_reg : sh_reg_type;
type mul_type is array (0 to 9) of unsigned(15 downto 0);
signal mul, rmul : mul_type;
signal rout_data : std_logic_vector(21 downto 0);
signal dcount, rdcount : std_logic_vector(8 downto 0);
type coeffT is array (0 to 9) of unsigned(7 downto 0);
constant coeff : coeffT := (to_unsigned(21,8),to_unsigned(23,8),to_unsigned(21,8),to_unsigned(19,8),to_unsigned(13,8),to_unsigned(9,8),to_unsigned(13,8),to_unsigned(15,8),to_unsigned(21,8),to_unsigned(17,8));
begin
comb: process(rsh_reg, rmul, start, pstate, rdcount, in_data)
variable vsh_reg : sh_reg_type;
variable vout_data : unsigned(21 downto 0);
variable start_flag : std_ulogic;
variable vdcount : std_logic_vector(8 downto 0);
begin
vdcount := rdcount;
vout_data := to_unsigned(0,22);
for i in 8 downto 1 loop
vsh_reg(i) := rsh_reg(i-1);
end loop;
vsh_reg(0) := unsigned(in_data(7 downto 0));
for i in 0 to 9 loop
vout_data := vout_data + rmul(i);
end loop;
in_data_read <= '0';
out_data_write <= '0';
case pstate is
when idle =>
if start='1' then
nstate <= running;
else
nstate <= idle;
vdcount := (others=>'0');
end if;
when running =>
if vdcount=std_logic_vector(to_unsigned(102,9)) then
nstate<=idle;
in_data_read <= '0';
else
nstate<=running;
in_data_read <= '1';
end if;
if vdcount>=std_logic_vector(to_unsigned(12,9)) then --9+2latency
out_data_write <= '1';
end if;
end case;
if pstate/= idle then
vdcount := vdcount+1;
end if;
sh_reg <= vsh_reg;
rout_data(21 downto 0) <= std_logic_vector(vout_data);
dcount <= vdcount;
end process;
reg: process(clk,rst)
begin
if (rst='1') then
for i in 0 to 8 loop
rsh_reg(i) <= (others=>'0');
end loop;
for i in 0 to 9 loop
rmul(i) <= (others=>'0');
end loop;
out_data <= (others=>'0');
rdcount <= (others=>'0');
pstate <= idle;
elsif rising_edge(clk) then
rsh_reg <= sh_reg;
rmul <= mul;
out_data <= "0000000000"&rout_data;
rdcount <= dcount;
pstate <= nstate;
end if;
end process;
mul_gen: for i in 1 to 9 generate
mul(i) <= rsh_reg(i-1) * coeff(i);
end generate;
mul(0) <= unsigned(in_data(7 downto 0))*coeff(0);
end fir_rtl;
|
--!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity idiv53 is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_divident : in std_logic_vector(52 downto 0);
i_divisor : in std_logic_vector(52 downto 0);
o_result : out std_logic_vector(104 downto 0);
o_lshift : out std_logic_vector(6 downto 0);
o_rdy : out std_logic;
o_overflow : out std_logic;
o_zero_resid : out std_logic
);
end;
architecture arch_idiv53 of idiv53 is
constant zero53 : std_logic_vector(52 downto 0) := (others => '0');
component divstage53 is
port (
i_mux_ena : in std_logic; -- find first non-zero bit
i_muxind : in std_logic_vector(55 downto 0); -- bits indexes 8x7 bits bus
i_divident : in std_logic_vector(60 downto 0); -- integer value
i_divisor : in std_logic_vector(52 downto 0); -- integer value
o_dif : out std_logic_vector(52 downto 0); -- residual value
o_bits : out std_logic_vector(7 downto 0); -- resulting bits
o_muxind : out std_logic_vector(6 downto 0); -- first found non-zero bit
o_muxind_rdy : out std_logic -- seeking was successfull
);
end component;
type RegistersType is record
delay : std_logic_vector(14 downto 0);
lshift : std_logic_vector(6 downto 0);
lshift_rdy : std_logic;
divisor : std_logic_vector(52 downto 0);
divident : std_logic_vector(60 downto 0);
bits : std_logic_vector(104 downto 0);
overflow : std_logic;
zero_resid : std_logic;
end record;
constant R_RESET : RegistersType := (
(others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'),
'0', '0');
signal r, rin : RegistersType;
signal w_mux_ena_i : std_logic;
signal wb_muxind_i : std_logic_vector(55 downto 0);
signal wb_divident_i : std_logic_vector(60 downto 0);
signal wb_divisor_i : std_logic_vector(52 downto 0);
signal wb_dif_o : std_logic_vector(52 downto 0);
signal wb_bits_o : std_logic_vector(7 downto 0);
signal wb_muxind_o : std_logic_vector(6 downto 0);
signal w_muxind_rdy_o : std_logic;
begin
divstage0 : divstage53 port map (
i_mux_ena => w_mux_ena_i,
i_muxind => wb_muxind_i,
i_divident => wb_divident_i,
i_divisor => wb_divisor_i,
o_dif => wb_dif_o,
o_bits => wb_bits_o,
o_muxind => wb_muxind_o,
o_muxind_rdy => w_muxind_rdy_o
);
-- registers:
comb : process(i_nrst, i_ena, i_divident, i_divisor, r,
wb_dif_o, wb_bits_o, wb_muxind_o, w_muxind_rdy_o)
variable v : RegistersType;
variable vb_muxind : std_logic_vector(55 downto 0);
variable vb_bits : std_logic_vector(104 downto 0);
variable v_mux_ena_i : std_logic;
begin
v := r;
vb_bits := r.bits;
v_mux_ena_i := '0';
v.delay := r.delay(13 downto 0) & i_ena;
vb_muxind := (others => '0');
if i_ena = '1' then
v.divident := X"00" & i_divident;
v.divisor := i_divisor;
v.lshift_rdy := '0';
v.overflow := '0';
v.zero_resid := '0';
elsif r.delay(0) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_bits(104) := not wb_dif_o(52);
elsif r.delay(1) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(1, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(2, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(3, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(4, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(5, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(6, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(7, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(8, 7);
vb_bits(103 downto 96) := wb_bits_o;
elsif r.delay(2) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(9, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(10, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(11, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(12, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(13, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(14, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(15, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(16, 7);
vb_bits(95 downto 88) := wb_bits_o;
elsif r.delay(3) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(17, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(18, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(19, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(20, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(21, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(22, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(23, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(24, 7);
vb_bits(87 downto 80) := wb_bits_o;
elsif r.delay(4) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(25, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(26, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(27, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(28, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(29, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(30, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(31, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(32, 7);
vb_bits(79 downto 72) := wb_bits_o;
elsif r.delay(5) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(33, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(34, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(35, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(36, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(37, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(38, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(39, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(40, 7);
vb_bits(71 downto 64) := wb_bits_o;
elsif r.delay(6) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(41, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(42, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(43, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(44, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(45, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(46, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(47, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(48, 7);
vb_bits(63 downto 56) := wb_bits_o;
elsif r.delay(7) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(49, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(50, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(51, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(52, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(53, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(54, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(55, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(56, 7);
vb_bits(55 downto 48) := wb_bits_o;
elsif r.delay(8) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(57, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(58, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(59, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(60, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(61, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(62, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(63, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(64, 7);
vb_bits(47 downto 40) := wb_bits_o;
elsif r.delay(9) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(65, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(66, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(67, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(68, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(69, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(70, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(71, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(72, 7);
vb_bits(39 downto 32) := wb_bits_o;
elsif r.delay(10) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(73, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(74, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(75, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(76, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(77, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(78, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(79, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(80, 7);
vb_bits(31 downto 24) := wb_bits_o;
elsif r.delay(11) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(81, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(82, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(83, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(84, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(85, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(86, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(87, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(88, 7);
vb_bits(23 downto 16) := wb_bits_o;
elsif r.delay(12) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(89, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(90, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(91, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(92, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(93, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(94, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(95, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(96, 7);
vb_bits(15 downto 8) := wb_bits_o;
elsif r.delay(13) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(97, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(98, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(99, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(100, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(101, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(102, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(103, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(104, 7);
vb_bits(7 downto 0) := wb_bits_o;
if wb_dif_o = zero53 then
v.zero_resid := '1';
end if;
if r.lshift = "1111111" then
v.overflow := '1';
end if;
end if;
if r.lshift_rdy = '0' then
if w_muxind_rdy_o = '1' then
v.lshift_rdy := '1';
v.lshift := wb_muxind_o;
elsif r.delay(13) = '1' then
v.lshift_rdy := '1';
v.lshift := conv_std_logic_vector(104, 7);
end if;
end if;
w_mux_ena_i <= v_mux_ena_i;
wb_divident_i <= r.divident;
wb_divisor_i <= r.divisor;
wb_muxind_i <= vb_muxind;
v.bits := vb_bits;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
end process;
o_result <= r.bits;
o_lshift <= r.lshift;
o_overflow <= r.overflow;
o_zero_resid <= r.zero_resid;
o_rdy <= r.delay(14);
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
|
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Paris Moschovakos
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--
-- global reset
-- -----
-- ENA ------- --------
-- ---------
-- WEN ----- ------
--
-- IEEE VHDL standard library:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_bit.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity vmm_global_reset is
port( clk : in std_logic; -- 100MHz
rst : in std_logic; -- reset
gbl_rst : in std_logic ; -- from control register. a pulse
vmm_ena : out std_logic ; -- these will be ored with same from other sm
vmm_wen : out std_logic -- these will be ored with same from other sm
);
end vmm_global_reset ;
architecture beh of vmm_global_reset is
signal state_switch_count : std_logic_vector(31 downto 0) := x"00010000"; --fast
signal cfg_rst_ctr : std_logic_vector(31 downto 0) := x"00000000";
signal state_nxt : std_logic_vector(2 downto 0) ;
signal vmm_wen_int, vmm_ena_int : std_logic ;
signal gbl_rst_int, done_int : std_logic ;
attribute keep: boolean;
attribute keep of vmm_ena_int: signal is true;
attribute keep of vmm_wen_int: signal is true;
attribute keep of cfg_rst_ctr: signal is true;
begin
process( clk, rst, done_int, gbl_rst, gbl_rst_int)
begin
if( rst = '1' or done_int = '1') then
gbl_rst_int <= '0' ;
else
if( rising_edge( clk)) then --100MHz
if (gbl_rst = '1') then
gbl_rst_int <= '1' ;
end if ;
end if ;
end if ;
end process ;
process( clk, state_nxt, rst, gbl_rst_int, vmm_ena_int, vmm_wen_int)
begin
if ( rising_edge( clk)) then --100MHz
if (rst = '1') then
state_nxt <= (others=>'0') ;
done_int <= '0' ;
vmm_ena_int <= '0' ;
vmm_wen_int <= '0' ;
cfg_rst_ctr <= (others=>'0') ;
else
case state_nxt is
when "000" =>
vmm_wen_int <= '0' ;
vmm_ena_int <= '0' ;
done_int <= '0' ;
if (gbl_rst_int = '1') then
state_nxt <= "001" ;
cfg_rst_ctr <= (others=>'0') ;
else
state_nxt <= "000" ;
end if ;
when "001" =>
vmm_ena_int <= '0' ;
vmm_wen_int <= '1' ;
if (cfg_rst_ctr = state_switch_count) then
state_nxt <= "010" ;
cfg_rst_ctr <= (others=>'0') ;
else
state_nxt <= "001" ;
cfg_rst_ctr <= cfg_rst_ctr + '1';
end if ;
when "010" =>
vmm_ena_int <= '1' ;
vmm_wen_int <= '1' ;
if (cfg_rst_ctr = state_switch_count) then
state_nxt <= "011" ;
cfg_rst_ctr <= (others=>'0') ;
else
state_nxt <= "010" ;
cfg_rst_ctr <= cfg_rst_ctr + '1';
end if ;
when "011" =>
vmm_ena_int <= '0' ;
vmm_wen_int <= '1' ;
if (cfg_rst_ctr = state_switch_count) then
state_nxt <= "100" ;
cfg_rst_ctr <= (others=>'0') ;
else
state_nxt <= "011" ;
cfg_rst_ctr <= cfg_rst_ctr + '1';
end if ;
when "100" =>
vmm_ena_int <= '0' ;
vmm_wen_int <= '0' ;
state_nxt <= "000" ;
done_int <= '1' ;
when others => vmm_ena_int <= '0' ;
vmm_wen_int <= '0' ;
done_int <= '1' ;
state_nxt <= (others=>'0') ;
end case ;
end if ;
end if;
end process ;
vmm_wen <= vmm_wen_int ;
vmm_ena <= vmm_ena_int ;
end beh ;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 7;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component feedforward_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_ddiv_29_no_dsp_64_u : component feedforward_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 7;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component feedforward_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_ddiv_29_no_dsp_64_u : component feedforward_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 7;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component feedforward_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_ddiv_29_no_dsp_64_u : component feedforward_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 7;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component feedforward_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_ddiv_29_no_dsp_64_u : component feedforward_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
entity top is
port( clk : in std_logic;
reset : in std_logic;
led : out std_logic);
end top;
architecture rtl of top is
component clk_gen is
generic( CLOCK_SPEED : integer := 50_000_000;
REQUIRED_HZ : integer := 1);
port( clk : in std_logic;
reset : in std_logic;
clk_out : out std_logic);
end component;
constant CLK_HZ : integer := 50_000_000;
signal hz_clk : std_logic;
signal led_s : std_logic;
begin
gen_1hz_clk : clk_gen
generic map (REQUIRED_HZ => CLK_HZ / 2)
port map (clk, reset, hz_clk);
combinatoral:
process(led_s)
begin
led <= led_s;
end process;
sequential:
process(hz_clk, reset)
begin
if reset = '1' then
led_s <= '0';
elsif rising_edge(hz_clk) then
if led_s = '1' then
led_s <= '0';
else
led_s <= '1';
end if;
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AuxPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
entity tb_Cell is
end tb_Cell;
architecture arch of tb_Cell is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, add, shift);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT signals
signal ClrxAB : std_logic := '1';
signal CExE : std_logic := '1';
signal Cfg : cellConfigRec;
signal ContextxS : std_logic_vector(CNTXTWIDTH-1 downto 0) := (others => '0');
signal In0xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In1xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In2xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In3xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In4xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In5xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In6xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal In7xD : std_logic_vector(DATAWIDTH-1 downto 0);
signal OutxD : std_logic_vector(DATAWIDTH-1 downto 0);
signal Out0xZ : std_logic_vector(DATAWIDTH-1 downto 0);
signal Out1xZ : std_logic_vector(DATAWIDTH-1 downto 0);
signal Out2xZ : std_logic_vector(DATAWIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : Cell
generic map (
DATAWIDTH => DATAWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrxABI => ClrxAB,
CExEI => CExE,
ConfigxI => Cfg,
ContextxSI => ContextxS,
In0xDI => In0xD,
In1xDI => In1xD,
In2xDI => In2xD,
In3xDI => In3xD,
In4xDI => In4xD,
In5xDI => In5xD,
In6xDI => In6xD,
In7xDI => In7xD,
OutxDO => OutxD,
Out0xZO => Out0xZ,
Out1xZO => Out1xZ,
Out2xZO => Out2xZ);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
In0xD <= std_logic_vector(to_unsigned(01, DATAWIDTH));
In1xD <= std_logic_vector(to_unsigned(10, DATAWIDTH));
In2xD <= std_logic_vector(to_unsigned(20, DATAWIDTH));
In3xD <= std_logic_vector(to_unsigned(30, DATAWIDTH));
In4xD <= std_logic_vector(to_unsigned(40, DATAWIDTH));
In5xD <= std_logic_vector(to_unsigned(50, DATAWIDTH));
In6xD <= std_logic_vector(to_unsigned(60, DATAWIDTH));
In7xD <= std_logic_vector(to_unsigned(70, DATAWIDTH));
tbStatus <= rst;
Cfg <= init_cellConfig;
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= add;
Cfg.routConf.Route0MuxS <= "011";
Cfg.routConf.Route1MuxS <= "110";
Cfg.routConf.Tri0OExE <= '1';
Cfg.routConf.Tri1OExE <= '1';
Cfg.routConf.Tri2OExE <= '1';
Cfg.procConf.Op0MuxS <= "00";
Cfg.procConf.Op1MuxS <= "00";
Cfg.procConf.OutMuxS <= '0';
Cfg.procConf.AluOpxS <= alu_addu;
Cfg.procConf.ConstOpxD <= std_logic_vector(to_unsigned(0, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_cellConfig;
wait for CLK_PERIOD;
tbStatus <= shift;
Cfg.routConf.Route0MuxS <= "010";
Cfg.routConf.Route1MuxS <= "000";
Cfg.routConf.Tri0OExE <= '1';
Cfg.routConf.Tri1OExE <= '0';
Cfg.routConf.Tri2OExE <= '1';
Cfg.procConf.Op0MuxS <= "00";
Cfg.procConf.Op1MuxS <= "10";
Cfg.procConf.OutMuxS <= '0';
Cfg.procConf.AluOpxS <= alu_sll;
Cfg.procConf.ConstOpxD <= std_logic_vector(to_unsigned(2, DATAWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
Cfg <= init_cellConfig;
wait for CLK_PERIOD*2;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a_e
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:55:45 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\io.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-conf-c.vhd,v 1.1 2004/04/06 11:04:58 wig Exp $
-- $Date: 2004/04/06 11:04:58 $
-- $Log: inst_a_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 11:04:58 wig
-- Adding result/io
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.17 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_a_e_rtl_conf / inst_a_e
--
configuration inst_a_e_rtl_conf of inst_a_e is
for rtl
-- Generated Configuration
for inst_aa : inst_aa_e
use configuration work.inst_aa_e_rtl_conf;
end for;
for inst_ab : inst_ab_e
use configuration work.inst_ab_e_rtl_conf;
end for;
for inst_ac : inst_ac_e
use configuration work.inst_ac_e_rtl_conf;
end for;
end for;
end inst_a_e_rtl_conf;
--
-- End of Generated Configuration inst_a_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc372.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n02i00372ent IS
END c03s02b01x01p03n02i00372ent;
ARCHITECTURE c03s02b01x01p03n02i00372arch OF c03s02b01x01p03n02i00372ent IS
subtype BFALSE is BOOLEAN range FALSE to FALSE;
type ONETWO is range 1 to 2;
type A5 is array (FALSE to FALSE,
BFALSE range <>,
1 to 2) of BIT; -- Failure_here
-- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
-- CANNOT BE MIXED
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p03n02i00372 - Unconstrained and constrained index ranges cannot be mixed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n02i00372arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc372.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n02i00372ent IS
END c03s02b01x01p03n02i00372ent;
ARCHITECTURE c03s02b01x01p03n02i00372arch OF c03s02b01x01p03n02i00372ent IS
subtype BFALSE is BOOLEAN range FALSE to FALSE;
type ONETWO is range 1 to 2;
type A5 is array (FALSE to FALSE,
BFALSE range <>,
1 to 2) of BIT; -- Failure_here
-- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
-- CANNOT BE MIXED
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p03n02i00372 - Unconstrained and constrained index ranges cannot be mixed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n02i00372arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc372.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n02i00372ent IS
END c03s02b01x01p03n02i00372ent;
ARCHITECTURE c03s02b01x01p03n02i00372arch OF c03s02b01x01p03n02i00372ent IS
subtype BFALSE is BOOLEAN range FALSE to FALSE;
type ONETWO is range 1 to 2;
type A5 is array (FALSE to FALSE,
BFALSE range <>,
1 to 2) of BIT; -- Failure_here
-- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
-- CANNOT BE MIXED
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p03n02i00372 - Unconstrained and constrained index ranges cannot be mixed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n02i00372arch;
|
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <[email protected]>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: F function
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity F is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end F;
architecture RTL of F is
-- S-BOX
component SBOX1 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX2 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX3 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX4 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
signal y : STD_LOGIC_VECTOR (0 to 63);
signal y1, y2, y3, y4, y5, y6, y7, y8 : STD_LOGIC_VECTOR (0 to 7);
signal so1, so2, so3, so4, so5, so6, so7, so8 : STD_LOGIC_VECTOR (0 to 7);
signal pa1, pa2, pa3, pa4, pa5, pa6, pa7, pa8 : STD_LOGIC_VECTOR (0 to 7);
signal pb1, pb2, pb3, pb4, pb5, pb6, pb7, pb8 : STD_LOGIC_VECTOR (0 to 7);
begin
y <= x xor k;
y8 <= y(56 to 63);
y7 <= y(48 to 55);
y6 <= y(40 to 47);
y5 <= y(32 to 39);
y4 <= y(24 to 31);
y3 <= y(16 to 23);
y2 <= y(8 to 15);
y1 <= y(0 to 7);
-- S-FUNCTION
S1 : SBOX1
port map(clk, y8, y1, so8, so1);
S2 : SBOX2
port map(clk, y5, y2, so5, so2);
S3 : SBOX3
port map(clk, y6, y3, so6, so3);
S4 : SBOX4
port map(clk, y7, y4, so7, so4);
-- P-FUNCTION
pa8 <= so8 xor pa2;
pa7 <= so7 xor pa1;
pa6 <= so6 xor pa4;
pa5 <= so5 xor pa3;
pa4 <= so4 xor so5;
pa3 <= so3 xor so8;
pa2 <= so2 xor so7;
pa1 <= so1 xor so6;
pb8 <= pa8 xor pb3;
pb7 <= pa7 xor pb2;
pb6 <= pa6 xor pb1;
pb5 <= pa5 xor pb4;
pb4 <= pa4 xor pa7;
pb3 <= pa3 xor pa6;
pb2 <= pa2 xor pa5;
pb1 <= pa1 xor pa8;
z <= pb5 & pb6 & pb7 & pb8 & pb1 & pb2 & pb3 & pb4;
end RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_rx is
end entity;
architecture tb of tb_ulpi_rx is
signal clock : std_logic := '0';
signal reset : std_logic;
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_last : std_logic := '0';
signal rx_valid : std_logic := '0';
signal rx_store : std_logic := '0';
signal pid : std_logic_vector(3 downto 0);
signal valid_token : std_logic;
signal token : std_logic_vector(10 downto 0);
signal valid_packet : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal data_valid : std_logic;
signal data_start : std_logic;
signal error : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_rx: entity work.ulpi_rx
port map (
clock => clock,
reset => reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => pid,
valid_token => valid_token,
token => token,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => error );
process
procedure packet(pkt : t_std_logic_8_vector) is
begin
for i in pkt'range loop
wait until clock='1';
rx_data <= pkt(i);
rx_valid <= '1';
rx_store <= '1';
if i = pkt'right then
rx_last <= '1';
else
rx_last <= '0';
end if;
end loop;
wait until clock='1';
rx_valid <= '0';
rx_last <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
end procedure packet;
begin
wait until reset='0';
wait until clock='1';
packet((X"A5", X"63", X"A9"));
packet((X"4B", X"00", X"00")); -- data1, length=0, crc = 0000
packet((X"C3", X"00", X"01", X"02", X"03", X"04", X"05", X"06",
X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", X"0E",
X"0F", X"10", X"19", X"44")); -- good crc
packet((X"C3", X"00", X"01", X"02", X"03", X"04", X"05", X"06",
X"07", X"08", X"09", X"03", X"0B", X"0C", X"0D", X"0E",
X"0F", X"10", X"19", X"44")); -- bad crc
packet((0=>X"D2")); -- good handshake
packet((0=>X"C3")); -- bad handshake (wrong pid data)
packet((0=>X"A5")); -- bad handshake (wrong pid token)
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_rx is
end entity;
architecture tb of tb_ulpi_rx is
signal clock : std_logic := '0';
signal reset : std_logic;
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_last : std_logic := '0';
signal rx_valid : std_logic := '0';
signal rx_store : std_logic := '0';
signal pid : std_logic_vector(3 downto 0);
signal valid_token : std_logic;
signal token : std_logic_vector(10 downto 0);
signal valid_packet : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal data_valid : std_logic;
signal data_start : std_logic;
signal error : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_rx: entity work.ulpi_rx
port map (
clock => clock,
reset => reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => pid,
valid_token => valid_token,
token => token,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => error );
process
procedure packet(pkt : t_std_logic_8_vector) is
begin
for i in pkt'range loop
wait until clock='1';
rx_data <= pkt(i);
rx_valid <= '1';
rx_store <= '1';
if i = pkt'right then
rx_last <= '1';
else
rx_last <= '0';
end if;
end loop;
wait until clock='1';
rx_valid <= '0';
rx_last <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
end procedure packet;
begin
wait until reset='0';
wait until clock='1';
packet((X"A5", X"63", X"A9"));
packet((X"4B", X"00", X"00")); -- data1, length=0, crc = 0000
packet((X"C3", X"00", X"01", X"02", X"03", X"04", X"05", X"06",
X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", X"0E",
X"0F", X"10", X"19", X"44")); -- good crc
packet((X"C3", X"00", X"01", X"02", X"03", X"04", X"05", X"06",
X"07", X"08", X"09", X"03", X"0B", X"0C", X"0D", X"0E",
X"0F", X"10", X"19", X"44")); -- bad crc
packet((0=>X"D2")); -- good handshake
packet((0=>X"C3")); -- bad handshake (wrong pid data)
packet((0=>X"A5")); -- bad handshake (wrong pid token)
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_rx is
end entity;
architecture tb of tb_ulpi_rx is
signal clock : std_logic := '0';
signal reset : std_logic;
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_last : std_logic := '0';
signal rx_valid : std_logic := '0';
signal rx_store : std_logic := '0';
signal pid : std_logic_vector(3 downto 0);
signal valid_token : std_logic;
signal token : std_logic_vector(10 downto 0);
signal valid_packet : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal data_valid : std_logic;
signal data_start : std_logic;
signal error : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_rx: entity work.ulpi_rx
port map (
clock => clock,
reset => reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => pid,
valid_token => valid_token,
token => token,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => error );
process
procedure packet(pkt : t_std_logic_8_vector) is
begin
for i in pkt'range loop
wait until clock='1';
rx_data <= pkt(i);
rx_valid <= '1';
rx_store <= '1';
if i = pkt'right then
rx_last <= '1';
else
rx_last <= '0';
end if;
end loop;
wait until clock='1';
rx_valid <= '0';
rx_last <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
end procedure packet;
begin
wait until reset='0';
wait until clock='1';
packet((X"A5", X"63", X"A9"));
packet((X"4B", X"00", X"00")); -- data1, length=0, crc = 0000
packet((X"C3", X"00", X"01", X"02", X"03", X"04", X"05", X"06",
X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", X"0E",
X"0F", X"10", X"19", X"44")); -- good crc
packet((X"C3", X"00", X"01", X"02", X"03", X"04", X"05", X"06",
X"07", X"08", X"09", X"03", X"0B", X"0C", X"0D", X"0E",
X"0F", X"10", X"19", X"44")); -- bad crc
packet((0=>X"D2")); -- good handshake
packet((0=>X"C3")); -- bad handshake (wrong pid data)
packet((0=>X"A5")); -- bad handshake (wrong pid token)
wait;
end process;
end tb;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axis_accelerator_adapter:2.1
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axis_accelerator_adapter_v2_1_6;
USE axis_accelerator_adapter_v2_1_6.axis_accelerator_adapter;
ENTITY zc702_get_0_if_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : OUT STD_LOGIC;
ap_start : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_continue : OUT STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_iscalar_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_1_vld : IN STD_LOGIC;
interrupt : OUT STD_LOGIC
);
END zc702_get_0_if_0;
ARCHITECTURE zc702_get_0_if_0_arch OF zc702_get_0_if_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_get_0_if_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_accelerator_adapter IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_AP_ADAPTER_ID : INTEGER;
C_N_INPUT_ARGS : INTEGER;
C_N_OUTPUT_ARGS : INTEGER;
C_S_AXIS_TDATA_WIDTH : INTEGER;
C_S_AXIS_TUSER_WIDTH : INTEGER;
C_S_AXIS_TID_WIDTH : INTEGER;
C_S_AXIS_TDEST_WIDTH : INTEGER;
C_AP_IARG_TYPE : STD_LOGIC_VECTOR;
C_AP_IARG_MB_DEPTH : STD_LOGIC_VECTOR;
C_AP_IARG_WIDTH : STD_LOGIC_VECTOR;
C_AP_IARG_N_DIM : STD_LOGIC_VECTOR;
C_AP_IARG_DIM_1 : STD_LOGIC_VECTOR;
C_AP_IARG_DIM_2 : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_TYPE : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_FACTOR : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_DIM : STD_LOGIC_VECTOR;
C_AP_IARG_0_DWIDTH : INTEGER;
C_AP_IARG_1_DWIDTH : INTEGER;
C_AP_IARG_2_DWIDTH : INTEGER;
C_AP_IARG_3_DWIDTH : INTEGER;
C_AP_IARG_4_DWIDTH : INTEGER;
C_AP_IARG_5_DWIDTH : INTEGER;
C_AP_IARG_6_DWIDTH : INTEGER;
C_AP_IARG_7_DWIDTH : INTEGER;
C_M_AXIS_TDATA_WIDTH : INTEGER;
C_M_AXIS_TUSER_WIDTH : INTEGER;
C_M_AXIS_TID_WIDTH : INTEGER;
C_M_AXIS_TDEST_WIDTH : INTEGER;
C_AP_OARG_TYPE : STD_LOGIC_VECTOR;
C_AP_OARG_MB_DEPTH : STD_LOGIC_VECTOR;
C_AP_OARG_WIDTH : STD_LOGIC_VECTOR;
C_AP_OARG_N_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_DIM_1 : STD_LOGIC_VECTOR;
C_AP_OARG_DIM_2 : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_TYPE : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_FACTOR : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_0_DWIDTH : INTEGER;
C_AP_OARG_1_DWIDTH : INTEGER;
C_AP_OARG_2_DWIDTH : INTEGER;
C_AP_OARG_3_DWIDTH : INTEGER;
C_AP_OARG_4_DWIDTH : INTEGER;
C_AP_OARG_5_DWIDTH : INTEGER;
C_AP_OARG_6_DWIDTH : INTEGER;
C_AP_OARG_7_DWIDTH : INTEGER;
C_N_INOUT_SCALARS : INTEGER;
C_N_INPUT_SCALARS : INTEGER;
C_INPUT_SCALAR_DWIDTH : STD_LOGIC_VECTOR;
C_INPUT_SCALAR_MODE : STD_LOGIC_VECTOR;
C_OUTPUT_SCALAR_MODE : STD_LOGIC_VECTOR;
C_AP_ISCALAR_DOUT_WIDTH : INTEGER;
C_AP_ISCALAR_IO_DOUT_WIDTH : INTEGER;
C_INPUT_SCALAR_0_WIDTH : INTEGER;
C_INPUT_SCALAR_1_WIDTH : INTEGER;
C_INPUT_SCALAR_2_WIDTH : INTEGER;
C_INPUT_SCALAR_3_WIDTH : INTEGER;
C_INPUT_SCALAR_4_WIDTH : INTEGER;
C_INPUT_SCALAR_5_WIDTH : INTEGER;
C_INPUT_SCALAR_6_WIDTH : INTEGER;
C_INPUT_SCALAR_7_WIDTH : INTEGER;
C_INPUT_SCALAR_8_WIDTH : INTEGER;
C_INPUT_SCALAR_9_WIDTH : INTEGER;
C_INPUT_SCALAR_10_WIDTH : INTEGER;
C_INPUT_SCALAR_11_WIDTH : INTEGER;
C_INPUT_SCALAR_12_WIDTH : INTEGER;
C_INPUT_SCALAR_13_WIDTH : INTEGER;
C_INPUT_SCALAR_14_WIDTH : INTEGER;
C_INPUT_SCALAR_15_WIDTH : INTEGER;
C_OUTPUT_SCALAR_0_WIDTH : INTEGER;
C_OUTPUT_SCALAR_1_WIDTH : INTEGER;
C_OUTPUT_SCALAR_2_WIDTH : INTEGER;
C_OUTPUT_SCALAR_3_WIDTH : INTEGER;
C_OUTPUT_SCALAR_4_WIDTH : INTEGER;
C_OUTPUT_SCALAR_5_WIDTH : INTEGER;
C_OUTPUT_SCALAR_6_WIDTH : INTEGER;
C_OUTPUT_SCALAR_7_WIDTH : INTEGER;
C_OUTPUT_SCALAR_8_WIDTH : INTEGER;
C_OUTPUT_SCALAR_9_WIDTH : INTEGER;
C_OUTPUT_SCALAR_10_WIDTH : INTEGER;
C_OUTPUT_SCALAR_11_WIDTH : INTEGER;
C_OUTPUT_SCALAR_12_WIDTH : INTEGER;
C_OUTPUT_SCALAR_13_WIDTH : INTEGER;
C_OUTPUT_SCALAR_14_WIDTH : INTEGER;
C_OUTPUT_SCALAR_15_WIDTH : INTEGER;
C_N_OUTPUT_SCALARS : INTEGER;
C_OUTPUT_SCALAR_DWIDTH : STD_LOGIC_VECTOR;
C_AP_OSCALAR_DIN_WIDTH : INTEGER;
C_AP_OSCALAR_IO_DIN_WIDTH : INTEGER;
C_ENABLE_STREAM_CLK : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_S_AXIS_HAS_TSTRB : INTEGER;
C_S_AXIS_HAS_TKEEP : INTEGER;
C_NONE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axis_aclk : IN STD_LOGIC;
s_axis_aresetn : IN STD_LOGIC;
s_axis_0_aclk : IN STD_LOGIC;
s_axis_0_aresetn : IN STD_LOGIC;
s_axis_0_tvalid : IN STD_LOGIC;
s_axis_0_tready : OUT STD_LOGIC;
s_axis_0_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_0_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_0_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_0_tlast : IN STD_LOGIC;
s_axis_0_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_0_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_0_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_aclk : IN STD_LOGIC;
s_axis_1_aresetn : IN STD_LOGIC;
s_axis_1_tvalid : IN STD_LOGIC;
s_axis_1_tready : OUT STD_LOGIC;
s_axis_1_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_1_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_tlast : IN STD_LOGIC;
s_axis_1_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_1_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_1_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_aclk : IN STD_LOGIC;
s_axis_2_aresetn : IN STD_LOGIC;
s_axis_2_tvalid : IN STD_LOGIC;
s_axis_2_tready : OUT STD_LOGIC;
s_axis_2_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_2_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_tlast : IN STD_LOGIC;
s_axis_2_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_2_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_2_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_aclk : IN STD_LOGIC;
s_axis_3_aresetn : IN STD_LOGIC;
s_axis_3_tvalid : IN STD_LOGIC;
s_axis_3_tready : OUT STD_LOGIC;
s_axis_3_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_3_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_tlast : IN STD_LOGIC;
s_axis_3_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_3_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_3_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_aclk : IN STD_LOGIC;
s_axis_4_aresetn : IN STD_LOGIC;
s_axis_4_tvalid : IN STD_LOGIC;
s_axis_4_tready : OUT STD_LOGIC;
s_axis_4_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_4_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_tlast : IN STD_LOGIC;
s_axis_4_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_4_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_4_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_aclk : IN STD_LOGIC;
s_axis_5_aresetn : IN STD_LOGIC;
s_axis_5_tvalid : IN STD_LOGIC;
s_axis_5_tready : OUT STD_LOGIC;
s_axis_5_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_5_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_tlast : IN STD_LOGIC;
s_axis_5_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_5_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_5_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_aclk : IN STD_LOGIC;
s_axis_6_aresetn : IN STD_LOGIC;
s_axis_6_tvalid : IN STD_LOGIC;
s_axis_6_tready : OUT STD_LOGIC;
s_axis_6_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_6_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_tlast : IN STD_LOGIC;
s_axis_6_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_6_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_6_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_aclk : IN STD_LOGIC;
s_axis_7_aresetn : IN STD_LOGIC;
s_axis_7_tvalid : IN STD_LOGIC;
s_axis_7_tready : OUT STD_LOGIC;
s_axis_7_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_7_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_tlast : IN STD_LOGIC;
s_axis_7_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_7_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_7_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ap_iarg_0_clk : IN STD_LOGIC;
ap_iarg_0_rst : IN STD_LOGIC;
ap_iarg_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_0_ce : IN STD_LOGIC;
ap_iarg_0_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_clk : IN STD_LOGIC;
ap_iarg_1_rst : IN STD_LOGIC;
ap_iarg_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_ce : IN STD_LOGIC;
ap_iarg_1_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_clk : IN STD_LOGIC;
ap_iarg_2_rst : IN STD_LOGIC;
ap_iarg_2_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_ce : IN STD_LOGIC;
ap_iarg_2_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_clk : IN STD_LOGIC;
ap_iarg_3_rst : IN STD_LOGIC;
ap_iarg_3_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_ce : IN STD_LOGIC;
ap_iarg_3_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_clk : IN STD_LOGIC;
ap_iarg_4_rst : IN STD_LOGIC;
ap_iarg_4_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_ce : IN STD_LOGIC;
ap_iarg_4_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_clk : IN STD_LOGIC;
ap_iarg_5_rst : IN STD_LOGIC;
ap_iarg_5_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_ce : IN STD_LOGIC;
ap_iarg_5_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_clk : IN STD_LOGIC;
ap_iarg_6_rst : IN STD_LOGIC;
ap_iarg_6_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_ce : IN STD_LOGIC;
ap_iarg_6_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_clk : IN STD_LOGIC;
ap_iarg_7_rst : IN STD_LOGIC;
ap_iarg_7_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_ce : IN STD_LOGIC;
ap_iarg_7_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_0_read : IN STD_LOGIC;
ap_fifo_iarg_0_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_1_read : IN STD_LOGIC;
ap_fifo_iarg_1_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_2_read : IN STD_LOGIC;
ap_fifo_iarg_2_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_3_read : IN STD_LOGIC;
ap_fifo_iarg_3_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_4_read : IN STD_LOGIC;
ap_fifo_iarg_4_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_5_read : IN STD_LOGIC;
ap_fifo_iarg_5_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_6_read : IN STD_LOGIC;
ap_fifo_iarg_6_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_7_read : IN STD_LOGIC;
ap_fifo_iarg_7_empty_n : OUT STD_LOGIC;
m_axis_aclk : IN STD_LOGIC;
m_axis_aresetn : IN STD_LOGIC;
m_axis_0_aclk : IN STD_LOGIC;
m_axis_0_aresetn : IN STD_LOGIC;
m_axis_0_tvalid : OUT STD_LOGIC;
m_axis_0_tready : IN STD_LOGIC;
m_axis_0_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_0_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_0_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_0_tlast : OUT STD_LOGIC;
m_axis_0_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_0_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_0_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_aclk : IN STD_LOGIC;
m_axis_1_aresetn : IN STD_LOGIC;
m_axis_1_tvalid : OUT STD_LOGIC;
m_axis_1_tready : IN STD_LOGIC;
m_axis_1_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_1_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_tlast : OUT STD_LOGIC;
m_axis_1_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_1_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_1_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_aclk : IN STD_LOGIC;
m_axis_2_aresetn : IN STD_LOGIC;
m_axis_2_tvalid : OUT STD_LOGIC;
m_axis_2_tready : IN STD_LOGIC;
m_axis_2_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_2_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_tlast : OUT STD_LOGIC;
m_axis_2_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_2_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_2_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_aclk : IN STD_LOGIC;
m_axis_3_aresetn : IN STD_LOGIC;
m_axis_3_tvalid : OUT STD_LOGIC;
m_axis_3_tready : IN STD_LOGIC;
m_axis_3_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_3_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_tlast : OUT STD_LOGIC;
m_axis_3_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_3_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_3_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_aclk : IN STD_LOGIC;
m_axis_4_aresetn : IN STD_LOGIC;
m_axis_4_tvalid : OUT STD_LOGIC;
m_axis_4_tready : IN STD_LOGIC;
m_axis_4_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_4_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_tlast : OUT STD_LOGIC;
m_axis_4_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_4_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_4_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_aclk : IN STD_LOGIC;
m_axis_5_aresetn : IN STD_LOGIC;
m_axis_5_tvalid : OUT STD_LOGIC;
m_axis_5_tready : IN STD_LOGIC;
m_axis_5_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_5_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_tlast : OUT STD_LOGIC;
m_axis_5_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_5_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_5_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_aclk : IN STD_LOGIC;
m_axis_6_aresetn : IN STD_LOGIC;
m_axis_6_tvalid : OUT STD_LOGIC;
m_axis_6_tready : IN STD_LOGIC;
m_axis_6_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_6_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_tlast : OUT STD_LOGIC;
m_axis_6_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_6_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_6_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_aclk : IN STD_LOGIC;
m_axis_7_aresetn : IN STD_LOGIC;
m_axis_7_tvalid : OUT STD_LOGIC;
m_axis_7_tready : IN STD_LOGIC;
m_axis_7_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_7_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_tlast : OUT STD_LOGIC;
m_axis_7_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_7_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_7_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ap_oarg_0_clk : IN STD_LOGIC;
ap_oarg_0_rst : IN STD_LOGIC;
ap_oarg_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_0_ce : IN STD_LOGIC;
ap_oarg_0_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_clk : IN STD_LOGIC;
ap_oarg_1_rst : IN STD_LOGIC;
ap_oarg_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_ce : IN STD_LOGIC;
ap_oarg_1_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_clk : IN STD_LOGIC;
ap_oarg_2_rst : IN STD_LOGIC;
ap_oarg_2_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_ce : IN STD_LOGIC;
ap_oarg_2_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_clk : IN STD_LOGIC;
ap_oarg_3_rst : IN STD_LOGIC;
ap_oarg_3_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_ce : IN STD_LOGIC;
ap_oarg_3_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_clk : IN STD_LOGIC;
ap_oarg_4_rst : IN STD_LOGIC;
ap_oarg_4_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_ce : IN STD_LOGIC;
ap_oarg_4_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_clk : IN STD_LOGIC;
ap_oarg_5_rst : IN STD_LOGIC;
ap_oarg_5_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_ce : IN STD_LOGIC;
ap_oarg_5_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_clk : IN STD_LOGIC;
ap_oarg_6_rst : IN STD_LOGIC;
ap_oarg_6_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_ce : IN STD_LOGIC;
ap_oarg_6_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_clk : IN STD_LOGIC;
ap_oarg_7_rst : IN STD_LOGIC;
ap_oarg_7_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_ce : IN STD_LOGIC;
ap_oarg_7_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_0_write : IN STD_LOGIC;
ap_fifo_oarg_0_full_n : OUT STD_LOGIC;
ap_fifo_oarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_1_write : IN STD_LOGIC;
ap_fifo_oarg_1_full_n : OUT STD_LOGIC;
ap_fifo_oarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_2_write : IN STD_LOGIC;
ap_fifo_oarg_2_full_n : OUT STD_LOGIC;
ap_fifo_oarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_3_write : IN STD_LOGIC;
ap_fifo_oarg_3_full_n : OUT STD_LOGIC;
ap_fifo_oarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_4_write : IN STD_LOGIC;
ap_fifo_oarg_4_full_n : OUT STD_LOGIC;
ap_fifo_oarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_5_write : IN STD_LOGIC;
ap_fifo_oarg_5_full_n : OUT STD_LOGIC;
ap_fifo_oarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_6_write : IN STD_LOGIC;
ap_fifo_oarg_6_full_n : OUT STD_LOGIC;
ap_fifo_oarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_7_write : IN STD_LOGIC;
ap_fifo_oarg_7_full_n : OUT STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : OUT STD_LOGIC;
ap_start : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_continue : OUT STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_iscalar_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_8_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_9_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_10_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_11_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_12_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_13_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_14_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_15_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_8_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_9_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_10_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_11_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_12_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_13_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_14_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_15_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_vld : IN STD_LOGIC;
ap_oscalar_1_vld : IN STD_LOGIC;
ap_oscalar_2_vld : IN STD_LOGIC;
ap_oscalar_3_vld : IN STD_LOGIC;
ap_oscalar_4_vld : IN STD_LOGIC;
ap_oscalar_5_vld : IN STD_LOGIC;
ap_oscalar_6_vld : IN STD_LOGIC;
ap_oscalar_7_vld : IN STD_LOGIC;
ap_oscalar_8_vld : IN STD_LOGIC;
ap_oscalar_9_vld : IN STD_LOGIC;
ap_oscalar_10_vld : IN STD_LOGIC;
ap_oscalar_11_vld : IN STD_LOGIC;
ap_oscalar_12_vld : IN STD_LOGIC;
ap_oscalar_13_vld : IN STD_LOGIC;
ap_oscalar_14_vld : IN STD_LOGIC;
ap_oscalar_15_vld : IN STD_LOGIC;
ap_oscalar_0_ack : OUT STD_LOGIC;
ap_oscalar_1_ack : OUT STD_LOGIC;
ap_oscalar_2_ack : OUT STD_LOGIC;
ap_oscalar_3_ack : OUT STD_LOGIC;
ap_oscalar_4_ack : OUT STD_LOGIC;
ap_oscalar_5_ack : OUT STD_LOGIC;
ap_oscalar_6_ack : OUT STD_LOGIC;
ap_oscalar_7_ack : OUT STD_LOGIC;
ap_oscalar_8_ack : OUT STD_LOGIC;
ap_oscalar_9_ack : OUT STD_LOGIC;
ap_oscalar_10_ack : OUT STD_LOGIC;
ap_oscalar_11_ack : OUT STD_LOGIC;
ap_oscalar_12_ack : OUT STD_LOGIC;
ap_oscalar_13_ack : OUT STD_LOGIC;
ap_oscalar_14_ack : OUT STD_LOGIC;
ap_oscalar_15_ack : OUT STD_LOGIC;
ap_iscalar_0_ack : IN STD_LOGIC;
ap_iscalar_1_ack : IN STD_LOGIC;
ap_iscalar_2_ack : IN STD_LOGIC;
ap_iscalar_3_ack : IN STD_LOGIC;
ap_iscalar_4_ack : IN STD_LOGIC;
ap_iscalar_5_ack : IN STD_LOGIC;
ap_iscalar_6_ack : IN STD_LOGIC;
ap_iscalar_7_ack : IN STD_LOGIC;
ap_iscalar_8_ack : IN STD_LOGIC;
ap_iscalar_9_ack : IN STD_LOGIC;
ap_iscalar_10_ack : IN STD_LOGIC;
ap_iscalar_11_ack : IN STD_LOGIC;
ap_iscalar_12_ack : IN STD_LOGIC;
ap_iscalar_13_ack : IN STD_LOGIC;
ap_iscalar_14_ack : IN STD_LOGIC;
ap_iscalar_15_ack : IN STD_LOGIC;
ap_iscalar_0_vld : OUT STD_LOGIC;
ap_iscalar_1_vld : OUT STD_LOGIC;
ap_iscalar_2_vld : OUT STD_LOGIC;
ap_iscalar_3_vld : OUT STD_LOGIC;
ap_iscalar_4_vld : OUT STD_LOGIC;
ap_iscalar_5_vld : OUT STD_LOGIC;
ap_iscalar_6_vld : OUT STD_LOGIC;
ap_iscalar_7_vld : OUT STD_LOGIC;
ap_iscalar_8_vld : OUT STD_LOGIC;
ap_iscalar_9_vld : OUT STD_LOGIC;
ap_iscalar_10_vld : OUT STD_LOGIC;
ap_iscalar_11_vld : OUT STD_LOGIC;
ap_iscalar_12_vld : OUT STD_LOGIC;
ap_iscalar_13_vld : OUT STD_LOGIC;
ap_iscalar_14_vld : OUT STD_LOGIC;
ap_iscalar_15_vld : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC
);
END COMPONENT axis_accelerator_adapter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zc702_get_0_if_0_arch: ARCHITECTURE IS "axis_accelerator_adapter,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zc702_get_0_if_0_arch : ARCHITECTURE IS "zc702_get_0_if_0,axis_accelerator_adapter,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zc702_get_0_if_0_arch: ARCHITECTURE IS "zc702_get_0_if_0,axis_accelerator_adapter,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_accelerator_adapter,x_ipVersion=2.1,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_AP_ADAPTER_ID=1,C_N_INPUT_ARGS=0,C_N_OUTPUT_ARGS=0,C_S_AXIS_TDATA_WIDTH=64,C_S_AXIS_TUSER_WIDTH=8,C_S_AXIS_TID_WIDTH=4,C_S_AXIS_TDEST_WIDTH=4,C_AP_IARG_TYPE=0x0000000000000000000000000000000000000000000000000000000000000000,C_AP_IARG_MB_DEPTH=0x0000000400000004000000040000000400000004000000040000000400000004,C_AP_IARG_WIDTH=0x0000002000000020000000200000002000000020000000200000002000000020,C_AP_IARG_N_DIM=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_IARG_DIM_1=0x0000040000000400000004000000040000000400000004000000040000000400,C_AP_IARG_DIM_2=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_IARG_FORMAT_TYPE=0x0000000000000000000000000000000000000000000000000000000000000000,C_AP_IARG_FORMAT_FACTOR=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_IARG_FORMAT_DIM=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_IARG_0_DWIDTH=32,C_AP_IARG_1_DWIDTH=32,C_AP_IARG_2_DWIDTH=32,C_AP_IARG_3_DWIDTH=32,C_AP_IARG_4_DWIDTH=32,C_AP_IARG_5_DWIDTH=32,C_AP_IARG_6_DWIDTH=32,C_AP_IARG_7_DWIDTH=32,C_M_AXIS_TDATA_WIDTH=64,C_M_AXIS_TUSER_WIDTH=8,C_M_AXIS_TID_WIDTH=4,C_M_AXIS_TDEST_WIDTH=4,C_AP_OARG_TYPE=0x0000000000000000000000000000000000000000000000000000000000000000,C_AP_OARG_MB_DEPTH=0x0000000400000004000000040000000400000004000000040000000400000004,C_AP_OARG_WIDTH=0x0000002000000020000000200000002000000020000000200000002000000020,C_AP_OARG_N_DIM=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_OARG_DIM=0x0000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000080000000001000000010000000100000008,C_AP_OARG_DIM_1=0x0000040000000400000004000000040000000400000004000000040000000400,C_AP_OARG_DIM_2=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_OARG_FORMAT_TYPE=0x0000000000000000000000000000000000000000000000000000000000000000,C_AP_OARG_FORMAT_FACTOR=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_OARG_FORMAT_DIM=0x0000000100000001000000010000000100000001000000010000000100000001,C_AP_OARG_0_DWIDTH=32,C_AP_OARG_1_DWIDTH=32,C_AP_OARG_2_DWIDTH=32,C_AP_OARG_3_DWIDTH=32,C_AP_OARG_4_DWIDTH=32,C_AP_OARG_5_DWIDTH=32,C_AP_OARG_6_DWIDTH=32,C_AP_OARG_7_DWIDTH=32,C_N_INOUT_SCALARS=0,C_N_INPUT_SCALARS=2,C_INPUT_SCALAR_DWIDTH=0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020,C_INPUT_SCALAR_MODE=0x0000000000000000,C_OUTPUT_SCALAR_MODE=0x0000000000000010,C_AP_ISCALAR_DOUT_WIDTH=64,C_AP_ISCALAR_IO_DOUT_WIDTH=32,C_INPUT_SCALAR_0_WIDTH=32,C_INPUT_SCALAR_1_WIDTH=32,C_INPUT_SCALAR_2_WIDTH=32,C_INPUT_SCALAR_3_WIDTH=32,C_INPUT_SCALAR_4_WIDTH=32,C_INPUT_SCALAR_5_WIDTH=32,C_INPUT_SCALAR_6_WIDTH=32,C_INPUT_SCALAR_7_WIDTH=32,C_INPUT_SCALAR_8_WIDTH=32,C_INPUT_SCALAR_9_WIDTH=32,C_INPUT_SCALAR_10_WIDTH=32,C_INPUT_SCALAR_11_WIDTH=32,C_INPUT_SCALAR_12_WIDTH=32,C_INPUT_SCALAR_13_WIDTH=32,C_INPUT_SCALAR_14_WIDTH=32,C_INPUT_SCALAR_15_WIDTH=32,C_OUTPUT_SCALAR_0_WIDTH=32,C_OUTPUT_SCALAR_1_WIDTH=32,C_OUTPUT_SCALAR_2_WIDTH=32,C_OUTPUT_SCALAR_3_WIDTH=32,C_OUTPUT_SCALAR_4_WIDTH=32,C_OUTPUT_SCALAR_5_WIDTH=32,C_OUTPUT_SCALAR_6_WIDTH=32,C_OUTPUT_SCALAR_7_WIDTH=32,C_OUTPUT_SCALAR_8_WIDTH=32,C_OUTPUT_SCALAR_9_WIDTH=32,C_OUTPUT_SCALAR_10_WIDTH=32,C_OUTPUT_SCALAR_11_WIDTH=32,C_OUTPUT_SCALAR_12_WIDTH=32,C_OUTPUT_SCALAR_13_WIDTH=32,C_OUTPUT_SCALAR_14_WIDTH=32,C_OUTPUT_SCALAR_15_WIDTH=32,C_N_OUTPUT_SCALARS=2,C_OUTPUT_SCALAR_DWIDTH=0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020,C_AP_OSCALAR_DIN_WIDTH=64,C_AP_OSCALAR_IO_DIN_WIDTH=32,C_ENABLE_STREAM_CLK=0,C_PRMRY_IS_ACLK_ASYNC=0,C_S_AXIS_HAS_TSTRB=0,C_S_AXIS_HAS_TKEEP=0,C_NONE=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF ap_start: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL start";
ATTRIBUTE X_INTERFACE_INFO OF ap_ready: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL ready";
ATTRIBUTE X_INTERFACE_INFO OF ap_done: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL done";
ATTRIBUTE X_INTERFACE_INFO OF ap_continue: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL continue";
ATTRIBUTE X_INTERFACE_INFO OF ap_idle: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL idle";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axis_accelerator_adapter
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_AP_ADAPTER_ID => 1,
C_N_INPUT_ARGS => 0,
C_N_OUTPUT_ARGS => 0,
C_S_AXIS_TDATA_WIDTH => 64,
C_S_AXIS_TUSER_WIDTH => 8,
C_S_AXIS_TID_WIDTH => 4,
C_S_AXIS_TDEST_WIDTH => 4,
C_AP_IARG_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_IARG_MB_DEPTH => X"0000000400000004000000040000000400000004000000040000000400000004",
C_AP_IARG_WIDTH => X"0000002000000020000000200000002000000020000000200000002000000020",
C_AP_IARG_N_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_DIM_1 => X"0000040000000400000004000000040000000400000004000000040000000400",
C_AP_IARG_DIM_2 => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_FORMAT_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_IARG_FORMAT_FACTOR => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_FORMAT_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_0_DWIDTH => 32,
C_AP_IARG_1_DWIDTH => 32,
C_AP_IARG_2_DWIDTH => 32,
C_AP_IARG_3_DWIDTH => 32,
C_AP_IARG_4_DWIDTH => 32,
C_AP_IARG_5_DWIDTH => 32,
C_AP_IARG_6_DWIDTH => 32,
C_AP_IARG_7_DWIDTH => 32,
C_M_AXIS_TDATA_WIDTH => 64,
C_M_AXIS_TUSER_WIDTH => 8,
C_M_AXIS_TID_WIDTH => 4,
C_M_AXIS_TDEST_WIDTH => 4,
C_AP_OARG_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_OARG_MB_DEPTH => X"0000000400000004000000040000000400000004000000040000000400000004",
C_AP_OARG_WIDTH => X"0000002000000020000000200000002000000020000000200000002000000020",
C_AP_OARG_N_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_DIM => X"0000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000080000000001000000010000000100000008",
C_AP_OARG_DIM_1 => X"0000040000000400000004000000040000000400000004000000040000000400",
C_AP_OARG_DIM_2 => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_FORMAT_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_OARG_FORMAT_FACTOR => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_FORMAT_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_0_DWIDTH => 32,
C_AP_OARG_1_DWIDTH => 32,
C_AP_OARG_2_DWIDTH => 32,
C_AP_OARG_3_DWIDTH => 32,
C_AP_OARG_4_DWIDTH => 32,
C_AP_OARG_5_DWIDTH => 32,
C_AP_OARG_6_DWIDTH => 32,
C_AP_OARG_7_DWIDTH => 32,
C_N_INOUT_SCALARS => 0,
C_N_INPUT_SCALARS => 2,
C_INPUT_SCALAR_DWIDTH => X"00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020",
C_INPUT_SCALAR_MODE => X"0000000000000000",
C_OUTPUT_SCALAR_MODE => X"0000000000000010",
C_AP_ISCALAR_DOUT_WIDTH => 64,
C_AP_ISCALAR_IO_DOUT_WIDTH => 32,
C_INPUT_SCALAR_0_WIDTH => 32,
C_INPUT_SCALAR_1_WIDTH => 32,
C_INPUT_SCALAR_2_WIDTH => 32,
C_INPUT_SCALAR_3_WIDTH => 32,
C_INPUT_SCALAR_4_WIDTH => 32,
C_INPUT_SCALAR_5_WIDTH => 32,
C_INPUT_SCALAR_6_WIDTH => 32,
C_INPUT_SCALAR_7_WIDTH => 32,
C_INPUT_SCALAR_8_WIDTH => 32,
C_INPUT_SCALAR_9_WIDTH => 32,
C_INPUT_SCALAR_10_WIDTH => 32,
C_INPUT_SCALAR_11_WIDTH => 32,
C_INPUT_SCALAR_12_WIDTH => 32,
C_INPUT_SCALAR_13_WIDTH => 32,
C_INPUT_SCALAR_14_WIDTH => 32,
C_INPUT_SCALAR_15_WIDTH => 32,
C_OUTPUT_SCALAR_0_WIDTH => 32,
C_OUTPUT_SCALAR_1_WIDTH => 32,
C_OUTPUT_SCALAR_2_WIDTH => 32,
C_OUTPUT_SCALAR_3_WIDTH => 32,
C_OUTPUT_SCALAR_4_WIDTH => 32,
C_OUTPUT_SCALAR_5_WIDTH => 32,
C_OUTPUT_SCALAR_6_WIDTH => 32,
C_OUTPUT_SCALAR_7_WIDTH => 32,
C_OUTPUT_SCALAR_8_WIDTH => 32,
C_OUTPUT_SCALAR_9_WIDTH => 32,
C_OUTPUT_SCALAR_10_WIDTH => 32,
C_OUTPUT_SCALAR_11_WIDTH => 32,
C_OUTPUT_SCALAR_12_WIDTH => 32,
C_OUTPUT_SCALAR_13_WIDTH => 32,
C_OUTPUT_SCALAR_14_WIDTH => 32,
C_OUTPUT_SCALAR_15_WIDTH => 32,
C_N_OUTPUT_SCALARS => 2,
C_OUTPUT_SCALAR_DWIDTH => X"00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020",
C_AP_OSCALAR_DIN_WIDTH => 64,
C_AP_OSCALAR_IO_DIN_WIDTH => 32,
C_ENABLE_STREAM_CLK => 0,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_S_AXIS_HAS_TSTRB => 0,
C_S_AXIS_HAS_TKEEP => 0,
C_NONE => 2
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axis_aclk => '0',
s_axis_aresetn => '0',
s_axis_0_aclk => '0',
s_axis_0_aresetn => '0',
s_axis_0_tvalid => '0',
s_axis_0_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_0_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_0_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_0_tlast => '0',
s_axis_0_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_0_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_0_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_aclk => '0',
s_axis_1_aresetn => '0',
s_axis_1_tvalid => '0',
s_axis_1_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_1_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_tlast => '0',
s_axis_1_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_1_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_1_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_aclk => '0',
s_axis_2_aresetn => '0',
s_axis_2_tvalid => '0',
s_axis_2_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_2_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_tlast => '0',
s_axis_2_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_2_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_2_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_aclk => '0',
s_axis_3_aresetn => '0',
s_axis_3_tvalid => '0',
s_axis_3_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_3_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_tlast => '0',
s_axis_3_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_3_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_3_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_aclk => '0',
s_axis_4_aresetn => '0',
s_axis_4_tvalid => '0',
s_axis_4_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_4_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_tlast => '0',
s_axis_4_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_4_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_4_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_aclk => '0',
s_axis_5_aresetn => '0',
s_axis_5_tvalid => '0',
s_axis_5_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_5_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_tlast => '0',
s_axis_5_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_5_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_5_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_aclk => '0',
s_axis_6_aresetn => '0',
s_axis_6_tvalid => '0',
s_axis_6_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_6_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_tlast => '0',
s_axis_6_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_6_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_6_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_aclk => '0',
s_axis_7_aresetn => '0',
s_axis_7_tvalid => '0',
s_axis_7_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_7_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_tlast => '0',
s_axis_7_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_7_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_7_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
ap_iarg_0_clk => '0',
ap_iarg_0_rst => '0',
ap_iarg_0_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_0_ce => '0',
ap_iarg_0_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_1_clk => '0',
ap_iarg_1_rst => '0',
ap_iarg_1_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_1_ce => '0',
ap_iarg_1_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_2_clk => '0',
ap_iarg_2_rst => '0',
ap_iarg_2_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_2_ce => '0',
ap_iarg_2_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_3_clk => '0',
ap_iarg_3_rst => '0',
ap_iarg_3_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_3_ce => '0',
ap_iarg_3_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_4_clk => '0',
ap_iarg_4_rst => '0',
ap_iarg_4_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_4_ce => '0',
ap_iarg_4_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_5_clk => '0',
ap_iarg_5_rst => '0',
ap_iarg_5_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_5_ce => '0',
ap_iarg_5_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_6_clk => '0',
ap_iarg_6_rst => '0',
ap_iarg_6_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_6_ce => '0',
ap_iarg_6_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_7_clk => '0',
ap_iarg_7_rst => '0',
ap_iarg_7_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_7_ce => '0',
ap_iarg_7_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_iarg_0_read => '0',
ap_fifo_iarg_1_read => '0',
ap_fifo_iarg_2_read => '0',
ap_fifo_iarg_3_read => '0',
ap_fifo_iarg_4_read => '0',
ap_fifo_iarg_5_read => '0',
ap_fifo_iarg_6_read => '0',
ap_fifo_iarg_7_read => '0',
m_axis_aclk => '0',
m_axis_aresetn => '0',
m_axis_0_aclk => '0',
m_axis_0_aresetn => '0',
m_axis_0_tready => '0',
m_axis_1_aclk => '0',
m_axis_1_aresetn => '0',
m_axis_1_tready => '0',
m_axis_2_aclk => '0',
m_axis_2_aresetn => '0',
m_axis_2_tready => '0',
m_axis_3_aclk => '0',
m_axis_3_aresetn => '0',
m_axis_3_tready => '0',
m_axis_4_aclk => '0',
m_axis_4_aresetn => '0',
m_axis_4_tready => '0',
m_axis_5_aclk => '0',
m_axis_5_aresetn => '0',
m_axis_5_tready => '0',
m_axis_6_aclk => '0',
m_axis_6_aresetn => '0',
m_axis_6_tready => '0',
m_axis_7_aclk => '0',
m_axis_7_aresetn => '0',
m_axis_7_tready => '0',
ap_oarg_0_clk => '0',
ap_oarg_0_rst => '0',
ap_oarg_0_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_0_ce => '0',
ap_oarg_0_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_1_clk => '0',
ap_oarg_1_rst => '0',
ap_oarg_1_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_1_ce => '0',
ap_oarg_1_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_2_clk => '0',
ap_oarg_2_rst => '0',
ap_oarg_2_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_2_ce => '0',
ap_oarg_2_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_3_clk => '0',
ap_oarg_3_rst => '0',
ap_oarg_3_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_3_ce => '0',
ap_oarg_3_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_4_clk => '0',
ap_oarg_4_rst => '0',
ap_oarg_4_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_4_ce => '0',
ap_oarg_4_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_5_clk => '0',
ap_oarg_5_rst => '0',
ap_oarg_5_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_5_ce => '0',
ap_oarg_5_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_6_clk => '0',
ap_oarg_6_rst => '0',
ap_oarg_6_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_6_ce => '0',
ap_oarg_6_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_7_clk => '0',
ap_oarg_7_rst => '0',
ap_oarg_7_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_7_ce => '0',
ap_oarg_7_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_0_write => '0',
ap_fifo_oarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_1_write => '0',
ap_fifo_oarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_2_write => '0',
ap_fifo_oarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_3_write => '0',
ap_fifo_oarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_4_write => '0',
ap_fifo_oarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_5_write => '0',
ap_fifo_oarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_6_write => '0',
ap_fifo_oarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_7_write => '0',
aclk => aclk,
aresetn => aresetn,
ap_start => ap_start,
ap_ready => ap_ready,
ap_done => ap_done,
ap_continue => ap_continue,
ap_idle => ap_idle,
ap_iscalar_0_dout => ap_iscalar_0_dout,
ap_iscalar_1_dout => ap_iscalar_1_dout,
ap_oscalar_0_din => ap_oscalar_0_din,
ap_oscalar_1_din => ap_oscalar_1_din,
ap_oscalar_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_8_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_9_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_10_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_11_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_12_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_13_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_14_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_15_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_0_vld => '0',
ap_oscalar_1_vld => ap_oscalar_1_vld,
ap_oscalar_2_vld => '0',
ap_oscalar_3_vld => '0',
ap_oscalar_4_vld => '0',
ap_oscalar_5_vld => '0',
ap_oscalar_6_vld => '0',
ap_oscalar_7_vld => '0',
ap_oscalar_8_vld => '0',
ap_oscalar_9_vld => '0',
ap_oscalar_10_vld => '0',
ap_oscalar_11_vld => '0',
ap_oscalar_12_vld => '0',
ap_oscalar_13_vld => '0',
ap_oscalar_14_vld => '0',
ap_oscalar_15_vld => '0',
ap_iscalar_0_ack => '0',
ap_iscalar_1_ack => '0',
ap_iscalar_2_ack => '0',
ap_iscalar_3_ack => '0',
ap_iscalar_4_ack => '0',
ap_iscalar_5_ack => '0',
ap_iscalar_6_ack => '0',
ap_iscalar_7_ack => '0',
ap_iscalar_8_ack => '0',
ap_iscalar_9_ack => '0',
ap_iscalar_10_ack => '0',
ap_iscalar_11_ack => '0',
ap_iscalar_12_ack => '0',
ap_iscalar_13_ack => '0',
ap_iscalar_14_ack => '0',
ap_iscalar_15_ack => '0',
interrupt => interrupt
);
END zc702_get_0_if_0_arch;
|
---------------------------------------------------------------------------
-- reg_unit.vhd --
-- Raj Vinjamuri --
-- 3-13 --
-- --
-- Purpose/Description: --
-- combines the registers to be used as simply as we desire the I/O --
-- --
-- based on register unit given by UIUC --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
-- --
-- --
-- Updates: --
-- --
-- >3.10: Made components lower case --
-- >changed A and B to SR and PR respectively --
-- >fixed 7 downto 0 to 10 downto 0 --
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg_unit is
Port ( Clk : in std_logic;
ClrSR, ClrPR : in std_logic;
D_In : in std_logic_vector(10 downto 0);
SR_In : in std_logic;
Ld_SR : in std_logic;
Ld_PR : in std_logic;
Shift_En : in std_logic;
SR_out : out std_logic;
PR_out : out std_logic;
SR : out std_logic_vector(10 downto 0);
PR : out std_logic_vector(10 downto 0));
end reg_unit;
architecture Behavioral of reg_unit is
component reg_11 is
Port ( Clk, Reset, Shift_In, Load, Shift_En : in std_logic;
D : in std_logic_vector(10 downto 0);
Shift_Out : out std_logic;
Data_Out : out std_logic_vector(10 downto 0));
end component reg_11;
signal shift_line : std_logic;
begin --connecting both registers so one feeds the other
scan_reg: reg_11
port map( Clk => Clk,
Reset => ClrSR,
D => D_In,
Shift_In => SR_in,
Load => Ld_SR,
Shift_En => Shift_En,
Shift_Out => shift_line,
Data_Out => SR);
prev_reg: reg_11
port map( Clk => Clk,
Reset => ClrPR,
D => D_In,
Shift_In => shift_line,
Load => Ld_PR,
Shift_En => Shift_En,
Shift_Out => PR_out,
Data_Out => PR);
end Behavioral; |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
use work.avblabs_common_pkg.all;
entity dvb_ts_filter is
port (
rst : in std_logic;
clk : in std_logic;
--
pid_tbl_addr : in std_logic_vector(7 downto 0);
pid_tbl_be : in std_logic_vector(3 downto 0);
pid_tbl_wrdata : in std_logic_vector(31 downto 0);
pid_tbl_write : in std_logic;
pid_tbl_rddata : out std_logic_vector(31 downto 0);
pid_tbl_read : in std_logic;
pid_tbl_waitreq : out std_logic;
--
dvb_in_dsop : in std_logic;
dvb_in_data : in std_logic_vector(7 downto 0);
dvb_in_dval : in std_logic;
--
dvb_out_dsop : out std_logic;
dvb_out_data : out std_logic_vector(7 downto 0);
dvb_out_dval : out std_logic
);
end entity;
architecture rtl of dvb_ts_filter is
-- type mem_t is array(0 to 255) of std_logic_vector(7 downto 0);
-- shared variable pid_tbl_ram_0 : mem_t;
-- shared variable pid_tbl_ram_1 : mem_t;
-- shared variable pid_tbl_ram_2 : mem_t;
-- shared variable pid_tbl_ram_3 : mem_t;
-- signal pid_tbl_ram_addr_a : unsigned(12 downto 5);
-- signal pid_tbl_ram_be_a : std_logic_vector(3 downto 0);
-- signal pid_tbl_ram_we_a : std_logic;
-- signal pid_tbl_ram_d_a : std_logic_vector(7 downto 0);
signal pid_tbl_ram_q_a_0 : std_logic_vector(7 downto 0);
signal pid_tbl_ram_q_a_1 : std_logic_vector(7 downto 0);
signal pid_tbl_ram_q_a_2 : std_logic_vector(7 downto 0);
signal pid_tbl_ram_q_a_3 : std_logic_vector(7 downto 0);
-- signal pid_tbl_ram_addr_b : unsigned(12 downto 1);
signal pid_tbl_ram_q_b_0 : std_logic_vector(0 downto 0);
signal pid_tbl_ram_q_b_1 : std_logic_vector(0 downto 0);
signal pid_tbl_ram_q_b_2 : std_logic_vector(0 downto 0);
signal pid_tbl_ram_q_b_3 : std_logic_vector(0 downto 0);
signal pid_tbl_value : std_logic_vector(3 downto 0);
signal pid_tbl_rddata_latch : std_logic_vector(31 downto 0);
signal latch_valid : std_logic;
signal rddata_valid : std_logic;
signal header : std_logic;
signal pkten : std_logic;
signal dvb_word_0 : std_logic_vector(9 downto 0);
signal dvb_word_1 : std_logic_vector(9 downto 0);
signal dvb_word_2 : std_logic_vector(9 downto 0);
signal dvb_word_3 : std_logic_vector(9 downto 0);
signal dvb_word_4 : std_logic_vector(9 downto 0);
-- attribute ramstyle : string;
-- attribute ramstyle of pid_tbl_ram_0 : variable is "M9K, no_rw_check";
-- attribute ramstyle of pid_tbl_ram_1 : variable is "M9K, no_rw_check";
-- attribute ramstyle of pid_tbl_ram_2 : variable is "M9K, no_rw_check";
-- attribute ramstyle of pid_tbl_ram_3 : variable is "M9K, no_rw_check";
begin
/*
-- RAM port A (read/write)
process (clk)
variable addr_a : integer range 0 to 255;
begin
if rising_edge(clk) then
addr_a := to_integer(unsigned(pid_tbl_addr));
--
if pid_tbl_write and pid_tbl_be(0) then
pid_tbl_ram_0(addr_a) := pid_tbl_wrdata(7 downto 0);
end if;
if pid_tbl_write and pid_tbl_be(1) then
pid_tbl_ram_1(addr_a) := pid_tbl_wrdata(15 downto 8);
end if;
if pid_tbl_write and pid_tbl_be(2) then
pid_tbl_ram_2(addr_a) := pid_tbl_wrdata(23 downto 16);
end if;
if pid_tbl_write and pid_tbl_be(3) then
pid_tbl_ram_3(addr_a) := pid_tbl_wrdata(31 downto 24);
end if;
--
pid_tbl_ram_q_a_0 <= pid_tbl_ram_0(addr_a);
pid_tbl_ram_q_a_1 <= pid_tbl_ram_1(addr_a);
pid_tbl_ram_q_a_2 <= pid_tbl_ram_2(addr_a);
pid_tbl_ram_q_a_3 <= pid_tbl_ram_3(addr_a);
end if;
end process;
-- RAM port B (read only)
process (clk)
variable addr_b : integer range 0 to 255;
begin
if rising_edge(clk) then
addr_b := to_integer(unsigned(dvb_word_1(4 downto 0)) & unsigned(dvb_word_0(7 downto 5)) & unsigned(dvb_word_0(2 downto 0)));
--
pid_tbl_ram_q_b_0 <= pid_tbl_ram_0(addr_b / 8)(addr_b rem 8);
pid_tbl_ram_q_b_1 <= pid_tbl_ram_1(addr_b / 8)(addr_b rem 8);
pid_tbl_ram_q_b_2 <= pid_tbl_ram_2(addr_b / 8)(addr_b rem 8);
pid_tbl_ram_q_b_3 <= pid_tbl_ram_3(addr_b / 8)(addr_b rem 8);
end if;
end process;
*/
RAM_0 : entity work.pid_table_ram
port map (
clock => clk,
--
address_a => pid_tbl_addr,
data_a => pid_tbl_wrdata(7 downto 0),
wren_a => pid_tbl_write and pid_tbl_be(0),
q_a => pid_tbl_ram_q_a_0,
--
address_b => dvb_word_1(4 downto 0) & dvb_word_0(7 downto 5) & dvb_word_0(2 downto 0),
data_b => (others => '0'),
wren_b => '0',
q_b => pid_tbl_ram_q_b_0
);
RAM_1 : entity work.pid_table_ram
port map (
clock => clk,
--
address_a => pid_tbl_addr,
data_a => pid_tbl_wrdata(15 downto 8),
wren_a => pid_tbl_write and pid_tbl_be(1),
q_a => pid_tbl_ram_q_a_1,
--
address_b => dvb_word_1(4 downto 0) & dvb_word_0(7 downto 5) & dvb_word_0(2 downto 0),
data_b => (others => '0'),
wren_b => '0',
q_b => pid_tbl_ram_q_b_1
);
RAM_2 : entity work.pid_table_ram
port map (
clock => clk,
--
address_a => pid_tbl_addr,
data_a => pid_tbl_wrdata(23 downto 16),
wren_a => pid_tbl_write and pid_tbl_be(2),
q_a => pid_tbl_ram_q_a_2,
--
address_b => dvb_word_1(4 downto 0) & dvb_word_0(7 downto 5) & dvb_word_0(2 downto 0),
data_b => (others => '0'),
wren_b => '0',
q_b => pid_tbl_ram_q_b_2
);
RAM_3 : entity work.pid_table_ram
port map (
clock => clk,
--
address_a => pid_tbl_addr,
data_a => pid_tbl_wrdata(31 downto 24),
wren_a => pid_tbl_write and pid_tbl_be(3),
q_a => pid_tbl_ram_q_a_3,
--
address_b => dvb_word_1(4 downto 0) & dvb_word_0(7 downto 5) & dvb_word_0(2 downto 0),
data_b => (others => '0'),
wren_b => '0',
q_b => pid_tbl_ram_q_b_3
);
-- other logic
-- pid_tbl_ram_addr_a <= unsigned(pid_tbl_addr);
-- pid_tbl_ram_be_a <= pid_tbl_be;
-- pid_tbl_ram_we_a <= pid_tbl_write;
-- REORG_0 : for i in 0 to 3 generate
-- pid_tbl_rddata_latch(i * 8 + 7 downto i * 8) <= pid_tbl_ram_q_a(i);
-- pid_tbl_ram_d_a(i) <= pid_tbl_wrdata(i * 8 + 7 downto i * 8);
-- end generate;
pid_tbl_rddata_latch <= pid_tbl_ram_q_a_3 & pid_tbl_ram_q_a_2 & pid_tbl_ram_q_a_1 & pid_tbl_ram_q_a_0;
pid_tbl_value <= pid_tbl_ram_q_b_3 & pid_tbl_ram_q_b_2 & pid_tbl_ram_q_b_1 & pid_tbl_ram_q_b_0;
-- pid_tbl_ram_addr_b <= unsigned(dvb_word_1(4 downto 0)) & unsigned(dvb_word_0(7 downto 5));
pid_tbl_waitreq <= pid_tbl_read and not rddata_valid;
process (rst, clk)
begin
if rising_edge(clk) then
pid_tbl_rddata <= pid_tbl_rddata_latch;
latch_valid <= pid_tbl_read and (latch_valid nor rddata_valid);
rddata_valid <= latch_valid;
--
if dvb_in_dval then
if dvb_in_dsop then
header <= '1';
elsif dvb_word_1(8) then
header <= '0';
end if;
end if;
if dvb_word_3(8) then
pkten <= not pid_tbl_value(to_integer(unsigned(dvb_word_1(4 downto 3))));--(to_integer(unsigned(dvb_word_1(4 downto 3))))(to_integer(unsigned(dvb_word_1(2 downto 0))));
end if;
if not header or dvb_in_dval then
dvb_word_0 <= dvb_in_dval & dvb_in_dsop & dvb_in_data;
dvb_word_1 <= dvb_word_0;
dvb_word_2 <= dvb_word_1;
dvb_word_3 <= dvb_word_2;
dvb_word_4 <= dvb_word_3;
-- output stage
if not pkten then
dvb_out_dval <= '0';
dvb_out_dsop <= '0';
dvb_out_data <= (others => '0');
else
dvb_out_dval <= dvb_word_4(9);
dvb_out_dsop <= dvb_word_4(8);
dvb_out_data <= dvb_word_4(7 downto 0);
end if;
end if;
end if;
if rst then
pid_tbl_rddata <= (others => '0');
latch_valid <= '0';
rddata_valid <= '0';
--
header <= '0';
pkten <= '0';
--
dvb_word_0 <= (others => '0');
dvb_word_1 <= (others => '0');
dvb_word_2 <= (others => '0');
dvb_word_3 <= (others => '0');
dvb_word_4 <= (others => '0');
--
dvb_out_dval <= '0';
dvb_out_dsop <= '0';
dvb_out_data <= (others => '0');
end if;
end process;
end architecture;
|
entity const9 is
constant str : string := const9'path_name;
end entity;
architecture test of const9 is
begin
p1: process is
begin
report str;
assert str = ":const9:";
wait;
end process;
end architecture;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config_hyperion.all;
package zpupkg_hyperion is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := 13;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg_hyperion;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config_hyperion.all;
package zpupkg_hyperion is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := 13;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg_hyperion;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config_hyperion.all;
package zpupkg_hyperion is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := 13;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg_hyperion;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config_hyperion.all;
package zpupkg_hyperion is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := 13;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg_hyperion;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config_hyperion.all;
package zpupkg_hyperion is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := 13;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg_hyperion;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config_hyperion.all;
package zpupkg_hyperion is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := 13;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg_hyperion;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config_hyperion.all;
package zpupkg_hyperion is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := 13;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg_hyperion;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config_hyperion.all;
package zpupkg_hyperion is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := 13;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg_hyperion;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config_hyperion.all;
package zpupkg_hyperion is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := 13;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg_hyperion;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config_hyperion.all;
package zpupkg_hyperion is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := 13;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg_hyperion;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config_hyperion.all;
package zpupkg_hyperion is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := 13;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg_hyperion;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config_hyperion.all;
package zpupkg_hyperion is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := 13;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg_hyperion;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config_hyperion.all;
package zpupkg_hyperion is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := 13;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme_hyperion is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg_hyperion;
|
-------------------------------------------------------------------------------
--
-- File: PhaseAlign.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 7 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module receives a DVI-encoded stream of 10-bit deserialized words
-- and tries to change the phase of the serial data to shift the sampling
-- event to the middle of the "eye", ie. the part of the bit period where
-- data is stable. Alignment is achieved by incrementing the tap count of
-- the IDELAYE2 primitives, delaying data by kIDLY_TapValuePs in each step.
-- In Artix-7 architecture each tap (step) accounts to 78 ps.
-- Data is considered valid when control tokens are recognized in the
-- stream. Alignment lock is achieved when the middle of the valid eye is
-- found. When this happens, pAligned will go high. If the whole range of
-- delay values had been exhausted and alignment lock could still not be
-- achieved, pError will go high. Resetting the module with pRst will
-- restart the alignment process.
-- The port pEyeSize provides an approximation of the width of the
-- eye in units of tap count. The larger the number, the better the signal
-- quality of the DVI stream.
-- Since the IDELAYE2 primitive only allows a fine alignment, the bitslip
-- feature of the ISERDES primitives complements the PhaseAlign module acting
-- as coarse alignment to find the 10-bit word boundary in the data stream.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PhaseAlign is
Generic (
kUseFastAlgorithm : boolean := false;
kCtlTknCount : natural := 128; --how many subsequent control tokens make a valid blank detection
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
pRst : in STD_LOGIC;
pTimeoutOvf : in std_logic; --50ms timeout expired
pTimeoutRst : out std_logic; --reset timeout
PixelClk : in STD_LOGIC;
pData : in STD_LOGIC_VECTOR (9 downto 0);
pIDLY_CE : out STD_LOGIC;
pIDLY_INC : out STD_LOGIC;
pIDLY_CNT : in STD_LOGIC_VECTOR (kIDLY_TapWidth-1 downto 0);
pIDLY_LD : out STD_LOGIC; --load default tap value
pAligned : out STD_LOGIC;
pError : out STD_LOGIC;
pEyeSize : out STD_LOGIC_VECTOR(kIDLY_TapWidth-1 downto 0));
end PhaseAlign;
architecture Behavioral of PhaseAlign is
-- Control Token Counter
signal pCtlTknCnt : natural range 0 to kCtlTknCount-1;
signal pCtlTknRst, pCtlTknOvf : std_logic;
-- Control Token Detection Pipeline
signal pTkn0Flag, pTkn1Flag, pTkn2Flag, pTkn3Flag : std_logic;
signal pTkn0FlagQ, pTkn1FlagQ, pTkn2FlagQ, pTkn3FlagQ : std_logic;
signal pTknFlag, pTknFlagQ, pBlankBegin : std_logic;
signal pDataQ : std_logic_vector(pData'high downto pData'low);
constant kTapCntEnd : std_logic_vector(pIDLY_CNT'range) := (others => '0');
constant kFastTapCntEnd : std_logic_vector(pIDLY_CNT'range) := std_logic_vector(to_unsigned(20, pIDLY_CNT'length)); -- fast search limit; if token not found in 20 taps, fail earlier and bitslip
signal pIDLY_CNT_Q : std_logic_vector(pIDLY_CNT'range);
signal pDelayOvf, pDelayFastOvf, pDelayCenter : std_logic;
-- IDELAY increment/decrement wait counter
-- CE, INC registered outputs + CNTVALUEOUT registered input + CNTVALUEOUT registered comparison
constant kDelayWaitEnd : natural := 3;
signal pDelayWaitCnt : natural range 0 to kDelayWaitEnd - 1;
signal pDelayWaitRst, pDelayWaitOvf : std_logic;
constant kEyeOpenCntMin : natural := 3;
constant kEyeOpenCntEnough : natural := 16;
signal pEyeOpenCnt : unsigned(kIDLY_TapWidth-1 downto 0);
signal pCenterTap : unsigned(kIDLY_TapWidth downto 0); -- 1 extra bit to increment with 1/2 for every open eye tap
signal pEyeOpenRst, pEyeOpenEn : std_logic;
--Flags
signal pFoundJtrFlag, pFoundEyeFlag : std_logic;
--FSM
--type state_t is (ResetSt, IdleSt, TokenSt, EyeOpenSt, JtrZoneSt, DlyIncSt, DlyTstOvfSt, DlyDecSt, DlyTstCenterSt, AlignedSt, AlignErrorSt);
subtype state_t is std_logic_vector(10 downto 0);
signal pState, pStateNxt : state_t;
-- Ugh, manual state encoding, since Vivado won't tell me the result of automatic encoding; we need this for debugging.
constant ResetSt : state_t := "00000000001";
constant IdleSt : state_t := "00000000010";
constant TokenSt : state_t := "00000000100";
constant EyeOpenSt : state_t := "00000001000";
constant JtrZoneSt : state_t := "00000010000";
constant DlyIncSt : state_t := "00000100000";
constant DlyTstOvfSt : state_t := "00001000000";
constant DlyDecSt : state_t := "00010000000";
constant DlyTstCenterSt : state_t :="00100000000";
constant AlignedSt : state_t := "01000000000";
constant AlignErrorSt : state_t := "10000000000";
begin
ControlTokenCounter: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pCtlTknRst = '1') then
pCtlTknCnt <= 0;
else
pCtlTknCnt <= pCtlTknCnt + 1;
-- Overflow
if (pCtlTknCnt = kCtlTknCount - 1) then
pCtlTknOvf <= '1';
else
pCtlTknOvf <= '0';
end if;
end if;
end if;
end process ControlTokenCounter;
-- Control Token Detection
pTkn0Flag <= '1' when pDataQ = kCtlTkn0 else '0';
pTkn1Flag <= '1' when pDataQ = kCtlTkn1 else '0';
pTkn2Flag <= '1' when pDataQ = kCtlTkn2 else '0';
pTkn3Flag <= '1' when pDataQ = kCtlTkn3 else '0';
-- Register pipeline
ControlTokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pDataQ <= pData; -- level 1
pTkn0FlagQ <= pTkn0Flag;
pTkn1FlagQ <= pTkn1Flag;
pTkn2FlagQ <= pTkn2Flag;
pTkn3FlagQ <= pTkn3Flag; -- level 2
pTknFlag <= pTkn0Flag or pTkn1Flag or pTkn2Flag or pTkn3Flag; -- level 3
pTknFlagQ <= pTknFlag;
pBlankBegin <= not pTknFlagQ and pTknFlag; -- level 4
end if;
end process ControlTokenDetect;
-- Open Eye Width Counter
EyeOpenCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pEyeOpenRst = '1') then
pEyeOpenCnt <= (others => '0');
pCenterTap <= unsigned(pIDLY_CNT_Q) & '1'; -- 1 extra bit for 1/2 increments; start with 1/2
elsif (pEyeOpenEn = '1') then
pEyeOpenCnt <= pEyeOpenCnt + 1;
pCenterTap <= pCenterTap + 1;
end if;
end if;
end process EyeOpenCnt;
pEyeSize <= std_logic_vector(pEyeOpenCnt);
-- Tap Delay Overflow
TapDelayCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
pIDLY_CNT_Q <= pIDLY_CNT;
if (pIDLY_CNT_Q = kTapCntEnd) then
pDelayOvf <= '1';
else
pDelayOvf <= '0';
end if;
if (pIDLY_CNT_Q = kFastTapCntEnd) then
pDelayFastOvf <= '1';
else
pDelayFastOvf <= '0';
end if;
end if;
end process TapDelayCnt;
-- Tap Delay Center
TapDelayCenter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (unsigned(pIDLY_CNT_Q) = SHIFT_RIGHT(pCenterTap, 1)) then
pDelayCenter <= '1';
else
pDelayCenter <= '0';
end if;
end if;
end process TapDelayCenter;
DelayIncWaitCounter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pDelayWaitRst = '1') then
pDelayWaitCnt <= 0;
else
pDelayWaitCnt <= pDelayWaitCnt + 1;
if (pDelayWaitCnt = kDelayWaitEnd - 1) then
pDelayWaitOvf <= '1';
else
pDelayWaitOvf <= '0';
end if;
end if;
end if;
end process DelayIncWaitCounter;
-- FSM
FSM_Sync: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRst = '1') then
pState <= ResetSt;
else
pState <= pStateNxt;
end if;
end if;
end process FSM_Sync;
--FSM Outputs
pTimeoutRst <= '0' when pState = IdleSt or pState = TokenSt else '1';
pCtlTknRst <= '0' when pState = TokenSt else '1';
pDelayWaitRst <= '0' when pState = DlyTstOvfSt or pState = DlyTstCenterSt else '1';
pEyeOpenRst <= '1' when pState = ResetSt or (pState = JtrZoneSt and pFoundEyeFlag = '0') else '0';
pEyeOpenEn <= '1' when pState = EyeOpenSt else '0';
--FSM Registered Outputs
FSM_RegOut: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pState = ResetSt) then
pIDLY_LD <= '1';
else
pIDLY_LD <= '0';
end if;
if (pState = DlyIncSt) then
pIDLY_INC <= '1';
pIDLY_CE <= '1';
elsif (pState = DlyDecSt) then
pIDLY_INC <= '0';
pIDLY_CE <= '1';
else
pIDLY_CE <= '0';
end if;
if (pState = AlignedSt) then
pAligned <= '1';
else
pAligned <= '0';
end if;
if (pState = AlignErrorSt) then
pError <= '1';
else
pError <= '0';
end if;
end if;
end process FSM_RegOut;
FSM_Flags: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
case (pState) is
when ResetSt =>
pFoundEyeFlag <= '0';
pFoundJtrFlag <= '0';
when JtrZoneSt =>
pFoundJtrFlag <= '1';
when EyeOpenSt =>
-- We consider the eye found, if we had found jitter before and the eye is at least kEyeOpenCntMin wide OR
-- We have not seen jitter yet (because tap 0 was already in the eye) and the eye is at least kEyeOpenCntEnough wide
if ((pFoundJtrFlag = '1' and pEyeOpenCnt = kEyeOpenCntMin) or (pEyeOpenCnt = kEyeOpenCntEnough)) then
pFoundEyeFlag <= '1';
end if;
when others =>
end case;
end if;
end process FSM_Flags;
FSM_NextState: process (pState, pBlankBegin, pTimeoutOvf, pCtlTknOvf, pDelayOvf, pDelayFastOvf, pDelayWaitOvf,
pEyeOpenCnt, pDelayCenter, pFoundEyeFlag, pTknFlagQ)
begin
pStateNxt <= pState; --default is to stay in current state
case (pState) is
when ResetSt =>
pStateNxt <= IdleSt;
when IdleSt => -- waiting for a token with timeout
if (pBlankBegin = '1') then
pStateNxt <= TokenSt;
elsif (pTimeoutOvf = '1') then
pStateNxt <= JtrZoneSt; -- we didn't find a proper blank, must be in jitter zone
end if;
when TokenSt => -- waiting for kCtlTknCount tokens with timeout
if (pTknFlagQ = '0') then
pStateNxt <= IdleSt;
elsif (pCtlTknOvf = '1') then
pStateNxt <= EyeOpenSt;
end if;
when JtrZoneSt =>
if (pFoundEyeFlag = '1') then
pStateNxt <= DlyDecSt; -- this jitter zone ends an open eye, go back to the middle of the eye
elsif (kUseFastAlgorithm and pDelayFastOvf = '1' and pFoundEyeFlag = '0') then
pStateNxt <= AlignErrorSt;
else
pStateNxt <= DlyIncSt;
end if;
when EyeOpenSt =>
-- If our eye is already kEyeOpenCntEnough wide, consider the search finished and consider the current tap value
-- the end of our eye = jitter zone
if (pEyeOpenCnt = kEyeOpenCntEnough) then
pStateNxt <= JtrZoneSt;
else
pStateNxt <= DlyIncSt;
end if;
when DlyIncSt =>
pStateNxt <= DlyTstOvfSt;
when DlyTstOvfSt =>
if (pDelayWaitOvf = '1') then
if (pDelayOvf = '1') then
pStateNxt <= AlignErrorSt; -- we went through all the delay taps
else
pStateNxt <= IdleSt;
end if;
end if;
when DlyDecSt =>
pStateNxt <= DlyTstCenterSt;
when DlyTstCenterSt =>
if (pDelayWaitOvf = '1') then
if (pDelayCenter = '1') then
pStateNxt <= AlignedSt; -- we went back to the center of the eye, done
else
pStateNxt <= DlyDecSt;
end if;
end if;
when AlignedSt =>
null; --stay here
when AlignErrorSt =>
null; --stay here
when others =>
pStateNxt <= ResetSt;
end case;
end process FSM_NextState;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: PhaseAlign.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 7 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module receives a DVI-encoded stream of 10-bit deserialized words
-- and tries to change the phase of the serial data to shift the sampling
-- event to the middle of the "eye", ie. the part of the bit period where
-- data is stable. Alignment is achieved by incrementing the tap count of
-- the IDELAYE2 primitives, delaying data by kIDLY_TapValuePs in each step.
-- In Artix-7 architecture each tap (step) accounts to 78 ps.
-- Data is considered valid when control tokens are recognized in the
-- stream. Alignment lock is achieved when the middle of the valid eye is
-- found. When this happens, pAligned will go high. If the whole range of
-- delay values had been exhausted and alignment lock could still not be
-- achieved, pError will go high. Resetting the module with pRst will
-- restart the alignment process.
-- The port pEyeSize provides an approximation of the width of the
-- eye in units of tap count. The larger the number, the better the signal
-- quality of the DVI stream.
-- Since the IDELAYE2 primitive only allows a fine alignment, the bitslip
-- feature of the ISERDES primitives complements the PhaseAlign module acting
-- as coarse alignment to find the 10-bit word boundary in the data stream.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PhaseAlign is
Generic (
kUseFastAlgorithm : boolean := false;
kCtlTknCount : natural := 128; --how many subsequent control tokens make a valid blank detection
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
pRst : in STD_LOGIC;
pTimeoutOvf : in std_logic; --50ms timeout expired
pTimeoutRst : out std_logic; --reset timeout
PixelClk : in STD_LOGIC;
pData : in STD_LOGIC_VECTOR (9 downto 0);
pIDLY_CE : out STD_LOGIC;
pIDLY_INC : out STD_LOGIC;
pIDLY_CNT : in STD_LOGIC_VECTOR (kIDLY_TapWidth-1 downto 0);
pIDLY_LD : out STD_LOGIC; --load default tap value
pAligned : out STD_LOGIC;
pError : out STD_LOGIC;
pEyeSize : out STD_LOGIC_VECTOR(kIDLY_TapWidth-1 downto 0));
end PhaseAlign;
architecture Behavioral of PhaseAlign is
-- Control Token Counter
signal pCtlTknCnt : natural range 0 to kCtlTknCount-1;
signal pCtlTknRst, pCtlTknOvf : std_logic;
-- Control Token Detection Pipeline
signal pTkn0Flag, pTkn1Flag, pTkn2Flag, pTkn3Flag : std_logic;
signal pTkn0FlagQ, pTkn1FlagQ, pTkn2FlagQ, pTkn3FlagQ : std_logic;
signal pTknFlag, pTknFlagQ, pBlankBegin : std_logic;
signal pDataQ : std_logic_vector(pData'high downto pData'low);
constant kTapCntEnd : std_logic_vector(pIDLY_CNT'range) := (others => '0');
constant kFastTapCntEnd : std_logic_vector(pIDLY_CNT'range) := std_logic_vector(to_unsigned(20, pIDLY_CNT'length)); -- fast search limit; if token not found in 20 taps, fail earlier and bitslip
signal pIDLY_CNT_Q : std_logic_vector(pIDLY_CNT'range);
signal pDelayOvf, pDelayFastOvf, pDelayCenter : std_logic;
-- IDELAY increment/decrement wait counter
-- CE, INC registered outputs + CNTVALUEOUT registered input + CNTVALUEOUT registered comparison
constant kDelayWaitEnd : natural := 3;
signal pDelayWaitCnt : natural range 0 to kDelayWaitEnd - 1;
signal pDelayWaitRst, pDelayWaitOvf : std_logic;
constant kEyeOpenCntMin : natural := 3;
constant kEyeOpenCntEnough : natural := 16;
signal pEyeOpenCnt : unsigned(kIDLY_TapWidth-1 downto 0);
signal pCenterTap : unsigned(kIDLY_TapWidth downto 0); -- 1 extra bit to increment with 1/2 for every open eye tap
signal pEyeOpenRst, pEyeOpenEn : std_logic;
--Flags
signal pFoundJtrFlag, pFoundEyeFlag : std_logic;
--FSM
--type state_t is (ResetSt, IdleSt, TokenSt, EyeOpenSt, JtrZoneSt, DlyIncSt, DlyTstOvfSt, DlyDecSt, DlyTstCenterSt, AlignedSt, AlignErrorSt);
subtype state_t is std_logic_vector(10 downto 0);
signal pState, pStateNxt : state_t;
-- Ugh, manual state encoding, since Vivado won't tell me the result of automatic encoding; we need this for debugging.
constant ResetSt : state_t := "00000000001";
constant IdleSt : state_t := "00000000010";
constant TokenSt : state_t := "00000000100";
constant EyeOpenSt : state_t := "00000001000";
constant JtrZoneSt : state_t := "00000010000";
constant DlyIncSt : state_t := "00000100000";
constant DlyTstOvfSt : state_t := "00001000000";
constant DlyDecSt : state_t := "00010000000";
constant DlyTstCenterSt : state_t :="00100000000";
constant AlignedSt : state_t := "01000000000";
constant AlignErrorSt : state_t := "10000000000";
begin
ControlTokenCounter: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pCtlTknRst = '1') then
pCtlTknCnt <= 0;
else
pCtlTknCnt <= pCtlTknCnt + 1;
-- Overflow
if (pCtlTknCnt = kCtlTknCount - 1) then
pCtlTknOvf <= '1';
else
pCtlTknOvf <= '0';
end if;
end if;
end if;
end process ControlTokenCounter;
-- Control Token Detection
pTkn0Flag <= '1' when pDataQ = kCtlTkn0 else '0';
pTkn1Flag <= '1' when pDataQ = kCtlTkn1 else '0';
pTkn2Flag <= '1' when pDataQ = kCtlTkn2 else '0';
pTkn3Flag <= '1' when pDataQ = kCtlTkn3 else '0';
-- Register pipeline
ControlTokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pDataQ <= pData; -- level 1
pTkn0FlagQ <= pTkn0Flag;
pTkn1FlagQ <= pTkn1Flag;
pTkn2FlagQ <= pTkn2Flag;
pTkn3FlagQ <= pTkn3Flag; -- level 2
pTknFlag <= pTkn0Flag or pTkn1Flag or pTkn2Flag or pTkn3Flag; -- level 3
pTknFlagQ <= pTknFlag;
pBlankBegin <= not pTknFlagQ and pTknFlag; -- level 4
end if;
end process ControlTokenDetect;
-- Open Eye Width Counter
EyeOpenCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pEyeOpenRst = '1') then
pEyeOpenCnt <= (others => '0');
pCenterTap <= unsigned(pIDLY_CNT_Q) & '1'; -- 1 extra bit for 1/2 increments; start with 1/2
elsif (pEyeOpenEn = '1') then
pEyeOpenCnt <= pEyeOpenCnt + 1;
pCenterTap <= pCenterTap + 1;
end if;
end if;
end process EyeOpenCnt;
pEyeSize <= std_logic_vector(pEyeOpenCnt);
-- Tap Delay Overflow
TapDelayCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
pIDLY_CNT_Q <= pIDLY_CNT;
if (pIDLY_CNT_Q = kTapCntEnd) then
pDelayOvf <= '1';
else
pDelayOvf <= '0';
end if;
if (pIDLY_CNT_Q = kFastTapCntEnd) then
pDelayFastOvf <= '1';
else
pDelayFastOvf <= '0';
end if;
end if;
end process TapDelayCnt;
-- Tap Delay Center
TapDelayCenter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (unsigned(pIDLY_CNT_Q) = SHIFT_RIGHT(pCenterTap, 1)) then
pDelayCenter <= '1';
else
pDelayCenter <= '0';
end if;
end if;
end process TapDelayCenter;
DelayIncWaitCounter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pDelayWaitRst = '1') then
pDelayWaitCnt <= 0;
else
pDelayWaitCnt <= pDelayWaitCnt + 1;
if (pDelayWaitCnt = kDelayWaitEnd - 1) then
pDelayWaitOvf <= '1';
else
pDelayWaitOvf <= '0';
end if;
end if;
end if;
end process DelayIncWaitCounter;
-- FSM
FSM_Sync: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRst = '1') then
pState <= ResetSt;
else
pState <= pStateNxt;
end if;
end if;
end process FSM_Sync;
--FSM Outputs
pTimeoutRst <= '0' when pState = IdleSt or pState = TokenSt else '1';
pCtlTknRst <= '0' when pState = TokenSt else '1';
pDelayWaitRst <= '0' when pState = DlyTstOvfSt or pState = DlyTstCenterSt else '1';
pEyeOpenRst <= '1' when pState = ResetSt or (pState = JtrZoneSt and pFoundEyeFlag = '0') else '0';
pEyeOpenEn <= '1' when pState = EyeOpenSt else '0';
--FSM Registered Outputs
FSM_RegOut: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pState = ResetSt) then
pIDLY_LD <= '1';
else
pIDLY_LD <= '0';
end if;
if (pState = DlyIncSt) then
pIDLY_INC <= '1';
pIDLY_CE <= '1';
elsif (pState = DlyDecSt) then
pIDLY_INC <= '0';
pIDLY_CE <= '1';
else
pIDLY_CE <= '0';
end if;
if (pState = AlignedSt) then
pAligned <= '1';
else
pAligned <= '0';
end if;
if (pState = AlignErrorSt) then
pError <= '1';
else
pError <= '0';
end if;
end if;
end process FSM_RegOut;
FSM_Flags: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
case (pState) is
when ResetSt =>
pFoundEyeFlag <= '0';
pFoundJtrFlag <= '0';
when JtrZoneSt =>
pFoundJtrFlag <= '1';
when EyeOpenSt =>
-- We consider the eye found, if we had found jitter before and the eye is at least kEyeOpenCntMin wide OR
-- We have not seen jitter yet (because tap 0 was already in the eye) and the eye is at least kEyeOpenCntEnough wide
if ((pFoundJtrFlag = '1' and pEyeOpenCnt = kEyeOpenCntMin) or (pEyeOpenCnt = kEyeOpenCntEnough)) then
pFoundEyeFlag <= '1';
end if;
when others =>
end case;
end if;
end process FSM_Flags;
FSM_NextState: process (pState, pBlankBegin, pTimeoutOvf, pCtlTknOvf, pDelayOvf, pDelayFastOvf, pDelayWaitOvf,
pEyeOpenCnt, pDelayCenter, pFoundEyeFlag, pTknFlagQ)
begin
pStateNxt <= pState; --default is to stay in current state
case (pState) is
when ResetSt =>
pStateNxt <= IdleSt;
when IdleSt => -- waiting for a token with timeout
if (pBlankBegin = '1') then
pStateNxt <= TokenSt;
elsif (pTimeoutOvf = '1') then
pStateNxt <= JtrZoneSt; -- we didn't find a proper blank, must be in jitter zone
end if;
when TokenSt => -- waiting for kCtlTknCount tokens with timeout
if (pTknFlagQ = '0') then
pStateNxt <= IdleSt;
elsif (pCtlTknOvf = '1') then
pStateNxt <= EyeOpenSt;
end if;
when JtrZoneSt =>
if (pFoundEyeFlag = '1') then
pStateNxt <= DlyDecSt; -- this jitter zone ends an open eye, go back to the middle of the eye
elsif (kUseFastAlgorithm and pDelayFastOvf = '1' and pFoundEyeFlag = '0') then
pStateNxt <= AlignErrorSt;
else
pStateNxt <= DlyIncSt;
end if;
when EyeOpenSt =>
-- If our eye is already kEyeOpenCntEnough wide, consider the search finished and consider the current tap value
-- the end of our eye = jitter zone
if (pEyeOpenCnt = kEyeOpenCntEnough) then
pStateNxt <= JtrZoneSt;
else
pStateNxt <= DlyIncSt;
end if;
when DlyIncSt =>
pStateNxt <= DlyTstOvfSt;
when DlyTstOvfSt =>
if (pDelayWaitOvf = '1') then
if (pDelayOvf = '1') then
pStateNxt <= AlignErrorSt; -- we went through all the delay taps
else
pStateNxt <= IdleSt;
end if;
end if;
when DlyDecSt =>
pStateNxt <= DlyTstCenterSt;
when DlyTstCenterSt =>
if (pDelayWaitOvf = '1') then
if (pDelayCenter = '1') then
pStateNxt <= AlignedSt; -- we went back to the center of the eye, done
else
pStateNxt <= DlyDecSt;
end if;
end if;
when AlignedSt =>
null; --stay here
when AlignErrorSt =>
null; --stay here
when others =>
pStateNxt <= ResetSt;
end case;
end process FSM_NextState;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: PhaseAlign.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 7 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module receives a DVI-encoded stream of 10-bit deserialized words
-- and tries to change the phase of the serial data to shift the sampling
-- event to the middle of the "eye", ie. the part of the bit period where
-- data is stable. Alignment is achieved by incrementing the tap count of
-- the IDELAYE2 primitives, delaying data by kIDLY_TapValuePs in each step.
-- In Artix-7 architecture each tap (step) accounts to 78 ps.
-- Data is considered valid when control tokens are recognized in the
-- stream. Alignment lock is achieved when the middle of the valid eye is
-- found. When this happens, pAligned will go high. If the whole range of
-- delay values had been exhausted and alignment lock could still not be
-- achieved, pError will go high. Resetting the module with pRst will
-- restart the alignment process.
-- The port pEyeSize provides an approximation of the width of the
-- eye in units of tap count. The larger the number, the better the signal
-- quality of the DVI stream.
-- Since the IDELAYE2 primitive only allows a fine alignment, the bitslip
-- feature of the ISERDES primitives complements the PhaseAlign module acting
-- as coarse alignment to find the 10-bit word boundary in the data stream.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PhaseAlign is
Generic (
kUseFastAlgorithm : boolean := false;
kCtlTknCount : natural := 128; --how many subsequent control tokens make a valid blank detection
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
pRst : in STD_LOGIC;
pTimeoutOvf : in std_logic; --50ms timeout expired
pTimeoutRst : out std_logic; --reset timeout
PixelClk : in STD_LOGIC;
pData : in STD_LOGIC_VECTOR (9 downto 0);
pIDLY_CE : out STD_LOGIC;
pIDLY_INC : out STD_LOGIC;
pIDLY_CNT : in STD_LOGIC_VECTOR (kIDLY_TapWidth-1 downto 0);
pIDLY_LD : out STD_LOGIC; --load default tap value
pAligned : out STD_LOGIC;
pError : out STD_LOGIC;
pEyeSize : out STD_LOGIC_VECTOR(kIDLY_TapWidth-1 downto 0));
end PhaseAlign;
architecture Behavioral of PhaseAlign is
-- Control Token Counter
signal pCtlTknCnt : natural range 0 to kCtlTknCount-1;
signal pCtlTknRst, pCtlTknOvf : std_logic;
-- Control Token Detection Pipeline
signal pTkn0Flag, pTkn1Flag, pTkn2Flag, pTkn3Flag : std_logic;
signal pTkn0FlagQ, pTkn1FlagQ, pTkn2FlagQ, pTkn3FlagQ : std_logic;
signal pTknFlag, pTknFlagQ, pBlankBegin : std_logic;
signal pDataQ : std_logic_vector(pData'high downto pData'low);
constant kTapCntEnd : std_logic_vector(pIDLY_CNT'range) := (others => '0');
constant kFastTapCntEnd : std_logic_vector(pIDLY_CNT'range) := std_logic_vector(to_unsigned(20, pIDLY_CNT'length)); -- fast search limit; if token not found in 20 taps, fail earlier and bitslip
signal pIDLY_CNT_Q : std_logic_vector(pIDLY_CNT'range);
signal pDelayOvf, pDelayFastOvf, pDelayCenter : std_logic;
-- IDELAY increment/decrement wait counter
-- CE, INC registered outputs + CNTVALUEOUT registered input + CNTVALUEOUT registered comparison
constant kDelayWaitEnd : natural := 3;
signal pDelayWaitCnt : natural range 0 to kDelayWaitEnd - 1;
signal pDelayWaitRst, pDelayWaitOvf : std_logic;
constant kEyeOpenCntMin : natural := 3;
constant kEyeOpenCntEnough : natural := 16;
signal pEyeOpenCnt : unsigned(kIDLY_TapWidth-1 downto 0);
signal pCenterTap : unsigned(kIDLY_TapWidth downto 0); -- 1 extra bit to increment with 1/2 for every open eye tap
signal pEyeOpenRst, pEyeOpenEn : std_logic;
--Flags
signal pFoundJtrFlag, pFoundEyeFlag : std_logic;
--FSM
--type state_t is (ResetSt, IdleSt, TokenSt, EyeOpenSt, JtrZoneSt, DlyIncSt, DlyTstOvfSt, DlyDecSt, DlyTstCenterSt, AlignedSt, AlignErrorSt);
subtype state_t is std_logic_vector(10 downto 0);
signal pState, pStateNxt : state_t;
-- Ugh, manual state encoding, since Vivado won't tell me the result of automatic encoding; we need this for debugging.
constant ResetSt : state_t := "00000000001";
constant IdleSt : state_t := "00000000010";
constant TokenSt : state_t := "00000000100";
constant EyeOpenSt : state_t := "00000001000";
constant JtrZoneSt : state_t := "00000010000";
constant DlyIncSt : state_t := "00000100000";
constant DlyTstOvfSt : state_t := "00001000000";
constant DlyDecSt : state_t := "00010000000";
constant DlyTstCenterSt : state_t :="00100000000";
constant AlignedSt : state_t := "01000000000";
constant AlignErrorSt : state_t := "10000000000";
begin
ControlTokenCounter: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pCtlTknRst = '1') then
pCtlTknCnt <= 0;
else
pCtlTknCnt <= pCtlTknCnt + 1;
-- Overflow
if (pCtlTknCnt = kCtlTknCount - 1) then
pCtlTknOvf <= '1';
else
pCtlTknOvf <= '0';
end if;
end if;
end if;
end process ControlTokenCounter;
-- Control Token Detection
pTkn0Flag <= '1' when pDataQ = kCtlTkn0 else '0';
pTkn1Flag <= '1' when pDataQ = kCtlTkn1 else '0';
pTkn2Flag <= '1' when pDataQ = kCtlTkn2 else '0';
pTkn3Flag <= '1' when pDataQ = kCtlTkn3 else '0';
-- Register pipeline
ControlTokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pDataQ <= pData; -- level 1
pTkn0FlagQ <= pTkn0Flag;
pTkn1FlagQ <= pTkn1Flag;
pTkn2FlagQ <= pTkn2Flag;
pTkn3FlagQ <= pTkn3Flag; -- level 2
pTknFlag <= pTkn0Flag or pTkn1Flag or pTkn2Flag or pTkn3Flag; -- level 3
pTknFlagQ <= pTknFlag;
pBlankBegin <= not pTknFlagQ and pTknFlag; -- level 4
end if;
end process ControlTokenDetect;
-- Open Eye Width Counter
EyeOpenCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pEyeOpenRst = '1') then
pEyeOpenCnt <= (others => '0');
pCenterTap <= unsigned(pIDLY_CNT_Q) & '1'; -- 1 extra bit for 1/2 increments; start with 1/2
elsif (pEyeOpenEn = '1') then
pEyeOpenCnt <= pEyeOpenCnt + 1;
pCenterTap <= pCenterTap + 1;
end if;
end if;
end process EyeOpenCnt;
pEyeSize <= std_logic_vector(pEyeOpenCnt);
-- Tap Delay Overflow
TapDelayCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
pIDLY_CNT_Q <= pIDLY_CNT;
if (pIDLY_CNT_Q = kTapCntEnd) then
pDelayOvf <= '1';
else
pDelayOvf <= '0';
end if;
if (pIDLY_CNT_Q = kFastTapCntEnd) then
pDelayFastOvf <= '1';
else
pDelayFastOvf <= '0';
end if;
end if;
end process TapDelayCnt;
-- Tap Delay Center
TapDelayCenter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (unsigned(pIDLY_CNT_Q) = SHIFT_RIGHT(pCenterTap, 1)) then
pDelayCenter <= '1';
else
pDelayCenter <= '0';
end if;
end if;
end process TapDelayCenter;
DelayIncWaitCounter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pDelayWaitRst = '1') then
pDelayWaitCnt <= 0;
else
pDelayWaitCnt <= pDelayWaitCnt + 1;
if (pDelayWaitCnt = kDelayWaitEnd - 1) then
pDelayWaitOvf <= '1';
else
pDelayWaitOvf <= '0';
end if;
end if;
end if;
end process DelayIncWaitCounter;
-- FSM
FSM_Sync: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRst = '1') then
pState <= ResetSt;
else
pState <= pStateNxt;
end if;
end if;
end process FSM_Sync;
--FSM Outputs
pTimeoutRst <= '0' when pState = IdleSt or pState = TokenSt else '1';
pCtlTknRst <= '0' when pState = TokenSt else '1';
pDelayWaitRst <= '0' when pState = DlyTstOvfSt or pState = DlyTstCenterSt else '1';
pEyeOpenRst <= '1' when pState = ResetSt or (pState = JtrZoneSt and pFoundEyeFlag = '0') else '0';
pEyeOpenEn <= '1' when pState = EyeOpenSt else '0';
--FSM Registered Outputs
FSM_RegOut: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pState = ResetSt) then
pIDLY_LD <= '1';
else
pIDLY_LD <= '0';
end if;
if (pState = DlyIncSt) then
pIDLY_INC <= '1';
pIDLY_CE <= '1';
elsif (pState = DlyDecSt) then
pIDLY_INC <= '0';
pIDLY_CE <= '1';
else
pIDLY_CE <= '0';
end if;
if (pState = AlignedSt) then
pAligned <= '1';
else
pAligned <= '0';
end if;
if (pState = AlignErrorSt) then
pError <= '1';
else
pError <= '0';
end if;
end if;
end process FSM_RegOut;
FSM_Flags: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
case (pState) is
when ResetSt =>
pFoundEyeFlag <= '0';
pFoundJtrFlag <= '0';
when JtrZoneSt =>
pFoundJtrFlag <= '1';
when EyeOpenSt =>
-- We consider the eye found, if we had found jitter before and the eye is at least kEyeOpenCntMin wide OR
-- We have not seen jitter yet (because tap 0 was already in the eye) and the eye is at least kEyeOpenCntEnough wide
if ((pFoundJtrFlag = '1' and pEyeOpenCnt = kEyeOpenCntMin) or (pEyeOpenCnt = kEyeOpenCntEnough)) then
pFoundEyeFlag <= '1';
end if;
when others =>
end case;
end if;
end process FSM_Flags;
FSM_NextState: process (pState, pBlankBegin, pTimeoutOvf, pCtlTknOvf, pDelayOvf, pDelayFastOvf, pDelayWaitOvf,
pEyeOpenCnt, pDelayCenter, pFoundEyeFlag, pTknFlagQ)
begin
pStateNxt <= pState; --default is to stay in current state
case (pState) is
when ResetSt =>
pStateNxt <= IdleSt;
when IdleSt => -- waiting for a token with timeout
if (pBlankBegin = '1') then
pStateNxt <= TokenSt;
elsif (pTimeoutOvf = '1') then
pStateNxt <= JtrZoneSt; -- we didn't find a proper blank, must be in jitter zone
end if;
when TokenSt => -- waiting for kCtlTknCount tokens with timeout
if (pTknFlagQ = '0') then
pStateNxt <= IdleSt;
elsif (pCtlTknOvf = '1') then
pStateNxt <= EyeOpenSt;
end if;
when JtrZoneSt =>
if (pFoundEyeFlag = '1') then
pStateNxt <= DlyDecSt; -- this jitter zone ends an open eye, go back to the middle of the eye
elsif (kUseFastAlgorithm and pDelayFastOvf = '1' and pFoundEyeFlag = '0') then
pStateNxt <= AlignErrorSt;
else
pStateNxt <= DlyIncSt;
end if;
when EyeOpenSt =>
-- If our eye is already kEyeOpenCntEnough wide, consider the search finished and consider the current tap value
-- the end of our eye = jitter zone
if (pEyeOpenCnt = kEyeOpenCntEnough) then
pStateNxt <= JtrZoneSt;
else
pStateNxt <= DlyIncSt;
end if;
when DlyIncSt =>
pStateNxt <= DlyTstOvfSt;
when DlyTstOvfSt =>
if (pDelayWaitOvf = '1') then
if (pDelayOvf = '1') then
pStateNxt <= AlignErrorSt; -- we went through all the delay taps
else
pStateNxt <= IdleSt;
end if;
end if;
when DlyDecSt =>
pStateNxt <= DlyTstCenterSt;
when DlyTstCenterSt =>
if (pDelayWaitOvf = '1') then
if (pDelayCenter = '1') then
pStateNxt <= AlignedSt; -- we went back to the center of the eye, done
else
pStateNxt <= DlyDecSt;
end if;
end if;
when AlignedSt =>
null; --stay here
when AlignErrorSt =>
null; --stay here
when others =>
pStateNxt <= ResetSt;
end case;
end process FSM_NextState;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: PhaseAlign.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 7 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module receives a DVI-encoded stream of 10-bit deserialized words
-- and tries to change the phase of the serial data to shift the sampling
-- event to the middle of the "eye", ie. the part of the bit period where
-- data is stable. Alignment is achieved by incrementing the tap count of
-- the IDELAYE2 primitives, delaying data by kIDLY_TapValuePs in each step.
-- In Artix-7 architecture each tap (step) accounts to 78 ps.
-- Data is considered valid when control tokens are recognized in the
-- stream. Alignment lock is achieved when the middle of the valid eye is
-- found. When this happens, pAligned will go high. If the whole range of
-- delay values had been exhausted and alignment lock could still not be
-- achieved, pError will go high. Resetting the module with pRst will
-- restart the alignment process.
-- The port pEyeSize provides an approximation of the width of the
-- eye in units of tap count. The larger the number, the better the signal
-- quality of the DVI stream.
-- Since the IDELAYE2 primitive only allows a fine alignment, the bitslip
-- feature of the ISERDES primitives complements the PhaseAlign module acting
-- as coarse alignment to find the 10-bit word boundary in the data stream.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PhaseAlign is
Generic (
kUseFastAlgorithm : boolean := false;
kCtlTknCount : natural := 128; --how many subsequent control tokens make a valid blank detection
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
pRst : in STD_LOGIC;
pTimeoutOvf : in std_logic; --50ms timeout expired
pTimeoutRst : out std_logic; --reset timeout
PixelClk : in STD_LOGIC;
pData : in STD_LOGIC_VECTOR (9 downto 0);
pIDLY_CE : out STD_LOGIC;
pIDLY_INC : out STD_LOGIC;
pIDLY_CNT : in STD_LOGIC_VECTOR (kIDLY_TapWidth-1 downto 0);
pIDLY_LD : out STD_LOGIC; --load default tap value
pAligned : out STD_LOGIC;
pError : out STD_LOGIC;
pEyeSize : out STD_LOGIC_VECTOR(kIDLY_TapWidth-1 downto 0));
end PhaseAlign;
architecture Behavioral of PhaseAlign is
-- Control Token Counter
signal pCtlTknCnt : natural range 0 to kCtlTknCount-1;
signal pCtlTknRst, pCtlTknOvf : std_logic;
-- Control Token Detection Pipeline
signal pTkn0Flag, pTkn1Flag, pTkn2Flag, pTkn3Flag : std_logic;
signal pTkn0FlagQ, pTkn1FlagQ, pTkn2FlagQ, pTkn3FlagQ : std_logic;
signal pTknFlag, pTknFlagQ, pBlankBegin : std_logic;
signal pDataQ : std_logic_vector(pData'high downto pData'low);
constant kTapCntEnd : std_logic_vector(pIDLY_CNT'range) := (others => '0');
constant kFastTapCntEnd : std_logic_vector(pIDLY_CNT'range) := std_logic_vector(to_unsigned(20, pIDLY_CNT'length)); -- fast search limit; if token not found in 20 taps, fail earlier and bitslip
signal pIDLY_CNT_Q : std_logic_vector(pIDLY_CNT'range);
signal pDelayOvf, pDelayFastOvf, pDelayCenter : std_logic;
-- IDELAY increment/decrement wait counter
-- CE, INC registered outputs + CNTVALUEOUT registered input + CNTVALUEOUT registered comparison
constant kDelayWaitEnd : natural := 3;
signal pDelayWaitCnt : natural range 0 to kDelayWaitEnd - 1;
signal pDelayWaitRst, pDelayWaitOvf : std_logic;
constant kEyeOpenCntMin : natural := 3;
constant kEyeOpenCntEnough : natural := 16;
signal pEyeOpenCnt : unsigned(kIDLY_TapWidth-1 downto 0);
signal pCenterTap : unsigned(kIDLY_TapWidth downto 0); -- 1 extra bit to increment with 1/2 for every open eye tap
signal pEyeOpenRst, pEyeOpenEn : std_logic;
--Flags
signal pFoundJtrFlag, pFoundEyeFlag : std_logic;
--FSM
--type state_t is (ResetSt, IdleSt, TokenSt, EyeOpenSt, JtrZoneSt, DlyIncSt, DlyTstOvfSt, DlyDecSt, DlyTstCenterSt, AlignedSt, AlignErrorSt);
subtype state_t is std_logic_vector(10 downto 0);
signal pState, pStateNxt : state_t;
-- Ugh, manual state encoding, since Vivado won't tell me the result of automatic encoding; we need this for debugging.
constant ResetSt : state_t := "00000000001";
constant IdleSt : state_t := "00000000010";
constant TokenSt : state_t := "00000000100";
constant EyeOpenSt : state_t := "00000001000";
constant JtrZoneSt : state_t := "00000010000";
constant DlyIncSt : state_t := "00000100000";
constant DlyTstOvfSt : state_t := "00001000000";
constant DlyDecSt : state_t := "00010000000";
constant DlyTstCenterSt : state_t :="00100000000";
constant AlignedSt : state_t := "01000000000";
constant AlignErrorSt : state_t := "10000000000";
begin
ControlTokenCounter: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pCtlTknRst = '1') then
pCtlTknCnt <= 0;
else
pCtlTknCnt <= pCtlTknCnt + 1;
-- Overflow
if (pCtlTknCnt = kCtlTknCount - 1) then
pCtlTknOvf <= '1';
else
pCtlTknOvf <= '0';
end if;
end if;
end if;
end process ControlTokenCounter;
-- Control Token Detection
pTkn0Flag <= '1' when pDataQ = kCtlTkn0 else '0';
pTkn1Flag <= '1' when pDataQ = kCtlTkn1 else '0';
pTkn2Flag <= '1' when pDataQ = kCtlTkn2 else '0';
pTkn3Flag <= '1' when pDataQ = kCtlTkn3 else '0';
-- Register pipeline
ControlTokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pDataQ <= pData; -- level 1
pTkn0FlagQ <= pTkn0Flag;
pTkn1FlagQ <= pTkn1Flag;
pTkn2FlagQ <= pTkn2Flag;
pTkn3FlagQ <= pTkn3Flag; -- level 2
pTknFlag <= pTkn0Flag or pTkn1Flag or pTkn2Flag or pTkn3Flag; -- level 3
pTknFlagQ <= pTknFlag;
pBlankBegin <= not pTknFlagQ and pTknFlag; -- level 4
end if;
end process ControlTokenDetect;
-- Open Eye Width Counter
EyeOpenCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pEyeOpenRst = '1') then
pEyeOpenCnt <= (others => '0');
pCenterTap <= unsigned(pIDLY_CNT_Q) & '1'; -- 1 extra bit for 1/2 increments; start with 1/2
elsif (pEyeOpenEn = '1') then
pEyeOpenCnt <= pEyeOpenCnt + 1;
pCenterTap <= pCenterTap + 1;
end if;
end if;
end process EyeOpenCnt;
pEyeSize <= std_logic_vector(pEyeOpenCnt);
-- Tap Delay Overflow
TapDelayCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
pIDLY_CNT_Q <= pIDLY_CNT;
if (pIDLY_CNT_Q = kTapCntEnd) then
pDelayOvf <= '1';
else
pDelayOvf <= '0';
end if;
if (pIDLY_CNT_Q = kFastTapCntEnd) then
pDelayFastOvf <= '1';
else
pDelayFastOvf <= '0';
end if;
end if;
end process TapDelayCnt;
-- Tap Delay Center
TapDelayCenter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (unsigned(pIDLY_CNT_Q) = SHIFT_RIGHT(pCenterTap, 1)) then
pDelayCenter <= '1';
else
pDelayCenter <= '0';
end if;
end if;
end process TapDelayCenter;
DelayIncWaitCounter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pDelayWaitRst = '1') then
pDelayWaitCnt <= 0;
else
pDelayWaitCnt <= pDelayWaitCnt + 1;
if (pDelayWaitCnt = kDelayWaitEnd - 1) then
pDelayWaitOvf <= '1';
else
pDelayWaitOvf <= '0';
end if;
end if;
end if;
end process DelayIncWaitCounter;
-- FSM
FSM_Sync: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRst = '1') then
pState <= ResetSt;
else
pState <= pStateNxt;
end if;
end if;
end process FSM_Sync;
--FSM Outputs
pTimeoutRst <= '0' when pState = IdleSt or pState = TokenSt else '1';
pCtlTknRst <= '0' when pState = TokenSt else '1';
pDelayWaitRst <= '0' when pState = DlyTstOvfSt or pState = DlyTstCenterSt else '1';
pEyeOpenRst <= '1' when pState = ResetSt or (pState = JtrZoneSt and pFoundEyeFlag = '0') else '0';
pEyeOpenEn <= '1' when pState = EyeOpenSt else '0';
--FSM Registered Outputs
FSM_RegOut: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pState = ResetSt) then
pIDLY_LD <= '1';
else
pIDLY_LD <= '0';
end if;
if (pState = DlyIncSt) then
pIDLY_INC <= '1';
pIDLY_CE <= '1';
elsif (pState = DlyDecSt) then
pIDLY_INC <= '0';
pIDLY_CE <= '1';
else
pIDLY_CE <= '0';
end if;
if (pState = AlignedSt) then
pAligned <= '1';
else
pAligned <= '0';
end if;
if (pState = AlignErrorSt) then
pError <= '1';
else
pError <= '0';
end if;
end if;
end process FSM_RegOut;
FSM_Flags: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
case (pState) is
when ResetSt =>
pFoundEyeFlag <= '0';
pFoundJtrFlag <= '0';
when JtrZoneSt =>
pFoundJtrFlag <= '1';
when EyeOpenSt =>
-- We consider the eye found, if we had found jitter before and the eye is at least kEyeOpenCntMin wide OR
-- We have not seen jitter yet (because tap 0 was already in the eye) and the eye is at least kEyeOpenCntEnough wide
if ((pFoundJtrFlag = '1' and pEyeOpenCnt = kEyeOpenCntMin) or (pEyeOpenCnt = kEyeOpenCntEnough)) then
pFoundEyeFlag <= '1';
end if;
when others =>
end case;
end if;
end process FSM_Flags;
FSM_NextState: process (pState, pBlankBegin, pTimeoutOvf, pCtlTknOvf, pDelayOvf, pDelayFastOvf, pDelayWaitOvf,
pEyeOpenCnt, pDelayCenter, pFoundEyeFlag, pTknFlagQ)
begin
pStateNxt <= pState; --default is to stay in current state
case (pState) is
when ResetSt =>
pStateNxt <= IdleSt;
when IdleSt => -- waiting for a token with timeout
if (pBlankBegin = '1') then
pStateNxt <= TokenSt;
elsif (pTimeoutOvf = '1') then
pStateNxt <= JtrZoneSt; -- we didn't find a proper blank, must be in jitter zone
end if;
when TokenSt => -- waiting for kCtlTknCount tokens with timeout
if (pTknFlagQ = '0') then
pStateNxt <= IdleSt;
elsif (pCtlTknOvf = '1') then
pStateNxt <= EyeOpenSt;
end if;
when JtrZoneSt =>
if (pFoundEyeFlag = '1') then
pStateNxt <= DlyDecSt; -- this jitter zone ends an open eye, go back to the middle of the eye
elsif (kUseFastAlgorithm and pDelayFastOvf = '1' and pFoundEyeFlag = '0') then
pStateNxt <= AlignErrorSt;
else
pStateNxt <= DlyIncSt;
end if;
when EyeOpenSt =>
-- If our eye is already kEyeOpenCntEnough wide, consider the search finished and consider the current tap value
-- the end of our eye = jitter zone
if (pEyeOpenCnt = kEyeOpenCntEnough) then
pStateNxt <= JtrZoneSt;
else
pStateNxt <= DlyIncSt;
end if;
when DlyIncSt =>
pStateNxt <= DlyTstOvfSt;
when DlyTstOvfSt =>
if (pDelayWaitOvf = '1') then
if (pDelayOvf = '1') then
pStateNxt <= AlignErrorSt; -- we went through all the delay taps
else
pStateNxt <= IdleSt;
end if;
end if;
when DlyDecSt =>
pStateNxt <= DlyTstCenterSt;
when DlyTstCenterSt =>
if (pDelayWaitOvf = '1') then
if (pDelayCenter = '1') then
pStateNxt <= AlignedSt; -- we went back to the center of the eye, done
else
pStateNxt <= DlyDecSt;
end if;
end if;
when AlignedSt =>
null; --stay here
when AlignErrorSt =>
null; --stay here
when others =>
pStateNxt <= ResetSt;
end case;
end process FSM_NextState;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: PhaseAlign.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 7 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module receives a DVI-encoded stream of 10-bit deserialized words
-- and tries to change the phase of the serial data to shift the sampling
-- event to the middle of the "eye", ie. the part of the bit period where
-- data is stable. Alignment is achieved by incrementing the tap count of
-- the IDELAYE2 primitives, delaying data by kIDLY_TapValuePs in each step.
-- In Artix-7 architecture each tap (step) accounts to 78 ps.
-- Data is considered valid when control tokens are recognized in the
-- stream. Alignment lock is achieved when the middle of the valid eye is
-- found. When this happens, pAligned will go high. If the whole range of
-- delay values had been exhausted and alignment lock could still not be
-- achieved, pError will go high. Resetting the module with pRst will
-- restart the alignment process.
-- The port pEyeSize provides an approximation of the width of the
-- eye in units of tap count. The larger the number, the better the signal
-- quality of the DVI stream.
-- Since the IDELAYE2 primitive only allows a fine alignment, the bitslip
-- feature of the ISERDES primitives complements the PhaseAlign module acting
-- as coarse alignment to find the 10-bit word boundary in the data stream.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PhaseAlign is
Generic (
kUseFastAlgorithm : boolean := false;
kCtlTknCount : natural := 128; --how many subsequent control tokens make a valid blank detection
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
pRst : in STD_LOGIC;
pTimeoutOvf : in std_logic; --50ms timeout expired
pTimeoutRst : out std_logic; --reset timeout
PixelClk : in STD_LOGIC;
pData : in STD_LOGIC_VECTOR (9 downto 0);
pIDLY_CE : out STD_LOGIC;
pIDLY_INC : out STD_LOGIC;
pIDLY_CNT : in STD_LOGIC_VECTOR (kIDLY_TapWidth-1 downto 0);
pIDLY_LD : out STD_LOGIC; --load default tap value
pAligned : out STD_LOGIC;
pError : out STD_LOGIC;
pEyeSize : out STD_LOGIC_VECTOR(kIDLY_TapWidth-1 downto 0));
end PhaseAlign;
architecture Behavioral of PhaseAlign is
-- Control Token Counter
signal pCtlTknCnt : natural range 0 to kCtlTknCount-1;
signal pCtlTknRst, pCtlTknOvf : std_logic;
-- Control Token Detection Pipeline
signal pTkn0Flag, pTkn1Flag, pTkn2Flag, pTkn3Flag : std_logic;
signal pTkn0FlagQ, pTkn1FlagQ, pTkn2FlagQ, pTkn3FlagQ : std_logic;
signal pTknFlag, pTknFlagQ, pBlankBegin : std_logic;
signal pDataQ : std_logic_vector(pData'high downto pData'low);
constant kTapCntEnd : std_logic_vector(pIDLY_CNT'range) := (others => '0');
constant kFastTapCntEnd : std_logic_vector(pIDLY_CNT'range) := std_logic_vector(to_unsigned(20, pIDLY_CNT'length)); -- fast search limit; if token not found in 20 taps, fail earlier and bitslip
signal pIDLY_CNT_Q : std_logic_vector(pIDLY_CNT'range);
signal pDelayOvf, pDelayFastOvf, pDelayCenter : std_logic;
-- IDELAY increment/decrement wait counter
-- CE, INC registered outputs + CNTVALUEOUT registered input + CNTVALUEOUT registered comparison
constant kDelayWaitEnd : natural := 3;
signal pDelayWaitCnt : natural range 0 to kDelayWaitEnd - 1;
signal pDelayWaitRst, pDelayWaitOvf : std_logic;
constant kEyeOpenCntMin : natural := 3;
constant kEyeOpenCntEnough : natural := 16;
signal pEyeOpenCnt : unsigned(kIDLY_TapWidth-1 downto 0);
signal pCenterTap : unsigned(kIDLY_TapWidth downto 0); -- 1 extra bit to increment with 1/2 for every open eye tap
signal pEyeOpenRst, pEyeOpenEn : std_logic;
--Flags
signal pFoundJtrFlag, pFoundEyeFlag : std_logic;
--FSM
--type state_t is (ResetSt, IdleSt, TokenSt, EyeOpenSt, JtrZoneSt, DlyIncSt, DlyTstOvfSt, DlyDecSt, DlyTstCenterSt, AlignedSt, AlignErrorSt);
subtype state_t is std_logic_vector(10 downto 0);
signal pState, pStateNxt : state_t;
-- Ugh, manual state encoding, since Vivado won't tell me the result of automatic encoding; we need this for debugging.
constant ResetSt : state_t := "00000000001";
constant IdleSt : state_t := "00000000010";
constant TokenSt : state_t := "00000000100";
constant EyeOpenSt : state_t := "00000001000";
constant JtrZoneSt : state_t := "00000010000";
constant DlyIncSt : state_t := "00000100000";
constant DlyTstOvfSt : state_t := "00001000000";
constant DlyDecSt : state_t := "00010000000";
constant DlyTstCenterSt : state_t :="00100000000";
constant AlignedSt : state_t := "01000000000";
constant AlignErrorSt : state_t := "10000000000";
begin
ControlTokenCounter: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pCtlTknRst = '1') then
pCtlTknCnt <= 0;
else
pCtlTknCnt <= pCtlTknCnt + 1;
-- Overflow
if (pCtlTknCnt = kCtlTknCount - 1) then
pCtlTknOvf <= '1';
else
pCtlTknOvf <= '0';
end if;
end if;
end if;
end process ControlTokenCounter;
-- Control Token Detection
pTkn0Flag <= '1' when pDataQ = kCtlTkn0 else '0';
pTkn1Flag <= '1' when pDataQ = kCtlTkn1 else '0';
pTkn2Flag <= '1' when pDataQ = kCtlTkn2 else '0';
pTkn3Flag <= '1' when pDataQ = kCtlTkn3 else '0';
-- Register pipeline
ControlTokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pDataQ <= pData; -- level 1
pTkn0FlagQ <= pTkn0Flag;
pTkn1FlagQ <= pTkn1Flag;
pTkn2FlagQ <= pTkn2Flag;
pTkn3FlagQ <= pTkn3Flag; -- level 2
pTknFlag <= pTkn0Flag or pTkn1Flag or pTkn2Flag or pTkn3Flag; -- level 3
pTknFlagQ <= pTknFlag;
pBlankBegin <= not pTknFlagQ and pTknFlag; -- level 4
end if;
end process ControlTokenDetect;
-- Open Eye Width Counter
EyeOpenCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pEyeOpenRst = '1') then
pEyeOpenCnt <= (others => '0');
pCenterTap <= unsigned(pIDLY_CNT_Q) & '1'; -- 1 extra bit for 1/2 increments; start with 1/2
elsif (pEyeOpenEn = '1') then
pEyeOpenCnt <= pEyeOpenCnt + 1;
pCenterTap <= pCenterTap + 1;
end if;
end if;
end process EyeOpenCnt;
pEyeSize <= std_logic_vector(pEyeOpenCnt);
-- Tap Delay Overflow
TapDelayCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
pIDLY_CNT_Q <= pIDLY_CNT;
if (pIDLY_CNT_Q = kTapCntEnd) then
pDelayOvf <= '1';
else
pDelayOvf <= '0';
end if;
if (pIDLY_CNT_Q = kFastTapCntEnd) then
pDelayFastOvf <= '1';
else
pDelayFastOvf <= '0';
end if;
end if;
end process TapDelayCnt;
-- Tap Delay Center
TapDelayCenter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (unsigned(pIDLY_CNT_Q) = SHIFT_RIGHT(pCenterTap, 1)) then
pDelayCenter <= '1';
else
pDelayCenter <= '0';
end if;
end if;
end process TapDelayCenter;
DelayIncWaitCounter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pDelayWaitRst = '1') then
pDelayWaitCnt <= 0;
else
pDelayWaitCnt <= pDelayWaitCnt + 1;
if (pDelayWaitCnt = kDelayWaitEnd - 1) then
pDelayWaitOvf <= '1';
else
pDelayWaitOvf <= '0';
end if;
end if;
end if;
end process DelayIncWaitCounter;
-- FSM
FSM_Sync: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRst = '1') then
pState <= ResetSt;
else
pState <= pStateNxt;
end if;
end if;
end process FSM_Sync;
--FSM Outputs
pTimeoutRst <= '0' when pState = IdleSt or pState = TokenSt else '1';
pCtlTknRst <= '0' when pState = TokenSt else '1';
pDelayWaitRst <= '0' when pState = DlyTstOvfSt or pState = DlyTstCenterSt else '1';
pEyeOpenRst <= '1' when pState = ResetSt or (pState = JtrZoneSt and pFoundEyeFlag = '0') else '0';
pEyeOpenEn <= '1' when pState = EyeOpenSt else '0';
--FSM Registered Outputs
FSM_RegOut: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pState = ResetSt) then
pIDLY_LD <= '1';
else
pIDLY_LD <= '0';
end if;
if (pState = DlyIncSt) then
pIDLY_INC <= '1';
pIDLY_CE <= '1';
elsif (pState = DlyDecSt) then
pIDLY_INC <= '0';
pIDLY_CE <= '1';
else
pIDLY_CE <= '0';
end if;
if (pState = AlignedSt) then
pAligned <= '1';
else
pAligned <= '0';
end if;
if (pState = AlignErrorSt) then
pError <= '1';
else
pError <= '0';
end if;
end if;
end process FSM_RegOut;
FSM_Flags: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
case (pState) is
when ResetSt =>
pFoundEyeFlag <= '0';
pFoundJtrFlag <= '0';
when JtrZoneSt =>
pFoundJtrFlag <= '1';
when EyeOpenSt =>
-- We consider the eye found, if we had found jitter before and the eye is at least kEyeOpenCntMin wide OR
-- We have not seen jitter yet (because tap 0 was already in the eye) and the eye is at least kEyeOpenCntEnough wide
if ((pFoundJtrFlag = '1' and pEyeOpenCnt = kEyeOpenCntMin) or (pEyeOpenCnt = kEyeOpenCntEnough)) then
pFoundEyeFlag <= '1';
end if;
when others =>
end case;
end if;
end process FSM_Flags;
FSM_NextState: process (pState, pBlankBegin, pTimeoutOvf, pCtlTknOvf, pDelayOvf, pDelayFastOvf, pDelayWaitOvf,
pEyeOpenCnt, pDelayCenter, pFoundEyeFlag, pTknFlagQ)
begin
pStateNxt <= pState; --default is to stay in current state
case (pState) is
when ResetSt =>
pStateNxt <= IdleSt;
when IdleSt => -- waiting for a token with timeout
if (pBlankBegin = '1') then
pStateNxt <= TokenSt;
elsif (pTimeoutOvf = '1') then
pStateNxt <= JtrZoneSt; -- we didn't find a proper blank, must be in jitter zone
end if;
when TokenSt => -- waiting for kCtlTknCount tokens with timeout
if (pTknFlagQ = '0') then
pStateNxt <= IdleSt;
elsif (pCtlTknOvf = '1') then
pStateNxt <= EyeOpenSt;
end if;
when JtrZoneSt =>
if (pFoundEyeFlag = '1') then
pStateNxt <= DlyDecSt; -- this jitter zone ends an open eye, go back to the middle of the eye
elsif (kUseFastAlgorithm and pDelayFastOvf = '1' and pFoundEyeFlag = '0') then
pStateNxt <= AlignErrorSt;
else
pStateNxt <= DlyIncSt;
end if;
when EyeOpenSt =>
-- If our eye is already kEyeOpenCntEnough wide, consider the search finished and consider the current tap value
-- the end of our eye = jitter zone
if (pEyeOpenCnt = kEyeOpenCntEnough) then
pStateNxt <= JtrZoneSt;
else
pStateNxt <= DlyIncSt;
end if;
when DlyIncSt =>
pStateNxt <= DlyTstOvfSt;
when DlyTstOvfSt =>
if (pDelayWaitOvf = '1') then
if (pDelayOvf = '1') then
pStateNxt <= AlignErrorSt; -- we went through all the delay taps
else
pStateNxt <= IdleSt;
end if;
end if;
when DlyDecSt =>
pStateNxt <= DlyTstCenterSt;
when DlyTstCenterSt =>
if (pDelayWaitOvf = '1') then
if (pDelayCenter = '1') then
pStateNxt <= AlignedSt; -- we went back to the center of the eye, done
else
pStateNxt <= DlyDecSt;
end if;
end if;
when AlignedSt =>
null; --stay here
when AlignErrorSt =>
null; --stay here
when others =>
pStateNxt <= ResetSt;
end case;
end process FSM_NextState;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity compressed is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
wa0_en : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
wa0_data : in std_logic_vector(31 downto 0)
);
end compressed;
architecture augh of compressed is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity compressed is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
wa0_en : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
wa0_data : in std_logic_vector(31 downto 0)
);
end compressed;
architecture augh of compressed is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity compressed is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
wa0_en : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
wa0_data : in std_logic_vector(31 downto 0)
);
end compressed;
architecture augh of compressed is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
------------------------------------------------------------------------------
-- irq_gen.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: irq_gen.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed May 30 12:34:16 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library my_ipif;
use my_ipif.ipif_pkg.SLV64_ARRAY_TYPE;
use my_ipif.ipif_pkg.INTEGER_ARRAY_TYPE;
use my_ipif.ipif_pkg.calc_start_ce_index;
use my_ipif.ipif_pkg.calc_num_ce;
-- library proc_common_v3_00_a;
-- use proc_common_v3_00_a.proc_common_pkg.all;
-- use proc_common_v3_00_a.ipif_pkg.all;
--
-- library axi_lite_ipif_v1_01_a;
-- use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library irq_gen_v1_00_a;
use irq_gen_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity irq_gen is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
IRQ : out std_logic;
VIO_IRQ_TICK : in std_logic;
vio_rise_edge : out std_logic;
slv_reg : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity irq_gen;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of irq_gen is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity my_ipif.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity irq_gen_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
IRQ => IRQ,
VIO_IRQ_TICK => VIO_IRQ_TICK,
vio_rise_edge => vio_rise_edge,
slv_reg => slv_reg,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
------------------------------------------------------------------------------
-- irq_gen.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: irq_gen.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed May 30 12:34:16 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library my_ipif;
use my_ipif.ipif_pkg.SLV64_ARRAY_TYPE;
use my_ipif.ipif_pkg.INTEGER_ARRAY_TYPE;
use my_ipif.ipif_pkg.calc_start_ce_index;
use my_ipif.ipif_pkg.calc_num_ce;
-- library proc_common_v3_00_a;
-- use proc_common_v3_00_a.proc_common_pkg.all;
-- use proc_common_v3_00_a.ipif_pkg.all;
--
-- library axi_lite_ipif_v1_01_a;
-- use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library irq_gen_v1_00_a;
use irq_gen_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity irq_gen is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
IRQ : out std_logic;
VIO_IRQ_TICK : in std_logic;
vio_rise_edge : out std_logic;
slv_reg : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity irq_gen;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of irq_gen is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity my_ipif.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity irq_gen_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
IRQ => IRQ,
VIO_IRQ_TICK => VIO_IRQ_TICK,
vio_rise_edge => vio_rise_edge,
slv_reg => slv_reg,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
architecture RTL of FIFO is
begin
CASE_LABEL : case data generate
when 0 =>
a <= z;
when 1 =>
a <= c;
when 2 =>
a <= b;
when others =>
null;
end generate;
-- Violations below
CASE_LABEL : case data generate
when 0 =>
a <= z;
when 1 =>
a <= c;
when 2 =>
a <= b;
when others =>
null;
end generate;
end;
|
ARCHITECTURE behavior OF tb_I2CCore IS
-- DEFINE FREQUENCY HERE!
CONSTANT InputFrequency : integer := 100 * 1000 * 1000; -- 100 MHz
-- SELECT TESTCASE HERE!
-- | TestCase | Description | T_sim |
-- |---------------------------------------------------------------------|
-- | Case 1 | Address + Nack + Stop | 150 us |
-- | Case 2 | Address + Ack + DoTransfer_i=0 | 150 us |
-- | Case 3 | Address + Ack + 2 Bytes Writing (getting Ack) | 320 us |
-- | Case 4 | Address + Ack + 2 Bytes Writing + Nack on 2nd | 320 us |
-- | Case 5 | Address + 1 Byte Reading + Sending NAck + Stop | 240 us |
-- | Case 6 | Address + 2 Bytes Reading + Ack 1st + NAck 2nd | 330 us |
-- | Case 7 | Address with Bus-Collision | 70 us |
-- |---------------------------------------------------------------------|
CONSTANT TestCase : Integer := 6;
--------------------------------------------------------------------------------
-- Configuration done - don't edit the following
--------------------------------------------------------------------------------
CONSTANT HalfClkPer : time := (1 sec)/(2*InputFrequency); -- 100 MHz => 5 ns
CONSTANT Divider : integer := (InputFrequency / (200 * 1000));
-- Component Declaration
COMPONENT i2ccore IS
Generic (Divider200_g : integer := (100 * 1000 * 1000 / (200 * 1000))-1;
Divider800_g : integer := (100 * 1000 * 1000 / (800 * 1000))-1);
Port ( Reset_i : in STD_LOGIC;
Clk_i : in STD_LOGIC;
Data_i : in STD_LOGIC_VECTOR (7 downto 0);
Data_o : out STD_LOGIC_VECTOR (7 downto 0);
DoTransfer_i : in STD_LOGIC;
ReadWrite_n_i : in STD_LOGIC;
AckTx_i : in STD_LOGIC;
AckRx_o : out STD_LOGIC;
Busy_o : out STD_LOGIC;
ByteReady_o : out STD_LOGIC;
BusErr_o : out STD_LOGIC;
SDA_o : out STD_LOGIC;
SDA_i : in STD_LOGIC;
SCL_o : out STD_LOGIC;
F100_400_n_i : in STD_LOGIC);
END COMPONENT;
-- Signal Declaration
TYPE ByteArray is array(3 downto 0) of std_logic_vector(7 downto 0);
SIGNAL WriteMemory : ByteArray := ("10011010","11010010","11010010","01010101");
SIGNAL ReadMemory : ByteArray;
SIGNAL Clk_i : std_logic;
SIGNAL Reset_i : std_logic;
SIGNAL Data_i : std_logic_vector (7 downto 0);
SIGNAL Data_o : std_logic_vector (7 downto 0);
SIGNAL DoTransfer_i : std_logic := '0';
SIGNAL ReadWrite_n_i: std_logic := '0';
SIGNAL AckRx_o : std_logic := '0';
SIGNAL AckTx_i : std_logic := '0';
SIGNAL Busy_o : std_logic := '0';
SIGNAL ByteReady_o : std_logic := '0';
SIGNAL BusErr_o : std_logic := '0';
SIGNAL SDA_o : std_logic := '1';
SIGNAL SDA_i : std_logic := '1';
SIGNAL SCL_o : std_logic := '1';
SIGNAL F100_400_n_i : std_logic := '1';
-- Wating Procedure
PROCEDURE wait4risingEdges(CONSTANT edges : IN INTEGER) IS
BEGIN
FOR edge IN 1 TO Divider*edges LOOP
wait until rising_edge(Clk_i);
END LOOP;
END PROCEDURE;
BEGIN
-- Component Instantiation
mycore : i2ccore
GENERIC MAP ( Divider200_g => Divider-1,
Divider800_g => (Divider/4)-1)
PORT MAP ( Reset_i => Reset_i,
Clk_i => Clk_i,
Data_i => Data_i,
Data_o => Data_o,
DoTransfer_i => DoTransfer_i,
ReadWrite_n_i => ReadWrite_n_i,
AckRx_o => AckRx_o,
AckTx_i => AckTx_i,
Busy_o => Busy_o,
ByteReady_o => ByteReady_o,
BusErr_o => BusErr_o,
SDA_o => SDA_o,
SDA_i => SDA_i,
SCL_o => SCL_o,
F100_400_n_i => F100_400_n_i);
-- PROCESS to generate Clock Signal (e.g. 100 MHz)
clock: PROCESS
BEGIN
Clk_i <= '0';
wait for HalfClkPer;
Clk_i <= '1';
wait for HalfClkPer;
END PROCESS clock;
-- Process to generate ControlCommands
CTRL : PROCESS
BEGIN
-- Reset
Reset_i <= '1';
wait until rising_edge(Clk_i);
Reset_i <= '0';
-- Apply Addressdata to Data_i
Data_i <= WriteMemory(3);
-- Check if all Outputs are set proper after Reset
assert SCL_o = '1' AND SDA_o = '1' AND AckRx_o = '0' AND ByteReady_o = '0' AND BusErr_o = '0' AND Busy_o = '0'
report "Output Signals not proper after Reset!"
severity warning;
DoTransfer_i <= '1';
wait4risingEdges(1);
-- Checking Start-Signal
assert SCL_o = '1' AND SDA_o = '1'
report "Error in 1st part of Start-Signal!"
severity warning;
wait4risingEdges(1);
assert SCL_o = '1' AND SDA_o = '0'
report "Error in 2nd part of Start-Signal!"
severity warning;
-- Running selected Testcase --
-- ========================= --
case TestCase is
-- Case 1: Address + Nack + Stop T_Sim 150 us
when 1 => DoTransfer_i <= '0';
for i in 7 downto 0 loop
SDA_i <= WriteMemory(3)(i);
wait4risingEdges(2);
end loop;
-- Check ByteReady_o
wait until rising_edge(Clk_i);
assert ByteReady_o = '1'
report "ByteReady_o is not set after core sent the last Bit!"
severity warning;
SDA_i <='1'; -- NAck
wait4risingEdges(2);
-- Check if Core sets AckRx_o
assert AckRx_o = '0'
report "Core did set AckRx_o unexpected!"
severity warning;
--------------------------------------------------------------------
-- Case 2: Address + Ack + DoTransfer_i=0 T_Sim 150 us
when 2 => DoTransfer_i <= '0';
for i in 7 downto 0 loop
SDA_i <= WriteMemory(3)(i);
wait4risingEdges(2);
end loop;
-- Check ByteReady_o
wait until rising_edge(Clk_i);
assert ByteReady_o = '1'
report "ByteReady_o is not set after Core sent the last Bit!"
severity warning;
SDA_i <= '0'; -- Ack
wait4risingEdges(2);
-- Check if Core sets AckRx_o
assert AckRx_o = '1'
report "Core did not set AckRx_o (in time)!"
severity warning;
--------------------------------------------------------------------
-- Case 3: Address + Ack + 2 Bytes Writing (with Acks) T_Sim 320 us
when 3 => for i in 7 downto 0 loop
SDA_i <= WriteMemory(3)(i);
wait4risingEdges(2);
end loop;
-- Check ByteReady_o
wait until rising_edge(Clk_i);
assert ByteReady_o = '1'
report "ByteReady_o is not set after Core sent the last Bit (Addressbyte)!"
severity warning;
SDA_i <= '0'; -- Ack
wait4risingEdges(2);
-- Check if Core sets AckRx_o
assert AckRx_o = '1'
report "Core did not set AckRx_o (in time) (Addressbyte)!"
severity warning;
Data_i <= WriteMemory(2); -- Applying 1st Databyte to write
for i in 7 downto 0 loop
SDA_i <= WriteMemory(2)(i);
wait4risingEdges(2);
end loop;
-- Check ByteReady_o
assert ByteReady_o = '1'
report "ByteReady_o is not set after Core sent the last Bit (Databyte 1)!"
severity warning;
SDA_i <= '0'; -- Ack
wait4risingEdges(2);
-- Check if Core sets AckRx_o
assert AckRx_o = '1'
report "Core did not set AckRx_o (in time) (Databyte 1)!"
severity warning;
Data_i <= WriteMemory(1); -- Applying 2nd Databyte to write
for i in 7 downto 0 loop
SDA_i <= WriteMemory(1)(i);
wait4risingEdges(2);
end loop;
DoTransfer_i <= '0';
-- Check ByteReady_o
assert ByteReady_o = '1'
report "ByteReady_o is not set after Core sent the last Bit (Databyte 2)!"
severity warning;
SDA_i <= '0'; -- Ack
wait4risingEdges(2);
-- Check if Core sets AckRx_o
assert AckRx_o = '1'
report "Core did not set AckRx_o (in time) (Databyte 2)!"
severity warning;
SDA_i <= '1';
--------------------------------------------------------------------
-- Case 4: Addr. + Ack + 2 Bytes Writing + Nack on 2nd T_Sim 320 us
when 4 => for i in 7 downto 0 loop
SDA_i <= WriteMemory(3)(i);
wait4risingEdges(2);
end loop;
-- Check ByteReady_o
wait until rising_edge(Clk_i);
assert ByteReady_o = '1'
report "ByteReady_o is not set after Core sent the last Bit (Addressbyte)!"
severity warning;
SDA_i <= '0'; -- Ack
wait4risingEdges(2);
-- Check if Core sets AckRx_o
assert AckRx_o = '1'
report "Core did not set AckRx_o (in time) (Addressbyte)!"
severity warning;
Data_i <= WriteMemory(2); -- Applying 1st Databyte to write
for i in 7 downto 0 loop
SDA_i <= WriteMemory(2)(i);
wait4risingEdges(2);
end loop;
-- Check ByteReady_o
assert ByteReady_o = '1'
report "ByteReady_o is not set after Core sent the last Bit (Databyte 1)!"
severity warning;
SDA_i <= '0'; -- Ack
wait4risingEdges(2);
-- Check if Core sets AckRx_o
assert AckRx_o = '1'
report "Core did not set AckRx_o (in time) (Databyte 1)!"
severity warning;
Data_i <= WriteMemory(1); -- Applying 2nd Databyte to write
for i in 7 downto 0 loop
SDA_i <= WriteMemory(1)(i);
wait4risingEdges(2);
end loop;
DoTransfer_i <= '0';
-- Check ByteReady_o
assert ByteReady_o = '1'
report "ByteReady_o is not set after Core sent the last Bit (Databyte 2)!"
severity warning;
SDA_i <= '1'; -- NAck
wait4risingEdges(2);
-- Check if Core sets AckRx_o
assert AckRx_o = '0'
report "Core did set AckRx_o unexpected (Databyte 2)!"
severity warning;
--------------------------------------------------------------------
-- Case 5: Addr + 1 Byte Reading + Sending NAck + Stop T_Sim 240 us
when 5 => ReadWrite_n_i <= '1'; -- Reading MODE
AckTx_i <= '0'; -- Send NAck after reading first Databyte
for i in 7 downto 0 loop
SDA_i <= WriteMemory(3)(i);
wait4risingEdges(2);
end loop;
-- Check ByteReady_o
wait until rising_edge(Clk_i);
assert ByteReady_o = '1'
report "ByteReady_o is not set after Core sent the last Bit (Addressbyte)!"
severity warning;
SDA_i <= '0'; -- Ack
wait4risingEdges(2);
-- Check if Core sets AckRx_o
assert AckRx_o = '1'
report "Core did not set AckRx_o (in time) (Addressbyte)!"
severity warning;
-- Data to read: 11100111
SDA_i <= '1';
wait4risingEdges(6); -- Data to read: 3 x '1'
SDA_i <= '0';
wait4risingEdges(4); -- Data to read: 2 x '0'
SDA_i <= '1';
wait4risingEdges(6); -- Data to read: 3 x '1'
-- Check if SDA_o was stable at '1' during reading-phase
assert SDA_o = '1' AND SDA_o'stable(32*HalfClkPer*Divider)
report "SDA_o not stable at '1' while reading!"
severity warning;
-- Check ByteReady_o
assert ByteReady_o = '1'
report "ByteReady_o is not set after Core read the last Bit!"
severity warning;
-- Check if Data was read correctly
assert Data_o = "11100111"
report "Data was not read correctly!"
severity warning;
DoTransfer_i <= '0';
ReadMemory(3) <= Data_o;
-- Check if Core writes Ack
wait4risingEdges(2);
assert SDA_o = '1'
report "Core did write Ack unexpected!"
severity warning;
--------------------------------------------------------------------
-- Case 6: Addr + 2 Bytes Reading + Ack 1st + NAck 2nd T_Sim 330 us
when 6 => ReadWrite_n_i <= '1'; -- Reading MODE
AckTx_i <= '1'; -- Send Ack after reading first Databyte
for i in 7 downto 0 loop
SDA_i <= WriteMemory(3)(i);
wait4risingEdges(2);
end loop;
-- Check ByteReady_o
wait until rising_edge(Clk_i);
assert ByteReady_o = '1'
report "ByteReady_o is not set after Core sent the last Bit (Addressbyte)!"
severity warning;
SDA_i <= '0'; -- Ack
wait4risingEdges(2);
-- Check if Core sets AckRx_o
assert AckRx_o = '1'
report "Core did not set AckRx_o (in time) (Addressbyte)!"
severity warning;
-- Reading 1st Byte: Data to read: 11100111
SDA_i <= '1';
wait4risingEdges(6); -- Data to read: 3 x '1'
SDA_i <= '0';
wait4risingEdges(4); -- Data to read: 2 x '0'
SDA_i <= '1';
wait4risingEdges(6); -- Data to read: 3 x '1'
-- Check if SDA_o was stable at '1' during reading-phase
assert SDA_o = '1' AND SDA_o'stable(32*HalfClkPer*Divider)
report "SDA_o not stable at '1' while reading!"
severity warning;
-- Check ByteReady_o
assert ByteReady_o = '1'
report "ByteReady_o is not set after Core read the last Bit!"
severity warning;
-- Check if Data was read correctly
assert Data_o = "11100111"
report "Data was not read correctly!"
severity warning;
ReadMemory(3) <= Data_o;
-- Check if Core writes Ack
wait4risingEdges(2);
assert SDA_o = '0'
report "Core did not write Ack!"
severity warning;
-- Reading 2nd Byte: Data to read: 11111111
AckTx_i <= '0'; -- Send NAck after reading 2nd Databyte
SDA_i <= '1';
wait4risingEdges(16); -- Data to read: 8 x '1'
DoTransfer_i <= '0';
-- Check if SDA_o was stable at '1' during reading-phase
assert SDA_o = '1' AND SDA_o'stable(32*HalfClkPer*Divider)
report "SDA_o not stable at '1' while reading!"
severity warning;
-- Check ByteReady_o
assert ByteReady_o = '1'
report "ByteReady_o is not set after Core read the last Bit!"
severity warning;
-- Check if Data was read correctly
assert Data_o = "11111111"
report "Data was not read correctly!"
severity warning;
ReadMemory(2) <= Data_o;
-- Check if Core writes Ack
wait4risingEdges(2);
assert SDA_o = '1'
report "Core did write Ack unexpected!"
severity warning;
--------------------------------------------------------------------
-- Case 7: Address with Bus-Collision T_Sim 50 us
when 7 => DoTransfer_i <= '0';
wait4risingEdges(2);
SDA_i <= '0';
wait4risingEdges(4);
SDA_i <= '1';
wait4risingEdges(2);
SDA_i <= '0';
wait4risingEdges(1);
-- Checking if Core recognizes Collision on 2nd Bit and sets BusErr_o
wait until rising_edge(Clk_i);
assert BusErr_o = '1'
report "Bus Collision was not detected/reported (in time)!"
severity warning;
when others =>
END CASE;
case TestCase is
when 7 => --nothing to do
when others => -- Checking Stop-Signal
wait4risingEdges(1);
assert SCL_o = '0' AND SDA_o = '0'
report "Error in 1st part of Stop-Signal!"
severity warning;
wait4risingEdges(1);
assert SCL_o = '1' AND SDA_o = '0'
report "Error in 2nd part of Stop-Signal!"
severity warning;
-- Check if all Outputs are set proper after Operation finished
wait4risingEdges(1);
assert SCL_o = '1' AND SDA_o = '1' AND AckRx_o = '0' AND ByteReady_o = '0' AND Busy_o = '0'
report "Output Signals not proper after testcase / Core did not finish!"
severity warning;
END CASE;
wait;
END PROCESS;
END;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbctrl
-- File: apbctrl.vhd
-- Author: Cobham Gaisler
-- Description: AMBA AHB/APB bridge with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
entity apbctrlx is
generic (
hindex0 : integer := 0;
haddr0 : integer := 0;
hmask0 : integer := 16#fff#;
hindex1 : integer := 0;
haddr1 : integer := 0;
hmask1 : integer := 16#fff#;
nslaves : integer range 1 to NAPBSLV := NAPBSLV;
nports : integer range 1 to 2 := 2;
wprot : integer range 0 to 1 := 0;
debug : integer range 0 to 2 := 2;
icheck : integer range 0 to 1 := 1;
enbusmon : integer range 0 to 1 := 0;
asserterr : integer range 0 to 1 := 0;
assertwarn : integer range 0 to 1 := 0;
pslvdisable : integer := 0;
mcheck : integer range 0 to 1 := 1;
ccheck : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_slv_in_vector_type(0 to nports-1);
ahbo : out ahb_slv_out_vector_type(0 to nports-1);
apbi : out apb_slv_in_vector;
apbo : in apb_slv_out_vector;
wp : in std_logic_vector(0 to nports-1) := (others => '0');
wpv : in std_logic_vector(256*nports-1 downto 0) := (others => '0')
);
end;
architecture rtl of apbctrlx is
type ivector_type is array (natural range <>) of integer range 0 to NAHBMST-1;
type pvector_type is array (natural range <>) of std_logic_vector(0 to NAPBSLV-1);
type pinteger_type is array (natural range <>) of integer range 0 to nslaves-1;
type ahb_config_vector_type is array (natural range <>) of ahb_config_type;
constant apbmax : integer := 19;
constant multiport: integer := conv_integer(conv_std_logic(nports>1));
constant VERSION : amba_version_type := 1;
constant hindex : ivector_type(0 to 1) := (hindex0, hindex1);
constant hconfig : ahb_config_vector_type(0 to 1) := (
(0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_APBMST, 0, VERSION, 0),
4 => ahb_membar(haddr0, '0', '0', hmask0),
others => zero32),
(0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_APBMST, 0, VERSION, 0),
4 => ahb_membar(haddr1, '0', '0', hmask1),
others => zero32));
constant IOAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(haddr0, 12);
constant IOMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(hmask0, 12);
constant IOAREA1 : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(haddr1, 12);
constant IOMSK1 : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(hmask1, 12);
type port_reg_type is record
haddr : std_logic_vector(apbmax downto 0); -- address bus
hwrite : std_logic; -- read/write
hready : std_logic; -- ready
penable : std_logic;
psel : std_logic;
prdata : std_logic_vector(31 downto 0); -- read data
pwdata : std_logic_vector(31 downto 0); -- write data
state : std_logic_vector(1 downto 0); -- state
cfgsel : std_logic;
hresp : std_logic_vector(1 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
constant RES_PORT : port_reg_type :=
(haddr => (others => '0'), hwrite => '0', hready => '1', penable => '0',
psel => '0', prdata => (others => '0'), pwdata => (others => '0'),
state => (others => '0'), cfgsel => '0', hresp => (others => '0'),
hmaster => (others => '0'));
type port_reg_vector is array (natural range <>) of port_reg_type;
type reg_type is record
p : port_reg_vector(0 to nports-1);
end record;
constant RES : reg_type := (
p => (others => RES_PORT));
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
signal r, rin : reg_type;
--pragma translate_off
signal lapbi : apb_slv_in_type;
--pragma translate_on
begin
comb : process(ahbi, apbo, wp, wpv, r, rst)
variable v : reg_type;
variable psel : pvector_type(0 to nports-1);
variable pwdata : std_logic_vector(31 downto 0);
variable apbaddr : std_logic_vector(31 downto 0);
variable pirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable nslave : pinteger_type(0 to nports-1);
variable bnslave : std_logic_vector(3 downto 0);
variable vapbi : apb_slv_in_vector_type(0 to nports-1);
variable lwprot : std_logic_vector(0 to 1);
variable lwprotv : std_logic_vector(15 downto 0);
begin
v := r; pirq := (others => '0');
for j in 0 to nports-1 loop
v.p(j).psel := '0'; v.p(j).penable := '0'; psel(j) := (others => '0');
-- Decode APB slave
for i in 0 to nslaves-1 loop
if ((apbo(i).pconfig(1)(1 downto 0) = "01") and
((apbo(i).pconfig(1)(31 downto 20) and apbo(i).pconfig(1)(15 downto 4)) =
(r.p(j).haddr(19 downto 8) and apbo(i).pconfig(1)(15 downto 4))))
then psel(j)(i) := '1'; end if;
end loop;
bnslave(0) := psel(j)( 1) or psel(j)( 3) or psel(j)( 5) or psel(j)( 7) or
psel(j)( 9) or psel(j)(11) or psel(j)(13) or psel(j)(15);
bnslave(1) := psel(j)( 2) or psel(j)( 3) or psel(j)( 6) or psel(j)( 7) or
psel(j)(10) or psel(j)(11) or psel(j)(14) or psel(j)(15);
bnslave(2) := psel(j)( 4) or psel(j)( 5) or psel(j)( 6) or psel(j)( 7) or
psel(j)(12) or psel(j)(13) or psel(j)(14) or psel(j)(15);
bnslave(3) := psel(j)( 8) or psel(j) (9) or psel(j)(10) or psel(j)(11) or
psel(j)(12) or psel(j)(13) or psel(j)(14) or psel(j)(15);
nslave(j) := conv_integer(bnslave);
-- write protection
if wprot = 1 then
--lwprotv := wpv(15+16*nslave(j)+256*j downto 16*nslave(j)+256*j);
--lwprot(j) := lwprotv(conv_integer(r.p(j).hmaster));
lwprot(j) := wpv(16*nslave(j)+256*j+conv_integer(r.p(j).hmaster));
else
lwprotv := (others => '0');
lwprot(j) := '0';
v.p(j).hmaster := (others => '0');
v.p(j).hresp := HRESP_OKAY;
end if;
-- detect start of cycle
if (ahbi(j).hready = '1') then
if ((ahbi(j).htrans = HTRANS_NONSEQ) or (ahbi(j).htrans = HTRANS_SEQ)) and
(ahbi(j).hsel(hindex(j)) = '1')
then
v.p(j).hready := '0'; v.p(j).hwrite := ahbi(j).hwrite;
v.p(j).haddr(apbmax downto 0) := ahbi(j).haddr(apbmax downto 0);
v.p(j).state := "01"; v.p(j).psel := not ahbi(j).hwrite;
if wprot = 1 then
v.p(j).hmaster := ahbi(j).hmaster;
end if;
end if;
end if;
case r.p(j).state is
when "00" => -- idle
v.p(j).hresp := HRESP_OKAY;
when "01" =>
if (multiport = 1) and (
(j = 1 and (r.p(0).penable = '0' or r.p(1*multiport).hwrite = '0') and (r.p(0).psel and orv(psel(0) and psel(1*multiport))) = '1') or
(j = 0 and r.p(1*multiport).penable = '1' and (r.p(1*multiport).psel and not r.p(0).hwrite and orv(psel(0) and psel(1*multiport))) = '1')) then
v.p(j).psel := '1';
else
if r.p(j).hwrite = '0' then v.p(j).penable := '1';
else v.p(j).pwdata := ahbreadword(ahbi(j).hwdata, r.p(j).haddr(4 downto 2)); end if;
v.p(j).psel := '1'; v.p(j).state := "10";
end if;
if wprot = 1 and r.p(j).hwrite = '1' and (wp(j*multiport) or lwprot(j*multiport)) = '1' then
v.p(j).state := "11";
v.p(j).psel := '0';
v.p(j).hresp := HRESP_ERROR;
end if;
when "11" =>
if wprot = 1 then
v.p(j).hready := '1';
v.p(j).state := "00";
else
null;
end if;
when others =>
if (multiport = 1) and (
(j = 1 and r.p(1*multiport).penable = '0' and (r.p(0).psel and orv(psel(0) and psel(1*multiport))) = '1') or
(j = 0 and r.p(1*multiport).penable = '1' and (r.p(1*multiport).psel and orv(psel(0) and psel(1*multiport))) = '1')) then
v.p(j).psel := '1';
else
if r.p(j).penable = '0' then v.p(j).psel := '1'; v.p(j).penable := '1'; end if;
v.p(j).state := "00"; v.p(j).hready := '1';
end if;
end case;
-- Decode PNP access
if (r.p(j).haddr(19 downto 12) = "11111111") then
v.p(j).cfgsel := '1'; psel(j) := (others => '0'); v.p(j).penable := '0';
else v.p(j).cfgsel := '0'; end if;
v.p(j).prdata := apbo(nslave(j)).prdata;
if r.p(j).cfgsel = '1' then
v.p(j).prdata := apbo(conv_integer(r.p(j).haddr(6 downto 3))).pconfig(conv_integer(r.p(j).haddr(2 downto 2)));
if nslaves <= conv_integer(r.p(j).haddr(6 downto 3)) then
v.p(j).prdata := (others => '0');
end if;
end if;
end loop;
for i in 0 to nslaves-1 loop pirq := pirq or apbo(i).pirq; end loop;
-- AHB respons
for j in 0 to nports-1 loop
ahbo(j).hready <= r.p(j).hready;
ahbo(j).hrdata <= ahbdrivedata(r.p(j).prdata);
ahbo(j).hirq <= pirq;
ahbo(j).hresp <= r.p(j).hresp;
ahbo(j).hindex <= hindex(j);
ahbo(j).hconfig <= hconfig(j);
ahbo(j).hsplit <= (others => '0');
end loop;
-- Reset
if (not RESET_ALL) and (rst = '0') then
for j in 0 to nports-1 loop
v.p(j).penable := RES.p(j).penable;
v.p(j).hready := RES.p(j).hready;
v.p(j).psel := RES.p(j).psel;
v.p(j).state := RES.p(j).state;
v.p(j).hwrite := RES.p(j).hwrite;
v.p(j).hresp := RES.p(j).hresp;
-- pragma translate_off
v.p(j).haddr := RES.p(j).haddr;
-- pragma translate_on
end loop;
end if;
rin <= v;
-- drive APB bus
for j in 0 to NAPBSLV-1 loop
apbaddr := (others => '0');
apbi(j).psel <= (others => '0');
if multiport = 0 and j < nslaves then
apbaddr(apbmax downto 0) := r.p(0).haddr(apbmax downto 0);
apbi(j).pwdata <= r.p(0).pwdata;
apbi(j).pwrite <= r.p(0).hwrite;
apbi(j).penable <= r.p(0).penable;
if r.p(0).psel = '1' then
apbi(j).psel <= psel(0);
end if;
elsif j < nslaves then
if (psel(0)(j) and r.p(0).psel and not (r.p(1*multiport).penable and r.p(1*multiport).psel and orv(psel(0) and psel(1*multiport)))) = '1' then
apbaddr(apbmax downto 0) := r.p(0).haddr(apbmax downto 0);
apbi(j).pwdata <= r.p(0).pwdata;
apbi(j).pwrite <= r.p(0).hwrite;
apbi(j).penable <= r.p(0).penable;
apbi(j).psel(j) <= '1';
elsif (psel(1*multiport)(j) and r.p(1*multiport).psel) = '1' then
apbaddr(apbmax downto 0) := r.p(1*multiport).haddr(apbmax downto 0);
apbi(j).pwdata <= r.p(1*multiport).pwdata;
apbi(j).pwrite <= r.p(1*multiport).hwrite;
apbi(j).penable <= r.p(1*multiport).penable;
apbi(j).psel(j) <= '1';
else
apbi(j).pwdata <= r.p(0).pwdata;
apbi(j).pwrite <= '0';
apbi(j).penable <= '0';
end if;
else
apbi(j).pwdata <= (others => '0');
apbi(j).pwrite <= '0';
apbi(j).penable <= '0';
end if;
apbi(j).paddr <= apbaddr;
apbi(j).pirq <= ahbi(0).hirq;
apbi(j).testen <= ahbi(0).testen;
apbi(j).testoen <= ahbi(0).testoen;
apbi(j).scanen <= ahbi(0).scanen;
apbi(j).testrst <= ahbi(0).testrst;
apbi(j).testin <= ahbi(0).testin;
end loop;
--pragma translate_off
lapbi.paddr <= apbaddr;
lapbi.pwdata <= r.p(0).pwdata;
lapbi.pwrite <= r.p(0).hwrite;
lapbi.penable <= r.p(0).penable;
lapbi.pirq <= ahbi(0).hirq;
for i in 0 to nslaves-1 loop lapbi.psel(i) <= (psel(0)(i) and r.p(0).psel) or (psel(1*multiport)(i) and r.p(1*multiport).psel); end loop;
--pragma translate_on
end process;
reg : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
-- pragma translate_off
mon0 : if enbusmon /= 0 generate
mon : apbmon
generic map(
asserterr => asserterr,
assertwarn => assertwarn,
pslvdisable => pslvdisable,
napb => nslaves)
port map(
rst => rst,
clk => clk,
apbi => lapbi,
apbo => apbo,
err => open);
end generate;
diag : process
type apb_memarea_type is record
start : std_logic_vector(31 downto 20);
stop : std_logic_vector(31 downto 20);
end record;
type memmap_type is array (0 to nslaves-1) of apb_memarea_type;
variable k : integer;
variable mask : std_logic_vector(11 downto 0);
variable device : std_logic_vector(11 downto 0);
variable devicei : integer;
variable vendor : std_logic_vector( 7 downto 0);
variable vendori : integer;
variable iosize : integer;
variable iounit : string(1 to 5) := "byte ";
variable memstart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
variable memstart1 : std_logic_vector(11 downto 0) := IOAREA1 and IOMSK1;
variable L1 : line := new string'("");
variable memmap : memmap_type;
begin
wait for 3 ns;
if debug > 0 then
if nports = 2 then
print("apbctrl: APB Bridge at " & tost(memstart) & "00000 (Port1 at " & tost(memstart1) & "00000) rev 1");
else
print("apbctrl: APB Bridge at " & tost(memstart) & "00000 rev 1");
end if;
end if;
for i in 0 to nslaves-1 loop
vendor := apbo(i).pconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
if debug > 1 then
device := apbo(i).pconfig(0)(23 downto 12);
devicei := conv_integer(device);
std.textio.write(L1, "apbctrl: slv" & tost(i) & ": " &
iptable(vendori).vendordesc & iptable(vendori).device_table(devicei));
std.textio.writeline(OUTPUT, L1);
mask := apbo(i).pconfig(1)(15 downto 4);
k := 0;
while (k<15) and (mask(k) = '0') loop k := k+1; end loop;
iosize := 256 * 2**k; iounit := "byte ";
if (iosize > 1023) then iosize := iosize/1024; iounit := "kbyte"; end if;
print("apbctrl: I/O ports at " &
tost(memstart & (apbo(i).pconfig(1)(31 downto 20) and
apbo(i).pconfig(1)(15 downto 4))) &
"00, size " & tost(iosize) & " " & iounit);
if mcheck /= 0 then
memmap(i).start := (apbo(i).pconfig(1)(31 downto 20) and
apbo(i).pconfig(1)(15 downto 4));
memmap(i).stop := memmap(i).start + 2**k;
end if;
end if;
assert (apbo(i).pindex = i) or (icheck = 0)
report "APB slave index error on slave " & tost(i) &
". Detected index value " & tost(apbo(i).pindex) severity failure;
if mcheck /= 0 then
for j in 0 to i loop
if memmap(i).start /= memmap(i).stop then
assert ((memmap(i).start >= memmap(j).stop) or
(memmap(i).stop <= memmap(j).start) or (i = j))
report "APB slave " & tost(i) & " memory area" &
" intersects with APB slave " & tost(j) & " memory area."
severity failure;
end if;
end loop;
end if;
else
for j in 0 to NAPBCFG-1 loop
assert (apbo(i).pconfig(j) = zx or ccheck = 0)
report "APB slave " & tost(i) & " appears to be disabled, " &
"but the config record is not driven to zero"
severity warning;
end loop;
end if;
end loop;
if nslaves < NAPBSLV then
for i in nslaves to NAPBSLV-1 loop
for j in 0 to NAPBCFG-1 loop
assert (apbo(i).pconfig(j) = zx or ccheck = 0)
report "APB slave " & tost(i) & " is outside the range of decoded " &
"slave indexes but the config record is not driven to zero"
severity warning;
end loop; -- j
end loop; -- i
end if;
wait;
end process;
-- pragma translate_on
end;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
generic map (
G_GEN_1 => 1,
G_GEN_2 => 2,
G_GEN_3 => 3
);
end architecture ARCH;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_13.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- not in book
entity computer_system is
end entity computer_system;
library stimulus;
use stimulus.stimulus_generators.all;
-- end not in book
architecture structure of computer_system is
component decoder_2_to_4 is
generic ( prop_delay : delay_length );
port ( in0, in1 : in bit;
out0, out1, out2, out3 : out bit );
end component decoder_2_to_4;
-- . . .
-- not in book
signal addr : bit_vector(5 downto 4);
signal interface_a_select, interface_b_select,
interface_c_select, interface_d_select : bit;
-- end not in book
begin
interface_decoder : component decoder_2_to_4
generic map ( prop_delay => 4 ns )
port map ( in0 => addr(4), in1 => addr(5),
out0 => interface_a_select, out1 => interface_b_select,
out2 => interface_c_select, out3 => interface_d_select );
-- . . .
-- not in book
all_possible_values(addr, 10 ns);
-- end not in book
end architecture structure;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_13.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- not in book
entity computer_system is
end entity computer_system;
library stimulus;
use stimulus.stimulus_generators.all;
-- end not in book
architecture structure of computer_system is
component decoder_2_to_4 is
generic ( prop_delay : delay_length );
port ( in0, in1 : in bit;
out0, out1, out2, out3 : out bit );
end component decoder_2_to_4;
-- . . .
-- not in book
signal addr : bit_vector(5 downto 4);
signal interface_a_select, interface_b_select,
interface_c_select, interface_d_select : bit;
-- end not in book
begin
interface_decoder : component decoder_2_to_4
generic map ( prop_delay => 4 ns )
port map ( in0 => addr(4), in1 => addr(5),
out0 => interface_a_select, out1 => interface_b_select,
out2 => interface_c_select, out3 => interface_d_select );
-- . . .
-- not in book
all_possible_values(addr, 10 ns);
-- end not in book
end architecture structure;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_13.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- not in book
entity computer_system is
end entity computer_system;
library stimulus;
use stimulus.stimulus_generators.all;
-- end not in book
architecture structure of computer_system is
component decoder_2_to_4 is
generic ( prop_delay : delay_length );
port ( in0, in1 : in bit;
out0, out1, out2, out3 : out bit );
end component decoder_2_to_4;
-- . . .
-- not in book
signal addr : bit_vector(5 downto 4);
signal interface_a_select, interface_b_select,
interface_c_select, interface_d_select : bit;
-- end not in book
begin
interface_decoder : component decoder_2_to_4
generic map ( prop_delay => 4 ns )
port map ( in0 => addr(4), in1 => addr(5),
out0 => interface_a_select, out1 => interface_b_select,
out2 => interface_c_select, out3 => interface_d_select );
-- . . .
-- not in book
all_possible_values(addr, 10 ns);
-- end not in book
end architecture structure;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:44:11 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_xadc_wiz_0_0/system_xadc_wiz_0_0_stub.vhdl
-- Design : system_xadc_wiz_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_xadc_wiz_0_0 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
vauxp0 : in STD_LOGIC;
vauxn0 : in STD_LOGIC;
vauxp1 : in STD_LOGIC;
vauxn1 : in STD_LOGIC;
vauxp2 : in STD_LOGIC;
vauxn2 : in STD_LOGIC;
vauxp4 : in STD_LOGIC;
vauxn4 : in STD_LOGIC;
vauxp5 : in STD_LOGIC;
vauxn5 : in STD_LOGIC;
vauxp6 : in STD_LOGIC;
vauxn6 : in STD_LOGIC;
vauxp7 : in STD_LOGIC;
vauxn7 : in STD_LOGIC;
vauxp9 : in STD_LOGIC;
vauxn9 : in STD_LOGIC;
vauxp10 : in STD_LOGIC;
vauxn10 : in STD_LOGIC;
vauxp12 : in STD_LOGIC;
vauxn12 : in STD_LOGIC;
vauxp13 : in STD_LOGIC;
vauxn13 : in STD_LOGIC;
vauxp14 : in STD_LOGIC;
vauxn14 : in STD_LOGIC;
vauxp15 : in STD_LOGIC;
vauxn15 : in STD_LOGIC;
busy_out : out STD_LOGIC;
channel_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
eoc_out : out STD_LOGIC;
eos_out : out STD_LOGIC;
vccaux_alarm_out : out STD_LOGIC;
vccint_alarm_out : out STD_LOGIC;
user_temp_alarm_out : out STD_LOGIC;
alarm_out : out STD_LOGIC;
temp_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
vp_in : in STD_LOGIC;
vn_in : in STD_LOGIC
);
end system_xadc_wiz_0_0;
architecture stub of system_xadc_wiz_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[10:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[10:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,vauxp0,vauxn0,vauxp1,vauxn1,vauxp2,vauxn2,vauxp4,vauxn4,vauxp5,vauxn5,vauxp6,vauxn6,vauxp7,vauxn7,vauxp9,vauxn9,vauxp10,vauxn10,vauxp12,vauxn12,vauxp13,vauxn13,vauxp14,vauxn14,vauxp15,vauxn15,busy_out,channel_out[4:0],eoc_out,eos_out,vccaux_alarm_out,vccint_alarm_out,user_temp_alarm_out,alarm_out,temp_out[11:0],vp_in,vn_in";
begin
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity Circuit17 is
Port ( TE,ROSEL: in STD_LOGIC;
G1 : in STD_LOGIC;
G2 : in STD_LOGIC;
G3 : in STD_LOGIC;
G6 : in STD_LOGIC;
G7 : in STD_LOGIC;
G22 : out STD_LOGIC;
G23 : out STD_LOGIC;
GEX: out STD_LOGIC);
end Circuit17;
architecture Behavioral of Circuit17 is
signal delay1,delay2 : std_logic;
signal G10,G11,G16,G19,G6t: STD_LOGIC;
signal sel1,G23t: std_logic;
attribute KEEP : string;
attribute KEEP of G10 : signal is "true";
attribute KEEP of G11 : signal is "true";
attribute KEEP of G16 : signal is "true";
attribute KEEP of G19 : signal is "true";
attribute KEEP of G6t : signal is "true";
--attribute KEEP of delay1 : signal is "true";
--attribute KEEP of delay2 : signal is "true";
attribute KEEP of G23t : signal is "true";
attribute INIT : string;
attribute INIT of G10_lut : label is "7";
attribute INIT of G11_lut : label is "7";
attribute INIT of G16_lut : label is "7";
attribute INIT of G19_lut : label is "7";
attribute INIT of G22_lut : label is "7";
attribute INIT of G23_lut : label is "7";
--attribute INIT of tr1_lut : label is "3";
--attribute INIT of tr2_lut : label is "3";
attribute LOC : string;
attribute LOC of G10_lut : label is "SLICE_X18Y14";
attribute LOC of G11_lut : label is "SLICE_X19Y14";
attribute LOC of G16_lut : label is "SLICE_X20Y14";
attribute LOC of G19_lut : label is "SLICE_X21Y14";
attribute LOC of G22_lut : label is "SLICE_X22Y14";
attribute LOC of G23_lut : label is "SLICE_X23Y14";
--attribute LOC of tr2_lut : label is "SLICE_X23Y14";
--attribute LOC of tr1_lut : label is "SLICE_X22Y14";
begin
sel1<= TE;
------- MUX BEFORE G10 (INPUT TO G10gat)---
process(sel1)
Begin
Case sel1 is
when '0' => G6t<= G6;
when '1' => G6t<= G23t;
When others=> G6t <= G6;
end case;
end process;
--------------------------
G10_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G1,I1 => G3,O => G10 );
G11_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G3,I1 => G6t,O => G11 );
G16_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G2,I1 => G11,O => G16 );
G19_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G11,I1 => G7,O => G19 );
G22_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G16,I1 => G10,O => G22 );
G23_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G19,I1 => G16,O => G23t );
---- TROJAN (INVERTER GATE) ----
--Tr1_lut: LUT2
-- generic map (INIT => X"3")
-- port map( I0 => TE,I1 => G23t,O => delay1);
--Tr2_lut: LUT2
-- generic map (INIT => X"3")
-- port map( I0 => TE,I1 => delay1,O => delay2 );
-----------------------------------
G23<= G23t;
GEX<= G23t;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity Circuit17 is
Port ( TE,ROSEL: in STD_LOGIC;
G1 : in STD_LOGIC;
G2 : in STD_LOGIC;
G3 : in STD_LOGIC;
G6 : in STD_LOGIC;
G7 : in STD_LOGIC;
G22 : out STD_LOGIC;
G23 : out STD_LOGIC;
GEX: out STD_LOGIC);
end Circuit17;
architecture Behavioral of Circuit17 is
signal delay1,delay2 : std_logic;
signal G10,G11,G16,G19,G6t: STD_LOGIC;
signal sel1,G23t: std_logic;
attribute KEEP : string;
attribute KEEP of G10 : signal is "true";
attribute KEEP of G11 : signal is "true";
attribute KEEP of G16 : signal is "true";
attribute KEEP of G19 : signal is "true";
attribute KEEP of G6t : signal is "true";
--attribute KEEP of delay1 : signal is "true";
--attribute KEEP of delay2 : signal is "true";
attribute KEEP of G23t : signal is "true";
attribute INIT : string;
attribute INIT of G10_lut : label is "7";
attribute INIT of G11_lut : label is "7";
attribute INIT of G16_lut : label is "7";
attribute INIT of G19_lut : label is "7";
attribute INIT of G22_lut : label is "7";
attribute INIT of G23_lut : label is "7";
--attribute INIT of tr1_lut : label is "3";
--attribute INIT of tr2_lut : label is "3";
attribute LOC : string;
attribute LOC of G10_lut : label is "SLICE_X18Y14";
attribute LOC of G11_lut : label is "SLICE_X19Y14";
attribute LOC of G16_lut : label is "SLICE_X20Y14";
attribute LOC of G19_lut : label is "SLICE_X21Y14";
attribute LOC of G22_lut : label is "SLICE_X22Y14";
attribute LOC of G23_lut : label is "SLICE_X23Y14";
--attribute LOC of tr2_lut : label is "SLICE_X23Y14";
--attribute LOC of tr1_lut : label is "SLICE_X22Y14";
begin
sel1<= TE;
------- MUX BEFORE G10 (INPUT TO G10gat)---
process(sel1)
Begin
Case sel1 is
when '0' => G6t<= G6;
when '1' => G6t<= G23t;
When others=> G6t <= G6;
end case;
end process;
--------------------------
G10_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G1,I1 => G3,O => G10 );
G11_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G3,I1 => G6t,O => G11 );
G16_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G2,I1 => G11,O => G16 );
G19_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G11,I1 => G7,O => G19 );
G22_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G16,I1 => G10,O => G22 );
G23_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G19,I1 => G16,O => G23t );
---- TROJAN (INVERTER GATE) ----
--Tr1_lut: LUT2
-- generic map (INIT => X"3")
-- port map( I0 => TE,I1 => G23t,O => delay1);
--Tr2_lut: LUT2
-- generic map (INIT => X"3")
-- port map( I0 => TE,I1 => delay1,O => delay2 );
-----------------------------------
G23<= G23t;
GEX<= G23t;
end Behavioral;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
-------------------------------------------------------------------------------
-- FILE NAME : TopLevel.vhd
-- MODULE NAME : TopLevel
-- AUTHOR : Bogdan Ardelean
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2016-05-2 Bogdan Ardelean Created
-------------------------------------------------------------------------------
-- DESCRIPTION : Unit that binds all other components to form the processor
--
-------------------------------------------------------------------------------
library ieee;
library xil_defaultlib;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FpwamPkg.all;
entity TopLevel is
port
(
clk : in std_logic
;rst_i : in std_logic
;led : out std_logic_vector(15 downto 0)
);
end TopLevel;
architecture Structural of TopLevel is
----- STACK AND HEAP MEMORY ----
signal mem_addr1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal mem_addr2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal mem_input_1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal mem_input_2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal mem_output_1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal mem_output_2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal mem_port1_rd : std_logic;
signal mem_port2_rd : std_logic;
signal mem_port1_wr : std_logic;
signal mem_port2_wr : std_logic;
----- GPRs -----
signal gpr_address1 : std_logic_vector(kGPRAddressWidth -1 downto 0);
signal gpr_input1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal gpr_output1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal gpr_wr1 : std_logic;
signal gpr_address2 : std_logic_vector(kGPRAddressWidth -1 downto 0);
signal gpr_input2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal gpr_output2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal gpr_wr2 : std_logic;
----- BIND UNIT -----
signal bind_start : std_logic;
signal bind_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal bind_word2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal bind_mem_addr1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal bind_mem_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal bind_mem_port1_wr : std_logic;
signal bind_mem_addr2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal bind_mem_word2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal bind_mem_port2_wr : std_logic;
signal bind_trail_input : std_logic_vector(kWamAddressWidth -1 downto 0);
signal bind_trail : std_logic;
signal bind_done : std_logic;
----- DEREF UNIT1 ----
signal deref1_start : std_logic;
signal deref1_word : std_logic_vector(kWamWordWidth -1 downto 0);
signal deref1_mem_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal deref1_mem_addr1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal deref1_mem_port1_rd : std_logic;
signal deref1_res_out : std_logic_vector(kWamWordWidth -1 downto 0);
signal deref1_addr_word : std_logic_vector(kWamWordWidth -1 downto 0);
signal deref1_addr : std_logic_vector(kWamAddressWidth -1 downto 0);
signal deref1_done : std_logic;
----- DEREF UNIT2 ----
----- THIS IS USED JUST BY UNIFYUNIT ----
signal deref2_start : std_logic;
signal deref2_word : std_logic_vector(kWamWordWidth -1 downto 0);
signal deref2_mem_word2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal deref2_mem_addr2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal deref2_mem_port2_rd : std_logic;
signal deref2_res_out : std_logic_vector(kWamWordWidth -1 downto 0);
signal deref2_done : std_logic;
----- UNIFY UNIT ----
signal unify_start : std_logic;
signal unify_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_word2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_mem_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_mem_word2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_deref1_in : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_deref1_done : std_logic;
signal unify_deref2_in : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_deref2_done : std_logic;
signal unify_bind_done : std_logic;
signal unify_done : std_logic;
signal unify_fail : std_logic;
signal unify_mem_addr1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal unify_mem_port1_rd : std_logic;
signal unify_mem_addr2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal unify_mem_port2_rd : std_logic;
signal unify_deref1_out : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_deref1_start : std_logic;
signal unify_deref2_out : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_deref2_start : std_logic;
signal unify_bind_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_bind_word2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal unify_bind_start : std_logic;
signal unify_mem_sel : unify_mem_sel_t;
signal unifyComb_mem_addr1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal unifyComb_mem_addr2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal unifyComb_mem_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal unifyComb_mem_word2 : std_logic_vector(kWamWordWidth -1 downto 0);
----- DATAFLOWCONTROL UNIT ----
signal dfc_instruction_in : std_logic_vector(kWamInstructionWidth-1 downto 0);
signal dfc_instruction_valid : std_logic;
signal dfc_mem_word1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal dfc_deref1_done : std_logic;
signal dfc_mode_reg : wam_mode_t;
signal dfc_unify_done : std_logic;
signal dfc_bind_done : std_logic;
signal dfc_nr_args : std_logic_vector(kGPRAddressWidth -1 downto 0);
signal dfc_unwind_done : std_logic;
signal dfc_local_fail : std_logic;
signal dfc_global_fail : std_logic;
signal dfc_b_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal dfc_new_b_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal dfc_deref_addr : std_logic_vector(kWamAddressWidth -1 downto 0);
signal dfc_deref_word : std_logic_vector(kWamWordWidth -1 downto 0);
signal dfc_h_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal dfc_e_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal dfc_bsearch_done : std_logic;
signal dfc_bsearch_found : std_logic;
signal dfc_local_fail_rst : std_logic;
signal dfc_global_fail_out : std_logic;
signal dfc_global_fail_rst : std_logic;
signal dfc_get_instruction : std_logic;
signal dfc_deref1_start : std_logic;
signal dfc_deref1_input : deref_input_t;
signal dfc_S_wr : std_logic;
signal dfc_S_input : s_input_t;
signal dfc_mode_wr : std_logic;
signal dfc_mode_value : wam_mode_t;
signal dfc_mem_port1_rd : std_logic;
signal dfc_mem_port1_wr : std_logic;
signal dfc_mem_input1 : mem_port_input_t;
signal dfc_mem_addr1 : mem_addr_input_t;
signal dfc_mem_port2_rd : std_logic;
signal dfc_mem_port2_wr : std_logic;
signal dfc_mem_input2 : mem_port_input_t;
signal dfc_mem_addr2 : mem_addr_input_t;
signal dfc_bind_start : std_logic;
signal dfc_bind_port1 : bind_input_t;
signal dfc_bind_port2 : bind_input_t;
signal dfc_trail_input : trail_input_t;
signal dfc_H_wr : std_logic;
signal dfc_H_input : h_input_t;
signal dfc_gpr_wr1 : std_logic;
signal dfc_gpr_addr1 : GPR_addr_input_t;
signal dfc_gpr_input1 : gpr_input_t;
signal dfc_gpr_wr2 : std_logic;
signal dfc_gpr_addr2 : GPR_addr_input_t;
signal dfc_gpr_input2 : gpr_input_t;
signal dfc_unify_start : std_logic;
signal dfc_unify_input_a : unify_input_t;
signal dfc_unify_input_b : unify_input_t;
signal dfc_P_input : p_input_t;
signal dfc_P_wr : std_logic;
signal dfc_CP_wr : std_logic;
signal dfc_CP_input : cp_input_t;
signal dfc_nr_wr : std_logic;
signal dfc_nr_input : nrargs_input_t;
signal dfc_newE_wr : std_logic;
signal dfc_E_wr : std_logic;
signal dfc_E_input : e_input_t;
signal dfc_B_input : b_input_t;
signal dfc_b_wr : std_logic;
signal dfc_newB_wr : std_logic;
signal dfc_tr_wr : std_logic;
signal dfc_tr_input : tr_input_t;
signal dfc_hb_wr : std_logic;
signal dfc_hb_input : hb_input_t;
signal dfc_i : unsigned(kWamAddressWidth -1 downto 0);
signal dfc_start_unwind : std_logic;
signal dfc_mem_addr1_out : std_logic_vector(kWamAddressWidth -1 downto 0);
signal dfc_mem_addr2_out : std_logic_vector(kWamAddressWidth -1 downto 0);
signal dfc_mem_out1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal dfc_mem_out2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal dfc_trail_do : std_logic;
signal dfc_bladdr_wr : std_logic;
signal dfc_bhaddr_wr : std_logic;
signal dfc_bsearch_start : std_logic;
----- TRAIL -----
signal trail_start : std_logic;
signal trail_address : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trail_H : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trail_HB : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trail_B : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trail_a : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trail_do : std_logic;
signal trailm_addr_1 : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal trailm_output_1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trailm_input_1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trailm_wr_1 : std_logic;
signal trailm_rd_1 : std_logic;
signal trailm_addr_2 : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal trailm_output_2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trailm_input_2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal trailm_wr_2 : std_logic;
signal trailm_rd_2 : std_logic;
----- UNWIND TRAIL ----
signal untrail_start : std_logic;
signal untrail_a1 : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal untrail_a2 : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal untrail_port_1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal untrail_port_1_rd : std_logic;
signal untrail_addr_1 : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal untrail_port_2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal untrail_port_2_rd : std_logic;
signal untrail_addr_2 : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal untrail_mem_port_1 : std_logic_vector(kWamWordWidth -1 downto 0);
signal untrail_mem_port_1_wr : std_logic;
signal untrail_mem_addr_1 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal untrail_mem_port_2 : std_logic_vector(kWamWordWidth -1 downto 0);
signal untrail_mem_port_2_wr : std_logic;
signal untrail_mem_addr_2 : std_logic_vector(kWamAddressWidth -1 downto 0);
signal untrail_done : std_logic;
----- REGISTERS ------
----- H REGISTER
signal H_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal H_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal H_wr : std_logic;
----- S REGISTER
signal S_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal S_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal S_wr : std_logic;
----- MODE REGISTER
signal M_reg : wam_mode_t;
signal M_comb : wam_mode_t;
signal M_wr : std_logic;
----- P REGISTER
signal P_reg : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal P_comb : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal P_wr : std_logic;
----- CP REGISTER
signal CP_reg : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal CP_comb : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal CP_wr : std_logic;
----- NRARGS REGISTER
signal NRARGS_reg : std_logic_vector(kGPRAddressWidth -1 downto 0);
signal NRARGS_comb : std_logic_vector(kGPRAddressWidth -1 downto 0);
signal NRARGS_wr : std_logic;
----- E REGISTER
signal E_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal E_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal E_wr : std_logic;
----- NewE REGISTER
signal NewE_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal NewE_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal NewE_wr : std_logic;
----- B REGISTER
signal B_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal B_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal B_wr : std_logic;
----- NewB REGISTER
signal NewB_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal NewB_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal NewB_wr : std_logic;
------ TR REGISTER
signal TR_reg : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal TR_comb : std_logic_vector(kWamTrailAddressWidth -1 downto 0);
signal TR_wr : std_logic;
------ HB register
signal HB_reg : std_logic_vector(kWamAddressWidth -1 downto 0);
signal HB_comb : std_logic_vector(kWamAddressWidth -1 downto 0);
signal HB_wr : std_logic;
------ LOCALFAIL register
signal LCLFAIL_reg : std_logic;
signal LCLFAIL_comb : std_logic;
signal LCLFAIL_rst : std_logic;
------ GLOBALFAIL register
signal GLBFAIL_reg : std_logic;
signal GLBFAIL_comb : std_logic;
signal GLBFAIL_rst : std_logic;
-- TEMPORARYMEMORY
type instr_mem is array (0 to 196) of std_logic_vector(kWamInstructionWidth - 1 downto 0);
-- signal mem : instr_mem :=
-- ("00000000000000000000000000000000" -- block
-- ,B"00001_000000001_00000000000001_0000" -- put_structure c/0, A1
-- ,B"00001_000000010_00000000000010_0000" -- put_structure d/0, A2
-- ,B"01010_000000000_00000000000100_0010" -- call p/2
-- ,"00000000000000000000000000000000" -- block
-- ,B"01110_000000000_00000000000000_1001" -- try_me_else 9 p(X,a).
-- ,B"00110_000000011_00000000000000_0001" -- get_variable x3, A1
-- ,B"00101_000000010_00000000000011_0000" -- get_structure a/0, A2
-- ,B"01011_000000000_00000000000000_0000" -- proceed.
-- ,"00000000000000000000000000000000" -- block
-- ,B"01111_000000000_00000000000000_1110" -- retry_me_else 14 p(b,X)
-- ,B"00101_000000001_00000000000100_0000" -- get_structure b/0, A1
-- ,B"00110_000000011_00000000000000_0010" -- get_variable x3, A2
-- ,B"01011_000000000_00000000000000_0000" -- proceed.
-- ,"00000000000000000000000000000000" -- block
-- ,B"10000_000000000_00000000000000_0000" -- trust_me p(X,Y) :- p(X, a), p(b, Y).
-- ,B"01100_000000000_00000000000000_0001" -- allocate 1
-- ,B"00110_000000011_00000000000000_0001" -- get_variable x3, A1
-- ,B"00110_000010001_00000000000000_0001" -- get_variable y1, A2
-- ,B"00100_000000011_00000000000000_0001" -- put_value X3, A1
-- ,B"00001_000000010_00000000000011_0000" -- put_structure a/0, A2
-- ,B"01010_000000000_00000000000100_0010" -- call p/2
-- ,B"00001_000000001_00000000000100_0000" -- put_structure a/0, A1
-- ,B"00100_000010001_00000000000000_0010" -- put_value Y1, A2
-- ,B"01010_000000000_00000000000100_0010" -- call p/2
-- ,B"01101_000000000_00000000000100_0000" -- deallocate
-- ,"00000000000000000000000000000000" -- block
-- );
--signal mem : instr_mem :=
--("00000000000000000000000000000000" -- block
--,B"10010_000000101_00000000000000_0000" -- put_list x5
--,B"01000_000000110_00000000000000_0000" -- unify_variable x6
--,B"10111_000000000_11111111111111_1111" -- unify_constant nil
--,B"00010_000000100_00000000000000_0001" -- put_variable x4, A1
--,B"10010_000000010_00000000000000_0000" -- put_list A2
--,B"01001_000000100_00000000000000_0000" -- unify_value x4
--,B"01001_000000101_00000000000000_0000" -- unify_value x5
--,B"00001_000000011_00000000000001_0001" -- put_structure f/1, A3
--,B"01001_000000110_00000000000000_0000" -- unify_value x6
--,B"01010_000000000_00000000001011_0011" -- call p/3
--,"00000000000000000000000000000000" -- block
--,B"00101_000000001_00000000000001_0001" -- get_structure f/1, A1
--,B"01000_000000100_00000000000000_0000" -- unify_variable x4
--,B"10100_000000010_00000000000000_0000" -- get_list A2
--,B"01000_000000101_00000000000000_0000" -- unify_variable x5
--,B"01000_000000110_00000000000000_0000" -- unify_variable x6
--,B"00111_000000101_00000000000000_0011" -- get_value x5, A3
--,B"10100_000000110_00000000000000_0000" -- get_list x6
--,B"01000_000000111_00000000000000_0000" -- unify_variable x7
--,B"10111_000000000_11111111111111_1111" -- unify_constant nil
--,B"00101_000000111_00000000000001_0001" -- get_structure f/1, A1
--,B"10111_000000000_11000000000000_0001" -- unify_constant a
--,B"01011_000000000_00000000000000_0000" -- proceed
--,"00000000000000000000000000000000" -- block
--,"00000000000000000000000000000000" -- block
--,"00000000000000000000000000000000" -- block
-- );
--signal mem : instr_mem := -- p(Z. h(Z, W), f(W))?
--("00000000000000000000000000000000" -- block
--,B"00001_000000001_00000000000001_0010" -- put_list x5
--,B"01000_000000000_00000000000000_0000" -- unify_variable x6
--,B"01000_000000011_00000000000000_0000" -- unify_constant nil
--,B"00001_000000010_00000000000010_0001" -- put_variable x4, A1
--,B"01001_000000011_00000000000000_0000" -- put_list A2
--,B"01010_000000000_00000000000111_0011" -- unify_value x4
--,"00000000000000000000000000000000" -- block -- unify_value x5
--,B"00101_000000000_00000000000010_0001" -- put_structure f/1, A3
--,B"11000_000000000_00000000000000_0001" -- unify_value x6
--,B"00101_000000001_00000000000001_0010" -- call p/3
--,B"10110_000000010_00000000000000_0000"-- block
--,B"11101_000000000_00000000000010_0001" -- get_structure f/1, A1
--,B"10111_000000000_00000000000000_0001" -- unify_variable x4
--,B"01011_000000000_00000000000000_0000" -- get_list A2
--,"00000000000000000000000000000000" -- unify_variable x5
--,B"01000_000000110_00000000000000_0000" -- unify_variable x6
--,B"00111_000000101_00000000000000_0011" -- get_value x5, A3
--,B"10100_000000110_00000000000000_0000" -- get_list x6
--,B"01000_000000111_00000000000000_0000" -- unify_variable x7
--,B"10111_000000000_11111111111111_1111" -- unify_constant nil
--,B"00101_000000111_00000000000001_0001" -- get_structure f/1, A1
--,B"10111_000000000_11000000000000_0001" -- unify_constant a
--,B"01011_000000000_00000000000000_0000" -- proceed
--,"00000000000000000000000000000000" -- block
--,"00000000000000000000000000000000" -- block
--,"00000000000000000000000000000000" -- block
--);
--signal mem : instr_mem :=
--("00000000000000000000000000000000" -- block
--,B"10010_000000101_00000000000000_0000" -- put_list x5
--,B"01000_000000110_00000000000000_0000" -- unify_variable x6
--,B"10111_000000000_11111111111111_1111" -- unify_constant nil
--,B"00010_000000100_00000000000000_0001" -- put_variable x4, A1
--,B"10010_000000010_00000000000000_0000" -- put_list A2
--,B"01001_000000100_00000000000000_0000" -- unify_value x4
--,B"01001_000000101_00000000000000_0000" -- unify_value x5
--,B"00001_000000011_00000000000001_0001" -- put_structure f/1, A3
--,B"01001_000000110_00000000000000_0000" -- unify_value x6
--,B"01010_000000000_00000000001011_0011" -- call p/3
--,"00000000000000000000000000000000" -- block
--,B"00101_000000001_00000000000001_0001" -- get_structure f/1, A1
--,B"01000_000000100_00000000000000_0000" -- unify_variable x4
--,B"10100_000000010_00000000000000_0000" -- get_list A2
--,B"01000_000000101_00000000000000_0000" -- unify_variable x5
--,B"01000_000000110_00000000000000_0000" -- unify_variable x6
--,B"00111_000000101_00000000000000_0011" -- get_value x5, A3
--,B"10100_000000110_00000000000000_0000" -- get_list x6
--,B"01000_000000111_00000000000000_0000" -- unify_variable x7
--,B"10111_000000000_11111111111111_1111" -- unify_constant nil
--,B"00101_000000111_00000000000001_0001" -- get_structure f/1, A1
--,B"10111_000000000_11000000000000_0001" -- unify_constant a
--,B"01011_000000000_00000000000000_0000" -- proceed
--,"00000000000000000000000000000000" -- block
--,"00000000000000000000000000000000" -- block
--,"00000000000000000000000000000000" -- block
-- );
signal mem : instr_mem := --
(
B"000000_00000000_00000000000000_0000"
,B"001100_00000000_00000000000000_0001"
,B"000011_00010001_00000000000000_0001"
,B"001010_00000000_00000010000011_0001"
,B"000001_00000001_00000000000011_0101"
,B"010111_00000000_11000000000000_0001"
,B"010111_00000000_11000000000000_0010"
,B"011000_00000000_00000000000000_0011"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11000000000000_0011"
,B"010111_00000000_11000000000000_0100"
,B"011000_00000000_00000000000000_0010"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"010111_00000000_11000000000000_0101"
,B"011000_00000000_00000000000000_0010"
,B"010111_00000000_11000000000000_0110"
,B"011000_00000000_00000000000000_0001"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11000000000000_0111"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11000000000000_1000"
,B"011000_00000000_00000000000000_0001"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"010111_00000000_11000000000000_0101"
,B"011000_00000000_00000000000000_0100"
,B"000001_00000010_00000000000011_0101"
,B"010111_00000000_11000000000000_1001"
,B"011000_00000000_00000000000000_0100"
,B"000100_00010001_00000000000000_0011"
,B"001010_00000000_00000010011010_0011"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0010"
,B"010111_00000000_11000000000000_1010"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11000000000000_1011"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"010111_00000000_11000000000000_1100"
,B"011000_00000000_00000000000000_0011"
,B"010111_00000000_11000000000000_1101"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000100_00010001_00000000000000_0001"
,B"010100_00000001_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"100001_00000000_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"100001_00000000_00000000000000_0000"
,B"001000_00000001_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"100001_00000000_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11111111111111_1111"
,B"000101_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0011"
,B"010111_00000000_11000000000000_1110"
,B"011000_00000000_00000000000000_0001"
,B"000100_00010001_00000000000000_0001"
,B"010100_00000001_00000000000000_0000"
,B"001000_00000001_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"000101_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11000000000000_1111"
,B"011000_00000000_00000000000000_0011"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0100"
,B"010111_00000000_11000000000001_0000"
,B"000001_00000010_00000000000011_0101"
,B"011000_00000000_00000000000000_0010"
,B"010111_00000000_11000000000001_0001"
,B"011000_00000000_00000000000000_0010"
,B"000100_00010001_00000000000000_0011"
,B"001010_00000000_00000010100111_0011"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0100"
,B"010111_00000000_11000000000000_1101"
,B"000001_00000010_00000000000011_0101"
,B"011000_00000000_00000000000000_0010"
,B"010111_00000000_11000000000001_0010"
,B"011000_00000000_00000000000000_0010"
,B"000100_00010001_00000000000000_0011"
,B"001010_00000000_00000010100111_0011"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0011"
,B"010111_00000000_11000000000001_0011"
,B"010111_00000000_11000000000001_0100"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11000000000001_0101"
,B"011000_00000000_00000000000000_0010"
,B"010111_00000000_11000000000001_0110"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0001"
,B"010111_00000000_11000000000000_1111"
,B"011000_00000000_00000000000000_0011"
,B"000001_00000010_00000000000011_0101"
,B"010111_00000000_11000000000001_0111"
,B"011000_00000000_00000000000000_0100"
,B"000100_00010001_00000000000000_0011"
,B"001010_00000000_00000010100111_0011"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0010"
,B"010111_00000000_11000000000001_1000"
,B"011000_00000000_00000000000000_0010"
,B"000100_00010001_00000000000000_0010"
,B"001010_00000000_00000010111011_0010"
,B"000001_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0011"
,B"010111_00000000_11000000000001_1001"
,B"011000_00000000_00000000000000_0001"
,B"010001_00010001_00000000000000_0010"
,B"001101_00000000_00000000000000_0000"
,B"011100_00000000_00000010111011_0010"
,B"000000_00000000_00000000000000_0000"
,B"010100_00000001_00000000000000_0000"
,B"001000_00000101_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"001000_00000100_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"001000_00000011_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"001000_00000010_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"001000_00000001_00000000000000_0000"
,B"010111_00000000_11111111111111_1111"
,B"000101_00000101_00000000000011_0101"
,B"011000_00000000_00000000000000_0101"
,B"000101_00000100_00000000000011_0101"
,B"011000_00000000_00000000000000_0101"
,B"000101_00000011_00000000000011_0101"
,B"011000_00000000_00000000000000_0101"
,B"000101_00000010_00000000000011_0101"
,B"011000_00000000_00000000000000_0101"
,B"000101_00000001_00000000000011_0101"
,B"011000_00000000_00000000000000_0101"
,B"001011_00000000_00000000000000_0000"
,B"000000_00000000_00000000000000_0000"
,B"001110_00000000_00000000001010_0001"
,B"010100_00000011_00000000000000_0000"
,B"010110_00000010_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"010110_00000001_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"001011_00000000_00000000000000_0000"
,B"010000_00000000_00000000000000_0000"
,B"010100_00000011_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"001000_00000011_00000000000000_0000"
,B"011100_00000000_00000010011010_0011"
,B"000000_00000000_00000000000000_0000"
,B"001110_00000000_00000000001010_1110"
,B"010100_00000011_00000000000000_0000"
,B"010110_00000001_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"010110_00000010_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"001011_00000000_00000000000000_0000"
,B"001111_00000000_00000000001011_0101"
,B"010100_00000011_00000000000000_0000"
,B"010110_00000010_00000000000000_0000"
,B"100001_00000000_00000000000000_0000"
,B"010110_00000001_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"001011_00000000_00000000000000_0000"
,B"010000_00000000_00000000000000_0000"
,B"010100_00000011_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"001000_00000011_00000000000000_0000"
,B"011100_00000000_00000010100111_0011"
,B"000000_00000000_00000000000000_0000"
,B"001110_00000000_00000000001100_0000"
,B"010100_00000010_00000000000000_0000"
,B"010110_00000001_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"001011_00000000_00000000000000_0000"
,B"010000_00000000_00000000000000_0000"
,B"010100_00000010_00000000000000_0000"
,B"011000_00000000_00000000000000_0001"
,B"001000_00000010_00000000000000_0000"
,B"011100_00000000_00000010111011_0010"
);
signal instruction_counter : unsigned(7 downto 0);
signal instruction : std_logic_vector(kWamInstructionWidth -1 downto 0);
signal instruction_valid : std_logic;
signal instr_mem_addr : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal instr_mem_out : std_logic_vector(kWamInstructionWidth -1 downto 0);
signal instr_mem_rd : std_logic;
signal rst : std_logic := '1';
-- HASH TABLE REPLACEMENT
signal bsearch_word : std_logic_vector(kWamWordWidth -1 downto 0);
signal bsearch_low_addr : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bsearch_high_addr : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bsearch_start : std_logic;
signal bsearch_done : std_logic;
signal bsearch_found : std_logic;
signal bsearch_memory_in : std_logic_vector(kWamWordWidth -1 downto 0);
signal bsearch_addr_out : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bsearch_memory_read : std_logic;
signal bsearch_laddr_wr : std_logic;
signal bsearch_laddr_comb : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bsearch_laddr_reg : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bsearch_haddr_wr : std_logic;
signal bsearch_haddr_comb : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bsearch_haddr_reg : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bmem_addr_port_1 : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bmem_port_1_out : std_logic_vector(kWamWordWidth+kWamInstrMemWidth -1 downto 0);
signal bmem_port_1_in : std_logic_vector(kWamWordWidth+kWamInstrMemWidth -1 downto 0);
signal bmem_port_1_wr : std_logic;
signal bmem_port_1_rd : std_logic;
signal bmem_addr_port_2 : std_logic_vector(kWamInstrMemWidth -1 downto 0);
signal bmem_port_2_out : std_logic_vector(kWamWordWidth+kWamInstrMemWidth -1 downto 0);
signal bmem_port_2_in : std_logic_vector(kWamWordWidth+kWamInstrMemWidth -1 downto 0);
signal bmem_port_2_wr : std_logic;
signal bmem_port_2_rd : std_logic;
constant kTarget : integer := 100000;
signal clock_counter : integer;
signal millis : unsigned(11 downto 0);
signal do_count : boolean;
begin
clk_cnt: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
clock_counter <= 0;
else
if do_count then
if clock_counter = kTarget then
clock_counter <= 0;
else
clock_counter <= clock_counter + 1;
end if;
end if;
end if;
end if;
end process;
milliscnt: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
millis <= to_unsigned(0, millis'length);
else
if clock_counter = kTarget and do_count then
millis <= millis+1;
end if;
end if;
end if;
end process;
RSTPRC: process(clk)
begin
if rising_edge(clk) then
rst <= '0';
end if;
end process;
do_count <= not((fpwam_instr(dfc_instruction_in) = i_nop) and (unsigned(P_reg) = to_unsigned(1, P_reg'length)));
led(0) <= GLBFAIL_reg;
led(1) <= to_std_logic(fpwam_instr(dfc_instruction_in) = i_nop);
led(2) <= to_std_logic(unsigned(P_reg) = to_unsigned(1, P_reg'length));
led(3) <= '1';
led(15 downto 4) <= std_logic_vector(millis);
-- INSTRUCTION MEMORY
instr_mem_addr <= P_reg;
instr_mem_rd <= dfc_get_instruction;
instruction_valid <= '1';
dfc_instruction_in <= instr_mem_out;
-- TEMPORARYMEMORY
INSTCNT: process(clk)
begin
if rising_edge(clk) then
if instr_mem_rd = '1' then
instr_mem_out <= mem(to_integer(unsigned(instr_mem_addr)));
end if;
end if;
end process;
-- INSTRMEM: entity work.Memory(Behavioral)
-- generic map
-- (
-- kMemAddressWidth => kWamInstrMemWidth
-- ,kWordWidth => kWamInstructionWidth
-- )
-- port map
-- (
-- clk => clk
--
-- ,addr_port_1 => instr_mem_addr
-- ,word_port_1_o => instr_mem_out
-- ,word_port_1_i => open
-- ,wr_port_1 => open
-- ,rd_port_1 => instr_mem_rd
--
-- ,addr_port_2 => open
-- ,word_port_2_o => open
-- ,word_port_2_i => open
-- ,wr_port_2 => open
-- ,rd_port_2 => open
-- );
-- MODE REGISTER BEGIN
M_wr <= dfc_mode_wr;
M_comb <= dfc_mode_value;
MREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
M_reg <= mode_read_t;
elsif M_wr = '1' then
M_reg <= M_comb;
end if;
end if;
end process;
-- H REGISTER BEGIN
H_wr <= dfc_H_wr;
HMUX: process(dfc_H_input, H_reg, HB_reg, mem_output_1, mem_output_2, dfc_instruction_in)
begin
H_comb <= H_reg;
case dfc_H_input is
when HI_p1_t =>
H_comb <= std_logic_vector(unsigned(H_reg) + 1);
when HI_p2_t =>
H_comb <= std_logic_vector(unsigned(H_reg) + 2);
when HI_HB_t =>
H_comb <= HB_reg;
when HI_mem_port1_t =>
H_comb <= mem_output_1(kWamAddressWidth -1 downto 0);
when HI_mem_port2_t =>
H_comb <= mem_output_2(kWamAddressWidth -1 downto 0);
when HI_Hpconstant_t =>
H_comb <= std_logic_vector(unsigned(H_reg)+unsigned(dfc_instruction_in(kGPRAddressWidth -1 downto 0)));
when others =>
null;
end case;
end process;
HREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
H_reg <= kWamHeapStart;
elsif H_wr = '1' then
H_reg <= H_comb;
end if;
end if;
end process;
-- H REGISTER END
-- S REGISTER START
S_wr <= dfc_S_wr;
SMUX: process(dfc_S_input, S_reg, deref1_res_out, dfc_instruction_in)
begin
S_comb <= S_reg;
case dfc_S_input is
when SI_untag_deref_p1_t =>
S_comb <= std_logic_vector(unsigned(fpwam_value(deref1_res_out))+1);
when SI_p1_t =>
S_comb <= std_logic_vector(unsigned(S_reg)+1);
when SI_untag_deref_t =>
S_comb <= std_logic_vector(fpwam_value(deref1_res_out));
when SI_pconstant_t =>
S_comb <= std_logic_vector(unsigned(S_reg)+unsigned(dfc_instruction_in(kGPRAddressWidth -1 downto 0)));
when others =>
null;
end case;
end process;
SREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
S_reg <= (others => '0');
elsif S_wr = '1' then
S_reg <= S_comb;
end if;
end if;
end process;
-- S REGISTER END
-- P REGISTER BEGIN
PMUX: process(dfc_P_input, P_reg, CP_reg, instr_mem_out, dfc_i, bmem_port_1_out, mem_output_1, mem_output_2)
begin
case dfc_P_input is
when PI_p1_t =>
P_comb <= std_logic_vector(unsigned(P_reg)+1);
when PI_CP_t =>
P_comb <= CP_reg;
when PI_instr_t =>
P_comb <= fpwam_instr_addr(instr_mem_out);
when PI_mem_port1_t =>
P_comb <= mem_output_1(kWamInstrMemWidth -1 downto 0);
when PI_mem_port2_t =>
P_comb <= mem_output_2(kWamInstrMemWidth -1 downto 0);
when PI_PpI_t =>
P_comb <= std_logic_vector(unsigned(P_reg)+dfc_i(kWamInstrMemWidth -1 downto 0));
when PI_bmem_port1_t =>
P_comb <= bmem_port_1_out(kWamInstrMemWidth -1 downto 0);
when PI_constant_t =>
P_comb <= instr_mem_out(kWamInstrMemWidth -1 downto 0);
when others =>
P_comb <= std_logic_vector(unsigned(P_reg)+1);
end case;
end process;
P_wr <= dfc_P_wr;
PREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
P_reg <= std_logic_vector(to_unsigned(1, P_reg'length));
elsif P_wr = '1' then
P_reg <= P_comb;
end if;
end if;
end process;
-- CP REGISTER BEGIN
CP_wr <= dfc_CP_wr;
CP_comb <= P_reg when dfc_CP_input = CPI_P_t else
mem_output_1(kWamInstrMemWidth -1 downto 0) when dfc_CP_input = CPI_mem_port1_t else
mem_output_2(kWamInstrMemWidth -1 downto 0);
CPREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
CP_reg <= (others => '0');
elsif CP_wr = '1' then
CP_reg <= CP_comb;
end if;
end if;
end process;
-- NRARGS REGISTER BEGIN
NRARGS_wr <= dfc_nr_wr;
NRARGS_comb <= fpwam_instr_arity(dfc_instruction_in) when dfc_nr_input = NRARGSI_instr_t else
mem_output_1(kGPRAddressWidth -1 downto 0) when dfc_nr_input = NRARGSI_mem_port1_t else
mem_output_2(kGPRAddressWidth -1 downto 0);
NRARGSREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
NRARGS_reg <= (others => '0');
elsif NRARGS_wr = '1' then
NRARGS_reg <= NRARGS_comb;
end if;
end if;
end process;
-- E REGISTER BEGIN
E_wr <= dfc_E_wr;
E_comb <= NewE_reg when dfc_E_input = EI_newE_t else
mem_output_1(kWamAddressWidth -1 downto 0) when dfc_E_input = EI_mem_port1_t else
mem_output_2(kWamAddressWidth -1 downto 0);
EREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
E_reg <= kWamStackStart;
elsif E_wr = '1' then
E_reg <= E_comb;
end if;
end if;
end process;
-- NewE REGISTER BEGIN
NewE_wr <= dfc_newE_wr;
NewE_comb <= std_logic_vector(unsigned(mem_output_2(kWamAddressWidth -1 downto 0)) + unsigned(E_reg) + 3) when E_reg > B_reg else
std_logic_vector(unsigned(mem_output_2(kWamAddressWidth -1 downto 0)) + unsigned(B_reg) + 7);
NEWEREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
NewE_reg <= kWamStackStart;
elsif NewE_wr = '1' then
NewE_reg <= NewE_comb;
end if;
end if;
end process;
-- B REGISTER BEGIN
B_wr <= dfc_B_wr;
B_comb <= NewB_reg when dfc_B_input = BRI_newB_t else
mem_output_1(kWamAddressWidth -1 downto 0) when dfc_B_input = BRI_mem_port1_t else
mem_output_2(kWamAddressWidth -1 downto 0);
BREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
B_reg <= kWamStackStart;
elsif B_wr = '1' then
B_reg <= B_comb;
end if;
end if;
end process;
-- NewB REGISTER BEGIN
NewB_wr <= dfc_newB_wr;
NewB_comb <= std_logic_vector(unsigned(mem_output_2(kWamAddressWidth -1 downto 0)) + unsigned(E_reg) + 3) when E_reg > B_reg else
std_logic_vector(unsigned(mem_output_2(kWamAddressWidth -1 downto 0)) + unsigned(B_reg) + 7);
NEWBREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
NewB_reg <= kWamStackStart;
elsif NewB_wr = '1' then
NewB_reg <= NewB_comb;
end if;
end if;
end process;
HB_comb <= H_reg when dfc_hb_input = HBI_H_t else
mem_output_1(kWamAddressWidth -1 downto 0) when dfc_hb_input = HBI_mem_port1_t else
mem_output_2(kWamAddressWidth -1 downto 0);
HB_wr <= dfc_hb_wr;
HBREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
HB_reg <= kWamStackStart;
elsif HB_wr = '1' then
HB_reg <= HB_comb;
end if;
end if;
end process;
-- TR REGISTER
TR_wr <= trail_do or dfc_tr_wr;
TR_comb <= std_logic_vector(unsigned(TR_reg)+1) when dfc_tr_input = TRI_Trp1_t else
mem_output_1(kWamTrailAddressWidth -1 downto 0) when dfc_tr_input = TRI_mem_port1_t else
mem_output_2(kWamTrailAddressWidth -1 downto 0);
TRREG: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
TR_reg <= (others => '0');
elsif TR_wr = '1' then
TR_reg <= TR_comb;
end if;
end if;
end process;
LCLFAIL_comb <= unify_fail;
LCLFAIL_rst <= dfc_local_fail_rst;
LCLFAIL: process(clk)
begin
if rising_edge(clk) then
if rst = '1' or LCLFAIL_rst = '1' then
LCLFAIL_reg <= '0';
else
LCLFAIL_reg <= LCLFAIL_reg or LCLFAIL_comb;
end if;
end if;
end process;
GLBFAIL_comb <= dfc_global_fail_out;
GLBFAIL_rst <= dfc_global_fail_rst;
GLBFAIL: process(clk)
begin
if rising_edge(clk) then
if rst = '1' or GLBFAIL_rst = '1' then
GLBFAIL_reg <= '0';
else
GLBFAIL_reg <= GLBFAIL_reg or GLBFAIL_comb;
end if;
end if;
end process;
bsearch_laddr_comb <= dfc_instruction_in(kWamInstrMemWidth -1 downto 0);
bsearch_laddr_wr <= dfc_bladdr_wr;
BLADDR: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
bsearch_laddr_reg <= (others => '0');
elsif bsearch_laddr_wr = '1' then
bsearch_laddr_reg <= bsearch_laddr_comb;
end if;
end if;
end process;
bsearch_haddr_comb <= dfc_instruction_in(kWamInstrMemWidth -1 downto 0);
bsearch_haddr_wr <= dfc_bhaddr_wr;
BHADDR: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
bsearch_haddr_reg <= (others => '0');
elsif bsearch_haddr_wr = '1' then
bsearch_haddr_reg <= bsearch_haddr_comb;
end if;
end if;
end process;
-- STACK AND HEAP MEMORY BEGIN
mem_port1_rd <= deref1_mem_port1_rd
or unify_mem_port1_rd
or dfc_mem_port1_rd
or mem_port1_wr;
mem_port2_rd <= deref2_mem_port2_rd
or unify_mem_port2_rd
or dfc_mem_port2_rd
or mem_port2_wr;
mem_port1_wr <= bind_mem_port1_wr
or dfc_mem_port1_wr
or untrail_mem_port_1_wr;
mem_port2_wr <= bind_mem_port2_wr
or dfc_mem_port2_wr
or untrail_mem_port_2_wr;
ADDR1MUX: process(deref1_res_out,dfc_mem_addr1, H_reg, deref1_mem_addr1, bind_mem_addr1, bind_mem_addr2, unifyComb_mem_addr1, S_reg,
E_reg, dfc_instruction_in, B_reg, NewE_reg, NewB_reg, NRARGS_reg, dfc_i, untrail_mem_addr_1, mem_output_1, dfc_mem_addr1_out)
begin
mem_addr1 <= (others => '0');
case dfc_mem_addr1 is
when MA_H_t =>
mem_addr1 <= H_reg;
when MA_Hplus1_t =>
mem_addr1 <= std_logic_vector(unsigned(H_reg)+1);
when MA_deref_unit_t =>
mem_addr1 <= deref1_mem_addr1;
when MA_bind_unit_1_t =>
mem_addr1 <= bind_mem_addr1;
when MA_bind_unit_2_t =>
mem_addr1 <= bind_mem_addr2;
when MA_unify_unit_t =>
mem_addr1 <= unifyComb_mem_addr1;
when MA_stack_addr_t => -- TODO
mem_addr1 <= fpwam_var_stack_addr(dfc_instruction_in, E_reg);
when MA_S_t =>
mem_addr1 <= S_reg;
when MA_untag_deref_t =>
mem_addr1 <= fpwam_value(deref1_res_out);
when MA_Ep2orB_t =>
if E_reg > B_reg then
mem_addr1 <= std_logic_vector(unsigned(E_reg)+2);
else
mem_addr1 <= B_reg;
end if;
when MA_newE_t =>
mem_addr1 <= NewE_reg;
when MA_newEp1_t =>
mem_addr1 <= std_logic_vector(unsigned(NewE_reg)+1);
when MA_newEp2_t =>
mem_addr1 <= std_logic_vector(unsigned(NewE_reg)+2);
when MA_E_t =>
mem_addr1 <= E_reg;
when MA_Ep1_t =>
mem_addr1 <= std_logic_vector(unsigned(E_reg)+1);
when MA_newB_t =>
mem_addr1 <= NewB_reg;
when MA_B_t =>
mem_addr1 <= B_reg;
when MA_unwind_trail_t =>
mem_addr1 <= untrail_mem_addr_1;
when MA_DFC_t =>
mem_addr1 <= dfc_mem_addr1_out;
when others =>
null;
end case;
end process;
ADDR2MUX: process(deref1_res_out, dfc_mem_addr2, H_reg, deref1_mem_addr1, bind_mem_addr1, bind_mem_addr2, unifyComb_mem_addr2, S_reg,
E_reg, dfc_instruction_in, B_reg, NewE_reg, NewB_reg, NRARGS_reg, dfc_i, untrail_mem_addr_2, dfc_mem_addr2_out)
begin
mem_addr2 <= (others => '0');
case dfc_mem_addr2 is
when MA_H_t =>
mem_addr2 <= H_reg;
when MA_Hplus1_t =>
mem_addr2 <= std_logic_vector(unsigned(H_reg)+1);
when MA_deref_unit_t =>
mem_addr2 <= deref1_mem_addr1;
when MA_bind_unit_1_t =>
mem_addr2 <= bind_mem_addr1;
when MA_bind_unit_2_t =>
mem_addr2 <= bind_mem_addr2;
when MA_unify_unit_t =>
mem_addr2 <= unifyComb_mem_addr2;
when MA_stack_addr_t => -- TODO
mem_addr2 <= fpwam_var_stack_addr(dfc_instruction_in, E_reg);
when MA_S_t =>
mem_addr2 <= S_reg;
when MA_untag_deref_t =>
mem_addr2 <= fpwam_value(deref1_res_out);
when MA_Ep2orB_t =>
if E_reg > B_reg then
mem_addr2 <= std_logic_vector(unsigned(E_reg)+2);
else
mem_addr2 <= B_reg;
end if;
when MA_newE_t =>
mem_addr2 <= NewE_reg;
when MA_newEp1_t =>
mem_addr2 <= std_logic_vector(unsigned(NewE_reg)+1);
when MA_newEp2_t =>
mem_addr2 <= std_logic_vector(unsigned(NewE_reg)+2);
when MA_E_t =>
mem_addr2 <= E_reg;
when MA_Ep1_t =>
mem_addr2 <= std_logic_vector(unsigned(E_reg)+1);
when MA_newB_t =>
mem_addr2 <= NewB_reg;
when MA_B_t =>
mem_addr2 <= B_reg;
when MA_unwind_trail_t =>
mem_addr2 <= untrail_mem_addr_2;
when MA_DFC_t =>
mem_addr2 <= dfc_mem_addr2_out;
when others =>
null;
end case;
end process;
PORT1MUX: process(dfc_mem_input1, mem_output_2,H_reg, dfc_instruction_in, gpr_output1, bind_mem_word1, bind_mem_word2, unifyComb_mem_word1, mem_input_2,
gpr_output1, gpr_output2, E_reg, CP_reg, B_reg, TR_reg, NRARGS_reg, untrail_mem_port_1, dfc_mem_out1, deref1_res_out, P_reg)
begin
mem_input_1 <= (others => '0');
case dfc_mem_input1 is
when MI_str_Hplus1_t =>
mem_input_1 <= fpwam_word(std_logic_vector(unsigned(H_reg)+1), tag_str_t);
when MI_constant_t =>
mem_input_1 <= dfc_instruction_in(kWamWordWidth -1 downto 0);
when MI_GPR_t =>
mem_input_1 <= gpr_output1;
when MI_GPR2_t =>
mem_input_1 <= gpr_output2;
when MI_bind_unit_1_t =>
mem_input_1 <= bind_mem_word1;
when MI_bind_unit_2_t =>
mem_input_1 <= bind_mem_word2;
when MI_unify_unit_t =>
mem_input_1 <= unifyComb_mem_word1;
when MI_ref_H_t =>
mem_input_1 <= fpwam_word(H_reg, tag_ref_t);
when MI_mem_port2_t =>
mem_input_1 <= mem_output_2;
when MI_E_t =>
mem_input_1 <= "00"&E_reg; -- TEMPORARY FIX
when MI_CP_t =>
mem_input_1 <= "00000000"&CP_reg; -- TEMPORARY FIX
when MI_ref_addr_t =>
mem_input_1 <= fpwam_word(fpwam_var_stack_addr(dfc_instruction_in, E_reg), tag_ref_t);
when MI_B_t =>
mem_input_1 <= "00"&B_reg; -- TEMPORARY FIX
when MI_TR_t =>
mem_input_1 <= "00000000"&TR_reg; -- TEMPORARY FIX
when MI_NRAGRGS_t =>
mem_input_1 <= "00000000000000"&NRARGS_reg; -- TEMPORARY FIX
when MI_unwind_trail_t =>
mem_input_1 <= untrail_mem_port_1;
when MI_H_t =>
mem_input_1 <= "00"&H_reg;
when MI_dfc_t =>
mem_input_1 <= dfc_mem_out1;
when MI_deref_t =>
mem_input_1 <= deref1_res_out;
when MI_lis_Hplus1_t =>
mem_input_1 <= fpwam_word(std_logic_vector(unsigned(H_reg)+1), tag_lis_t);
when MI_P_t =>
mem_input_1 <= "00000000"&std_logic_vector(unsigned(P_reg));
when others =>
null;
end case;
end process;
PORT2MUX: process(dfc_mem_input2, H_reg, mem_output_1, dfc_instruction_in, gpr_output1, bind_mem_word1, bind_mem_word2, unifyComb_mem_word2, mem_input_1,
gpr_output1, gpr_output2, E_reg, CP_reg, B_reg, TR_reg, NRARGS_reg, untrail_mem_port_2, dfc_mem_out2, deref1_res_out, P_reg )
begin
mem_input_2 <= (others => '0');
case dfc_mem_input2 is
when MI_str_Hplus1_t =>
mem_input_2 <= fpwam_word(std_logic_vector(unsigned(H_reg)+1), tag_str_t);
when MI_constant_t =>
mem_input_2 <= dfc_instruction_in(kWamWordWidth -1 downto 0);
when MI_GPR_t =>
mem_input_2 <= gpr_output1;
when MI_GPR2_t =>
mem_input_2 <= gpr_output2;
when MI_bind_unit_1_t =>
mem_input_2 <= bind_mem_word1;
when MI_bind_unit_2_t =>
mem_input_2 <= bind_mem_word2;
when MI_unify_unit_t =>
mem_input_2 <= unifyComb_mem_word2;
when MI_ref_H_t =>
mem_input_2 <= fpwam_word(H_reg, tag_ref_t);
when MI_mem_port1_t =>
mem_input_2 <= mem_output_1;
when MI_E_t =>
mem_input_2 <= "00"&E_reg; -- TEMPORARY FIX
when MI_CP_t =>
mem_input_2 <= "00000000"&CP_reg; -- TEMPORARY FIX
when MI_ref_addr_t =>
mem_input_2 <= fpwam_word(fpwam_var_stack_addr(dfc_instruction_in, E_reg), tag_ref_t);
when MI_B_t =>
mem_input_2 <= "00"&B_reg; -- TEMPORARY FIX
when MI_TR_t =>
mem_input_2 <= "00000000"&TR_reg; -- TEMPORARY FIX
when MI_NRAGRGS_t =>
mem_input_2 <= "00000000000000"&NRARGS_reg; -- TEMPORARY FIX
when MI_unwind_trail_t =>
mem_input_2 <= untrail_mem_port_2;
when MI_H_t =>
mem_input_2 <= "00"&H_reg;
when MI_dfc_t =>
mem_input_2 <= dfc_mem_out2;
when MI_deref_t =>
mem_input_2 <= deref1_res_out;
when MI_lis_Hplus1_t =>
mem_input_2 <= fpwam_word(std_logic_vector(unsigned(H_reg)+1), tag_lis_t);
when MI_P_t =>
mem_input_2 <= "00000000"&std_logic_vector(unsigned(P_reg));
when others =>
null;
end case;
end process;
HEAPSTACK: entity work.Memory(Behavioral)
generic map
(
kMemAddressWidth => kWamAddressWidth
,kWordWidth => kWamWordWidth
)
port map
(
clk => clk
,addr_port_1 => mem_addr1
,word_port_1_o => mem_output_1
,word_port_1_i => mem_input_1
,wr_port_1 => mem_port1_wr
,rd_port_1 => mem_port1_rd
,addr_port_2 => mem_addr2
,word_port_2_o => mem_output_2
,word_port_2_i => mem_input_2
,wr_port_2 => mem_port2_wr
,rd_port_2 => mem_port2_rd
);
-- STACK AND HEAP MEMORY END
-- GPRs BEGIN
gpr_address1 <= dfc_instruction_in(kGPRAddressWidth-1 + kWamWordWidth downto kWamWordWidth) when dfc_gpr_addr1 = GPRA_instr_t else
std_logic_vector(dfc_i(kGPRAddressWidth-1 downto 0)) when dfc_gpr_addr1 = GPRA_I_t else
std_logic_vector(to_unsigned(1, kGPRAddressWidth)) when dfc_gpr_addr1 = GPRA_1_t else
std_logic_vector(dfc_i(kGPRAddressWidth-1 downto 0) + 1);
gpr_wr1 <= dfc_gpr_wr1;
GPRINMUX: process(dfc_gpr_input1, H_reg, mem_output_1, mem_output_2, E_reg, deref1_res_out, dfc_instruction_in)
begin
gpr_input1 <= (others => '0');
case dfc_gpr_input1 is
when GPRI_ref_H_t =>
gpr_input1 <= fpwam_word(H_reg, tag_ref_t);
when GPRI_mem_port1_t =>
gpr_input1 <= mem_output_1;
when GPRI_mem_port2_t =>
gpr_input1 <= mem_output_2;
when GPRI_str_H_t =>
gpr_input1 <= fpwam_word(H_reg, tag_str_t);
when GPRI_ref_addr_t =>
gpr_input1 <= fpwam_word(fpwam_var_stack_addr(dfc_instruction_in, E_reg), tag_ref_t);
when GPRI_lis_H_t =>
gpr_input1 <= fpwam_word(H_reg, tag_lis_t);
when GPRI_con_t =>
gpr_input1 <= dfc_instruction_in(kWamWordWidth -1 downto 0);
when GPRI_deref_t =>
gpr_input1 <= deref1_res_out;
when GPRI_constant_t =>
gpr_input1 <= dfc_instruction_in(kWamWordWidth -1 downto 0);
when GPRI_gpr2_t =>
gpr_input1 <= gpr_output2;
when others =>
null;
end case;
end process;
gpr_address2 <= dfc_instruction_in(kGPRAddressWidth-1 downto 0) when dfc_gpr_addr2 = GPRA_instr_t else
std_logic_vector(dfc_i(kGPRAddressWidth-1 downto 0)) when dfc_gpr_addr2 = GPRA_I_t else
std_logic_vector(to_unsigned(1, kGPRAddressWidth)) when dfc_gpr_addr2 = GPRA_1_t else
std_logic_vector(dfc_i(kGPRAddressWidth-1 downto 0) + 1);
gpr_wr2 <= dfc_gpr_wr2;
GPRINMUX2: process(dfc_gpr_input2, H_reg, mem_output_1, mem_output_2, E_reg, deref1_res_out, dfc_instruction_in)
begin
gpr_input2 <= (others => '0');
case dfc_gpr_input2 is
when GPRI_ref_H_t =>
gpr_input2 <= fpwam_word(H_reg, tag_ref_t);
when GPRI_mem_port1_t =>
gpr_input2 <= mem_output_1;
when GPRI_mem_port2_t =>
gpr_input2 <= mem_output_2;
when GPRI_ref_addr_t =>
gpr_input2 <= fpwam_word(fpwam_var_stack_addr(dfc_instruction_in, E_reg), tag_ref_t);
when GPRI_lis_H_t =>
gpr_input2 <= fpwam_word(H_reg, tag_lis_t);
when GPRI_con_t =>
gpr_input2 <= dfc_instruction_in(kWamWordWidth -1 downto 0);
when GPRI_deref_t =>
gpr_input2 <= deref1_res_out;
when GPRI_gpr1_t =>
gpr_input2 <= gpr_output1;
when GPRI_constant_t =>
gpr_input2 <= dfc_instruction_in(kWamWordWidth -1 downto 0);
when others =>
null;
end case;
end process;
GPRS: entity work.GPR(Behavioral)
generic map
(
kAddressWidth => kGPRAddressWidth
,kWordWidth => kWamWordWidth
)
port map
(
clk => clk
,address1 => gpr_address1
,wr1 => gpr_wr1
,input_word1 => gpr_input1
,output_word1 => gpr_output1
,address2 => gpr_address2
,wr2 => gpr_wr2
,input_word2 => gpr_input2
,output_word2 => gpr_output2
);
-- GPRs END
-- BIND START
bind_start <= dfc_bind_start
or unify_bind_start;
BINDINPUT1MUX: process(dfc_bind_port1, deref1_res_out, mem_output_1, unify_bind_word1)
begin
bind_word1 <= (others => '0');
case dfc_bind_port1 is
when BI_deref_unit_t =>
bind_word1 <= deref1_res_out;
when BI_mem_port1_t =>
bind_word1 <= mem_output_1;
when BI_unify_unit_t =>
bind_word1 <= unify_bind_word1;
when others =>
null;
end case;
end process;
BINDINPUT2MUX: process(dfc_bind_port2, deref1_res_out, mem_output_1, unify_bind_word2)
begin
bind_word2 <= (others => '0');
case dfc_bind_port2 is
when BI_deref_unit_t =>
bind_word2 <= deref1_res_out;
when BI_mem_port1_t =>
bind_word2 <= mem_output_1;
when BI_unify_unit_t =>
bind_word2 <= unify_bind_word2;
when others =>
null;
end case;
end process;
BINDUNIT: entity work.BindUnit(Behavioral)
generic map
(
kAddressWidth => kWamAddressWidth
,kWordWidth => kWamWordWidth
)
port map
(
clk => clk
,rst => rst
,start_bind => bind_start
,start_word1 => bind_word1
,start_word2 => bind_word2
,mem_addr1 => bind_mem_addr1
,mem_out1 => bind_mem_word1
,mem_wr_1 => bind_mem_port1_wr
,mem_addr2 => bind_mem_addr2
,mem_out2 => bind_mem_word2
,mem_wr_2 => bind_mem_port2_wr
,trail_input => bind_trail_input
,trail => bind_trail
,bind_done => bind_done
);
-- BIND end
-- DEREF1 START
deref1_start <= dfc_deref1_start
or unify_deref1_start;
deref1_mem_word1 <= mem_output_1;
DEREFINPUTMUX: process(dfc_deref1_input, gpr_output1, mem_output_1, mem_output_2, unify_deref1_out, dfc_instruction_in, E_reg)
begin
deref1_word <= (others => '0');
case dfc_deref1_input is
when DI_GPR_t =>
deref1_word <= gpr_output1;
when DI_unify_unit_t =>
deref1_word <= unify_deref1_out;
when DI_EYnp2_t =>
deref1_word <= fpwam_word(std_logic_vector(unsigned(E_reg)+
unsigned(dfc_instruction_in(kGPRAddressWidth-1 + kWamWordWidth downto kWamWordWidth))+2), tag_ref_t);
when DI_mem_port1_t =>
deref1_word <= mem_output_1;
when others =>
null;
end case;
end process;
deref1_addr <= fpwam_value(deref1_addr_word);
DEREF1: entity work.DerefUnit(Behavioral)
generic map
(
kAddressWidth => kWamAddressWidth
,kWordWidth => kWamWordWidth
)
port map
(
clk => clk
,rst => rst
,start_deref => deref1_start
,start_word => deref1_word
,memory_in => deref1_mem_word1
,addr_out => deref1_mem_addr1
,rd_mem => deref1_mem_port1_rd
,res_out => deref1_res_out
,res_addr => deref1_addr_word
,done => deref1_done
);
-- DEREF1 END
-- DEREF2 START
deref2_start <= unify_deref2_start;
deref2_mem_word2 <= mem_output_2;
deref2_word <= unify_deref2_out;
DEREF2: entity work.DerefUnit(Behavioral)
generic map
(
kAddressWidth => kWamAddressWidth
,kWordWidth => kWamWordWidth
)
port map
(
clk => clk
,rst => rst
,start_deref => deref2_start
,start_word => deref2_word
,memory_in => deref2_mem_word2
,addr_out => deref2_mem_addr2
,rd_mem => deref2_mem_port2_rd
,res_out => deref2_res_out
,res_addr => open
,done => deref2_done
);
-- DEREF2 END
-- UNIFYUNIT START
unify_start <= dfc_unify_start;
UNIFY1MUX: process(dfc_unify_input_a, gpr_output1, mem_output_1, mem_output_2)
begin
unify_word1 <= (others => '0');
case dfc_unify_input_a is
when UI_GPR_t =>
unify_word1 <= gpr_output1;
when UI_mem_port1_t =>
unify_word1 <= mem_output_1;
when UI_mem_port2_t =>
unify_word1 <= mem_output_2;
when others =>
null;
end case;
end process;
UNIFY2MUX: process(dfc_unify_input_b, gpr_output1, mem_output_1, mem_output_2, gpr_output2)
begin
unify_word2 <= (others => '0');
case dfc_unify_input_b is
when UI_GPR_t =>
unify_word2 <= gpr_output2;
when UI_mem_port1_t =>
unify_word2 <= mem_output_1;
when UI_mem_port2_t =>
unify_word2 <= mem_output_2;
when others =>
null;
end case;
end process;
UNIFYMEMSEL: process(unify_mem_sel, unify_mem_addr1, unify_mem_addr2, deref1_mem_addr1, deref2_mem_addr2, deref1_mem_word1, deref2_mem_word2, bind_mem_word1, bind_mem_word2, bind_mem_addr1, bind_mem_addr2)
begin
unifyComb_mem_addr1 <= (others => '0');
unifyComb_mem_addr2 <= (others => '0');
unifyComb_mem_word1 <= (others => '0');
unifyComb_mem_word2 <= (others => '0');
case unify_mem_sel is
when sel_unify_t =>
unifyComb_mem_addr1 <= unify_mem_addr1;
unifyComb_mem_addr2 <= unify_mem_addr2;
when sel_deref_t =>
unifyComb_mem_addr1 <= deref1_mem_addr1;
unifyComb_mem_addr2 <= deref2_mem_addr2;
unifyComb_mem_word1 <= deref1_mem_word1;
unifyComb_mem_word2 <= deref2_mem_word2;
when sel_bind_t =>
unifyComb_mem_addr1 <= bind_mem_addr1;
unifyComb_mem_addr2 <= bind_mem_addr2;
unifyComb_mem_word1 <= bind_mem_word1;
unifyComb_mem_word2 <= bind_mem_word2;
when others =>
null;
end case;
end process;
unify_mem_word1 <= mem_output_1;
unify_mem_word2 <= mem_output_2;
UNIFYU: entity work.UnifyUnit(Behavioral)
generic map
(
kAddressWidth => kWamAddressWidth
,kWordWidth => kWamWordWidth
,kPdlAddressWidth => kWamPdlAddressWidth
)
port map
(
clk => clk
,rst => rst
,start_unify => unify_start
,word1 => unify_word1
,word2 => unify_word2
,mem1_input => unify_mem_word1
,mem2_input => unify_mem_word2
,deref1_input => deref1_res_out
,deref1_done => deref1_done
,deref2_input => deref2_res_out
,deref2_done => deref2_done
,bind_done => bind_done
,unify_done => unify_done
,fail => unify_fail
,mem1_output => unify_mem_addr1
,rd_mem_port1 => unify_mem_port1_rd
,mem2_output => unify_mem_addr2
,rd_mem_port2 => unify_mem_port2_rd
,deref1_output => unify_deref1_out
,deref1_start => unify_deref1_start
,deref2_output => unify_deref2_out
,deref2_start => unify_deref2_start
,bind1_output => unify_bind_word1
,bind2_output => unify_bind_word2
,bind_start => unify_bind_start
,mem_sel => unify_mem_sel
);
-- UNIFYUNIT END
-- DFC BEGIN
dfc_instruction_valid <= instruction_valid;
dfc_mem_word1 <= mem_output_2;
dfc_deref1_done <= deref1_done;
dfc_mode_reg <= M_reg;
dfc_nr_args <= NRARGS_reg;
dfc_unify_done <= unify_done;
dfc_bind_done <= bind_done;
dfc_local_fail <= LCLFAIL_reg;
dfc_global_fail <= GLBFAIL_reg;
dfc_b_reg <= B_reg;
dfc_new_b_reg <= NewB_reg;
dfc_unwind_done <= untrail_done;
dfc_deref_addr <= deref1_addr;
dfc_deref_word <= deref1_res_out;
dfc_h_reg <= H_reg;
dfc_e_reg <= E_reg;
dfc_bsearch_done <= bsearch_done;
dfc_bsearch_found <= bsearch_found;
DFC: entity work.DataFlowControl(Behavioral)
port map
(
clk => clk
,rst => rst
,instruction => dfc_instruction_in
,instruction_valid => dfc_instruction_valid
,mem_obj => dfc_mem_word1
,deref_done => dfc_deref1_done
,mode_reg => dfc_mode_reg
,unify_done => dfc_unify_done
,bind_done => dfc_bind_done
,nr_args => dfc_nr_args
,unwind_done => dfc_unwind_done
,local_fail => dfc_local_fail
,global_fail => dfc_global_fail
,b_reg => dfc_b_reg
,new_b_reg => dfc_new_b_reg
,deref_addr => dfc_deref_addr
,deref_word => dfc_deref_word
,H_reg => dfc_h_reg
,E_reg => dfc_e_reg
,bsearch_done => dfc_bsearch_done
,bsearch_found => dfc_bsearch_found
,local_fail_rst => dfc_local_fail_rst
,global_fail_out => dfc_global_fail_out
,global_fail_rst => dfc_global_fail_rst
,get_instruction => dfc_get_instruction
,start_deref => dfc_deref1_start
,deref_input => dfc_deref1_input
,wr_s_reg => dfc_S_wr
,s_reg_input => dfc_S_input
,wr_mode_reg => dfc_mode_wr
,mode_value => dfc_mode_value
,rd_mem_port1 => dfc_mem_port1_rd
,wr_mem_port1 => dfc_mem_port1_wr
,mem_input1 => dfc_mem_input1
,mem_addr_input1 => dfc_mem_addr1
,rd_mem_port2 => dfc_mem_port2_rd
,wr_mem_port2 => dfc_mem_port2_wr
,mem_input2 => dfc_mem_input2
,mem_addr_input2 => dfc_mem_addr2
,bind => dfc_bind_start
,bind_port1 => dfc_bind_port1
,bind_port2 => dfc_bind_port2
,trail_input => dfc_trail_input
,wr_h_reg => dfc_H_wr
,h_input => dfc_H_input
,wr_gpr1 => dfc_gpr_wr1
,gpr_addr1 => dfc_gpr_addr1
,gpr_input1 => dfc_gpr_input1
,wr_gpr2 => dfc_gpr_wr2
,gpr_addr2 => dfc_gpr_addr2
,gpr_input2 => dfc_gpr_input2
,start_unify => dfc_unify_start
,unify_input_a => dfc_unify_input_a
,unify_input_b => dfc_unify_input_b
,p_input => dfc_P_input
,p_wr => dfc_P_wr
,cp_wr => dfc_CP_wr
,cp_input => dfc_CP_input
,nrargs_wr => dfc_nr_wr
,nrargs_input => dfc_nr_input
,newE_wr => dfc_newE_wr
,E_wr => dfc_E_wr
,e_input => dfc_E_input
,b_input => dfc_B_input
,b_wr => dfc_B_wr
,newB_wr => dfc_newB_wr
,tr_wr => dfc_tr_wr
,tr_input => dfc_tr_input
,hb_wr => dfc_hb_wr
,hb_input => dfc_hb_input
,i => dfc_i
,start_unwind => dfc_start_unwind
,mem_addr1 => dfc_mem_addr1_out
,mem_addr2 => dfc_mem_addr2_out
,mem_out1 => dfc_mem_out1
,mem_out2 => dfc_mem_out2
,trail_do => dfc_trail_do
,bladdr_wr => dfc_bladdr_wr
,bhaddr_wr => dfc_bhaddr_wr
,bsearch_start => dfc_bsearch_start
);
-- DFC END
-- TRAIL BEGIN
trail_start <= bind_trail or dfc_trail_do;
trail_address <= bind_trail_input when dfc_trail_input = TI_bind_output_t else
fpwam_value(deref1_res_out) when dfc_trail_input = TI_deref_t else
bind_trail_input;
trail_H <= H_reg;
trail_HB <= HB_reg;
trail_B <= B_reg;
TRAILUNIT: entity work.TrailUnit(Behavioral)
generic map
(
kAddressWidth => kWamAddressWidth
)
port map
(
trail => trail_start
,trail_address => trail_address
,H => trail_H
,HB => trail_HB
,B => trail_B
,a => trail_a
,do_trail => trail_do
);
trailm_addr_1 <= TR_reg when dfc_trail_input = TI_bind_output_t else
untrail_addr_1 when dfc_trail_input = TI_unwind_trail_t else
TR_reg;
trailm_input_1 <= trail_a;
trailm_wr_1 <= trail_do;
trailm_rd_1 <= untrail_port_1_rd or trailm_wr_1;
trailm_addr_2 <= untrail_addr_2;
trailm_wr_2 <= '0';
trailm_rd_2 <= untrail_port_2_rd;
TRAIL: entity work.Memory(Behavioral)
generic map
(
kMemAddressWidth => kWamTrailAddressWidth
,kWordWidth => kWamAddressWidth
)
port map
(
clk => clk
,addr_port_1 => trailm_addr_1
,word_port_1_o => trailm_output_1
,word_port_1_i => trailm_input_1
,wr_port_1 => trailm_wr_1
,rd_port_1 => trailm_rd_1
,addr_port_2 => trailm_addr_2
,word_port_2_o => trailm_output_2
,word_port_2_i => trailm_input_2
,wr_port_2 => trailm_wr_2
,rd_port_2 => trailm_rd_2
);
untrail_start <= dfc_start_unwind;
untrail_a1 <= mem_output_1(kWamTrailAddressWidth -1 downto 0);
untrail_a2 <= TR_reg;
untrail_port_1 <= trailm_output_1;
untrail_port_2 <= trailm_output_2;
UNWINDTRAIL: entity work.UnwindTrailUnit(Behavioral)
port map
(
clk => clk
,rst => rst
,start_unwind => untrail_start
,a1 => untrail_a1
,a2 => untrail_a2
,trail_port_1 => untrail_port_1
,trail_port_1_rd => untrail_port_1_rd
,trail_addr_1 => untrail_addr_1
,trail_port_2 => untrail_port_2
,trail_port_2_rd => untrail_port_2_rd
,trail_addr_2 => untrail_addr_2
,mem_port_1 => untrail_mem_port_1
,mem_port_1_wr => untrail_mem_port_1_wr
,mem_addr_1 => untrail_mem_addr_1
,mem_port_2 => untrail_mem_port_2
,mem_port_2_wr => untrail_mem_port_2_wr
,mem_addr_2 => untrail_mem_addr_2
,done => untrail_done
);
bsearch_word <= deref1_res_out;
bsearch_low_addr <= bsearch_laddr_reg;
bsearch_high_addr <= bsearch_haddr_reg;
bsearch_start <= dfc_bsearch_start;
bsearch_memory_in <= bmem_port_1_out(kWamWordWidth+kWamInstrMemWidth -1 downto kWamInstrMemWidth);
BSEARCH: entity work.BinarySearch(Behavioral)
generic map
(
kWordWidth => kWamWordWidth
,kMemAddressWidth => kWamInstrMemWidth
)
port map
(
clk => clk
,rst => rst
,search_word => bsearch_word
,low_address => bsearch_low_addr
,high_address => bsearch_high_addr
,start_search => bsearch_start
,done => bsearch_done
,found => bsearch_found
,memory_in => bsearch_memory_in
,memory_address_out => bsearch_addr_out
,memory_read => bsearch_memory_read
);
bmem_addr_port_1 <= bsearch_addr_out;
bmem_port_1_rd <= bsearch_memory_read;
BMEM: entity work.Memory(Behavioral)
generic map
(
kMemAddressWidth => kWamInstrMemWidth
,kWordWidth => kWamWordWidth+kWamInstrMemWidth
)
port map
(
clk => clk
,addr_port_1 => bmem_addr_port_1
,word_port_1_o => bmem_port_1_out
,word_port_1_i => bmem_port_1_in
,wr_port_1 => bmem_port_1_wr
,rd_port_1 => bmem_port_1_rd
,addr_port_2 => bmem_addr_port_2
,word_port_2_o => bmem_port_2_out
,word_port_2_i => bmem_port_2_in
,wr_port_2 => bmem_port_2_wr
,rd_port_2 => bmem_port_2_rd
);
end Structural;
|
-- MIL-STD-1553 controllers
constant CFG_GR1553B_ENABLE : integer := CONFIG_GR1553B_ENABLE;
constant CFG_GR1553B_RTEN : integer := CONFIG_GR1553B_RTEN;
constant CFG_GR1553B_BCEN : integer := CONFIG_GR1553B_BCEN;
constant CFG_GR1553B_BMEN : integer := CONFIG_GR1553B_BMEN;
|
-- MIL-STD-1553 controllers
constant CFG_GR1553B_ENABLE : integer := CONFIG_GR1553B_ENABLE;
constant CFG_GR1553B_RTEN : integer := CONFIG_GR1553B_RTEN;
constant CFG_GR1553B_BCEN : integer := CONFIG_GR1553B_BCEN;
constant CFG_GR1553B_BMEN : integer := CONFIG_GR1553B_BMEN;
|
-- MIL-STD-1553 controllers
constant CFG_GR1553B_ENABLE : integer := CONFIG_GR1553B_ENABLE;
constant CFG_GR1553B_RTEN : integer := CONFIG_GR1553B_RTEN;
constant CFG_GR1553B_BCEN : integer := CONFIG_GR1553B_BCEN;
constant CFG_GR1553B_BMEN : integer := CONFIG_GR1553B_BMEN;
|
-- MIL-STD-1553 controllers
constant CFG_GR1553B_ENABLE : integer := CONFIG_GR1553B_ENABLE;
constant CFG_GR1553B_RTEN : integer := CONFIG_GR1553B_RTEN;
constant CFG_GR1553B_BCEN : integer := CONFIG_GR1553B_BCEN;
constant CFG_GR1553B_BMEN : integer := CONFIG_GR1553B_BMEN;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
entity lpddr2if is
generic (
hindex: integer;
haddr: integer := 16#400#;
hmask: integer := 16#000#;
burstlen: integer := 8
);
port (
pll_ref_clk: in std_ulogic;
global_reset_n: in std_ulogic;
mem_ca: out std_logic_vector(9 downto 0);
mem_ck: out std_ulogic;
mem_ck_n: out std_ulogic;
mem_cke: out std_ulogic;
mem_cs_n: out std_ulogic;
mem_dm: out std_logic_vector(1 downto 0);
mem_dq: inout std_logic_vector(15 downto 0);
mem_dqs: inout std_logic_vector(1 downto 0);
mem_dqs_n: inout std_logic_vector(1 downto 0);
oct_rzqin: in std_logic;
ahb_clk: in std_ulogic;
ahb_rst: in std_ulogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type
);
end;
architecture rtl of lpddr2if is
component lpddr2ctrl1 is
port (
pll_ref_clk : in std_logic := 'X'; -- clk
global_reset_n : in std_logic := 'X'; -- reset_n
soft_reset_n : in std_logic := 'X'; -- reset_n
afi_clk : out std_logic; -- clk
afi_half_clk : out std_logic; -- clk
afi_reset_n : out std_logic; -- reset_n
afi_reset_export_n : out std_logic; -- reset_n
mem_ca : out std_logic_vector(9 downto 0); -- mem_ca
mem_ck : out std_logic_vector(0 downto 0); -- mem_ck
mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_dm : out std_logic_vector(1 downto 0); -- mem_dm
mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs
mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n
avl_ready : out std_logic; -- waitrequest_n
avl_burstbegin : in std_logic := 'X'; -- beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
avl_rdata_valid : out std_logic; -- readdatavalid
avl_rdata : out std_logic_vector(63 downto 0); -- readdata
avl_wdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- writedata
avl_be : in std_logic_vector(7 downto 0) := (others => 'X'); -- byteenable
avl_read_req : in std_logic := 'X'; -- read
avl_write_req : in std_logic := 'X'; -- write
avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
local_init_done : out std_logic; -- local_init_done
local_cal_success : out std_logic; -- local_cal_success
local_cal_fail : out std_logic; -- local_cal_fail
oct_rzqin : in std_logic := 'X'; -- rzqin
pll_mem_clk : out std_logic; -- pll_mem_clk
pll_write_clk : out std_logic; -- pll_write_clk
pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk
pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk
pll_locked : out std_logic; -- pll_locked
pll_avl_clk : out std_logic; -- pll_avl_clk
pll_config_clk : out std_logic; -- pll_config_clk
pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk
afi_phy_clk : out std_logic; -- afi_phy_clk
pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk
);
end component lpddr2ctrl1;
signal vcc: std_ulogic;
signal afi_clk, afi_half_clk, afi_reset_n: std_ulogic;
signal local_init_done, local_cal_success, local_cal_fail: std_ulogic;
signal ck_p_arr, ck_n_arr, cke_arr, cs_arr: std_logic_vector(0 downto 0);
signal avlsi: ddravl_slv_in_type;
signal avlso: ddravl_slv_out_type;
begin
vcc <= '1';
mem_ck <= ck_p_arr(0);
mem_ck_n <= ck_n_arr(0);
mem_cke <= cke_arr(0);
mem_cs_n <= cs_arr(0);
ctrl0: lpddr2ctrl1
port map (
pll_ref_clk => pll_ref_clk,
global_reset_n => global_reset_n,
soft_reset_n => vcc,
afi_clk => afi_clk,
afi_half_clk => afi_half_clk,
afi_reset_n => afi_reset_n,
afi_reset_export_n => open,
mem_ca => mem_ca,
mem_ck => ck_p_arr,
mem_ck_n => ck_n_arr,
mem_cke => cke_arr,
mem_cs_n => cs_arr,
mem_dm => mem_dm,
mem_dq => mem_dq,
mem_dqs => mem_dqs,
mem_dqs_n => mem_dqs_n,
avl_ready => avlso.ready,
avl_burstbegin => avlsi.burstbegin,
avl_addr => avlsi.addr(24 downto 0),
avl_rdata_valid => avlso.rdata_valid,
avl_rdata => avlso.rdata(63 downto 0),
avl_wdata => avlsi.wdata(63 downto 0),
avl_be => avlsi.be(7 downto 0),
avl_read_req => avlsi.read_req,
avl_write_req => avlsi.write_req,
avl_size => avlsi.size(2 downto 0),
local_init_done => local_init_done,
local_cal_success => local_cal_success,
local_cal_fail => local_cal_fail,
oct_rzqin => oct_rzqin,
pll_mem_clk => open,
pll_write_clk => open,
pll_write_clk_pre_phy_clk => open,
pll_addr_cmd_clk => open,
pll_locked => open,
pll_avl_clk => open,
pll_config_clk => open,
pll_mem_phy_clk => open,
afi_phy_clk => open,
pll_avl_phy_clk => open
);
avlso.rdata(avlso.rdata'high downto 64) <= (others => '0');
ahb2avl0: ahb2avl_async
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
burstlen => burstlen,
nosync => 0,
avldbits => 64,
avlabits => 25
)
port map (
rst_ahb => ahb_rst,
clk_ahb => ahb_clk,
ahbsi => ahbsi,
ahbso => ahbso,
rst_avl => afi_reset_n,
clk_avl => afi_clk,
avlsi => avlsi,
avlso => avlso
);
end;
|
architecture RTL of FIFO is
constant con1 : integer := a + b + c + d;
constant con1 : integer :=
a + b + c + d;
constant con2 : integer := a + b +
c + d;
constant con3 : integer :=
(
0,
1,
2,
3
);
constant con4 : dictionary :=
(
(3, 4, 5),
(1, 2, 3),
(9, 8, 7)
);
-- Violations
constant con2 : integer := a + b +
c + d;
constant con2 : integer := a + b +
c + d;
constant con1 : integer :=
a + b + c + d;
constant con3 : integer :=
(
0,
1,
2,
3
);
constant con4 : dictionary :=
(
(3, 4, 5),
(1, 2, 3),
(9, 8, 7)
);
begin
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1322.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p09n04i01322ent IS
END c08s04b00x00p09n04i01322ent;
ARCHITECTURE c08s04b00x00p09n04i01322arch OF c08s04b00x00p09n04i01322ent IS
signal S1 : BIT := '1';
signal S2 : BIT := '1';
BEGIN
S1 <= transport '0' after 5 ns,
'1' after 10 ns;
S2 <= S1 after 15 ns;
TESTING: PROCESS(S2)
BEGIN
assert NOT( S2 = '1' )
report "***PASSED TEST: c08s04b00x00p09n04i01322"
severity NOTE;
assert ( S2 = '1' )
report "***FAILED TEST: c08s04b00x00p09n04i01322 - A pulse whose duration is shorter than the switching time of the circuit is not transmitted."
severity ERROR;
END PROCESS TESTING;
END c08s04b00x00p09n04i01322arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1322.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p09n04i01322ent IS
END c08s04b00x00p09n04i01322ent;
ARCHITECTURE c08s04b00x00p09n04i01322arch OF c08s04b00x00p09n04i01322ent IS
signal S1 : BIT := '1';
signal S2 : BIT := '1';
BEGIN
S1 <= transport '0' after 5 ns,
'1' after 10 ns;
S2 <= S1 after 15 ns;
TESTING: PROCESS(S2)
BEGIN
assert NOT( S2 = '1' )
report "***PASSED TEST: c08s04b00x00p09n04i01322"
severity NOTE;
assert ( S2 = '1' )
report "***FAILED TEST: c08s04b00x00p09n04i01322 - A pulse whose duration is shorter than the switching time of the circuit is not transmitted."
severity ERROR;
END PROCESS TESTING;
END c08s04b00x00p09n04i01322arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1322.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p09n04i01322ent IS
END c08s04b00x00p09n04i01322ent;
ARCHITECTURE c08s04b00x00p09n04i01322arch OF c08s04b00x00p09n04i01322ent IS
signal S1 : BIT := '1';
signal S2 : BIT := '1';
BEGIN
S1 <= transport '0' after 5 ns,
'1' after 10 ns;
S2 <= S1 after 15 ns;
TESTING: PROCESS(S2)
BEGIN
assert NOT( S2 = '1' )
report "***PASSED TEST: c08s04b00x00p09n04i01322"
severity NOTE;
assert ( S2 = '1' )
report "***FAILED TEST: c08s04b00x00p09n04i01322 - A pulse whose duration is shorter than the switching time of the circuit is not transmitted."
severity ERROR;
END PROCESS TESTING;
END c08s04b00x00p09n04i01322arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:17:21 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_sim_netlist.vhdl
-- Design : system_zed_hdmi_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0_i2c_sender is
port (
hdmi_sda : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
clk_100 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zed_hdmi_0_0_i2c_sender : entity is "i2c_sender";
end system_zed_hdmi_0_0_i2c_sender;
architecture STRUCTURE of system_zed_hdmi_0_0_i2c_sender is
signal address : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \address[0]_i_1_n_0\ : STD_LOGIC;
signal \address[1]_i_1_n_0\ : STD_LOGIC;
signal \address[2]_i_1_n_0\ : STD_LOGIC;
signal \address[3]_i_1_n_0\ : STD_LOGIC;
signal \address[3]_i_2_n_0\ : STD_LOGIC;
signal \address[4]_i_1_n_0\ : STD_LOGIC;
signal \address[5]_i_1_n_0\ : STD_LOGIC;
signal \address[5]_i_2_n_0\ : STD_LOGIC;
signal \address[5]_i_3_n_0\ : STD_LOGIC;
signal \address[5]_i_4_n_0\ : STD_LOGIC;
signal \address[5]_i_5_n_0\ : STD_LOGIC;
signal \address[5]_i_6_n_0\ : STD_LOGIC;
signal \address[5]_i_7_n_0\ : STD_LOGIC;
signal busy_sr : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal clk_first_quarter : STD_LOGIC_VECTOR ( 28 to 28 );
signal \clk_first_quarter[28]_i_1_n_0\ : STD_LOGIC;
signal clk_last_quarter : STD_LOGIC_VECTOR ( 28 downto 1 );
signal \clk_last_quarter[2]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[0]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[0]_i_2_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal divider : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \divider[0]_i_1_n_0\ : STD_LOGIC;
signal \divider[1]_i_1_n_0\ : STD_LOGIC;
signal \divider[2]_i_1_n_0\ : STD_LOGIC;
signal \divider[3]_i_1_n_0\ : STD_LOGIC;
signal \divider[4]_i_1_n_0\ : STD_LOGIC;
signal \divider[5]_i_1_n_0\ : STD_LOGIC;
signal \divider[5]_i_2_n_0\ : STD_LOGIC;
signal \divider[6]_i_1_n_0\ : STD_LOGIC;
signal \divider[7]_i_1_n_0\ : STD_LOGIC;
signal \divider[7]_i_2_n_0\ : STD_LOGIC;
signal \divider[7]_i_3_n_0\ : STD_LOGIC;
signal finished_i_1_n_0 : STD_LOGIC;
signal finished_reg_n_0 : STD_LOGIC;
signal \initial_pause[5]_i_2_n_0\ : STD_LOGIC;
signal \initial_pause[7]_i_1_n_0\ : STD_LOGIC;
signal \initial_pause[7]_i_3_n_0\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[0]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[1]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[2]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[3]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[4]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[5]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[6]\ : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in : STD_LOGIC;
signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_2_in : STD_LOGIC_VECTOR ( 18 downto 2 );
signal reg_value_reg_n_10 : STD_LOGIC;
signal reg_value_reg_n_11 : STD_LOGIC;
signal reg_value_reg_n_12 : STD_LOGIC;
signal reg_value_reg_n_13 : STD_LOGIC;
signal reg_value_reg_n_14 : STD_LOGIC;
signal reg_value_reg_n_15 : STD_LOGIC;
signal reg_value_reg_n_8 : STD_LOGIC;
signal reg_value_reg_n_9 : STD_LOGIC;
signal \tristate_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[28]_inv_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg_gate__0_n_0\ : STD_LOGIC;
signal \tristate_sr_reg_gate__1_n_0\ : STD_LOGIC;
signal tristate_sr_reg_gate_n_0 : STD_LOGIC;
signal \tristate_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[9]\ : STD_LOGIC;
signal tristate_sr_reg_r_0_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_1_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_2_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_3_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_4_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_5_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_6_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_n_0 : STD_LOGIC;
signal NLW_reg_value_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_reg_value_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_reg_value_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \address[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \address[3]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \address[5]_i_4\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \address[5]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \data_sr[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \data_sr[11]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[2]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \initial_pause[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \initial_pause[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \initial_pause[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \initial_pause[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \initial_pause[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \initial_pause[7]_i_2\ : label is "soft_lutpair5";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of reg_value_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of reg_value_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of reg_value_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of reg_value_reg : label is 1024;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of reg_value_reg : label is "reg_value";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of reg_value_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of reg_value_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of reg_value_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of reg_value_reg : label is 15;
attribute srl_bus_name : string;
attribute srl_bus_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name : string;
attribute srl_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 ";
attribute srl_bus_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5 ";
attribute srl_bus_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 ";
attribute SOFT_HLUTNM of \tristate_sr_reg_gate__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \tristate_sr_reg_gate__1\ : label is "soft_lutpair16";
begin
\address[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => p_0_in,
I1 => \address[5]_i_5_n_0\,
I2 => \address[5]_i_3_n_0\,
I3 => address(0),
O => \address[0]_i_1_n_0\
);
\address[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00080800"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(0),
I4 => address(1),
O => \address[1]_i_1_n_0\
);
\address[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008080808000000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(1),
I4 => address(0),
I5 => address(2),
O => \address[2]_i_1_n_0\
);
\address[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000008"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => \address[3]_i_2_n_0\,
I4 => address(3),
O => \address[3]_i_1_n_0\
);
\address[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => address(1),
I1 => address(0),
I2 => address(2),
O => \address[3]_i_2_n_0\
);
\address[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000008"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => \address[5]_i_6_n_0\,
I4 => address(4),
O => \address[4]_i_1_n_0\
);
\address[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => finished_reg_n_0,
I2 => p_1_in,
I3 => \address[5]_i_4_n_0\,
I4 => divider(7),
I5 => p_0_in,
O => \address[5]_i_1_n_0\
);
\address[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808000800000800"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(4),
I4 => \address[5]_i_6_n_0\,
I5 => address(5),
O => \address[5]_i_2_n_0\
);
\address[5]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF7FFF"
)
port map (
I0 => \p_0_in__0\(2),
I1 => \p_0_in__0\(3),
I2 => \p_0_in__0\(0),
I3 => \p_0_in__0\(1),
I4 => \address[5]_i_7_n_0\,
O => \address[5]_i_3_n_0\
);
\address[5]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => divider(6),
O => \address[5]_i_4_n_0\
);
\address[5]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00400000"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => divider(6),
I3 => \divider[7]_i_3_n_0\,
I4 => divider(7),
O => \address[5]_i_5_n_0\
);
\address[5]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => address(2),
I1 => address(0),
I2 => address(1),
I3 => address(3),
O => \address[5]_i_6_n_0\
);
\address[5]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \p_0_in__0\(5),
I1 => \p_0_in__0\(4),
I2 => \p_0_in__0\(7),
I3 => \p_0_in__0\(6),
O => \address[5]_i_7_n_0\
);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[0]_i_1_n_0\,
Q => address(0),
R => '0'
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[1]_i_1_n_0\,
Q => address(1),
R => '0'
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[2]_i_1_n_0\,
Q => address(2),
R => '0'
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[3]_i_1_n_0\,
Q => address(3),
R => '0'
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[4]_i_1_n_0\,
Q => address(4),
R => '0'
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[5]_i_2_n_0\,
Q => address(5),
R => '0'
);
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FF200000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => finished_reg_n_0,
I2 => p_1_in,
I3 => p_0_in,
I4 => divider(7),
I5 => \address[5]_i_4_n_0\,
O => busy_sr
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[9]\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[10]\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[11]\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[12]\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[13]\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[14]\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[15]\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[16]\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[17]\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[18]\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[0]\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[19]\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[20]\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[21]\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[22]\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[23]\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[24]\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[25]\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[26]\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => \address[5]_i_4_n_0\,
I1 => divider(7),
I2 => p_0_in,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => \address[5]_i_3_n_0\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[28]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[27]\,
O => \busy_sr[28]_i_2_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[1]\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[2]\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[3]\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[4]\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[5]\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[6]\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[7]\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[8]\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \address[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[19]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[19]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[20]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[20]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[28]_i_2_n_0\,
Q => p_0_in,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[28]_i_1_n_0\
);
\clk_first_quarter[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => clk_last_quarter(28),
O => \clk_first_quarter[28]_i_1_n_0\
);
\clk_first_quarter_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \clk_first_quarter[28]_i_1_n_0\,
Q => clk_first_quarter(28),
S => \busy_sr[28]_i_1_n_0\
);
\clk_last_quarter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => p_1_in,
I1 => finished_reg_n_0,
I2 => \address[5]_i_3_n_0\,
I3 => p_0_in,
I4 => divider(7),
I5 => \address[5]_i_4_n_0\,
O => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(9),
Q => clk_last_quarter(10),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(10),
Q => clk_last_quarter(11),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(11),
Q => clk_last_quarter(12),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(12),
Q => clk_last_quarter(13),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(13),
Q => clk_last_quarter(14),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(14),
Q => clk_last_quarter(15),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(15),
Q => clk_last_quarter(16),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(16),
Q => clk_last_quarter(17),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(17),
Q => clk_last_quarter(18),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(18),
Q => clk_last_quarter(19),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \tristate_sr[19]_i_1_n_0\,
Q => clk_last_quarter(1),
R => '0'
);
\clk_last_quarter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(19),
Q => clk_last_quarter(20),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(20),
Q => clk_last_quarter(21),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(21),
Q => clk_last_quarter(22),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(22),
Q => clk_last_quarter(23),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(23),
Q => clk_last_quarter(24),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(24),
Q => clk_last_quarter(25),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(25),
Q => clk_last_quarter(26),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(26),
Q => clk_last_quarter(27),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(27),
Q => clk_last_quarter(28),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(1),
Q => clk_last_quarter(2),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(2),
Q => clk_last_quarter(3),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(3),
Q => clk_last_quarter(4),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(4),
Q => clk_last_quarter(5),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(5),
Q => clk_last_quarter(6),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(6),
Q => clk_last_quarter(7),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(7),
Q => clk_last_quarter(8),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(8),
Q => clk_last_quarter(9),
R => \clk_last_quarter[2]_i_1_n_0\
);
\data_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAEACAEAEAEAEAEA"
)
port map (
I0 => \data_sr_reg_n_0_[0]\,
I1 => p_0_in,
I2 => \data_sr[0]_i_2_n_0\,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => \address[5]_i_3_n_0\,
O => \data_sr[0]_i_1_n_0\
);
\data_sr[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => divider(7),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(6),
O => \data_sr[0]_i_2_n_0\
);
\data_sr[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[10]\,
I1 => p_0_in,
I2 => \p_0_in__0\(0),
O => p_2_in(11)
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => p_0_in,
I2 => \p_0_in__0\(1),
O => p_2_in(12)
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => p_0_in,
I2 => \p_0_in__0\(2),
O => p_2_in(13)
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => p_0_in,
I2 => \p_0_in__0\(3),
O => p_2_in(14)
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => p_0_in,
I2 => \p_0_in__0\(4),
O => p_2_in(15)
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => p_0_in,
I2 => \p_0_in__0\(5),
O => p_2_in(16)
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => p_0_in,
I2 => \p_0_in__0\(6),
O => p_2_in(17)
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => p_0_in,
I2 => \p_0_in__0\(7),
O => p_2_in(18)
);
\data_sr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[1]\,
I1 => p_0_in,
I2 => reg_value_reg_n_15,
O => p_2_in(2)
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => p_0_in,
I2 => reg_value_reg_n_14,
O => p_2_in(3)
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => p_0_in,
I2 => reg_value_reg_n_13,
O => p_2_in(4)
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => p_0_in,
I2 => reg_value_reg_n_12,
O => p_2_in(5)
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => p_0_in,
I2 => reg_value_reg_n_11,
O => p_2_in(6)
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => p_0_in,
I2 => reg_value_reg_n_10,
O => p_2_in(7)
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => p_0_in,
I2 => reg_value_reg_n_9,
O => p_2_in(8)
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => p_0_in,
I2 => reg_value_reg_n_8,
O => p_2_in(9)
);
\data_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => '1',
D => \data_sr[0]_i_1_n_0\,
Q => \data_sr_reg_n_0_[0]\,
R => '0'
);
\data_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[9]\,
Q => \data_sr_reg_n_0_[10]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(11),
Q => \data_sr_reg_n_0_[11]\,
R => '0'
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(12),
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(13),
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(14),
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(15),
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(16),
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(17),
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(18),
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[18]\,
Q => \data_sr_reg_n_0_[19]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[0]\,
Q => \data_sr_reg_n_0_[1]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[21]\,
Q => \data_sr_reg_n_0_[22]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[26]\,
Q => \data_sr_reg_n_0_[27]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(2),
Q => \data_sr_reg_n_0_[2]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(3),
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(4),
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(5),
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(6),
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(7),
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(8),
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(9),
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
I2 => finished_reg_n_0,
I3 => divider(0),
O => \divider[0]_i_1_n_0\
);
\divider[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00F4F400"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
I3 => divider(0),
I4 => divider(1),
O => \divider[1]_i_1_n_0\
);
\divider[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F4F4F4F4000000"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
I3 => divider(1),
I4 => divider(0),
I5 => divider(2),
O => \divider[2]_i_1_n_0\
);
\divider[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAA8000"
)
port map (
I0 => \divider[7]_i_1_n_0\,
I1 => divider(2),
I2 => divider(0),
I3 => divider(1),
I4 => divider(3),
O => \divider[3]_i_1_n_0\
);
\divider[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => divider(2),
I1 => divider(0),
I2 => divider(1),
I3 => divider(3),
I4 => \divider[7]_i_1_n_0\,
I5 => divider(4),
O => \divider[4]_i_1_n_0\
);
\divider[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A84454"
)
port map (
I0 => \divider[5]_i_2_n_0\,
I1 => p_0_in,
I2 => p_1_in,
I3 => finished_reg_n_0,
I4 => divider(5),
O => \divider[5]_i_1_n_0\
);
\divider[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => divider(3),
I1 => divider(1),
I2 => divider(0),
I3 => divider(2),
I4 => divider(4),
O => \divider[5]_i_2_n_0\
);
\divider[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A84454"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => p_0_in,
I2 => p_1_in,
I3 => finished_reg_n_0,
I4 => divider(6),
O => \divider[6]_i_1_n_0\
);
\divider[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
O => \divider[7]_i_1_n_0\
);
\divider[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0B0BBB040404440"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => divider(6),
I2 => p_0_in,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => divider(7),
O => \divider[7]_i_2_n_0\
);
\divider[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => divider(4),
I1 => divider(2),
I2 => divider(0),
I3 => divider(1),
I4 => divider(3),
I5 => divider(5),
O => \divider[7]_i_3_n_0\
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[0]_i_1_n_0\,
Q => divider(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[1]_i_1_n_0\,
Q => divider(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[2]_i_1_n_0\,
Q => divider(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[3]_i_1_n_0\,
Q => divider(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[4]_i_1_n_0\,
Q => divider(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[5]_i_1_n_0\,
Q => divider(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[6]_i_1_n_0\,
Q => divider(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[7]_i_2_n_0\,
Q => divider(7),
R => '0'
);
finished_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000020"
)
port map (
I0 => p_1_in,
I1 => \address[5]_i_4_n_0\,
I2 => divider(7),
I3 => \address[5]_i_3_n_0\,
I4 => p_0_in,
I5 => finished_reg_n_0,
O => finished_i_1_n_0
);
finished_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => '1',
D => finished_i_1_n_0,
Q => finished_reg_n_0,
R => '0'
);
hdmi_scl_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => clk_first_quarter(28),
I1 => divider(7),
O => hdmi_scl
);
hdmi_sda_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[28]\,
I1 => \tristate_sr_reg[28]_inv_n_0\,
O => hdmi_sda
);
\initial_pause[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => p_1_in,
I1 => p_0_in,
I2 => \initial_pause_reg_n_0_[0]\,
O => \p_1_in__0\(0)
);
\initial_pause[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0110"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[1]\,
O => \p_1_in__0\(1)
);
\initial_pause[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00070008"
)
port map (
I0 => \initial_pause_reg_n_0_[0]\,
I1 => \initial_pause_reg_n_0_[1]\,
I2 => p_1_in,
I3 => p_0_in,
I4 => \initial_pause_reg_n_0_[2]\,
O => \p_1_in__0\(2)
);
\initial_pause[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000007F00000080"
)
port map (
I0 => \initial_pause_reg_n_0_[1]\,
I1 => \initial_pause_reg_n_0_[0]\,
I2 => \initial_pause_reg_n_0_[2]\,
I3 => p_1_in,
I4 => p_0_in,
I5 => \initial_pause_reg_n_0_[3]\,
O => \p_1_in__0\(3)
);
\initial_pause[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => \initial_pause_reg_n_0_[2]\,
I1 => \initial_pause_reg_n_0_[0]\,
I2 => \initial_pause_reg_n_0_[1]\,
I3 => \initial_pause_reg_n_0_[3]\,
I4 => \initial_pause[7]_i_1_n_0\,
I5 => \initial_pause_reg_n_0_[4]\,
O => \p_1_in__0\(4)
);
\initial_pause[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0201"
)
port map (
I0 => \initial_pause[5]_i_2_n_0\,
I1 => p_1_in,
I2 => p_0_in,
I3 => \initial_pause_reg_n_0_[5]\,
O => \p_1_in__0\(5)
);
\initial_pause[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \initial_pause_reg_n_0_[3]\,
I1 => \initial_pause_reg_n_0_[1]\,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[2]\,
I4 => \initial_pause_reg_n_0_[4]\,
O => \initial_pause[5]_i_2_n_0\
);
\initial_pause[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0201"
)
port map (
I0 => \initial_pause[7]_i_3_n_0\,
I1 => p_1_in,
I2 => p_0_in,
I3 => \initial_pause_reg_n_0_[6]\,
O => \p_1_in__0\(6)
);
\initial_pause[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
O => \initial_pause[7]_i_1_n_0\
);
\initial_pause[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \initial_pause_reg_n_0_[6]\,
I1 => p_0_in,
I2 => p_1_in,
I3 => \initial_pause[7]_i_3_n_0\,
O => \p_1_in__0\(7)
);
\initial_pause[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \initial_pause_reg_n_0_[4]\,
I1 => \initial_pause_reg_n_0_[2]\,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[1]\,
I4 => \initial_pause_reg_n_0_[3]\,
I5 => \initial_pause_reg_n_0_[5]\,
O => \initial_pause[7]_i_3_n_0\
);
\initial_pause_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(0),
Q => \initial_pause_reg_n_0_[0]\,
R => '0'
);
\initial_pause_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(1),
Q => \initial_pause_reg_n_0_[1]\,
R => '0'
);
\initial_pause_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(2),
Q => \initial_pause_reg_n_0_[2]\,
R => '0'
);
\initial_pause_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(3),
Q => \initial_pause_reg_n_0_[3]\,
R => '0'
);
\initial_pause_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(4),
Q => \initial_pause_reg_n_0_[4]\,
R => '0'
);
\initial_pause_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(5),
Q => \initial_pause_reg_n_0_[5]\,
R => '0'
);
\initial_pause_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(6),
Q => \initial_pause_reg_n_0_[6]\,
R => '0'
);
\initial_pause_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(7),
Q => p_1_in,
R => '0'
);
reg_value_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"AF04D03C1700163748101506F9005512E0D0A3A4A2A49D619C309AE098034110",
INIT_01 => X"2524241F23AD220421DC201D1F1B1E1C1D001C001BAD1A04193418E740004C04",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFF2F772E1B2D7C2C082BAD2A042900280027352601",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 10) => B"0000",
ADDRARDADDR(9 downto 4) => address(5 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk_100,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 8) => \p_0_in__0\(7 downto 0),
DOADO(7) => reg_value_reg_n_8,
DOADO(6) => reg_value_reg_n_9,
DOADO(5) => reg_value_reg_n_10,
DOADO(4) => reg_value_reg_n_11,
DOADO(3) => reg_value_reg_n_12,
DOADO(2) => reg_value_reg_n_13,
DOADO(1) => reg_value_reg_n_14,
DOADO(0) => reg_value_reg_n_15,
DOBDO(15 downto 0) => NLW_reg_value_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_reg_value_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_reg_value_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
\tristate_sr[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
O => \tristate_sr[19]_i_1_n_0\
);
\tristate_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_n_0_[9]\,
Q => \tristate_sr_reg_n_0_[10]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[10]\,
Q => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\
);
\tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\,
Q => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
R => '0'
);
\tristate_sr_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_gate__0_n_0\,
Q => \tristate_sr_reg_n_0_[18]\,
R => \address[5]_i_1_n_0\
);
\tristate_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_n_0_[18]\,
Q => \tristate_sr_reg_n_0_[19]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => '0',
Q => \tristate_sr_reg_n_0_[1]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[19]\,
Q => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\
);
\tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
Q => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\,
R => '0'
);
\tristate_sr_reg[28]_inv\: unisim.vcomponents.FDSE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_gate_n_0,
Q => \tristate_sr_reg[28]_inv_n_0\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[1]\,
Q => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\
);
\tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\,
Q => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
R => '0'
);
\tristate_sr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_gate__1_n_0\,
Q => \tristate_sr_reg_n_0_[9]\,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_gate: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\,
I1 => tristate_sr_reg_r_6_n_0,
O => tristate_sr_reg_gate_n_0
);
\tristate_sr_reg_gate__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
I1 => tristate_sr_reg_r_5_n_0,
O => \tristate_sr_reg_gate__0_n_0\
);
\tristate_sr_reg_gate__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
I1 => tristate_sr_reg_r_5_n_0,
O => \tristate_sr_reg_gate__1_n_0\
);
tristate_sr_reg_r: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => '1',
Q => tristate_sr_reg_r_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_0: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_n_0,
Q => tristate_sr_reg_r_0_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_1: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_0_n_0,
Q => tristate_sr_reg_r_1_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_2: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_1_n_0,
Q => tristate_sr_reg_r_2_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_3: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_2_n_0,
Q => tristate_sr_reg_r_3_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_4: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_3_n_0,
Q => tristate_sr_reg_r_4_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_5: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_4_n_0,
Q => tristate_sr_reg_r_5_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_6: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_5_n_0,
Q => tristate_sr_reg_r_6_n_0,
R => \address[5]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0_zed_hdmi is
port (
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_de : out STD_LOGIC;
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[31]_0\ : out STD_LOGIC;
\cr_int_reg[31]_1\ : out STD_LOGIC;
O : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cb_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[27]_0\ : out STD_LOGIC;
\cr_int_reg[27]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[31]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cr_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cr_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cr_int_reg[27]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[7]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\y_int_reg[23]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cb_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[3]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[27]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[19]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[23]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
hdmi_sda : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_scl : out STD_LOGIC;
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
clk_100 : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
\rgb888[8]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[13]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[13]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[12]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[12]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_11\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_12\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_13\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_14\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_15\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_16\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_18\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_19\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[14]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_20\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_21\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[0]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[14]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[1]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\rgb888[14]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_22\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_24\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_25\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_26\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_27\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_28\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_29\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_30\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_31\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[0]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_32\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_9\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zed_hdmi_0_0_zed_hdmi : entity is "zed_hdmi";
end system_zed_hdmi_0_0_zed_hdmi;
architecture STRUCTURE of system_zed_hdmi_0_0_zed_hdmi is
signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal D1 : STD_LOGIC;
signal \^di\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^o\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal cb : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cb[0]_i_1_n_0\ : STD_LOGIC;
signal \cb[1]_i_1_n_0\ : STD_LOGIC;
signal \cb[2]_i_1_n_0\ : STD_LOGIC;
signal \cb[3]_i_1_n_0\ : STD_LOGIC;
signal \cb[4]_i_1_n_0\ : STD_LOGIC;
signal \cb[5]_i_1_n_0\ : STD_LOGIC;
signal \cb[6]_i_1_n_0\ : STD_LOGIC;
signal \cb[7]_i_10_n_0\ : STD_LOGIC;
signal \cb[7]_i_11_n_0\ : STD_LOGIC;
signal \cb[7]_i_13_n_0\ : STD_LOGIC;
signal \cb[7]_i_14_n_0\ : STD_LOGIC;
signal \cb[7]_i_15_n_0\ : STD_LOGIC;
signal \cb[7]_i_16_n_0\ : STD_LOGIC;
signal \cb[7]_i_17_n_0\ : STD_LOGIC;
signal \cb[7]_i_18_n_0\ : STD_LOGIC;
signal \cb[7]_i_19_n_0\ : STD_LOGIC;
signal \cb[7]_i_20_n_0\ : STD_LOGIC;
signal \cb[7]_i_21_n_0\ : STD_LOGIC;
signal \cb[7]_i_22_n_0\ : STD_LOGIC;
signal \cb[7]_i_23_n_0\ : STD_LOGIC;
signal \cb[7]_i_24_n_0\ : STD_LOGIC;
signal \cb[7]_i_25_n_0\ : STD_LOGIC;
signal \cb[7]_i_26_n_0\ : STD_LOGIC;
signal \cb[7]_i_27_n_0\ : STD_LOGIC;
signal \cb[7]_i_28_n_0\ : STD_LOGIC;
signal \cb[7]_i_2_n_0\ : STD_LOGIC;
signal \cb[7]_i_4_n_0\ : STD_LOGIC;
signal \cb[7]_i_5_n_0\ : STD_LOGIC;
signal \cb[7]_i_6_n_0\ : STD_LOGIC;
signal \cb[7]_i_7_n_0\ : STD_LOGIC;
signal \cb[7]_i_8_n_0\ : STD_LOGIC;
signal \cb[7]_i_9_n_0\ : STD_LOGIC;
signal cb_hold : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cb_hold[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_102_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_103_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_104_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_105_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_106_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_107_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_108_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_109_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_110_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_111_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_112_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_113_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_114_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_51_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_61_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_85_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_86_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_87_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_94_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_26_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_75_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_102_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_103_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_104_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_105_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_106_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_24_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_51_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_66_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_90_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_75_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_9_n_0\ : STD_LOGIC;
signal cb_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg5 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg7 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal cb_int_reg8 : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_18_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_18_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_4\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_5\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_6\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_7\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_1\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_2\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_34_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \^cb_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cb_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \cb_int_reg_n_0_[0]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[1]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[2]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[3]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[4]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[5]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[6]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[7]\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_3\ : STD_LOGIC;
signal cb_regn_0_0 : STD_LOGIC;
signal cr : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cr[0]_i_1_n_0\ : STD_LOGIC;
signal \cr[1]_i_1_n_0\ : STD_LOGIC;
signal \cr[2]_i_1_n_0\ : STD_LOGIC;
signal \cr[3]_i_1_n_0\ : STD_LOGIC;
signal \cr[4]_i_1_n_0\ : STD_LOGIC;
signal \cr[5]_i_1_n_0\ : STD_LOGIC;
signal \cr[6]_i_1_n_0\ : STD_LOGIC;
signal \cr[7]_i_10_n_0\ : STD_LOGIC;
signal \cr[7]_i_11_n_0\ : STD_LOGIC;
signal \cr[7]_i_13_n_0\ : STD_LOGIC;
signal \cr[7]_i_14_n_0\ : STD_LOGIC;
signal \cr[7]_i_15_n_0\ : STD_LOGIC;
signal \cr[7]_i_16_n_0\ : STD_LOGIC;
signal \cr[7]_i_17_n_0\ : STD_LOGIC;
signal \cr[7]_i_18_n_0\ : STD_LOGIC;
signal \cr[7]_i_19_n_0\ : STD_LOGIC;
signal \cr[7]_i_20_n_0\ : STD_LOGIC;
signal \cr[7]_i_21_n_0\ : STD_LOGIC;
signal \cr[7]_i_22_n_0\ : STD_LOGIC;
signal \cr[7]_i_23_n_0\ : STD_LOGIC;
signal \cr[7]_i_24_n_0\ : STD_LOGIC;
signal \cr[7]_i_25_n_0\ : STD_LOGIC;
signal \cr[7]_i_26_n_0\ : STD_LOGIC;
signal \cr[7]_i_27_n_0\ : STD_LOGIC;
signal \cr[7]_i_28_n_0\ : STD_LOGIC;
signal \cr[7]_i_2_n_0\ : STD_LOGIC;
signal \cr[7]_i_4_n_0\ : STD_LOGIC;
signal \cr[7]_i_5_n_0\ : STD_LOGIC;
signal \cr[7]_i_6_n_0\ : STD_LOGIC;
signal \cr[7]_i_7_n_0\ : STD_LOGIC;
signal \cr[7]_i_8_n_0\ : STD_LOGIC;
signal \cr[7]_i_9_n_0\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[0]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[1]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[2]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[3]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[4]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[5]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[6]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[7]\ : STD_LOGIC;
signal \cr_int[11]_i_100_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_101_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_102_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_104_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_105_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_106_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_107_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_109_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_110_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_111_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_112_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_113_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_114_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_115_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_117_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_118_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_119_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_120_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_121_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_122_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_123_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_124_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_126_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_127_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_128_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_129_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_130_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_131_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_132_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_133_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_134_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_135_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_136_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_137_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_138_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_139_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_140_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_141_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_142_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_143_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_144_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_145_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_146_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_147_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_148_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_149_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_150_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_151_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_152_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_153_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_154_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_155_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_156_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_54_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_59_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_65_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_70_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_86_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_91_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_97_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_98_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_99_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_21_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_100_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_103_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_108_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_109_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_110_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_111_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_112_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_113_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_114_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_115_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_116_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_117_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_118_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_119_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_120_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_121_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_122_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_123_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_124_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_125_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_126_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_20_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_56_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_59_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_79_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_92_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_97_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_56_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_63_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_69_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_79_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_86_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_91_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_92_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_20_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_21_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_9_n_0\ : STD_LOGIC;
signal cr_int_reg3 : STD_LOGIC_VECTOR ( 7 to 7 );
signal \cr_int_reg3__0\ : STD_LOGIC_VECTOR ( 8 downto 1 );
signal cr_int_reg4 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cr_int_reg6 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal cr_int_reg7 : STD_LOGIC;
signal \^cr_int_reg[11]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[11]_i_103_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_3\ : STD_LOGIC;
signal \^cr_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_7\ : STD_LOGIC;
signal \^cr_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_3\ : STD_LOGIC;
signal \^cr_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^cr_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \cr_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_3\ : STD_LOGIC;
signal \^cr_int_reg[27]_0\ : STD_LOGIC;
signal \^cr_int_reg[27]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^cr_int_reg[27]_2\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \cr_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[27]_i_9_n_3\ : STD_LOGIC;
signal \^cr_int_reg[31]_0\ : STD_LOGIC;
signal \^cr_int_reg[31]_1\ : STD_LOGIC;
signal \^cr_int_reg[31]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cr_int_reg[31]_i_101_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_48_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_48_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_63_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_63_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \^cr_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^cr_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^cr_int_reg[3]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cr_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_7\ : STD_LOGIC;
signal \^cr_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^cr_int_reg[7]_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \cr_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \cr_int_reg_n_0_[0]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[1]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[2]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[3]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[4]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[5]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[6]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[7]\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_3\ : STD_LOGIC;
signal edge : STD_LOGIC;
signal edge_i_1_n_0 : STD_LOGIC;
signal edge_rb : STD_LOGIC;
signal edge_rb_i_1_n_0 : STD_LOGIC;
signal \hdmi_d[10]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[11]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[12]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[13]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[14]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[15]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[15]_i_2_n_0\ : STD_LOGIC;
signal \hdmi_d[8]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[9]_i_1_n_0\ : STD_LOGIC;
signal hdmi_vsync_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal y : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \y[0]_i_1_n_0\ : STD_LOGIC;
signal \y[1]_i_1_n_0\ : STD_LOGIC;
signal \y[2]_i_1_n_0\ : STD_LOGIC;
signal \y[3]_i_1_n_0\ : STD_LOGIC;
signal \y[4]_i_1_n_0\ : STD_LOGIC;
signal \y[5]_i_1_n_0\ : STD_LOGIC;
signal \y[6]_i_1_n_0\ : STD_LOGIC;
signal \y[7]_i_10_n_0\ : STD_LOGIC;
signal \y[7]_i_11_n_0\ : STD_LOGIC;
signal \y[7]_i_13_n_0\ : STD_LOGIC;
signal \y[7]_i_14_n_0\ : STD_LOGIC;
signal \y[7]_i_15_n_0\ : STD_LOGIC;
signal \y[7]_i_16_n_0\ : STD_LOGIC;
signal \y[7]_i_17_n_0\ : STD_LOGIC;
signal \y[7]_i_18_n_0\ : STD_LOGIC;
signal \y[7]_i_19_n_0\ : STD_LOGIC;
signal \y[7]_i_20_n_0\ : STD_LOGIC;
signal \y[7]_i_21_n_0\ : STD_LOGIC;
signal \y[7]_i_22_n_0\ : STD_LOGIC;
signal \y[7]_i_23_n_0\ : STD_LOGIC;
signal \y[7]_i_24_n_0\ : STD_LOGIC;
signal \y[7]_i_25_n_0\ : STD_LOGIC;
signal \y[7]_i_26_n_0\ : STD_LOGIC;
signal \y[7]_i_27_n_0\ : STD_LOGIC;
signal \y[7]_i_28_n_0\ : STD_LOGIC;
signal \y[7]_i_2_n_0\ : STD_LOGIC;
signal \y[7]_i_4_n_0\ : STD_LOGIC;
signal \y[7]_i_5_n_0\ : STD_LOGIC;
signal \y[7]_i_6_n_0\ : STD_LOGIC;
signal \y[7]_i_7_n_0\ : STD_LOGIC;
signal \y[7]_i_8_n_0\ : STD_LOGIC;
signal \y[7]_i_9_n_0\ : STD_LOGIC;
signal y_hold : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \y_int[11]_i_100_n_0\ : STD_LOGIC;
signal \y_int[11]_i_10_n_0\ : STD_LOGIC;
signal \y_int[11]_i_12_n_0\ : STD_LOGIC;
signal \y_int[11]_i_16_n_0\ : STD_LOGIC;
signal \y_int[11]_i_19_n_0\ : STD_LOGIC;
signal \y_int[11]_i_29_n_0\ : STD_LOGIC;
signal \y_int[11]_i_2_n_0\ : STD_LOGIC;
signal \y_int[11]_i_30_n_0\ : STD_LOGIC;
signal \y_int[11]_i_31_n_0\ : STD_LOGIC;
signal \y_int[11]_i_32_n_0\ : STD_LOGIC;
signal \y_int[11]_i_34_n_0\ : STD_LOGIC;
signal \y_int[11]_i_35_n_0\ : STD_LOGIC;
signal \y_int[11]_i_36_n_0\ : STD_LOGIC;
signal \y_int[11]_i_37_n_0\ : STD_LOGIC;
signal \y_int[11]_i_3_n_0\ : STD_LOGIC;
signal \y_int[11]_i_40_n_0\ : STD_LOGIC;
signal \y_int[11]_i_41_n_0\ : STD_LOGIC;
signal \y_int[11]_i_42_n_0\ : STD_LOGIC;
signal \y_int[11]_i_43_n_0\ : STD_LOGIC;
signal \y_int[11]_i_45_n_0\ : STD_LOGIC;
signal \y_int[11]_i_46_n_0\ : STD_LOGIC;
signal \y_int[11]_i_47_n_0\ : STD_LOGIC;
signal \y_int[11]_i_48_n_0\ : STD_LOGIC;
signal \y_int[11]_i_4_n_0\ : STD_LOGIC;
signal \y_int[11]_i_50_n_0\ : STD_LOGIC;
signal \y_int[11]_i_51_n_0\ : STD_LOGIC;
signal \y_int[11]_i_52_n_0\ : STD_LOGIC;
signal \y_int[11]_i_53_n_0\ : STD_LOGIC;
signal \y_int[11]_i_58_n_0\ : STD_LOGIC;
signal \y_int[11]_i_59_n_0\ : STD_LOGIC;
signal \y_int[11]_i_5_n_0\ : STD_LOGIC;
signal \y_int[11]_i_60_n_0\ : STD_LOGIC;
signal \y_int[11]_i_61_n_0\ : STD_LOGIC;
signal \y_int[11]_i_62_n_0\ : STD_LOGIC;
signal \y_int[11]_i_63_n_0\ : STD_LOGIC;
signal \y_int[11]_i_64_n_0\ : STD_LOGIC;
signal \y_int[11]_i_65_n_0\ : STD_LOGIC;
signal \y_int[11]_i_66_n_0\ : STD_LOGIC;
signal \y_int[11]_i_67_n_0\ : STD_LOGIC;
signal \y_int[11]_i_68_n_0\ : STD_LOGIC;
signal \y_int[11]_i_69_n_0\ : STD_LOGIC;
signal \y_int[11]_i_6_n_0\ : STD_LOGIC;
signal \y_int[11]_i_70_n_0\ : STD_LOGIC;
signal \y_int[11]_i_71_n_0\ : STD_LOGIC;
signal \y_int[11]_i_72_n_0\ : STD_LOGIC;
signal \y_int[11]_i_73_n_0\ : STD_LOGIC;
signal \y_int[11]_i_74_n_0\ : STD_LOGIC;
signal \y_int[11]_i_75_n_0\ : STD_LOGIC;
signal \y_int[11]_i_76_n_0\ : STD_LOGIC;
signal \y_int[11]_i_77_n_0\ : STD_LOGIC;
signal \y_int[11]_i_78_n_0\ : STD_LOGIC;
signal \y_int[11]_i_79_n_0\ : STD_LOGIC;
signal \y_int[11]_i_7_n_0\ : STD_LOGIC;
signal \y_int[11]_i_81_n_0\ : STD_LOGIC;
signal \y_int[11]_i_82_n_0\ : STD_LOGIC;
signal \y_int[11]_i_83_n_0\ : STD_LOGIC;
signal \y_int[11]_i_84_n_0\ : STD_LOGIC;
signal \y_int[11]_i_86_n_0\ : STD_LOGIC;
signal \y_int[11]_i_87_n_0\ : STD_LOGIC;
signal \y_int[11]_i_88_n_0\ : STD_LOGIC;
signal \y_int[11]_i_89_n_0\ : STD_LOGIC;
signal \y_int[11]_i_8_n_0\ : STD_LOGIC;
signal \y_int[11]_i_90_n_0\ : STD_LOGIC;
signal \y_int[11]_i_91_n_0\ : STD_LOGIC;
signal \y_int[11]_i_92_n_0\ : STD_LOGIC;
signal \y_int[11]_i_93_n_0\ : STD_LOGIC;
signal \y_int[11]_i_94_n_0\ : STD_LOGIC;
signal \y_int[11]_i_95_n_0\ : STD_LOGIC;
signal \y_int[11]_i_96_n_0\ : STD_LOGIC;
signal \y_int[11]_i_97_n_0\ : STD_LOGIC;
signal \y_int[11]_i_98_n_0\ : STD_LOGIC;
signal \y_int[11]_i_99_n_0\ : STD_LOGIC;
signal \y_int[11]_i_9_n_0\ : STD_LOGIC;
signal \y_int[15]_i_10_n_0\ : STD_LOGIC;
signal \y_int[15]_i_12_n_0\ : STD_LOGIC;
signal \y_int[15]_i_16_n_0\ : STD_LOGIC;
signal \y_int[15]_i_18_n_0\ : STD_LOGIC;
signal \y_int[15]_i_25_n_0\ : STD_LOGIC;
signal \y_int[15]_i_26_n_0\ : STD_LOGIC;
signal \y_int[15]_i_27_n_0\ : STD_LOGIC;
signal \y_int[15]_i_28_n_0\ : STD_LOGIC;
signal \y_int[15]_i_29_n_0\ : STD_LOGIC;
signal \y_int[15]_i_2_n_0\ : STD_LOGIC;
signal \y_int[15]_i_30_n_0\ : STD_LOGIC;
signal \y_int[15]_i_31_n_0\ : STD_LOGIC;
signal \y_int[15]_i_32_n_0\ : STD_LOGIC;
signal \y_int[15]_i_3_n_0\ : STD_LOGIC;
signal \y_int[15]_i_40_n_0\ : STD_LOGIC;
signal \y_int[15]_i_41_n_0\ : STD_LOGIC;
signal \y_int[15]_i_42_n_0\ : STD_LOGIC;
signal \y_int[15]_i_43_n_0\ : STD_LOGIC;
signal \y_int[15]_i_48_n_0\ : STD_LOGIC;
signal \y_int[15]_i_49_n_0\ : STD_LOGIC;
signal \y_int[15]_i_4_n_0\ : STD_LOGIC;
signal \y_int[15]_i_50_n_0\ : STD_LOGIC;
signal \y_int[15]_i_51_n_0\ : STD_LOGIC;
signal \y_int[15]_i_5_n_0\ : STD_LOGIC;
signal \y_int[15]_i_6_n_0\ : STD_LOGIC;
signal \y_int[15]_i_7_n_0\ : STD_LOGIC;
signal \y_int[15]_i_8_n_0\ : STD_LOGIC;
signal \y_int[15]_i_9_n_0\ : STD_LOGIC;
signal \y_int[19]_i_10_n_0\ : STD_LOGIC;
signal \y_int[19]_i_12_n_0\ : STD_LOGIC;
signal \y_int[19]_i_16_n_0\ : STD_LOGIC;
signal \y_int[19]_i_18_n_0\ : STD_LOGIC;
signal \y_int[19]_i_25_n_0\ : STD_LOGIC;
signal \y_int[19]_i_26_n_0\ : STD_LOGIC;
signal \y_int[19]_i_27_n_0\ : STD_LOGIC;
signal \y_int[19]_i_28_n_0\ : STD_LOGIC;
signal \y_int[19]_i_29_n_0\ : STD_LOGIC;
signal \y_int[19]_i_2_n_0\ : STD_LOGIC;
signal \y_int[19]_i_30_n_0\ : STD_LOGIC;
signal \y_int[19]_i_31_n_0\ : STD_LOGIC;
signal \y_int[19]_i_32_n_0\ : STD_LOGIC;
signal \y_int[19]_i_3_n_0\ : STD_LOGIC;
signal \y_int[19]_i_48_n_0\ : STD_LOGIC;
signal \y_int[19]_i_49_n_0\ : STD_LOGIC;
signal \y_int[19]_i_4_n_0\ : STD_LOGIC;
signal \y_int[19]_i_50_n_0\ : STD_LOGIC;
signal \y_int[19]_i_51_n_0\ : STD_LOGIC;
signal \y_int[19]_i_5_n_0\ : STD_LOGIC;
signal \y_int[19]_i_6_n_0\ : STD_LOGIC;
signal \y_int[19]_i_7_n_0\ : STD_LOGIC;
signal \y_int[19]_i_8_n_0\ : STD_LOGIC;
signal \y_int[19]_i_9_n_0\ : STD_LOGIC;
signal \y_int[23]_i_100_n_0\ : STD_LOGIC;
signal \y_int[23]_i_101_n_0\ : STD_LOGIC;
signal \y_int[23]_i_102_n_0\ : STD_LOGIC;
signal \y_int[23]_i_103_n_0\ : STD_LOGIC;
signal \y_int[23]_i_104_n_0\ : STD_LOGIC;
signal \y_int[23]_i_12_n_0\ : STD_LOGIC;
signal \y_int[23]_i_14_n_0\ : STD_LOGIC;
signal \y_int[23]_i_18_n_0\ : STD_LOGIC;
signal \y_int[23]_i_20_n_0\ : STD_LOGIC;
signal \y_int[23]_i_26_n_0\ : STD_LOGIC;
signal \y_int[23]_i_27_n_0\ : STD_LOGIC;
signal \y_int[23]_i_28_n_0\ : STD_LOGIC;
signal \y_int[23]_i_29_n_0\ : STD_LOGIC;
signal \y_int[23]_i_2_n_0\ : STD_LOGIC;
signal \y_int[23]_i_30_n_0\ : STD_LOGIC;
signal \y_int[23]_i_31_n_0\ : STD_LOGIC;
signal \y_int[23]_i_36_n_0\ : STD_LOGIC;
signal \y_int[23]_i_37_n_0\ : STD_LOGIC;
signal \y_int[23]_i_38_n_0\ : STD_LOGIC;
signal \y_int[23]_i_39_n_0\ : STD_LOGIC;
signal \y_int[23]_i_3_n_0\ : STD_LOGIC;
signal \y_int[23]_i_40_n_0\ : STD_LOGIC;
signal \y_int[23]_i_41_n_0\ : STD_LOGIC;
signal \y_int[23]_i_42_n_0\ : STD_LOGIC;
signal \y_int[23]_i_43_n_0\ : STD_LOGIC;
signal \y_int[23]_i_46_n_0\ : STD_LOGIC;
signal \y_int[23]_i_47_n_0\ : STD_LOGIC;
signal \y_int[23]_i_48_n_0\ : STD_LOGIC;
signal \y_int[23]_i_49_n_0\ : STD_LOGIC;
signal \y_int[23]_i_4_n_0\ : STD_LOGIC;
signal \y_int[23]_i_52_n_0\ : STD_LOGIC;
signal \y_int[23]_i_53_n_0\ : STD_LOGIC;
signal \y_int[23]_i_54_n_0\ : STD_LOGIC;
signal \y_int[23]_i_55_n_0\ : STD_LOGIC;
signal \y_int[23]_i_56_n_0\ : STD_LOGIC;
signal \y_int[23]_i_57_n_0\ : STD_LOGIC;
signal \y_int[23]_i_5_n_0\ : STD_LOGIC;
signal \y_int[23]_i_62_n_0\ : STD_LOGIC;
signal \y_int[23]_i_63_n_0\ : STD_LOGIC;
signal \y_int[23]_i_64_n_0\ : STD_LOGIC;
signal \y_int[23]_i_65_n_0\ : STD_LOGIC;
signal \y_int[23]_i_67_n_0\ : STD_LOGIC;
signal \y_int[23]_i_68_n_0\ : STD_LOGIC;
signal \y_int[23]_i_69_n_0\ : STD_LOGIC;
signal \y_int[23]_i_6_n_0\ : STD_LOGIC;
signal \y_int[23]_i_70_n_0\ : STD_LOGIC;
signal \y_int[23]_i_71_n_0\ : STD_LOGIC;
signal \y_int[23]_i_72_n_0\ : STD_LOGIC;
signal \y_int[23]_i_73_n_0\ : STD_LOGIC;
signal \y_int[23]_i_74_n_0\ : STD_LOGIC;
signal \y_int[23]_i_76_n_0\ : STD_LOGIC;
signal \y_int[23]_i_77_n_0\ : STD_LOGIC;
signal \y_int[23]_i_78_n_0\ : STD_LOGIC;
signal \y_int[23]_i_79_n_0\ : STD_LOGIC;
signal \y_int[23]_i_7_n_0\ : STD_LOGIC;
signal \y_int[23]_i_80_n_0\ : STD_LOGIC;
signal \y_int[23]_i_81_n_0\ : STD_LOGIC;
signal \y_int[23]_i_82_n_0\ : STD_LOGIC;
signal \y_int[23]_i_83_n_0\ : STD_LOGIC;
signal \y_int[23]_i_84_n_0\ : STD_LOGIC;
signal \y_int[23]_i_85_n_0\ : STD_LOGIC;
signal \y_int[23]_i_86_n_0\ : STD_LOGIC;
signal \y_int[23]_i_87_n_0\ : STD_LOGIC;
signal \y_int[23]_i_88_n_0\ : STD_LOGIC;
signal \y_int[23]_i_8_n_0\ : STD_LOGIC;
signal \y_int[23]_i_90_n_0\ : STD_LOGIC;
signal \y_int[23]_i_91_n_0\ : STD_LOGIC;
signal \y_int[23]_i_92_n_0\ : STD_LOGIC;
signal \y_int[23]_i_93_n_0\ : STD_LOGIC;
signal \y_int[23]_i_94_n_0\ : STD_LOGIC;
signal \y_int[23]_i_95_n_0\ : STD_LOGIC;
signal \y_int[23]_i_96_n_0\ : STD_LOGIC;
signal \y_int[23]_i_97_n_0\ : STD_LOGIC;
signal \y_int[23]_i_98_n_0\ : STD_LOGIC;
signal \y_int[23]_i_99_n_0\ : STD_LOGIC;
signal \y_int[23]_i_9_n_0\ : STD_LOGIC;
signal \y_int[27]_i_2_n_0\ : STD_LOGIC;
signal \y_int[27]_i_3_n_0\ : STD_LOGIC;
signal \y_int[27]_i_4_n_0\ : STD_LOGIC;
signal \y_int[27]_i_5_n_0\ : STD_LOGIC;
signal \y_int[31]_i_101_n_0\ : STD_LOGIC;
signal \y_int[31]_i_104_n_0\ : STD_LOGIC;
signal \y_int[31]_i_105_n_0\ : STD_LOGIC;
signal \y_int[31]_i_106_n_0\ : STD_LOGIC;
signal \y_int[31]_i_107_n_0\ : STD_LOGIC;
signal \y_int[31]_i_108_n_0\ : STD_LOGIC;
signal \y_int[31]_i_109_n_0\ : STD_LOGIC;
signal \y_int[31]_i_110_n_0\ : STD_LOGIC;
signal \y_int[31]_i_111_n_0\ : STD_LOGIC;
signal \y_int[31]_i_112_n_0\ : STD_LOGIC;
signal \y_int[31]_i_113_n_0\ : STD_LOGIC;
signal \y_int[31]_i_114_n_0\ : STD_LOGIC;
signal \y_int[31]_i_115_n_0\ : STD_LOGIC;
signal \y_int[31]_i_116_n_0\ : STD_LOGIC;
signal \y_int[31]_i_13_n_0\ : STD_LOGIC;
signal \y_int[31]_i_14_n_0\ : STD_LOGIC;
signal \y_int[31]_i_15_n_0\ : STD_LOGIC;
signal \y_int[31]_i_17_n_0\ : STD_LOGIC;
signal \y_int[31]_i_18_n_0\ : STD_LOGIC;
signal \y_int[31]_i_19_n_0\ : STD_LOGIC;
signal \y_int[31]_i_20_n_0\ : STD_LOGIC;
signal \y_int[31]_i_2_n_0\ : STD_LOGIC;
signal \y_int[31]_i_32_n_0\ : STD_LOGIC;
signal \y_int[31]_i_33_n_0\ : STD_LOGIC;
signal \y_int[31]_i_34_n_0\ : STD_LOGIC;
signal \y_int[31]_i_35_n_0\ : STD_LOGIC;
signal \y_int[31]_i_36_n_0\ : STD_LOGIC;
signal \y_int[31]_i_3_n_0\ : STD_LOGIC;
signal \y_int[31]_i_40_n_0\ : STD_LOGIC;
signal \y_int[31]_i_41_n_0\ : STD_LOGIC;
signal \y_int[31]_i_42_n_0\ : STD_LOGIC;
signal \y_int[31]_i_43_n_0\ : STD_LOGIC;
signal \y_int[31]_i_44_n_0\ : STD_LOGIC;
signal \y_int[31]_i_45_n_0\ : STD_LOGIC;
signal \y_int[31]_i_46_n_0\ : STD_LOGIC;
signal \y_int[31]_i_47_n_0\ : STD_LOGIC;
signal \y_int[31]_i_4_n_0\ : STD_LOGIC;
signal \y_int[31]_i_5_n_0\ : STD_LOGIC;
signal \y_int[31]_i_63_n_0\ : STD_LOGIC;
signal \y_int[31]_i_64_n_0\ : STD_LOGIC;
signal \y_int[31]_i_65_n_0\ : STD_LOGIC;
signal \y_int[31]_i_66_n_0\ : STD_LOGIC;
signal \y_int[31]_i_67_n_0\ : STD_LOGIC;
signal \y_int[31]_i_68_n_0\ : STD_LOGIC;
signal \y_int[31]_i_69_n_0\ : STD_LOGIC;
signal \y_int[31]_i_6_n_0\ : STD_LOGIC;
signal \y_int[31]_i_70_n_0\ : STD_LOGIC;
signal \y_int[31]_i_89_n_0\ : STD_LOGIC;
signal \y_int[31]_i_90_n_0\ : STD_LOGIC;
signal \y_int[31]_i_91_n_0\ : STD_LOGIC;
signal \y_int[31]_i_92_n_0\ : STD_LOGIC;
signal \y_int[3]_i_10_n_0\ : STD_LOGIC;
signal \y_int[3]_i_13_n_0\ : STD_LOGIC;
signal \y_int[3]_i_17_n_0\ : STD_LOGIC;
signal \y_int[3]_i_18_n_0\ : STD_LOGIC;
signal \y_int[3]_i_22_n_0\ : STD_LOGIC;
signal \y_int[3]_i_23_n_0\ : STD_LOGIC;
signal \y_int[3]_i_24_n_0\ : STD_LOGIC;
signal \y_int[3]_i_25_n_0\ : STD_LOGIC;
signal \y_int[3]_i_27_n_0\ : STD_LOGIC;
signal \y_int[3]_i_28_n_0\ : STD_LOGIC;
signal \y_int[3]_i_29_n_0\ : STD_LOGIC;
signal \y_int[3]_i_2_n_0\ : STD_LOGIC;
signal \y_int[3]_i_31_n_0\ : STD_LOGIC;
signal \y_int[3]_i_32_n_0\ : STD_LOGIC;
signal \y_int[3]_i_33_n_0\ : STD_LOGIC;
signal \y_int[3]_i_34_n_0\ : STD_LOGIC;
signal \y_int[3]_i_3_n_0\ : STD_LOGIC;
signal \y_int[3]_i_4_n_0\ : STD_LOGIC;
signal \y_int[3]_i_50_n_0\ : STD_LOGIC;
signal \y_int[3]_i_51_n_0\ : STD_LOGIC;
signal \y_int[3]_i_52_n_0\ : STD_LOGIC;
signal \y_int[3]_i_53_n_0\ : STD_LOGIC;
signal \y_int[3]_i_54_n_0\ : STD_LOGIC;
signal \y_int[3]_i_56_n_0\ : STD_LOGIC;
signal \y_int[3]_i_57_n_0\ : STD_LOGIC;
signal \y_int[3]_i_58_n_0\ : STD_LOGIC;
signal \y_int[3]_i_59_n_0\ : STD_LOGIC;
signal \y_int[3]_i_5_n_0\ : STD_LOGIC;
signal \y_int[3]_i_60_n_0\ : STD_LOGIC;
signal \y_int[3]_i_61_n_0\ : STD_LOGIC;
signal \y_int[3]_i_62_n_0\ : STD_LOGIC;
signal \y_int[3]_i_63_n_0\ : STD_LOGIC;
signal \y_int[3]_i_66_n_0\ : STD_LOGIC;
signal \y_int[3]_i_67_n_0\ : STD_LOGIC;
signal \y_int[3]_i_68_n_0\ : STD_LOGIC;
signal \y_int[3]_i_69_n_0\ : STD_LOGIC;
signal \y_int[3]_i_6_n_0\ : STD_LOGIC;
signal \y_int[3]_i_71_n_0\ : STD_LOGIC;
signal \y_int[3]_i_72_n_0\ : STD_LOGIC;
signal \y_int[3]_i_73_n_0\ : STD_LOGIC;
signal \y_int[3]_i_74_n_0\ : STD_LOGIC;
signal \y_int[3]_i_7_n_0\ : STD_LOGIC;
signal \y_int[3]_i_84_n_0\ : STD_LOGIC;
signal \y_int[3]_i_85_n_0\ : STD_LOGIC;
signal \y_int[3]_i_86_n_0\ : STD_LOGIC;
signal \y_int[3]_i_87_n_0\ : STD_LOGIC;
signal \y_int[3]_i_88_n_0\ : STD_LOGIC;
signal \y_int[3]_i_89_n_0\ : STD_LOGIC;
signal \y_int[3]_i_8_n_0\ : STD_LOGIC;
signal \y_int[3]_i_90_n_0\ : STD_LOGIC;
signal \y_int[3]_i_91_n_0\ : STD_LOGIC;
signal \y_int[3]_i_92_n_0\ : STD_LOGIC;
signal \y_int[7]_i_11_n_0\ : STD_LOGIC;
signal \y_int[7]_i_13_n_0\ : STD_LOGIC;
signal \y_int[7]_i_16_n_0\ : STD_LOGIC;
signal \y_int[7]_i_19_n_0\ : STD_LOGIC;
signal \y_int[7]_i_29_n_0\ : STD_LOGIC;
signal \y_int[7]_i_2_n_0\ : STD_LOGIC;
signal \y_int[7]_i_30_n_0\ : STD_LOGIC;
signal \y_int[7]_i_31_n_0\ : STD_LOGIC;
signal \y_int[7]_i_32_n_0\ : STD_LOGIC;
signal \y_int[7]_i_33_n_0\ : STD_LOGIC;
signal \y_int[7]_i_3_n_0\ : STD_LOGIC;
signal \y_int[7]_i_4_n_0\ : STD_LOGIC;
signal \y_int[7]_i_5_n_0\ : STD_LOGIC;
signal \y_int[7]_i_6_n_0\ : STD_LOGIC;
signal \y_int[7]_i_7_n_0\ : STD_LOGIC;
signal \y_int[7]_i_8_n_0\ : STD_LOGIC;
signal \y_int[7]_i_9_n_0\ : STD_LOGIC;
signal y_int_reg1 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg2 : STD_LOGIC_VECTOR ( 8 downto 1 );
signal y_int_reg20_in : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg5 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal y_int_reg6 : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_3\ : STD_LOGIC;
signal \^y_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[15]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_3\ : STD_LOGIC;
signal \^y_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[19]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_3\ : STD_LOGIC;
signal \^y_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^y_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^y_int_reg[23]_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[23]_i_10_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_10_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_10_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_11_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_3\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_75_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_75_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \^y_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^y_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \y_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_64_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_64_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_3\ : STD_LOGIC;
signal \^y_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \y_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \y_int_reg_n_0_[0]\ : STD_LOGIC;
signal \y_int_reg_n_0_[1]\ : STD_LOGIC;
signal \y_int_reg_n_0_[2]\ : STD_LOGIC;
signal \y_int_reg_n_0_[3]\ : STD_LOGIC;
signal \y_int_reg_n_0_[4]\ : STD_LOGIC;
signal \y_int_reg_n_0_[5]\ : STD_LOGIC;
signal \y_int_reg_n_0_[6]\ : STD_LOGIC;
signal \y_int_reg_n_0_[7]\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_3\ : STD_LOGIC;
signal NLW_ODDR_inst_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR_inst_S_UNCONNECTED : STD_LOGIC;
signal \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cr_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute \__SRVAL\ : string;
attribute \__SRVAL\ of ODDR_inst : label is "TRUE";
attribute box_type : string;
attribute box_type of ODDR_inst : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cb[0]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \cb[1]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cb[2]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cb[3]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cb[4]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cb[5]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cb[6]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cb[7]_i_2\ : label is "soft_lutpair34";
attribute HLUTNM : string;
attribute HLUTNM of \cb_int[11]_i_2\ : label is "lutpair8";
attribute HLUTNM of \cb_int[11]_i_3\ : label is "lutpair7";
attribute HLUTNM of \cb_int[11]_i_4\ : label is "lutpair6";
attribute HLUTNM of \cb_int[11]_i_6\ : label is "lutpair9";
attribute HLUTNM of \cb_int[11]_i_7\ : label is "lutpair8";
attribute HLUTNM of \cb_int[11]_i_8\ : label is "lutpair7";
attribute HLUTNM of \cb_int[11]_i_9\ : label is "lutpair6";
attribute HLUTNM of \cb_int[15]_i_2\ : label is "lutpair12";
attribute HLUTNM of \cb_int[15]_i_3\ : label is "lutpair11";
attribute HLUTNM of \cb_int[15]_i_4\ : label is "lutpair10";
attribute HLUTNM of \cb_int[15]_i_5\ : label is "lutpair9";
attribute HLUTNM of \cb_int[15]_i_6\ : label is "lutpair13";
attribute HLUTNM of \cb_int[15]_i_7\ : label is "lutpair12";
attribute HLUTNM of \cb_int[15]_i_8\ : label is "lutpair11";
attribute HLUTNM of \cb_int[15]_i_9\ : label is "lutpair10";
attribute HLUTNM of \cb_int[19]_i_2\ : label is "lutpair16";
attribute HLUTNM of \cb_int[19]_i_3\ : label is "lutpair15";
attribute HLUTNM of \cb_int[19]_i_4\ : label is "lutpair14";
attribute HLUTNM of \cb_int[19]_i_5\ : label is "lutpair13";
attribute HLUTNM of \cb_int[19]_i_6\ : label is "lutpair17";
attribute HLUTNM of \cb_int[19]_i_7\ : label is "lutpair16";
attribute HLUTNM of \cb_int[19]_i_8\ : label is "lutpair15";
attribute HLUTNM of \cb_int[19]_i_9\ : label is "lutpair14";
attribute HLUTNM of \cb_int[23]_i_2\ : label is "lutpair20";
attribute SOFT_HLUTNM of \cb_int[23]_i_20\ : label is "soft_lutpair19";
attribute HLUTNM of \cb_int[23]_i_3\ : label is "lutpair19";
attribute HLUTNM of \cb_int[23]_i_4\ : label is "lutpair18";
attribute HLUTNM of \cb_int[23]_i_5\ : label is "lutpair17";
attribute HLUTNM of \cb_int[23]_i_6\ : label is "lutpair21";
attribute HLUTNM of \cb_int[23]_i_7\ : label is "lutpair20";
attribute HLUTNM of \cb_int[23]_i_8\ : label is "lutpair19";
attribute HLUTNM of \cb_int[23]_i_9\ : label is "lutpair18";
attribute HLUTNM of \cb_int[27]_i_2\ : label is "lutpair21";
attribute SOFT_HLUTNM of \cb_int[31]_i_13\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \cb_int[31]_i_86\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \cb_int[31]_i_87\ : label is "soft_lutpair18";
attribute HLUTNM of \cb_int[3]_i_2\ : label is "lutpair2";
attribute HLUTNM of \cb_int[3]_i_3\ : label is "lutpair1";
attribute HLUTNM of \cb_int[3]_i_4\ : label is "lutpair39";
attribute HLUTNM of \cb_int[3]_i_5\ : label is "lutpair3";
attribute HLUTNM of \cb_int[3]_i_6\ : label is "lutpair2";
attribute HLUTNM of \cb_int[3]_i_7\ : label is "lutpair1";
attribute HLUTNM of \cb_int[3]_i_8\ : label is "lutpair39";
attribute HLUTNM of \cb_int[7]_i_3\ : label is "lutpair5";
attribute HLUTNM of \cb_int[7]_i_4\ : label is "lutpair4";
attribute HLUTNM of \cb_int[7]_i_5\ : label is "lutpair3";
attribute HLUTNM of \cb_int[7]_i_8\ : label is "lutpair5";
attribute HLUTNM of \cb_int[7]_i_9\ : label is "lutpair4";
attribute SOFT_HLUTNM of \cr[0]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cr[1]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cr[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cr[4]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cr[5]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cr[6]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \cr[7]_i_2\ : label is "soft_lutpair26";
attribute HLUTNM of \cr_int[11]_i_2\ : label is "lutpair29";
attribute SOFT_HLUTNM of \cr_int[11]_i_22\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cr_int[11]_i_23\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cr_int[11]_i_27\ : label is "soft_lutpair20";
attribute HLUTNM of \cr_int[11]_i_7\ : label is "lutpair29";
attribute HLUTNM of \cr_int[15]_i_2\ : label is "lutpair30";
attribute HLUTNM of \cr_int[15]_i_7\ : label is "lutpair30";
attribute HLUTNM of \cr_int[19]_i_2\ : label is "lutpair31";
attribute HLUTNM of \cr_int[19]_i_7\ : label is "lutpair31";
attribute HLUTNM of \cr_int[23]_i_2\ : label is "lutpair32";
attribute HLUTNM of \cr_int[23]_i_7\ : label is "lutpair32";
attribute SOFT_HLUTNM of \cr_int[31]_i_13\ : label is "soft_lutpair20";
attribute HLUTNM of \cr_int[31]_i_16\ : label is "lutpair23";
attribute HLUTNM of \cr_int[31]_i_44\ : label is "lutpair23";
attribute HLUTNM of \cr_int[3]_i_2\ : label is "lutpair25";
attribute HLUTNM of \cr_int[3]_i_3\ : label is "lutpair24";
attribute HLUTNM of \cr_int[3]_i_34\ : label is "lutpair22";
attribute HLUTNM of \cr_int[3]_i_39\ : label is "lutpair22";
attribute HLUTNM of \cr_int[3]_i_4\ : label is "lutpair40";
attribute HLUTNM of \cr_int[3]_i_5\ : label is "lutpair26";
attribute HLUTNM of \cr_int[3]_i_6\ : label is "lutpair25";
attribute HLUTNM of \cr_int[3]_i_7\ : label is "lutpair24";
attribute HLUTNM of \cr_int[3]_i_8\ : label is "lutpair40";
attribute HLUTNM of \cr_int[7]_i_3\ : label is "lutpair28";
attribute HLUTNM of \cr_int[7]_i_4\ : label is "lutpair27";
attribute HLUTNM of \cr_int[7]_i_5\ : label is "lutpair26";
attribute HLUTNM of \cr_int[7]_i_8\ : label is "lutpair28";
attribute HLUTNM of \cr_int[7]_i_9\ : label is "lutpair27";
attribute SOFT_HLUTNM of \y[0]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \y[1]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \y[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \y[3]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \y[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \y[5]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \y[6]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \y[7]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \y_hold[0]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y_hold[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y_hold[2]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \y_hold[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \y_hold[4]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \y_hold[5]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \y_hold[6]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y_hold[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y_int[23]_i_12\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \y_int[31]_i_13\ : label is "soft_lutpair21";
attribute HLUTNM of \y_int[3]_i_2\ : label is "lutpair35";
attribute HLUTNM of \y_int[3]_i_3\ : label is "lutpair34";
attribute HLUTNM of \y_int[3]_i_4\ : label is "lutpair33";
attribute HLUTNM of \y_int[3]_i_5\ : label is "lutpair36";
attribute HLUTNM of \y_int[3]_i_6\ : label is "lutpair35";
attribute HLUTNM of \y_int[3]_i_7\ : label is "lutpair34";
attribute HLUTNM of \y_int[3]_i_8\ : label is "lutpair33";
attribute HLUTNM of \y_int[7]_i_3\ : label is "lutpair38";
attribute HLUTNM of \y_int[7]_i_4\ : label is "lutpair37";
attribute HLUTNM of \y_int[7]_i_5\ : label is "lutpair36";
attribute HLUTNM of \y_int[7]_i_8\ : label is "lutpair38";
attribute HLUTNM of \y_int[7]_i_9\ : label is "lutpair37";
begin
CO(0) <= \^co\(0);
DI(0) <= \^di\(0);
O(1 downto 0) <= \^o\(1 downto 0);
\cb_int_reg[3]_0\(3 downto 0) <= \^cb_int_reg[3]_0\(3 downto 0);
\cr_int_reg[11]_0\(3 downto 0) <= \^cr_int_reg[11]_0\(3 downto 0);
\cr_int_reg[15]_0\(3 downto 0) <= \^cr_int_reg[15]_0\(3 downto 0);
\cr_int_reg[19]_0\(3 downto 0) <= \^cr_int_reg[19]_0\(3 downto 0);
\cr_int_reg[23]_0\(3 downto 0) <= \^cr_int_reg[23]_0\(3 downto 0);
\cr_int_reg[23]_1\(0) <= \^cr_int_reg[23]_1\(0);
\cr_int_reg[27]_0\ <= \^cr_int_reg[27]_0\;
\cr_int_reg[27]_1\(1 downto 0) <= \^cr_int_reg[27]_1\(1 downto 0);
\cr_int_reg[27]_2\(0) <= \^cr_int_reg[27]_2\(0);
\cr_int_reg[31]_0\ <= \^cr_int_reg[31]_0\;
\cr_int_reg[31]_1\ <= \^cr_int_reg[31]_1\;
\cr_int_reg[31]_2\(1 downto 0) <= \^cr_int_reg[31]_2\(1 downto 0);
\cr_int_reg[3]_0\(2 downto 0) <= \^cr_int_reg[3]_0\(2 downto 0);
\cr_int_reg[3]_1\(0) <= \^cr_int_reg[3]_1\(0);
\cr_int_reg[3]_2\(1 downto 0) <= \^cr_int_reg[3]_2\(1 downto 0);
\cr_int_reg[7]_0\(3 downto 0) <= \^cr_int_reg[7]_0\(3 downto 0);
\cr_int_reg[7]_1\(3 downto 0) <= \^cr_int_reg[7]_1\(3 downto 0);
\y_int_reg[15]_0\(3 downto 0) <= \^y_int_reg[15]_0\(3 downto 0);
\y_int_reg[19]_0\(3 downto 0) <= \^y_int_reg[19]_0\(3 downto 0);
\y_int_reg[23]_0\(0) <= \^y_int_reg[23]_0\(0);
\y_int_reg[23]_1\(1 downto 0) <= \^y_int_reg[23]_1\(1 downto 0);
\y_int_reg[23]_2\(3 downto 0) <= \^y_int_reg[23]_2\(3 downto 0);
\y_int_reg[3]_0\(3 downto 0) <= \^y_int_reg[3]_0\(3 downto 0);
\y_int_reg[3]_1\(0) <= \^y_int_reg[3]_1\(0);
\y_int_reg[7]_0\(0) <= \^y_int_reg[7]_0\(0);
Inst_i2c_sender: entity work.system_zed_hdmi_0_0_i2c_sender
port map (
clk_100 => clk_100,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda
);
ODDR_inst: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
IS_C_INVERTED => '0',
IS_D1_INVERTED => '0',
IS_D2_INVERTED => '0',
SRTYPE => "SYNC"
)
port map (
C => clk_x2,
CE => '1',
D1 => D1,
D2 => D1,
Q => hdmi_clk,
R => NLW_ODDR_inst_R_UNCONNECTED,
S => NLW_ODDR_inst_S_UNCONNECTED
);
\cb[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[0]\,
I1 => \cb_int_reg__0\(31),
O => \cb[0]_i_1_n_0\
);
\cb[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[1]\,
I1 => \cb_int_reg__0\(31),
O => \cb[1]_i_1_n_0\
);
\cb[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[2]\,
I1 => \cb_int_reg__0\(31),
O => \cb[2]_i_1_n_0\
);
\cb[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[3]\,
I1 => \cb_int_reg__0\(31),
O => \cb[3]_i_1_n_0\
);
\cb[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[4]\,
I1 => \cb_int_reg__0\(31),
O => \cb[4]_i_1_n_0\
);
\cb[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[5]\,
I1 => \cb_int_reg__0\(31),
O => \cb[5]_i_1_n_0\
);
\cb[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[6]\,
I1 => \cb_int_reg__0\(31),
O => \cb[6]_i_1_n_0\
);
\cb[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(26),
I1 => \cb_int_reg__0\(27),
O => \cb[7]_i_10_n_0\
);
\cb[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(24),
I1 => \cb_int_reg__0\(25),
O => \cb[7]_i_11_n_0\
);
\cb[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(22),
I1 => \cb_int_reg__0\(23),
O => \cb[7]_i_13_n_0\
);
\cb[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(20),
I1 => \cb_int_reg__0\(21),
O => \cb[7]_i_14_n_0\
);
\cb[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(18),
I1 => \cb_int_reg__0\(19),
O => \cb[7]_i_15_n_0\
);
\cb[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(16),
I1 => \cb_int_reg__0\(17),
O => \cb[7]_i_16_n_0\
);
\cb[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(22),
I1 => \cb_int_reg__0\(23),
O => \cb[7]_i_17_n_0\
);
\cb[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(20),
I1 => \cb_int_reg__0\(21),
O => \cb[7]_i_18_n_0\
);
\cb[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(18),
I1 => \cb_int_reg__0\(19),
O => \cb[7]_i_19_n_0\
);
\cb[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[7]\,
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_2_n_0\
);
\cb[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(16),
I1 => \cb_int_reg__0\(17),
O => \cb[7]_i_20_n_0\
);
\cb[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(14),
I1 => \cb_int_reg__0\(15),
O => \cb[7]_i_21_n_0\
);
\cb[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(12),
I1 => \cb_int_reg__0\(13),
O => \cb[7]_i_22_n_0\
);
\cb[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(10),
I1 => \cb_int_reg__0\(11),
O => \cb[7]_i_23_n_0\
);
\cb[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(8),
I1 => \cb_int_reg__0\(9),
O => \cb[7]_i_24_n_0\
);
\cb[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(14),
I1 => \cb_int_reg__0\(15),
O => \cb[7]_i_25_n_0\
);
\cb[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(12),
I1 => \cb_int_reg__0\(13),
O => \cb[7]_i_26_n_0\
);
\cb[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(10),
I1 => \cb_int_reg__0\(11),
O => \cb[7]_i_27_n_0\
);
\cb[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(8),
I1 => \cb_int_reg__0\(9),
O => \cb[7]_i_28_n_0\
);
\cb[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg__0\(30),
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_4_n_0\
);
\cb[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(28),
I1 => \cb_int_reg__0\(29),
O => \cb[7]_i_5_n_0\
);
\cb[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(26),
I1 => \cb_int_reg__0\(27),
O => \cb[7]_i_6_n_0\
);
\cb[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(24),
I1 => \cb_int_reg__0\(25),
O => \cb[7]_i_7_n_0\
);
\cb[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(30),
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_8_n_0\
);
\cb[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(28),
I1 => \cb_int_reg__0\(29),
O => \cb[7]_i_9_n_0\
);
\cb_hold[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => edge,
I1 => edge_rb,
O => \cb_hold[7]_i_1_n_0\
);
\cb_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(0),
Q => cb_hold(0),
R => '0'
);
\cb_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(1),
Q => cb_hold(1),
R => '0'
);
\cb_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(2),
Q => cb_hold(2),
R => '0'
);
\cb_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(3),
Q => cb_hold(3),
R => '0'
);
\cb_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(4),
Q => cb_hold(4),
R => '0'
);
\cb_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(5),
Q => cb_hold(5),
R => '0'
);
\cb_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(6),
Q => cb_hold(6),
R => '0'
);
\cb_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(7),
Q => cb_hold(7),
R => '0'
);
\cb_int[11]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(10),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(18),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_25_n_0\,
I5 => cb_int_reg2(10),
O => \cb_int[11]_i_10_n_0\
);
\cb_int[11]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_6\,
I1 => \cb_int_reg[3]_i_16_n_5\,
O => \cb_int[11]_i_100_n_0\
);
\cb_int[11]_i_101\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_4\,
I1 => \cb_int_reg[3]_i_16_n_7\,
O => \cb_int[11]_i_101_n_0\
);
\cb_int[11]_i_102\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_6\,
I1 => \cb_int_reg[3]_i_26_n_5\,
O => \cb_int[11]_i_102_n_0\
);
\cb_int[11]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_7\,
I1 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[11]_i_103_n_0\
);
\cb_int[11]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_5\,
I1 => \cb_int_reg[3]_i_16_n_6\,
O => \cb_int[11]_i_104_n_0\
);
\cb_int[11]_i_105\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_7\,
I1 => \cb_int_reg[3]_i_26_n_4\,
O => \cb_int[11]_i_105_n_0\
);
\cb_int[11]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_5\,
I1 => \cb_int_reg[3]_i_26_n_6\,
O => \cb_int[11]_i_106_n_0\
);
\cb_int[11]_i_107\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_7\,
I1 => \cb_int_reg[3]_i_20_n_6\,
O => \cb_int[11]_i_107_n_0\
);
\cb_int[11]_i_108\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_7\,
I1 => \cb_int_reg[3]_i_44_n_6\,
O => \cb_int[11]_i_108_n_0\
);
\cb_int[11]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_5\,
I1 => \cb_int_reg[3]_i_75_n_4\,
O => \cb_int[11]_i_109_n_0\
);
\cb_int[11]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(9),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(17),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_20_n_0\,
I5 => cb_int_reg2(9),
O => \cb_int[11]_i_11_n_0\
);
\cb_int[11]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_7\,
I1 => \cb_int_reg[3]_i_75_n_6\,
O => \cb_int[11]_i_110_n_0\
);
\cb_int[11]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_6\,
I1 => \cb_int_reg[3]_i_20_n_7\,
O => \cb_int[11]_i_111_n_0\
);
\cb_int[11]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_6\,
I1 => \cb_int_reg[3]_i_44_n_7\,
O => \cb_int[11]_i_112_n_0\
);
\cb_int[11]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_4\,
I1 => \cb_int_reg[3]_i_75_n_5\,
O => \cb_int[11]_i_113_n_0\
);
\cb_int[11]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_6\,
I1 => \cb_int_reg[3]_i_75_n_7\,
O => \cb_int[11]_i_114_n_0\
);
\cb_int[11]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(9),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(17),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_20_n_0\,
I5 => cb_int_reg2(9),
O => \cb_int[11]_i_12_n_0\
);
\cb_int[11]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(8),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(16),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_22_n_0\,
I5 => cb_int_reg2(8),
O => \cb_int[11]_i_13_n_0\
);
\cb_int[11]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(8),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(16),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_22_n_0\,
I5 => cb_int_reg2(8),
O => \cb_int[11]_i_14_n_0\
);
\cb_int[11]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFE200E2"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
I3 => \rgb888[0]\(3),
I4 => cb_int_reg3(7),
I5 => \cb_int[11]_i_27_n_0\,
O => \cb_int[11]_i_15_n_0\
);
\cb_int[11]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE200E2001DFF1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
I3 => \rgb888[0]\(3),
I4 => cb_int_reg3(7),
I5 => \cb_int[11]_i_27_n_0\,
O => \cb_int[11]_i_19_n_0\
);
\cb_int[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_10_n_0\,
I1 => \cb_int[11]_i_11_n_0\,
O => \cb_int[11]_i_2_n_0\
);
\cb_int[11]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(0),
O => \cb_int[11]_i_20_n_0\
);
\cb_int[11]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(9),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(9)
);
\cb_int[11]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_3\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]\(3),
O => \cb_int[11]_i_22_n_0\
);
\cb_int[11]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(8),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_4\,
O => cb_int_reg2(8)
);
\cb_int[11]_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(2),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(2),
I3 => \^co\(0),
I4 => \rgb888[8]_1\(0),
O => \cb_int[11]_i_27_n_0\
);
\cb_int[11]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(16),
O => \cb_int[11]_i_29_n_0\
);
\cb_int[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_12_n_0\,
I1 => \cb_int[11]_i_13_n_0\,
O => \cb_int[11]_i_3_n_0\
);
\cb_int[11]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(15),
O => \cb_int[11]_i_30_n_0\
);
\cb_int[11]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(14),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_31_n_0\
);
\cb_int[11]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(13),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_32_n_0\
);
\cb_int[11]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_34_n_0\
);
\cb_int[11]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_35_n_0\
);
\cb_int[11]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_36_n_0\
);
\cb_int[11]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_37_n_0\
);
\cb_int[11]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_39_n_0\
);
\cb_int[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_14_n_0\,
I1 => \cb_int[11]_i_15_n_0\,
O => \cb_int[11]_i_4_n_0\
);
\cb_int[11]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_40_n_0\
);
\cb_int[11]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_41_n_0\
);
\cb_int[11]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_42_n_0\
);
\cb_int[11]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_43_n_0\
);
\cb_int[11]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(2),
O => \cb_int[11]_i_44_n_0\
);
\cb_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(1),
O => \cb_int[11]_i_45_n_0\
);
\cb_int[11]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(0),
O => \cb_int[11]_i_46_n_0\
);
\cb_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_47_n_0\
);
\cb_int[11]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_49_n_0\
);
\cb_int[11]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"DD1D0000"
)
port map (
I0 => cb_int_reg5(7),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(15),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_19_n_0\,
O => \cb_int[11]_i_5_n_0\
);
\cb_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_50_n_0\
);
\cb_int[11]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_51_n_0\
);
\cb_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_52_n_0\
);
\cb_int[11]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(2),
O => \cb_int[11]_i_53_n_0\
);
\cb_int[11]_i_54\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
O => \cb_int[11]_i_54_n_0\
);
\cb_int[11]_i_55\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_6\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(0),
O => \cb_int[11]_i_55_n_0\
);
\cb_int[11]_i_56\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_7\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_56_n_0\
);
\cb_int[11]_i_57\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[11]_i_57_n_0\
);
\cb_int[11]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(12),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_58_n_0\
);
\cb_int[11]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(11),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_59_n_0\
);
\cb_int[11]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_16_n_0\,
I1 => \cb_int[15]_i_17_n_0\,
I2 => \cb_int[11]_i_2_n_0\,
O => \cb_int[11]_i_6_n_0\
);
\cb_int[11]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(10),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[11]_i_60_n_0\
);
\cb_int[11]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(9),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[11]_i_61_n_0\
);
\cb_int[11]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_62_n_0\
);
\cb_int[11]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_63_n_0\
);
\cb_int[11]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_64_n_0\
);
\cb_int[11]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_65_n_0\
);
\cb_int[11]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_67_n_0\
);
\cb_int[11]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_68_n_0\
);
\cb_int[11]_i_69\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_69_n_0\
);
\cb_int[11]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_10_n_0\,
I1 => \cb_int[11]_i_11_n_0\,
I2 => \cb_int[11]_i_3_n_0\,
O => \cb_int[11]_i_7_n_0\
);
\cb_int[11]_i_70\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_70_n_0\
);
\cb_int[11]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_71_n_0\
);
\cb_int[11]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_72_n_0\
);
\cb_int[11]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_73_n_0\
);
\cb_int[11]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_74_n_0\
);
\cb_int[11]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]\(2),
I1 => \rgb888[0]\(3),
O => \cb_int[11]_i_76_n_0\
);
\cb_int[11]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_77_n_0\
);
\cb_int[11]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_78_n_0\
);
\cb_int[11]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_79_n_0\
);
\cb_int[11]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_12_n_0\,
I1 => \cb_int[11]_i_13_n_0\,
I2 => \cb_int[11]_i_4_n_0\,
O => \cb_int[11]_i_8_n_0\
);
\cb_int[11]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \rgb888[0]\(2),
O => \cb_int[11]_i_80_n_0\
);
\cb_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_82_n_0\
);
\cb_int[11]_i_83\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_6\,
I1 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_83_n_0\
);
\cb_int[11]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_4\,
I1 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_84_n_0\
);
\cb_int[11]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_6\,
I1 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_85_n_0\
);
\cb_int[11]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_86_n_0\
);
\cb_int[11]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_87_n_0\
);
\cb_int[11]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_7\,
I1 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_88_n_0\
);
\cb_int[11]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_5\,
I1 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[11]_i_89_n_0\
);
\cb_int[11]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_14_n_0\,
I1 => \cb_int[11]_i_15_n_0\,
I2 => \cb_int[11]_i_5_n_0\,
O => \cb_int[11]_i_9_n_0\
);
\cb_int[11]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]\(0),
I1 => \rgb888[0]\(1),
O => \cb_int[11]_i_91_n_0\
);
\cb_int[11]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]_0\(2),
I1 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_92_n_0\
);
\cb_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]_0\(0),
I1 => \rgb888[0]_0\(1),
O => \cb_int[11]_i_93_n_0\
);
\cb_int[11]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
I1 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[11]_i_94_n_0\
);
\cb_int[11]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(1),
I1 => \rgb888[0]\(0),
O => \cb_int[11]_i_95_n_0\
);
\cb_int[11]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(3),
I1 => \rgb888[0]_0\(2),
O => \cb_int[11]_i_96_n_0\
);
\cb_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(1),
I1 => \rgb888[0]_0\(0),
O => \cb_int[11]_i_97_n_0\
);
\cb_int[11]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_4\,
I1 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[11]_i_98_n_0\
);
\cb_int[11]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_4\,
I1 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[11]_i_99_n_0\
);
\cb_int[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(14),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(22),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_26_n_0\,
I5 => cb_int_reg2(14),
O => \cb_int[15]_i_10_n_0\
);
\cb_int[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(13),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(21),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_18_n_0\,
I5 => cb_int_reg2(13),
O => \cb_int[15]_i_11_n_0\
);
\cb_int[15]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(13),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(21),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_18_n_0\,
I5 => cb_int_reg2(13),
O => \cb_int[15]_i_12_n_0\
);
\cb_int[15]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(12),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(20),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_21_n_0\,
I5 => cb_int_reg2(12),
O => \cb_int[15]_i_13_n_0\
);
\cb_int[15]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(12),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(20),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_21_n_0\,
I5 => cb_int_reg2(12),
O => \cb_int[15]_i_14_n_0\
);
\cb_int[15]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(11),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(19),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_23_n_0\,
I5 => cb_int_reg2(11),
O => \cb_int[15]_i_15_n_0\
);
\cb_int[15]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(11),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(19),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_23_n_0\,
I5 => cb_int_reg2(11),
O => \cb_int[15]_i_16_n_0\
);
\cb_int[15]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(10),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(18),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_25_n_0\,
I5 => cb_int_reg2(10),
O => \cb_int[15]_i_17_n_0\
);
\cb_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(0),
O => \cb_int[15]_i_18_n_0\
);
\cb_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(13),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(13)
);
\cb_int[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_10_n_0\,
I1 => \cb_int[15]_i_11_n_0\,
O => \cb_int[15]_i_2_n_0\
);
\cb_int[15]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(3),
O => \cb_int[15]_i_21_n_0\
);
\cb_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(12),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(12)
);
\cb_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(2),
O => \cb_int[15]_i_23_n_0\
);
\cb_int[15]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(11),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(11)
);
\cb_int[15]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(1),
O => \cb_int[15]_i_25_n_0\
);
\cb_int[15]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(10),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(10)
);
\cb_int[15]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(20),
O => \cb_int[15]_i_27_n_0\
);
\cb_int[15]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(19),
O => \cb_int[15]_i_28_n_0\
);
\cb_int[15]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(18),
O => \cb_int[15]_i_29_n_0\
);
\cb_int[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_12_n_0\,
I1 => \cb_int[15]_i_13_n_0\,
O => \cb_int[15]_i_3_n_0\
);
\cb_int[15]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(17),
O => \cb_int[15]_i_30_n_0\
);
\cb_int[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_14_n_0\,
I1 => \cb_int[15]_i_15_n_0\,
O => \cb_int[15]_i_4_n_0\
);
\cb_int[15]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(3),
O => \cb_int[15]_i_43_n_0\
);
\cb_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(2),
O => \cb_int[15]_i_44_n_0\
);
\cb_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(1),
O => \cb_int[15]_i_45_n_0\
);
\cb_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(0),
O => \cb_int[15]_i_46_n_0\
);
\cb_int[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_16_n_0\,
I1 => \cb_int[15]_i_17_n_0\,
O => \cb_int[15]_i_5_n_0\
);
\cb_int[15]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_16_n_0\,
I1 => \cb_int[19]_i_17_n_0\,
I2 => \cb_int[15]_i_2_n_0\,
O => \cb_int[15]_i_6_n_0\
);
\cb_int[15]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_10_n_0\,
I1 => \cb_int[15]_i_11_n_0\,
I2 => \cb_int[15]_i_3_n_0\,
O => \cb_int[15]_i_7_n_0\
);
\cb_int[15]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_12_n_0\,
I1 => \cb_int[15]_i_13_n_0\,
I2 => \cb_int[15]_i_4_n_0\,
O => \cb_int[15]_i_8_n_0\
);
\cb_int[15]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_14_n_0\,
I1 => \cb_int[15]_i_15_n_0\,
I2 => \cb_int[15]_i_5_n_0\,
O => \cb_int[15]_i_9_n_0\
);
\cb_int[19]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(18),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(26),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_25_n_0\,
I5 => cb_int_reg2(18),
O => \cb_int[19]_i_10_n_0\
);
\cb_int[19]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(17),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(25),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_18_n_0\,
I5 => cb_int_reg2(17),
O => \cb_int[19]_i_11_n_0\
);
\cb_int[19]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(17),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(25),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_18_n_0\,
I5 => cb_int_reg2(17),
O => \cb_int[19]_i_12_n_0\
);
\cb_int[19]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(16),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(24),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_21_n_0\,
I5 => cb_int_reg2(16),
O => \cb_int[19]_i_13_n_0\
);
\cb_int[19]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(16),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(24),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_21_n_0\,
I5 => cb_int_reg2(16),
O => \cb_int[19]_i_14_n_0\
);
\cb_int[19]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(15),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(23),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_23_n_0\,
I5 => cb_int_reg2(15),
O => \cb_int[19]_i_15_n_0\
);
\cb_int[19]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(15),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(23),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_23_n_0\,
I5 => cb_int_reg2(15),
O => \cb_int[19]_i_16_n_0\
);
\cb_int[19]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(14),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(22),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_26_n_0\,
I5 => cb_int_reg2(14),
O => \cb_int[19]_i_17_n_0\
);
\cb_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(0),
O => \cb_int[19]_i_18_n_0\
);
\cb_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(17),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(17)
);
\cb_int[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_10_n_0\,
I1 => \cb_int[19]_i_11_n_0\,
O => \cb_int[19]_i_2_n_0\
);
\cb_int[19]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(3),
O => \cb_int[19]_i_21_n_0\
);
\cb_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(16),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(16)
);
\cb_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(2),
O => \cb_int[19]_i_23_n_0\
);
\cb_int[19]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(15),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(15)
);
\cb_int[19]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(1),
O => \cb_int[19]_i_26_n_0\
);
\cb_int[19]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(14),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(14)
);
\cb_int[19]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(24),
O => \cb_int[19]_i_28_n_0\
);
\cb_int[19]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(23),
O => \cb_int[19]_i_29_n_0\
);
\cb_int[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_12_n_0\,
I1 => \cb_int[19]_i_13_n_0\,
O => \cb_int[19]_i_3_n_0\
);
\cb_int[19]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(22),
O => \cb_int[19]_i_30_n_0\
);
\cb_int[19]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(21),
O => \cb_int[19]_i_31_n_0\
);
\cb_int[19]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_34_n_0\
);
\cb_int[19]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_35_n_0\
);
\cb_int[19]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_36_n_0\
);
\cb_int[19]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_37_n_0\
);
\cb_int[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_14_n_0\,
I1 => \cb_int[19]_i_15_n_0\,
O => \cb_int[19]_i_4_n_0\
);
\cb_int[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_16_n_0\,
I1 => \cb_int[19]_i_17_n_0\,
O => \cb_int[19]_i_5_n_0\
);
\cb_int[19]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_16_n_0\,
I1 => \cb_int[23]_i_17_n_0\,
I2 => \cb_int[19]_i_2_n_0\,
O => \cb_int[19]_i_6_n_0\
);
\cb_int[19]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_10_n_0\,
I1 => \cb_int[19]_i_11_n_0\,
I2 => \cb_int[19]_i_3_n_0\,
O => \cb_int[19]_i_7_n_0\
);
\cb_int[19]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_12_n_0\,
I1 => \cb_int[19]_i_13_n_0\,
I2 => \cb_int[19]_i_4_n_0\,
O => \cb_int[19]_i_8_n_0\
);
\cb_int[19]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_14_n_0\,
I1 => \cb_int[19]_i_15_n_0\,
I2 => \cb_int[19]_i_5_n_0\,
O => \cb_int[19]_i_9_n_0\
);
\cb_int[23]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(22),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(30),
I3 => cb_int_reg8,
I4 => \cb_int[27]_i_10_n_0\,
I5 => cb_int_reg2(22),
O => \cb_int[23]_i_10_n_0\
);
\cb_int[23]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(21),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(29),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_18_n_0\,
I5 => cb_int_reg2(21),
O => \cb_int[23]_i_11_n_0\
);
\cb_int[23]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(21),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(29),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_18_n_0\,
I5 => cb_int_reg2(21),
O => \cb_int[23]_i_12_n_0\
);
\cb_int[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(20),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(28),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_20_n_0\,
I5 => cb_int_reg2(20),
O => \cb_int[23]_i_13_n_0\
);
\cb_int[23]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(20),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(28),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_20_n_0\,
I5 => cb_int_reg2(20),
O => \cb_int[23]_i_14_n_0\
);
\cb_int[23]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(19),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(27),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_22_n_0\,
I5 => cb_int_reg2(19),
O => \cb_int[23]_i_15_n_0\
);
\cb_int[23]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(19),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(27),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_22_n_0\,
I5 => cb_int_reg2(19),
O => \cb_int[23]_i_16_n_0\
);
\cb_int[23]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(18),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(26),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_25_n_0\,
I5 => cb_int_reg2(18),
O => \cb_int[23]_i_17_n_0\
);
\cb_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_9\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_10\(0),
O => \cb_int[23]_i_18_n_0\
);
\cb_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(21),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_1\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(21)
);
\cb_int[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_10_n_0\,
I1 => \cb_int[23]_i_11_n_0\,
O => \cb_int[23]_i_2_n_0\
);
\cb_int[23]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(3),
O => \cb_int[23]_i_20_n_0\
);
\cb_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(20),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(20)
);
\cb_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(2),
O => \cb_int[23]_i_22_n_0\
);
\cb_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(19),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(19)
);
\cb_int[23]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(1),
O => \cb_int[23]_i_25_n_0\
);
\cb_int[23]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(18),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(18)
);
\cb_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_29_n_0\
);
\cb_int[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_12_n_0\,
I1 => \cb_int[23]_i_13_n_0\,
O => \cb_int[23]_i_3_n_0\
);
\cb_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_30_n_0\
);
\cb_int[23]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_31_n_0\
);
\cb_int[23]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_32_n_0\
);
\cb_int[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_14_n_0\,
I1 => \cb_int[23]_i_15_n_0\,
O => \cb_int[23]_i_4_n_0\
);
\cb_int[23]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_16_n_0\,
I1 => \cb_int[23]_i_17_n_0\,
O => \cb_int[23]_i_5_n_0\
);
\cb_int[23]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[27]_i_7_n_0\,
I1 => \cb_int[27]_i_8_n_0\,
I2 => \cb_int[23]_i_2_n_0\,
O => \cb_int[23]_i_6_n_0\
);
\cb_int[23]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_10_n_0\,
I1 => \cb_int[23]_i_11_n_0\,
I2 => \cb_int[23]_i_3_n_0\,
O => \cb_int[23]_i_7_n_0\
);
\cb_int[23]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_12_n_0\,
I1 => \cb_int[23]_i_13_n_0\,
I2 => \cb_int[23]_i_4_n_0\,
O => \cb_int[23]_i_8_n_0\
);
\cb_int[23]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_14_n_0\,
I1 => \cb_int[23]_i_15_n_0\,
I2 => \cb_int[23]_i_5_n_0\,
O => \cb_int[23]_i_9_n_0\
);
\cb_int[27]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_9\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_10\(1),
O => \cb_int[27]_i_10_n_0\
);
\cb_int[27]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(22),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_1\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(22)
);
\cb_int[27]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_12_n_0\
);
\cb_int[27]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_13_n_0\
);
\cb_int[27]_i_14\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_14_n_0\
);
\cb_int[27]_i_15\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_15_n_0\
);
\cb_int[27]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[27]_i_7_n_0\,
I1 => \cb_int[27]_i_8_n_0\,
O => \cb_int[27]_i_2_n_0\
);
\cb_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_3_n_0\
);
\cb_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_4_n_0\
);
\cb_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_5_n_0\
);
\cb_int[27]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[27]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_6_n_0\
);
\cb_int[27]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"1E111E11E1EE1E11"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => \cb_int_reg[31]_i_11_n_1\,
I2 => \rgb888[8]_11\(0),
I3 => \rgb888[8]_1\(1),
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_7_n_0\
);
\cb_int[27]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(22),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(30),
I3 => cb_int_reg8,
I4 => \cb_int[27]_i_10_n_0\,
I5 => cb_int_reg2(22),
O => \cb_int[27]_i_8_n_0\
);
\cb_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rgb888[8]_11\(0),
I1 => \rgb888[8]_1\(1),
O => \cb_int[31]_i_13_n_0\
);
\cb_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_1\(1),
O => \cb_int[31]_i_15_n_0\
);
\cb_int[31]_i_16\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_1\(0),
O => \cb_int[31]_i_16_n_0\
);
\cb_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4404440444040000"
)
port map (
I0 => \cb_int_reg[31]_i_7_n_1\,
I1 => \rgb888[0]\(3),
I2 => \rgb888[8]_1\(1),
I3 => \rgb888[8]_11\(0),
I4 => \cb_int_reg[31]_i_11_n_1\,
I5 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[31]_i_2_n_0\
);
\cb_int[31]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \^di\(0)
);
\cb_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_3_n_0\
);
\cb_int[31]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(30),
O => \cb_int[31]_i_31_n_0\
);
\cb_int[31]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(29),
O => \cb_int[31]_i_32_n_0\
);
\cb_int[31]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_34_n_2\,
O => \cb_int[31]_i_35_n_0\
);
\cb_int[31]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_34_n_2\,
O => \cb_int[31]_i_36_n_0\
);
\cb_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(3),
O => \cb_int[31]_i_38_n_0\
);
\cb_int[31]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(2),
O => \cb_int[31]_i_39_n_0\
);
\cb_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_4_n_0\
);
\cb_int[31]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(1),
O => \cb_int[31]_i_40_n_0\
);
\cb_int[31]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(0),
O => \cb_int[31]_i_41_n_0\
);
\cb_int[31]_i_43\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFE"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(1),
I3 => rgb888(2),
I4 => rgb888(4),
I5 => rgb888(6),
O => \^cr_int_reg[27]_1\(1)
);
\cb_int[31]_i_44\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFE"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => rgb888(5),
O => \^cr_int_reg[27]_1\(0)
);
\cb_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_5_n_0\
);
\cb_int[31]_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(1),
I3 => rgb888(2),
I4 => rgb888(4),
I5 => rgb888(6),
O => \^cr_int_reg[27]_0\
);
\cb_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_6_n_0\
);
\cb_int[31]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(28),
O => \cb_int[31]_i_67_n_0\
);
\cb_int[31]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(27),
O => \cb_int[31]_i_68_n_0\
);
\cb_int[31]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(26),
O => \cb_int[31]_i_69_n_0\
);
\cb_int[31]_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(25),
O => \cb_int[31]_i_70_n_0\
);
\cb_int[31]_i_71\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_5\,
I1 => rgb888(23),
I2 => rgb888(22),
O => \cb_int[31]_i_71_n_0\
);
\cb_int[31]_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_6\,
I1 => rgb888(23),
I2 => rgb888(22),
O => \cb_int[31]_i_72_n_0\
);
\cb_int[31]_i_74\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FE0"
)
port map (
I0 => rgb888(22),
I1 => rgb888(23),
I2 => \cb_int_reg[31]_i_73_n_4\,
I3 => \cb_int_reg[31]_i_34_n_7\,
O => \cb_int[31]_i_74_n_0\
);
\cb_int[31]_i_75\: unisim.vcomponents.LUT4
generic map(
INIT => X"3336"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_5\,
I1 => \cb_int_reg[31]_i_73_n_4\,
I2 => rgb888(22),
I3 => rgb888(23),
O => \cb_int[31]_i_75_n_0\
);
\cb_int[31]_i_76\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_6\,
I1 => rgb888(22),
I2 => rgb888(23),
I3 => \cb_int_reg[31]_i_73_n_5\,
O => \cb_int[31]_i_76_n_0\
);
\cb_int[31]_i_77\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
I1 => \cb_int_reg[31]_i_73_n_6\,
I2 => rgb888(22),
I3 => rgb888(23),
O => \cb_int[31]_i_77_n_0\
);
\cb_int[31]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \cb_int[31]_i_78_n_0\
);
\cb_int[31]_i_79\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(3),
O => \cb_int[31]_i_79_n_0\
);
\cb_int[31]_i_80\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(2),
O => \cb_int[31]_i_80_n_0\
);
\cb_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(1),
O => \cb_int[31]_i_81_n_0\
);
\cb_int[31]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(0),
O => \cb_int[31]_i_82_n_0\
);
\cb_int[31]_i_86\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rgb888(11),
I1 => rgb888(10),
I2 => rgb888(12),
I3 => rgb888(13),
O => \^cr_int_reg[31]_1\
);
\cb_int[31]_i_87\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
I4 => rgb888(14),
O => \^cr_int_reg[31]_0\
);
\cb_int[31]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(22),
O => \cb_int[31]_i_95_n_0\
);
\cb_int[31]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(23),
I1 => rgb888(21),
O => \cb_int[31]_i_96_n_0\
);
\cb_int[31]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
O => \cb_int[31]_i_97_n_0\
);
\cb_int[31]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
O => \cb_int[31]_i_98_n_0\
);
\cb_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(1),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(1),
I3 => \^co\(0),
I4 => \rgb888[8]\(3),
O => \cb_int[3]_i_10_n_0\
);
\cb_int[3]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(0),
I1 => rgb888(2),
O => \cb_int[3]_i_100_n_0\
);
\cb_int[3]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \cb_int[3]_i_101_n_0\
);
\cb_int[3]_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(0),
O => \cb_int[3]_i_102_n_0\
);
\cb_int[3]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(11),
O => \cb_int[3]_i_103_n_0\
);
\cb_int[3]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(10),
O => \cb_int[3]_i_104_n_0\
);
\cb_int[3]_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \cb_int[3]_i_105_n_0\
);
\cb_int[3]_i_106\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \cb_int[3]_i_106_n_0\
);
\cb_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(2),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_6\,
O => cb_int_reg2(2)
);
\cb_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(9),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_7\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(1),
O => \cb_int[3]_i_12_n_0\
);
\cb_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(0),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(0),
I3 => \^co\(0),
I4 => \rgb888[8]\(2),
O => \cb_int[3]_i_13_n_0\
);
\cb_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(1),
I1 => \rgb888[0]\(3),
I2 => \cb_int_reg[3]_i_20_n_4\,
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_7\,
O => cb_int_reg2(1)
);
\cb_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb888[8]\(1),
I1 => \^co\(0),
I2 => \rgb888[13]\(0),
O => \cb_int[3]_i_17_n_0\
);
\cb_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_33_n_4\,
O => \cb_int[3]_i_18_n_0\
);
\cb_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[3]_i_9_n_0\,
I1 => \cb_int[3]_i_10_n_0\,
I2 => cb_int_reg2(2),
O => \cb_int[3]_i_2_n_0\
);
\cb_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[3]_i_22_n_0\
);
\cb_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[3]_i_23_n_0\
);
\cb_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[3]_i_24_n_0\
);
\cb_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_5\,
O => \cb_int[3]_i_25_n_0\
);
\cb_int[3]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
O => \cb_int[3]_i_27_n_0\
);
\cb_int[3]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
I1 => rgb888(22),
O => \cb_int[3]_i_28_n_0\
);
\cb_int[3]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => \cb_int_reg[3]_i_57_n_4\,
O => \cb_int[3]_i_29_n_0\
);
\cb_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[3]_i_12_n_0\,
I1 => \cb_int[3]_i_13_n_0\,
I2 => cb_int_reg2(1),
O => \cb_int[3]_i_3_n_0\
);
\cb_int[3]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => \cb_int_reg[3]_i_57_n_5\,
O => \cb_int[3]_i_30_n_0\
);
\cb_int[3]_i_31\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => \cb_int_reg[3]_i_57_n_6\,
O => \cb_int[3]_i_31_n_0\
);
\cb_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DFF001D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
I3 => \cb_int[3]_i_17_n_0\,
I4 => \cb_int[3]_i_18_n_0\,
O => \cb_int[3]_i_4_n_0\
);
\cb_int[3]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(2),
I1 => rgb888(1),
I2 => \rgb888[0]_8\(1),
O => \cb_int[3]_i_45_n_0\
);
\cb_int[3]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb888[0]_8\(0),
I1 => rgb888(1),
O => \cb_int[3]_i_46_n_0\
);
\cb_int[3]_i_47\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_4\,
I1 => rgb888(0),
O => \cb_int[3]_i_47_n_0\
);
\cb_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_5\,
O => \cb_int[3]_i_48_n_0\
);
\cb_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_6\,
O => \cb_int[3]_i_49_n_0\
);
\cb_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_16_n_0\,
I1 => \cb_int[7]_i_17_n_0\,
I2 => cb_int_reg2(3),
I3 => \cb_int[3]_i_2_n_0\,
O => \cb_int[3]_i_5_n_0\
);
\cb_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_6\,
O => \cb_int[3]_i_50_n_0\
);
\cb_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_7\,
O => \cb_int[3]_i_51_n_0\
);
\cb_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_4\,
O => \cb_int[3]_i_52_n_0\
);
\cb_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_5\,
O => \cb_int[3]_i_53_n_0\
);
\cb_int[3]_i_54\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => \cb_int_reg[3]_i_57_n_7\,
O => \cb_int[3]_i_54_n_0\
);
\cb_int[3]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(17),
I1 => rgb888(16),
O => \cb_int[3]_i_55_n_0\
);
\cb_int[3]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(16),
O => \cb_int[3]_i_56_n_0\
);
\cb_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[3]_i_9_n_0\,
I1 => \cb_int[3]_i_10_n_0\,
I2 => cb_int_reg2(2),
I3 => \cb_int[3]_i_3_n_0\,
O => \cb_int[3]_i_6_n_0\
);
\cb_int[3]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[3]_i_64_n_0\
);
\cb_int[3]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_6\,
O => \cb_int[3]_i_65_n_0\
);
\cb_int[3]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_7\,
O => \cb_int[3]_i_66_n_0\
);
\cb_int[3]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_6\,
O => \cb_int[3]_i_67_n_0\
);
\cb_int[3]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
I2 => \rgb888[8]_31\(2),
O => \cb_int[3]_i_69_n_0\
);
\cb_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[3]_i_12_n_0\,
I1 => \cb_int[3]_i_13_n_0\,
I2 => cb_int_reg2(1),
I3 => \cb_int[3]_i_4_n_0\,
O => \cb_int[3]_i_7_n_0\
);
\cb_int[3]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_31\(1),
I1 => rgb888(9),
O => \cb_int[3]_i_70_n_0\
);
\cb_int[3]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_31\(0),
I1 => rgb888(8),
O => \cb_int[3]_i_71_n_0\
);
\cb_int[3]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_4\,
O => \cb_int[3]_i_72_n_0\
);
\cb_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \cb_int[3]_i_76_n_0\
);
\cb_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \cb_int[3]_i_77_n_0\
);
\cb_int[3]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \cb_int[3]_i_78_n_0\
);
\cb_int[3]_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \cb_int[3]_i_79_n_0\
);
\cb_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DE2E21D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
I3 => \cb_int[3]_i_17_n_0\,
I4 => \cb_int[3]_i_18_n_0\,
O => \cb_int[3]_i_8_n_0\
);
\cb_int[3]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
O => \cb_int[3]_i_80_n_0\
);
\cb_int[3]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => rgb888(17),
O => \cb_int[3]_i_81_n_0\
);
\cb_int[3]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => rgb888(16),
O => \cb_int[3]_i_82_n_0\
);
\cb_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(17),
O => \cb_int[3]_i_83_n_0\
);
\cb_int[3]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_7\,
O => \cb_int[3]_i_89_n_0\
);
\cb_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(10),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_6\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(2),
O => \cb_int[3]_i_9_n_0\
);
\cb_int[3]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_7\,
O => \cb_int[3]_i_90_n_0\
);
\cb_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_4\,
O => \cb_int[3]_i_91_n_0\
);
\cb_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_5\,
O => \cb_int[3]_i_92_n_0\
);
\cb_int[3]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_6\,
O => \cb_int[3]_i_93_n_0\
);
\cb_int[3]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \cb_int[3]_i_99_n_0\
);
\cb_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(13),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_7\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(5),
O => \cb_int[7]_i_10_n_0\
);
\cb_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(0),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(0),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(2),
O => \cb_int[7]_i_11_n_0\
);
\cb_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(5),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_7\,
O => cb_int_reg2(5)
);
\cb_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(12),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_4\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(4),
O => \cb_int[7]_i_13_n_0\
);
\cb_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(3),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(3),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(1),
O => \cb_int[7]_i_14_n_0\
);
\cb_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(4),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_4\,
O => cb_int_reg2(4)
);
\cb_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(11),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_5\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(3),
O => \cb_int[7]_i_16_n_0\
);
\cb_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(2),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(2),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(0),
O => \cb_int[7]_i_17_n_0\
);
\cb_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(3),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_5\,
O => cb_int_reg2(3)
);
\cb_int[7]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0BF"
)
port map (
I0 => cb_int_reg8,
I1 => cb_int_reg7(15),
I2 => \cb_int_reg[31]_i_12_n_1\,
I3 => cb_int_reg5(7),
O => \cb_int[7]_i_19_n_0\
);
\cb_int[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"5959A959"
)
port map (
I0 => \cb_int[11]_i_19_n_0\,
I1 => cb_int_reg5(7),
I2 => \cb_int_reg[31]_i_12_n_1\,
I3 => cb_int_reg7(15),
I4 => cb_int_reg8,
O => \cb_int[7]_i_2_n_0\
);
\cb_int[7]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(6),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_6\,
O => cb_int_reg2(6)
);
\cb_int[7]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(1),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(1),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(3),
O => \cb_int[7]_i_21_n_0\
);
\cb_int[7]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(14),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_6\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(6),
O => \cb_int[7]_i_22_n_0\
);
\cb_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_10_n_0\,
I1 => \cb_int[7]_i_11_n_0\,
I2 => cb_int_reg2(5),
O => \cb_int[7]_i_3_n_0\
);
\cb_int[7]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_39_n_0\
);
\cb_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_13_n_0\,
I1 => \cb_int[7]_i_14_n_0\,
I2 => cb_int_reg2(4),
O => \cb_int[7]_i_4_n_0\
);
\cb_int[7]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_40_n_0\
);
\cb_int[7]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_41_n_0\
);
\cb_int[7]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_42_n_0\
);
\cb_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_16_n_0\,
I1 => \cb_int[7]_i_17_n_0\,
I2 => cb_int_reg2(3),
O => \cb_int[7]_i_5_n_0\
);
\cb_int[7]_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[3]_i_33_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[7]_i_52_n_0\
);
\cb_int[7]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(2),
O => \cb_int[7]_i_53_n_0\
);
\cb_int[7]_i_54\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(1),
O => \cb_int[7]_i_54_n_0\
);
\cb_int[7]_i_55\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_6\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(0),
O => \cb_int[7]_i_55_n_0\
);
\cb_int[7]_i_56\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_7\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[7]_i_56_n_0\
);
\cb_int[7]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(2),
O => \cb_int[7]_i_57_n_0\
);
\cb_int[7]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(1),
O => \cb_int[7]_i_58_n_0\
);
\cb_int[7]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(0),
O => \cb_int[7]_i_59_n_0\
);
\cb_int[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => \cb_int[7]_i_19_n_0\,
I1 => \cb_int[11]_i_19_n_0\,
I2 => cb_int_reg2(6),
I3 => \cb_int[7]_i_21_n_0\,
I4 => \cb_int[7]_i_22_n_0\,
O => \cb_int[7]_i_6_n_0\
);
\cb_int[7]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[7]_i_60_n_0\
);
\cb_int[7]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_62_n_0\
);
\cb_int[7]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_63_n_0\
);
\cb_int[7]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_64_n_0\
);
\cb_int[7]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_65_n_0\
);
\cb_int[7]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_0\(3),
I1 => \rgb888[8]_1\(0),
O => \cb_int[7]_i_67_n_0\
);
\cb_int[7]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_0\(1),
I1 => \rgb888[8]_0\(2),
O => \cb_int[7]_i_68_n_0\
);
\cb_int[7]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]\(3),
I1 => \rgb888[8]_0\(0),
O => \cb_int[7]_i_69_n_0\
);
\cb_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_3_n_0\,
I1 => cb_int_reg2(6),
I2 => \cb_int[7]_i_21_n_0\,
I3 => \cb_int[7]_i_22_n_0\,
O => \cb_int[7]_i_7_n_0\
);
\cb_int[7]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]\(1),
I1 => \rgb888[8]\(2),
O => \cb_int[7]_i_70_n_0\
);
\cb_int[7]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(0),
I1 => \rgb888[8]_0\(3),
O => \cb_int[7]_i_71_n_0\
);
\cb_int[7]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_0\(2),
I1 => \rgb888[8]_0\(1),
O => \cb_int[7]_i_72_n_0\
);
\cb_int[7]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_0\(0),
I1 => \rgb888[8]\(3),
O => \cb_int[7]_i_73_n_0\
);
\cb_int[7]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]\(2),
I1 => \rgb888[8]\(1),
O => \cb_int[7]_i_74_n_0\
);
\cb_int[7]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cb_int_reg[3]_0\(3),
I1 => \rgb888[8]\(0),
O => \cb_int[7]_i_75_n_0\
);
\cb_int[7]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cb_int_reg[3]_0\(1),
I1 => \^cb_int_reg[3]_0\(2),
O => \cb_int[7]_i_76_n_0\
);
\cb_int[7]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^o\(1),
I1 => \^cb_int_reg[3]_0\(0),
O => \cb_int[7]_i_77_n_0\
);
\cb_int[7]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(8),
I1 => \^o\(0),
O => \cb_int[7]_i_78_n_0\
);
\cb_int[7]_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]\(0),
I1 => \^cb_int_reg[3]_0\(3),
O => \cb_int[7]_i_79_n_0\
);
\cb_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_10_n_0\,
I1 => \cb_int[7]_i_11_n_0\,
I2 => cb_int_reg2(5),
I3 => \cb_int[7]_i_4_n_0\,
O => \cb_int[7]_i_8_n_0\
);
\cb_int[7]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cb_int_reg[3]_0\(2),
I1 => \^cb_int_reg[3]_0\(1),
O => \cb_int[7]_i_80_n_0\
);
\cb_int[7]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cb_int_reg[3]_0\(0),
I1 => \^o\(1),
O => \cb_int[7]_i_81_n_0\
);
\cb_int[7]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^o\(0),
I1 => rgb888(8),
O => \cb_int[7]_i_82_n_0\
);
\cb_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_13_n_0\,
I1 => \cb_int[7]_i_14_n_0\,
I2 => cb_int_reg2(4),
I3 => \cb_int[7]_i_5_n_0\,
O => \cb_int[7]_i_9_n_0\
);
\cb_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_7\,
Q => \cb_int_reg_n_0_[0]\,
R => '0'
);
\cb_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_5\,
Q => \cb_int_reg__0\(10),
R => '0'
);
\cb_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_4\,
Q => \cb_int_reg__0\(11),
R => '0'
);
\cb_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_1_n_0\,
CO(3) => \cb_int_reg[11]_i_1_n_0\,
CO(2) => \cb_int_reg[11]_i_1_n_1\,
CO(1) => \cb_int_reg[11]_i_1_n_2\,
CO(0) => \cb_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_2_n_0\,
DI(2) => \cb_int[11]_i_3_n_0\,
DI(1) => \cb_int[11]_i_4_n_0\,
DI(0) => \cb_int[11]_i_5_n_0\,
O(3) => \cb_int_reg[11]_i_1_n_4\,
O(2) => \cb_int_reg[11]_i_1_n_5\,
O(1) => \cb_int_reg[11]_i_1_n_6\,
O(0) => \cb_int_reg[11]_i_1_n_7\,
S(3) => \cb_int[11]_i_6_n_0\,
S(2) => \cb_int[11]_i_7_n_0\,
S(1) => \cb_int[11]_i_8_n_0\,
S(0) => \cb_int[11]_i_9_n_0\
);
\cb_int_reg[11]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_28_n_0\,
CO(3) => \cb_int_reg[11]_i_16_n_0\,
CO(2) => \cb_int_reg[11]_i_16_n_1\,
CO(1) => \cb_int_reg[11]_i_16_n_2\,
CO(0) => \cb_int_reg[11]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(8 downto 5),
S(3) => \cb_int[11]_i_29_n_0\,
S(2) => \cb_int[11]_i_30_n_0\,
S(1) => \cb_int[11]_i_31_n_0\,
S(0) => \cb_int[11]_i_32_n_0\
);
\cb_int_reg[11]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_33_n_0\,
CO(3) => \cb_int_reg[11]_i_17_n_0\,
CO(2) => \cb_int_reg[11]_i_17_n_1\,
CO(1) => \cb_int_reg[11]_i_17_n_2\,
CO(0) => \cb_int_reg[11]_i_17_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(18 downto 15),
S(3) => \cb_int[11]_i_34_n_0\,
S(2) => \cb_int[11]_i_35_n_0\,
S(1) => \cb_int[11]_i_36_n_0\,
S(0) => \cb_int[11]_i_37_n_0\
);
\cb_int_reg[11]_i_18\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_38_n_0\,
CO(3) => \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\(3),
CO(2) => cb_int_reg8,
CO(1) => \cb_int_reg[11]_i_18_n_2\,
CO(0) => \cb_int_reg[11]_i_18_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cb_int[11]_i_39_n_0\,
DI(0) => \cb_int[11]_i_40_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\(3 downto 0),
S(3) => '0',
S(2) => \cb_int[11]_i_41_n_0\,
S(1) => \cb_int[11]_i_42_n_0\,
S(0) => \cb_int[11]_i_43_n_0\
);
\cb_int_reg[11]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_29_n_0\,
CO(3) => \cb_int_reg[15]_0\(0),
CO(2) => \cb_int_reg[11]_i_24_n_1\,
CO(1) => \cb_int_reg[11]_i_24_n_2\,
CO(0) => \cb_int_reg[11]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[11]_i_24_n_4\,
O(2) => \cb_int_reg[11]_i_24_n_5\,
O(1) => \cb_int_reg[11]_i_24_n_6\,
O(0) => \cb_int_reg[11]_i_24_n_7\,
S(3) => \cb_int[11]_i_44_n_0\,
S(2) => \cb_int[11]_i_45_n_0\,
S(1) => \cb_int[11]_i_46_n_0\,
S(0) => \cb_int[11]_i_47_n_0\
);
\cb_int_reg[11]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_48_n_0\,
CO(3) => \cb_int_reg[11]_i_25_n_0\,
CO(2) => \cb_int_reg[11]_i_25_n_1\,
CO(1) => \cb_int_reg[11]_i_25_n_2\,
CO(0) => \cb_int_reg[11]_i_25_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[0]\(3),
DI(1) => \rgb888[0]\(3),
DI(0) => \rgb888[0]\(3),
O(3 downto 0) => \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_49_n_0\,
S(2) => \cb_int[11]_i_50_n_0\,
S(1) => \cb_int[11]_i_51_n_0\,
S(0) => \cb_int[11]_i_52_n_0\
);
\cb_int_reg[11]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_28_n_0\,
CO(3) => \cb_int_reg[11]_i_26_n_0\,
CO(2) => \cb_int_reg[11]_i_26_n_1\,
CO(1) => \cb_int_reg[11]_i_26_n_2\,
CO(0) => \cb_int_reg[11]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(8 downto 5),
S(3) => \cb_int[11]_i_53_n_0\,
S(2) => \cb_int[11]_i_54_n_0\,
S(1) => \cb_int[11]_i_55_n_0\,
S(0) => \cb_int[11]_i_56_n_0\
);
\cb_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_28_n_0\,
CO(2) => \cb_int_reg[11]_i_28_n_1\,
CO(1) => \cb_int_reg[11]_i_28_n_2\,
CO(0) => \cb_int_reg[11]_i_28_n_3\,
CYINIT => \cb_int[11]_i_57_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(4 downto 1),
S(3) => \cb_int[11]_i_58_n_0\,
S(2) => \cb_int[11]_i_59_n_0\,
S(1) => \cb_int[11]_i_60_n_0\,
S(0) => \cb_int[11]_i_61_n_0\
);
\cb_int_reg[11]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_15_n_0\,
CO(3) => \cb_int_reg[11]_i_33_n_0\,
CO(2) => \cb_int_reg[11]_i_33_n_1\,
CO(1) => \cb_int_reg[11]_i_33_n_2\,
CO(0) => \cb_int_reg[11]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(14 downto 11),
S(3) => \cb_int[11]_i_62_n_0\,
S(2) => \cb_int[11]_i_63_n_0\,
S(1) => \cb_int[11]_i_64_n_0\,
S(0) => \cb_int[11]_i_65_n_0\
);
\cb_int_reg[11]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_66_n_0\,
CO(3) => \cb_int_reg[11]_i_38_n_0\,
CO(2) => \cb_int_reg[11]_i_38_n_1\,
CO(1) => \cb_int_reg[11]_i_38_n_2\,
CO(0) => \cb_int_reg[11]_i_38_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_67_n_0\,
DI(2) => \cb_int[11]_i_68_n_0\,
DI(1) => \cb_int[11]_i_69_n_0\,
DI(0) => \cb_int[11]_i_70_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_71_n_0\,
S(2) => \cb_int[11]_i_72_n_0\,
S(1) => \cb_int[11]_i_73_n_0\,
S(0) => \cb_int[11]_i_74_n_0\
);
\cb_int_reg[11]_i_48\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_75_n_0\,
CO(3) => \cb_int_reg[11]_i_48_n_0\,
CO(2) => \cb_int_reg[11]_i_48_n_1\,
CO(1) => \cb_int_reg[11]_i_48_n_2\,
CO(0) => \cb_int_reg[11]_i_48_n_3\,
CYINIT => '0',
DI(3) => \rgb888[0]\(3),
DI(2) => \rgb888[0]\(3),
DI(1) => \rgb888[0]\(3),
DI(0) => \cb_int[11]_i_76_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_77_n_0\,
S(2) => \cb_int[11]_i_78_n_0\,
S(1) => \cb_int[11]_i_79_n_0\,
S(0) => \cb_int[11]_i_80_n_0\
);
\cb_int_reg[11]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_81_n_0\,
CO(3) => \cb_int_reg[11]_i_66_n_0\,
CO(2) => \cb_int_reg[11]_i_66_n_1\,
CO(1) => \cb_int_reg[11]_i_66_n_2\,
CO(0) => \cb_int_reg[11]_i_66_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_82_n_0\,
DI(2) => \cb_int[11]_i_83_n_0\,
DI(1) => \cb_int[11]_i_84_n_0\,
DI(0) => \cb_int[11]_i_85_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_86_n_0\,
S(2) => \cb_int[11]_i_87_n_0\,
S(1) => \cb_int[11]_i_88_n_0\,
S(0) => \cb_int[11]_i_89_n_0\
);
\cb_int_reg[11]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_90_n_0\,
CO(3) => \cb_int_reg[11]_i_75_n_0\,
CO(2) => \cb_int_reg[11]_i_75_n_1\,
CO(1) => \cb_int_reg[11]_i_75_n_2\,
CO(0) => \cb_int_reg[11]_i_75_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_91_n_0\,
DI(2) => \cb_int[11]_i_92_n_0\,
DI(1) => \cb_int[11]_i_93_n_0\,
DI(0) => \cb_int[11]_i_94_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_95_n_0\,
S(2) => \cb_int[11]_i_96_n_0\,
S(1) => \cb_int[11]_i_97_n_0\,
S(0) => \cb_int[11]_i_98_n_0\
);
\cb_int_reg[11]_i_81\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_81_n_0\,
CO(2) => \cb_int_reg[11]_i_81_n_1\,
CO(1) => \cb_int_reg[11]_i_81_n_2\,
CO(0) => \cb_int_reg[11]_i_81_n_3\,
CYINIT => '1',
DI(3) => \cb_int[11]_i_99_n_0\,
DI(2) => \cb_int[11]_i_100_n_0\,
DI(1) => \cb_int[11]_i_101_n_0\,
DI(0) => \cb_int[11]_i_102_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_103_n_0\,
S(2) => \cb_int[11]_i_104_n_0\,
S(1) => \cb_int[11]_i_105_n_0\,
S(0) => \cb_int[11]_i_106_n_0\
);
\cb_int_reg[11]_i_90\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_90_n_0\,
CO(2) => \cb_int_reg[11]_i_90_n_1\,
CO(1) => \cb_int_reg[11]_i_90_n_2\,
CO(0) => \cb_int_reg[11]_i_90_n_3\,
CYINIT => '1',
DI(3) => \cb_int[11]_i_107_n_0\,
DI(2) => \cb_int[11]_i_108_n_0\,
DI(1) => \cb_int[11]_i_109_n_0\,
DI(0) => \cb_int[11]_i_110_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_111_n_0\,
S(2) => \cb_int[11]_i_112_n_0\,
S(1) => \cb_int[11]_i_113_n_0\,
S(0) => \cb_int[11]_i_114_n_0\
);
\cb_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_7\,
Q => \cb_int_reg__0\(12),
R => '0'
);
\cb_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_6\,
Q => \cb_int_reg__0\(13),
R => '0'
);
\cb_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_5\,
Q => \cb_int_reg__0\(14),
R => '0'
);
\cb_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_4\,
Q => \cb_int_reg__0\(15),
R => '0'
);
\cb_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_1_n_0\,
CO(3) => \cb_int_reg[15]_i_1_n_0\,
CO(2) => \cb_int_reg[15]_i_1_n_1\,
CO(1) => \cb_int_reg[15]_i_1_n_2\,
CO(0) => \cb_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[15]_i_2_n_0\,
DI(2) => \cb_int[15]_i_3_n_0\,
DI(1) => \cb_int[15]_i_4_n_0\,
DI(0) => \cb_int[15]_i_5_n_0\,
O(3) => \cb_int_reg[15]_i_1_n_4\,
O(2) => \cb_int_reg[15]_i_1_n_5\,
O(1) => \cb_int_reg[15]_i_1_n_6\,
O(0) => \cb_int_reg[15]_i_1_n_7\,
S(3) => \cb_int[15]_i_6_n_0\,
S(2) => \cb_int[15]_i_7_n_0\,
S(1) => \cb_int[15]_i_8_n_0\,
S(0) => \cb_int[15]_i_9_n_0\
);
\cb_int_reg[15]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_16_n_0\,
CO(3) => \cb_int_reg[15]_i_20_n_0\,
CO(2) => \cb_int_reg[15]_i_20_n_1\,
CO(1) => \cb_int_reg[15]_i_20_n_2\,
CO(0) => \cb_int_reg[15]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(12 downto 9),
S(3) => \cb_int[15]_i_27_n_0\,
S(2) => \cb_int[15]_i_28_n_0\,
S(1) => \cb_int[15]_i_29_n_0\,
S(0) => \cb_int[15]_i_30_n_0\
);
\cb_int_reg[15]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_26_n_0\,
CO(3) => \cb_int_reg[15]_i_33_n_0\,
CO(2) => \cb_int_reg[15]_i_33_n_1\,
CO(1) => \cb_int_reg[15]_i_33_n_2\,
CO(0) => \cb_int_reg[15]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(12 downto 9),
S(3) => \cb_int[15]_i_43_n_0\,
S(2) => \cb_int[15]_i_44_n_0\,
S(1) => \cb_int[15]_i_45_n_0\,
S(0) => \cb_int[15]_i_46_n_0\
);
\cb_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_7\,
Q => \cb_int_reg__0\(16),
R => '0'
);
\cb_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_6\,
Q => \cb_int_reg__0\(17),
R => '0'
);
\cb_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_5\,
Q => \cb_int_reg__0\(18),
R => '0'
);
\cb_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_4\,
Q => \cb_int_reg__0\(19),
R => '0'
);
\cb_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_1_n_0\,
CO(3) => \cb_int_reg[19]_i_1_n_0\,
CO(2) => \cb_int_reg[19]_i_1_n_1\,
CO(1) => \cb_int_reg[19]_i_1_n_2\,
CO(0) => \cb_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[19]_i_2_n_0\,
DI(2) => \cb_int[19]_i_3_n_0\,
DI(1) => \cb_int[19]_i_4_n_0\,
DI(0) => \cb_int[19]_i_5_n_0\,
O(3) => \cb_int_reg[19]_i_1_n_4\,
O(2) => \cb_int_reg[19]_i_1_n_5\,
O(1) => \cb_int_reg[19]_i_1_n_6\,
O(0) => \cb_int_reg[19]_i_1_n_7\,
S(3) => \cb_int[19]_i_6_n_0\,
S(2) => \cb_int[19]_i_7_n_0\,
S(1) => \cb_int[19]_i_8_n_0\,
S(0) => \cb_int[19]_i_9_n_0\
);
\cb_int_reg[19]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_20_n_0\,
CO(3) => \cb_int_reg[19]_i_20_n_0\,
CO(2) => \cb_int_reg[19]_i_20_n_1\,
CO(1) => \cb_int_reg[19]_i_20_n_2\,
CO(0) => \cb_int_reg[19]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(16 downto 13),
S(3) => \cb_int[19]_i_28_n_0\,
S(2) => \cb_int[19]_i_29_n_0\,
S(1) => \cb_int[19]_i_30_n_0\,
S(0) => \cb_int[19]_i_31_n_0\
);
\cb_int_reg[19]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_17_n_0\,
CO(3) => \cb_int_reg[19]_i_25_n_0\,
CO(2) => \cb_int_reg[19]_i_25_n_1\,
CO(1) => \cb_int_reg[19]_i_25_n_2\,
CO(0) => \cb_int_reg[19]_i_25_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(22 downto 19),
S(3) => \cb_int[19]_i_34_n_0\,
S(2) => \cb_int[19]_i_35_n_0\,
S(1) => \cb_int[19]_i_36_n_0\,
S(0) => \cb_int[19]_i_37_n_0\
);
\cb_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_6\,
Q => \cb_int_reg_n_0_[1]\,
R => '0'
);
\cb_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_7\,
Q => \cb_int_reg__0\(20),
R => '0'
);
\cb_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_6\,
Q => \cb_int_reg__0\(21),
R => '0'
);
\cb_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_5\,
Q => \cb_int_reg__0\(22),
R => '0'
);
\cb_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_4\,
Q => \cb_int_reg__0\(23),
R => '0'
);
\cb_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_1_n_0\,
CO(3) => \cb_int_reg[23]_i_1_n_0\,
CO(2) => \cb_int_reg[23]_i_1_n_1\,
CO(1) => \cb_int_reg[23]_i_1_n_2\,
CO(0) => \cb_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[23]_i_2_n_0\,
DI(2) => \cb_int[23]_i_3_n_0\,
DI(1) => \cb_int[23]_i_4_n_0\,
DI(0) => \cb_int[23]_i_5_n_0\,
O(3) => \cb_int_reg[23]_i_1_n_4\,
O(2) => \cb_int_reg[23]_i_1_n_5\,
O(1) => \cb_int_reg[23]_i_1_n_6\,
O(0) => \cb_int_reg[23]_i_1_n_7\,
S(3) => \cb_int[23]_i_6_n_0\,
S(2) => \cb_int[23]_i_7_n_0\,
S(1) => \cb_int[23]_i_8_n_0\,
S(0) => \cb_int[23]_i_9_n_0\
);
\cb_int_reg[23]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_25_n_0\,
CO(3) => \cb_int_reg[23]_i_24_n_0\,
CO(2) => \cb_int_reg[23]_i_24_n_1\,
CO(1) => \cb_int_reg[23]_i_24_n_2\,
CO(0) => \cb_int_reg[23]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(26 downto 23),
S(3) => \cb_int[23]_i_29_n_0\,
S(2) => \cb_int[23]_i_30_n_0\,
S(1) => \cb_int[23]_i_31_n_0\,
S(0) => \cb_int[23]_i_32_n_0\
);
\cb_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_7\,
Q => \cb_int_reg__0\(24),
R => '0'
);
\cb_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_6\,
Q => \cb_int_reg__0\(25),
R => '0'
);
\cb_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_5\,
Q => \cb_int_reg__0\(26),
R => '0'
);
\cb_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_4\,
Q => \cb_int_reg__0\(27),
R => '0'
);
\cb_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_1_n_0\,
CO(3) => \cb_int_reg[27]_i_1_n_0\,
CO(2) => \cb_int_reg[27]_i_1_n_1\,
CO(1) => \cb_int_reg[27]_i_1_n_2\,
CO(0) => \cb_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[31]_i_2_n_0\,
DI(2) => \cb_int[31]_i_2_n_0\,
DI(1) => \cb_int[31]_i_2_n_0\,
DI(0) => \cb_int[27]_i_2_n_0\,
O(3) => \cb_int_reg[27]_i_1_n_4\,
O(2) => \cb_int_reg[27]_i_1_n_5\,
O(1) => \cb_int_reg[27]_i_1_n_6\,
O(0) => \cb_int_reg[27]_i_1_n_7\,
S(3) => \cb_int[27]_i_3_n_0\,
S(2) => \cb_int[27]_i_4_n_0\,
S(1) => \cb_int[27]_i_5_n_0\,
S(0) => \cb_int[27]_i_6_n_0\
);
\cb_int_reg[27]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_24_n_0\,
CO(3) => \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[27]_i_9_n_1\,
CO(1) => \cb_int_reg[27]_i_9_n_2\,
CO(0) => \cb_int_reg[27]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(30 downto 27),
S(3) => \cb_int[27]_i_12_n_0\,
S(2) => \cb_int[27]_i_13_n_0\,
S(1) => \cb_int[27]_i_14_n_0\,
S(0) => \cb_int[27]_i_15_n_0\
);
\cb_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_7\,
Q => \cb_int_reg__0\(28),
R => '0'
);
\cb_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_6\,
Q => \cb_int_reg__0\(29),
R => '0'
);
\cb_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_5\,
Q => \cb_int_reg_n_0_[2]\,
R => '0'
);
\cb_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_5\,
Q => \cb_int_reg__0\(30),
R => '0'
);
\cb_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_4\,
Q => \cb_int_reg__0\(31),
R => '0'
);
\cb_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_1_n_1\,
CO(1) => \cb_int_reg[31]_i_1_n_2\,
CO(0) => \cb_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cb_int[31]_i_2_n_0\,
DI(1) => \cb_int[31]_i_2_n_0\,
DI(0) => \cb_int[31]_i_2_n_0\,
O(3) => \cb_int_reg[31]_i_1_n_4\,
O(2) => \cb_int_reg[31]_i_1_n_5\,
O(1) => \cb_int_reg[31]_i_1_n_6\,
O(0) => \cb_int_reg[31]_i_1_n_7\,
S(3) => \cb_int[31]_i_3_n_0\,
S(2) => \cb_int[31]_i_4_n_0\,
S(1) => \cb_int[31]_i_5_n_0\,
S(0) => \cb_int[31]_i_6_n_0\
);
\cb_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_11_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cb_int_reg5(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_31_n_0\,
S(0) => \cb_int[31]_i_32_n_0\
);
\cb_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_33_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cb_int_reg[31]_i_34_n_2\,
DI(0) => '0',
O(3 downto 2) => \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_12_n_6\,
O(0) => \cb_int_reg[31]_i_12_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_35_n_0\,
S(0) => \cb_int[31]_i_36_n_0\
);
\cb_int_reg[31]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_37_n_0\,
CO(3) => \cb_int_reg[31]_i_14_n_0\,
CO(2) => \cb_int_reg[31]_i_14_n_1\,
CO(1) => \cb_int_reg[31]_i_14_n_2\,
CO(0) => \cb_int_reg[31]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(20 downto 17),
S(3) => \cb_int[31]_i_38_n_0\,
S(2) => \cb_int[31]_i_39_n_0\,
S(1) => \cb_int[31]_i_40_n_0\,
S(0) => \cb_int[31]_i_41_n_0\
);
\cb_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_20_n_0\,
CO(3) => \cb_int_reg[31]_i_30_n_0\,
CO(2) => \cb_int_reg[31]_i_30_n_1\,
CO(1) => \cb_int_reg[31]_i_30_n_2\,
CO(0) => \cb_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(20 downto 17),
S(3) => \cb_int[31]_i_67_n_0\,
S(2) => \cb_int[31]_i_68_n_0\,
S(1) => \cb_int[31]_i_69_n_0\,
S(0) => \cb_int[31]_i_70_n_0\
);
\cb_int_reg[31]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_16_n_0\,
CO(3) => \cb_int_reg[31]_i_33_n_0\,
CO(2) => \cb_int_reg[31]_i_33_n_1\,
CO(1) => \cb_int_reg[31]_i_33_n_2\,
CO(0) => \cb_int_reg[31]_i_33_n_3\,
CYINIT => '0',
DI(3) => \cb_int_reg[31]_i_34_n_7\,
DI(2) => \cb_int[31]_i_71_n_0\,
DI(1) => \cb_int[31]_i_72_n_0\,
DI(0) => \cb_int_reg[31]_i_73_n_7\,
O(3) => \cb_int_reg[31]_i_33_n_4\,
O(2) => \cb_int_reg[31]_i_33_n_5\,
O(1) => \cb_int_reg[31]_i_33_n_6\,
O(0) => \cb_int_reg[31]_i_33_n_7\,
S(3) => \cb_int[31]_i_74_n_0\,
S(2) => \cb_int[31]_i_75_n_0\,
S(1) => \cb_int[31]_i_76_n_0\,
S(0) => \cb_int[31]_i_77_n_0\
);
\cb_int_reg[31]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_73_n_0\,
CO(3 downto 2) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cb_int_reg[31]_i_34_n_2\,
CO(0) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(23),
O(3 downto 1) => \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\(3 downto 1),
O(0) => \cb_int_reg[31]_i_34_n_7\,
S(3 downto 1) => B"001",
S(0) => \cb_int[31]_i_78_n_0\
);
\cb_int_reg[31]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_33_n_0\,
CO(3) => \cb_int_reg[31]_i_37_n_0\,
CO(2) => \cb_int_reg[31]_i_37_n_1\,
CO(1) => \cb_int_reg[31]_i_37_n_2\,
CO(0) => \cb_int_reg[31]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(16 downto 13),
S(3) => \cb_int[31]_i_79_n_0\,
S(2) => \cb_int[31]_i_80_n_0\,
S(1) => \cb_int[31]_i_81_n_0\,
S(0) => \cb_int[31]_i_82_n_0\
);
\cb_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_14_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_7_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cb_int_reg3(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_15_n_0\,
S(0) => \cb_int[31]_i_16_n_0\
);
\cb_int_reg[31]_i_73\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_57_n_0\,
CO(3) => \cb_int_reg[31]_i_73_n_0\,
CO(2) => \cb_int_reg[31]_i_73_n_1\,
CO(1) => \cb_int_reg[31]_i_73_n_2\,
CO(0) => \cb_int_reg[31]_i_73_n_3\,
CYINIT => '0',
DI(3) => rgb888(22),
DI(2 downto 0) => rgb888(23 downto 21),
O(3) => \cb_int_reg[31]_i_73_n_4\,
O(2) => \cb_int_reg[31]_i_73_n_5\,
O(1) => \cb_int_reg[31]_i_73_n_6\,
O(0) => \cb_int_reg[31]_i_73_n_7\,
S(3) => \cb_int[31]_i_95_n_0\,
S(2) => \cb_int[31]_i_96_n_0\,
S(1) => \cb_int[31]_i_97_n_0\,
S(0) => \cb_int[31]_i_98_n_0\
);
\cb_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_4\,
Q => \cb_int_reg_n_0_[3]\,
R => '0'
);
\cb_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_1_n_0\,
CO(2) => \cb_int_reg[3]_i_1_n_1\,
CO(1) => \cb_int_reg[3]_i_1_n_2\,
CO(0) => \cb_int_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3) => \cb_int[3]_i_2_n_0\,
DI(2) => \cb_int[3]_i_3_n_0\,
DI(1) => \cb_int[3]_i_4_n_0\,
DI(0) => '1',
O(3) => \cb_int_reg[3]_i_1_n_4\,
O(2) => \cb_int_reg[3]_i_1_n_5\,
O(1) => \cb_int_reg[3]_i_1_n_6\,
O(0) => \cb_int_reg[3]_i_1_n_7\,
S(3) => \cb_int[3]_i_5_n_0\,
S(2) => \cb_int[3]_i_6_n_0\,
S(1) => \cb_int[3]_i_7_n_0\,
S(0) => \cb_int[3]_i_8_n_0\
);
\cb_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_21_n_0\,
CO(3) => \cb_int_reg[3]_i_15_n_0\,
CO(2) => \cb_int_reg[3]_i_15_n_1\,
CO(1) => \cb_int_reg[3]_i_15_n_2\,
CO(0) => \cb_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => cb_int_reg7(10 downto 8),
O(0) => \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\(0),
S(3) => \cb_int[3]_i_22_n_0\,
S(2) => \cb_int[3]_i_23_n_0\,
S(1) => \cb_int[3]_i_24_n_0\,
S(0) => \cb_int[3]_i_25_n_0\
);
\cb_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_26_n_0\,
CO(3) => \cb_int_reg[3]_i_16_n_0\,
CO(2) => \cb_int_reg[3]_i_16_n_1\,
CO(1) => \cb_int_reg[3]_i_16_n_2\,
CO(0) => \cb_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \cb_int[3]_i_27_n_0\,
DI(2 downto 0) => rgb888(21 downto 19),
O(3) => \cb_int_reg[3]_i_16_n_4\,
O(2) => \cb_int_reg[3]_i_16_n_5\,
O(1) => \cb_int_reg[3]_i_16_n_6\,
O(0) => \cb_int_reg[3]_i_16_n_7\,
S(3) => \cb_int[3]_i_28_n_0\,
S(2) => \cb_int[3]_i_29_n_0\,
S(1) => \cb_int[3]_i_30_n_0\,
S(0) => \cb_int[3]_i_31_n_0\
);
\cb_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[27]_0\(0),
CO(2) => \cb_int_reg[3]_i_20_n_1\,
CO(1) => \cb_int_reg[3]_i_20_n_2\,
CO(0) => \cb_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 2) => \rgb888[0]_8\(1 downto 0),
DI(1) => \cb_int_reg[3]_i_44_n_4\,
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_20_n_4\,
O(2) => \cb_int_reg[3]_i_20_n_5\,
O(1) => \cb_int_reg[3]_i_20_n_6\,
O(0) => \cb_int_reg[3]_i_20_n_7\,
S(3) => \cb_int[3]_i_45_n_0\,
S(2) => \cb_int[3]_i_46_n_0\,
S(1) => \cb_int[3]_i_47_n_0\,
S(0) => \cb_int[3]_i_48_n_0\
);
\cb_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_21_n_0\,
CO(2) => \cb_int_reg[3]_i_21_n_1\,
CO(1) => \cb_int_reg[3]_i_21_n_2\,
CO(0) => \cb_int_reg[3]_i_21_n_3\,
CYINIT => \cb_int[3]_i_49_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_50_n_0\,
S(2) => \cb_int[3]_i_51_n_0\,
S(1) => \cb_int[3]_i_52_n_0\,
S(0) => \cb_int[3]_i_53_n_0\
);
\cb_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_26_n_0\,
CO(2) => \cb_int_reg[3]_i_26_n_1\,
CO(1) => \cb_int_reg[3]_i_26_n_2\,
CO(0) => \cb_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(18 downto 16),
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_26_n_4\,
O(2) => \cb_int_reg[3]_i_26_n_5\,
O(1) => \cb_int_reg[3]_i_26_n_6\,
O(0) => \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\(0),
S(3) => \cb_int[3]_i_54_n_0\,
S(2) => \cb_int[3]_i_55_n_0\,
S(1) => \cb_int[3]_i_56_n_0\,
S(0) => '0'
);
\cb_int_reg[3]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_63_n_0\,
CO(3) => \cb_int_reg[3]_i_33_n_0\,
CO(2) => \cb_int_reg[3]_i_33_n_1\,
CO(1) => \cb_int_reg[3]_i_33_n_2\,
CO(0) => \cb_int_reg[3]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[3]_i_33_n_4\,
O(2 downto 0) => \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\(2 downto 0),
S(3) => \cb_int[3]_i_64_n_0\,
S(2) => \cb_int[3]_i_65_n_0\,
S(1) => \cb_int[3]_i_66_n_0\,
S(0) => \cb_int[3]_i_67_n_0\
);
\cb_int_reg[3]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_2\(0),
CO(2) => \cb_int_reg[3]_i_34_n_1\,
CO(1) => \cb_int_reg[3]_i_34_n_2\,
CO(0) => \cb_int_reg[3]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 1) => \rgb888[8]_31\(2 downto 0),
DI(0) => '0',
O(3 downto 0) => \^cb_int_reg[3]_0\(3 downto 0),
S(3) => \cb_int[3]_i_69_n_0\,
S(2) => \cb_int[3]_i_70_n_0\,
S(1) => \cb_int[3]_i_71_n_0\,
S(0) => \cb_int[3]_i_72_n_0\
);
\cb_int_reg[3]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_75_n_0\,
CO(3) => \cb_int_reg[3]_3\(0),
CO(2) => \cb_int_reg[3]_i_44_n_1\,
CO(1) => \cb_int_reg[3]_i_44_n_2\,
CO(0) => \cb_int_reg[3]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(5 downto 2),
O(3) => \cb_int_reg[3]_i_44_n_4\,
O(2) => \cb_int_reg[3]_i_44_n_5\,
O(1) => \cb_int_reg[3]_i_44_n_6\,
O(0) => \cb_int_reg[3]_i_44_n_7\,
S(3) => \cb_int[3]_i_76_n_0\,
S(2) => \cb_int[3]_i_77_n_0\,
S(1) => \cb_int[3]_i_78_n_0\,
S(0) => \cb_int[3]_i_79_n_0\
);
\cb_int_reg[3]_i_57\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_57_n_0\,
CO(2) => \cb_int_reg[3]_i_57_n_1\,
CO(1) => \cb_int_reg[3]_i_57_n_2\,
CO(0) => \cb_int_reg[3]_i_57_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(20 downto 18),
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_57_n_4\,
O(2) => \cb_int_reg[3]_i_57_n_5\,
O(1) => \cb_int_reg[3]_i_57_n_6\,
O(0) => \cb_int_reg[3]_i_57_n_7\,
S(3) => \cb_int[3]_i_80_n_0\,
S(2) => \cb_int[3]_i_81_n_0\,
S(1) => \cb_int[3]_i_82_n_0\,
S(0) => \cb_int[3]_i_83_n_0\
);
\cb_int_reg[3]_i_63\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_63_n_0\,
CO(2) => \cb_int_reg[3]_i_63_n_1\,
CO(1) => \cb_int_reg[3]_i_63_n_2\,
CO(0) => \cb_int_reg[3]_i_63_n_3\,
CYINIT => \cb_int[3]_i_89_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_90_n_0\,
S(2) => \cb_int[3]_i_91_n_0\,
S(1) => \cb_int[3]_i_92_n_0\,
S(0) => \cb_int[3]_i_93_n_0\
);
\cb_int_reg[3]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_75_n_0\,
CO(2) => \cb_int_reg[3]_i_75_n_1\,
CO(1) => \cb_int_reg[3]_i_75_n_2\,
CO(0) => \cb_int_reg[3]_i_75_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(1 downto 0),
DI(1 downto 0) => B"01",
O(3) => \cb_int_reg[3]_i_75_n_4\,
O(2) => \cb_int_reg[3]_i_75_n_5\,
O(1) => \cb_int_reg[3]_i_75_n_6\,
O(0) => \cb_int_reg[3]_i_75_n_7\,
S(3) => \cb_int[3]_i_99_n_0\,
S(2) => \cb_int[3]_i_100_n_0\,
S(1) => \cb_int[3]_i_101_n_0\,
S(0) => \cb_int[3]_i_102_n_0\
);
\cb_int_reg[3]_i_94\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_1\(0),
CO(2) => \cb_int_reg[3]_i_94_n_1\,
CO(1) => \cb_int_reg[3]_i_94_n_2\,
CO(0) => \cb_int_reg[3]_i_94_n_3\,
CYINIT => '0',
DI(3) => rgb888(8),
DI(2 downto 0) => B"001",
O(3) => \cb_int_reg[3]_i_94_n_4\,
O(2 downto 1) => \^o\(1 downto 0),
O(0) => \cb_int_reg[3]_i_94_n_7\,
S(3) => \cb_int[3]_i_103_n_0\,
S(2) => \cb_int[3]_i_104_n_0\,
S(1) => \cb_int[3]_i_105_n_0\,
S(0) => \cb_int[3]_i_106_n_0\
);
\cb_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_7\,
Q => \cb_int_reg_n_0_[4]\,
R => '0'
);
\cb_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_6\,
Q => \cb_int_reg_n_0_[5]\,
R => '0'
);
\cb_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_5\,
Q => \cb_int_reg_n_0_[6]\,
R => '0'
);
\cb_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_4\,
Q => \cb_int_reg_n_0_[7]\,
R => '0'
);
\cb_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_1_n_0\,
CO(3) => \cb_int_reg[7]_i_1_n_0\,
CO(2) => \cb_int_reg[7]_i_1_n_1\,
CO(1) => \cb_int_reg[7]_i_1_n_2\,
CO(0) => \cb_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[7]_i_2_n_0\,
DI(2) => \cb_int[7]_i_3_n_0\,
DI(1) => \cb_int[7]_i_4_n_0\,
DI(0) => \cb_int[7]_i_5_n_0\,
O(3) => \cb_int_reg[7]_i_1_n_4\,
O(2) => \cb_int_reg[7]_i_1_n_5\,
O(1) => \cb_int_reg[7]_i_1_n_6\,
O(0) => \cb_int_reg[7]_i_1_n_7\,
S(3) => \cb_int[7]_i_6_n_0\,
S(2) => \cb_int[7]_i_7_n_0\,
S(1) => \cb_int[7]_i_8_n_0\,
S(0) => \cb_int[7]_i_9_n_0\
);
\cb_int_reg[7]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_38_n_0\,
CO(3) => \^co\(0),
CO(2) => \cb_int_reg[7]_i_25_n_1\,
CO(1) => \cb_int_reg[7]_i_25_n_2\,
CO(0) => \cb_int_reg[7]_i_25_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[8]_1\(1),
DI(1) => \rgb888[8]_1\(1),
DI(0) => \rgb888[8]_1\(1),
O(3 downto 0) => \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_39_n_0\,
S(2) => \cb_int[7]_i_40_n_0\,
S(1) => \cb_int[7]_i_41_n_0\,
S(0) => \cb_int[7]_i_42_n_0\
);
\cb_int_reg[7]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_28_n_0\,
CO(2) => \cb_int_reg[7]_i_28_n_1\,
CO(1) => \cb_int_reg[7]_i_28_n_2\,
CO(0) => \cb_int_reg[7]_i_28_n_3\,
CYINIT => \cb_int[7]_i_52_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(4 downto 1),
S(3) => \cb_int[7]_i_53_n_0\,
S(2) => \cb_int[7]_i_54_n_0\,
S(1) => \cb_int[7]_i_55_n_0\,
S(0) => \cb_int[7]_i_56_n_0\
);
\cb_int_reg[7]_i_29\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_33_n_0\,
CO(3) => \cb_int_reg[7]_i_29_n_0\,
CO(2) => \cb_int_reg[7]_i_29_n_1\,
CO(1) => \cb_int_reg[7]_i_29_n_2\,
CO(0) => \cb_int_reg[7]_i_29_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_29_n_4\,
O(2) => \cb_int_reg[7]_i_29_n_5\,
O(1) => \cb_int_reg[7]_i_29_n_6\,
O(0) => \cb_int_reg[7]_i_29_n_7\,
S(3) => \cb_int[7]_i_57_n_0\,
S(2) => \cb_int[7]_i_58_n_0\,
S(1) => \cb_int[7]_i_59_n_0\,
S(0) => \cb_int[7]_i_60_n_0\
);
\cb_int_reg[7]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_61_n_0\,
CO(3) => \cb_int_reg[7]_i_38_n_0\,
CO(2) => \cb_int_reg[7]_i_38_n_1\,
CO(1) => \cb_int_reg[7]_i_38_n_2\,
CO(0) => \cb_int_reg[7]_i_38_n_3\,
CYINIT => '0',
DI(3) => \rgb888[8]_1\(1),
DI(2) => \rgb888[8]_1\(1),
DI(1) => \rgb888[8]_1\(1),
DI(0) => \rgb888[8]_1\(1),
O(3 downto 0) => \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_62_n_0\,
S(2) => \cb_int[7]_i_63_n_0\,
S(1) => \cb_int[7]_i_64_n_0\,
S(0) => \cb_int[7]_i_65_n_0\
);
\cb_int_reg[7]_i_61\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_66_n_0\,
CO(3) => \cb_int_reg[7]_i_61_n_0\,
CO(2) => \cb_int_reg[7]_i_61_n_1\,
CO(1) => \cb_int_reg[7]_i_61_n_2\,
CO(0) => \cb_int_reg[7]_i_61_n_3\,
CYINIT => '0',
DI(3) => \cb_int[7]_i_67_n_0\,
DI(2) => \cb_int[7]_i_68_n_0\,
DI(1) => \cb_int[7]_i_69_n_0\,
DI(0) => \cb_int[7]_i_70_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_71_n_0\,
S(2) => \cb_int[7]_i_72_n_0\,
S(1) => \cb_int[7]_i_73_n_0\,
S(0) => \cb_int[7]_i_74_n_0\
);
\cb_int_reg[7]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_66_n_0\,
CO(2) => \cb_int_reg[7]_i_66_n_1\,
CO(1) => \cb_int_reg[7]_i_66_n_2\,
CO(0) => \cb_int_reg[7]_i_66_n_3\,
CYINIT => '1',
DI(3) => \cb_int[7]_i_75_n_0\,
DI(2) => \cb_int[7]_i_76_n_0\,
DI(1) => \cb_int[7]_i_77_n_0\,
DI(0) => \cb_int[7]_i_78_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_79_n_0\,
S(2) => \cb_int[7]_i_80_n_0\,
S(1) => \cb_int[7]_i_81_n_0\,
S(0) => \cb_int[7]_i_82_n_0\
);
\cb_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_7\,
Q => \cb_int_reg__0\(8),
R => '0'
);
\cb_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_6\,
Q => \cb_int_reg__0\(9),
R => '0'
);
\cb_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[0]_i_1_n_0\,
Q => cb(0),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[1]_i_1_n_0\,
Q => cb(1),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[2]_i_1_n_0\,
Q => cb(2),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[3]_i_1_n_0\,
Q => cb(3),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[4]_i_1_n_0\,
Q => cb(4),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[5]_i_1_n_0\,
Q => cb(5),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[6]_i_1_n_0\,
Q => cb(6),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[7]_i_2_n_0\,
Q => cb(7),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_reg[7]_i_3_n_0\,
CO(3) => \cb_reg[7]_i_1_n_0\,
CO(2) => \cb_reg[7]_i_1_n_1\,
CO(1) => \cb_reg[7]_i_1_n_2\,
CO(0) => \cb_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_4_n_0\,
DI(2) => \cb[7]_i_5_n_0\,
DI(1) => \cb[7]_i_6_n_0\,
DI(0) => \cb[7]_i_7_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_8_n_0\,
S(2) => \cb[7]_i_9_n_0\,
S(1) => \cb[7]_i_10_n_0\,
S(0) => \cb[7]_i_11_n_0\
);
\cb_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_reg[7]_i_12_n_0\,
CO(2) => \cb_reg[7]_i_12_n_1\,
CO(1) => \cb_reg[7]_i_12_n_2\,
CO(0) => \cb_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_21_n_0\,
DI(2) => \cb[7]_i_22_n_0\,
DI(1) => \cb[7]_i_23_n_0\,
DI(0) => \cb[7]_i_24_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_25_n_0\,
S(2) => \cb[7]_i_26_n_0\,
S(1) => \cb[7]_i_27_n_0\,
S(0) => \cb[7]_i_28_n_0\
);
\cb_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \cb_reg[7]_i_12_n_0\,
CO(3) => \cb_reg[7]_i_3_n_0\,
CO(2) => \cb_reg[7]_i_3_n_1\,
CO(1) => \cb_reg[7]_i_3_n_2\,
CO(0) => \cb_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_13_n_0\,
DI(2) => \cb[7]_i_14_n_0\,
DI(1) => \cb[7]_i_15_n_0\,
DI(0) => \cb[7]_i_16_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_17_n_0\,
S(2) => \cb[7]_i_18_n_0\,
S(1) => \cb[7]_i_19_n_0\,
S(0) => \cb[7]_i_20_n_0\
);
cb_regi_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk,
O => cb_regn_0_0
);
\cr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[0]\,
I1 => \cr_int_reg__0\(31),
O => \cr[0]_i_1_n_0\
);
\cr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[1]\,
I1 => \cr_int_reg__0\(31),
O => \cr[1]_i_1_n_0\
);
\cr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[2]\,
I1 => \cr_int_reg__0\(31),
O => \cr[2]_i_1_n_0\
);
\cr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[3]\,
I1 => \cr_int_reg__0\(31),
O => \cr[3]_i_1_n_0\
);
\cr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[4]\,
I1 => \cr_int_reg__0\(31),
O => \cr[4]_i_1_n_0\
);
\cr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[5]\,
I1 => \cr_int_reg__0\(31),
O => \cr[5]_i_1_n_0\
);
\cr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[6]\,
I1 => \cr_int_reg__0\(31),
O => \cr[6]_i_1_n_0\
);
\cr[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(26),
I1 => \cr_int_reg__0\(27),
O => \cr[7]_i_10_n_0\
);
\cr[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(24),
I1 => \cr_int_reg__0\(25),
O => \cr[7]_i_11_n_0\
);
\cr[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(22),
I1 => \cr_int_reg__0\(23),
O => \cr[7]_i_13_n_0\
);
\cr[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(20),
I1 => \cr_int_reg__0\(21),
O => \cr[7]_i_14_n_0\
);
\cr[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(18),
I1 => \cr_int_reg__0\(19),
O => \cr[7]_i_15_n_0\
);
\cr[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(16),
I1 => \cr_int_reg__0\(17),
O => \cr[7]_i_16_n_0\
);
\cr[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(22),
I1 => \cr_int_reg__0\(23),
O => \cr[7]_i_17_n_0\
);
\cr[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(20),
I1 => \cr_int_reg__0\(21),
O => \cr[7]_i_18_n_0\
);
\cr[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(18),
I1 => \cr_int_reg__0\(19),
O => \cr[7]_i_19_n_0\
);
\cr[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[7]\,
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_2_n_0\
);
\cr[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(16),
I1 => \cr_int_reg__0\(17),
O => \cr[7]_i_20_n_0\
);
\cr[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(14),
I1 => \cr_int_reg__0\(15),
O => \cr[7]_i_21_n_0\
);
\cr[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(12),
I1 => \cr_int_reg__0\(13),
O => \cr[7]_i_22_n_0\
);
\cr[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(10),
I1 => \cr_int_reg__0\(11),
O => \cr[7]_i_23_n_0\
);
\cr[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(8),
I1 => \cr_int_reg__0\(9),
O => \cr[7]_i_24_n_0\
);
\cr[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(14),
I1 => \cr_int_reg__0\(15),
O => \cr[7]_i_25_n_0\
);
\cr[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(12),
I1 => \cr_int_reg__0\(13),
O => \cr[7]_i_26_n_0\
);
\cr[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(10),
I1 => \cr_int_reg__0\(11),
O => \cr[7]_i_27_n_0\
);
\cr[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(8),
I1 => \cr_int_reg__0\(9),
O => \cr[7]_i_28_n_0\
);
\cr[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg__0\(30),
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_4_n_0\
);
\cr[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(28),
I1 => \cr_int_reg__0\(29),
O => \cr[7]_i_5_n_0\
);
\cr[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(26),
I1 => \cr_int_reg__0\(27),
O => \cr[7]_i_6_n_0\
);
\cr[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(24),
I1 => \cr_int_reg__0\(25),
O => \cr[7]_i_7_n_0\
);
\cr[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(30),
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_8_n_0\
);
\cr[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(28),
I1 => \cr_int_reg__0\(29),
O => \cr[7]_i_9_n_0\
);
\cr_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(0),
Q => \cr_hold_reg_n_0_[0]\,
R => '0'
);
\cr_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(1),
Q => \cr_hold_reg_n_0_[1]\,
R => '0'
);
\cr_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(2),
Q => \cr_hold_reg_n_0_[2]\,
R => '0'
);
\cr_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(3),
Q => \cr_hold_reg_n_0_[3]\,
R => '0'
);
\cr_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(4),
Q => \cr_hold_reg_n_0_[4]\,
R => '0'
);
\cr_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(5),
Q => \cr_hold_reg_n_0_[5]\,
R => '0'
);
\cr_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(6),
Q => \cr_hold_reg_n_0_[6]\,
R => '0'
);
\cr_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(7),
Q => \cr_hold_reg_n_0_[7]\,
R => '0'
);
\cr_int[11]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(18),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(10),
I4 => \cr_int[15]_i_26_n_0\,
I5 => \cr_int[15]_i_27_n_0\,
O => \cr_int[11]_i_10_n_0\
);
\cr_int[11]_i_100\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(11),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_100_n_0\
);
\cr_int[11]_i_101\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(10),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_101_n_0\
);
\cr_int[11]_i_102\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(9),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_102_n_0\
);
\cr_int[11]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_104_n_0\
);
\cr_int[11]_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_105_n_0\
);
\cr_int[11]_i_106\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_106_n_0\
);
\cr_int[11]_i_107\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_107_n_0\
);
\cr_int[11]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_6\,
I1 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_109_n_0\
);
\cr_int[11]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(17),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(9),
I4 => \cr_int[11]_i_24_n_0\,
I5 => \cr_int[11]_i_25_n_0\,
O => \cr_int[11]_i_11_n_0\
);
\cr_int[11]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_4\,
I1 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_110_n_0\
);
\cr_int[11]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
I1 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_111_n_0\
);
\cr_int[11]_i_112\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_112_n_0\
);
\cr_int[11]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_5\,
I1 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_113_n_0\
);
\cr_int[11]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_7\,
I1 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_114_n_0\
);
\cr_int[11]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_5\,
I1 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[11]_i_115_n_0\
);
\cr_int[11]_i_117\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_7\,
I1 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_117_n_0\
);
\cr_int[11]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_5\,
I1 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_118_n_0\
);
\cr_int[11]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_7\,
I1 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_119_n_0\
);
\cr_int[11]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(17),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(9),
I4 => \cr_int[11]_i_24_n_0\,
I5 => \cr_int[11]_i_25_n_0\,
O => \cr_int[11]_i_12_n_0\
);
\cr_int[11]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_5\,
I1 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_120_n_0\
);
\cr_int[11]_i_121\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_6\,
I1 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_121_n_0\
);
\cr_int[11]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_4\,
I1 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_122_n_0\
);
\cr_int[11]_i_123\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_6\,
I1 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_123_n_0\
);
\cr_int[11]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_4\,
I1 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[11]_i_124_n_0\
);
\cr_int[11]_i_126\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[7]_0\(3),
I1 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_126_n_0\
);
\cr_int[11]_i_127\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[7]_0\(1),
I1 => \^cr_int_reg[7]_0\(2),
O => \cr_int[11]_i_127_n_0\
);
\cr_int[11]_i_128\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[3]_0\(2),
I1 => \^cr_int_reg[7]_0\(0),
O => \cr_int[11]_i_128_n_0\
);
\cr_int[11]_i_129\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
I1 => \^cr_int_reg[3]_0\(1),
O => \cr_int[11]_i_129_n_0\
);
\cr_int[11]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"8EEE8E888EEE8EEE"
)
port map (
I0 => \cr_int_reg3__0\(8),
I1 => \cr_int[11]_i_27_n_0\,
I2 => \cr_int_reg[11]_i_16_n_4\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_13_n_0\
);
\cr_int[11]_i_130\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(0),
I1 => \^cr_int_reg[7]_0\(3),
O => \cr_int[11]_i_130_n_0\
);
\cr_int[11]_i_131\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(2),
I1 => \^cr_int_reg[7]_0\(1),
O => \cr_int[11]_i_131_n_0\
);
\cr_int[11]_i_132\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(0),
I1 => \^cr_int_reg[3]_0\(2),
O => \cr_int[11]_i_132_n_0\
);
\cr_int[11]_i_133\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(1),
I1 => \^cr_int_reg[3]_0\(0),
O => \cr_int[11]_i_133_n_0\
);
\cr_int[11]_i_134\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_4\,
I1 => \cr_int_reg[31]_i_14_n_7\,
O => \cr_int[11]_i_134_n_0\
);
\cr_int[11]_i_135\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_6\,
I1 => \cr_int_reg[31]_i_39_n_5\,
O => \cr_int[11]_i_135_n_0\
);
\cr_int[11]_i_136\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_6\,
I1 => \cr_int_reg[31]_i_39_n_7\,
O => \cr_int[11]_i_136_n_0\
);
\cr_int[11]_i_137\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(0),
I1 => \cr_int_reg[31]_i_86_n_7\,
O => \cr_int[11]_i_137_n_0\
);
\cr_int[11]_i_138\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_7\,
I1 => \cr_int_reg[31]_i_39_n_4\,
O => \cr_int[11]_i_138_n_0\
);
\cr_int[11]_i_139\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_5\,
I1 => \cr_int_reg[31]_i_39_n_6\,
O => \cr_int[11]_i_139_n_0\
);
\cr_int[11]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999696669996999"
)
port map (
I0 => \cr_int_reg3__0\(8),
I1 => \cr_int[11]_i_27_n_0\,
I2 => \cr_int_reg[11]_i_16_n_4\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_14_n_0\
);
\cr_int[11]_i_140\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_7\,
I1 => \cr_int_reg[31]_i_86_n_6\,
O => \cr_int[11]_i_140_n_0\
);
\cr_int[11]_i_141\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_7\,
I1 => rgb888(0),
O => \cr_int[11]_i_141_n_0\
);
\cr_int[11]_i_142\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_7\,
I1 => \cr_int_reg[3]_i_16_n_6\,
O => \cr_int[11]_i_142_n_0\
);
\cr_int[11]_i_143\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_7\,
I1 => \cr_int_reg[3]_i_27_n_6\,
O => \cr_int[11]_i_143_n_0\
);
\cr_int[11]_i_144\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_5\,
I1 => \cr_int_reg[3]_i_54_n_4\,
O => \cr_int[11]_i_144_n_0\
);
\cr_int[11]_i_145\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_7\,
I1 => \cr_int_reg[3]_i_54_n_6\,
O => \cr_int[11]_i_145_n_0\
);
\cr_int[11]_i_146\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_6\,
I1 => \cr_int_reg[3]_i_16_n_7\,
O => \cr_int[11]_i_146_n_0\
);
\cr_int[11]_i_147\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_6\,
I1 => \cr_int_reg[3]_i_27_n_7\,
O => \cr_int[11]_i_147_n_0\
);
\cr_int[11]_i_148\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_4\,
I1 => \cr_int_reg[3]_i_54_n_5\,
O => \cr_int[11]_i_148_n_0\
);
\cr_int[11]_i_149\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_6\,
I1 => \cr_int_reg[3]_i_54_n_7\,
O => \cr_int[11]_i_149_n_0\
);
\cr_int[11]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[11]_0\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_15_n_0\
);
\cr_int[11]_i_150\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_4\,
I1 => \cr_int_reg[3]_i_19_n_7\,
O => \cr_int[11]_i_150_n_0\
);
\cr_int[11]_i_151\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_6\,
I1 => \cr_int_reg[3]_i_33_n_5\,
O => \cr_int[11]_i_151_n_0\
);
\cr_int[11]_i_152\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_6\,
I1 => \cr_int_reg[3]_i_65_n_5\,
I2 => rgb888(8),
O => \cr_int[11]_i_152_n_0\
);
\cr_int[11]_i_153\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_19_n_7\,
I1 => \cr_int_reg[3]_i_33_n_4\,
O => \cr_int[11]_i_153_n_0\
);
\cr_int[11]_i_154\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_5\,
I1 => \cr_int_reg[3]_i_33_n_6\,
O => \cr_int[11]_i_154_n_0\
);
\cr_int[11]_i_155\: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_65_n_5\,
I2 => \cr_int_reg[3]_i_65_n_6\,
O => \cr_int[11]_i_155_n_0\
);
\cr_int[11]_i_156\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_7\,
O => \cr_int[11]_i_156_n_0\
);
\cr_int[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[11]_i_10_n_0\,
I1 => \cr_int[11]_i_11_n_0\,
O => \cr_int[11]_i_2_n_0\
);
\cr_int[11]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"0DFDF202"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \^cr_int_reg[27]_2\(0),
I3 => \cr_int_reg[11]_i_16_n_5\,
I4 => \cr_int[11]_i_15_n_0\,
O => \cr_int[11]_i_22_n_0\
);
\cr_int[11]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0DFD"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \^cr_int_reg[27]_2\(0),
I3 => \cr_int_reg[11]_i_16_n_5\,
I4 => \cr_int[11]_i_15_n_0\,
O => \cr_int[11]_i_23_n_0\
);
\cr_int[11]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[11]_0\(3),
O => \cr_int[11]_i_24_n_0\
);
\cr_int[11]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(0),
O => \cr_int[11]_i_25_n_0\
);
\cr_int[11]_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(8),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_5\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(16),
O => \cr_int_reg3__0\(8)
);
\cr_int[11]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_13\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[11]_0\(2),
O => \cr_int[11]_i_27_n_0\
);
\cr_int[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[11]_i_12_n_0\,
I1 => \cr_int[11]_i_13_n_0\,
O => \cr_int[11]_i_3_n_0\
);
\cr_int[11]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_32_n_0\
);
\cr_int[11]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_5\,
O => \cr_int[11]_i_33_n_0\
);
\cr_int[11]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_6\,
O => \cr_int[11]_i_34_n_0\
);
\cr_int[11]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_7\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_35_n_0\
);
\cr_int[11]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_37_n_0\
);
\cr_int[11]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_38_n_0\
);
\cr_int[11]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_39_n_0\
);
\cr_int[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAA8A888AAA8AAA"
)
port map (
I0 => \cr_int[11]_i_14_n_0\,
I1 => \cr_int[11]_i_15_n_0\,
I2 => \cr_int_reg[11]_i_16_n_5\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_5\,
O => \cr_int[11]_i_4_n_0\
);
\cr_int[11]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_40_n_0\
);
\cr_int[11]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_42_n_0\
);
\cr_int[11]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_43_n_0\
);
\cr_int[11]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_44_n_0\
);
\cr_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_45_n_0\
);
\cr_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_47_n_0\
);
\cr_int[11]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_48_n_0\
);
\cr_int[11]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_49_n_0\
);
\cr_int[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE200E200000000"
)
port map (
I0 => cr_int_reg6(15),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_6\,
I3 => \cr_int_reg[31]_i_11_n_4\,
I4 => cr_int_reg4(7),
I5 => \cr_int[11]_i_22_n_0\,
O => \cr_int[11]_i_5_n_0\
);
\cr_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_50_n_0\
);
\cr_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_52_n_0\
);
\cr_int[11]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_53_n_0\
);
\cr_int[11]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_54_n_0\
);
\cr_int[11]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_55_n_0\
);
\cr_int[11]_i_57\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(16),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_57_n_0\
);
\cr_int[11]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(15),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_58_n_0\
);
\cr_int[11]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(14),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_59_n_0\
);
\cr_int[11]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_16_n_0\,
I1 => \cr_int[15]_i_17_n_0\,
I2 => \cr_int[11]_i_2_n_0\,
O => \cr_int[11]_i_6_n_0\
);
\cr_int[11]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(13),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_60_n_0\
);
\cr_int[11]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_65_n_0\
);
\cr_int[11]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_66_n_0\
);
\cr_int[11]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_67_n_0\
);
\cr_int[11]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(3),
O => \cr_int[11]_i_68_n_0\
);
\cr_int[11]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_10_n_0\,
I1 => \cr_int[11]_i_11_n_0\,
I2 => \cr_int[11]_i_3_n_0\,
O => \cr_int[11]_i_7_n_0\
);
\cr_int[11]_i_70\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_70_n_0\
);
\cr_int[11]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_71_n_0\
);
\cr_int[11]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_72_n_0\
);
\cr_int[11]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_73_n_0\
);
\cr_int[11]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[3]_i_32_n_4\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[11]_i_74_n_0\
);
\cr_int[11]_i_75\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_4\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_75_n_0\
);
\cr_int[11]_i_76\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_76_n_0\
);
\cr_int[11]_i_77\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_6\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_77_n_0\
);
\cr_int[11]_i_78\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_7\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_78_n_0\
);
\cr_int[11]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_12_n_0\,
I1 => \cr_int[11]_i_13_n_0\,
I2 => \cr_int[11]_i_4_n_0\,
O => \cr_int[11]_i_8_n_0\
);
\cr_int[11]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_80_n_0\
);
\cr_int[11]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_81_n_0\
);
\cr_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_82_n_0\
);
\cr_int[11]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_83_n_0\
);
\cr_int[11]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_84_n_0\
);
\cr_int[11]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_85_n_0\
);
\cr_int[11]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_86_n_0\
);
\cr_int[11]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_87_n_0\
);
\cr_int[11]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_88_n_0\
);
\cr_int[11]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_89_n_0\
);
\cr_int[11]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_5_n_0\,
I1 => \cr_int[11]_i_14_n_0\,
I2 => \cr_int[11]_i_23_n_0\,
O => \cr_int[11]_i_9_n_0\
);
\cr_int[11]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_90_n_0\
);
\cr_int[11]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_91_n_0\
);
\cr_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_5\,
I1 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_93_n_0\
);
\cr_int[11]_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_94_n_0\
);
\cr_int[11]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_95_n_0\
);
\cr_int[11]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_96_n_0\
);
\cr_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_97_n_0\
);
\cr_int[11]_i_98\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[11]_i_98_n_0\
);
\cr_int[11]_i_99\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(12),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_99_n_0\
);
\cr_int[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(22),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(14),
I4 => \cr_int[19]_i_26_n_0\,
I5 => \cr_int[19]_i_27_n_0\,
O => \cr_int[15]_i_10_n_0\
);
\cr_int[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(21),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(13),
I4 => \cr_int[15]_i_18_n_0\,
I5 => \cr_int[15]_i_19_n_0\,
O => \cr_int[15]_i_11_n_0\
);
\cr_int[15]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(21),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(13),
I4 => \cr_int[15]_i_18_n_0\,
I5 => \cr_int[15]_i_19_n_0\,
O => \cr_int[15]_i_12_n_0\
);
\cr_int[15]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(20),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(12),
I4 => \cr_int[15]_i_22_n_0\,
I5 => \cr_int[15]_i_23_n_0\,
O => \cr_int[15]_i_13_n_0\
);
\cr_int[15]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(20),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(12),
I4 => \cr_int[15]_i_22_n_0\,
I5 => \cr_int[15]_i_23_n_0\,
O => \cr_int[15]_i_14_n_0\
);
\cr_int[15]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(19),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(11),
I4 => \cr_int[15]_i_24_n_0\,
I5 => \cr_int[15]_i_25_n_0\,
O => \cr_int[15]_i_15_n_0\
);
\cr_int[15]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(19),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(11),
I4 => \cr_int[15]_i_24_n_0\,
I5 => \cr_int[15]_i_25_n_0\,
O => \cr_int[15]_i_16_n_0\
);
\cr_int[15]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(18),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(10),
I4 => \cr_int[15]_i_26_n_0\,
I5 => \cr_int[15]_i_27_n_0\,
O => \cr_int[15]_i_17_n_0\
);
\cr_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(3),
O => \cr_int[15]_i_18_n_0\
);
\cr_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(0),
O => \cr_int[15]_i_19_n_0\
);
\cr_int[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_10_n_0\,
I1 => \cr_int[15]_i_11_n_0\,
O => \cr_int[15]_i_2_n_0\
);
\cr_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(2),
O => \cr_int[15]_i_22_n_0\
);
\cr_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(3),
O => \cr_int[15]_i_23_n_0\
);
\cr_int[15]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(1),
O => \cr_int[15]_i_24_n_0\
);
\cr_int[15]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(2),
O => \cr_int[15]_i_25_n_0\
);
\cr_int[15]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(0),
O => \cr_int[15]_i_26_n_0\
);
\cr_int[15]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(1),
O => \cr_int[15]_i_27_n_0\
);
\cr_int[15]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_29_n_0\
);
\cr_int[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_12_n_0\,
I1 => \cr_int[15]_i_13_n_0\,
O => \cr_int[15]_i_3_n_0\
);
\cr_int[15]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_30_n_0\
);
\cr_int[15]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_31_n_0\
);
\cr_int[15]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_32_n_0\
);
\cr_int[15]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(20),
O => \cr_int[15]_i_33_n_0\
);
\cr_int[15]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(19),
O => \cr_int[15]_i_34_n_0\
);
\cr_int[15]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(18),
O => \cr_int[15]_i_35_n_0\
);
\cr_int[15]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(17),
O => \cr_int[15]_i_36_n_0\
);
\cr_int[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_14_n_0\,
I1 => \cr_int[15]_i_15_n_0\,
O => \cr_int[15]_i_4_n_0\
);
\cr_int[15]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_40_n_0\
);
\cr_int[15]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_41_n_0\
);
\cr_int[15]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_42_n_0\
);
\cr_int[15]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_43_n_0\
);
\cr_int[15]_i_48\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(3),
O => \cr_int[15]_i_48_n_0\
);
\cr_int[15]_i_49\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(2),
O => \cr_int[15]_i_49_n_0\
);
\cr_int[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_16_n_0\,
I1 => \cr_int[15]_i_17_n_0\,
O => \cr_int[15]_i_5_n_0\
);
\cr_int[15]_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(1),
O => \cr_int[15]_i_50_n_0\
);
\cr_int[15]_i_51\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(0),
O => \cr_int[15]_i_51_n_0\
);
\cr_int[15]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_16_n_0\,
I1 => \cr_int[19]_i_17_n_0\,
I2 => \cr_int[15]_i_2_n_0\,
O => \cr_int[15]_i_6_n_0\
);
\cr_int[15]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_10_n_0\,
I1 => \cr_int[15]_i_11_n_0\,
I2 => \cr_int[15]_i_3_n_0\,
O => \cr_int[15]_i_7_n_0\
);
\cr_int[15]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_12_n_0\,
I1 => \cr_int[15]_i_13_n_0\,
I2 => \cr_int[15]_i_4_n_0\,
O => \cr_int[15]_i_8_n_0\
);
\cr_int[15]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_14_n_0\,
I1 => \cr_int[15]_i_15_n_0\,
I2 => \cr_int[15]_i_5_n_0\,
O => \cr_int[15]_i_9_n_0\
);
\cr_int[19]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(26),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(18),
I4 => \cr_int[23]_i_25_n_0\,
I5 => \cr_int[23]_i_26_n_0\,
O => \cr_int[19]_i_10_n_0\
);
\cr_int[19]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(25),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(17),
I4 => \cr_int[19]_i_18_n_0\,
I5 => \cr_int[19]_i_19_n_0\,
O => \cr_int[19]_i_11_n_0\
);
\cr_int[19]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(25),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(17),
I4 => \cr_int[19]_i_18_n_0\,
I5 => \cr_int[19]_i_19_n_0\,
O => \cr_int[19]_i_12_n_0\
);
\cr_int[19]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(24),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(16),
I4 => \cr_int[19]_i_22_n_0\,
I5 => \cr_int[19]_i_23_n_0\,
O => \cr_int[19]_i_13_n_0\
);
\cr_int[19]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(24),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(16),
I4 => \cr_int[19]_i_22_n_0\,
I5 => \cr_int[19]_i_23_n_0\,
O => \cr_int[19]_i_14_n_0\
);
\cr_int[19]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(23),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(15),
I4 => \cr_int[19]_i_24_n_0\,
I5 => \cr_int[19]_i_25_n_0\,
O => \cr_int[19]_i_15_n_0\
);
\cr_int[19]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(23),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(15),
I4 => \cr_int[19]_i_24_n_0\,
I5 => \cr_int[19]_i_25_n_0\,
O => \cr_int[19]_i_16_n_0\
);
\cr_int[19]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(22),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(14),
I4 => \cr_int[19]_i_26_n_0\,
I5 => \cr_int[19]_i_27_n_0\,
O => \cr_int[19]_i_17_n_0\
);
\cr_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(3),
O => \cr_int[19]_i_18_n_0\
);
\cr_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(0),
O => \cr_int[19]_i_19_n_0\
);
\cr_int[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_10_n_0\,
I1 => \cr_int[19]_i_11_n_0\,
O => \cr_int[19]_i_2_n_0\
);
\cr_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(2),
O => \cr_int[19]_i_22_n_0\
);
\cr_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(3),
O => \cr_int[19]_i_23_n_0\
);
\cr_int[19]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(1),
O => \cr_int[19]_i_24_n_0\
);
\cr_int[19]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(2),
O => \cr_int[19]_i_25_n_0\
);
\cr_int[19]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(0),
O => \cr_int[19]_i_26_n_0\
);
\cr_int[19]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(1),
O => \cr_int[19]_i_27_n_0\
);
\cr_int[19]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_29_n_0\
);
\cr_int[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_12_n_0\,
I1 => \cr_int[19]_i_13_n_0\,
O => \cr_int[19]_i_3_n_0\
);
\cr_int[19]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_30_n_0\
);
\cr_int[19]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_31_n_0\
);
\cr_int[19]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_32_n_0\
);
\cr_int[19]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(24),
O => \cr_int[19]_i_33_n_0\
);
\cr_int[19]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(23),
O => \cr_int[19]_i_34_n_0\
);
\cr_int[19]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(22),
O => \cr_int[19]_i_35_n_0\
);
\cr_int[19]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(21),
O => \cr_int[19]_i_36_n_0\
);
\cr_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_38_n_0\
);
\cr_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_39_n_0\
);
\cr_int[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_14_n_0\,
I1 => \cr_int[19]_i_15_n_0\,
O => \cr_int[19]_i_4_n_0\
);
\cr_int[19]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_40_n_0\
);
\cr_int[19]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_41_n_0\
);
\cr_int[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_16_n_0\,
I1 => \cr_int[19]_i_17_n_0\,
O => \cr_int[19]_i_5_n_0\
);
\cr_int[19]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_16_n_0\,
I1 => \cr_int[23]_i_17_n_0\,
I2 => \cr_int[19]_i_2_n_0\,
O => \cr_int[19]_i_6_n_0\
);
\cr_int[19]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_10_n_0\,
I1 => \cr_int[19]_i_11_n_0\,
I2 => \cr_int[19]_i_3_n_0\,
O => \cr_int[19]_i_7_n_0\
);
\cr_int[19]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_12_n_0\,
I1 => \cr_int[19]_i_13_n_0\,
I2 => \cr_int[19]_i_4_n_0\,
O => \cr_int[19]_i_8_n_0\
);
\cr_int[19]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_14_n_0\,
I1 => \cr_int[19]_i_15_n_0\,
I2 => \cr_int[19]_i_5_n_0\,
O => \cr_int[19]_i_9_n_0\
);
\cr_int[23]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(30),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(22),
I4 => \cr_int[27]_i_10_n_0\,
I5 => \cr_int[27]_i_11_n_0\,
O => \cr_int[23]_i_10_n_0\
);
\cr_int[23]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(29),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(21),
I4 => \cr_int[23]_i_18_n_0\,
I5 => \cr_int[23]_i_19_n_0\,
O => \cr_int[23]_i_11_n_0\
);
\cr_int[23]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(29),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(21),
I4 => \cr_int[23]_i_18_n_0\,
I5 => \cr_int[23]_i_19_n_0\,
O => \cr_int[23]_i_12_n_0\
);
\cr_int[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(28),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(20),
I4 => \cr_int[23]_i_21_n_0\,
I5 => \cr_int[23]_i_22_n_0\,
O => \cr_int[23]_i_13_n_0\
);
\cr_int[23]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(28),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(20),
I4 => \cr_int[23]_i_21_n_0\,
I5 => \cr_int[23]_i_22_n_0\,
O => \cr_int[23]_i_14_n_0\
);
\cr_int[23]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(27),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(19),
I4 => \cr_int[23]_i_23_n_0\,
I5 => \cr_int[23]_i_24_n_0\,
O => \cr_int[23]_i_15_n_0\
);
\cr_int[23]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(27),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(19),
I4 => \cr_int[23]_i_23_n_0\,
I5 => \cr_int[23]_i_24_n_0\,
O => \cr_int[23]_i_16_n_0\
);
\cr_int[23]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(26),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(18),
I4 => \cr_int[23]_i_25_n_0\,
I5 => \cr_int[23]_i_26_n_0\,
O => \cr_int[23]_i_17_n_0\
);
\cr_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_17\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(3),
O => \cr_int[23]_i_18_n_0\
);
\cr_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_8_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_6\(0),
O => \cr_int[23]_i_19_n_0\
);
\cr_int[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_10_n_0\,
I1 => \cr_int[23]_i_11_n_0\,
O => \cr_int[23]_i_2_n_0\
);
\cr_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(2),
O => \cr_int[23]_i_21_n_0\
);
\cr_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(3),
O => \cr_int[23]_i_22_n_0\
);
\cr_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(1),
O => \cr_int[23]_i_23_n_0\
);
\cr_int[23]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(2),
O => \cr_int[23]_i_24_n_0\
);
\cr_int[23]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(0),
O => \cr_int[23]_i_25_n_0\
);
\cr_int[23]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(1),
O => \cr_int[23]_i_26_n_0\
);
\cr_int[23]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_27_n_0\
);
\cr_int[23]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_28_n_0\
);
\cr_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_29_n_0\
);
\cr_int[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_12_n_0\,
I1 => \cr_int[23]_i_13_n_0\,
O => \cr_int[23]_i_3_n_0\
);
\cr_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_30_n_0\
);
\cr_int[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_14_n_0\,
I1 => \cr_int[23]_i_15_n_0\,
O => \cr_int[23]_i_4_n_0\
);
\cr_int[23]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_16_n_0\,
I1 => \cr_int[23]_i_17_n_0\,
O => \cr_int[23]_i_5_n_0\
);
\cr_int[23]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[27]_i_7_n_0\,
I1 => \cr_int[27]_i_8_n_0\,
I2 => \cr_int[23]_i_2_n_0\,
O => \cr_int[23]_i_6_n_0\
);
\cr_int[23]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_10_n_0\,
I1 => \cr_int[23]_i_11_n_0\,
I2 => \cr_int[23]_i_3_n_0\,
O => \cr_int[23]_i_7_n_0\
);
\cr_int[23]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_12_n_0\,
I1 => \cr_int[23]_i_13_n_0\,
I2 => \cr_int[23]_i_4_n_0\,
O => \cr_int[23]_i_8_n_0\
);
\cr_int[23]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_14_n_0\,
I1 => \cr_int[23]_i_15_n_0\,
I2 => \cr_int[23]_i_5_n_0\,
O => \cr_int[23]_i_9_n_0\
);
\cr_int[27]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_17\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_1\(0),
O => \cr_int[27]_i_10_n_0\
);
\cr_int[27]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_8_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_6\(1),
O => \cr_int[27]_i_11_n_0\
);
\cr_int[27]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[27]_i_12_n_0\
);
\cr_int[27]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[27]_i_13_n_0\
);
\cr_int[27]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[27]_i_7_n_0\,
I1 => \cr_int[27]_i_8_n_0\,
O => \cr_int[27]_i_2_n_0\
);
\cr_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_3_n_0\
);
\cr_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_4_n_0\
);
\cr_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_5_n_0\
);
\cr_int[27]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[27]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_6_n_0\
);
\cr_int[27]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"4B44B4BB4B444B44"
)
port map (
I0 => \cr_int_reg[31]_i_12_n_1\,
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \rgb888[8]_18\(0),
I3 => \^cr_int_reg[31]_2\(1),
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_7_n_0\
);
\cr_int[27]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(30),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(22),
I4 => \cr_int[27]_i_10_n_0\,
I5 => \cr_int[27]_i_11_n_0\,
O => \cr_int[27]_i_8_n_0\
);
\cr_int[31]_i_100\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => rgb888(14),
I5 => rgb888(15),
O => \cr_int[31]_i_100_n_0\
);
\cr_int[31]_i_103\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cr_int[31]_i_103_n_0\
);
\cr_int[31]_i_108\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_108_n_0\
);
\cr_int[31]_i_109\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_109_n_0\
);
\cr_int[31]_i_110\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_110_n_0\
);
\cr_int[31]_i_111\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_111_n_0\
);
\cr_int[31]_i_112\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_112_n_0\
);
\cr_int[31]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \cr_int[31]_i_113_n_0\
);
\cr_int[31]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \cr_int[31]_i_114_n_0\
);
\cr_int[31]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \cr_int[31]_i_115_n_0\
);
\cr_int[31]_i_116\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(1),
O => \cr_int[31]_i_116_n_0\
);
\cr_int[31]_i_117\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(6),
O => \cr_int[31]_i_117_n_0\
);
\cr_int[31]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \cr_int[31]_i_118_n_0\
);
\cr_int[31]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \cr_int[31]_i_119_n_0\
);
\cr_int[31]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \cr_int[31]_i_120_n_0\
);
\cr_int[31]_i_121\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cr_int[31]_i_121_n_0\
);
\cr_int[31]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
O => \cr_int[31]_i_122_n_0\
);
\cr_int[31]_i_123\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(14),
O => \cr_int[31]_i_123_n_0\
);
\cr_int[31]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \cr_int[31]_i_124_n_0\
);
\cr_int[31]_i_125\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(14),
I1 => rgb888(12),
O => \cr_int[31]_i_125_n_0\
);
\cr_int[31]_i_126\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
O => \cr_int[31]_i_126_n_0\
);
\cr_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rgb888[8]_18\(0),
I1 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_13_n_0\
);
\cr_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"60"
)
port map (
I0 => \^cr_int_reg[27]_0\,
I1 => rgb888(7),
I2 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_15_n_0\
);
\cr_int[31]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_1\(1),
I1 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_16_n_0\
);
\cr_int[31]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => \^cr_int_reg[27]_0\,
O => \cr_int[31]_i_17_n_0\
);
\cr_int[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => \^cr_int_reg[27]_0\,
O => \cr_int[31]_i_18_n_0\
);
\cr_int[31]_i_19\: unisim.vcomponents.LUT3
generic map(
INIT => X"17"
)
port map (
I0 => \cr_int_reg[31]_i_48_n_2\,
I1 => \^cr_int_reg[27]_0\,
I2 => rgb888(7),
O => \cr_int[31]_i_19_n_0\
);
\cr_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000DD0D0000"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[31]_i_8_n_1\,
I2 => \^cr_int_reg[31]_2\(1),
I3 => \rgb888[8]_18\(0),
I4 => \cr_int_reg[31]_i_11_n_4\,
I5 => \cr_int_reg[31]_i_12_n_1\,
O => \cr_int[31]_i_2_n_0\
);
\cr_int[31]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \^cr_int_reg[27]_0\,
I1 => rgb888(7),
I2 => \cr_int[31]_i_16_n_0\,
I3 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_20_n_0\
);
\cr_int[31]_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_6\(1),
O => \cr_int[31]_i_22_n_0\
);
\cr_int[31]_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_6\(0),
O => \cr_int[31]_i_23_n_0\
);
\cr_int[31]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cr_int[31]_i_25_n_0\
);
\cr_int[31]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => \cr_int_reg[31]_i_63_n_2\,
I1 => \^di\(0),
O => \cr_int[31]_i_26_n_0\
);
\cr_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_3_n_0\
);
\cr_int[31]_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
I5 => rgb888(21),
O => \cr_int[31]_i_31_n_0\
);
\cr_int[31]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_32_n_0\
);
\cr_int[31]_i_33\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_33_n_0\
);
\cr_int[31]_i_34\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_34_n_0\
);
\cr_int[31]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_80_n_0\,
I2 => rgb888(22),
O => \cr_int[31]_i_35_n_0\
);
\cr_int[31]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(30),
O => \cr_int[31]_i_37_n_0\
);
\cr_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(29),
O => \cr_int[31]_i_38_n_0\
);
\cr_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_4_n_0\
);
\cr_int[31]_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888888882"
)
port map (
I0 => \cr_int_reg[31]_i_48_n_7\,
I1 => rgb888(5),
I2 => rgb888(3),
I3 => rgb888(1),
I4 => rgb888(2),
I5 => rgb888(4),
O => \cr_int[31]_i_40_n_0\
);
\cr_int[31]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEEEEEEB"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_4\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cr_int[31]_i_41_n_0\
);
\cr_int[31]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_4\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cr_int[31]_i_42_n_0\
);
\cr_int[31]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_6\,
I1 => rgb888(2),
I2 => rgb888(1),
O => \cr_int[31]_i_43_n_0\
);
\cr_int[31]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cr_int_reg[27]_1\(1),
I1 => \cr_int_reg[31]_i_48_n_2\,
I2 => \cr_int[31]_i_40_n_0\,
O => \cr_int[31]_i_44_n_0\
);
\cr_int[31]_i_45\: unisim.vcomponents.LUT4
generic map(
INIT => X"1EE1"
)
port map (
I0 => \cr_int[31]_i_92_n_0\,
I1 => \cr_int_reg[31]_i_91_n_4\,
I2 => \^cr_int_reg[27]_1\(0),
I3 => \cr_int_reg[31]_i_48_n_7\,
O => \cr_int[31]_i_45_n_0\
);
\cr_int[31]_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699999999996"
)
port map (
I0 => rgb888(4),
I1 => \cr_int_reg[31]_i_91_n_4\,
I2 => \cr_int_reg[31]_i_91_n_5\,
I3 => rgb888(2),
I4 => rgb888(1),
I5 => rgb888(3),
O => \cr_int[31]_i_46_n_0\
);
\cr_int[31]_i_47\: unisim.vcomponents.LUT5
generic map(
INIT => X"817E7E81"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_6\,
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => \cr_int_reg[31]_i_91_n_5\,
O => \cr_int[31]_i_47_n_0\
);
\cr_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_5_n_0\
);
\cr_int[31]_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(3),
O => \cr_int[31]_i_50_n_0\
);
\cr_int[31]_i_51\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(2),
O => \cr_int[31]_i_51_n_0\
);
\cr_int[31]_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(1),
O => \cr_int[31]_i_52_n_0\
);
\cr_int[31]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(0),
O => \cr_int[31]_i_53_n_0\
);
\cr_int[31]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int[31]_i_100_n_0\,
I1 => \cr_int_reg[31]_i_63_n_2\,
O => \cr_int[31]_i_55_n_0\
);
\cr_int[31]_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAA00000000"
)
port map (
I0 => rgb888(14),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => \cr_int_reg[31]_i_63_n_7\,
O => \cr_int[31]_i_56_n_0\
);
\cr_int[31]_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFEAAA2AAA8000"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_1\,
I1 => rgb888(11),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => rgb888(13),
I5 => \cr_int_reg[31]_i_102_n_4\,
O => \cr_int[31]_i_57_n_0\
);
\cr_int[31]_i_58\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFEA2A80"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(12),
I4 => \cr_int_reg[31]_i_102_n_5\,
O => \cr_int[31]_i_58_n_0\
);
\cr_int[31]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"36"
)
port map (
I0 => \cr_int[31]_i_100_n_0\,
I1 => \^di\(0),
I2 => \cr_int_reg[31]_i_63_n_2\,
O => \cr_int[31]_i_59_n_0\
);
\cr_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_6_n_0\
);
\cr_int[31]_i_60\: unisim.vcomponents.LUT4
generic map(
INIT => X"7887"
)
port map (
I0 => \cr_int_reg[31]_i_63_n_7\,
I1 => \^cr_int_reg[31]_0\,
I2 => \cr_int_reg[31]_i_63_n_2\,
I3 => \cr_int[31]_i_100_n_0\,
O => \cr_int[31]_i_60_n_0\
);
\cr_int[31]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[31]_i_57_n_0\,
I1 => \^cr_int_reg[31]_0\,
I2 => \cr_int_reg[31]_i_63_n_7\,
O => \cr_int[31]_i_61_n_0\
);
\cr_int[31]_i_62\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int[31]_i_58_n_0\,
I1 => \cr_int_reg[31]_i_102_n_4\,
I2 => \^cr_int_reg[31]_1\,
I3 => \cr_int_reg[31]_i_101_n_1\,
O => \cr_int[31]_i_62_n_0\
);
\cr_int[31]_i_71\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFE"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
I2 => rgb888(17),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(22),
O => \cr_int[31]_i_71_n_0\
);
\cr_int[31]_i_72\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFE"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
I4 => rgb888(21),
O => \cr_int[31]_i_72_n_0\
);
\cr_int[31]_i_73\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
O => \cr_int[31]_i_73_n_0\
);
\cr_int[31]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(18),
I1 => rgb888(17),
O => \cr_int[31]_i_74_n_0\
);
\cr_int[31]_i_75\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA955555555"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
I5 => rgb888(21),
O => \cr_int[31]_i_75_n_0\
);
\cr_int[31]_i_76\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCC999999993"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(21),
I2 => rgb888(19),
I3 => rgb888(17),
I4 => rgb888(18),
I5 => rgb888(20),
O => \cr_int[31]_i_76_n_0\
);
\cr_int[31]_i_77\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA99995"
)
port map (
I0 => rgb888(20),
I1 => \cr_int_reg[3]_i_26_n_1\,
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
O => \cr_int[31]_i_77_n_0\
);
\cr_int[31]_i_78\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A95"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
O => \cr_int[31]_i_78_n_0\
);
\cr_int[31]_i_79\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
I2 => rgb888(17),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(22),
O => \cr_int[31]_i_79_n_0\
);
\cr_int[31]_i_80\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
I4 => rgb888(21),
O => \cr_int[31]_i_80_n_0\
);
\cr_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(28),
O => \cr_int[31]_i_81_n_0\
);
\cr_int[31]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(27),
O => \cr_int[31]_i_82_n_0\
);
\cr_int[31]_i_83\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(26),
O => \cr_int[31]_i_83_n_0\
);
\cr_int[31]_i_84\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(25),
O => \cr_int[31]_i_84_n_0\
);
\cr_int[31]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \cr_int[31]_i_85_n_0\
);
\cr_int[31]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => \cr_int_reg[31]_i_91_n_6\,
O => \cr_int[31]_i_87_n_0\
);
\cr_int[31]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(1),
I1 => \cr_int_reg[31]_i_91_n_7\,
O => \cr_int[31]_i_88_n_0\
);
\cr_int[31]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_4\,
I1 => rgb888(0),
O => \cr_int[31]_i_89_n_0\
);
\cr_int[31]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_5\,
O => \cr_int[31]_i_90_n_0\
);
\cr_int[31]_i_92\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(2),
I3 => rgb888(4),
O => \cr_int[31]_i_92_n_0\
);
\cr_int[31]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \cr_int[31]_i_93_n_0\
);
\cr_int[31]_i_94\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(3),
O => \cr_int[31]_i_94_n_0\
);
\cr_int[31]_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(2),
O => \cr_int[31]_i_95_n_0\
);
\cr_int[31]_i_96\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(1),
O => \cr_int[31]_i_96_n_0\
);
\cr_int[31]_i_97\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(0),
O => \cr_int[31]_i_97_n_0\
);
\cr_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(0),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[3]_0\(2),
O => \cr_int[3]_i_10_n_0\
);
\cr_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_6\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[3]_i_11_n_0\
);
\cr_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(1),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[3]_i_16_n_4\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(9),
O => \cr_int_reg3__0\(1)
);
\cr_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_2\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[3]_0\(1),
O => \cr_int[3]_i_13_n_0\
);
\cr_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_7\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[3]_i_14_n_0\
);
\cr_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
I1 => \^cr_int_reg[3]_1\(0),
I2 => \^cr_int_reg[3]_2\(0),
O => \cr_int[3]_i_17_n_0\
);
\cr_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[3]_i_32_n_4\,
O => \cr_int[3]_i_18_n_0\
);
\cr_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(2),
I1 => \cr_int[3]_i_10_n_0\,
I2 => \cr_int[3]_i_11_n_0\,
O => \cr_int[3]_i_2_n_0\
);
\cr_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[3]_i_22_n_0\
);
\cr_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_6\,
O => \cr_int[3]_i_23_n_0\
);
\cr_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_7\,
O => \cr_int[3]_i_24_n_0\
);
\cr_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_6\,
O => \cr_int[3]_i_25_n_0\
);
\cr_int[3]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(18),
I1 => rgb888(17),
I2 => \cr_int_reg[3]_i_26_n_6\,
O => \cr_int[3]_i_28_n_0\
);
\cr_int[3]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_7\,
I1 => rgb888(17),
O => \cr_int[3]_i_29_n_0\
);
\cr_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(1),
I1 => \cr_int[3]_i_13_n_0\,
I2 => \cr_int[3]_i_14_n_0\,
O => \cr_int[3]_i_3_n_0\
);
\cr_int[3]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_4\,
I1 => rgb888(16),
O => \cr_int[3]_i_30_n_0\
);
\cr_int[3]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_5\,
O => \cr_int[3]_i_31_n_0\
);
\cr_int[3]_i_34\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_7\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => \cr_int_reg[31]_i_102_n_6\,
O => \cr_int[3]_i_34_n_0\
);
\cr_int[3]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(10),
I1 => \cr_int_reg[3]_i_64_n_4\,
I2 => \cr_int_reg[31]_i_102_n_7\,
O => \cr_int[3]_i_35_n_0\
);
\cr_int[3]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_5\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_70_n_4\,
O => \cr_int[3]_i_36_n_0\
);
\cr_int[3]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_5\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_70_n_4\,
O => \cr_int[3]_i_37_n_0\
);
\cr_int[3]_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969969696"
)
port map (
I0 => \cr_int[3]_i_34_n_0\,
I1 => \cr_int_reg[31]_i_102_n_5\,
I2 => rgb888(12),
I3 => rgb888(11),
I4 => rgb888(10),
I5 => \cr_int_reg[31]_i_101_n_6\,
O => \cr_int[3]_i_38_n_0\
);
\cr_int[3]_i_39\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_7\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => \cr_int_reg[31]_i_102_n_6\,
I4 => \cr_int[3]_i_35_n_0\,
O => \cr_int[3]_i_39_n_0\
);
\cr_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00E2E2FF"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
I3 => \cr_int[3]_i_17_n_0\,
I4 => \cr_int[3]_i_18_n_0\,
O => \cr_int[3]_i_4_n_0\
);
\cr_int[3]_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => \cr_int_reg[3]_i_70_n_4\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_64_n_5\,
I3 => \cr_int_reg[31]_i_102_n_7\,
I4 => rgb888(10),
I5 => \cr_int_reg[3]_i_64_n_4\,
O => \cr_int[3]_i_40_n_0\
);
\cr_int[3]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => \cr_int_reg[3]_i_70_n_4\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_64_n_5\,
I3 => \cr_int_reg[3]_i_70_n_5\,
I4 => rgb888(8),
O => \cr_int[3]_i_41_n_0\
);
\cr_int[3]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(1),
O => \cr_int[3]_i_43_n_0\
);
\cr_int[3]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
O => \cr_int[3]_i_44_n_0\
);
\cr_int[3]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_19_n_7\,
O => \cr_int[3]_i_45_n_0\
);
\cr_int[3]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_4\,
O => \cr_int[3]_i_46_n_0\
);
\cr_int[3]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_7\,
O => \cr_int[3]_i_47_n_0\
);
\cr_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_7\,
O => \cr_int[3]_i_48_n_0\
);
\cr_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_4\,
O => \cr_int[3]_i_49_n_0\
);
\cr_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(3),
I1 => \cr_int[7]_i_17_n_0\,
I2 => \cr_int[7]_i_18_n_0\,
I3 => \cr_int[3]_i_2_n_0\,
O => \cr_int[3]_i_5_n_0\
);
\cr_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_5\,
O => \cr_int[3]_i_50_n_0\
);
\cr_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_6\,
O => \cr_int[3]_i_51_n_0\
);
\cr_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \cr_int[3]_i_52_n_0\
);
\cr_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(22),
O => \cr_int[3]_i_53_n_0\
);
\cr_int[3]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(21),
I1 => rgb888(23),
O => \cr_int[3]_i_55_n_0\
);
\cr_int[3]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(20),
I1 => rgb888(22),
O => \cr_int[3]_i_56_n_0\
);
\cr_int[3]_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(19),
I1 => rgb888(21),
O => \cr_int[3]_i_57_n_0\
);
\cr_int[3]_i_58\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(18),
I1 => rgb888(20),
O => \cr_int[3]_i_58_n_0\
);
\cr_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(2),
I1 => \cr_int[3]_i_10_n_0\,
I2 => \cr_int[3]_i_11_n_0\,
I3 => \cr_int[3]_i_3_n_0\,
O => \cr_int[3]_i_6_n_0\
);
\cr_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[3]_i_60_n_0\
);
\cr_int[3]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_7\,
O => \cr_int[3]_i_61_n_0\
);
\cr_int[3]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_4\,
O => \cr_int[3]_i_62_n_0\
);
\cr_int[3]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_5\,
O => \cr_int[3]_i_63_n_0\
);
\cr_int[3]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_70_n_5\,
I2 => \cr_int_reg[3]_i_64_n_6\,
O => \cr_int[3]_i_66_n_0\
);
\cr_int[3]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_7\,
I1 => \cr_int_reg[3]_i_70_n_6\,
O => \cr_int[3]_i_67_n_0\
);
\cr_int[3]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_4\,
I1 => \cr_int_reg[3]_i_70_n_7\,
O => \cr_int[3]_i_68_n_0\
);
\cr_int[3]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_5\,
I1 => rgb888(8),
O => \cr_int[3]_i_69_n_0\
);
\cr_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(1),
I1 => \cr_int[3]_i_13_n_0\,
I2 => \cr_int[3]_i_14_n_0\,
I3 => \cr_int[3]_i_4_n_0\,
O => \cr_int[3]_i_7_n_0\
);
\cr_int[3]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_7\,
O => \cr_int[3]_i_71_n_0\
);
\cr_int[3]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_5\,
O => \cr_int[3]_i_72_n_0\
);
\cr_int[3]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_6\,
O => \cr_int[3]_i_73_n_0\
);
\cr_int[3]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_65_n_5\,
O => \cr_int[3]_i_74_n_0\
);
\cr_int[3]_i_75\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_6\,
O => \cr_int[3]_i_75_n_0\
);
\cr_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(17),
I1 => rgb888(19),
O => \cr_int[3]_i_76_n_0\
);
\cr_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(16),
I1 => rgb888(18),
O => \cr_int[3]_i_77_n_0\
);
\cr_int[3]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
O => \cr_int[3]_i_78_n_0\
);
\cr_int[3]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(16),
O => \cr_int[3]_i_79_n_0\
);
\cr_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DE2E21D"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
I3 => \cr_int[3]_i_17_n_0\,
I4 => \cr_int[3]_i_18_n_0\,
O => \cr_int[3]_i_8_n_0\
);
\cr_int[3]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(0),
O => \cr_int[3]_i_80_n_0\
);
\cr_int[3]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_6\,
O => \cr_int[3]_i_81_n_0\
);
\cr_int[3]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_7\,
O => \cr_int[3]_i_82_n_0\
);
\cr_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_6\,
O => \cr_int[3]_i_83_n_0\
);
\cr_int[3]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_7\,
O => \cr_int[3]_i_84_n_0\
);
\cr_int[3]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \cr_int[3]_i_85_n_0\
);
\cr_int[3]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(14),
O => \cr_int[3]_i_86_n_0\
);
\cr_int[3]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(13),
O => \cr_int[3]_i_87_n_0\
);
\cr_int[3]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(12),
O => \cr_int[3]_i_88_n_0\
);
\cr_int[3]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(11),
O => \cr_int[3]_i_89_n_0\
);
\cr_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(2),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_7\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(10),
O => \cr_int_reg3__0\(2)
);
\cr_int[3]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
O => \cr_int[3]_i_90_n_0\
);
\cr_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \cr_int[3]_i_91_n_0\
);
\cr_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \cr_int[3]_i_92_n_0\
);
\cr_int[3]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
O => \cr_int[3]_i_93_n_0\
);
\cr_int[3]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
O => \cr_int[3]_i_94_n_0\
);
\cr_int[3]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(10),
I1 => rgb888(8),
O => \cr_int[3]_i_95_n_0\
);
\cr_int[3]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(9),
O => \cr_int[3]_i_96_n_0\
);
\cr_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(5),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_4\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(13),
O => \cr_int_reg3__0\(5)
);
\cr_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(3),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(2),
O => \cr_int[7]_i_11_n_0\
);
\cr_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_16_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_18_n_7\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[7]_i_12_n_0\
);
\cr_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(4),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_5\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(12),
O => \cr_int_reg3__0\(4)
);
\cr_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(2),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(1),
O => \cr_int[7]_i_14_n_0\
);
\cr_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_4\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[7]_i_15_n_0\
);
\cr_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(3),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_6\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(11),
O => \cr_int_reg3__0\(3)
);
\cr_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(0),
O => \cr_int[7]_i_17_n_0\
);
\cr_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_5\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[7]_i_18_n_0\
);
\cr_int[7]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(7),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_6\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(15),
O => cr_int_reg3(7)
);
\cr_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555556A6AAAA56A6"
)
port map (
I0 => \cr_int[11]_i_22_n_0\,
I1 => cr_int_reg6(15),
I2 => cr_int_reg7,
I3 => \cr_int_reg[31]_i_11_n_6\,
I4 => \cr_int_reg[31]_i_11_n_4\,
I5 => cr_int_reg4(7),
O => \cr_int[7]_i_2_n_0\
);
\cr_int[7]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[11]_i_16_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \cr_int_reg[11]_i_18_n_6\,
O => \cr_int[7]_i_20_n_0\
);
\cr_int[7]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[11]_0\(0),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(3),
O => \cr_int[7]_i_21_n_0\
);
\cr_int[7]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(6),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_7\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(14),
O => \cr_int_reg3__0\(6)
);
\cr_int[7]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(2),
O => \cr_int[7]_i_25_n_0\
);
\cr_int[7]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(1),
O => \cr_int[7]_i_26_n_0\
);
\cr_int[7]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(0),
O => \cr_int[7]_i_27_n_0\
);
\cr_int[7]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(2),
O => \cr_int[7]_i_28_n_0\
);
\cr_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(5),
I1 => \cr_int[7]_i_11_n_0\,
I2 => \cr_int[7]_i_12_n_0\,
O => \cr_int[7]_i_3_n_0\
);
\cr_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(4),
I1 => \cr_int[7]_i_14_n_0\,
I2 => \cr_int[7]_i_15_n_0\,
O => \cr_int[7]_i_4_n_0\
);
\cr_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(3),
I1 => \cr_int[7]_i_17_n_0\,
I2 => \cr_int[7]_i_18_n_0\,
O => \cr_int[7]_i_5_n_0\
);
\cr_int[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => cr_int_reg3(7),
I1 => \cr_int[11]_i_22_n_0\,
I2 => \cr_int[7]_i_20_n_0\,
I3 => \cr_int[7]_i_21_n_0\,
I4 => \cr_int_reg3__0\(6),
O => \cr_int[7]_i_6_n_0\
);
\cr_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int[7]_i_3_n_0\,
I1 => \cr_int[7]_i_20_n_0\,
I2 => \cr_int[7]_i_21_n_0\,
I3 => \cr_int_reg3__0\(6),
O => \cr_int[7]_i_7_n_0\
);
\cr_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(5),
I1 => \cr_int[7]_i_11_n_0\,
I2 => \cr_int[7]_i_12_n_0\,
I3 => \cr_int[7]_i_4_n_0\,
O => \cr_int[7]_i_8_n_0\
);
\cr_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(4),
I1 => \cr_int[7]_i_14_n_0\,
I2 => \cr_int[7]_i_15_n_0\,
I3 => \cr_int[7]_i_5_n_0\,
O => \cr_int[7]_i_9_n_0\
);
\cr_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_7\,
Q => \cr_int_reg_n_0_[0]\,
R => '0'
);
\cr_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_5\,
Q => \cr_int_reg__0\(10),
R => '0'
);
\cr_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_4\,
Q => \cr_int_reg__0\(11),
R => '0'
);
\cr_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_1_n_0\,
CO(3) => \cr_int_reg[11]_i_1_n_0\,
CO(2) => \cr_int_reg[11]_i_1_n_1\,
CO(1) => \cr_int_reg[11]_i_1_n_2\,
CO(0) => \cr_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_2_n_0\,
DI(2) => \cr_int[11]_i_3_n_0\,
DI(1) => \cr_int[11]_i_4_n_0\,
DI(0) => \cr_int[11]_i_5_n_0\,
O(3) => \cr_int_reg[11]_i_1_n_4\,
O(2) => \cr_int_reg[11]_i_1_n_5\,
O(1) => \cr_int_reg[11]_i_1_n_6\,
O(0) => \cr_int_reg[11]_i_1_n_7\,
S(3) => \cr_int[11]_i_6_n_0\,
S(2) => \cr_int[11]_i_7_n_0\,
S(1) => \cr_int[11]_i_8_n_0\,
S(0) => \cr_int[11]_i_9_n_0\
);
\cr_int_reg[11]_i_103\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_125_n_0\,
CO(3) => \cr_int_reg[11]_i_103_n_0\,
CO(2) => \cr_int_reg[11]_i_103_n_1\,
CO(1) => \cr_int_reg[11]_i_103_n_2\,
CO(0) => \cr_int_reg[11]_i_103_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_126_n_0\,
DI(2) => \cr_int[11]_i_127_n_0\,
DI(1) => \cr_int[11]_i_128_n_0\,
DI(0) => \cr_int[11]_i_129_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_130_n_0\,
S(2) => \cr_int[11]_i_131_n_0\,
S(1) => \cr_int[11]_i_132_n_0\,
S(0) => \cr_int[11]_i_133_n_0\
);
\cr_int_reg[11]_i_108\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_108_n_0\,
CO(2) => \cr_int_reg[11]_i_108_n_1\,
CO(1) => \cr_int_reg[11]_i_108_n_2\,
CO(0) => \cr_int_reg[11]_i_108_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_134_n_0\,
DI(2) => \cr_int[11]_i_135_n_0\,
DI(1) => \cr_int[11]_i_136_n_0\,
DI(0) => \cr_int[11]_i_137_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_138_n_0\,
S(2) => \cr_int[11]_i_139_n_0\,
S(1) => \cr_int[11]_i_140_n_0\,
S(0) => \cr_int[11]_i_141_n_0\
);
\cr_int_reg[11]_i_116\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_116_n_0\,
CO(2) => \cr_int_reg[11]_i_116_n_1\,
CO(1) => \cr_int_reg[11]_i_116_n_2\,
CO(0) => \cr_int_reg[11]_i_116_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_142_n_0\,
DI(2) => \cr_int[11]_i_143_n_0\,
DI(1) => \cr_int[11]_i_144_n_0\,
DI(0) => \cr_int[11]_i_145_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_146_n_0\,
S(2) => \cr_int[11]_i_147_n_0\,
S(1) => \cr_int[11]_i_148_n_0\,
S(0) => \cr_int[11]_i_149_n_0\
);
\cr_int_reg[11]_i_125\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_125_n_0\,
CO(2) => \cr_int_reg[11]_i_125_n_1\,
CO(1) => \cr_int_reg[11]_i_125_n_2\,
CO(0) => \cr_int_reg[11]_i_125_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_150_n_0\,
DI(2) => \cr_int[11]_i_151_n_0\,
DI(1) => \cr_int[11]_i_152_n_0\,
DI(0) => \cb_int_reg[3]_i_94_n_7\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_153_n_0\,
S(2) => \cr_int[11]_i_154_n_0\,
S(1) => \cr_int[11]_i_155_n_0\,
S(0) => \cr_int[11]_i_156_n_0\
);
\cr_int_reg[11]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_31_n_0\,
CO(3) => \cr_int_reg[11]_i_16_n_0\,
CO(2) => \cr_int_reg[11]_i_16_n_1\,
CO(1) => \cr_int_reg[11]_i_16_n_2\,
CO(0) => \cr_int_reg[11]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_16_n_4\,
O(2) => \cr_int_reg[11]_i_16_n_5\,
O(1) => \cr_int_reg[11]_i_16_n_6\,
O(0) => \cr_int_reg[11]_i_16_n_7\,
S(3) => \cr_int[11]_i_32_n_0\,
S(2) => \cr_int[11]_i_33_n_0\,
S(1) => \cr_int[11]_i_34_n_0\,
S(0) => \cr_int[11]_i_35_n_0\
);
\cr_int_reg[11]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_36_n_0\,
CO(3) => \cr_int_reg[11]_i_17_n_0\,
CO(2) => \cr_int_reg[11]_i_17_n_1\,
CO(1) => \cr_int_reg[11]_i_17_n_2\,
CO(0) => \cr_int_reg[11]_i_17_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^cr_int_reg[27]_2\(0),
DI(1) => \^cr_int_reg[27]_2\(0),
DI(0) => \^cr_int_reg[27]_2\(0),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_37_n_0\,
S(2) => \cr_int[11]_i_38_n_0\,
S(1) => \cr_int[11]_i_39_n_0\,
S(0) => \cr_int[11]_i_40_n_0\
);
\cr_int_reg[11]_i_18\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_41_n_0\,
CO(3) => \cr_int_reg[15]_1\(0),
CO(2) => \cr_int_reg[11]_i_18_n_1\,
CO(1) => \cr_int_reg[11]_i_18_n_2\,
CO(0) => \cr_int_reg[11]_i_18_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_18_n_4\,
O(2) => \cr_int_reg[11]_i_18_n_5\,
O(1) => \cr_int_reg[11]_i_18_n_6\,
O(0) => \cr_int_reg[11]_i_18_n_7\,
S(3) => \cr_int[11]_i_42_n_0\,
S(2) => \cr_int[11]_i_43_n_0\,
S(1) => \cr_int[11]_i_44_n_0\,
S(0) => \cr_int[11]_i_45_n_0\
);
\cr_int_reg[11]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_46_n_0\,
CO(3) => \cr_int_reg[11]_i_19_n_0\,
CO(2) => \cr_int_reg[11]_i_19_n_1\,
CO(1) => \cr_int_reg[11]_i_19_n_2\,
CO(0) => \cr_int_reg[11]_i_19_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(16 downto 13),
S(3) => \cr_int[11]_i_47_n_0\,
S(2) => \cr_int[11]_i_48_n_0\,
S(1) => \cr_int[11]_i_49_n_0\,
S(0) => \cr_int[11]_i_50_n_0\
);
\cr_int_reg[11]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_51_n_0\,
CO(3) => cr_int_reg7,
CO(2) => \cr_int_reg[11]_i_20_n_1\,
CO(1) => \cr_int_reg[11]_i_20_n_2\,
CO(0) => \cr_int_reg[11]_i_20_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cr_int_reg[31]_i_11_n_4\,
DI(1) => \cr_int_reg[31]_i_11_n_4\,
DI(0) => \cr_int_reg[31]_i_11_n_4\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_52_n_0\,
S(2) => \cr_int[11]_i_53_n_0\,
S(1) => \cr_int[11]_i_54_n_0\,
S(0) => \cr_int[11]_i_55_n_0\
);
\cr_int_reg[11]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_56_n_0\,
CO(3) => \cr_int_reg[11]_i_21_n_0\,
CO(2) => \cr_int_reg[11]_i_21_n_1\,
CO(1) => \cr_int_reg[11]_i_21_n_2\,
CO(0) => \cr_int_reg[11]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(8 downto 5),
S(3) => \cr_int[11]_i_57_n_0\,
S(2) => \cr_int[11]_i_58_n_0\,
S(1) => \cr_int[11]_i_59_n_0\,
S(0) => \cr_int[11]_i_60_n_0\
);
\cr_int_reg[11]_i_29\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_23_n_0\,
CO(3) => \cr_int_reg[11]_i_29_n_0\,
CO(2) => \cr_int_reg[11]_i_29_n_1\,
CO(1) => \cr_int_reg[11]_i_29_n_2\,
CO(0) => \cr_int_reg[11]_i_29_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[11]_0\(3 downto 0),
S(3) => \cr_int[11]_i_65_n_0\,
S(2) => \cr_int[11]_i_66_n_0\,
S(1) => \cr_int[11]_i_67_n_0\,
S(0) => \cr_int[11]_i_68_n_0\
);
\cr_int_reg[11]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_69_n_0\,
CO(3) => \^cr_int_reg[3]_1\(0),
CO(2) => \cr_int_reg[11]_i_30_n_1\,
CO(1) => \cr_int_reg[11]_i_30_n_2\,
CO(0) => \cr_int_reg[11]_i_30_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^cr_int_reg[31]_2\(1),
DI(1) => \^cr_int_reg[31]_2\(1),
DI(0) => \^cr_int_reg[31]_2\(1),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_70_n_0\,
S(2) => \cr_int[11]_i_71_n_0\,
S(1) => \cr_int[11]_i_72_n_0\,
S(0) => \cr_int[11]_i_73_n_0\
);
\cr_int_reg[11]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_31_n_0\,
CO(2) => \cr_int_reg[11]_i_31_n_1\,
CO(1) => \cr_int_reg[11]_i_31_n_2\,
CO(0) => \cr_int_reg[11]_i_31_n_3\,
CYINIT => \cr_int[11]_i_74_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_31_n_4\,
O(2) => \cr_int_reg[11]_i_31_n_5\,
O(1) => \cr_int_reg[11]_i_31_n_6\,
O(0) => \cr_int_reg[11]_i_31_n_7\,
S(3) => \cr_int[11]_i_75_n_0\,
S(2) => \cr_int[11]_i_76_n_0\,
S(1) => \cr_int[11]_i_77_n_0\,
S(0) => \cr_int[11]_i_78_n_0\
);
\cr_int_reg[11]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_79_n_0\,
CO(3) => \cr_int_reg[11]_i_36_n_0\,
CO(2) => \cr_int_reg[11]_i_36_n_1\,
CO(1) => \cr_int_reg[11]_i_36_n_2\,
CO(0) => \cr_int_reg[11]_i_36_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[27]_2\(0),
DI(2) => \^cr_int_reg[27]_2\(0),
DI(1) => \^cr_int_reg[27]_2\(0),
DI(0) => \^cr_int_reg[27]_2\(0),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_80_n_0\,
S(2) => \cr_int[11]_i_81_n_0\,
S(1) => \cr_int[11]_i_82_n_0\,
S(0) => \cr_int[11]_i_83_n_0\
);
\cr_int_reg[11]_i_41\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_32_n_0\,
CO(3) => \cr_int_reg[11]_i_41_n_0\,
CO(2) => \cr_int_reg[11]_i_41_n_1\,
CO(1) => \cr_int_reg[11]_i_41_n_2\,
CO(0) => \cr_int_reg[11]_i_41_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_41_n_4\,
O(2) => \cr_int_reg[11]_i_41_n_5\,
O(1) => \cr_int_reg[11]_i_41_n_6\,
O(0) => \cr_int_reg[11]_i_41_n_7\,
S(3) => \cr_int[11]_i_84_n_0\,
S(2) => \cr_int[11]_i_85_n_0\,
S(1) => \cr_int[11]_i_86_n_0\,
S(0) => \cr_int[11]_i_87_n_0\
);
\cr_int_reg[11]_i_46\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_15_n_0\,
CO(3) => \cr_int_reg[11]_i_46_n_0\,
CO(2) => \cr_int_reg[11]_i_46_n_1\,
CO(1) => \cr_int_reg[11]_i_46_n_2\,
CO(0) => \cr_int_reg[11]_i_46_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(12 downto 9),
S(3) => \cr_int[11]_i_88_n_0\,
S(2) => \cr_int[11]_i_89_n_0\,
S(1) => \cr_int[11]_i_90_n_0\,
S(0) => \cr_int[11]_i_91_n_0\
);
\cr_int_reg[11]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_92_n_0\,
CO(3) => \cr_int_reg[11]_i_51_n_0\,
CO(2) => \cr_int_reg[11]_i_51_n_1\,
CO(1) => \cr_int_reg[11]_i_51_n_2\,
CO(0) => \cr_int_reg[11]_i_51_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[31]_i_11_n_4\,
DI(2) => \cr_int_reg[31]_i_11_n_4\,
DI(1) => \cr_int_reg[31]_i_11_n_4\,
DI(0) => \cr_int[11]_i_93_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_94_n_0\,
S(2) => \cr_int[11]_i_95_n_0\,
S(1) => \cr_int[11]_i_96_n_0\,
S(0) => \cr_int[11]_i_97_n_0\
);
\cr_int_reg[11]_i_56\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_56_n_0\,
CO(2) => \cr_int_reg[11]_i_56_n_1\,
CO(1) => \cr_int_reg[11]_i_56_n_2\,
CO(0) => \cr_int_reg[11]_i_56_n_3\,
CYINIT => \cr_int[11]_i_98_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(4 downto 1),
S(3) => \cr_int[11]_i_99_n_0\,
S(2) => \cr_int[11]_i_100_n_0\,
S(1) => \cr_int[11]_i_101_n_0\,
S(0) => \cr_int[11]_i_102_n_0\
);
\cr_int_reg[11]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_103_n_0\,
CO(3) => \cr_int_reg[11]_i_69_n_0\,
CO(2) => \cr_int_reg[11]_i_69_n_1\,
CO(1) => \cr_int_reg[11]_i_69_n_2\,
CO(0) => \cr_int_reg[11]_i_69_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[31]_2\(1),
DI(2) => \^cr_int_reg[31]_2\(1),
DI(1) => \^cr_int_reg[31]_2\(1),
DI(0) => \^cr_int_reg[31]_2\(1),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_104_n_0\,
S(2) => \cr_int[11]_i_105_n_0\,
S(1) => \cr_int[11]_i_106_n_0\,
S(0) => \cr_int[11]_i_107_n_0\
);
\cr_int_reg[11]_i_79\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_108_n_0\,
CO(3) => \cr_int_reg[11]_i_79_n_0\,
CO(2) => \cr_int_reg[11]_i_79_n_1\,
CO(1) => \cr_int_reg[11]_i_79_n_2\,
CO(0) => \cr_int_reg[11]_i_79_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[27]_2\(0),
DI(2) => \cr_int[11]_i_109_n_0\,
DI(1) => \cr_int[11]_i_110_n_0\,
DI(0) => \cr_int[11]_i_111_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_112_n_0\,
S(2) => \cr_int[11]_i_113_n_0\,
S(1) => \cr_int[11]_i_114_n_0\,
S(0) => \cr_int[11]_i_115_n_0\
);
\cr_int_reg[11]_i_92\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_116_n_0\,
CO(3) => \cr_int_reg[11]_i_92_n_0\,
CO(2) => \cr_int_reg[11]_i_92_n_1\,
CO(1) => \cr_int_reg[11]_i_92_n_2\,
CO(0) => \cr_int_reg[11]_i_92_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_117_n_0\,
DI(2) => \cr_int[11]_i_118_n_0\,
DI(1) => \cr_int[11]_i_119_n_0\,
DI(0) => \cr_int[11]_i_120_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_121_n_0\,
S(2) => \cr_int[11]_i_122_n_0\,
S(1) => \cr_int[11]_i_123_n_0\,
S(0) => \cr_int[11]_i_124_n_0\
);
\cr_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_7\,
Q => \cr_int_reg__0\(12),
R => '0'
);
\cr_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_6\,
Q => \cr_int_reg__0\(13),
R => '0'
);
\cr_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_5\,
Q => \cr_int_reg__0\(14),
R => '0'
);
\cr_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_4\,
Q => \cr_int_reg__0\(15),
R => '0'
);
\cr_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_1_n_0\,
CO(3) => \cr_int_reg[15]_i_1_n_0\,
CO(2) => \cr_int_reg[15]_i_1_n_1\,
CO(1) => \cr_int_reg[15]_i_1_n_2\,
CO(0) => \cr_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[15]_i_2_n_0\,
DI(2) => \cr_int[15]_i_3_n_0\,
DI(1) => \cr_int[15]_i_4_n_0\,
DI(0) => \cr_int[15]_i_5_n_0\,
O(3) => \cr_int_reg[15]_i_1_n_4\,
O(2) => \cr_int_reg[15]_i_1_n_5\,
O(1) => \cr_int_reg[15]_i_1_n_6\,
O(0) => \cr_int_reg[15]_i_1_n_7\,
S(3) => \cr_int[15]_i_6_n_0\,
S(2) => \cr_int[15]_i_7_n_0\,
S(1) => \cr_int[15]_i_8_n_0\,
S(0) => \cr_int[15]_i_9_n_0\
);
\cr_int_reg[15]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_19_n_0\,
CO(3) => \cr_int_reg[15]_i_20_n_0\,
CO(2) => \cr_int_reg[15]_i_20_n_1\,
CO(1) => \cr_int_reg[15]_i_20_n_2\,
CO(0) => \cr_int_reg[15]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(20 downto 17),
S(3) => \cr_int[15]_i_29_n_0\,
S(2) => \cr_int[15]_i_30_n_0\,
S(1) => \cr_int[15]_i_31_n_0\,
S(0) => \cr_int[15]_i_32_n_0\
);
\cr_int_reg[15]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_21_n_0\,
CO(3) => \cr_int_reg[15]_i_21_n_0\,
CO(2) => \cr_int_reg[15]_i_21_n_1\,
CO(1) => \cr_int_reg[15]_i_21_n_2\,
CO(0) => \cr_int_reg[15]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(12 downto 9),
S(3) => \cr_int[15]_i_33_n_0\,
S(2) => \cr_int[15]_i_34_n_0\,
S(1) => \cr_int[15]_i_35_n_0\,
S(0) => \cr_int[15]_i_36_n_0\
);
\cr_int_reg[15]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_29_n_0\,
CO(3) => \cr_int_reg[15]_i_28_n_0\,
CO(2) => \cr_int_reg[15]_i_28_n_1\,
CO(1) => \cr_int_reg[15]_i_28_n_2\,
CO(0) => \cr_int_reg[15]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[15]_0\(3 downto 0),
S(3) => \cr_int[15]_i_40_n_0\,
S(2) => \cr_int[15]_i_41_n_0\,
S(1) => \cr_int[15]_i_42_n_0\,
S(0) => \cr_int[15]_i_43_n_0\
);
\cr_int_reg[15]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_16_n_0\,
CO(3) => \cr_int_reg[15]_i_38_n_0\,
CO(2) => \cr_int_reg[15]_i_38_n_1\,
CO(1) => \cr_int_reg[15]_i_38_n_2\,
CO(0) => \cr_int_reg[15]_i_38_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_38_n_4\,
O(2) => \cr_int_reg[15]_i_38_n_5\,
O(1) => \cr_int_reg[15]_i_38_n_6\,
O(0) => \cr_int_reg[15]_i_38_n_7\,
S(3) => \cr_int[15]_i_48_n_0\,
S(2) => \cr_int[15]_i_49_n_0\,
S(1) => \cr_int[15]_i_50_n_0\,
S(0) => \cr_int[15]_i_51_n_0\
);
\cr_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_7\,
Q => \cr_int_reg__0\(16),
R => '0'
);
\cr_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_6\,
Q => \cr_int_reg__0\(17),
R => '0'
);
\cr_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_5\,
Q => \cr_int_reg__0\(18),
R => '0'
);
\cr_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_4\,
Q => \cr_int_reg__0\(19),
R => '0'
);
\cr_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_1_n_0\,
CO(3) => \cr_int_reg[19]_i_1_n_0\,
CO(2) => \cr_int_reg[19]_i_1_n_1\,
CO(1) => \cr_int_reg[19]_i_1_n_2\,
CO(0) => \cr_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[19]_i_2_n_0\,
DI(2) => \cr_int[19]_i_3_n_0\,
DI(1) => \cr_int[19]_i_4_n_0\,
DI(0) => \cr_int[19]_i_5_n_0\,
O(3) => \cr_int_reg[19]_i_1_n_4\,
O(2) => \cr_int_reg[19]_i_1_n_5\,
O(1) => \cr_int_reg[19]_i_1_n_6\,
O(0) => \cr_int_reg[19]_i_1_n_7\,
S(3) => \cr_int[19]_i_6_n_0\,
S(2) => \cr_int[19]_i_7_n_0\,
S(1) => \cr_int[19]_i_8_n_0\,
S(0) => \cr_int[19]_i_9_n_0\
);
\cr_int_reg[19]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_20_n_0\,
CO(3) => \cr_int_reg[19]_i_20_n_0\,
CO(2) => \cr_int_reg[19]_i_20_n_1\,
CO(1) => \cr_int_reg[19]_i_20_n_2\,
CO(0) => \cr_int_reg[19]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(24 downto 21),
S(3) => \cr_int[19]_i_29_n_0\,
S(2) => \cr_int[19]_i_30_n_0\,
S(1) => \cr_int[19]_i_31_n_0\,
S(0) => \cr_int[19]_i_32_n_0\
);
\cr_int_reg[19]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_21_n_0\,
CO(3) => \cr_int_reg[19]_i_21_n_0\,
CO(2) => \cr_int_reg[19]_i_21_n_1\,
CO(1) => \cr_int_reg[19]_i_21_n_2\,
CO(0) => \cr_int_reg[19]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(16 downto 13),
S(3) => \cr_int[19]_i_33_n_0\,
S(2) => \cr_int[19]_i_34_n_0\,
S(1) => \cr_int[19]_i_35_n_0\,
S(0) => \cr_int[19]_i_36_n_0\
);
\cr_int_reg[19]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_28_n_0\,
CO(3) => \cr_int_reg[19]_i_28_n_0\,
CO(2) => \cr_int_reg[19]_i_28_n_1\,
CO(1) => \cr_int_reg[19]_i_28_n_2\,
CO(0) => \cr_int_reg[19]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[19]_0\(3 downto 0),
S(3) => \cr_int[19]_i_38_n_0\,
S(2) => \cr_int[19]_i_39_n_0\,
S(1) => \cr_int[19]_i_40_n_0\,
S(0) => \cr_int[19]_i_41_n_0\
);
\cr_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_6\,
Q => \cr_int_reg_n_0_[1]\,
R => '0'
);
\cr_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_7\,
Q => \cr_int_reg__0\(20),
R => '0'
);
\cr_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_6\,
Q => \cr_int_reg__0\(21),
R => '0'
);
\cr_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_5\,
Q => \cr_int_reg__0\(22),
R => '0'
);
\cr_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_4\,
Q => \cr_int_reg__0\(23),
R => '0'
);
\cr_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_1_n_0\,
CO(3) => \cr_int_reg[23]_i_1_n_0\,
CO(2) => \cr_int_reg[23]_i_1_n_1\,
CO(1) => \cr_int_reg[23]_i_1_n_2\,
CO(0) => \cr_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[23]_i_2_n_0\,
DI(2) => \cr_int[23]_i_3_n_0\,
DI(1) => \cr_int[23]_i_4_n_0\,
DI(0) => \cr_int[23]_i_5_n_0\,
O(3) => \cr_int_reg[23]_i_1_n_4\,
O(2) => \cr_int_reg[23]_i_1_n_5\,
O(1) => \cr_int_reg[23]_i_1_n_6\,
O(0) => \cr_int_reg[23]_i_1_n_7\,
S(3) => \cr_int[23]_i_6_n_0\,
S(2) => \cr_int[23]_i_7_n_0\,
S(1) => \cr_int[23]_i_8_n_0\,
S(0) => \cr_int[23]_i_9_n_0\
);
\cr_int_reg[23]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_20_n_0\,
CO(3) => \cr_int_reg[23]_i_20_n_0\,
CO(2) => \cr_int_reg[23]_i_20_n_1\,
CO(1) => \cr_int_reg[23]_i_20_n_2\,
CO(0) => \cr_int_reg[23]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(28 downto 25),
S(3) => \cr_int[23]_i_27_n_0\,
S(2) => \cr_int[23]_i_28_n_0\,
S(1) => \cr_int[23]_i_29_n_0\,
S(0) => \cr_int[23]_i_30_n_0\
);
\cr_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_7\,
Q => \cr_int_reg__0\(24),
R => '0'
);
\cr_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_6\,
Q => \cr_int_reg__0\(25),
R => '0'
);
\cr_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_5\,
Q => \cr_int_reg__0\(26),
R => '0'
);
\cr_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_4\,
Q => \cr_int_reg__0\(27),
R => '0'
);
\cr_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_1_n_0\,
CO(3) => \cr_int_reg[27]_i_1_n_0\,
CO(2) => \cr_int_reg[27]_i_1_n_1\,
CO(1) => \cr_int_reg[27]_i_1_n_2\,
CO(0) => \cr_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_2_n_0\,
DI(2) => \cr_int[31]_i_2_n_0\,
DI(1) => \cr_int[31]_i_2_n_0\,
DI(0) => \cr_int[27]_i_2_n_0\,
O(3) => \cr_int_reg[27]_i_1_n_4\,
O(2) => \cr_int_reg[27]_i_1_n_5\,
O(1) => \cr_int_reg[27]_i_1_n_6\,
O(0) => \cr_int_reg[27]_i_1_n_7\,
S(3) => \cr_int[27]_i_3_n_0\,
S(2) => \cr_int[27]_i_4_n_0\,
S(1) => \cr_int[27]_i_5_n_0\,
S(0) => \cr_int[27]_i_6_n_0\
);
\cr_int_reg[27]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_20_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[27]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cr_int_reg6(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \cr_int[27]_i_12_n_0\,
S(0) => \cr_int[27]_i_13_n_0\
);
\cr_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_7\,
Q => \cr_int_reg__0\(28),
R => '0'
);
\cr_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_6\,
Q => \cr_int_reg__0\(29),
R => '0'
);
\cr_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_5\,
Q => \cr_int_reg_n_0_[2]\,
R => '0'
);
\cr_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_5\,
Q => \cr_int_reg__0\(30),
R => '0'
);
\cr_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_4\,
Q => \cr_int_reg__0\(31),
R => '0'
);
\cr_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_1_n_1\,
CO(1) => \cr_int_reg[31]_i_1_n_2\,
CO(0) => \cr_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cr_int[31]_i_2_n_0\,
DI(1) => \cr_int[31]_i_2_n_0\,
DI(0) => \cr_int[31]_i_2_n_0\,
O(3) => \cr_int_reg[31]_i_1_n_4\,
O(2) => \cr_int_reg[31]_i_1_n_5\,
O(1) => \cr_int_reg[31]_i_1_n_6\,
O(0) => \cr_int_reg[31]_i_1_n_7\,
S(3) => \cr_int[31]_i_3_n_0\,
S(2) => \cr_int[31]_i_4_n_0\,
S(1) => \cr_int[31]_i_5_n_0\,
S(0) => \cr_int[31]_i_6_n_0\
);
\cr_int_reg[31]_i_101\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_64_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_101_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_101_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => rgb888(15 downto 14),
O(3 downto 2) => \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_101_n_6\,
O(0) => \cr_int_reg[31]_i_101_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_121_n_0\,
S(0) => \cr_int[31]_i_122_n_0\
);
\cr_int_reg[31]_i_102\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_70_n_0\,
CO(3) => \cr_int_reg[31]_i_102_n_0\,
CO(2) => \cr_int_reg[31]_i_102_n_1\,
CO(1) => \cr_int_reg[31]_i_102_n_2\,
CO(0) => \cr_int_reg[31]_i_102_n_3\,
CYINIT => '0',
DI(3) => rgb888(14),
DI(2 downto 0) => rgb888(15 downto 13),
O(3) => \cr_int_reg[31]_i_102_n_4\,
O(2) => \cr_int_reg[31]_i_102_n_5\,
O(1) => \cr_int_reg[31]_i_102_n_6\,
O(0) => \cr_int_reg[31]_i_102_n_7\,
S(3) => \cr_int[31]_i_123_n_0\,
S(2) => \cr_int[31]_i_124_n_0\,
S(1) => \cr_int[31]_i_125_n_0\,
S(0) => \cr_int[31]_i_126_n_0\
);
\cr_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_11_n_1\,
CO(1) => \cr_int_reg[31]_i_11_n_2\,
CO(0) => \cr_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \cr_int[31]_i_31_n_0\,
O(3) => \cr_int_reg[31]_i_11_n_4\,
O(2) => \cr_int_reg[31]_i_11_n_5\,
O(1) => \cr_int_reg[31]_i_11_n_6\,
O(0) => \cr_int_reg[31]_i_11_n_7\,
S(3) => \cr_int[31]_i_32_n_0\,
S(2) => \cr_int[31]_i_33_n_0\,
S(1) => \cr_int[31]_i_34_n_0\,
S(0) => \cr_int[31]_i_35_n_0\
);
\cr_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_36_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cr_int_reg4(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_37_n_0\,
S(0) => \cr_int[31]_i_38_n_0\
);
\cr_int_reg[31]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_39_n_0\,
CO(3) => \cr_int_reg[31]_i_14_n_0\,
CO(2) => \cr_int_reg[31]_i_14_n_1\,
CO(1) => \cr_int_reg[31]_i_14_n_2\,
CO(0) => \cr_int_reg[31]_i_14_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_40_n_0\,
DI(2) => \cr_int[31]_i_41_n_0\,
DI(1) => \cr_int[31]_i_42_n_0\,
DI(0) => \cr_int[31]_i_43_n_0\,
O(3) => \cr_int_reg[31]_i_14_n_4\,
O(2) => \cr_int_reg[31]_i_14_n_5\,
O(1) => \cr_int_reg[31]_i_14_n_6\,
O(0) => \cr_int_reg[31]_i_14_n_7\,
S(3) => \cr_int[31]_i_44_n_0\,
S(2) => \cr_int[31]_i_45_n_0\,
S(1) => \cr_int[31]_i_46_n_0\,
S(0) => \cr_int[31]_i_47_n_0\
);
\cr_int_reg[31]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_49_n_0\,
CO(3) => \cr_int_reg[31]_i_21_n_0\,
CO(2) => \cr_int_reg[31]_i_21_n_1\,
CO(1) => \cr_int_reg[31]_i_21_n_2\,
CO(0) => \cr_int_reg[31]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_21_n_4\,
O(2) => \cr_int_reg[31]_i_21_n_5\,
O(1) => \cr_int_reg[31]_i_21_n_6\,
O(0) => \cr_int_reg[31]_i_21_n_7\,
S(3) => \cr_int[31]_i_50_n_0\,
S(2) => \cr_int[31]_i_51_n_0\,
S(1) => \cr_int[31]_i_52_n_0\,
S(0) => \cr_int[31]_i_53_n_0\
);
\cr_int_reg[31]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_19_n_0\,
CO(3) => \cr_int_reg[31]_i_24_n_0\,
CO(2) => \cr_int_reg[31]_i_24_n_1\,
CO(1) => \cr_int_reg[31]_i_24_n_2\,
CO(0) => \cr_int_reg[31]_i_24_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_55_n_0\,
DI(2) => \cr_int[31]_i_56_n_0\,
DI(1) => \cr_int[31]_i_57_n_0\,
DI(0) => \cr_int[31]_i_58_n_0\,
O(3 downto 0) => \^cr_int_reg[7]_0\(3 downto 0),
S(3) => \cr_int[31]_i_59_n_0\,
S(2) => \cr_int[31]_i_60_n_0\,
S(1) => \cr_int[31]_i_61_n_0\,
S(0) => \cr_int[31]_i_62_n_0\
);
\cr_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_16_n_0\,
CO(3) => \cr_int_reg[31]_i_30_n_0\,
CO(2) => \cr_int_reg[31]_i_30_n_1\,
CO(1) => \cr_int_reg[31]_i_30_n_2\,
CO(0) => \cr_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_71_n_0\,
DI(2) => \cr_int[31]_i_72_n_0\,
DI(1) => \cr_int[31]_i_73_n_0\,
DI(0) => \cr_int[31]_i_74_n_0\,
O(3) => \cr_int_reg[31]_i_30_n_4\,
O(2) => \cr_int_reg[31]_i_30_n_5\,
O(1) => \cr_int_reg[31]_i_30_n_6\,
O(0) => \cr_int_reg[31]_i_30_n_7\,
S(3) => \cr_int[31]_i_75_n_0\,
S(2) => \cr_int[31]_i_76_n_0\,
S(1) => \cr_int[31]_i_77_n_0\,
S(0) => \cr_int[31]_i_78_n_0\
);
\cr_int_reg[31]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_21_n_0\,
CO(3) => \cr_int_reg[31]_i_36_n_0\,
CO(2) => \cr_int_reg[31]_i_36_n_1\,
CO(1) => \cr_int_reg[31]_i_36_n_2\,
CO(0) => \cr_int_reg[31]_i_36_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(20 downto 17),
S(3) => \cr_int[31]_i_81_n_0\,
S(2) => \cr_int[31]_i_82_n_0\,
S(1) => \cr_int[31]_i_83_n_0\,
S(0) => \cr_int[31]_i_84_n_0\
);
\cr_int_reg[31]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[31]_i_39_n_0\,
CO(2) => \cr_int_reg[31]_i_39_n_1\,
CO(1) => \cr_int_reg[31]_i_39_n_2\,
CO(0) => \cr_int_reg[31]_i_39_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_85_n_0\,
DI(2) => rgb888(1),
DI(1) => \cr_int_reg[31]_i_86_n_4\,
DI(0) => '0',
O(3) => \cr_int_reg[31]_i_39_n_4\,
O(2) => \cr_int_reg[31]_i_39_n_5\,
O(1) => \cr_int_reg[31]_i_39_n_6\,
O(0) => \cr_int_reg[31]_i_39_n_7\,
S(3) => \cr_int[31]_i_87_n_0\,
S(2) => \cr_int[31]_i_88_n_0\,
S(1) => \cr_int[31]_i_89_n_0\,
S(0) => \cr_int[31]_i_90_n_0\
);
\cr_int_reg[31]_i_48\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_91_n_0\,
CO(3 downto 2) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cr_int_reg[31]_i_48_n_2\,
CO(0) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(7),
O(3 downto 1) => \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\(3 downto 1),
O(0) => \cr_int_reg[31]_i_48_n_7\,
S(3 downto 1) => B"001",
S(0) => \cr_int[31]_i_93_n_0\
);
\cr_int_reg[31]_i_49\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_38_n_0\,
CO(3) => \cr_int_reg[31]_i_49_n_0\,
CO(2) => \cr_int_reg[31]_i_49_n_1\,
CO(1) => \cr_int_reg[31]_i_49_n_2\,
CO(0) => \cr_int_reg[31]_i_49_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_49_n_4\,
O(2) => \cr_int_reg[31]_i_49_n_5\,
O(1) => \cr_int_reg[31]_i_49_n_6\,
O(0) => \cr_int_reg[31]_i_49_n_7\,
S(3) => \cr_int[31]_i_94_n_0\,
S(2) => \cr_int[31]_i_95_n_0\,
S(1) => \cr_int[31]_i_96_n_0\,
S(0) => \cr_int[31]_i_97_n_0\
);
\cr_int_reg[31]_i_63\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_102_n_0\,
CO(3 downto 2) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cr_int_reg[31]_i_63_n_2\,
CO(0) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(15),
O(3 downto 1) => \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\(3 downto 1),
O(0) => \cr_int_reg[31]_i_63_n_7\,
S(3 downto 1) => B"001",
S(0) => \cr_int[31]_i_103_n_0\
);
\cr_int_reg[31]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_70_n_0\,
CO(3 downto 0) => \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\(3 downto 1),
O(0) => \^cr_int_reg[23]_1\(0),
S(3 downto 1) => B"000",
S(0) => \cr_int[31]_i_108_n_0\
);
\cr_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_14_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_7_n_1\,
CO(1) => \cr_int_reg[31]_i_7_n_2\,
CO(0) => \cr_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cr_int[31]_i_15_n_0\,
DI(0) => \cr_int[31]_i_16_n_0\,
O(3) => \^cr_int_reg[27]_2\(0),
O(2) => \cr_int_reg[31]_i_7_n_5\,
O(1) => \cr_int_reg[31]_i_7_n_6\,
O(0) => \cr_int_reg[31]_i_7_n_7\,
S(3) => \cr_int[31]_i_17_n_0\,
S(2) => \cr_int[31]_i_18_n_0\,
S(1) => \cr_int[31]_i_19_n_0\,
S(0) => \cr_int[31]_i_20_n_0\
);
\cr_int_reg[31]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_28_n_0\,
CO(3) => \cr_int_reg[31]_i_70_n_0\,
CO(2) => \cr_int_reg[31]_i_70_n_1\,
CO(1) => \cr_int_reg[31]_i_70_n_2\,
CO(0) => \cr_int_reg[31]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[23]_0\(3 downto 0),
S(3) => \cr_int[31]_i_109_n_0\,
S(2) => \cr_int[31]_i_110_n_0\,
S(1) => \cr_int[31]_i_111_n_0\,
S(0) => \cr_int[31]_i_112_n_0\
);
\cr_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_21_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_8_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_8_n_6\,
O(0) => \cr_int_reg[31]_i_8_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_22_n_0\,
S(0) => \cr_int[31]_i_23_n_0\
);
\cr_int_reg[31]_i_86\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[31]_i_86_n_0\,
CO(2) => \cr_int_reg[31]_i_86_n_1\,
CO(1) => \cr_int_reg[31]_i_86_n_2\,
CO(0) => \cr_int_reg[31]_i_86_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(4 downto 2),
DI(0) => '0',
O(3) => \cr_int_reg[31]_i_86_n_4\,
O(2) => \cr_int_reg[31]_i_86_n_5\,
O(1) => \cr_int_reg[31]_i_86_n_6\,
O(0) => \cr_int_reg[31]_i_86_n_7\,
S(3) => \cr_int[31]_i_113_n_0\,
S(2) => \cr_int[31]_i_114_n_0\,
S(1) => \cr_int[31]_i_115_n_0\,
S(0) => \cr_int[31]_i_116_n_0\
);
\cr_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_24_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^di\(0),
O(3 downto 2) => \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \^cr_int_reg[31]_2\(1 downto 0),
S(3 downto 2) => B"00",
S(1) => \cr_int[31]_i_25_n_0\,
S(0) => \cr_int[31]_i_26_n_0\
);
\cr_int_reg[31]_i_91\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_86_n_0\,
CO(3) => \cr_int_reg[31]_i_91_n_0\,
CO(2) => \cr_int_reg[31]_i_91_n_1\,
CO(1) => \cr_int_reg[31]_i_91_n_2\,
CO(0) => \cr_int_reg[31]_i_91_n_3\,
CYINIT => '0',
DI(3) => rgb888(6),
DI(2 downto 0) => rgb888(7 downto 5),
O(3) => \cr_int_reg[31]_i_91_n_4\,
O(2) => \cr_int_reg[31]_i_91_n_5\,
O(1) => \cr_int_reg[31]_i_91_n_6\,
O(0) => \cr_int_reg[31]_i_91_n_7\,
S(3) => \cr_int[31]_i_117_n_0\,
S(2) => \cr_int[31]_i_118_n_0\,
S(1) => \cr_int[31]_i_119_n_0\,
S(0) => \cr_int[31]_i_120_n_0\
);
\cr_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_4\,
Q => \cr_int_reg_n_0_[3]\,
R => '0'
);
\cr_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_1_n_0\,
CO(2) => \cr_int_reg[3]_i_1_n_1\,
CO(1) => \cr_int_reg[3]_i_1_n_2\,
CO(0) => \cr_int_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3) => \cr_int[3]_i_2_n_0\,
DI(2) => \cr_int[3]_i_3_n_0\,
DI(1) => \cr_int[3]_i_4_n_0\,
DI(0) => '1',
O(3) => \cr_int_reg[3]_i_1_n_4\,
O(2) => \cr_int_reg[3]_i_1_n_5\,
O(1) => \cr_int_reg[3]_i_1_n_6\,
O(0) => \cr_int_reg[3]_i_1_n_7\,
S(3) => \cr_int[3]_i_5_n_0\,
S(2) => \cr_int[3]_i_6_n_0\,
S(1) => \cr_int[3]_i_7_n_0\,
S(0) => \cr_int[3]_i_8_n_0\
);
\cr_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_21_n_0\,
CO(3) => \cr_int_reg[3]_i_15_n_0\,
CO(2) => \cr_int_reg[3]_i_15_n_1\,
CO(1) => \cr_int_reg[3]_i_15_n_2\,
CO(0) => \cr_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => cr_int_reg6(8),
O(2 downto 0) => \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0),
S(3) => \cr_int[3]_i_22_n_0\,
S(2) => \cr_int[3]_i_23_n_0\,
S(1) => \cr_int[3]_i_24_n_0\,
S(0) => \cr_int[3]_i_25_n_0\
);
\cr_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_16_n_0\,
CO(2) => \cr_int_reg[3]_i_16_n_1\,
CO(1) => \cr_int_reg[3]_i_16_n_2\,
CO(0) => \cr_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[3]_i_26_n_6\,
DI(2) => \cr_int_reg[3]_i_26_n_7\,
DI(1) => \cr_int_reg[3]_i_27_n_4\,
DI(0) => '0',
O(3) => \cr_int_reg[3]_i_16_n_4\,
O(2) => \cr_int_reg[3]_i_16_n_5\,
O(1) => \cr_int_reg[3]_i_16_n_6\,
O(0) => \cr_int_reg[3]_i_16_n_7\,
S(3) => \cr_int[3]_i_28_n_0\,
S(2) => \cr_int[3]_i_29_n_0\,
S(1) => \cr_int[3]_i_30_n_0\,
S(0) => \cr_int[3]_i_31_n_0\
);
\cr_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_33_n_0\,
CO(3) => \cr_int_reg[3]_i_19_n_0\,
CO(2) => \cr_int_reg[3]_i_19_n_1\,
CO(1) => \cr_int_reg[3]_i_19_n_2\,
CO(0) => \cr_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \cr_int[3]_i_34_n_0\,
DI(2) => \cr_int[3]_i_35_n_0\,
DI(1) => \cr_int[3]_i_36_n_0\,
DI(0) => \cr_int[3]_i_37_n_0\,
O(3 downto 1) => \^cr_int_reg[3]_0\(2 downto 0),
O(0) => \cr_int_reg[3]_i_19_n_7\,
S(3) => \cr_int[3]_i_38_n_0\,
S(2) => \cr_int[3]_i_39_n_0\,
S(1) => \cr_int[3]_i_40_n_0\,
S(0) => \cr_int[3]_i_41_n_0\
);
\cr_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_42_n_0\,
CO(3) => \cr_int_reg[3]_i_20_n_0\,
CO(2) => \cr_int_reg[3]_i_20_n_1\,
CO(1) => \cr_int_reg[3]_i_20_n_2\,
CO(0) => \cr_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \^cr_int_reg[3]_2\(1 downto 0),
O(1 downto 0) => \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0),
S(3) => \cr_int[3]_i_43_n_0\,
S(2) => \cr_int[3]_i_44_n_0\,
S(1) => \cr_int[3]_i_45_n_0\,
S(0) => \cr_int[3]_i_46_n_0\
);
\cr_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_21_n_0\,
CO(2) => \cr_int_reg[3]_i_21_n_1\,
CO(1) => \cr_int_reg[3]_i_21_n_2\,
CO(0) => \cr_int_reg[3]_i_21_n_3\,
CYINIT => \cr_int[3]_i_47_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_48_n_0\,
S(2) => \cr_int[3]_i_49_n_0\,
S(1) => \cr_int[3]_i_50_n_0\,
S(0) => \cr_int[3]_i_51_n_0\
);
\cr_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_27_n_0\,
CO(3) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[3]_i_26_n_1\,
CO(1) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(23),
DI(0) => '0',
O(3 downto 2) => \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[3]_i_26_n_6\,
O(0) => \cr_int_reg[3]_i_26_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[3]_i_52_n_0\,
S(0) => \cr_int[3]_i_53_n_0\
);
\cr_int_reg[3]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_54_n_0\,
CO(3) => \cr_int_reg[3]_i_27_n_0\,
CO(2) => \cr_int_reg[3]_i_27_n_1\,
CO(1) => \cr_int_reg[3]_i_27_n_2\,
CO(0) => \cr_int_reg[3]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(21 downto 18),
O(3) => \cr_int_reg[3]_i_27_n_4\,
O(2) => \cr_int_reg[3]_i_27_n_5\,
O(1) => \cr_int_reg[3]_i_27_n_6\,
O(0) => \cr_int_reg[3]_i_27_n_7\,
S(3) => \cr_int[3]_i_55_n_0\,
S(2) => \cr_int[3]_i_56_n_0\,
S(1) => \cr_int[3]_i_57_n_0\,
S(0) => \cr_int[3]_i_58_n_0\
);
\cr_int_reg[3]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_59_n_0\,
CO(3) => \cr_int_reg[3]_i_32_n_0\,
CO(2) => \cr_int_reg[3]_i_32_n_1\,
CO(1) => \cr_int_reg[3]_i_32_n_2\,
CO(0) => \cr_int_reg[3]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[3]_i_32_n_4\,
O(2 downto 0) => \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0),
S(3) => \cr_int[3]_i_60_n_0\,
S(2) => \cr_int[3]_i_61_n_0\,
S(1) => \cr_int[3]_i_62_n_0\,
S(0) => \cr_int[3]_i_63_n_0\
);
\cr_int_reg[3]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_33_n_0\,
CO(2) => \cr_int_reg[3]_i_33_n_1\,
CO(1) => \cr_int_reg[3]_i_33_n_2\,
CO(0) => \cr_int_reg[3]_i_33_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[3]_i_64_n_6\,
DI(2) => \cr_int_reg[3]_i_64_n_7\,
DI(1) => \cr_int_reg[3]_i_65_n_4\,
DI(0) => \cr_int_reg[3]_i_65_n_5\,
O(3) => \cr_int_reg[3]_i_33_n_4\,
O(2) => \cr_int_reg[3]_i_33_n_5\,
O(1) => \cr_int_reg[3]_i_33_n_6\,
O(0) => \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\(0),
S(3) => \cr_int[3]_i_66_n_0\,
S(2) => \cr_int[3]_i_67_n_0\,
S(1) => \cr_int[3]_i_68_n_0\,
S(0) => \cr_int[3]_i_69_n_0\
);
\cr_int_reg[3]_i_42\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_42_n_0\,
CO(2) => \cr_int_reg[3]_i_42_n_1\,
CO(1) => \cr_int_reg[3]_i_42_n_2\,
CO(0) => \cr_int_reg[3]_i_42_n_3\,
CYINIT => \cr_int[3]_i_71_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_72_n_0\,
S(2) => \cr_int[3]_i_73_n_0\,
S(1) => \cr_int[3]_i_74_n_0\,
S(0) => \cr_int[3]_i_75_n_0\
);
\cr_int_reg[3]_i_54\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_54_n_0\,
CO(2) => \cr_int_reg[3]_i_54_n_1\,
CO(1) => \cr_int_reg[3]_i_54_n_2\,
CO(0) => \cr_int_reg[3]_i_54_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(17 downto 16),
DI(1 downto 0) => B"01",
O(3) => \cr_int_reg[3]_i_54_n_4\,
O(2) => \cr_int_reg[3]_i_54_n_5\,
O(1) => \cr_int_reg[3]_i_54_n_6\,
O(0) => \cr_int_reg[3]_i_54_n_7\,
S(3) => \cr_int[3]_i_76_n_0\,
S(2) => \cr_int[3]_i_77_n_0\,
S(1) => \cr_int[3]_i_78_n_0\,
S(0) => \cr_int[3]_i_79_n_0\
);
\cr_int_reg[3]_i_59\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_59_n_0\,
CO(2) => \cr_int_reg[3]_i_59_n_1\,
CO(1) => \cr_int_reg[3]_i_59_n_2\,
CO(0) => \cr_int_reg[3]_i_59_n_3\,
CYINIT => \cr_int[3]_i_80_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_81_n_0\,
S(2) => \cr_int[3]_i_82_n_0\,
S(1) => \cr_int[3]_i_83_n_0\,
S(0) => \cr_int[3]_i_84_n_0\
);
\cr_int_reg[3]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_65_n_0\,
CO(3) => \cr_int_reg[3]_i_64_n_0\,
CO(2) => \cr_int_reg[3]_i_64_n_1\,
CO(1) => \cr_int_reg[3]_i_64_n_2\,
CO(0) => \cr_int_reg[3]_i_64_n_3\,
CYINIT => '0',
DI(3) => rgb888(15),
DI(2 downto 0) => rgb888(12 downto 10),
O(3) => \cr_int_reg[3]_i_64_n_4\,
O(2) => \cr_int_reg[3]_i_64_n_5\,
O(1) => \cr_int_reg[3]_i_64_n_6\,
O(0) => \cr_int_reg[3]_i_64_n_7\,
S(3) => \cr_int[3]_i_85_n_0\,
S(2) => \cr_int[3]_i_86_n_0\,
S(1) => \cr_int[3]_i_87_n_0\,
S(0) => \cr_int[3]_i_88_n_0\
);
\cr_int_reg[3]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_65_n_0\,
CO(2) => \cr_int_reg[3]_i_65_n_1\,
CO(1) => \cr_int_reg[3]_i_65_n_2\,
CO(0) => \cr_int_reg[3]_i_65_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(9 downto 8),
DI(1 downto 0) => B"01",
O(3) => \cr_int_reg[3]_i_65_n_4\,
O(2) => \cr_int_reg[3]_i_65_n_5\,
O(1) => \cr_int_reg[3]_i_65_n_6\,
O(0) => \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\(0),
S(3) => \cr_int[3]_i_89_n_0\,
S(2) => \cr_int[3]_i_90_n_0\,
S(1) => \cr_int[3]_i_91_n_0\,
S(0) => \cr_int[3]_i_92_n_0\
);
\cr_int_reg[3]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_70_n_0\,
CO(2) => \cr_int_reg[3]_i_70_n_1\,
CO(1) => \cr_int_reg[3]_i_70_n_2\,
CO(0) => \cr_int_reg[3]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(12 downto 10),
DI(0) => '0',
O(3) => \cr_int_reg[3]_i_70_n_4\,
O(2) => \cr_int_reg[3]_i_70_n_5\,
O(1) => \cr_int_reg[3]_i_70_n_6\,
O(0) => \cr_int_reg[3]_i_70_n_7\,
S(3) => \cr_int[3]_i_93_n_0\,
S(2) => \cr_int[3]_i_94_n_0\,
S(1) => \cr_int[3]_i_95_n_0\,
S(0) => \cr_int[3]_i_96_n_0\
);
\cr_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_7\,
Q => \cr_int_reg_n_0_[4]\,
R => '0'
);
\cr_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_6\,
Q => \cr_int_reg_n_0_[5]\,
R => '0'
);
\cr_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_5\,
Q => \cr_int_reg_n_0_[6]\,
R => '0'
);
\cr_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_4\,
Q => \cr_int_reg_n_0_[7]\,
R => '0'
);
\cr_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_1_n_0\,
CO(3) => \cr_int_reg[7]_i_1_n_0\,
CO(2) => \cr_int_reg[7]_i_1_n_1\,
CO(1) => \cr_int_reg[7]_i_1_n_2\,
CO(0) => \cr_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[7]_i_2_n_0\,
DI(2) => \cr_int[7]_i_3_n_0\,
DI(1) => \cr_int[7]_i_4_n_0\,
DI(0) => \cr_int[7]_i_5_n_0\,
O(3) => \cr_int_reg[7]_i_1_n_4\,
O(2) => \cr_int_reg[7]_i_1_n_5\,
O(1) => \cr_int_reg[7]_i_1_n_6\,
O(0) => \cr_int_reg[7]_i_1_n_7\,
S(3) => \cr_int[7]_i_6_n_0\,
S(2) => \cr_int[7]_i_7_n_0\,
S(1) => \cr_int[7]_i_8_n_0\,
S(0) => \cr_int[7]_i_9_n_0\
);
\cr_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_20_n_0\,
CO(3) => \cr_int_reg[7]_i_23_n_0\,
CO(2) => \cr_int_reg[7]_i_23_n_1\,
CO(1) => \cr_int_reg[7]_i_23_n_2\,
CO(0) => \cr_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[7]_1\(3 downto 0),
S(3) => \cr_int[7]_i_25_n_0\,
S(2) => \cr_int[7]_i_26_n_0\,
S(1) => \cr_int[7]_i_27_n_0\,
S(0) => \cr_int[7]_i_28_n_0\
);
\cr_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_7\,
Q => \cr_int_reg__0\(8),
R => '0'
);
\cr_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_6\,
Q => \cr_int_reg__0\(9),
R => '0'
);
\cr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[0]_i_1_n_0\,
Q => cr(0),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[1]_i_1_n_0\,
Q => cr(1),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[2]_i_1_n_0\,
Q => cr(2),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[3]_i_1_n_0\,
Q => cr(3),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[4]_i_1_n_0\,
Q => cr(4),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[5]_i_1_n_0\,
Q => cr(5),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[6]_i_1_n_0\,
Q => cr(6),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[7]_i_2_n_0\,
Q => cr(7),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_reg[7]_i_3_n_0\,
CO(3) => \cr_reg[7]_i_1_n_0\,
CO(2) => \cr_reg[7]_i_1_n_1\,
CO(1) => \cr_reg[7]_i_1_n_2\,
CO(0) => \cr_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_4_n_0\,
DI(2) => \cr[7]_i_5_n_0\,
DI(1) => \cr[7]_i_6_n_0\,
DI(0) => \cr[7]_i_7_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_8_n_0\,
S(2) => \cr[7]_i_9_n_0\,
S(1) => \cr[7]_i_10_n_0\,
S(0) => \cr[7]_i_11_n_0\
);
\cr_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_reg[7]_i_12_n_0\,
CO(2) => \cr_reg[7]_i_12_n_1\,
CO(1) => \cr_reg[7]_i_12_n_2\,
CO(0) => \cr_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_21_n_0\,
DI(2) => \cr[7]_i_22_n_0\,
DI(1) => \cr[7]_i_23_n_0\,
DI(0) => \cr[7]_i_24_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_25_n_0\,
S(2) => \cr[7]_i_26_n_0\,
S(1) => \cr[7]_i_27_n_0\,
S(0) => \cr[7]_i_28_n_0\
);
\cr_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \cr_reg[7]_i_12_n_0\,
CO(3) => \cr_reg[7]_i_3_n_0\,
CO(2) => \cr_reg[7]_i_3_n_1\,
CO(1) => \cr_reg[7]_i_3_n_2\,
CO(0) => \cr_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_13_n_0\,
DI(2) => \cr[7]_i_14_n_0\,
DI(1) => \cr[7]_i_15_n_0\,
DI(0) => \cr[7]_i_16_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_17_n_0\,
S(2) => \cr[7]_i_18_n_0\,
S(1) => \cr[7]_i_19_n_0\,
S(0) => \cr[7]_i_20_n_0\
);
edge_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => edge,
O => edge_i_1_n_0
);
edge_rb_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => edge,
I1 => edge_rb,
O => edge_rb_i_1_n_0
);
edge_rb_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => edge_rb_i_1_n_0,
Q => edge_rb,
R => \hdmi_d[15]_i_1_n_0\
);
edge_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => edge_i_1_n_0,
Q => edge,
R => '0'
);
\hdmi_clk_bits_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => edge_i_1_n_0,
Q => D1,
R => '0'
);
\hdmi_d[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(2),
I1 => \cr_hold_reg_n_0_[2]\,
I2 => y_hold(2),
I3 => edge_rb,
I4 => y(2),
I5 => edge,
O => \hdmi_d[10]_i_1_n_0\
);
\hdmi_d[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(3),
I1 => \cr_hold_reg_n_0_[3]\,
I2 => y_hold(3),
I3 => edge_rb,
I4 => y(3),
I5 => edge,
O => \hdmi_d[11]_i_1_n_0\
);
\hdmi_d[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(4),
I1 => \cr_hold_reg_n_0_[4]\,
I2 => y_hold(4),
I3 => edge_rb,
I4 => y(4),
I5 => edge,
O => \hdmi_d[12]_i_1_n_0\
);
\hdmi_d[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(5),
I1 => \cr_hold_reg_n_0_[5]\,
I2 => y_hold(5),
I3 => edge_rb,
I4 => y(5),
I5 => edge,
O => \hdmi_d[13]_i_1_n_0\
);
\hdmi_d[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(6),
I1 => \cr_hold_reg_n_0_[6]\,
I2 => y_hold(6),
I3 => edge_rb,
I4 => y(6),
I5 => edge,
O => \hdmi_d[14]_i_1_n_0\
);
\hdmi_d[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active,
O => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(7),
I1 => \cr_hold_reg_n_0_[7]\,
I2 => y_hold(7),
I3 => edge_rb,
I4 => y(7),
I5 => edge,
O => \hdmi_d[15]_i_2_n_0\
);
\hdmi_d[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(0),
I1 => \cr_hold_reg_n_0_[0]\,
I2 => y_hold(0),
I3 => edge_rb,
I4 => y(0),
I5 => edge,
O => \hdmi_d[8]_i_1_n_0\
);
\hdmi_d[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(1),
I1 => \cr_hold_reg_n_0_[1]\,
I2 => y_hold(1),
I3 => edge_rb,
I4 => y(1),
I5 => edge,
O => \hdmi_d[9]_i_1_n_0\
);
\hdmi_d_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[10]_i_1_n_0\,
Q => hdmi_d(2),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[11]_i_1_n_0\,
Q => hdmi_d(3),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[12]_i_1_n_0\,
Q => hdmi_d(4),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[13]_i_1_n_0\,
Q => hdmi_d(5),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[14]_i_1_n_0\,
Q => hdmi_d(6),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[15]_i_2_n_0\,
Q => hdmi_d(7),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[8]_i_1_n_0\,
Q => hdmi_d(0),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[9]_i_1_n_0\,
Q => hdmi_d(1),
R => \hdmi_d[15]_i_1_n_0\
);
hdmi_de_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => active,
Q => hdmi_de,
R => '0'
);
hdmi_hsync_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hsync,
O => p_0_in
);
hdmi_hsync_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => p_0_in,
Q => hdmi_hsync,
R => '0'
);
hdmi_vsync_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => vsync,
O => hdmi_vsync_i_1_n_0
);
hdmi_vsync_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => hdmi_vsync_i_1_n_0,
Q => hdmi_vsync,
R => '0'
);
\y[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[0]\,
I1 => \y_int_reg__0\(31),
O => \y[0]_i_1_n_0\
);
\y[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[1]\,
I1 => \y_int_reg__0\(31),
O => \y[1]_i_1_n_0\
);
\y[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[2]\,
I1 => \y_int_reg__0\(31),
O => \y[2]_i_1_n_0\
);
\y[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[3]\,
I1 => \y_int_reg__0\(31),
O => \y[3]_i_1_n_0\
);
\y[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[4]\,
I1 => \y_int_reg__0\(31),
O => \y[4]_i_1_n_0\
);
\y[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[5]\,
I1 => \y_int_reg__0\(31),
O => \y[5]_i_1_n_0\
);
\y[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[6]\,
I1 => \y_int_reg__0\(31),
O => \y[6]_i_1_n_0\
);
\y[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(26),
I1 => \y_int_reg__0\(27),
O => \y[7]_i_10_n_0\
);
\y[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(24),
I1 => \y_int_reg__0\(25),
O => \y[7]_i_11_n_0\
);
\y[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(22),
I1 => \y_int_reg__0\(23),
O => \y[7]_i_13_n_0\
);
\y[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(20),
I1 => \y_int_reg__0\(21),
O => \y[7]_i_14_n_0\
);
\y[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(18),
I1 => \y_int_reg__0\(19),
O => \y[7]_i_15_n_0\
);
\y[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(16),
I1 => \y_int_reg__0\(17),
O => \y[7]_i_16_n_0\
);
\y[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(22),
I1 => \y_int_reg__0\(23),
O => \y[7]_i_17_n_0\
);
\y[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(20),
I1 => \y_int_reg__0\(21),
O => \y[7]_i_18_n_0\
);
\y[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(18),
I1 => \y_int_reg__0\(19),
O => \y[7]_i_19_n_0\
);
\y[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[7]\,
I1 => \y_int_reg__0\(31),
O => \y[7]_i_2_n_0\
);
\y[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(16),
I1 => \y_int_reg__0\(17),
O => \y[7]_i_20_n_0\
);
\y[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(14),
I1 => \y_int_reg__0\(15),
O => \y[7]_i_21_n_0\
);
\y[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(12),
I1 => \y_int_reg__0\(13),
O => \y[7]_i_22_n_0\
);
\y[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(10),
I1 => \y_int_reg__0\(11),
O => \y[7]_i_23_n_0\
);
\y[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(8),
I1 => \y_int_reg__0\(9),
O => \y[7]_i_24_n_0\
);
\y[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(14),
I1 => \y_int_reg__0\(15),
O => \y[7]_i_25_n_0\
);
\y[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(12),
I1 => \y_int_reg__0\(13),
O => \y[7]_i_26_n_0\
);
\y[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(10),
I1 => \y_int_reg__0\(11),
O => \y[7]_i_27_n_0\
);
\y[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(8),
I1 => \y_int_reg__0\(9),
O => \y[7]_i_28_n_0\
);
\y[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg__0\(30),
I1 => \y_int_reg__0\(31),
O => \y[7]_i_4_n_0\
);
\y[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(28),
I1 => \y_int_reg__0\(29),
O => \y[7]_i_5_n_0\
);
\y[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(26),
I1 => \y_int_reg__0\(27),
O => \y[7]_i_6_n_0\
);
\y[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(24),
I1 => \y_int_reg__0\(25),
O => \y[7]_i_7_n_0\
);
\y[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(30),
I1 => \y_int_reg__0\(31),
O => \y[7]_i_8_n_0\
);
\y[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(28),
I1 => \y_int_reg__0\(29),
O => \y[7]_i_9_n_0\
);
\y_hold[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(0),
I1 => y(0),
I2 => edge_rb,
O => p_1_in(0)
);
\y_hold[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(1),
I1 => y(1),
I2 => edge_rb,
O => p_1_in(1)
);
\y_hold[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(2),
I1 => y(2),
I2 => edge_rb,
O => p_1_in(2)
);
\y_hold[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(3),
I1 => y(3),
I2 => edge_rb,
O => p_1_in(3)
);
\y_hold[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(4),
I1 => y(4),
I2 => edge_rb,
O => p_1_in(4)
);
\y_hold[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(5),
I1 => y(5),
I2 => edge_rb,
O => p_1_in(5)
);
\y_hold[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(6),
I1 => y(6),
I2 => edge_rb,
O => p_1_in(6)
);
\y_hold[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(7),
I1 => y(7),
I2 => edge_rb,
O => p_1_in(7)
);
\y_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(0),
Q => y_hold(0),
R => '0'
);
\y_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(1),
Q => y_hold(1),
R => '0'
);
\y_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(2),
Q => y_hold(2),
R => '0'
);
\y_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(3),
Q => y_hold(3),
R => '0'
);
\y_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(4),
Q => y_hold(4),
R => '0'
);
\y_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(5),
Q => y_hold(5),
R => '0'
);
\y_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(6),
Q => y_hold(6),
R => '0'
);
\y_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(7),
Q => y_hold(7),
R => '0'
);
\y_int[11]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[11]_i_10_n_0\
);
\y_int[11]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
I1 => rgb888(0),
O => \y_int[11]_i_100_n_0\
);
\y_int[11]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(1),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(10)
);
\y_int[11]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_22\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[11]_i_12_n_0\
);
\y_int[11]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(0),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(9)
);
\y_int[11]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_21\(1),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(2),
O => \y_int[11]_i_16_n_0\
);
\y_int[11]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(8),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_4\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(8)
);
\y_int[11]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(7),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_8_n_6\,
I3 => y_int_reg6,
I4 => y_int_reg5(15),
O => y_int_reg20_in(7)
);
\y_int[11]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_21\(0),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(1),
O => \y_int[11]_i_19_n_0\
);
\y_int[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(18),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(10),
I4 => \y_int[11]_i_10_n_0\,
I5 => y_int_reg1(10),
O => \y_int[11]_i_2_n_0\
);
\y_int[11]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(11),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(19),
I3 => y_int_reg6,
O => y_int_reg20_in(11)
);
\y_int[11]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(10),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(18),
I3 => y_int_reg6,
O => y_int_reg20_in(10)
);
\y_int[11]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(9),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(17),
I3 => y_int_reg6,
O => y_int_reg20_in(9)
);
\y_int[11]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(8),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(16),
I3 => y_int_reg6,
O => y_int_reg20_in(8)
);
\y_int[11]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[11]_i_29_n_0\
);
\y_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(17),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(9),
I4 => \y_int[11]_i_12_n_0\,
I5 => y_int_reg1(9),
O => \y_int[11]_i_3_n_0\
);
\y_int[11]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[11]_i_30_n_0\
);
\y_int[11]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[11]_i_31_n_0\
);
\y_int[11]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[11]_i_32_n_0\
);
\y_int[11]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(16),
O => \y_int[11]_i_34_n_0\
);
\y_int[11]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(15),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[11]_i_35_n_0\
);
\y_int[11]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(14),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[11]_i_36_n_0\
);
\y_int[11]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(13),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[11]_i_37_n_0\
);
\y_int[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(16),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(8),
I4 => \y_int[11]_i_16_n_0\,
I5 => y_int_reg1(8),
O => \y_int[11]_i_4_n_0\
);
\y_int[11]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_4\,
O => \y_int[11]_i_40_n_0\
);
\y_int[11]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_5\,
O => \y_int[11]_i_41_n_0\
);
\y_int[11]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_6\,
O => \y_int[11]_i_42_n_0\
);
\y_int[11]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_21_n_7\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_43_n_0\
);
\y_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_45_n_0\
);
\y_int[11]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_46_n_0\
);
\y_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_47_n_0\
);
\y_int[11]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_48_n_0\
);
\y_int[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"E888E888E8EEE888"
)
port map (
I0 => y_int_reg20_in(7),
I1 => \y_int[11]_i_19_n_0\,
I2 => y_int_reg2(7),
I3 => \^y_int_reg[23]_0\(0),
I4 => \y_int_reg[11]_i_21_n_5\,
I5 => \^y_int_reg[7]_0\(0),
O => \y_int[11]_i_5_n_0\
);
\y_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_50_n_0\
);
\y_int[11]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_51_n_0\
);
\y_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_52_n_0\
);
\y_int[11]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_53_n_0\
);
\y_int[11]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[11]_i_58_n_0\
);
\y_int[11]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[11]_i_59_n_0\
);
\y_int[11]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_2_n_0\,
I1 => y_int_reg1(11),
I2 => \y_int[15]_i_18_n_0\,
I3 => y_int_reg20_in(11),
O => \y_int[11]_i_6_n_0\
);
\y_int[11]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[11]_i_60_n_0\
);
\y_int[11]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[11]_i_61_n_0\
);
\y_int[11]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[11]_i_62_n_0\
);
\y_int[11]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(12),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[11]_i_63_n_0\
);
\y_int[11]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(11),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[11]_i_64_n_0\
);
\y_int[11]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(10),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[11]_i_65_n_0\
);
\y_int[11]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(9),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[11]_i_66_n_0\
);
\y_int[11]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_21\(1),
O => \y_int[11]_i_67_n_0\
);
\y_int[11]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_21\(0),
O => \y_int[11]_i_68_n_0\
);
\y_int[11]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(3),
O => \y_int[11]_i_69_n_0\
);
\y_int[11]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_3_n_0\,
I1 => y_int_reg1(10),
I2 => \y_int[11]_i_10_n_0\,
I3 => y_int_reg20_in(10),
O => \y_int[11]_i_7_n_0\
);
\y_int[11]_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(3),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(2),
O => \y_int[11]_i_70_n_0\
);
\y_int[11]_i_71\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[3]_i_35_n_4\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[11]_i_71_n_0\
);
\y_int[11]_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_4\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_72_n_0\
);
\y_int[11]_i_73\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_5\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_73_n_0\
);
\y_int[11]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_6\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_74_n_0\
);
\y_int[11]_i_75\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_7\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_75_n_0\
);
\y_int[11]_i_76\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_76_n_0\
);
\y_int[11]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_77_n_0\
);
\y_int[11]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_78_n_0\
);
\y_int[11]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_79_n_0\
);
\y_int[11]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_4_n_0\,
I1 => y_int_reg1(9),
I2 => \y_int[11]_i_12_n_0\,
I3 => y_int_reg20_in(9),
O => \y_int[11]_i_8_n_0\
);
\y_int[11]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_81_n_0\
);
\y_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_82_n_0\
);
\y_int[11]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_83_n_0\
);
\y_int[11]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_84_n_0\
);
\y_int[11]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_11_n_6\,
I1 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_86_n_0\
);
\y_int[11]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_30_n_4\,
I1 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_87_n_0\
);
\y_int[11]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
I1 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_88_n_0\
);
\y_int[11]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_89_n_0\
);
\y_int[11]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_5_n_0\,
I1 => y_int_reg1(8),
I2 => \y_int[11]_i_16_n_0\,
I3 => y_int_reg20_in(8),
O => \y_int[11]_i_9_n_0\
);
\y_int[11]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_5\,
I1 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_90_n_0\
);
\y_int[11]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_7\,
I1 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_91_n_0\
);
\y_int[11]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_5\,
I1 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[11]_i_92_n_0\
);
\y_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_62_n_4\,
I1 => \y_int_reg[31]_i_30_n_7\,
O => \y_int[11]_i_93_n_0\
);
\y_int[11]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_62_n_6\,
I1 => \y_int_reg[31]_i_62_n_5\,
O => \y_int[11]_i_94_n_0\
);
\y_int[11]_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \y_int_reg[31]_i_88_n_6\,
I1 => \y_int_reg[31]_i_88_n_5\,
I2 => rgb888(0),
O => \y_int[11]_i_95_n_0\
);
\y_int[11]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(0),
I1 => rgb888(1),
O => \y_int[11]_i_96_n_0\
);
\y_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_7\,
I1 => \y_int_reg[31]_i_62_n_4\,
O => \y_int[11]_i_97_n_0\
);
\y_int[11]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_5\,
I1 => \y_int_reg[31]_i_62_n_6\,
O => \y_int[11]_i_98_n_0\
);
\y_int[11]_i_99\: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => rgb888(0),
I1 => \y_int_reg[31]_i_88_n_5\,
I2 => \y_int_reg[31]_i_88_n_6\,
O => \y_int[11]_i_99_n_0\
);
\y_int[15]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_10_n_0\
);
\y_int[15]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(5),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(14)
);
\y_int[15]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_12_n_0\
);
\y_int[15]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(4),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(13)
);
\y_int[15]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_16_n_0\
);
\y_int[15]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(3),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(12)
);
\y_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_18_n_0\
);
\y_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(2),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(11)
);
\y_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(22),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(14),
I4 => \y_int[15]_i_10_n_0\,
I5 => y_int_reg1(14),
O => \y_int[15]_i_2_n_0\
);
\y_int[15]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(15),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(23),
I3 => y_int_reg6,
O => y_int_reg20_in(15)
);
\y_int[15]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(14),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(22),
I3 => y_int_reg6,
O => y_int_reg20_in(14)
);
\y_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(13),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(21),
I3 => y_int_reg6,
O => y_int_reg20_in(13)
);
\y_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(12),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(20),
I3 => y_int_reg6,
O => y_int_reg20_in(12)
);
\y_int[15]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_25_n_0\
);
\y_int[15]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_26_n_0\
);
\y_int[15]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_27_n_0\
);
\y_int[15]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_28_n_0\
);
\y_int[15]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(20),
O => \y_int[15]_i_29_n_0\
);
\y_int[15]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(21),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(13),
I4 => \y_int[15]_i_12_n_0\,
I5 => y_int_reg1(13),
O => \y_int[15]_i_3_n_0\
);
\y_int[15]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(19),
O => \y_int[15]_i_30_n_0\
);
\y_int[15]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(18),
O => \y_int[15]_i_31_n_0\
);
\y_int[15]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(17),
O => \y_int[15]_i_32_n_0\
);
\y_int[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(20),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(12),
I4 => \y_int[15]_i_16_n_0\,
I5 => y_int_reg1(12),
O => \y_int[15]_i_4_n_0\
);
\y_int[15]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(2),
O => \y_int[15]_i_40_n_0\
);
\y_int[15]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(1),
O => \y_int[15]_i_41_n_0\
);
\y_int[15]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(0),
O => \y_int[15]_i_42_n_0\
);
\y_int[15]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_22\(3),
O => \y_int[15]_i_43_n_0\
);
\y_int[15]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_48_n_0\
);
\y_int[15]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_49_n_0\
);
\y_int[15]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(19),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(11),
I4 => \y_int[15]_i_18_n_0\,
I5 => y_int_reg1(11),
O => \y_int[15]_i_5_n_0\
);
\y_int[15]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_50_n_0\
);
\y_int[15]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_51_n_0\
);
\y_int[15]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_2_n_0\,
I1 => y_int_reg1(15),
I2 => \y_int[19]_i_18_n_0\,
I3 => y_int_reg20_in(15),
O => \y_int[15]_i_6_n_0\
);
\y_int[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_3_n_0\,
I1 => y_int_reg1(14),
I2 => \y_int[15]_i_10_n_0\,
I3 => y_int_reg20_in(14),
O => \y_int[15]_i_7_n_0\
);
\y_int[15]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_4_n_0\,
I1 => y_int_reg1(13),
I2 => \y_int[15]_i_12_n_0\,
I3 => y_int_reg20_in(13),
O => \y_int[15]_i_8_n_0\
);
\y_int[15]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_5_n_0\,
I1 => y_int_reg1(12),
I2 => \y_int[15]_i_16_n_0\,
I3 => y_int_reg20_in(12),
O => \y_int[15]_i_9_n_0\
);
\y_int[19]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_10_n_0\
);
\y_int[19]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(9),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(18)
);
\y_int[19]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_12_n_0\
);
\y_int[19]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(8),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(17)
);
\y_int[19]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(3),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_16_n_0\
);
\y_int[19]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(7),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(16)
);
\y_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(2),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_18_n_0\
);
\y_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(6),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(15)
);
\y_int[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(26),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(18),
I4 => \y_int[19]_i_10_n_0\,
I5 => y_int_reg1(18),
O => \y_int[19]_i_2_n_0\
);
\y_int[19]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(19),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(27),
I3 => y_int_reg6,
O => y_int_reg20_in(19)
);
\y_int[19]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(18),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(26),
I3 => y_int_reg6,
O => y_int_reg20_in(18)
);
\y_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(17),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(25),
I3 => y_int_reg6,
O => y_int_reg20_in(17)
);
\y_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(16),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(24),
I3 => y_int_reg6,
O => y_int_reg20_in(16)
);
\y_int[19]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_25_n_0\
);
\y_int[19]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_26_n_0\
);
\y_int[19]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_27_n_0\
);
\y_int[19]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_28_n_0\
);
\y_int[19]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(24),
O => \y_int[19]_i_29_n_0\
);
\y_int[19]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(25),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(17),
I4 => \y_int[19]_i_12_n_0\,
I5 => y_int_reg1(17),
O => \y_int[19]_i_3_n_0\
);
\y_int[19]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(23),
O => \y_int[19]_i_30_n_0\
);
\y_int[19]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(22),
O => \y_int[19]_i_31_n_0\
);
\y_int[19]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(21),
O => \y_int[19]_i_32_n_0\
);
\y_int[19]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(24),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(16),
I4 => \y_int[19]_i_16_n_0\,
I5 => y_int_reg1(16),
O => \y_int[19]_i_4_n_0\
);
\y_int[19]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_48_n_0\
);
\y_int[19]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_49_n_0\
);
\y_int[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(23),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(15),
I4 => \y_int[19]_i_18_n_0\,
I5 => y_int_reg1(15),
O => \y_int[19]_i_5_n_0\
);
\y_int[19]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_50_n_0\
);
\y_int[19]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_51_n_0\
);
\y_int[19]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_2_n_0\,
I1 => y_int_reg1(19),
I2 => \y_int[23]_i_20_n_0\,
I3 => y_int_reg20_in(19),
O => \y_int[19]_i_6_n_0\
);
\y_int[19]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_3_n_0\,
I1 => y_int_reg1(18),
I2 => \y_int[19]_i_10_n_0\,
I3 => y_int_reg20_in(18),
O => \y_int[19]_i_7_n_0\
);
\y_int[19]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_4_n_0\,
I1 => y_int_reg1(17),
I2 => \y_int[19]_i_12_n_0\,
I3 => y_int_reg20_in(17),
O => \y_int[19]_i_8_n_0\
);
\y_int[19]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_5_n_0\,
I1 => y_int_reg1(16),
I2 => \y_int[19]_i_16_n_0\,
I3 => y_int_reg20_in(16),
O => \y_int[19]_i_9_n_0\
);
\y_int[23]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_19\(0),
I1 => \^y_int_reg[3]_0\(0),
O => \y_int[23]_i_100_n_0\
);
\y_int[23]_i_101\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[14]\(0),
I1 => \^y_int_reg[3]_0\(3),
O => \y_int[23]_i_101_n_0\
);
\y_int[23]_i_102\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[3]_0\(2),
I1 => \^y_int_reg[3]_0\(1),
O => \y_int[23]_i_102_n_0\
);
\y_int[23]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[3]_0\(0),
I1 => \rgb888[8]_19\(0),
O => \y_int[23]_i_103_n_0\
);
\y_int[23]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(8),
O => \y_int[23]_i_104_n_0\
);
\y_int[23]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_23\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_24\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_12_n_0\
);
\y_int[23]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(13),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_1\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(22)
);
\y_int[23]_i_14\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_23\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_14_n_0\
);
\y_int[23]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(12),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_1\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(21)
);
\y_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(3),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_18_n_0\
);
\y_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(11),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(20)
);
\y_int[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(30),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(22),
I4 => \y_int[23]_i_12_n_0\,
I5 => y_int_reg1(22),
O => \y_int[23]_i_2_n_0\
);
\y_int[23]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(2),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_20_n_0\
);
\y_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(10),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(19)
);
\y_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(22),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(30),
I3 => y_int_reg6,
O => y_int_reg20_in(22)
);
\y_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(21),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(29),
I3 => y_int_reg6,
O => y_int_reg20_in(21)
);
\y_int[23]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(20),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(28),
I3 => y_int_reg6,
O => y_int_reg20_in(20)
);
\y_int[23]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_26_n_0\
);
\y_int[23]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_27_n_0\
);
\y_int[23]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_28_n_0\
);
\y_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_29_n_0\
);
\y_int[23]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(29),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(21),
I4 => \y_int[23]_i_14_n_0\,
I5 => y_int_reg1(21),
O => \y_int[23]_i_3_n_0\
);
\y_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_30_n_0\
);
\y_int[23]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_31_n_0\
);
\y_int[23]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_36_n_0\
);
\y_int[23]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_37_n_0\
);
\y_int[23]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_38_n_0\
);
\y_int[23]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_39_n_0\
);
\y_int[23]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(28),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(20),
I4 => \y_int[23]_i_18_n_0\,
I5 => y_int_reg1(20),
O => \y_int[23]_i_4_n_0\
);
\y_int[23]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(28),
O => \y_int[23]_i_40_n_0\
);
\y_int[23]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(27),
O => \y_int[23]_i_41_n_0\
);
\y_int[23]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(26),
O => \y_int[23]_i_42_n_0\
);
\y_int[23]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(25),
O => \y_int[23]_i_43_n_0\
);
\y_int[23]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_46_n_0\
);
\y_int[23]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_47_n_0\
);
\y_int[23]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_48_n_0\
);
\y_int[23]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_49_n_0\
);
\y_int[23]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(27),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(19),
I4 => \y_int[23]_i_20_n_0\,
I5 => y_int_reg1(19),
O => \y_int[23]_i_5_n_0\
);
\y_int[23]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_52_n_0\
);
\y_int[23]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_53_n_0\
);
\y_int[23]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_54_n_0\
);
\y_int[23]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_55_n_0\
);
\y_int[23]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_56_n_0\
);
\y_int[23]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_57_n_0\
);
\y_int[23]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[23]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[23]_i_6_n_0\
);
\y_int[23]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_62_n_0\
);
\y_int[23]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_63_n_0\
);
\y_int[23]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_64_n_0\
);
\y_int[23]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_65_n_0\
);
\y_int[23]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_8_n_7\,
I1 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[23]_i_67_n_0\
);
\y_int[23]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_16_n_5\,
I1 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[23]_i_68_n_0\
);
\y_int[23]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_16_n_7\,
I1 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[23]_i_69_n_0\
);
\y_int[23]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_3_n_0\,
I1 => y_int_reg1(22),
I2 => \y_int[23]_i_12_n_0\,
I3 => y_int_reg20_in(22),
O => \y_int[23]_i_7_n_0\
);
\y_int[23]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_16_n_5\,
I1 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[23]_i_70_n_0\
);
\y_int[23]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_6\,
I1 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[23]_i_71_n_0\
);
\y_int[23]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_4\,
I1 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[23]_i_72_n_0\
);
\y_int[23]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_6\,
I1 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[23]_i_73_n_0\
);
\y_int[23]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_4\,
I1 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[23]_i_74_n_0\
);
\y_int[23]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_21\(1),
I1 => \rgb888[8]_21\(2),
O => \y_int[23]_i_76_n_0\
);
\y_int[23]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_77_n_0\
);
\y_int[23]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_78_n_0\
);
\y_int[23]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_79_n_0\
);
\y_int[23]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_4_n_0\,
I1 => y_int_reg1(21),
I2 => \y_int[23]_i_14_n_0\,
I3 => y_int_reg20_in(21),
O => \y_int[23]_i_8_n_0\
);
\y_int[23]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \rgb888[8]_21\(1),
O => \y_int[23]_i_80_n_0\
);
\y_int[23]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_16_n_7\,
I1 => \y_int_reg[3]_i_16_n_6\,
O => \y_int[23]_i_81_n_0\
);
\y_int[23]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_26_n_5\,
I1 => \y_int_reg[3]_i_26_n_4\,
O => \y_int[23]_i_82_n_0\
);
\y_int[23]_i_83\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_26_n_7\,
I1 => \y_int_reg[3]_i_26_n_6\,
O => \y_int[23]_i_83_n_0\
);
\y_int[23]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(16),
I1 => rgb888(17),
O => \y_int[23]_i_84_n_0\
);
\y_int[23]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_6\,
I1 => \y_int_reg[3]_i_16_n_7\,
O => \y_int[23]_i_85_n_0\
);
\y_int[23]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_4\,
I1 => \y_int_reg[3]_i_26_n_5\,
O => \y_int[23]_i_86_n_0\
);
\y_int[23]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_6\,
I1 => \y_int_reg[3]_i_26_n_7\,
O => \y_int[23]_i_87_n_0\
);
\y_int[23]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
I1 => rgb888(16),
O => \y_int[23]_i_88_n_0\
);
\y_int[23]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_5_n_0\,
I1 => y_int_reg1(20),
I2 => \y_int[23]_i_18_n_0\,
I3 => y_int_reg20_in(20),
O => \y_int[23]_i_9_n_0\
);
\y_int[23]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_20\(3),
I1 => \rgb888[8]_21\(0),
O => \y_int[23]_i_90_n_0\
);
\y_int[23]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_20\(1),
I1 => \rgb888[8]_20\(2),
O => \y_int[23]_i_91_n_0\
);
\y_int[23]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[14]\(3),
I1 => \rgb888[8]_20\(0),
O => \y_int[23]_i_92_n_0\
);
\y_int[23]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[14]\(1),
I1 => \rgb888[14]\(2),
O => \y_int[23]_i_93_n_0\
);
\y_int[23]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(0),
I1 => \rgb888[8]_20\(3),
O => \y_int[23]_i_94_n_0\
);
\y_int[23]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_20\(2),
I1 => \rgb888[8]_20\(1),
O => \y_int[23]_i_95_n_0\
);
\y_int[23]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_20\(0),
I1 => \rgb888[14]\(3),
O => \y_int[23]_i_96_n_0\
);
\y_int[23]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[14]\(2),
I1 => \rgb888[14]\(1),
O => \y_int[23]_i_97_n_0\
);
\y_int[23]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^y_int_reg[3]_0\(3),
I1 => \rgb888[14]\(0),
O => \y_int[23]_i_98_n_0\
);
\y_int[23]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^y_int_reg[3]_0\(1),
I1 => \^y_int_reg[3]_0\(2),
O => \y_int[23]_i_99_n_0\
);
\y_int[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_2_n_0\
);
\y_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_3_n_0\
);
\y_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_4_n_0\
);
\y_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_5_n_0\
);
\y_int[31]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \y_int[31]_i_101_n_0\
);
\y_int[31]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(1),
I1 => rgb888(3),
O => \y_int[31]_i_104_n_0\
);
\y_int[31]_i_105\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(2),
O => \y_int[31]_i_105_n_0\
);
\y_int[31]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \y_int[31]_i_106_n_0\
);
\y_int[31]_i_107\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \y_int[31]_i_107_n_0\
);
\y_int[31]_i_108\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(0),
O => \y_int[31]_i_108_n_0\
);
\y_int[31]_i_109\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(6),
O => \y_int[31]_i_109_n_0\
);
\y_int[31]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \y_int[31]_i_110_n_0\
);
\y_int[31]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \y_int[31]_i_111_n_0\
);
\y_int[31]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \y_int[31]_i_112_n_0\
);
\y_int[31]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \y_int[31]_i_113_n_0\
);
\y_int[31]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \y_int[31]_i_114_n_0\
);
\y_int[31]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \y_int[31]_i_115_n_0\
);
\y_int[31]_i_116\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(1),
O => \y_int[31]_i_116_n_0\
);
\y_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \rgb888[8]_30\(0),
O => \y_int[31]_i_13_n_0\
);
\y_int[31]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(30),
O => \y_int[31]_i_14_n_0\
);
\y_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(29),
O => \y_int[31]_i_15_n_0\
);
\y_int[31]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(21),
I4 => rgb888(22),
I5 => rgb888(23),
O => \y_int[31]_i_17_n_0\
);
\y_int[31]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(23),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(19),
I4 => rgb888(21),
I5 => rgb888(22),
O => \y_int[31]_i_18_n_0\
);
\y_int[31]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(23),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(19),
I4 => rgb888(21),
I5 => rgb888(22),
O => \y_int[31]_i_19_n_0\
);
\y_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040004044F40040"
)
port map (
I0 => \y_int_reg[31]_i_7_n_1\,
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \rgb888[8]_21\(2),
I3 => \rgb888[8]_30\(0),
I4 => \^y_int_reg[23]_0\(0),
I5 => \rgb888[1]_0\(0),
O => \y_int[31]_i_2_n_0\
);
\y_int[31]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFFFFFF"
)
port map (
I0 => rgb888(22),
I1 => rgb888(21),
I2 => rgb888(19),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(23),
O => \y_int[31]_i_20_n_0\
);
\y_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_3_n_0\
);
\y_int[31]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_7\(3),
I1 => \y_int_reg[31]_i_75_n_2\,
O => \y_int[31]_i_32_n_0\
);
\y_int[31]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_9\(2),
O => \y_int[31]_i_33_n_0\
);
\y_int[31]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_9\(2),
O => \y_int[31]_i_34_n_0\
);
\y_int[31]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \y_int_reg[31]_i_75_n_2\,
I1 => \rgb888[0]_9\(0),
I2 => \rgb888[0]_9\(1),
O => \y_int[31]_i_35_n_0\
);
\y_int[31]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"36"
)
port map (
I0 => \rgb888[0]_7\(3),
I1 => \rgb888[0]_9\(0),
I2 => \y_int_reg[31]_i_75_n_2\,
O => \y_int[31]_i_36_n_0\
);
\y_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_4_n_0\
);
\y_int[31]_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(21),
I4 => rgb888(22),
O => \y_int[31]_i_40_n_0\
);
\y_int[31]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"BEEEEEEE"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(21),
I2 => rgb888(20),
I3 => rgb888(18),
I4 => rgb888(19),
O => \y_int[31]_i_41_n_0\
);
\y_int[31]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FD51540"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(20),
I4 => rgb888(23),
O => \y_int[31]_i_42_n_0\
);
\y_int[31]_i_43\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \y_int_reg[3]_i_64_n_7\,
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(22),
O => \y_int[31]_i_43_n_0\
);
\y_int[31]_i_44\: unisim.vcomponents.LUT6
generic map(
INIT => X"A999999999999999"
)
port map (
I0 => rgb888(23),
I1 => rgb888(22),
I2 => rgb888(21),
I3 => rgb888(19),
I4 => rgb888(18),
I5 => rgb888(20),
O => \y_int[31]_i_44_n_0\
);
\y_int[31]_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"6CC9C9C9C9C9C9C9"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(22),
I2 => rgb888(21),
I3 => rgb888(19),
I4 => rgb888(18),
I5 => rgb888(20),
O => \y_int[31]_i_45_n_0\
);
\y_int[31]_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"157FEA807FEA8015"
)
port map (
I0 => rgb888(23),
I1 => rgb888(19),
I2 => rgb888(18),
I3 => rgb888(20),
I4 => rgb888(21),
I5 => \y_int_reg[3]_i_64_n_2\,
O => \y_int[31]_i_46_n_0\
);
\y_int[31]_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996699669"
)
port map (
I0 => \y_int[31]_i_43_n_0\,
I1 => \y_int_reg[3]_i_64_n_2\,
I2 => rgb888(23),
I3 => rgb888(20),
I4 => rgb888(19),
I5 => rgb888(18),
O => \y_int[31]_i_47_n_0\
);
\y_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_5_n_0\
);
\y_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_6_n_0\
);
\y_int[31]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \rgb888[0]_7\(2),
I1 => \y_int_reg[31]_i_75_n_7\,
O => \y_int[31]_i_63_n_0\
);
\y_int[31]_i_64\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_87_n_4\,
I1 => \rgb888[0]_7\(1),
O => \y_int[31]_i_64_n_0\
);
\y_int[31]_i_65\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_int_reg[31]_i_87_n_4\,
I1 => \rgb888[0]_7\(1),
O => \y_int[31]_i_65_n_0\
);
\y_int[31]_i_66\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \y_int_reg[31]_i_86_n_4\,
I1 => \y_int_reg[31]_i_87_n_6\,
O => \y_int[31]_i_66_n_0\
);
\y_int[31]_i_67\: unisim.vcomponents.LUT4
generic map(
INIT => X"7887"
)
port map (
I0 => \y_int_reg[31]_i_75_n_7\,
I1 => \rgb888[0]_7\(2),
I2 => \y_int_reg[31]_i_75_n_2\,
I3 => \rgb888[0]_7\(3),
O => \y_int[31]_i_67_n_0\
);
\y_int[31]_i_68\: unisim.vcomponents.LUT4
generic map(
INIT => X"E11E"
)
port map (
I0 => \rgb888[0]_7\(1),
I1 => \y_int_reg[31]_i_87_n_4\,
I2 => \rgb888[0]_7\(2),
I3 => \y_int_reg[31]_i_75_n_7\,
O => \y_int[31]_i_68_n_0\
);
\y_int[31]_i_69\: unisim.vcomponents.LUT4
generic map(
INIT => X"6999"
)
port map (
I0 => \rgb888[0]_7\(1),
I1 => \y_int_reg[31]_i_87_n_4\,
I2 => \y_int_reg[31]_i_87_n_5\,
I3 => \rgb888[0]_7\(0),
O => \y_int[31]_i_69_n_0\
);
\y_int[31]_i_70\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \y_int_reg[31]_i_87_n_6\,
I1 => \y_int_reg[31]_i_86_n_4\,
I2 => \rgb888[0]_7\(0),
I3 => \y_int_reg[31]_i_87_n_5\,
O => \y_int[31]_i_70_n_0\
);
\y_int[31]_i_89\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \y_int_reg[31]_i_86_n_5\,
I1 => \y_int_reg[31]_i_86_n_4\,
I2 => \y_int_reg[31]_i_87_n_6\,
O => \y_int[31]_i_89_n_0\
);
\y_int[31]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_int_reg[31]_i_86_n_5\,
I1 => \y_int_reg[31]_i_87_n_7\,
O => \y_int[31]_i_90_n_0\
);
\y_int[31]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[31]_i_88_n_4\,
I1 => \y_int_reg[31]_i_86_n_6\,
O => \y_int[31]_i_91_n_0\
);
\y_int[31]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[31]_i_88_n_5\,
I1 => rgb888(0),
O => \y_int[31]_i_92_n_0\
);
\y_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[14]\(3),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(0),
O => \y_int[3]_i_10_n_0\
);
\y_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(2),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_30_n_4\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_6\,
O => y_int_reg1(2)
);
\y_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(1),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[3]_i_16_n_4\,
I3 => y_int_reg6,
I4 => y_int_reg5(9),
O => y_int_reg20_in(1)
);
\y_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[14]\(2),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_0\(1),
O => \y_int[3]_i_13_n_0\
);
\y_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(1),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_30_n_5\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_7\,
O => y_int_reg1(1)
);
\y_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb888[14]\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]_0\(0),
O => \y_int[3]_i_17_n_0\
);
\y_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[3]_i_35_n_4\,
O => \y_int[3]_i_18_n_0\
);
\y_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(2),
I1 => \y_int[3]_i_10_n_0\,
I2 => y_int_reg1(2),
O => \y_int[3]_i_2_n_0\
);
\y_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[3]_i_22_n_0\
);
\y_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_6\,
O => \y_int[3]_i_23_n_0\
);
\y_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_7\,
O => \y_int[3]_i_24_n_0\
);
\y_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_4\,
O => \y_int[3]_i_25_n_0\
);
\y_int[3]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(18),
I1 => \y_int_reg[3]_i_30_n_4\,
I2 => rgb888(21),
O => \y_int[3]_i_27_n_0\
);
\y_int[3]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \y_int_reg[3]_i_30_n_5\,
I1 => rgb888(17),
I2 => rgb888(20),
O => \y_int[3]_i_28_n_0\
);
\y_int[3]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \y_int_reg[3]_i_30_n_5\,
I1 => rgb888(17),
I2 => rgb888(20),
O => \y_int[3]_i_29_n_0\
);
\y_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(1),
I1 => \y_int[3]_i_13_n_0\,
I2 => y_int_reg1(1),
O => \y_int[3]_i_3_n_0\
);
\y_int[3]_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \y_int[3]_i_27_n_0\,
I1 => rgb888(22),
I2 => rgb888(19),
I3 => rgb888(18),
I4 => \y_int_reg[3]_i_64_n_7\,
O => \y_int[3]_i_31_n_0\
);
\y_int[3]_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(20),
I1 => rgb888(17),
I2 => \y_int_reg[3]_i_30_n_5\,
I3 => rgb888(21),
I4 => rgb888(18),
I5 => \y_int_reg[3]_i_30_n_4\,
O => \y_int[3]_i_32_n_0\
);
\y_int[3]_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => rgb888(20),
I1 => rgb888(17),
I2 => \y_int_reg[3]_i_30_n_5\,
I3 => rgb888(19),
I4 => rgb888(16),
O => \y_int[3]_i_33_n_0\
);
\y_int[3]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(16),
I1 => rgb888(19),
I2 => \y_int_reg[3]_i_30_n_6\,
O => \y_int[3]_i_34_n_0\
);
\y_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2E200"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
I3 => \y_int[3]_i_17_n_0\,
I4 => \y_int[3]_i_18_n_0\,
O => \y_int[3]_i_4_n_0\
);
\y_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(3),
I1 => \y_int[7]_i_19_n_0\,
I2 => y_int_reg1(3),
I3 => \y_int[3]_i_2_n_0\,
O => \y_int[3]_i_5_n_0\
);
\y_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(16),
O => \y_int[3]_i_50_n_0\
);
\y_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_5\,
O => \y_int[3]_i_51_n_0\
);
\y_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_6\,
O => \y_int[3]_i_52_n_0\
);
\y_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_7\,
O => \y_int[3]_i_53_n_0\
);
\y_int[3]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
O => \y_int[3]_i_54_n_0\
);
\y_int[3]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_30_n_7\,
I1 => rgb888(18),
O => \y_int[3]_i_56_n_0\
);
\y_int[3]_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_55_n_4\,
I1 => rgb888(17),
O => \y_int[3]_i_57_n_0\
);
\y_int[3]_i_58\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_55_n_5\,
I1 => rgb888(16),
O => \y_int[3]_i_58_n_0\
);
\y_int[3]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg[3]_i_55_n_6\,
O => \y_int[3]_i_59_n_0\
);
\y_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(2),
I1 => \y_int[3]_i_10_n_0\,
I2 => y_int_reg1(2),
I3 => \y_int[3]_i_3_n_0\,
O => \y_int[3]_i_6_n_0\
);
\y_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(22),
O => \y_int[3]_i_60_n_0\
);
\y_int[3]_i_61\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(23),
I1 => rgb888(21),
O => \y_int[3]_i_61_n_0\
);
\y_int[3]_i_62\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
O => \y_int[3]_i_62_n_0\
);
\y_int[3]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
O => \y_int[3]_i_63_n_0\
);
\y_int[3]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[3]_i_66_n_0\
);
\y_int[3]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_7\,
O => \y_int[3]_i_67_n_0\
);
\y_int[3]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_4\,
O => \y_int[3]_i_68_n_0\
);
\y_int[3]_i_69\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_5\,
O => \y_int[3]_i_69_n_0\
);
\y_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(1),
I1 => \y_int[3]_i_13_n_0\,
I2 => y_int_reg1(1),
I3 => \y_int[3]_i_4_n_0\,
O => \y_int[3]_i_7_n_0\
);
\y_int[3]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_32\(1),
I1 => rgb888(10),
O => \y_int[3]_i_71_n_0\
);
\y_int[3]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_32\(0),
I1 => rgb888(9),
O => \y_int[3]_i_72_n_0\
);
\y_int[3]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_19\(2),
I1 => rgb888(8),
O => \y_int[3]_i_73_n_0\
);
\y_int[3]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[8]_19\(1),
O => \y_int[3]_i_74_n_0\
);
\y_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"E21D1DE2"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
I3 => \y_int[3]_i_17_n_0\,
I4 => \y_int[3]_i_18_n_0\,
O => \y_int[3]_i_8_n_0\
);
\y_int[3]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
O => \y_int[3]_i_84_n_0\
);
\y_int[3]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => rgb888(17),
O => \y_int[3]_i_85_n_0\
);
\y_int[3]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => rgb888(16),
O => \y_int[3]_i_86_n_0\
);
\y_int[3]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(17),
O => \y_int[3]_i_87_n_0\
);
\y_int[3]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \y_int[3]_i_88_n_0\
);
\y_int[3]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_6\,
O => \y_int[3]_i_89_n_0\
);
\y_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(2),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_7\,
I3 => y_int_reg6,
I4 => y_int_reg5(10),
O => y_int_reg20_in(2)
);
\y_int[3]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(0),
I1 => \y_int_reg[31]_i_88_n_5\,
O => \y_int[3]_i_90_n_0\
);
\y_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_88_n_6\,
O => \y_int[3]_i_91_n_0\
);
\y_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \y_int[3]_i_92_n_0\
);
\y_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(6),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_8_n_7\,
I3 => y_int_reg6,
I4 => y_int_reg5(14),
O => y_int_reg20_in(6)
);
\y_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(3),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(0),
O => \y_int[7]_i_11_n_0\
);
\y_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(5),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_4\,
I3 => y_int_reg6,
I4 => y_int_reg5(13),
O => y_int_reg20_in(5)
);
\y_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(2),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(3),
O => \y_int[7]_i_13_n_0\
);
\y_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(5),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_5\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_21_n_7\,
O => y_int_reg1(5)
);
\y_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(4),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_5\,
I3 => y_int_reg6,
I4 => y_int_reg5(12),
O => y_int_reg20_in(4)
);
\y_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(1),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(2),
O => \y_int[7]_i_16_n_0\
);
\y_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(4),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_6\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_4\,
O => y_int_reg1(4)
);
\y_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(3),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_6\,
I3 => y_int_reg6,
I4 => y_int_reg5(11),
O => y_int_reg20_in(3)
);
\y_int[7]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(0),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(1),
O => \y_int[7]_i_19_n_0\
);
\y_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"E888E888E8EEE888"
)
port map (
I0 => y_int_reg20_in(6),
I1 => \y_int[7]_i_11_n_0\,
I2 => y_int_reg2(6),
I3 => \^y_int_reg[23]_0\(0),
I4 => \y_int_reg[11]_i_21_n_6\,
I5 => \^y_int_reg[7]_0\(0),
O => \y_int[7]_i_2_n_0\
);
\y_int[7]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(3),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_7\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_5\,
O => y_int_reg1(3)
);
\y_int[7]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(7),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_5\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(7)
);
\y_int[7]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(6),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_6\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(6)
);
\y_int[7]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_0\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(1),
O => \y_int[7]_i_29_n_0\
);
\y_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(5),
I1 => \y_int[7]_i_13_n_0\,
I2 => y_int_reg1(5),
O => \y_int[7]_i_3_n_0\
);
\y_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(1),
O => \y_int[7]_i_30_n_0\
);
\y_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(0),
O => \y_int[7]_i_31_n_0\
);
\y_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(3),
O => \y_int[7]_i_32_n_0\
);
\y_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_0\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(2),
O => \y_int[7]_i_33_n_0\
);
\y_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(4),
I1 => \y_int[7]_i_16_n_0\,
I2 => y_int_reg1(4),
O => \y_int[7]_i_4_n_0\
);
\y_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(3),
I1 => \y_int[7]_i_19_n_0\,
I2 => y_int_reg1(3),
O => \y_int[7]_i_5_n_0\
);
\y_int[7]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[7]_i_2_n_0\,
I1 => y_int_reg1(7),
I2 => \y_int[11]_i_19_n_0\,
I3 => y_int_reg20_in(7),
O => \y_int[7]_i_6_n_0\
);
\y_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[7]_i_3_n_0\,
I1 => y_int_reg1(6),
I2 => \y_int[7]_i_11_n_0\,
I3 => y_int_reg20_in(6),
O => \y_int[7]_i_7_n_0\
);
\y_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(5),
I1 => \y_int[7]_i_13_n_0\,
I2 => y_int_reg1(5),
I3 => \y_int[7]_i_4_n_0\,
O => \y_int[7]_i_8_n_0\
);
\y_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(4),
I1 => \y_int[7]_i_16_n_0\,
I2 => y_int_reg1(4),
I3 => \y_int[7]_i_5_n_0\,
O => \y_int[7]_i_9_n_0\
);
\y_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_7\,
Q => \y_int_reg_n_0_[0]\,
R => '0'
);
\y_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_5\,
Q => \y_int_reg__0\(10),
R => '0'
);
\y_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_4\,
Q => \y_int_reg__0\(11),
R => '0'
);
\y_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_1_n_0\,
CO(3) => \y_int_reg[11]_i_1_n_0\,
CO(2) => \y_int_reg[11]_i_1_n_1\,
CO(1) => \y_int_reg[11]_i_1_n_2\,
CO(0) => \y_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[11]_i_2_n_0\,
DI(2) => \y_int[11]_i_3_n_0\,
DI(1) => \y_int[11]_i_4_n_0\,
DI(0) => \y_int[11]_i_5_n_0\,
O(3) => \y_int_reg[11]_i_1_n_4\,
O(2) => \y_int_reg[11]_i_1_n_5\,
O(1) => \y_int_reg[11]_i_1_n_6\,
O(0) => \y_int_reg[11]_i_1_n_7\,
S(3) => \y_int[11]_i_6_n_0\,
S(2) => \y_int[11]_i_7_n_0\,
S(1) => \y_int[11]_i_8_n_0\,
S(0) => \y_int[11]_i_9_n_0\
);
\y_int_reg[11]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_28_n_0\,
CO(3) => \y_int_reg[11]_i_14_n_0\,
CO(2) => \y_int_reg[11]_i_14_n_1\,
CO(1) => \y_int_reg[11]_i_14_n_2\,
CO(0) => \y_int_reg[11]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(16 downto 13),
S(3) => \y_int[11]_i_29_n_0\,
S(2) => \y_int[11]_i_30_n_0\,
S(1) => \y_int[11]_i_31_n_0\,
S(0) => \y_int[11]_i_32_n_0\
);
\y_int_reg[11]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_33_n_0\,
CO(3) => \y_int_reg[11]_i_15_n_0\,
CO(2) => \y_int_reg[11]_i_15_n_1\,
CO(1) => \y_int_reg[11]_i_15_n_2\,
CO(0) => \y_int_reg[11]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(8 downto 5),
S(3) => \y_int[11]_i_34_n_0\,
S(2) => \y_int[11]_i_35_n_0\,
S(1) => \y_int[11]_i_36_n_0\,
S(0) => \y_int[11]_i_37_n_0\
);
\y_int_reg[11]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_39_n_0\,
CO(3) => \y_int_reg[15]_1\(0),
CO(2) => \y_int_reg[11]_i_20_n_1\,
CO(1) => \y_int_reg[11]_i_20_n_2\,
CO(0) => \y_int_reg[11]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(8 downto 5),
S(3) => \y_int[11]_i_40_n_0\,
S(2) => \y_int[11]_i_41_n_0\,
S(1) => \y_int[11]_i_42_n_0\,
S(0) => \y_int[11]_i_43_n_0\
);
\y_int_reg[11]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_44_n_0\,
CO(3) => \y_int_reg[11]_i_21_n_0\,
CO(2) => \y_int_reg[11]_i_21_n_1\,
CO(1) => \y_int_reg[11]_i_21_n_2\,
CO(0) => \y_int_reg[11]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_21_n_4\,
O(2) => \y_int_reg[11]_i_21_n_5\,
O(1) => \y_int_reg[11]_i_21_n_6\,
O(0) => \y_int_reg[11]_i_21_n_7\,
S(3) => \y_int[11]_i_45_n_0\,
S(2) => \y_int[11]_i_46_n_0\,
S(1) => \y_int[11]_i_47_n_0\,
S(0) => \y_int[11]_i_48_n_0\
);
\y_int_reg[11]_i_22\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_49_n_0\,
CO(3) => \^y_int_reg[7]_0\(0),
CO(2) => \y_int_reg[11]_i_22_n_1\,
CO(1) => \y_int_reg[11]_i_22_n_2\,
CO(0) => \y_int_reg[11]_i_22_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^y_int_reg[23]_0\(0),
DI(1) => \^y_int_reg[23]_0\(0),
DI(0) => \^y_int_reg[23]_0\(0),
O(3 downto 0) => \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_50_n_0\,
S(2) => \y_int[11]_i_51_n_0\,
S(1) => \y_int[11]_i_52_n_0\,
S(0) => \y_int[11]_i_53_n_0\
);
\y_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_15_n_0\,
CO(3) => \y_int_reg[11]_i_28_n_0\,
CO(2) => \y_int_reg[11]_i_28_n_1\,
CO(1) => \y_int_reg[11]_i_28_n_2\,
CO(0) => \y_int_reg[11]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(12 downto 9),
S(3) => \y_int[11]_i_58_n_0\,
S(2) => \y_int[11]_i_59_n_0\,
S(1) => \y_int[11]_i_60_n_0\,
S(0) => \y_int[11]_i_61_n_0\
);
\y_int_reg[11]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_33_n_0\,
CO(2) => \y_int_reg[11]_i_33_n_1\,
CO(1) => \y_int_reg[11]_i_33_n_2\,
CO(0) => \y_int_reg[11]_i_33_n_3\,
CYINIT => \y_int[11]_i_62_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(4 downto 1),
S(3) => \y_int[11]_i_63_n_0\,
S(2) => \y_int[11]_i_64_n_0\,
S(1) => \y_int[11]_i_65_n_0\,
S(0) => \y_int[11]_i_66_n_0\
);
\y_int_reg[11]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_24_n_0\,
CO(3) => \y_int_reg[11]_i_38_n_0\,
CO(2) => \y_int_reg[11]_i_38_n_1\,
CO(1) => \y_int_reg[11]_i_38_n_2\,
CO(0) => \y_int_reg[11]_i_38_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_38_n_4\,
O(2) => \y_int_reg[11]_i_38_n_5\,
O(1) => \y_int_reg[11]_i_38_n_6\,
O(0) => \y_int_reg[11]_i_38_n_7\,
S(3) => \y_int[11]_i_67_n_0\,
S(2) => \y_int[11]_i_68_n_0\,
S(1) => \y_int[11]_i_69_n_0\,
S(0) => \y_int[11]_i_70_n_0\
);
\y_int_reg[11]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_39_n_0\,
CO(2) => \y_int_reg[11]_i_39_n_1\,
CO(1) => \y_int_reg[11]_i_39_n_2\,
CO(0) => \y_int_reg[11]_i_39_n_3\,
CYINIT => \y_int[11]_i_71_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(4 downto 1),
S(3) => \y_int[11]_i_72_n_0\,
S(2) => \y_int[11]_i_73_n_0\,
S(1) => \y_int[11]_i_74_n_0\,
S(0) => \y_int[11]_i_75_n_0\
);
\y_int_reg[11]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_35_n_0\,
CO(3) => \y_int_reg[11]_i_44_n_0\,
CO(2) => \y_int_reg[11]_i_44_n_1\,
CO(1) => \y_int_reg[11]_i_44_n_2\,
CO(0) => \y_int_reg[11]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_44_n_4\,
O(2) => \y_int_reg[11]_i_44_n_5\,
O(1) => \y_int_reg[11]_i_44_n_6\,
O(0) => \y_int_reg[11]_i_44_n_7\,
S(3) => \y_int[11]_i_76_n_0\,
S(2) => \y_int[11]_i_77_n_0\,
S(1) => \y_int[11]_i_78_n_0\,
S(0) => \y_int[11]_i_79_n_0\
);
\y_int_reg[11]_i_49\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_80_n_0\,
CO(3) => \y_int_reg[11]_i_49_n_0\,
CO(2) => \y_int_reg[11]_i_49_n_1\,
CO(1) => \y_int_reg[11]_i_49_n_2\,
CO(0) => \y_int_reg[11]_i_49_n_3\,
CYINIT => '0',
DI(3) => \^y_int_reg[23]_0\(0),
DI(2) => \^y_int_reg[23]_0\(0),
DI(1) => \^y_int_reg[23]_0\(0),
DI(0) => \^y_int_reg[23]_0\(0),
O(3 downto 0) => \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_81_n_0\,
S(2) => \y_int[11]_i_82_n_0\,
S(1) => \y_int[11]_i_83_n_0\,
S(0) => \y_int[11]_i_84_n_0\
);
\y_int_reg[11]_i_80\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_85_n_0\,
CO(3) => \y_int_reg[11]_i_80_n_0\,
CO(2) => \y_int_reg[11]_i_80_n_1\,
CO(1) => \y_int_reg[11]_i_80_n_2\,
CO(0) => \y_int_reg[11]_i_80_n_3\,
CYINIT => '0',
DI(3) => \^y_int_reg[23]_0\(0),
DI(2) => \y_int[11]_i_86_n_0\,
DI(1) => \y_int[11]_i_87_n_0\,
DI(0) => \y_int[11]_i_88_n_0\,
O(3 downto 0) => \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_89_n_0\,
S(2) => \y_int[11]_i_90_n_0\,
S(1) => \y_int[11]_i_91_n_0\,
S(0) => \y_int[11]_i_92_n_0\
);
\y_int_reg[11]_i_85\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_85_n_0\,
CO(2) => \y_int_reg[11]_i_85_n_1\,
CO(1) => \y_int_reg[11]_i_85_n_2\,
CO(0) => \y_int_reg[11]_i_85_n_3\,
CYINIT => '1',
DI(3) => \y_int[11]_i_93_n_0\,
DI(2) => \y_int[11]_i_94_n_0\,
DI(1) => \y_int[11]_i_95_n_0\,
DI(0) => \y_int[11]_i_96_n_0\,
O(3 downto 0) => \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_97_n_0\,
S(2) => \y_int[11]_i_98_n_0\,
S(1) => \y_int[11]_i_99_n_0\,
S(0) => \y_int[11]_i_100_n_0\
);
\y_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_7\,
Q => \y_int_reg__0\(12),
R => '0'
);
\y_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_6\,
Q => \y_int_reg__0\(13),
R => '0'
);
\y_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_5\,
Q => \y_int_reg__0\(14),
R => '0'
);
\y_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_4\,
Q => \y_int_reg__0\(15),
R => '0'
);
\y_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_1_n_0\,
CO(3) => \y_int_reg[15]_i_1_n_0\,
CO(2) => \y_int_reg[15]_i_1_n_1\,
CO(1) => \y_int_reg[15]_i_1_n_2\,
CO(0) => \y_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[15]_i_2_n_0\,
DI(2) => \y_int[15]_i_3_n_0\,
DI(1) => \y_int[15]_i_4_n_0\,
DI(0) => \y_int[15]_i_5_n_0\,
O(3) => \y_int_reg[15]_i_1_n_4\,
O(2) => \y_int_reg[15]_i_1_n_5\,
O(1) => \y_int_reg[15]_i_1_n_6\,
O(0) => \y_int_reg[15]_i_1_n_7\,
S(3) => \y_int[15]_i_6_n_0\,
S(2) => \y_int[15]_i_7_n_0\,
S(1) => \y_int[15]_i_8_n_0\,
S(0) => \y_int[15]_i_9_n_0\
);
\y_int_reg[15]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_14_n_0\,
CO(3) => \y_int_reg[15]_i_14_n_0\,
CO(2) => \y_int_reg[15]_i_14_n_1\,
CO(1) => \y_int_reg[15]_i_14_n_2\,
CO(0) => \y_int_reg[15]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(20 downto 17),
S(3) => \y_int[15]_i_25_n_0\,
S(2) => \y_int[15]_i_26_n_0\,
S(1) => \y_int[15]_i_27_n_0\,
S(0) => \y_int[15]_i_28_n_0\
);
\y_int_reg[15]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_15_n_0\,
CO(3) => \y_int_reg[15]_i_15_n_0\,
CO(2) => \y_int_reg[15]_i_15_n_1\,
CO(1) => \y_int_reg[15]_i_15_n_2\,
CO(0) => \y_int_reg[15]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(12 downto 9),
S(3) => \y_int[15]_i_29_n_0\,
S(2) => \y_int[15]_i_30_n_0\,
S(1) => \y_int[15]_i_31_n_0\,
S(0) => \y_int[15]_i_32_n_0\
);
\y_int_reg[15]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_38_n_0\,
CO(3) => \y_int_reg[19]_1\(0),
CO(2) => \y_int_reg[15]_i_33_n_1\,
CO(1) => \y_int_reg[15]_i_33_n_2\,
CO(0) => \y_int_reg[15]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[15]_i_33_n_4\,
O(2) => \y_int_reg[15]_i_33_n_5\,
O(1) => \y_int_reg[15]_i_33_n_6\,
O(0) => \y_int_reg[15]_i_33_n_7\,
S(3) => \y_int[15]_i_40_n_0\,
S(2) => \y_int[15]_i_41_n_0\,
S(1) => \y_int[15]_i_42_n_0\,
S(0) => \y_int[15]_i_43_n_0\
);
\y_int_reg[15]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_21_n_0\,
CO(3) => \y_int_reg[15]_i_35_n_0\,
CO(2) => \y_int_reg[15]_i_35_n_1\,
CO(1) => \y_int_reg[15]_i_35_n_2\,
CO(0) => \y_int_reg[15]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[15]_0\(3 downto 0),
S(3) => \y_int[15]_i_48_n_0\,
S(2) => \y_int[15]_i_49_n_0\,
S(1) => \y_int[15]_i_50_n_0\,
S(0) => \y_int[15]_i_51_n_0\
);
\y_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_7\,
Q => \y_int_reg__0\(16),
R => '0'
);
\y_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_6\,
Q => \y_int_reg__0\(17),
R => '0'
);
\y_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_5\,
Q => \y_int_reg__0\(18),
R => '0'
);
\y_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_4\,
Q => \y_int_reg__0\(19),
R => '0'
);
\y_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_1_n_0\,
CO(3) => \y_int_reg[19]_i_1_n_0\,
CO(2) => \y_int_reg[19]_i_1_n_1\,
CO(1) => \y_int_reg[19]_i_1_n_2\,
CO(0) => \y_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[19]_i_2_n_0\,
DI(2) => \y_int[19]_i_3_n_0\,
DI(1) => \y_int[19]_i_4_n_0\,
DI(0) => \y_int[19]_i_5_n_0\,
O(3) => \y_int_reg[19]_i_1_n_4\,
O(2) => \y_int_reg[19]_i_1_n_5\,
O(1) => \y_int_reg[19]_i_1_n_6\,
O(0) => \y_int_reg[19]_i_1_n_7\,
S(3) => \y_int[19]_i_6_n_0\,
S(2) => \y_int[19]_i_7_n_0\,
S(1) => \y_int[19]_i_8_n_0\,
S(0) => \y_int[19]_i_9_n_0\
);
\y_int_reg[19]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_14_n_0\,
CO(3) => \y_int_reg[19]_i_14_n_0\,
CO(2) => \y_int_reg[19]_i_14_n_1\,
CO(1) => \y_int_reg[19]_i_14_n_2\,
CO(0) => \y_int_reg[19]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(24 downto 21),
S(3) => \y_int[19]_i_25_n_0\,
S(2) => \y_int[19]_i_26_n_0\,
S(1) => \y_int[19]_i_27_n_0\,
S(0) => \y_int[19]_i_28_n_0\
);
\y_int_reg[19]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_15_n_0\,
CO(3) => \y_int_reg[19]_i_15_n_0\,
CO(2) => \y_int_reg[19]_i_15_n_1\,
CO(1) => \y_int_reg[19]_i_15_n_2\,
CO(0) => \y_int_reg[19]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(16 downto 13),
S(3) => \y_int[19]_i_29_n_0\,
S(2) => \y_int[19]_i_30_n_0\,
S(1) => \y_int[19]_i_31_n_0\,
S(0) => \y_int[19]_i_32_n_0\
);
\y_int_reg[19]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_35_n_0\,
CO(3) => \y_int_reg[19]_i_35_n_0\,
CO(2) => \y_int_reg[19]_i_35_n_1\,
CO(1) => \y_int_reg[19]_i_35_n_2\,
CO(0) => \y_int_reg[19]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[19]_0\(3 downto 0),
S(3) => \y_int[19]_i_48_n_0\,
S(2) => \y_int[19]_i_49_n_0\,
S(1) => \y_int[19]_i_50_n_0\,
S(0) => \y_int[19]_i_51_n_0\
);
\y_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_6\,
Q => \y_int_reg_n_0_[1]\,
R => '0'
);
\y_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_7\,
Q => \y_int_reg__0\(20),
R => '0'
);
\y_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_6\,
Q => \y_int_reg__0\(21),
R => '0'
);
\y_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_5\,
Q => \y_int_reg__0\(22),
R => '0'
);
\y_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_4\,
Q => \y_int_reg__0\(23),
R => '0'
);
\y_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_1_n_0\,
CO(3) => \y_int_reg[23]_i_1_n_0\,
CO(2) => \y_int_reg[23]_i_1_n_1\,
CO(1) => \y_int_reg[23]_i_1_n_2\,
CO(0) => \y_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_2_n_0\,
DI(2) => \y_int[23]_i_3_n_0\,
DI(1) => \y_int[23]_i_4_n_0\,
DI(0) => \y_int[23]_i_5_n_0\,
O(3) => \y_int_reg[23]_i_1_n_4\,
O(2) => \y_int_reg[23]_i_1_n_5\,
O(1) => \y_int_reg[23]_i_1_n_6\,
O(0) => \y_int_reg[23]_i_1_n_7\,
S(3) => \y_int[23]_i_6_n_0\,
S(2) => \y_int[23]_i_7_n_0\,
S(1) => \y_int[23]_i_8_n_0\,
S(0) => \y_int[23]_i_9_n_0\
);
\y_int_reg[23]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_25_n_0\,
CO(3) => y_int_reg6,
CO(2) => \y_int_reg[23]_i_10_n_1\,
CO(1) => \y_int_reg[23]_i_10_n_2\,
CO(0) => \y_int_reg[23]_i_10_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \y_int_reg[31]_i_8_n_5\,
DI(1) => \y_int_reg[31]_i_8_n_5\,
DI(0) => \y_int_reg[31]_i_8_n_5\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_26_n_0\,
S(2) => \y_int[23]_i_27_n_0\,
S(1) => \y_int[23]_i_28_n_0\,
S(0) => \y_int[23]_i_29_n_0\
);
\y_int_reg[23]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_16_n_0\,
CO(3 downto 1) => \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_int_reg[23]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg5(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \y_int[23]_i_30_n_0\,
S(0) => \y_int[23]_i_31_n_0\
);
\y_int_reg[23]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_14_n_0\,
CO(3) => \y_int_reg[23]_i_16_n_0\,
CO(2) => \y_int_reg[23]_i_16_n_1\,
CO(1) => \y_int_reg[23]_i_16_n_2\,
CO(0) => \y_int_reg[23]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(28 downto 25),
S(3) => \y_int[23]_i_36_n_0\,
S(2) => \y_int[23]_i_37_n_0\,
S(1) => \y_int[23]_i_38_n_0\,
S(0) => \y_int[23]_i_39_n_0\
);
\y_int_reg[23]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_15_n_0\,
CO(3) => \y_int_reg[23]_i_17_n_0\,
CO(2) => \y_int_reg[23]_i_17_n_1\,
CO(1) => \y_int_reg[23]_i_17_n_2\,
CO(0) => \y_int_reg[23]_i_17_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(20 downto 17),
S(3) => \y_int[23]_i_40_n_0\,
S(2) => \y_int[23]_i_41_n_0\,
S(1) => \y_int[23]_i_42_n_0\,
S(0) => \y_int[23]_i_43_n_0\
);
\y_int_reg[23]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_45_n_0\,
CO(3) => \y_int_reg[23]_i_25_n_0\,
CO(2) => \y_int_reg[23]_i_25_n_1\,
CO(1) => \y_int_reg[23]_i_25_n_2\,
CO(0) => \y_int_reg[23]_i_25_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[31]_i_8_n_5\,
DI(2) => \y_int_reg[31]_i_8_n_5\,
DI(1) => \y_int_reg[31]_i_8_n_5\,
DI(0) => \y_int_reg[31]_i_8_n_5\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_46_n_0\,
S(2) => \y_int[23]_i_47_n_0\,
S(1) => \y_int[23]_i_48_n_0\,
S(0) => \y_int[23]_i_49_n_0\
);
\y_int_reg[23]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_51_n_0\,
CO(3) => \^y_int_reg[3]_1\(0),
CO(2) => \y_int_reg[23]_i_33_n_1\,
CO(1) => \y_int_reg[23]_i_33_n_2\,
CO(0) => \y_int_reg[23]_i_33_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[8]_21\(2),
DI(1) => \rgb888[8]_21\(2),
DI(0) => \rgb888[8]_21\(2),
O(3 downto 0) => \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_52_n_0\,
S(2) => \y_int[23]_i_53_n_0\,
S(1) => \y_int[23]_i_54_n_0\,
S(0) => \y_int[23]_i_55_n_0\
);
\y_int_reg[23]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_44_n_0\,
CO(3 downto 1) => \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_int_reg[23]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \^y_int_reg[23]_1\(1 downto 0),
S(3 downto 2) => B"00",
S(1) => \y_int[23]_i_56_n_0\,
S(0) => \y_int[23]_i_57_n_0\
);
\y_int_reg[23]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_35_n_0\,
CO(3) => \y_int_reg[23]_i_44_n_0\,
CO(2) => \y_int_reg[23]_i_44_n_1\,
CO(1) => \y_int_reg[23]_i_44_n_2\,
CO(0) => \y_int_reg[23]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[23]_2\(3 downto 0),
S(3) => \y_int[23]_i_62_n_0\,
S(2) => \y_int[23]_i_63_n_0\,
S(1) => \y_int[23]_i_64_n_0\,
S(0) => \y_int[23]_i_65_n_0\
);
\y_int_reg[23]_i_45\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_66_n_0\,
CO(3) => \y_int_reg[23]_i_45_n_0\,
CO(2) => \y_int_reg[23]_i_45_n_1\,
CO(1) => \y_int_reg[23]_i_45_n_2\,
CO(0) => \y_int_reg[23]_i_45_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_67_n_0\,
DI(2) => \y_int[23]_i_68_n_0\,
DI(1) => \y_int[23]_i_69_n_0\,
DI(0) => \y_int[23]_i_70_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_71_n_0\,
S(2) => \y_int[23]_i_72_n_0\,
S(1) => \y_int[23]_i_73_n_0\,
S(0) => \y_int[23]_i_74_n_0\
);
\y_int_reg[23]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_75_n_0\,
CO(3) => \y_int_reg[23]_i_51_n_0\,
CO(2) => \y_int_reg[23]_i_51_n_1\,
CO(1) => \y_int_reg[23]_i_51_n_2\,
CO(0) => \y_int_reg[23]_i_51_n_3\,
CYINIT => '0',
DI(3) => \rgb888[8]_21\(2),
DI(2) => \rgb888[8]_21\(2),
DI(1) => \rgb888[8]_21\(2),
DI(0) => \y_int[23]_i_76_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_77_n_0\,
S(2) => \y_int[23]_i_78_n_0\,
S(1) => \y_int[23]_i_79_n_0\,
S(0) => \y_int[23]_i_80_n_0\
);
\y_int_reg[23]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_i_66_n_0\,
CO(2) => \y_int_reg[23]_i_66_n_1\,
CO(1) => \y_int_reg[23]_i_66_n_2\,
CO(0) => \y_int_reg[23]_i_66_n_3\,
CYINIT => '1',
DI(3) => \y_int[23]_i_81_n_0\,
DI(2) => \y_int[23]_i_82_n_0\,
DI(1) => \y_int[23]_i_83_n_0\,
DI(0) => \y_int[23]_i_84_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_85_n_0\,
S(2) => \y_int[23]_i_86_n_0\,
S(1) => \y_int[23]_i_87_n_0\,
S(0) => \y_int[23]_i_88_n_0\
);
\y_int_reg[23]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_89_n_0\,
CO(3) => \y_int_reg[23]_i_75_n_0\,
CO(2) => \y_int_reg[23]_i_75_n_1\,
CO(1) => \y_int_reg[23]_i_75_n_2\,
CO(0) => \y_int_reg[23]_i_75_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_90_n_0\,
DI(2) => \y_int[23]_i_91_n_0\,
DI(1) => \y_int[23]_i_92_n_0\,
DI(0) => \y_int[23]_i_93_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_94_n_0\,
S(2) => \y_int[23]_i_95_n_0\,
S(1) => \y_int[23]_i_96_n_0\,
S(0) => \y_int[23]_i_97_n_0\
);
\y_int_reg[23]_i_89\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_i_89_n_0\,
CO(2) => \y_int_reg[23]_i_89_n_1\,
CO(1) => \y_int_reg[23]_i_89_n_2\,
CO(0) => \y_int_reg[23]_i_89_n_3\,
CYINIT => '1',
DI(3) => \y_int[23]_i_98_n_0\,
DI(2) => \y_int[23]_i_99_n_0\,
DI(1) => \y_int[23]_i_100_n_0\,
DI(0) => rgb888(8),
O(3 downto 0) => \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_101_n_0\,
S(2) => \y_int[23]_i_102_n_0\,
S(1) => \y_int[23]_i_103_n_0\,
S(0) => \y_int[23]_i_104_n_0\
);
\y_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_7\,
Q => \y_int_reg__0\(24),
R => '0'
);
\y_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_6\,
Q => \y_int_reg__0\(25),
R => '0'
);
\y_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_5\,
Q => \y_int_reg__0\(26),
R => '0'
);
\y_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_4\,
Q => \y_int_reg__0\(27),
R => '0'
);
\y_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_1_n_0\,
CO(3) => \y_int_reg[27]_i_1_n_0\,
CO(2) => \y_int_reg[27]_i_1_n_1\,
CO(1) => \y_int_reg[27]_i_1_n_2\,
CO(0) => \y_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_2_n_0\,
DI(2) => \y_int[31]_i_2_n_0\,
DI(1) => \y_int[31]_i_2_n_0\,
DI(0) => \y_int[31]_i_2_n_0\,
O(3) => \y_int_reg[27]_i_1_n_4\,
O(2) => \y_int_reg[27]_i_1_n_5\,
O(1) => \y_int_reg[27]_i_1_n_6\,
O(0) => \y_int_reg[27]_i_1_n_7\,
S(3) => \y_int[27]_i_2_n_0\,
S(2) => \y_int[27]_i_3_n_0\,
S(1) => \y_int[27]_i_4_n_0\,
S(0) => \y_int[27]_i_5_n_0\
);
\y_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_7\,
Q => \y_int_reg__0\(28),
R => '0'
);
\y_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_6\,
Q => \y_int_reg__0\(29),
R => '0'
);
\y_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_5\,
Q => \y_int_reg_n_0_[2]\,
R => '0'
);
\y_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_5\,
Q => \y_int_reg__0\(30),
R => '0'
);
\y_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_4\,
Q => \y_int_reg__0\(31),
R => '0'
);
\y_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_1_n_1\,
CO(1) => \y_int_reg[31]_i_1_n_2\,
CO(0) => \y_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \y_int[31]_i_2_n_0\,
DI(1) => \y_int[31]_i_2_n_0\,
DI(0) => \y_int[31]_i_2_n_0\,
O(3) => \y_int_reg[31]_i_1_n_4\,
O(2) => \y_int_reg[31]_i_1_n_5\,
O(1) => \y_int_reg[31]_i_1_n_6\,
O(0) => \y_int_reg[31]_i_1_n_7\,
S(3) => \y_int[31]_i_3_n_0\,
S(2) => \y_int[31]_i_4_n_0\,
S(1) => \y_int[31]_i_5_n_0\,
S(0) => \y_int[31]_i_6_n_0\
);
\y_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_11_n_1\,
CO(1) => \y_int_reg[31]_i_11_n_2\,
CO(0) => \y_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \rgb888[0]_9\(1),
DI(0) => \y_int[31]_i_32_n_0\,
O(3) => \^y_int_reg[23]_0\(0),
O(2) => \y_int_reg[31]_i_11_n_5\,
O(1) => \y_int_reg[31]_i_11_n_6\,
O(0) => \y_int_reg[31]_i_11_n_7\,
S(3) => \y_int[31]_i_33_n_0\,
S(2) => \y_int[31]_i_34_n_0\,
S(1) => \y_int[31]_i_35_n_0\,
S(0) => \y_int[31]_i_36_n_0\
);
\y_int_reg[31]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_16_n_0\,
CO(3) => \y_int_reg[31]_i_16_n_0\,
CO(2) => \y_int_reg[31]_i_16_n_1\,
CO(1) => \y_int_reg[31]_i_16_n_2\,
CO(0) => \y_int_reg[31]_i_16_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_40_n_0\,
DI(2) => \y_int[31]_i_41_n_0\,
DI(1) => \y_int[31]_i_42_n_0\,
DI(0) => \y_int[31]_i_43_n_0\,
O(3) => \y_int_reg[31]_i_16_n_4\,
O(2) => \y_int_reg[31]_i_16_n_5\,
O(1) => \y_int_reg[31]_i_16_n_6\,
O(0) => \y_int_reg[31]_i_16_n_7\,
S(3) => \y_int[31]_i_44_n_0\,
S(2) => \y_int[31]_i_45_n_0\,
S(1) => \y_int[31]_i_46_n_0\,
S(0) => \y_int[31]_i_47_n_0\
);
\y_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_62_n_0\,
CO(3) => \y_int_reg[31]_i_30_n_0\,
CO(2) => \y_int_reg[31]_i_30_n_1\,
CO(1) => \y_int_reg[31]_i_30_n_2\,
CO(0) => \y_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_63_n_0\,
DI(2) => \y_int[31]_i_64_n_0\,
DI(1) => \y_int[31]_i_65_n_0\,
DI(0) => \y_int[31]_i_66_n_0\,
O(3) => \y_int_reg[31]_i_30_n_4\,
O(2) => \y_int_reg[31]_i_30_n_5\,
O(1) => \y_int_reg[31]_i_30_n_6\,
O(0) => \y_int_reg[31]_i_30_n_7\,
S(3) => \y_int[31]_i_67_n_0\,
S(2) => \y_int[31]_i_68_n_0\,
S(1) => \y_int[31]_i_69_n_0\,
S(0) => \y_int[31]_i_70_n_0\
);
\y_int_reg[31]_i_62\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[31]_i_62_n_0\,
CO(2) => \y_int_reg[31]_i_62_n_1\,
CO(1) => \y_int_reg[31]_i_62_n_2\,
CO(0) => \y_int_reg[31]_i_62_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[31]_i_86_n_5\,
DI(2) => \y_int_reg[31]_i_87_n_7\,
DI(1) => \y_int_reg[31]_i_88_n_4\,
DI(0) => \y_int_reg[31]_i_88_n_5\,
O(3) => \y_int_reg[31]_i_62_n_4\,
O(2) => \y_int_reg[31]_i_62_n_5\,
O(1) => \y_int_reg[31]_i_62_n_6\,
O(0) => \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_89_n_0\,
S(2) => \y_int[31]_i_90_n_0\,
S(1) => \y_int[31]_i_91_n_0\,
S(0) => \y_int[31]_i_92_n_0\
);
\y_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_17_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_7_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg3(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_14_n_0\,
S(0) => \y_int[31]_i_15_n_0\
);
\y_int_reg[31]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_87_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_75_n_2\,
CO(0) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(7),
O(3 downto 1) => \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[31]_i_75_n_7\,
S(3 downto 1) => B"001",
S(0) => \y_int[31]_i_101_n_0\
);
\y_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_16_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_8_n_2\,
CO(0) => \y_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \y_int[31]_i_17_n_0\,
O(3) => \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_8_n_5\,
O(1) => \y_int_reg[31]_i_8_n_6\,
O(0) => \y_int_reg[31]_i_8_n_7\,
S(3) => '0',
S(2) => \y_int[31]_i_18_n_0\,
S(1) => \y_int[31]_i_19_n_0\,
S(0) => \y_int[31]_i_20_n_0\
);
\y_int_reg[31]_i_86\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_3\(0),
CO(2) => \y_int_reg[31]_i_86_n_1\,
CO(1) => \y_int_reg[31]_i_86_n_2\,
CO(0) => \y_int_reg[31]_i_86_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_104_n_0\,
DI(2) => rgb888(2),
DI(1 downto 0) => B"01",
O(3) => \y_int_reg[31]_i_86_n_4\,
O(2) => \y_int_reg[31]_i_86_n_5\,
O(1) => \y_int_reg[31]_i_86_n_6\,
O(0) => \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_105_n_0\,
S(2) => \y_int[31]_i_106_n_0\,
S(1) => \y_int[31]_i_107_n_0\,
S(0) => \y_int[31]_i_108_n_0\
);
\y_int_reg[31]_i_87\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_88_n_0\,
CO(3) => \y_int_reg[31]_i_87_n_0\,
CO(2) => \y_int_reg[31]_i_87_n_1\,
CO(1) => \y_int_reg[31]_i_87_n_2\,
CO(0) => \y_int_reg[31]_i_87_n_3\,
CYINIT => '0',
DI(3) => rgb888(6),
DI(2 downto 0) => rgb888(7 downto 5),
O(3) => \y_int_reg[31]_i_87_n_4\,
O(2) => \y_int_reg[31]_i_87_n_5\,
O(1) => \y_int_reg[31]_i_87_n_6\,
O(0) => \y_int_reg[31]_i_87_n_7\,
S(3) => \y_int[31]_i_109_n_0\,
S(2) => \y_int[31]_i_110_n_0\,
S(1) => \y_int[31]_i_111_n_0\,
S(0) => \y_int[31]_i_112_n_0\
);
\y_int_reg[31]_i_88\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[31]_i_88_n_0\,
CO(2) => \y_int_reg[31]_i_88_n_1\,
CO(1) => \y_int_reg[31]_i_88_n_2\,
CO(0) => \y_int_reg[31]_i_88_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(4 downto 2),
DI(0) => '0',
O(3) => \y_int_reg[31]_i_88_n_4\,
O(2) => \y_int_reg[31]_i_88_n_5\,
O(1) => \y_int_reg[31]_i_88_n_6\,
O(0) => \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_113_n_0\,
S(2) => \y_int[31]_i_114_n_0\,
S(1) => \y_int[31]_i_115_n_0\,
S(0) => \y_int[31]_i_116_n_0\
);
\y_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_4\,
Q => \y_int_reg_n_0_[3]\,
R => '0'
);
\y_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_1_n_0\,
CO(2) => \y_int_reg[3]_i_1_n_1\,
CO(1) => \y_int_reg[3]_i_1_n_2\,
CO(0) => \y_int_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_2_n_0\,
DI(2) => \y_int[3]_i_3_n_0\,
DI(1) => \y_int[3]_i_4_n_0\,
DI(0) => '0',
O(3) => \y_int_reg[3]_i_1_n_4\,
O(2) => \y_int_reg[3]_i_1_n_5\,
O(1) => \y_int_reg[3]_i_1_n_6\,
O(0) => \y_int_reg[3]_i_1_n_7\,
S(3) => \y_int[3]_i_5_n_0\,
S(2) => \y_int[3]_i_6_n_0\,
S(1) => \y_int[3]_i_7_n_0\,
S(0) => \y_int[3]_i_8_n_0\
);
\y_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_21_n_0\,
CO(3) => \y_int_reg[3]_i_15_n_0\,
CO(2) => \y_int_reg[3]_i_15_n_1\,
CO(1) => \y_int_reg[3]_i_15_n_2\,
CO(0) => \y_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => y_int_reg5(8),
O(2 downto 0) => \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0),
S(3) => \y_int[3]_i_22_n_0\,
S(2) => \y_int[3]_i_23_n_0\,
S(1) => \y_int[3]_i_24_n_0\,
S(0) => \y_int[3]_i_25_n_0\
);
\y_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_26_n_0\,
CO(3) => \y_int_reg[3]_i_16_n_0\,
CO(2) => \y_int_reg[3]_i_16_n_1\,
CO(1) => \y_int_reg[3]_i_16_n_2\,
CO(0) => \y_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_27_n_0\,
DI(2) => \y_int[3]_i_28_n_0\,
DI(1) => \y_int[3]_i_29_n_0\,
DI(0) => \y_int_reg[3]_i_30_n_6\,
O(3) => \y_int_reg[3]_i_16_n_4\,
O(2) => \y_int_reg[3]_i_16_n_5\,
O(1) => \y_int_reg[3]_i_16_n_6\,
O(0) => \y_int_reg[3]_i_16_n_7\,
S(3) => \y_int[3]_i_31_n_0\,
S(2) => \y_int[3]_i_32_n_0\,
S(1) => \y_int[3]_i_33_n_0\,
S(0) => \y_int[3]_i_34_n_0\
);
\y_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_21_n_0\,
CO(2) => \y_int_reg[3]_i_21_n_1\,
CO(1) => \y_int_reg[3]_i_21_n_2\,
CO(0) => \y_int_reg[3]_i_21_n_3\,
CYINIT => \y_int[3]_i_50_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_51_n_0\,
S(2) => \y_int[3]_i_52_n_0\,
S(1) => \y_int[3]_i_53_n_0\,
S(0) => \y_int[3]_i_54_n_0\
);
\y_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_26_n_0\,
CO(2) => \y_int_reg[3]_i_26_n_1\,
CO(1) => \y_int_reg[3]_i_26_n_2\,
CO(0) => \y_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[3]_i_30_n_7\,
DI(2) => \y_int_reg[3]_i_55_n_4\,
DI(1) => \y_int_reg[3]_i_55_n_5\,
DI(0) => '0',
O(3) => \y_int_reg[3]_i_26_n_4\,
O(2) => \y_int_reg[3]_i_26_n_5\,
O(1) => \y_int_reg[3]_i_26_n_6\,
O(0) => \y_int_reg[3]_i_26_n_7\,
S(3) => \y_int[3]_i_56_n_0\,
S(2) => \y_int[3]_i_57_n_0\,
S(1) => \y_int[3]_i_58_n_0\,
S(0) => \y_int[3]_i_59_n_0\
);
\y_int_reg[3]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_55_n_0\,
CO(3) => \y_int_reg[3]_i_30_n_0\,
CO(2) => \y_int_reg[3]_i_30_n_1\,
CO(1) => \y_int_reg[3]_i_30_n_2\,
CO(0) => \y_int_reg[3]_i_30_n_3\,
CYINIT => '0',
DI(3) => rgb888(22),
DI(2 downto 0) => rgb888(23 downto 21),
O(3) => \y_int_reg[3]_i_30_n_4\,
O(2) => \y_int_reg[3]_i_30_n_5\,
O(1) => \y_int_reg[3]_i_30_n_6\,
O(0) => \y_int_reg[3]_i_30_n_7\,
S(3) => \y_int[3]_i_60_n_0\,
S(2) => \y_int[3]_i_61_n_0\,
S(1) => \y_int[3]_i_62_n_0\,
S(0) => \y_int[3]_i_63_n_0\
);
\y_int_reg[3]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_65_n_0\,
CO(3) => \y_int_reg[3]_i_35_n_0\,
CO(2) => \y_int_reg[3]_i_35_n_1\,
CO(1) => \y_int_reg[3]_i_35_n_2\,
CO(0) => \y_int_reg[3]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[3]_i_35_n_4\,
O(2 downto 0) => \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\(2 downto 0),
S(3) => \y_int[3]_i_66_n_0\,
S(2) => \y_int[3]_i_67_n_0\,
S(1) => \y_int[3]_i_68_n_0\,
S(0) => \y_int[3]_i_69_n_0\
);
\y_int_reg[3]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_2\(0),
CO(2) => \y_int_reg[3]_i_36_n_1\,
CO(1) => \y_int_reg[3]_i_36_n_2\,
CO(0) => \y_int_reg[3]_i_36_n_3\,
CYINIT => '0',
DI(3 downto 2) => \rgb888[8]_32\(1 downto 0),
DI(1) => \rgb888[8]_19\(2),
DI(0) => '0',
O(3 downto 0) => \^y_int_reg[3]_0\(3 downto 0),
S(3) => \y_int[3]_i_71_n_0\,
S(2) => \y_int[3]_i_72_n_0\,
S(1) => \y_int[3]_i_73_n_0\,
S(0) => \y_int[3]_i_74_n_0\
);
\y_int_reg[3]_i_55\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_55_n_0\,
CO(2) => \y_int_reg[3]_i_55_n_1\,
CO(1) => \y_int_reg[3]_i_55_n_2\,
CO(0) => \y_int_reg[3]_i_55_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(20 downto 18),
DI(0) => '0',
O(3) => \y_int_reg[3]_i_55_n_4\,
O(2) => \y_int_reg[3]_i_55_n_5\,
O(1) => \y_int_reg[3]_i_55_n_6\,
O(0) => \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\(0),
S(3) => \y_int[3]_i_84_n_0\,
S(2) => \y_int[3]_i_85_n_0\,
S(1) => \y_int[3]_i_86_n_0\,
S(0) => \y_int[3]_i_87_n_0\
);
\y_int_reg[3]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_30_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[3]_i_64_n_2\,
CO(0) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(23),
O(3 downto 1) => \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[3]_i_64_n_7\,
S(3 downto 1) => B"001",
S(0) => \y_int[3]_i_88_n_0\
);
\y_int_reg[3]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_65_n_0\,
CO(2) => \y_int_reg[3]_i_65_n_1\,
CO(1) => \y_int_reg[3]_i_65_n_2\,
CO(0) => \y_int_reg[3]_i_65_n_3\,
CYINIT => \cr_int[3]_i_80_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_89_n_0\,
S(2) => \y_int[3]_i_90_n_0\,
S(1) => \y_int[3]_i_91_n_0\,
S(0) => \y_int[3]_i_92_n_0\
);
\y_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_7\,
Q => \y_int_reg_n_0_[4]\,
R => '0'
);
\y_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_6\,
Q => \y_int_reg_n_0_[5]\,
R => '0'
);
\y_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_5\,
Q => \y_int_reg_n_0_[6]\,
R => '0'
);
\y_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_4\,
Q => \y_int_reg_n_0_[7]\,
R => '0'
);
\y_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_1_n_0\,
CO(3) => \y_int_reg[7]_i_1_n_0\,
CO(2) => \y_int_reg[7]_i_1_n_1\,
CO(1) => \y_int_reg[7]_i_1_n_2\,
CO(0) => \y_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[7]_i_2_n_0\,
DI(2) => \y_int[7]_i_3_n_0\,
DI(1) => \y_int[7]_i_4_n_0\,
DI(0) => \y_int[7]_i_5_n_0\,
O(3) => \y_int_reg[7]_i_1_n_4\,
O(2) => \y_int_reg[7]_i_1_n_5\,
O(1) => \y_int_reg[7]_i_1_n_6\,
O(0) => \y_int_reg[7]_i_1_n_7\,
S(3) => \y_int[7]_i_6_n_0\,
S(2) => \y_int[7]_i_7_n_0\,
S(1) => \y_int[7]_i_8_n_0\,
S(0) => \y_int[7]_i_9_n_0\
);
\y_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[7]_i_24_n_0\,
CO(2) => \y_int_reg[7]_i_24_n_1\,
CO(1) => \y_int_reg[7]_i_24_n_2\,
CO(0) => \y_int_reg[7]_i_24_n_3\,
CYINIT => \y_int[7]_i_29_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[7]_i_24_n_4\,
O(2) => \y_int_reg[7]_i_24_n_5\,
O(1) => \y_int_reg[7]_i_24_n_6\,
O(0) => \y_int_reg[7]_i_24_n_7\,
S(3) => \y_int[7]_i_30_n_0\,
S(2) => \y_int[7]_i_31_n_0\,
S(1) => \y_int[7]_i_32_n_0\,
S(0) => \y_int[7]_i_33_n_0\
);
\y_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_7\,
Q => \y_int_reg__0\(8),
R => '0'
);
\y_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_6\,
Q => \y_int_reg__0\(9),
R => '0'
);
\y_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[0]_i_1_n_0\,
Q => y(0),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[1]_i_1_n_0\,
Q => y(1),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[2]_i_1_n_0\,
Q => y(2),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[3]_i_1_n_0\,
Q => y(3),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[4]_i_1_n_0\,
Q => y(4),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[5]_i_1_n_0\,
Q => y(5),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[6]_i_1_n_0\,
Q => y(6),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[7]_i_2_n_0\,
Q => y(7),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_reg[7]_i_3_n_0\,
CO(3) => \y_reg[7]_i_1_n_0\,
CO(2) => \y_reg[7]_i_1_n_1\,
CO(1) => \y_reg[7]_i_1_n_2\,
CO(0) => \y_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_4_n_0\,
DI(2) => \y[7]_i_5_n_0\,
DI(1) => \y[7]_i_6_n_0\,
DI(0) => \y[7]_i_7_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_8_n_0\,
S(2) => \y[7]_i_9_n_0\,
S(1) => \y[7]_i_10_n_0\,
S(0) => \y[7]_i_11_n_0\
);
\y_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_reg[7]_i_12_n_0\,
CO(2) => \y_reg[7]_i_12_n_1\,
CO(1) => \y_reg[7]_i_12_n_2\,
CO(0) => \y_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_21_n_0\,
DI(2) => \y[7]_i_22_n_0\,
DI(1) => \y[7]_i_23_n_0\,
DI(0) => \y[7]_i_24_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_25_n_0\,
S(2) => \y[7]_i_26_n_0\,
S(1) => \y[7]_i_27_n_0\,
S(0) => \y[7]_i_28_n_0\
);
\y_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \y_reg[7]_i_12_n_0\,
CO(3) => \y_reg[7]_i_3_n_0\,
CO(2) => \y_reg[7]_i_3_n_1\,
CO(1) => \y_reg[7]_i_3_n_2\,
CO(0) => \y_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_13_n_0\,
DI(2) => \y[7]_i_14_n_0\,
DI(1) => \y[7]_i_15_n_0\,
DI(0) => \y[7]_i_16_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_17_n_0\,
S(2) => \y[7]_i_18_n_0\,
S(1) => \y[7]_i_19_n_0\,
S(0) => \y[7]_i_20_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_zed_hdmi_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_zed_hdmi_0_0 : entity is "system_zed_hdmi_0_0,zed_hdmi,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_zed_hdmi_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_zed_hdmi_0_0 : entity is "zed_hdmi,Vivado 2016.4";
end system_zed_hdmi_0_0;
architecture STRUCTURE of system_zed_hdmi_0_0 is
signal \<const0>\ : STD_LOGIC;
signal U0_n_10 : STD_LOGIC;
signal U0_n_11 : STD_LOGIC;
signal U0_n_12 : STD_LOGIC;
signal U0_n_13 : STD_LOGIC;
signal U0_n_14 : STD_LOGIC;
signal U0_n_15 : STD_LOGIC;
signal U0_n_16 : STD_LOGIC;
signal U0_n_17 : STD_LOGIC;
signal U0_n_18 : STD_LOGIC;
signal U0_n_19 : STD_LOGIC;
signal U0_n_20 : STD_LOGIC;
signal U0_n_21 : STD_LOGIC;
signal U0_n_22 : STD_LOGIC;
signal U0_n_23 : STD_LOGIC;
signal U0_n_24 : STD_LOGIC;
signal U0_n_25 : STD_LOGIC;
signal U0_n_26 : STD_LOGIC;
signal U0_n_27 : STD_LOGIC;
signal U0_n_28 : STD_LOGIC;
signal U0_n_29 : STD_LOGIC;
signal U0_n_30 : STD_LOGIC;
signal U0_n_31 : STD_LOGIC;
signal U0_n_32 : STD_LOGIC;
signal U0_n_33 : STD_LOGIC;
signal U0_n_34 : STD_LOGIC;
signal U0_n_35 : STD_LOGIC;
signal U0_n_36 : STD_LOGIC;
signal U0_n_37 : STD_LOGIC;
signal U0_n_38 : STD_LOGIC;
signal U0_n_39 : STD_LOGIC;
signal U0_n_4 : STD_LOGIC;
signal U0_n_40 : STD_LOGIC;
signal U0_n_41 : STD_LOGIC;
signal U0_n_42 : STD_LOGIC;
signal U0_n_43 : STD_LOGIC;
signal U0_n_44 : STD_LOGIC;
signal U0_n_45 : STD_LOGIC;
signal U0_n_46 : STD_LOGIC;
signal U0_n_47 : STD_LOGIC;
signal U0_n_48 : STD_LOGIC;
signal U0_n_49 : STD_LOGIC;
signal U0_n_5 : STD_LOGIC;
signal U0_n_50 : STD_LOGIC;
signal U0_n_51 : STD_LOGIC;
signal U0_n_52 : STD_LOGIC;
signal U0_n_53 : STD_LOGIC;
signal U0_n_54 : STD_LOGIC;
signal U0_n_55 : STD_LOGIC;
signal U0_n_56 : STD_LOGIC;
signal U0_n_57 : STD_LOGIC;
signal U0_n_58 : STD_LOGIC;
signal U0_n_59 : STD_LOGIC;
signal U0_n_6 : STD_LOGIC;
signal U0_n_60 : STD_LOGIC;
signal U0_n_61 : STD_LOGIC;
signal U0_n_62 : STD_LOGIC;
signal U0_n_63 : STD_LOGIC;
signal U0_n_64 : STD_LOGIC;
signal U0_n_65 : STD_LOGIC;
signal U0_n_66 : STD_LOGIC;
signal U0_n_67 : STD_LOGIC;
signal U0_n_68 : STD_LOGIC;
signal U0_n_69 : STD_LOGIC;
signal U0_n_7 : STD_LOGIC;
signal U0_n_70 : STD_LOGIC;
signal U0_n_71 : STD_LOGIC;
signal U0_n_72 : STD_LOGIC;
signal U0_n_73 : STD_LOGIC;
signal U0_n_74 : STD_LOGIC;
signal U0_n_75 : STD_LOGIC;
signal U0_n_76 : STD_LOGIC;
signal U0_n_77 : STD_LOGIC;
signal U0_n_78 : STD_LOGIC;
signal U0_n_79 : STD_LOGIC;
signal U0_n_8 : STD_LOGIC;
signal U0_n_80 : STD_LOGIC;
signal U0_n_81 : STD_LOGIC;
signal U0_n_9 : STD_LOGIC;
signal \cb_int[15]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_33_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_26_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_90_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_94_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_61_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_85_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_86_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_87_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_33_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_51_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_7\ : STD_LOGIC;
signal \cr_int[11]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_63_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_64_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_54_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_104_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_105_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_106_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_107_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_65_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_98_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_99_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_33_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_7\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_4\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_5\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_6\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_7\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_3\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_4\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_5\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_6\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_7\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \^hdmi_d\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \y_int[11]_i_54_n_0\ : STD_LOGIC;
signal \y_int[11]_i_55_n_0\ : STD_LOGIC;
signal \y_int[11]_i_56_n_0\ : STD_LOGIC;
signal \y_int[11]_i_57_n_0\ : STD_LOGIC;
signal \y_int[15]_i_36_n_0\ : STD_LOGIC;
signal \y_int[15]_i_37_n_0\ : STD_LOGIC;
signal \y_int[15]_i_38_n_0\ : STD_LOGIC;
signal \y_int[15]_i_39_n_0\ : STD_LOGIC;
signal \y_int[15]_i_44_n_0\ : STD_LOGIC;
signal \y_int[15]_i_45_n_0\ : STD_LOGIC;
signal \y_int[15]_i_46_n_0\ : STD_LOGIC;
signal \y_int[15]_i_47_n_0\ : STD_LOGIC;
signal \y_int[19]_i_36_n_0\ : STD_LOGIC;
signal \y_int[19]_i_37_n_0\ : STD_LOGIC;
signal \y_int[19]_i_38_n_0\ : STD_LOGIC;
signal \y_int[19]_i_39_n_0\ : STD_LOGIC;
signal \y_int[19]_i_40_n_0\ : STD_LOGIC;
signal \y_int[19]_i_41_n_0\ : STD_LOGIC;
signal \y_int[19]_i_42_n_0\ : STD_LOGIC;
signal \y_int[19]_i_43_n_0\ : STD_LOGIC;
signal \y_int[19]_i_44_n_0\ : STD_LOGIC;
signal \y_int[19]_i_45_n_0\ : STD_LOGIC;
signal \y_int[19]_i_46_n_0\ : STD_LOGIC;
signal \y_int[19]_i_47_n_0\ : STD_LOGIC;
signal \y_int[23]_i_50_n_0\ : STD_LOGIC;
signal \y_int[23]_i_58_n_0\ : STD_LOGIC;
signal \y_int[23]_i_59_n_0\ : STD_LOGIC;
signal \y_int[23]_i_60_n_0\ : STD_LOGIC;
signal \y_int[23]_i_61_n_0\ : STD_LOGIC;
signal \y_int[31]_i_100_n_0\ : STD_LOGIC;
signal \y_int[31]_i_102_n_0\ : STD_LOGIC;
signal \y_int[31]_i_103_n_0\ : STD_LOGIC;
signal \y_int[31]_i_22_n_0\ : STD_LOGIC;
signal \y_int[31]_i_23_n_0\ : STD_LOGIC;
signal \y_int[31]_i_24_n_0\ : STD_LOGIC;
signal \y_int[31]_i_25_n_0\ : STD_LOGIC;
signal \y_int[31]_i_26_n_0\ : STD_LOGIC;
signal \y_int[31]_i_28_n_0\ : STD_LOGIC;
signal \y_int[31]_i_29_n_0\ : STD_LOGIC;
signal \y_int[31]_i_38_n_0\ : STD_LOGIC;
signal \y_int[31]_i_39_n_0\ : STD_LOGIC;
signal \y_int[31]_i_48_n_0\ : STD_LOGIC;
signal \y_int[31]_i_49_n_0\ : STD_LOGIC;
signal \y_int[31]_i_50_n_0\ : STD_LOGIC;
signal \y_int[31]_i_51_n_0\ : STD_LOGIC;
signal \y_int[31]_i_52_n_0\ : STD_LOGIC;
signal \y_int[31]_i_53_n_0\ : STD_LOGIC;
signal \y_int[31]_i_54_n_0\ : STD_LOGIC;
signal \y_int[31]_i_55_n_0\ : STD_LOGIC;
signal \y_int[31]_i_56_n_0\ : STD_LOGIC;
signal \y_int[31]_i_57_n_0\ : STD_LOGIC;
signal \y_int[31]_i_58_n_0\ : STD_LOGIC;
signal \y_int[31]_i_59_n_0\ : STD_LOGIC;
signal \y_int[31]_i_60_n_0\ : STD_LOGIC;
signal \y_int[31]_i_61_n_0\ : STD_LOGIC;
signal \y_int[31]_i_72_n_0\ : STD_LOGIC;
signal \y_int[31]_i_73_n_0\ : STD_LOGIC;
signal \y_int[31]_i_74_n_0\ : STD_LOGIC;
signal \y_int[31]_i_76_n_0\ : STD_LOGIC;
signal \y_int[31]_i_77_n_0\ : STD_LOGIC;
signal \y_int[31]_i_78_n_0\ : STD_LOGIC;
signal \y_int[31]_i_79_n_0\ : STD_LOGIC;
signal \y_int[31]_i_80_n_0\ : STD_LOGIC;
signal \y_int[31]_i_81_n_0\ : STD_LOGIC;
signal \y_int[31]_i_83_n_0\ : STD_LOGIC;
signal \y_int[31]_i_84_n_0\ : STD_LOGIC;
signal \y_int[31]_i_85_n_0\ : STD_LOGIC;
signal \y_int[31]_i_93_n_0\ : STD_LOGIC;
signal \y_int[31]_i_94_n_0\ : STD_LOGIC;
signal \y_int[31]_i_95_n_0\ : STD_LOGIC;
signal \y_int[31]_i_96_n_0\ : STD_LOGIC;
signal \y_int[31]_i_97_n_0\ : STD_LOGIC;
signal \y_int[31]_i_98_n_0\ : STD_LOGIC;
signal \y_int[31]_i_99_n_0\ : STD_LOGIC;
signal \y_int[3]_i_37_n_0\ : STD_LOGIC;
signal \y_int[3]_i_38_n_0\ : STD_LOGIC;
signal \y_int[3]_i_39_n_0\ : STD_LOGIC;
signal \y_int[3]_i_41_n_0\ : STD_LOGIC;
signal \y_int[3]_i_42_n_0\ : STD_LOGIC;
signal \y_int[3]_i_43_n_0\ : STD_LOGIC;
signal \y_int[3]_i_44_n_0\ : STD_LOGIC;
signal \y_int[3]_i_46_n_0\ : STD_LOGIC;
signal \y_int[3]_i_47_n_0\ : STD_LOGIC;
signal \y_int[3]_i_48_n_0\ : STD_LOGIC;
signal \y_int[3]_i_49_n_0\ : STD_LOGIC;
signal \y_int[3]_i_75_n_0\ : STD_LOGIC;
signal \y_int[3]_i_76_n_0\ : STD_LOGIC;
signal \y_int[3]_i_77_n_0\ : STD_LOGIC;
signal \y_int[3]_i_78_n_0\ : STD_LOGIC;
signal \y_int[3]_i_79_n_0\ : STD_LOGIC;
signal \y_int[3]_i_80_n_0\ : STD_LOGIC;
signal \y_int[3]_i_81_n_0\ : STD_LOGIC;
signal \y_int[3]_i_82_n_0\ : STD_LOGIC;
signal \y_int[3]_i_83_n_0\ : STD_LOGIC;
signal \y_int[3]_i_93_n_0\ : STD_LOGIC;
signal \y_int[3]_i_94_n_0\ : STD_LOGIC;
signal \y_int[3]_i_95_n_0\ : STD_LOGIC;
signal \y_int[3]_i_96_n_0\ : STD_LOGIC;
signal \y_int[7]_i_25_n_0\ : STD_LOGIC;
signal \y_int[7]_i_26_n_0\ : STD_LOGIC;
signal \y_int[7]_i_27_n_0\ : STD_LOGIC;
signal \y_int[7]_i_28_n_0\ : STD_LOGIC;
signal y_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 9 );
signal \y_int_reg[11]_i_27_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_32_n_7\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_4\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_5\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_6\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_7\ : STD_LOGIC;
signal \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute HLUTNM : string;
attribute HLUTNM of \cb_int[3]_i_35\ : label is "lutpair0";
attribute HLUTNM of \cb_int[3]_i_40\ : label is "lutpair0";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y_int[31]_i_57\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \y_int[31]_i_80\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \y_int[31]_i_81\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \y_int[31]_i_84\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \y_int[31]_i_85\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \y_int[3]_i_79\ : label is "soft_lutpair38";
begin
hdmi_d(15 downto 8) <= \^hdmi_d\(15 downto 8);
hdmi_d(7) <= \<const0>\;
hdmi_d(6) <= \<const0>\;
hdmi_d(5) <= \<const0>\;
hdmi_d(4) <= \<const0>\;
hdmi_d(3) <= \<const0>\;
hdmi_d(2) <= \<const0>\;
hdmi_d(1) <= \<const0>\;
hdmi_d(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_zed_hdmi_0_0_zed_hdmi
port map (
CO(0) => U0_n_16,
DI(0) => U0_n_4,
O(1) => U0_n_7,
O(0) => U0_n_8,
active => active,
\cb_int_reg[15]_0\(0) => U0_n_76,
\cb_int_reg[27]_0\(0) => U0_n_75,
\cb_int_reg[3]_0\(3) => U0_n_9,
\cb_int_reg[3]_0\(2) => U0_n_10,
\cb_int_reg[3]_0\(1) => U0_n_11,
\cb_int_reg[3]_0\(0) => U0_n_12,
\cb_int_reg[3]_1\(0) => U0_n_72,
\cb_int_reg[3]_2\(0) => U0_n_73,
\cb_int_reg[3]_3\(0) => U0_n_74,
clk => clk,
clk_100 => clk_100,
clk_x2 => clk_x2,
\cr_int_reg[11]_0\(3) => U0_n_34,
\cr_int_reg[11]_0\(2) => U0_n_35,
\cr_int_reg[11]_0\(1) => U0_n_36,
\cr_int_reg[11]_0\(0) => U0_n_37,
\cr_int_reg[15]_0\(3) => U0_n_38,
\cr_int_reg[15]_0\(2) => U0_n_39,
\cr_int_reg[15]_0\(1) => U0_n_40,
\cr_int_reg[15]_0\(0) => U0_n_41,
\cr_int_reg[15]_1\(0) => U0_n_77,
\cr_int_reg[19]_0\(3) => U0_n_42,
\cr_int_reg[19]_0\(2) => U0_n_43,
\cr_int_reg[19]_0\(1) => U0_n_44,
\cr_int_reg[19]_0\(0) => U0_n_45,
\cr_int_reg[23]_0\(3) => U0_n_46,
\cr_int_reg[23]_0\(2) => U0_n_47,
\cr_int_reg[23]_0\(1) => U0_n_48,
\cr_int_reg[23]_0\(0) => U0_n_49,
\cr_int_reg[23]_1\(0) => U0_n_50,
\cr_int_reg[27]_0\ => U0_n_13,
\cr_int_reg[27]_1\(1) => U0_n_14,
\cr_int_reg[27]_1\(0) => U0_n_15,
\cr_int_reg[27]_2\(0) => U0_n_29,
\cr_int_reg[31]_0\ => U0_n_5,
\cr_int_reg[31]_1\ => U0_n_6,
\cr_int_reg[31]_2\(1) => U0_n_17,
\cr_int_reg[31]_2\(0) => U0_n_18,
\cr_int_reg[3]_0\(2) => U0_n_23,
\cr_int_reg[3]_0\(1) => U0_n_24,
\cr_int_reg[3]_0\(0) => U0_n_25,
\cr_int_reg[3]_1\(0) => U0_n_26,
\cr_int_reg[3]_2\(1) => U0_n_27,
\cr_int_reg[3]_2\(0) => U0_n_28,
\cr_int_reg[7]_0\(3) => U0_n_19,
\cr_int_reg[7]_0\(2) => U0_n_20,
\cr_int_reg[7]_0\(1) => U0_n_21,
\cr_int_reg[7]_0\(0) => U0_n_22,
\cr_int_reg[7]_1\(3) => U0_n_30,
\cr_int_reg[7]_1\(2) => U0_n_31,
\cr_int_reg[7]_1\(1) => U0_n_32,
\cr_int_reg[7]_1\(0) => U0_n_33,
hdmi_clk => hdmi_clk,
hdmi_d(7 downto 0) => \^hdmi_d\(15 downto 8),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
hsync => hsync,
rgb888(23 downto 0) => rgb888(23 downto 0),
\rgb888[0]\(3) => \cb_int_reg[31]_i_8_n_4\,
\rgb888[0]\(2) => \cb_int_reg[31]_i_8_n_5\,
\rgb888[0]\(1) => \cb_int_reg[31]_i_8_n_6\,
\rgb888[0]\(0) => \cb_int_reg[31]_i_8_n_7\,
\rgb888[0]_0\(3) => \cb_int_reg[31]_i_17_n_4\,
\rgb888[0]_0\(2) => \cb_int_reg[31]_i_17_n_5\,
\rgb888[0]_0\(1) => \cb_int_reg[31]_i_17_n_6\,
\rgb888[0]_0\(0) => \cb_int_reg[31]_i_17_n_7\,
\rgb888[0]_1\(1) => \cb_int_reg[31]_i_42_n_6\,
\rgb888[0]_1\(0) => \cb_int_reg[31]_i_42_n_7\,
\rgb888[0]_2\(3) => \cb_int_reg[23]_i_28_n_4\,
\rgb888[0]_2\(2) => \cb_int_reg[23]_i_28_n_5\,
\rgb888[0]_2\(1) => \cb_int_reg[23]_i_28_n_6\,
\rgb888[0]_2\(0) => \cb_int_reg[23]_i_28_n_7\,
\rgb888[0]_3\(3) => \cb_int_reg[19]_i_33_n_4\,
\rgb888[0]_3\(2) => \cb_int_reg[19]_i_33_n_5\,
\rgb888[0]_3\(1) => \cb_int_reg[19]_i_33_n_6\,
\rgb888[0]_3\(0) => \cb_int_reg[19]_i_33_n_7\,
\rgb888[0]_4\(3) => \cb_int_reg[15]_i_34_n_4\,
\rgb888[0]_4\(2) => \cb_int_reg[15]_i_34_n_5\,
\rgb888[0]_4\(1) => \cb_int_reg[15]_i_34_n_6\,
\rgb888[0]_4\(0) => \cb_int_reg[15]_i_34_n_7\,
\rgb888[0]_5\(3) => \cr_int_reg[23]_i_31_n_4\,
\rgb888[0]_5\(2) => \cr_int_reg[23]_i_31_n_5\,
\rgb888[0]_5\(1) => \cr_int_reg[23]_i_31_n_6\,
\rgb888[0]_5\(0) => \cr_int_reg[23]_i_31_n_7\,
\rgb888[0]_6\(1) => \cr_int_reg[31]_i_54_n_6\,
\rgb888[0]_6\(0) => \cr_int_reg[31]_i_54_n_7\,
\rgb888[0]_7\(3) => \y_int_reg[31]_i_71_n_4\,
\rgb888[0]_7\(2) => \y_int_reg[31]_i_71_n_5\,
\rgb888[0]_7\(1) => \y_int_reg[31]_i_71_n_6\,
\rgb888[0]_7\(0) => \y_int_reg[31]_i_71_n_7\,
\rgb888[0]_8\(1) => \cb_int_reg[3]_i_43_n_6\,
\rgb888[0]_8\(0) => \cb_int_reg[3]_i_43_n_7\,
\rgb888[0]_9\(2) => \y_int_reg[31]_i_31_n_5\,
\rgb888[0]_9\(1) => \y_int_reg[31]_i_31_n_6\,
\rgb888[0]_9\(0) => \y_int_reg[31]_i_31_n_7\,
\rgb888[12]\(3) => \cb_int_reg[7]_i_24_n_4\,
\rgb888[12]\(2) => \cb_int_reg[7]_i_24_n_5\,
\rgb888[12]\(1) => \cb_int_reg[7]_i_24_n_6\,
\rgb888[12]\(0) => \cb_int_reg[7]_i_24_n_7\,
\rgb888[12]_0\(3) => \cb_int_reg[15]_i_32_n_4\,
\rgb888[12]_0\(2) => \cb_int_reg[15]_i_32_n_5\,
\rgb888[12]_0\(1) => \cb_int_reg[15]_i_32_n_6\,
\rgb888[12]_0\(0) => \cb_int_reg[15]_i_32_n_7\,
\rgb888[13]\(0) => \cb_int_reg[3]_i_32_n_4\,
\rgb888[13]_0\(3) => \cb_int_reg[7]_i_27_n_4\,
\rgb888[13]_0\(2) => \cb_int_reg[7]_i_27_n_5\,
\rgb888[13]_0\(1) => \cb_int_reg[7]_i_27_n_6\,
\rgb888[13]_0\(0) => \cb_int_reg[7]_i_27_n_7\,
\rgb888[14]\(3) => \y_int_reg[3]_i_19_n_4\,
\rgb888[14]\(2) => \y_int_reg[3]_i_19_n_5\,
\rgb888[14]\(1) => \y_int_reg[3]_i_19_n_6\,
\rgb888[14]\(0) => \y_int_reg[3]_i_19_n_7\,
\rgb888[14]_0\(1) => \y_int_reg[3]_i_20_n_4\,
\rgb888[14]_0\(0) => \y_int_reg[3]_i_20_n_5\,
\rgb888[14]_1\(3) => \y_int_reg[7]_i_23_n_4\,
\rgb888[14]_1\(2) => \y_int_reg[7]_i_23_n_5\,
\rgb888[14]_1\(1) => \y_int_reg[7]_i_23_n_6\,
\rgb888[14]_1\(0) => \y_int_reg[7]_i_23_n_7\,
\rgb888[1]\(13 downto 0) => y_int_reg2(22 downto 9),
\rgb888[1]_0\(0) => \y_int_reg[31]_i_12_n_1\,
\rgb888[3]\(3) => \cr_int_reg[15]_i_39_n_4\,
\rgb888[3]\(2) => \cr_int_reg[15]_i_39_n_5\,
\rgb888[3]\(1) => \cr_int_reg[15]_i_39_n_6\,
\rgb888[3]\(0) => \cr_int_reg[15]_i_39_n_7\,
\rgb888[3]_0\(3) => \cr_int_reg[19]_i_37_n_4\,
\rgb888[3]_0\(2) => \cr_int_reg[19]_i_37_n_5\,
\rgb888[3]_0\(1) => \cr_int_reg[19]_i_37_n_6\,
\rgb888[3]_0\(0) => \cr_int_reg[19]_i_37_n_7\,
\rgb888[8]\(3) => \cb_int_reg[3]_i_19_n_4\,
\rgb888[8]\(2) => \cb_int_reg[3]_i_19_n_5\,
\rgb888[8]\(1) => \cb_int_reg[3]_i_19_n_6\,
\rgb888[8]\(0) => \cb_int_reg[3]_i_19_n_7\,
\rgb888[8]_0\(3) => \cb_int_reg[31]_i_23_n_4\,
\rgb888[8]_0\(2) => \cb_int_reg[31]_i_23_n_5\,
\rgb888[8]_0\(1) => \cb_int_reg[31]_i_23_n_6\,
\rgb888[8]_0\(0) => \cb_int_reg[31]_i_23_n_7\,
\rgb888[8]_1\(1) => \cb_int_reg[31]_i_9_n_6\,
\rgb888[8]_1\(0) => \cb_int_reg[31]_i_9_n_7\,
\rgb888[8]_10\(1) => \cb_int_reg[31]_i_66_n_6\,
\rgb888[8]_10\(0) => \cb_int_reg[31]_i_66_n_7\,
\rgb888[8]_11\(0) => \cb_int_reg[31]_i_10_n_1\,
\rgb888[8]_12\(3) => \cr_int_reg[7]_i_24_n_4\,
\rgb888[8]_12\(2) => \cr_int_reg[7]_i_24_n_5\,
\rgb888[8]_12\(1) => \cr_int_reg[7]_i_24_n_6\,
\rgb888[8]_12\(0) => \cr_int_reg[7]_i_24_n_7\,
\rgb888[8]_13\(3) => \cr_int_reg[11]_i_28_n_4\,
\rgb888[8]_13\(2) => \cr_int_reg[11]_i_28_n_5\,
\rgb888[8]_13\(1) => \cr_int_reg[11]_i_28_n_6\,
\rgb888[8]_13\(0) => \cr_int_reg[11]_i_28_n_7\,
\rgb888[8]_14\(3) => \cr_int_reg[15]_i_37_n_4\,
\rgb888[8]_14\(2) => \cr_int_reg[15]_i_37_n_5\,
\rgb888[8]_14\(1) => \cr_int_reg[15]_i_37_n_6\,
\rgb888[8]_14\(0) => \cr_int_reg[15]_i_37_n_7\,
\rgb888[8]_15\(3) => \cr_int_reg[31]_i_64_n_4\,
\rgb888[8]_15\(2) => \cr_int_reg[31]_i_64_n_5\,
\rgb888[8]_15\(1) => \cr_int_reg[31]_i_64_n_6\,
\rgb888[8]_15\(0) => \cr_int_reg[31]_i_64_n_7\,
\rgb888[8]_16\(3) => \cr_int_reg[31]_i_27_n_4\,
\rgb888[8]_16\(2) => \cr_int_reg[31]_i_27_n_5\,
\rgb888[8]_16\(1) => \cr_int_reg[31]_i_27_n_6\,
\rgb888[8]_16\(0) => \cr_int_reg[31]_i_27_n_7\,
\rgb888[8]_17\(1) => \cr_int_reg[31]_i_10_n_6\,
\rgb888[8]_17\(0) => \cr_int_reg[31]_i_10_n_7\,
\rgb888[8]_18\(0) => \cr_int_reg[31]_i_10_n_1\,
\rgb888[8]_19\(2) => \y_int_reg[3]_i_70_n_4\,
\rgb888[8]_19\(1) => \y_int_reg[3]_i_70_n_5\,
\rgb888[8]_19\(0) => \y_int_reg[3]_i_70_n_6\,
\rgb888[8]_2\(3) => \cb_int_reg[7]_i_26_n_4\,
\rgb888[8]_2\(2) => \cb_int_reg[7]_i_26_n_5\,
\rgb888[8]_2\(1) => \cb_int_reg[7]_i_26_n_6\,
\rgb888[8]_2\(0) => \cb_int_reg[7]_i_26_n_7\,
\rgb888[8]_20\(3) => \y_int_reg[31]_i_21_n_4\,
\rgb888[8]_20\(2) => \y_int_reg[31]_i_21_n_5\,
\rgb888[8]_20\(1) => \y_int_reg[31]_i_21_n_6\,
\rgb888[8]_20\(0) => \y_int_reg[31]_i_21_n_7\,
\rgb888[8]_21\(2) => \y_int_reg[31]_i_9_n_5\,
\rgb888[8]_21\(1) => \y_int_reg[31]_i_9_n_6\,
\rgb888[8]_21\(0) => \y_int_reg[31]_i_9_n_7\,
\rgb888[8]_22\(3) => \y_int_reg[11]_i_27_n_4\,
\rgb888[8]_22\(2) => \y_int_reg[11]_i_27_n_5\,
\rgb888[8]_22\(1) => \y_int_reg[11]_i_27_n_6\,
\rgb888[8]_22\(0) => \y_int_reg[11]_i_27_n_7\,
\rgb888[8]_23\(1) => \y_int_reg[31]_i_10_n_6\,
\rgb888[8]_23\(0) => \y_int_reg[31]_i_10_n_7\,
\rgb888[8]_24\(0) => \y_int_reg[23]_i_32_n_7\,
\rgb888[8]_25\(3) => \y_int_reg[23]_i_35_n_4\,
\rgb888[8]_25\(2) => \y_int_reg[23]_i_35_n_5\,
\rgb888[8]_25\(1) => \y_int_reg[23]_i_35_n_6\,
\rgb888[8]_25\(0) => \y_int_reg[23]_i_35_n_7\,
\rgb888[8]_26\(3) => \y_int_reg[31]_i_27_n_4\,
\rgb888[8]_26\(2) => \y_int_reg[31]_i_27_n_5\,
\rgb888[8]_26\(1) => \y_int_reg[31]_i_27_n_6\,
\rgb888[8]_26\(0) => \y_int_reg[31]_i_27_n_7\,
\rgb888[8]_27\(3) => \y_int_reg[19]_i_24_n_4\,
\rgb888[8]_27\(2) => \y_int_reg[19]_i_24_n_5\,
\rgb888[8]_27\(1) => \y_int_reg[19]_i_24_n_6\,
\rgb888[8]_27\(0) => \y_int_reg[19]_i_24_n_7\,
\rgb888[8]_28\(3) => \y_int_reg[19]_i_33_n_4\,
\rgb888[8]_28\(2) => \y_int_reg[19]_i_33_n_5\,
\rgb888[8]_28\(1) => \y_int_reg[19]_i_33_n_6\,
\rgb888[8]_28\(0) => \y_int_reg[19]_i_33_n_7\,
\rgb888[8]_29\(3) => \y_int_reg[15]_i_24_n_4\,
\rgb888[8]_29\(2) => \y_int_reg[15]_i_24_n_5\,
\rgb888[8]_29\(1) => \y_int_reg[15]_i_24_n_6\,
\rgb888[8]_29\(0) => \y_int_reg[15]_i_24_n_7\,
\rgb888[8]_3\(3) => \cb_int_reg[7]_i_23_n_4\,
\rgb888[8]_3\(2) => \cb_int_reg[7]_i_23_n_5\,
\rgb888[8]_3\(1) => \cb_int_reg[7]_i_23_n_6\,
\rgb888[8]_3\(0) => \cb_int_reg[7]_i_23_n_7\,
\rgb888[8]_30\(0) => \y_int_reg[31]_i_10_n_1\,
\rgb888[8]_31\(2) => \cb_int_reg[3]_i_68_n_5\,
\rgb888[8]_31\(1) => \cb_int_reg[3]_i_68_n_6\,
\rgb888[8]_31\(0) => \cb_int_reg[3]_i_68_n_7\,
\rgb888[8]_32\(1) => \y_int_reg[3]_i_40_n_6\,
\rgb888[8]_32\(0) => \y_int_reg[3]_i_40_n_7\,
\rgb888[8]_4\(3) => \cb_int_reg[15]_i_31_n_4\,
\rgb888[8]_4\(2) => \cb_int_reg[15]_i_31_n_5\,
\rgb888[8]_4\(1) => \cb_int_reg[15]_i_31_n_6\,
\rgb888[8]_4\(0) => \cb_int_reg[15]_i_31_n_7\,
\rgb888[8]_5\(3) => \cb_int_reg[31]_i_61_n_4\,
\rgb888[8]_5\(2) => \cb_int_reg[31]_i_61_n_5\,
\rgb888[8]_5\(1) => \cb_int_reg[31]_i_61_n_6\,
\rgb888[8]_5\(0) => \cb_int_reg[31]_i_61_n_7\,
\rgb888[8]_6\(3) => \cb_int_reg[19]_i_32_n_4\,
\rgb888[8]_6\(2) => \cb_int_reg[19]_i_32_n_5\,
\rgb888[8]_6\(1) => \cb_int_reg[19]_i_32_n_6\,
\rgb888[8]_6\(0) => \cb_int_reg[19]_i_32_n_7\,
\rgb888[8]_7\(3) => \cb_int_reg[31]_i_27_n_4\,
\rgb888[8]_7\(2) => \cb_int_reg[31]_i_27_n_5\,
\rgb888[8]_7\(1) => \cb_int_reg[31]_i_27_n_6\,
\rgb888[8]_7\(0) => \cb_int_reg[31]_i_27_n_7\,
\rgb888[8]_8\(3) => \cb_int_reg[23]_i_27_n_4\,
\rgb888[8]_8\(2) => \cb_int_reg[23]_i_27_n_5\,
\rgb888[8]_8\(1) => \cb_int_reg[23]_i_27_n_6\,
\rgb888[8]_8\(0) => \cb_int_reg[23]_i_27_n_7\,
\rgb888[8]_9\(1) => \cb_int_reg[31]_i_10_n_6\,
\rgb888[8]_9\(0) => \cb_int_reg[31]_i_10_n_7\,
vsync => vsync,
\y_int_reg[15]_0\(3) => U0_n_68,
\y_int_reg[15]_0\(2) => U0_n_69,
\y_int_reg[15]_0\(1) => U0_n_70,
\y_int_reg[15]_0\(0) => U0_n_71,
\y_int_reg[15]_1\(0) => U0_n_81,
\y_int_reg[19]_0\(3) => U0_n_64,
\y_int_reg[19]_0\(2) => U0_n_65,
\y_int_reg[19]_0\(1) => U0_n_66,
\y_int_reg[19]_0\(0) => U0_n_67,
\y_int_reg[19]_1\(0) => U0_n_79,
\y_int_reg[23]_0\(0) => U0_n_55,
\y_int_reg[23]_1\(1) => U0_n_58,
\y_int_reg[23]_1\(0) => U0_n_59,
\y_int_reg[23]_2\(3) => U0_n_60,
\y_int_reg[23]_2\(2) => U0_n_61,
\y_int_reg[23]_2\(1) => U0_n_62,
\y_int_reg[23]_2\(0) => U0_n_63,
\y_int_reg[23]_3\(0) => U0_n_80,
\y_int_reg[3]_0\(3) => U0_n_51,
\y_int_reg[3]_0\(2) => U0_n_52,
\y_int_reg[3]_0\(1) => U0_n_53,
\y_int_reg[3]_0\(0) => U0_n_54,
\y_int_reg[3]_1\(0) => U0_n_57,
\y_int_reg[3]_2\(0) => U0_n_78,
\y_int_reg[7]_0\(0) => U0_n_56
);
\cb_int[15]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_4\,
O => \cb_int[15]_i_35_n_0\
);
\cb_int[15]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_5\,
O => \cb_int[15]_i_36_n_0\
);
\cb_int[15]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_6\,
O => \cb_int[15]_i_37_n_0\
);
\cb_int[15]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_7\,
O => \cb_int[15]_i_38_n_0\
);
\cb_int[15]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_39_n_0\
);
\cb_int[15]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_40_n_0\
);
\cb_int[15]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_41_n_0\
);
\cb_int[15]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_42_n_0\
);
\cb_int[15]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_47_n_0\
);
\cb_int[15]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_48_n_0\
);
\cb_int[15]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_49_n_0\
);
\cb_int[15]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_50_n_0\
);
\cb_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_38_n_0\
);
\cb_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_39_n_0\
);
\cb_int[19]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_40_n_0\
);
\cb_int[19]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_41_n_0\
);
\cb_int[19]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_42_n_0\
);
\cb_int[19]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_43_n_0\
);
\cb_int[19]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_44_n_0\
);
\cb_int[19]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_45_n_0\
);
\cb_int[23]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_33_n_0\
);
\cb_int[23]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_34_n_0\
);
\cb_int[23]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_35_n_0\
);
\cb_int[23]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_36_n_0\
);
\cb_int[23]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_37_n_0\
);
\cb_int[23]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_38_n_0\
);
\cb_int[23]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_39_n_0\
);
\cb_int[23]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_40_n_0\
);
\cb_int[31]_i_100\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(14),
O => \cb_int[31]_i_100_n_0\
);
\cb_int[31]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(13),
O => \cb_int[31]_i_101_n_0\
);
\cb_int[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_n_13,
I1 => rgb888(7),
O => \cb_int[31]_i_18_n_0\
);
\cb_int[31]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_19_n_0\
);
\cb_int[31]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_20_n_0\
);
\cb_int[31]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_21_n_0\
);
\cb_int[31]_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => rgb888(7),
I1 => \cb_int[31]_i_52_n_0\,
I2 => rgb888(6),
O => \cb_int[31]_i_22_n_0\
);
\cb_int[31]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_25_n_0\
);
\cb_int[31]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cb_int[31]_i_26_n_0\
);
\cb_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_66_n_6\,
O => \cb_int[31]_i_28_n_0\
);
\cb_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_66_n_7\,
O => \cb_int[31]_i_29_n_0\
);
\cb_int[31]_i_45\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cb_int[31]_i_45_n_0\
);
\cb_int[31]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(2),
I1 => rgb888(1),
O => \cb_int[31]_i_46_n_0\
);
\cb_int[31]_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA955555555"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
I5 => rgb888(5),
O => \cb_int[31]_i_47_n_0\
);
\cb_int[31]_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCC999999993"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(5),
I2 => rgb888(3),
I3 => rgb888(1),
I4 => rgb888(2),
I5 => rgb888(4),
O => \cb_int[31]_i_48_n_0\
);
\cb_int[31]_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA99995"
)
port map (
I0 => rgb888(4),
I1 => \cb_int_reg[3]_i_43_n_1\,
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cb_int[31]_i_49_n_0\
);
\cb_int[31]_i_50\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A95"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
O => \cb_int[31]_i_50_n_0\
);
\cb_int[31]_i_52\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => rgb888(5),
O => \cb_int[31]_i_52_n_0\
);
\cb_int[31]_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => rgb888(14),
I1 => rgb888(12),
I2 => rgb888(10),
I3 => rgb888(11),
I4 => rgb888(13),
I5 => rgb888(15),
O => \cb_int[31]_i_53_n_0\
);
\cb_int[31]_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000006AAAAAAA"
)
port map (
I0 => rgb888(14),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(15),
O => \cb_int[31]_i_54_n_0\
);
\cb_int[31]_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"2BBBBBBBB2222222"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_0\,
I1 => rgb888(15),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(13),
O => \cb_int[31]_i_55_n_0\
);
\cb_int[31]_i_56\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFEA2A80"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_5\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(12),
I4 => rgb888(14),
O => \cb_int[31]_i_56_n_0\
);
\cb_int[31]_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"9555555555555555"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_57_n_0\
);
\cb_int[31]_i_58\: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAAAAAABFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_58_n_0\
);
\cb_int[31]_i_59\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => U0_n_6,
I1 => \cb_int_reg[31]_i_85_n_0\,
I2 => rgb888(15),
I3 => U0_n_5,
O => \cb_int[31]_i_59_n_0\
);
\cb_int[31]_i_60\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(14),
I1 => \cb_int[31]_i_88_n_0\,
I2 => \cb_int_reg[31]_i_85_n_5\,
I3 => U0_n_6,
I4 => rgb888(15),
I5 => \cb_int_reg[31]_i_85_n_0\,
O => \cb_int[31]_i_60_n_0\
);
\cb_int[31]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_4\,
O => \cb_int[31]_i_62_n_0\
);
\cb_int[31]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_5\,
O => \cb_int[31]_i_63_n_0\
);
\cb_int[31]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_6\,
O => \cb_int[31]_i_64_n_0\
);
\cb_int[31]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_7\,
O => \cb_int[31]_i_65_n_0\
);
\cb_int[31]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[31]_i_83_n_0\
);
\cb_int[31]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[31]_i_84_n_0\
);
\cb_int[31]_i_88\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rgb888(10),
I1 => rgb888(11),
I2 => rgb888(12),
O => \cb_int[31]_i_88_n_0\
);
\cb_int[31]_i_89\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_4\,
O => \cb_int[31]_i_89_n_0\
);
\cb_int[31]_i_90\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_5\,
O => \cb_int[31]_i_90_n_0\
);
\cb_int[31]_i_91\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_6\,
O => \cb_int[31]_i_91_n_0\
);
\cb_int[31]_i_92\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_7\,
O => \cb_int[31]_i_92_n_0\
);
\cb_int[31]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[31]_i_93_n_0\
);
\cb_int[31]_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[31]_i_94_n_0\
);
\cb_int[31]_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cb_int[31]_i_99_n_0\
);
\cb_int[3]_i_35\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
O => \cb_int[3]_i_35_n_0\
);
\cb_int[3]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(10),
I1 => \cb_int_reg[31]_i_85_n_7\,
I2 => rgb888(12),
O => \cb_int[3]_i_36_n_0\
);
\cb_int[3]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int_reg[3]_i_68_n_4\,
I1 => rgb888(9),
I2 => rgb888(11),
O => \cb_int[3]_i_37_n_0\
);
\cb_int[3]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int_reg[3]_i_68_n_4\,
I1 => rgb888(9),
I2 => rgb888(11),
O => \cb_int[3]_i_38_n_0\
);
\cb_int[3]_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969969696"
)
port map (
I0 => \cb_int[3]_i_35_n_0\,
I1 => rgb888(14),
I2 => rgb888(12),
I3 => rgb888(11),
I4 => rgb888(10),
I5 => \cb_int_reg[31]_i_85_n_5\,
O => \cb_int[3]_i_39_n_0\
);
\cb_int[3]_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
I4 => \cb_int[3]_i_36_n_0\,
O => \cb_int[3]_i_40_n_0\
);
\cb_int[3]_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => \cb_int_reg[3]_i_68_n_4\,
I3 => rgb888(12),
I4 => rgb888(10),
I5 => \cb_int_reg[31]_i_85_n_7\,
O => \cb_int[3]_i_41_n_0\
);
\cb_int[3]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => \cb_int_reg[3]_i_68_n_4\,
I3 => rgb888(10),
I4 => rgb888(8),
O => \cb_int[3]_i_42_n_0\
);
\cb_int[3]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_6\,
O => \cb_int[3]_i_59_n_0\
);
\cb_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_7\,
O => \cb_int[3]_i_60_n_0\
);
\cb_int[3]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_9,
O => \cb_int[3]_i_61_n_0\
);
\cb_int[3]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_10,
O => \cb_int[3]_i_62_n_0\
);
\cb_int[3]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \cb_int[3]_i_73_n_0\
);
\cb_int[3]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(6),
O => \cb_int[3]_i_74_n_0\
);
\cb_int[3]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(8),
O => \cb_int[3]_i_84_n_0\
);
\cb_int[3]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_11,
O => \cb_int[3]_i_85_n_0\
);
\cb_int[3]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_12,
O => \cb_int[3]_i_86_n_0\
);
\cb_int[3]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_7,
O => \cb_int[3]_i_87_n_0\
);
\cb_int[3]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_8,
O => \cb_int[3]_i_88_n_0\
);
\cb_int[3]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(15),
O => \cb_int[3]_i_95_n_0\
);
\cb_int[3]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(14),
O => \cb_int[3]_i_96_n_0\
);
\cb_int[3]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(13),
O => \cb_int[3]_i_97_n_0\
);
\cb_int[3]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(12),
O => \cb_int[3]_i_98_n_0\
);
\cb_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[7]_i_24_n_4\,
O => \cb_int[7]_i_30_n_0\
);
\cb_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_5\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_9_n_7\,
O => \cb_int[7]_i_31_n_0\
);
\cb_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_4\,
O => \cb_int[7]_i_32_n_0\
);
\cb_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_7\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_5\,
O => \cb_int[7]_i_33_n_0\
);
\cb_int[7]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[7]_i_34_n_0\
);
\cb_int[7]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_7\,
O => \cb_int[7]_i_35_n_0\
);
\cb_int[7]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_4\,
O => \cb_int[7]_i_36_n_0\
);
\cb_int[7]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_5\,
O => \cb_int[7]_i_37_n_0\
);
\cb_int[7]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[3]_i_32_n_4\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_6\,
O => \cb_int[7]_i_43_n_0\
);
\cb_int[7]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_4\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_6\,
O => \cb_int[7]_i_44_n_0\
);
\cb_int[7]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_5\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_7\,
O => \cb_int[7]_i_45_n_0\
);
\cb_int[7]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_4\,
O => \cb_int[7]_i_46_n_0\
);
\cb_int[7]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_7\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_5\,
O => \cb_int[7]_i_47_n_0\
);
\cb_int[7]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_6\,
O => \cb_int[7]_i_48_n_0\
);
\cb_int[7]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_7\,
O => \cb_int[7]_i_49_n_0\
);
\cb_int[7]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_4\,
O => \cb_int[7]_i_50_n_0\
);
\cb_int[7]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_5\,
O => \cb_int[7]_i_51_n_0\
);
\cb_int_reg[15]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_23_n_0\,
CO(3) => \cb_int_reg[15]_i_31_n_0\,
CO(2) => \cb_int_reg[15]_i_31_n_1\,
CO(1) => \cb_int_reg[15]_i_31_n_2\,
CO(0) => \cb_int_reg[15]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_31_n_4\,
O(2) => \cb_int_reg[15]_i_31_n_5\,
O(1) => \cb_int_reg[15]_i_31_n_6\,
O(0) => \cb_int_reg[15]_i_31_n_7\,
S(3) => \cb_int[15]_i_35_n_0\,
S(2) => \cb_int[15]_i_36_n_0\,
S(1) => \cb_int[15]_i_37_n_0\,
S(0) => \cb_int[15]_i_38_n_0\
);
\cb_int_reg[15]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_24_n_0\,
CO(3) => \cb_int_reg[15]_i_32_n_0\,
CO(2) => \cb_int_reg[15]_i_32_n_1\,
CO(1) => \cb_int_reg[15]_i_32_n_2\,
CO(0) => \cb_int_reg[15]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_32_n_4\,
O(2) => \cb_int_reg[15]_i_32_n_5\,
O(1) => \cb_int_reg[15]_i_32_n_6\,
O(0) => \cb_int_reg[15]_i_32_n_7\,
S(3) => \cb_int[15]_i_39_n_0\,
S(2) => \cb_int[15]_i_40_n_0\,
S(1) => \cb_int[15]_i_41_n_0\,
S(0) => \cb_int[15]_i_42_n_0\
);
\cb_int_reg[15]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_76,
CO(3) => \cb_int_reg[15]_i_34_n_0\,
CO(2) => \cb_int_reg[15]_i_34_n_1\,
CO(1) => \cb_int_reg[15]_i_34_n_2\,
CO(0) => \cb_int_reg[15]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_34_n_4\,
O(2) => \cb_int_reg[15]_i_34_n_5\,
O(1) => \cb_int_reg[15]_i_34_n_6\,
O(0) => \cb_int_reg[15]_i_34_n_7\,
S(3) => \cb_int[15]_i_47_n_0\,
S(2) => \cb_int[15]_i_48_n_0\,
S(1) => \cb_int[15]_i_49_n_0\,
S(0) => \cb_int[15]_i_50_n_0\
);
\cb_int_reg[19]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_32_n_0\,
CO(3) => \cb_int_reg[19]_i_32_n_0\,
CO(2) => \cb_int_reg[19]_i_32_n_1\,
CO(1) => \cb_int_reg[19]_i_32_n_2\,
CO(0) => \cb_int_reg[19]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[19]_i_32_n_4\,
O(2) => \cb_int_reg[19]_i_32_n_5\,
O(1) => \cb_int_reg[19]_i_32_n_6\,
O(0) => \cb_int_reg[19]_i_32_n_7\,
S(3) => \cb_int[19]_i_38_n_0\,
S(2) => \cb_int[19]_i_39_n_0\,
S(1) => \cb_int[19]_i_40_n_0\,
S(0) => \cb_int[19]_i_41_n_0\
);
\cb_int_reg[19]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_34_n_0\,
CO(3) => \cb_int_reg[19]_i_33_n_0\,
CO(2) => \cb_int_reg[19]_i_33_n_1\,
CO(1) => \cb_int_reg[19]_i_33_n_2\,
CO(0) => \cb_int_reg[19]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[19]_i_33_n_4\,
O(2) => \cb_int_reg[19]_i_33_n_5\,
O(1) => \cb_int_reg[19]_i_33_n_6\,
O(0) => \cb_int_reg[19]_i_33_n_7\,
S(3) => \cb_int[19]_i_42_n_0\,
S(2) => \cb_int[19]_i_43_n_0\,
S(1) => \cb_int[19]_i_44_n_0\,
S(0) => \cb_int[19]_i_45_n_0\
);
\cb_int_reg[23]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_32_n_0\,
CO(3) => \cb_int_reg[23]_i_27_n_0\,
CO(2) => \cb_int_reg[23]_i_27_n_1\,
CO(1) => \cb_int_reg[23]_i_27_n_2\,
CO(0) => \cb_int_reg[23]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[23]_i_27_n_4\,
O(2) => \cb_int_reg[23]_i_27_n_5\,
O(1) => \cb_int_reg[23]_i_27_n_6\,
O(0) => \cb_int_reg[23]_i_27_n_7\,
S(3) => \cb_int[23]_i_33_n_0\,
S(2) => \cb_int[23]_i_34_n_0\,
S(1) => \cb_int[23]_i_35_n_0\,
S(0) => \cb_int[23]_i_36_n_0\
);
\cb_int_reg[23]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_33_n_0\,
CO(3) => \cb_int_reg[23]_i_28_n_0\,
CO(2) => \cb_int_reg[23]_i_28_n_1\,
CO(1) => \cb_int_reg[23]_i_28_n_2\,
CO(0) => \cb_int_reg[23]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[23]_i_28_n_4\,
O(2) => \cb_int_reg[23]_i_28_n_5\,
O(1) => \cb_int_reg[23]_i_28_n_6\,
O(0) => \cb_int_reg[23]_i_28_n_7\,
S(3) => \cb_int[23]_i_37_n_0\,
S(2) => \cb_int[23]_i_38_n_0\,
S(1) => \cb_int[23]_i_39_n_0\,
S(0) => \cb_int[23]_i_40_n_0\
);
\cb_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_10_n_6\,
O(0) => \cb_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_28_n_0\,
S(0) => \cb_int[31]_i_29_n_0\
);
\cb_int_reg[31]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_75,
CO(3) => \cb_int_reg[31]_i_17_n_0\,
CO(2) => \cb_int_reg[31]_i_17_n_1\,
CO(1) => \cb_int_reg[31]_i_17_n_2\,
CO(0) => \cb_int_reg[31]_i_17_n_3\,
CYINIT => '0',
DI(3) => U0_n_14,
DI(2) => U0_n_15,
DI(1) => \cb_int[31]_i_45_n_0\,
DI(0) => \cb_int[31]_i_46_n_0\,
O(3) => \cb_int_reg[31]_i_17_n_4\,
O(2) => \cb_int_reg[31]_i_17_n_5\,
O(1) => \cb_int_reg[31]_i_17_n_6\,
O(0) => \cb_int_reg[31]_i_17_n_7\,
S(3) => \cb_int[31]_i_47_n_0\,
S(2) => \cb_int[31]_i_48_n_0\,
S(1) => \cb_int[31]_i_49_n_0\,
S(0) => \cb_int[31]_i_50_n_0\
);
\cb_int_reg[31]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_19_n_0\,
CO(3) => \cb_int_reg[31]_i_23_n_0\,
CO(2) => \cb_int_reg[31]_i_23_n_1\,
CO(1) => \cb_int_reg[31]_i_23_n_2\,
CO(0) => \cb_int_reg[31]_i_23_n_3\,
CYINIT => '0',
DI(3) => \cb_int[31]_i_53_n_0\,
DI(2) => \cb_int[31]_i_54_n_0\,
DI(1) => \cb_int[31]_i_55_n_0\,
DI(0) => \cb_int[31]_i_56_n_0\,
O(3) => \cb_int_reg[31]_i_23_n_4\,
O(2) => \cb_int_reg[31]_i_23_n_5\,
O(1) => \cb_int_reg[31]_i_23_n_6\,
O(0) => \cb_int_reg[31]_i_23_n_7\,
S(3) => \cb_int[31]_i_57_n_0\,
S(2) => \cb_int[31]_i_58_n_0\,
S(1) => \cb_int[31]_i_59_n_0\,
S(0) => \cb_int[31]_i_60_n_0\
);
\cb_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_61_n_0\,
CO(3) => \cb_int_reg[31]_i_27_n_0\,
CO(2) => \cb_int_reg[31]_i_27_n_1\,
CO(1) => \cb_int_reg[31]_i_27_n_2\,
CO(0) => \cb_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[31]_i_27_n_4\,
O(2) => \cb_int_reg[31]_i_27_n_5\,
O(1) => \cb_int_reg[31]_i_27_n_6\,
O(0) => \cb_int_reg[31]_i_27_n_7\,
S(3) => \cb_int[31]_i_62_n_0\,
S(2) => \cb_int[31]_i_63_n_0\,
S(1) => \cb_int[31]_i_64_n_0\,
S(0) => \cb_int[31]_i_65_n_0\
);
\cb_int_reg[31]_i_42\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_28_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_42_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_42_n_6\,
O(0) => \cb_int_reg[31]_i_42_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_83_n_0\,
S(0) => \cb_int[31]_i_84_n_0\
);
\cb_int_reg[31]_i_61\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_31_n_0\,
CO(3) => \cb_int_reg[31]_i_61_n_0\,
CO(2) => \cb_int_reg[31]_i_61_n_1\,
CO(1) => \cb_int_reg[31]_i_61_n_2\,
CO(0) => \cb_int_reg[31]_i_61_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[31]_i_61_n_4\,
O(2) => \cb_int_reg[31]_i_61_n_5\,
O(1) => \cb_int_reg[31]_i_61_n_6\,
O(0) => \cb_int_reg[31]_i_61_n_7\,
S(3) => \cb_int[31]_i_89_n_0\,
S(2) => \cb_int[31]_i_90_n_0\,
S(1) => \cb_int[31]_i_91_n_0\,
S(0) => \cb_int[31]_i_92_n_0\
);
\cb_int_reg[31]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_27_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_66_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_66_n_6\,
O(0) => \cb_int_reg[31]_i_66_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_93_n_0\,
S(0) => \cb_int[31]_i_94_n_0\
);
\cb_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_17_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_8_n_1\,
CO(1) => \cb_int_reg[31]_i_8_n_2\,
CO(0) => \cb_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \cb_int[31]_i_18_n_0\,
O(3) => \cb_int_reg[31]_i_8_n_4\,
O(2) => \cb_int_reg[31]_i_8_n_5\,
O(1) => \cb_int_reg[31]_i_8_n_6\,
O(0) => \cb_int_reg[31]_i_8_n_7\,
S(3) => \cb_int[31]_i_19_n_0\,
S(2) => \cb_int[31]_i_20_n_0\,
S(1) => \cb_int[31]_i_21_n_0\,
S(0) => \cb_int[31]_i_22_n_0\
);
\cb_int_reg[31]_i_85\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_68_n_0\,
CO(3) => \cb_int_reg[31]_i_85_n_0\,
CO(2) => \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\(2),
CO(1) => \cb_int_reg[31]_i_85_n_2\,
CO(0) => \cb_int_reg[31]_i_85_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 1) => rgb888(15 downto 14),
DI(0) => '0',
O(3) => \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\(3),
O(2) => \cb_int_reg[31]_i_85_n_5\,
O(1) => \cb_int_reg[31]_i_85_n_6\,
O(0) => \cb_int_reg[31]_i_85_n_7\,
S(3) => '1',
S(2) => \cb_int[31]_i_99_n_0\,
S(1) => \cb_int[31]_i_100_n_0\,
S(0) => \cb_int[31]_i_101_n_0\
);
\cb_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_23_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => U0_n_4,
O(3 downto 2) => \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_9_n_6\,
O(0) => \cb_int_reg[31]_i_9_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_25_n_0\,
S(0) => \cb_int[31]_i_26_n_0\
);
\cb_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_73,
CO(3) => \cb_int_reg[3]_i_19_n_0\,
CO(2) => \cb_int_reg[3]_i_19_n_1\,
CO(1) => \cb_int_reg[3]_i_19_n_2\,
CO(0) => \cb_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \cb_int[3]_i_35_n_0\,
DI(2) => \cb_int[3]_i_36_n_0\,
DI(1) => \cb_int[3]_i_37_n_0\,
DI(0) => \cb_int[3]_i_38_n_0\,
O(3) => \cb_int_reg[3]_i_19_n_4\,
O(2) => \cb_int_reg[3]_i_19_n_5\,
O(1) => \cb_int_reg[3]_i_19_n_6\,
O(0) => \cb_int_reg[3]_i_19_n_7\,
S(3) => \cb_int[3]_i_39_n_0\,
S(2) => \cb_int[3]_i_40_n_0\,
S(1) => \cb_int[3]_i_41_n_0\,
S(0) => \cb_int[3]_i_42_n_0\
);
\cb_int_reg[3]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_58_n_0\,
CO(3) => \cb_int_reg[3]_i_32_n_0\,
CO(2) => \cb_int_reg[3]_i_32_n_1\,
CO(1) => \cb_int_reg[3]_i_32_n_2\,
CO(0) => \cb_int_reg[3]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[3]_i_32_n_4\,
O(2 downto 0) => \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0),
S(3) => \cb_int[3]_i_59_n_0\,
S(2) => \cb_int[3]_i_60_n_0\,
S(1) => \cb_int[3]_i_61_n_0\,
S(0) => \cb_int[3]_i_62_n_0\
);
\cb_int_reg[3]_i_43\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_74,
CO(3) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[3]_i_43_n_1\,
CO(1) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[3]_i_43_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(7),
DI(0) => '0',
O(3 downto 2) => \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[3]_i_43_n_6\,
O(0) => \cb_int_reg[3]_i_43_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[3]_i_73_n_0\,
S(0) => \cb_int[3]_i_74_n_0\
);
\cb_int_reg[3]_i_58\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_58_n_0\,
CO(2) => \cb_int_reg[3]_i_58_n_1\,
CO(1) => \cb_int_reg[3]_i_58_n_2\,
CO(0) => \cb_int_reg[3]_i_58_n_3\,
CYINIT => \cb_int[3]_i_84_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_85_n_0\,
S(2) => \cb_int[3]_i_86_n_0\,
S(1) => \cb_int[3]_i_87_n_0\,
S(0) => \cb_int[3]_i_88_n_0\
);
\cb_int_reg[3]_i_68\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_72,
CO(3) => \cb_int_reg[3]_i_68_n_0\,
CO(2) => \cb_int_reg[3]_i_68_n_1\,
CO(1) => \cb_int_reg[3]_i_68_n_2\,
CO(0) => \cb_int_reg[3]_i_68_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(12 downto 9),
O(3) => \cb_int_reg[3]_i_68_n_4\,
O(2) => \cb_int_reg[3]_i_68_n_5\,
O(1) => \cb_int_reg[3]_i_68_n_6\,
O(0) => \cb_int_reg[3]_i_68_n_7\,
S(3) => \cb_int[3]_i_95_n_0\,
S(2) => \cb_int[3]_i_96_n_0\,
S(1) => \cb_int[3]_i_97_n_0\,
S(0) => \cb_int[3]_i_98_n_0\
);
\cb_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_26_n_0\,
CO(3) => \cb_int_reg[7]_i_23_n_0\,
CO(2) => \cb_int_reg[7]_i_23_n_1\,
CO(1) => \cb_int_reg[7]_i_23_n_2\,
CO(0) => \cb_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_23_n_4\,
O(2) => \cb_int_reg[7]_i_23_n_5\,
O(1) => \cb_int_reg[7]_i_23_n_6\,
O(0) => \cb_int_reg[7]_i_23_n_7\,
S(3) => \cb_int[7]_i_30_n_0\,
S(2) => \cb_int[7]_i_31_n_0\,
S(1) => \cb_int[7]_i_32_n_0\,
S(0) => \cb_int[7]_i_33_n_0\
);
\cb_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_27_n_0\,
CO(3) => \cb_int_reg[7]_i_24_n_0\,
CO(2) => \cb_int_reg[7]_i_24_n_1\,
CO(1) => \cb_int_reg[7]_i_24_n_2\,
CO(0) => \cb_int_reg[7]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_24_n_4\,
O(2) => \cb_int_reg[7]_i_24_n_5\,
O(1) => \cb_int_reg[7]_i_24_n_6\,
O(0) => \cb_int_reg[7]_i_24_n_7\,
S(3) => \cb_int[7]_i_34_n_0\,
S(2) => \cb_int[7]_i_35_n_0\,
S(1) => \cb_int[7]_i_36_n_0\,
S(0) => \cb_int[7]_i_37_n_0\
);
\cb_int_reg[7]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_26_n_0\,
CO(2) => \cb_int_reg[7]_i_26_n_1\,
CO(1) => \cb_int_reg[7]_i_26_n_2\,
CO(0) => \cb_int_reg[7]_i_26_n_3\,
CYINIT => \cb_int[7]_i_43_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_26_n_4\,
O(2) => \cb_int_reg[7]_i_26_n_5\,
O(1) => \cb_int_reg[7]_i_26_n_6\,
O(0) => \cb_int_reg[7]_i_26_n_7\,
S(3) => \cb_int[7]_i_44_n_0\,
S(2) => \cb_int[7]_i_45_n_0\,
S(1) => \cb_int[7]_i_46_n_0\,
S(0) => \cb_int[7]_i_47_n_0\
);
\cb_int_reg[7]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_32_n_0\,
CO(3) => \cb_int_reg[7]_i_27_n_0\,
CO(2) => \cb_int_reg[7]_i_27_n_1\,
CO(1) => \cb_int_reg[7]_i_27_n_2\,
CO(0) => \cb_int_reg[7]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_27_n_4\,
O(2) => \cb_int_reg[7]_i_27_n_5\,
O(1) => \cb_int_reg[7]_i_27_n_6\,
O(0) => \cb_int_reg[7]_i_27_n_7\,
S(3) => \cb_int[7]_i_48_n_0\,
S(2) => \cb_int[7]_i_49_n_0\,
S(1) => \cb_int[7]_i_50_n_0\,
S(0) => \cb_int[7]_i_51_n_0\
);
\cr_int[11]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_35,
O => \cr_int[11]_i_61_n_0\
);
\cr_int[11]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_36,
I1 => U0_n_26,
I2 => U0_n_18,
O => \cr_int[11]_i_62_n_0\
);
\cr_int[11]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_37,
I1 => U0_n_26,
I2 => U0_n_19,
O => \cr_int[11]_i_63_n_0\
);
\cr_int[11]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_30,
I1 => U0_n_26,
I2 => U0_n_20,
O => \cr_int[11]_i_64_n_0\
);
\cr_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_39,
O => \cr_int[15]_i_44_n_0\
);
\cr_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_40,
O => \cr_int[15]_i_45_n_0\
);
\cr_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_41,
O => \cr_int[15]_i_46_n_0\
);
\cr_int[15]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_34,
O => \cr_int[15]_i_47_n_0\
);
\cr_int[15]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_52_n_0\
);
\cr_int[15]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_53_n_0\
);
\cr_int[15]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_54_n_0\
);
\cr_int[15]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_55_n_0\
);
\cr_int[19]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_42_n_0\
);
\cr_int[19]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_43_n_0\
);
\cr_int[19]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_44_n_0\
);
\cr_int[19]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_45_n_0\
);
\cr_int[23]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_32_n_0\
);
\cr_int[23]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_33_n_0\
);
\cr_int[23]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_34_n_0\
);
\cr_int[23]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_35_n_0\
);
\cr_int[31]_i_104\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_43,
O => \cr_int[31]_i_104_n_0\
);
\cr_int[31]_i_105\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_44,
O => \cr_int[31]_i_105_n_0\
);
\cr_int[31]_i_106\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_45,
O => \cr_int[31]_i_106_n_0\
);
\cr_int[31]_i_107\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_38,
O => \cr_int[31]_i_107_n_0\
);
\cr_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_50,
O => \cr_int[31]_i_28_n_0\
);
\cr_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_46,
O => \cr_int[31]_i_29_n_0\
);
\cr_int[31]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_47,
O => \cr_int[31]_i_65_n_0\
);
\cr_int[31]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_48,
O => \cr_int[31]_i_66_n_0\
);
\cr_int[31]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_49,
O => \cr_int[31]_i_67_n_0\
);
\cr_int[31]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_42,
O => \cr_int[31]_i_68_n_0\
);
\cr_int[31]_i_98\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[31]_i_98_n_0\
);
\cr_int[31]_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[31]_i_99_n_0\
);
\cr_int[7]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_28,
I1 => U0_n_26,
I2 => U0_n_25,
O => \cr_int[7]_i_29_n_0\
);
\cr_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_31,
I1 => U0_n_26,
I2 => U0_n_21,
O => \cr_int[7]_i_30_n_0\
);
\cr_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_32,
I1 => U0_n_26,
I2 => U0_n_22,
O => \cr_int[7]_i_31_n_0\
);
\cr_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_33,
I1 => U0_n_26,
I2 => U0_n_23,
O => \cr_int[7]_i_32_n_0\
);
\cr_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_27,
I1 => U0_n_26,
I2 => U0_n_24,
O => \cr_int[7]_i_33_n_0\
);
\cr_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_24_n_0\,
CO(3) => \cr_int_reg[11]_i_28_n_0\,
CO(2) => \cr_int_reg[11]_i_28_n_1\,
CO(1) => \cr_int_reg[11]_i_28_n_2\,
CO(0) => \cr_int_reg[11]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_28_n_4\,
O(2) => \cr_int_reg[11]_i_28_n_5\,
O(1) => \cr_int_reg[11]_i_28_n_6\,
O(0) => \cr_int_reg[11]_i_28_n_7\,
S(3) => \cr_int[11]_i_61_n_0\,
S(2) => \cr_int[11]_i_62_n_0\,
S(1) => \cr_int[11]_i_63_n_0\,
S(0) => \cr_int[11]_i_64_n_0\
);
\cr_int_reg[15]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_28_n_0\,
CO(3) => \cr_int_reg[15]_i_37_n_0\,
CO(2) => \cr_int_reg[15]_i_37_n_1\,
CO(1) => \cr_int_reg[15]_i_37_n_2\,
CO(0) => \cr_int_reg[15]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_37_n_4\,
O(2) => \cr_int_reg[15]_i_37_n_5\,
O(1) => \cr_int_reg[15]_i_37_n_6\,
O(0) => \cr_int_reg[15]_i_37_n_7\,
S(3) => \cr_int[15]_i_44_n_0\,
S(2) => \cr_int[15]_i_45_n_0\,
S(1) => \cr_int[15]_i_46_n_0\,
S(0) => \cr_int[15]_i_47_n_0\
);
\cr_int_reg[15]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_77,
CO(3) => \cr_int_reg[15]_i_39_n_0\,
CO(2) => \cr_int_reg[15]_i_39_n_1\,
CO(1) => \cr_int_reg[15]_i_39_n_2\,
CO(0) => \cr_int_reg[15]_i_39_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_39_n_4\,
O(2) => \cr_int_reg[15]_i_39_n_5\,
O(1) => \cr_int_reg[15]_i_39_n_6\,
O(0) => \cr_int_reg[15]_i_39_n_7\,
S(3) => \cr_int[15]_i_52_n_0\,
S(2) => \cr_int[15]_i_53_n_0\,
S(1) => \cr_int[15]_i_54_n_0\,
S(0) => \cr_int[15]_i_55_n_0\
);
\cr_int_reg[19]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_39_n_0\,
CO(3) => \cr_int_reg[19]_i_37_n_0\,
CO(2) => \cr_int_reg[19]_i_37_n_1\,
CO(1) => \cr_int_reg[19]_i_37_n_2\,
CO(0) => \cr_int_reg[19]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[19]_i_37_n_4\,
O(2) => \cr_int_reg[19]_i_37_n_5\,
O(1) => \cr_int_reg[19]_i_37_n_6\,
O(0) => \cr_int_reg[19]_i_37_n_7\,
S(3) => \cr_int[19]_i_42_n_0\,
S(2) => \cr_int[19]_i_43_n_0\,
S(1) => \cr_int[19]_i_44_n_0\,
S(0) => \cr_int[19]_i_45_n_0\
);
\cr_int_reg[23]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_37_n_0\,
CO(3) => \cr_int_reg[23]_i_31_n_0\,
CO(2) => \cr_int_reg[23]_i_31_n_1\,
CO(1) => \cr_int_reg[23]_i_31_n_2\,
CO(0) => \cr_int_reg[23]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[23]_i_31_n_4\,
O(2) => \cr_int_reg[23]_i_31_n_5\,
O(1) => \cr_int_reg[23]_i_31_n_6\,
O(0) => \cr_int_reg[23]_i_31_n_7\,
S(3) => \cr_int[23]_i_32_n_0\,
S(2) => \cr_int[23]_i_33_n_0\,
S(1) => \cr_int[23]_i_34_n_0\,
S(0) => \cr_int[23]_i_35_n_0\
);
\cr_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_10_n_6\,
O(0) => \cr_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_28_n_0\,
S(0) => \cr_int[31]_i_29_n_0\
);
\cr_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_64_n_0\,
CO(3) => \cr_int_reg[31]_i_27_n_0\,
CO(2) => \cr_int_reg[31]_i_27_n_1\,
CO(1) => \cr_int_reg[31]_i_27_n_2\,
CO(0) => \cr_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_27_n_4\,
O(2) => \cr_int_reg[31]_i_27_n_5\,
O(1) => \cr_int_reg[31]_i_27_n_6\,
O(0) => \cr_int_reg[31]_i_27_n_7\,
S(3) => \cr_int[31]_i_65_n_0\,
S(2) => \cr_int[31]_i_66_n_0\,
S(1) => \cr_int[31]_i_67_n_0\,
S(0) => \cr_int[31]_i_68_n_0\
);
\cr_int_reg[31]_i_54\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_31_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[31]_i_54_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_54_n_6\,
O(0) => \cr_int_reg[31]_i_54_n_7\,
S(3 downto 2) => B"00",
S(1) => \cr_int[31]_i_98_n_0\,
S(0) => \cr_int[31]_i_99_n_0\
);
\cr_int_reg[31]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_37_n_0\,
CO(3) => \cr_int_reg[31]_i_64_n_0\,
CO(2) => \cr_int_reg[31]_i_64_n_1\,
CO(1) => \cr_int_reg[31]_i_64_n_2\,
CO(0) => \cr_int_reg[31]_i_64_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_64_n_4\,
O(2) => \cr_int_reg[31]_i_64_n_5\,
O(1) => \cr_int_reg[31]_i_64_n_6\,
O(0) => \cr_int_reg[31]_i_64_n_7\,
S(3) => \cr_int[31]_i_104_n_0\,
S(2) => \cr_int[31]_i_105_n_0\,
S(1) => \cr_int[31]_i_106_n_0\,
S(0) => \cr_int[31]_i_107_n_0\
);
\cr_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[7]_i_24_n_0\,
CO(2) => \cr_int_reg[7]_i_24_n_1\,
CO(1) => \cr_int_reg[7]_i_24_n_2\,
CO(0) => \cr_int_reg[7]_i_24_n_3\,
CYINIT => \cr_int[7]_i_29_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[7]_i_24_n_4\,
O(2) => \cr_int_reg[7]_i_24_n_5\,
O(1) => \cr_int_reg[7]_i_24_n_6\,
O(0) => \cr_int_reg[7]_i_24_n_7\,
S(3) => \cr_int[7]_i_30_n_0\,
S(2) => \cr_int[7]_i_31_n_0\,
S(1) => \cr_int[7]_i_32_n_0\,
S(0) => \cr_int[7]_i_33_n_0\
);
\y_int[11]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[11]_i_54_n_0\
);
\y_int[11]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_6\,
O => \y_int[11]_i_55_n_0\
);
\y_int[11]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_7\,
O => \y_int[11]_i_56_n_0\
);
\y_int[11]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_4\,
O => \y_int[11]_i_57_n_0\
);
\y_int[15]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_36_n_0\
);
\y_int[15]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_37_n_0\
);
\y_int[15]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_38_n_0\
);
\y_int[15]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_39_n_0\
);
\y_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_68,
O => \y_int[15]_i_44_n_0\
);
\y_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_69,
O => \y_int[15]_i_45_n_0\
);
\y_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_70,
O => \y_int[15]_i_46_n_0\
);
\y_int[15]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_71,
O => \y_int[15]_i_47_n_0\
);
\y_int[19]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_36_n_0\
);
\y_int[19]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_37_n_0\
);
\y_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_38_n_0\
);
\y_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_39_n_0\
);
\y_int[19]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_5\,
O => \y_int[19]_i_40_n_0\
);
\y_int[19]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_6\,
O => \y_int[19]_i_41_n_0\
);
\y_int[19]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_7\,
O => \y_int[19]_i_42_n_0\
);
\y_int[19]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[15]_i_24_n_4\,
O => \y_int[19]_i_43_n_0\
);
\y_int[19]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_64,
O => \y_int[19]_i_44_n_0\
);
\y_int[19]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_65,
O => \y_int[19]_i_45_n_0\
);
\y_int[19]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_66,
O => \y_int[19]_i_46_n_0\
);
\y_int[19]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_67,
O => \y_int[19]_i_47_n_0\
);
\y_int[23]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_50_n_0\
);
\y_int[23]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_58_n_0\
);
\y_int[23]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_59_n_0\
);
\y_int[23]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_60_n_0\
);
\y_int[23]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_61_n_0\
);
\y_int[31]_i_100\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(4),
I3 => rgb888(2),
O => \y_int[31]_i_100_n_0\
);
\y_int[31]_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \y_int[31]_i_102_n_0\
);
\y_int[31]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
O => \y_int[31]_i_103_n_0\
);
\y_int[31]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_56_n_0\,
O => \y_int[31]_i_22_n_0\
);
\y_int[31]_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_57_n_0\,
I2 => rgb888(14),
O => \y_int[31]_i_23_n_0\
);
\y_int[31]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_56_n_0\,
O => \y_int[31]_i_24_n_0\
);
\y_int[31]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \y_int[31]_i_25_n_0\
);
\y_int[31]_i_26\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
I2 => \y_int[31]_i_57_n_0\,
O => \y_int[31]_i_26_n_0\
);
\y_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_32_n_7\,
O => \y_int[31]_i_28_n_0\
);
\y_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_4\,
O => \y_int[31]_i_29_n_0\
);
\y_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_58,
O => \y_int[31]_i_38_n_0\
);
\y_int[31]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_59,
O => \y_int[31]_i_39_n_0\
);
\y_int[31]_i_48\: unisim.vcomponents.LUT4
generic map(
INIT => X"1002"
)
port map (
I0 => rgb888(14),
I1 => rgb888(15),
I2 => \y_int[31]_i_80_n_0\,
I3 => rgb888(13),
O => \y_int[31]_i_48_n_0\
);
\y_int[31]_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"81560042"
)
port map (
I0 => rgb888(13),
I1 => rgb888(12),
I2 => \y_int[31]_i_81_n_0\,
I3 => rgb888(15),
I4 => \y_int_reg[31]_i_82_n_1\,
O => \y_int[31]_i_49_n_0\
);
\y_int[31]_i_50\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A88A80808008"
)
port map (
I0 => \y_int[31]_i_83_n_0\,
I1 => rgb888(14),
I2 => rgb888(11),
I3 => rgb888(9),
I4 => rgb888(10),
I5 => \y_int_reg[31]_i_82_n_6\,
O => \y_int[31]_i_50_n_0\
);
\y_int[31]_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"9696966996000069"
)
port map (
I0 => rgb888(14),
I1 => rgb888(11),
I2 => \y_int_reg[31]_i_82_n_6\,
I3 => rgb888(9),
I4 => rgb888(10),
I5 => rgb888(13),
O => \y_int[31]_i_51_n_0\
);
\y_int[31]_i_52\: unisim.vcomponents.LUT4
generic map(
INIT => X"6559"
)
port map (
I0 => \y_int[31]_i_48_n_0\,
I1 => rgb888(15),
I2 => \y_int[31]_i_57_n_0\,
I3 => rgb888(14),
O => \y_int[31]_i_52_n_0\
);
\y_int[31]_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"6CCCCCC9CCCCC993"
)
port map (
I0 => \y_int_reg[31]_i_82_n_1\,
I1 => rgb888(14),
I2 => rgb888(12),
I3 => \y_int[31]_i_81_n_0\,
I4 => rgb888(13),
I5 => rgb888(15),
O => \y_int[31]_i_53_n_0\
);
\y_int[31]_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"366C6CC96CC9C993"
)
port map (
I0 => \y_int[31]_i_84_n_0\,
I1 => rgb888(13),
I2 => \y_int[31]_i_81_n_0\,
I3 => rgb888(12),
I4 => rgb888(15),
I5 => \y_int_reg[31]_i_82_n_1\,
O => \y_int[31]_i_54_n_0\
);
\y_int[31]_i_55\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => \y_int[31]_i_51_n_0\,
I1 => \y_int[31]_i_83_n_0\,
I2 => \y_int_reg[31]_i_82_n_6\,
I3 => \y_int[31]_i_85_n_0\,
I4 => rgb888(14),
O => \y_int[31]_i_55_n_0\
);
\y_int[31]_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
I2 => rgb888(9),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \y_int[31]_i_56_n_0\
);
\y_int[31]_i_57\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(13),
O => \y_int[31]_i_57_n_0\
);
\y_int[31]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_5\,
O => \y_int[31]_i_58_n_0\
);
\y_int[31]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_6\,
O => \y_int[31]_i_59_n_0\
);
\y_int[31]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_7\,
O => \y_int[31]_i_60_n_0\
);
\y_int[31]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_4\,
O => \y_int[31]_i_61_n_0\
);
\y_int[31]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(5),
I1 => rgb888(7),
O => \y_int[31]_i_72_n_0\
);
\y_int[31]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(7),
O => \y_int[31]_i_73_n_0\
);
\y_int[31]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
I2 => rgb888(6),
O => \y_int[31]_i_74_n_0\
);
\y_int[31]_i_76\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_60,
O => \y_int[31]_i_76_n_0\
);
\y_int[31]_i_77\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_61,
O => \y_int[31]_i_77_n_0\
);
\y_int[31]_i_78\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_62,
O => \y_int[31]_i_78_n_0\
);
\y_int[31]_i_79\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_63,
O => \y_int[31]_i_79_n_0\
);
\y_int[31]_i_80\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => rgb888(10),
I3 => rgb888(12),
O => \y_int[31]_i_80_n_0\
);
\y_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => rgb888(10),
I1 => rgb888(9),
I2 => rgb888(11),
O => \y_int[31]_i_81_n_0\
);
\y_int[31]_i_83\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666999999996"
)
port map (
I0 => \y_int_reg[31]_i_82_n_1\,
I1 => rgb888(15),
I2 => rgb888(11),
I3 => rgb888(9),
I4 => rgb888(10),
I5 => rgb888(12),
O => \y_int[31]_i_83_n_0\
);
\y_int[31]_i_84\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEABA802"
)
port map (
I0 => \y_int_reg[31]_i_82_n_6\,
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(14),
O => \y_int[31]_i_84_n_0\
);
\y_int[31]_i_85\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => rgb888(10),
I1 => rgb888(9),
I2 => rgb888(11),
O => \y_int[31]_i_85_n_0\
);
\y_int[31]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(4),
I1 => rgb888(6),
O => \y_int[31]_i_93_n_0\
);
\y_int[31]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(3),
I1 => rgb888(5),
O => \y_int[31]_i_94_n_0\
);
\y_int[31]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(2),
I1 => rgb888(4),
O => \y_int[31]_i_95_n_0\
);
\y_int[31]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(1),
I1 => rgb888(3),
O => \y_int[31]_i_96_n_0\
);
\y_int[31]_i_97\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
I2 => rgb888(7),
I3 => rgb888(5),
O => \y_int[31]_i_97_n_0\
);
\y_int[31]_i_98\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(6),
I3 => rgb888(4),
O => \y_int[31]_i_98_n_0\
);
\y_int[31]_i_99\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(5),
I3 => rgb888(3),
O => \y_int[31]_i_99_n_0\
);
\y_int[3]_i_37\: unisim.vcomponents.LUT4
generic map(
INIT => X"8228"
)
port map (
I0 => \y_int_reg[31]_i_82_n_7\,
I1 => rgb888(9),
I2 => rgb888(10),
I3 => rgb888(13),
O => \y_int[3]_i_37_n_0\
);
\y_int[3]_i_38\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(9),
I1 => rgb888(10),
I2 => rgb888(13),
I3 => \y_int_reg[31]_i_82_n_7\,
O => \y_int[3]_i_38_n_0\
);
\y_int[3]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \y_int_reg[3]_i_40_n_4\,
I1 => rgb888(9),
I2 => rgb888(12),
O => \y_int[3]_i_39_n_0\
);
\y_int[3]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969699"
)
port map (
I0 => \y_int[3]_i_37_n_0\,
I1 => \y_int[3]_i_79_n_0\,
I2 => rgb888(13),
I3 => rgb888(10),
I4 => rgb888(9),
O => \y_int[3]_i_41_n_0\
);
\y_int[3]_i_42\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969696996"
)
port map (
I0 => \y_int_reg[31]_i_82_n_7\,
I1 => rgb888(13),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => \y_int_reg[3]_i_40_n_4\,
I5 => rgb888(9),
O => \y_int[3]_i_42_n_0\
);
\y_int[3]_i_43\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => rgb888(12),
I1 => rgb888(9),
I2 => \y_int_reg[3]_i_40_n_4\,
I3 => rgb888(11),
I4 => rgb888(8),
O => \y_int[3]_i_43_n_0\
);
\y_int[3]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(11),
I2 => \y_int_reg[3]_i_40_n_5\,
O => \y_int[3]_i_44_n_0\
);
\y_int[3]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_5\,
O => \y_int[3]_i_46_n_0\
);
\y_int[3]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_6\,
O => \y_int[3]_i_47_n_0\
);
\y_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_7\,
O => \y_int[3]_i_48_n_0\
);
\y_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_51,
O => \y_int[3]_i_49_n_0\
);
\y_int[3]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \y_int[3]_i_75_n_0\
);
\y_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(14),
O => \y_int[3]_i_76_n_0\
);
\y_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(13),
O => \y_int[3]_i_77_n_0\
);
\y_int[3]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(12),
O => \y_int[3]_i_78_n_0\
);
\y_int[3]_i_79\: unisim.vcomponents.LUT5
generic map(
INIT => X"A95656A9"
)
port map (
I0 => \y_int_reg[31]_i_82_n_6\,
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(14),
O => \y_int[3]_i_79_n_0\
);
\y_int[3]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_52,
O => \y_int[3]_i_80_n_0\
);
\y_int[3]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_53,
O => \y_int[3]_i_81_n_0\
);
\y_int[3]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_54,
O => \y_int[3]_i_82_n_0\
);
\y_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_70_n_6\,
O => \y_int[3]_i_83_n_0\
);
\y_int[3]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(11),
O => \y_int[3]_i_93_n_0\
);
\y_int[3]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
O => \y_int[3]_i_94_n_0\
);
\y_int[3]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \y_int[3]_i_95_n_0\
);
\y_int[3]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \y_int[3]_i_96_n_0\
);
\y_int[7]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_5\,
O => \y_int[7]_i_25_n_0\
);
\y_int[7]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_6\,
O => \y_int[7]_i_26_n_0\
);
\y_int[7]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_7\,
O => \y_int[7]_i_27_n_0\
);
\y_int[7]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_4\,
O => \y_int[7]_i_28_n_0\
);
\y_int_reg[11]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_23_n_0\,
CO(3) => \y_int_reg[11]_i_27_n_0\,
CO(2) => \y_int_reg[11]_i_27_n_1\,
CO(1) => \y_int_reg[11]_i_27_n_2\,
CO(0) => \y_int_reg[11]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_27_n_4\,
O(2) => \y_int_reg[11]_i_27_n_5\,
O(1) => \y_int_reg[11]_i_27_n_6\,
O(0) => \y_int_reg[11]_i_27_n_7\,
S(3) => \y_int[11]_i_54_n_0\,
S(2) => \y_int[11]_i_55_n_0\,
S(1) => \y_int[11]_i_56_n_0\,
S(0) => \y_int[11]_i_57_n_0\
);
\y_int_reg[15]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_27_n_0\,
CO(3) => \y_int_reg[15]_i_24_n_0\,
CO(2) => \y_int_reg[15]_i_24_n_1\,
CO(1) => \y_int_reg[15]_i_24_n_2\,
CO(0) => \y_int_reg[15]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[15]_i_24_n_4\,
O(2) => \y_int_reg[15]_i_24_n_5\,
O(1) => \y_int_reg[15]_i_24_n_6\,
O(0) => \y_int_reg[15]_i_24_n_7\,
S(3) => \y_int[15]_i_36_n_0\,
S(2) => \y_int[15]_i_37_n_0\,
S(1) => \y_int[15]_i_38_n_0\,
S(0) => \y_int[15]_i_39_n_0\
);
\y_int_reg[15]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_81,
CO(3) => \y_int_reg[15]_i_34_n_0\,
CO(2) => \y_int_reg[15]_i_34_n_1\,
CO(1) => \y_int_reg[15]_i_34_n_2\,
CO(0) => \y_int_reg[15]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(12 downto 9),
S(3) => \y_int[15]_i_44_n_0\,
S(2) => \y_int[15]_i_45_n_0\,
S(1) => \y_int[15]_i_46_n_0\,
S(0) => \y_int[15]_i_47_n_0\
);
\y_int_reg[19]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_24_n_0\,
CO(3) => \y_int_reg[19]_i_24_n_0\,
CO(2) => \y_int_reg[19]_i_24_n_1\,
CO(1) => \y_int_reg[19]_i_24_n_2\,
CO(0) => \y_int_reg[19]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[19]_i_24_n_4\,
O(2) => \y_int_reg[19]_i_24_n_5\,
O(1) => \y_int_reg[19]_i_24_n_6\,
O(0) => \y_int_reg[19]_i_24_n_7\,
S(3) => \y_int[19]_i_36_n_0\,
S(2) => \y_int[19]_i_37_n_0\,
S(1) => \y_int[19]_i_38_n_0\,
S(0) => \y_int[19]_i_39_n_0\
);
\y_int_reg[19]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_79,
CO(3) => \y_int_reg[19]_i_33_n_0\,
CO(2) => \y_int_reg[19]_i_33_n_1\,
CO(1) => \y_int_reg[19]_i_33_n_2\,
CO(0) => \y_int_reg[19]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[19]_i_33_n_4\,
O(2) => \y_int_reg[19]_i_33_n_5\,
O(1) => \y_int_reg[19]_i_33_n_6\,
O(0) => \y_int_reg[19]_i_33_n_7\,
S(3) => \y_int[19]_i_40_n_0\,
S(2) => \y_int[19]_i_41_n_0\,
S(1) => \y_int[19]_i_42_n_0\,
S(0) => \y_int[19]_i_43_n_0\
);
\y_int_reg[19]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_34_n_0\,
CO(3) => \y_int_reg[19]_i_34_n_0\,
CO(2) => \y_int_reg[19]_i_34_n_1\,
CO(1) => \y_int_reg[19]_i_34_n_2\,
CO(0) => \y_int_reg[19]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(16 downto 13),
S(3) => \y_int[19]_i_44_n_0\,
S(2) => \y_int[19]_i_45_n_0\,
S(1) => \y_int[19]_i_46_n_0\,
S(0) => \y_int[19]_i_47_n_0\
);
\y_int_reg[23]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_35_n_0\,
CO(3 downto 0) => \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[23]_i_32_n_7\,
S(3 downto 1) => B"000",
S(0) => \y_int[23]_i_50_n_0\
);
\y_int_reg[23]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_24_n_0\,
CO(3) => \y_int_reg[23]_i_35_n_0\,
CO(2) => \y_int_reg[23]_i_35_n_1\,
CO(1) => \y_int_reg[23]_i_35_n_2\,
CO(0) => \y_int_reg[23]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[23]_i_35_n_4\,
O(2) => \y_int_reg[23]_i_35_n_5\,
O(1) => \y_int_reg[23]_i_35_n_6\,
O(0) => \y_int_reg[23]_i_35_n_7\,
S(3) => \y_int[23]_i_58_n_0\,
S(2) => \y_int[23]_i_59_n_0\,
S(1) => \y_int[23]_i_60_n_0\,
S(0) => \y_int[23]_i_61_n_0\
);
\y_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \y_int_reg[31]_i_10_n_6\,
O(0) => \y_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_28_n_0\,
S(0) => \y_int[31]_i_29_n_0\
);
\y_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_37_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg2(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_38_n_0\,
S(0) => \y_int[31]_i_39_n_0\
);
\y_int_reg[31]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_19_n_0\,
CO(3) => \y_int_reg[31]_i_21_n_0\,
CO(2) => \y_int_reg[31]_i_21_n_1\,
CO(1) => \y_int_reg[31]_i_21_n_2\,
CO(0) => \y_int_reg[31]_i_21_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_48_n_0\,
DI(2) => \y_int[31]_i_49_n_0\,
DI(1) => \y_int[31]_i_50_n_0\,
DI(0) => \y_int[31]_i_51_n_0\,
O(3) => \y_int_reg[31]_i_21_n_4\,
O(2) => \y_int_reg[31]_i_21_n_5\,
O(1) => \y_int_reg[31]_i_21_n_6\,
O(0) => \y_int_reg[31]_i_21_n_7\,
S(3) => \y_int[31]_i_52_n_0\,
S(2) => \y_int[31]_i_53_n_0\,
S(1) => \y_int[31]_i_54_n_0\,
S(0) => \y_int[31]_i_55_n_0\
);
\y_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_33_n_0\,
CO(3) => \y_int_reg[31]_i_27_n_0\,
CO(2) => \y_int_reg[31]_i_27_n_1\,
CO(1) => \y_int_reg[31]_i_27_n_2\,
CO(0) => \y_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[31]_i_27_n_4\,
O(2) => \y_int_reg[31]_i_27_n_5\,
O(1) => \y_int_reg[31]_i_27_n_6\,
O(0) => \y_int_reg[31]_i_27_n_7\,
S(3) => \y_int[31]_i_58_n_0\,
S(2) => \y_int[31]_i_59_n_0\,
S(1) => \y_int[31]_i_60_n_0\,
S(0) => \y_int[31]_i_61_n_0\
);
\y_int_reg[31]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_71_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_31_n_2\,
CO(0) => \y_int_reg[31]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(6),
DI(0) => \y_int[31]_i_72_n_0\,
O(3) => \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_31_n_5\,
O(1) => \y_int_reg[31]_i_31_n_6\,
O(0) => \y_int_reg[31]_i_31_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_73_n_0\,
S(0) => \y_int[31]_i_74_n_0\
);
\y_int_reg[31]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_34_n_0\,
CO(3) => \y_int_reg[31]_i_37_n_0\,
CO(2) => \y_int_reg[31]_i_37_n_1\,
CO(1) => \y_int_reg[31]_i_37_n_2\,
CO(0) => \y_int_reg[31]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(20 downto 17),
S(3) => \y_int[31]_i_76_n_0\,
S(2) => \y_int[31]_i_77_n_0\,
S(1) => \y_int[31]_i_78_n_0\,
S(0) => \y_int[31]_i_79_n_0\
);
\y_int_reg[31]_i_71\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_80,
CO(3) => \y_int_reg[31]_i_71_n_0\,
CO(2) => \y_int_reg[31]_i_71_n_1\,
CO(1) => \y_int_reg[31]_i_71_n_2\,
CO(0) => \y_int_reg[31]_i_71_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_93_n_0\,
DI(2) => \y_int[31]_i_94_n_0\,
DI(1) => \y_int[31]_i_95_n_0\,
DI(0) => \y_int[31]_i_96_n_0\,
O(3) => \y_int_reg[31]_i_71_n_4\,
O(2) => \y_int_reg[31]_i_71_n_5\,
O(1) => \y_int_reg[31]_i_71_n_6\,
O(0) => \y_int_reg[31]_i_71_n_7\,
S(3) => \y_int[31]_i_97_n_0\,
S(2) => \y_int[31]_i_98_n_0\,
S(1) => \y_int[31]_i_99_n_0\,
S(0) => \y_int[31]_i_100_n_0\
);
\y_int_reg[31]_i_82\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_40_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_82_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_82_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => rgb888(15 downto 14),
O(3 downto 2) => \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\(3 downto 2),
O(1) => \y_int_reg[31]_i_82_n_6\,
O(0) => \y_int_reg[31]_i_82_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_102_n_0\,
S(0) => \y_int[31]_i_103_n_0\
);
\y_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_21_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_9_n_2\,
CO(0) => \y_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \y_int[31]_i_22_n_0\,
DI(0) => \y_int[31]_i_23_n_0\,
O(3) => \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_9_n_5\,
O(1) => \y_int_reg[31]_i_9_n_6\,
O(0) => \y_int_reg[31]_i_9_n_7\,
S(3) => '0',
S(2) => \y_int[31]_i_24_n_0\,
S(1) => \y_int[31]_i_25_n_0\,
S(0) => \y_int[31]_i_26_n_0\
);
\y_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_78,
CO(3) => \y_int_reg[3]_i_19_n_0\,
CO(2) => \y_int_reg[3]_i_19_n_1\,
CO(1) => \y_int_reg[3]_i_19_n_2\,
CO(0) => \y_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_37_n_0\,
DI(2) => \y_int[3]_i_38_n_0\,
DI(1) => \y_int[3]_i_39_n_0\,
DI(0) => \y_int_reg[3]_i_40_n_5\,
O(3) => \y_int_reg[3]_i_19_n_4\,
O(2) => \y_int_reg[3]_i_19_n_5\,
O(1) => \y_int_reg[3]_i_19_n_6\,
O(0) => \y_int_reg[3]_i_19_n_7\,
S(3) => \y_int[3]_i_41_n_0\,
S(2) => \y_int[3]_i_42_n_0\,
S(1) => \y_int[3]_i_43_n_0\,
S(0) => \y_int[3]_i_44_n_0\
);
\y_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_45_n_0\,
CO(3) => \y_int_reg[3]_i_20_n_0\,
CO(2) => \y_int_reg[3]_i_20_n_1\,
CO(1) => \y_int_reg[3]_i_20_n_2\,
CO(0) => \y_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[3]_i_20_n_4\,
O(2) => \y_int_reg[3]_i_20_n_5\,
O(1 downto 0) => \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0),
S(3) => \y_int[3]_i_46_n_0\,
S(2) => \y_int[3]_i_47_n_0\,
S(1) => \y_int[3]_i_48_n_0\,
S(0) => \y_int[3]_i_49_n_0\
);
\y_int_reg[3]_i_40\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_70_n_0\,
CO(3) => \y_int_reg[3]_i_40_n_0\,
CO(2) => \y_int_reg[3]_i_40_n_1\,
CO(1) => \y_int_reg[3]_i_40_n_2\,
CO(0) => \y_int_reg[3]_i_40_n_3\,
CYINIT => '0',
DI(3) => rgb888(15),
DI(2 downto 0) => rgb888(12 downto 10),
O(3) => \y_int_reg[3]_i_40_n_4\,
O(2) => \y_int_reg[3]_i_40_n_5\,
O(1) => \y_int_reg[3]_i_40_n_6\,
O(0) => \y_int_reg[3]_i_40_n_7\,
S(3) => \y_int[3]_i_75_n_0\,
S(2) => \y_int[3]_i_76_n_0\,
S(1) => \y_int[3]_i_77_n_0\,
S(0) => \y_int[3]_i_78_n_0\
);
\y_int_reg[3]_i_45\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_45_n_0\,
CO(2) => \y_int_reg[3]_i_45_n_1\,
CO(1) => \y_int_reg[3]_i_45_n_2\,
CO(0) => \y_int_reg[3]_i_45_n_3\,
CYINIT => \cb_int[3]_i_84_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_80_n_0\,
S(2) => \y_int[3]_i_81_n_0\,
S(1) => \y_int[3]_i_82_n_0\,
S(0) => \y_int[3]_i_83_n_0\
);
\y_int_reg[3]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_70_n_0\,
CO(2) => \y_int_reg[3]_i_70_n_1\,
CO(1) => \y_int_reg[3]_i_70_n_2\,
CO(0) => \y_int_reg[3]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(9 downto 8),
DI(1 downto 0) => B"01",
O(3) => \y_int_reg[3]_i_70_n_4\,
O(2) => \y_int_reg[3]_i_70_n_5\,
O(1) => \y_int_reg[3]_i_70_n_6\,
O(0) => \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\(0),
S(3) => \y_int[3]_i_93_n_0\,
S(2) => \y_int[3]_i_94_n_0\,
S(1) => \y_int[3]_i_95_n_0\,
S(0) => \y_int[3]_i_96_n_0\
);
\y_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_20_n_0\,
CO(3) => \y_int_reg[7]_i_23_n_0\,
CO(2) => \y_int_reg[7]_i_23_n_1\,
CO(1) => \y_int_reg[7]_i_23_n_2\,
CO(0) => \y_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[7]_i_23_n_4\,
O(2) => \y_int_reg[7]_i_23_n_5\,
O(1) => \y_int_reg[7]_i_23_n_6\,
O(0) => \y_int_reg[7]_i_23_n_7\,
S(3) => \y_int[7]_i_25_n_0\,
S(2) => \y_int[7]_i_26_n_0\,
S(1) => \y_int[7]_i_27_n_0\,
S(0) => \y_int[7]_i_28_n_0\
);
end STRUCTURE;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package vhdl_range_pkg is
subtype integer_asc is integer range 0 to 7;
subtype integer_desc is integer range 8 downto 1;
end vhdl_range_pkg;
package body vhdl_range_pkg is
end vhdl_range_pkg;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package vhdl_range_pkg is
subtype integer_asc is integer range 0 to 7;
subtype integer_desc is integer range 8 downto 1;
end vhdl_range_pkg;
package body vhdl_range_pkg is
end vhdl_range_pkg;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package vhdl_range_pkg is
subtype integer_asc is integer range 0 to 7;
subtype integer_desc is integer range 8 downto 1;
end vhdl_range_pkg;
package body vhdl_range_pkg is
end vhdl_range_pkg;
|
library ieee;
use ieee.math_real.all;
entity issue527 is
end entity;
architecture test of issue527 is
signal s : bit;
begin
p1: process (s) is
variable s1, s2 : positive := 12345;
impure function random (x, y : delay_length) return delay_length is
variable r : real;
begin
uniform(s1, s2, r);
return x + r * (y - x);
end function;
begin
s <= not s after random(1 ns, 2 ns);
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the FIR Compiler IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the FIR Compiler product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated FIR Compiler core
-- instance named "fir_bp_p".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_fir_bp_p is
end tb_fir_bp_p;
architecture tb of tb_fir_bp_p is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT signals
-----------------------------------------------------------------------
-- General signals
signal aclk : std_logic := '0'; -- the master clock
-- Data slave channel signals
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
signal s_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(47 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data slave channel alias signals
signal s_axis_data_tdata_data : std_logic_vector(15 downto 0) := (others => '0');
-- Data master channel alias signals
signal m_axis_data_tdata_data : std_logic_vector(40 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.fir_bp_p
port map (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
-- Procedure to drive a number of input samples with specific data
-- data is the data value to drive on the tdata signal
-- samples is the number of zero-data input samples to drive
procedure drive_data ( data : std_logic_vector(15 downto 0);
samples : natural := 1 ) is
variable ip_count : integer := 0;
begin
ip_count := 0;
loop
s_axis_data_tvalid <= '1';
s_axis_data_tdata <= data;
loop
wait until rising_edge(aclk);
exit when s_axis_data_tready = '1';
end loop;
ip_count := ip_count + 1;
wait for T_HOLD;
exit when ip_count >= samples;
end loop;
end procedure drive_data;
-- Procedure to drive a number of zero-data input samples
-- samples is the number of zero-data input samples to drive
procedure drive_zeros ( samples : natural := 1 ) is
begin
drive_data((others => '0'), samples);
end procedure drive_zeros;
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
procedure drive_impulse ( samples : natural := 342 ) is
variable impulse : std_logic_vector(15 downto 0);
begin
impulse := (others => '0'); -- initialize unused bits to zero
impulse(15 downto 0) := "0100000000000000";
drive_data(impulse);
if samples > 1 then
drive_zeros(samples-1);
end if;
end procedure drive_impulse;
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive a single impulse and let the impulse response emerge
drive_impulse;
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
drive_impulse(2); -- start of impulse; data is now zero
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 5; -- provide no data for 5 input samples worth
drive_zeros(340); -- back to normal operation
-- End of test
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the master DATA channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data slave channel alias signals
s_axis_data_tdata_data <= s_axis_data_tdata(15 downto 0);
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_data <= m_axis_data_tdata(40 downto 0) when m_axis_data_tvalid = '1';
end tb;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1651.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s13b00x00p03n01i01651ent IS
procedure passive is
begin
null; -- or is that "dull"?
end passive;
begin
passive;
END c08s13b00x00p03n01i01651ent;
ARCHITECTURE c08s13b00x00p03n01i01651arch OF c08s13b00x00p03n01i01651ent IS
function troo return boolean is
begin
null;
return true;
end troo;
BEGIN
TESTING: PROCESS
variable v1 : integer := 1;
variable v2 : integer := 0;
BEGIN
if v1 > v2 then
null;
elsif v1 < v2 then
null;
else
null;
end if;
case troo is
when false => null;
when true => null;
end case;
loop
null;
exit; -- jump out of the infinite loop
end loop;
null;
assert FALSE
report "***PASSED TEST: c08s13b00x00p03n01i01651"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s13b00x00p03n01i01651arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1651.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s13b00x00p03n01i01651ent IS
procedure passive is
begin
null; -- or is that "dull"?
end passive;
begin
passive;
END c08s13b00x00p03n01i01651ent;
ARCHITECTURE c08s13b00x00p03n01i01651arch OF c08s13b00x00p03n01i01651ent IS
function troo return boolean is
begin
null;
return true;
end troo;
BEGIN
TESTING: PROCESS
variable v1 : integer := 1;
variable v2 : integer := 0;
BEGIN
if v1 > v2 then
null;
elsif v1 < v2 then
null;
else
null;
end if;
case troo is
when false => null;
when true => null;
end case;
loop
null;
exit; -- jump out of the infinite loop
end loop;
null;
assert FALSE
report "***PASSED TEST: c08s13b00x00p03n01i01651"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s13b00x00p03n01i01651arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1651.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s13b00x00p03n01i01651ent IS
procedure passive is
begin
null; -- or is that "dull"?
end passive;
begin
passive;
END c08s13b00x00p03n01i01651ent;
ARCHITECTURE c08s13b00x00p03n01i01651arch OF c08s13b00x00p03n01i01651ent IS
function troo return boolean is
begin
null;
return true;
end troo;
BEGIN
TESTING: PROCESS
variable v1 : integer := 1;
variable v2 : integer := 0;
BEGIN
if v1 > v2 then
null;
elsif v1 < v2 then
null;
else
null;
end if;
case troo is
when false => null;
when true => null;
end case;
loop
null;
exit; -- jump out of the infinite loop
end loop;
null;
assert FALSE
report "***PASSED TEST: c08s13b00x00p03n01i01651"
severity NOTE;
wait;
END PROCESS TESTING;
END c08s13b00x00p03n01i01651arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dac is
port (pulse : out STD_LOGIC;
data : in STD_LOGIC_VECTOR(7 downto 0);
clk : in STD_LOGIC
);
end dac;
architecture behavioral of dac is
signal sum : STD_LOGIC_VECTOR(8 downto 0) := (others => '0');
begin
pulse <= sum(8);
process(clk)
begin
if rising_edge(clk) then
sum <= std_logic_vector(unsigned("0" & sum(7 downto 0)) + unsigned("0" & data));
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- Company: Digilent Ro
-- Engineer: Elod Gyorgy
--
-- Create Date: 14:55:31 04/07/2011
-- Design Name:
-- Module Name: PkgTWI_Utils - Package
-- Project Name: TWI Master Controller Reference Design
-- Target Devices:
-- Tool versions:
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Description: This package provides enumeration types for TWI (Two-Wire
-- Interface) bus status and error conditions.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
package PkgTWI_Utils is
type busState_type is (busUnknown, busBusy, busFree);
type error_type is (errArb, errNAck);
end PkgTWI_Utils;
package body PkgTWI_Utils is
end PkgTWI_Utils;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:03:30 06/04/2011
-- Design Name:
-- Module Name: tx_arbitrator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: arbitrate between two sources that want to transmit onto a bus
-- handles arbitration and multiplexing
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Made sticky on port M1 to optimise access on this port and allow immediate grant
-- Revision 0.03 - Added first
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipv4_types.all;
entity tx_arbitrator_over_ip is
port (
clk : in std_logic;
reset : in std_logic;
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in ipv4_tx_type; -- data byte to tx
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in ipv4_tx_type; -- data byte to tx
data : out ipv4_tx_type -- data byte to tx
);
end tx_arbitrator_over_ip;
architecture Behavioral of tx_arbitrator_over_ip is
type grant_type is (M1,M2);
signal grant : grant_type;
begin
combinatorial : process (
grant,
data_1,
data_2
)
begin
-- grant outputs
case grant is
when M1 =>
grant_1 <= '1';
grant_2 <= '0';
when M2 =>
grant_1 <= '0';
grant_2 <= '1';
end case;
-- multiplexer
if grant = M1 then
data <= data_1;
else
data <= data_2;
end if;
end process;
sequential : process (clk, reset, req_1, req_2, grant)
begin
if rising_edge(clk) then
if reset = '1' then
grant <= M1;
else
case grant is
when M1 =>
if req_1 = '1' then
grant <= M1;
elsif req_2 = '1' then
grant <= M2;
end if;
when M2 =>
if req_2 = '1' then
grant <= M2;
else
grant <= M1;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library testgrouppolito;
use testgrouppolito.dprc_pkg.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
wdogn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_logic; -- bus ready
bexcn : in std_logic; -- bus exception
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_int : inout std_logic_vector(3 downto 0);
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
-- can_stb : out std_logic_vector(0 to CFG_CAN_NUM-1)
spw_clk : in std_logic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal spw_clkl : std_logic;
signal stati : ahbstat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal wdog : std_logic;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal pci_dirq : std_logic_vector(3 downto 0);
signal tck, tms, tdi, tdo : std_logic;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN + CFG_PCI + CFG_GRPCI2_MASTER;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant OEPOL : integer := padoen_polarity(padtech);
----------------------------------------------------------------------
--- FIR component declaration --------------------------------------
----------------------------------------------------------------------
component fir_ahb_dma_apb is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
technology : integer := virtex4);
port (
clk : in std_logic;
rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbin : in ahb_mst_in_type;
ahbout : out ahb_mst_out_type;
rm_reset: in std_logic
);
end component;
signal rm_reset : std_logic_vector(31 downto 0);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_INVCLK, CFG_PCI+CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_NUM+2*CFG_PRC, -- CFG_PRC if FIR core not included,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.edac <= gpioo.val(2); memi.bwidth <= gpioo.val(1 downto 0);
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, oepol => OEPOL,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
data_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (data, memo.data, memo.vbdrive, memi.data);
brdyn_pad : inpad generic map (tech => padtech) port map (brdyn, memi.brdyn);
bexcn_pad : inpad generic map (tech => padtech) port map (bexcn, memi.bexcn);
memi.writen <= '1'; memi.wrn <= "1111";
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
sd_pad : iopadvv generic map (tech => padtech, width => 32, oepol => OEPOL)
port map (sd(31 downto 0), memo.sddata(31 downto 0),
memo.svbdrive(31 downto 0), memi.sd(31 downto 0));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadvv generic map (tech => padtech, width => 32)
port map (sd(63 downto 32), memo.data(31 downto 0),
memo.svbdrive(63 downto 32), memi.sd(63 downto 32));
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width => 8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- No PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, vcc);
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, vcc(1 downto 0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
-- apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
wdog <= gpto.wdogn when OEPOL = 0 else gpto.wdog;
wdogn_pad : odpad generic map (tech => padtech, oepol => OEPOL) port map (wdogn, wdog);
end generate;
-- notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 6, paddr => 6, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(6), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pci : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 or CFG_PCI /= 0 generate
grpci2x : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 and (CFG_PCI+CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
oepol => OEPOL,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4,
haddr => 16#C00#,
hmask => 16#E00#,
ioaddr => 16#000#,
pindex => 4,
paddr => 4,
irq => 4,
irqmode => 0,
master => CFG_GRPCI2_MASTER,
target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA,
tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID,
deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS,
revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP,
ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO,
extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0,
bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2,
bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4,
bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH,
fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN,
deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK,
hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2,
hostrst => 1,
bypass => CFG_GRPCI2_BYPASS,
debug => 0,
tbapben => 0,
tbpindex => 5,
tbpaddr => 16#400#,
tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
open, open, open, open, open);
end generate;
grpci2xd : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 and CFG_PCI = 0 and
CFG_GRPCI2_DMA /= 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
oepol => OEPOL,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4,
haddr => 16#C00#,
hmask => 16#E00#,
ioaddr => 16#000#,
pindex => 4,
paddr => 4,
irq => 4,
irqmode => 0,
master => CFG_GRPCI2_MASTER,
target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA,
tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID,
deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS,
revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP,
ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO,
extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0,
bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2,
bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4,
bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH,
fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN,
deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK,
hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2,
hostrst => 1,
bypass => CFG_GRPCI2_BYPASS,
debug => 0,
tbapben => 0,
tbpindex => 5,
tbpaddr => 16#400#,
tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
open, open, open, open);
end generate;
grpci1x : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) = 0 and CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 13, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(13));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 8, paddr => 8,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(8)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 1, oepol => OEPOL,
noreset => 0, drivereset => 0, int => 10) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio, pci_int);
end generate;
-- nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
-- nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
-- nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
-- notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
-- noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(14), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (etx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
-- emdis_pad : outpad generic map (tech => padtech)
-- port map (emddis, vcc(0));
-- eepwrdwn_pad : outpad generic map (tech => padtech)
-- port map (epwrdwn, gnd(0));
-- esleep_pad : outpad generic map (tech => padtech)
-- port map (esleep, gnd(0));
-- epause_pad : outpad generic map (tech => padtech)
-- port map (epause, gnd(0));
-- ereset_pad : outpad generic map (tech => padtech)
-- port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
can_pads : for i in 0 to CFG_CAN_NUM-1 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd(i), can_ltx(i));
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd(i), can_lrx(i));
end generate;
end generate;
-- can_stb <= '0'; -- no standby
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
-- ocram : if CFG_AHBRAMEN = 1 generate
-- ahbram0 : ftahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
-- tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pindex => 6,
-- paddr => 6, edacen => CFG_AHBRAEDAC, autoscrub => CFG_AHBRASCRU,
-- errcnten => CFG_AHBRAECNT, cntbits => CFG_AHBRAEBIT)
-- port map ( rstn, clkm, ahbsi, ahbso(7), apbi, apbo(6), open);
-- end generate;
--
-- nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_clkl);
-- spw_clkl <= pciclk;
spw_rxtxclk <= spw_clkl;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 1)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => fabtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i,
pindex => 10+i, paddr => 10+i, pirq => 5+i,
sysfreq => CPU_FREQ, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 1, memtech => memtech,
rmapbufs => CFG_SPW_RMAPBUF,ft => CFG_SPW_FT, ports => 1,
dmachan => CFG_SPW_DMACHAN, netlist => CFG_SPW_NETLIST, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME, rxunaligned => CFG_SPW_RXUNAL)
port map(rstn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+i),
apbi, apbo(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '0';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txdp(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txsp(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- DYNAMIC PARTIAL RECONFIGURATION ---------------------------------
-----------------------------------------------------------------------
prc : if CFG_PRC = 1 generate
p1 : dprc generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_NUM, pindex => 10+CFG_SPW_NUM, paddr => 10+CFG_SPW_NUM,
technology => CFG_FABTECH, crc_en => CFG_CRC_EN, words_block => CFG_WORDS_BLOCK, fifo_dcm_inst => CFG_DCM_FIFO, fifo_depth => CFG_DPR_FIFO)
port map(rstn => rstn, clkm => clkm, clkraw => lclk, clk100 => '0', ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH
+CFG_SPW_NUM), apbi => apbi, apbo => apbo(10+CFG_SPW_NUM), rm_reset => rm_reset);
--------------------------------------------------------------------
-- FIR component instantiation (for dprc demo) -------------------
--------------------------------------------------------------------
fir_ex : FIR_AHB_DMA_APB
generic map (hindex=>CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH+CFG_SPW_NUM+CFG_PRC, pindex=>10+CFG_SPW_NUM+1, paddr=>10+CFG_SPW_NUM+1,
pmask=>16#fff#, technology =>CFG_FABTECH)
port map (rstn=>rstn, clk=>clkm, apbi=>apbi, apbo=>apbo(10+CFG_SPW_NUM+1), ahbin=>ahbmi, ahbout=>ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+log2x(CFG_PCI)+CFG_AHB_JTAG+CFG_GRETH
+CFG_SPW_NUM+CFG_PRC), rm_reset => rm_reset(0));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+log2x(CFG_PCI)+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+log2x(CFG_PCI)-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3FT GR-CPCI-XC4V Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research
-- Description: Combined LEON3 debug support and AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity dsu3x is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of dsu3x is
constant TBUFABITS : integer := log2(kbytes) + 6;
constant NBITS : integer := log2x(ncpu);
constant PROC_H : integer := 24+NBITS-1;
constant PROC_L : integer := 24;
constant AREA_H : integer := 23;
constant AREA_L : integer := 20;
constant HBITS : integer := 28;
constant DSU3_VERSION : integer := 2;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON3DSU, 0, DSU3_VERSION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
others => zero32);
type slv_reg_type is record
hsel : std_ulogic;
haddr : std_logic_vector(PROC_H downto 0);
hwrite : std_ulogic;
hwdata : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hready : std_ulogic;
hready2 : std_ulogic;
end record;
constant slv_reg_none : slv_reg_type := (
hsel => '0',
haddr => (others => '0'),
hwrite => '0',
hwdata => (others => '0'),
hrdata => (others => '0'),
hready => '1',
hready2 => '1'
);
type reg_type is record
slv : slv_reg_type;
en : std_logic_vector(0 to NCPU-1);
te : std_logic_vector(0 to NCPU-1);
be : std_logic_vector(0 to NCPU-1);
bw : std_logic_vector(0 to NCPU-1);
bs : std_logic_vector(0 to NCPU-1);
bx : std_logic_vector(0 to NCPU-1);
bz : std_logic_vector(0 to NCPU-1);
halt : std_logic_vector(0 to NCPU-1);
reset : std_logic_vector(0 to NCPU-1);
bn : std_logic_vector(NCPU-1 downto 0);
ss : std_logic_vector(NCPU-1 downto 0);
bmsk : std_logic_vector(NCPU-1 downto 0);
dmsk : std_logic_vector(NCPU-1 downto 0);
cnt : std_logic_vector(2 downto 0);
dsubre : std_logic_vector(2 downto 0);
dsuen : std_logic_vector(2 downto 0);
act : std_ulogic;
timer : std_logic_vector(tbits-1 downto 0);
pwd : std_logic_vector(NCPU-1 downto 0);
tstop : std_ulogic;
end record;
constant RRES : reg_type := (
slv => slv_reg_none,
en => (others => '0'),
te => (others => '0'),
be => (others => '0'),
bw => (others => '0'),
bs => (others => '0'),
bx => (others => '0'),
bz => (others => '0'),
halt => (others => '0'),
reset => (others => '0'),
bn => (others => '0'),
ss => (others => '0'),
bmsk => (others => '0'),
dmsk => (others => '0'),
cnt => (others => '0'),
dsubre => (others => '0'),
dsuen => (others => '0'),
act => '0',
timer => (others => '0'),
pwd => (others => '0'),
tstop => '0'
);
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
end record;
constant trace_break_none : trace_break_reg := (
addr => (others => '0'),
mask => (others => '0'),
read => '0',
write => '0'
);
type tregtype is record
haddr : std_logic_vector(31 downto 0);
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
hmastlock : std_logic;
ahbactive : std_logic;
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
enable : std_logic; -- trace enable
bphit : std_logic; -- AHB breakpoint hit
bphit2 : std_logic; -- delayed bphit
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
tbwr : std_logic; -- trace buffer write enable
break : std_logic; -- break CPU when AHB tracing stops
tforce : std_logic; -- Force AHB trace
timeren : std_logic; -- Keep timer enabled
sample : std_logic; -- Force sample
end record;
constant TRES : tregtype := (
haddr => (others => '0'),
hwrite => '0',
htrans => (others => '0'),
hsize => (others => '0'),
hburst => (others => '0'),
hwdata => (others => '0'),
hmaster => (others => '0'),
hmastlock => '0',
ahbactive => '0',
aindex => (others => '0'),
enable => '0',
bphit => '0',
bphit2 => '0',
dcnten => '0',
delaycnt => (others => '0'),
tbreg1 => trace_break_none,
tbreg2 => trace_break_none,
tbwr => '0',
break => '0',
tforce => '0',
timeren => '0',
sample => '0'
);
type tfregtype is record
shsel : std_logic_vector(0 to NAHBSLV-1);
pf : std_ulogic; -- Filter perf outputs
af : std_ulogic; -- Address filtering
fr : std_ulogic; -- Filter reads
fw : std_ulogic; -- Filter writes
smask : std_logic_vector(15 downto 0);
mmask : std_logic_vector(15 downto 0);
bpfilt : std_logic_vector(1 downto 0);
end record;
type pregtype is record
stat : dsu_astat_type;
split : std_ulogic;
splmst : std_logic_vector(3 downto 0);
hready : std_ulogic;
hresp : std_logic_vector(1 downto 0);
end record;
constant PRES : pregtype := (
stat => dsu_astat_none, split => '0', splmst => "0000", hready => '1', hresp => "00");
constant TFRES : tfregtype :=
(shsel => (others => '0'), pf => '0', af => '0', fr => '0', fw => '0',
smask => (others => '0'), mmask => (others => '0'),
bpfilt => (others => '0'));
type hclk_reg_type is record
irq : std_ulogic;
oen : std_ulogic;
end record;
constant hclk_reg_none : hclk_reg_type := (
irq => '0', oen => '0'
);
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant TRACEN : boolean := (kbytes /= 0);
constant FILTEN : boolean := TRACEN and (ahbpf > 0);
constant PERFEN : boolean := (ahbpf > 1);
function ahb_filt_hit (
tr : tregtype;
tfr : tfregtype) return boolean is
variable hit : boolean;
begin
-- filter hit -> inhibit
hit := false;
-- Filter on read/write
if ((tfr.fw and tr.hwrite) or (tfr.fr and not tr.hwrite)) = '1' then
hit := true;
end if;
-- Filter on address range
if (((tr.tbreg2.addr xor tr.haddr(31 downto 2)) and tr.tbreg2.mask) /= zero32(29 downto 0)) then
if tfr.af = '1' then hit := true; end if;
end if;
-- Filter on master mask
for i in tfr.mmask'range loop
if i > NAHBMST-1 then exit; end if;
if i = conv_integer(tr.hmaster) and tfr.mmask(i) = '1' then
hit := true;
end if;
end loop;
-- Filter on slave mask
for i in tfr.smask'range loop
if i > NAHBSLV-1 then exit; end if;
if (tfr.shsel(i) and tfr.smask(i)) /= '0' then
hit := true;
end if;
end loop;
return hit;
end function ahb_filt_hit;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal pr, prin : pregtype;
signal tfr, tfrin : tfregtype;
signal tr, trin : tregtype;
signal r, rin : reg_type;
signal rh, rhin : hclk_reg_type;
signal ahbsi2, tahbsi2 : ahb_slv_in_type;
signal hrdata2x : std_logic_vector(31 downto 0);
begin
comb: process(rst, r, ahbsi, ahbsi2, tahbsi2, dbgi, dsui, ahbmi, tr, tbo, hclken, rh, hrdata2x, tfr, pr)
variable v : reg_type;
variable iuacc : std_ulogic;
variable dbgmode, tstop : std_ulogic;
variable rawindex : integer range 0 to (2**NBITS)-1;
variable index : natural range 0 to NCPU-1;
variable hasel1 : std_logic_vector(AREA_H-1 downto AREA_L);
variable hasel2 : std_logic_vector(6 downto 2);
variable tv : tregtype;
variable vabufi : tracebuf_in_type;
variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable cpwd : std_logic_vector(15 downto 0);
variable hrdata : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable rdata, wdata : std_logic_vector(127 downto 0);
variable bphit : std_logic_vector(1 to 2);
variable vh : hclk_reg_type;
variable atact : std_ulogic; -- ahb trace active
variable tfv : tfregtype;
variable pv : pregtype;
variable slvhaddr : std_logic_vector(2 downto 0);
begin
v := r;
iuacc := '0'; --v.slv.hready := '0';
dbgmode := '0'; tstop := '1';
v.dsubre := r.dsubre(1 downto 0) & dsui.break;
v.dsuen := r.dsuen(1 downto 0) & dsui.enable;
hrdata := r.slv.hrdata; hwdata := ahbreadword(ahbsi2.hwdata, r.slv.haddr(4 downto 2));
wdata := (others => '0'); rdata := (others => '0');
tv := tr; vabufi.enable := '0'; tv.bphit := '0'; tv.tbwr := '0'; tv.sample := '0';
if (clk2x /= 0) then tv.bphit2 := tr.bphit; else tv.bphit2 := '0'; end if;
vabufi.data := (others => '0'); vabufi.addr := (others => '0');
vabufi.write := (others => '0'); aindex := (others => '0');
hirq := (others => '0'); v.reset := (others => '0');
tfv := tfr; pv := pr;
if TRACEN then
aindex := tr.aindex + 1;
if (clk2x /= 0) then vh.irq := tr.bphit or tr.bphit2; hirq(irq) := rh.irq;
else hirq(irq) := tr.bphit; end if;
end if;
if hclken = '1' then
v.slv.hready := '0'; v.act := '0';
end if;
atact := tr.enable and ((not r.act) or tr.tforce);
-- check for AHB watchpoints
bphit := (others => '0');
if TRACEN and ((tahbsi2.hready and tr.ahbactive) = '1') then
if ((((tr.tbreg1.addr xor tr.haddr(31 downto 2)) and tr.tbreg1.mask) = zero32(29 downto 0)) and
(((tr.tbreg1.read and not tr.hwrite) or (tr.tbreg1.write and tr.hwrite)) = '1'))
then bphit(1) := '1'; end if;
if ((((tr.tbreg2.addr xor tr.haddr(31 downto 2)) and tr.tbreg2.mask) = zero32(29 downto 0)) and
(((tr.tbreg2.read and not tr.hwrite) or (tr.tbreg2.write and tr.hwrite)) = '1'))
then bphit(2) := '1'; end if;
end if;
-- generate AHB buffer inputs
vabufi.write := (others => '0');
if TRACEN then
wdata(AHBDW-1 downto 0) := tahbsi2.hwdata;
rdata(AHBDW-1 downto 0) := ahbmi.hrdata;
if atact = '1' then
vabufi.addr(TBUFABITS-1 downto 0) := tr.aindex;
vabufi.data(127) := orv(bphit);
vabufi.data(96+tbits-1 downto 96) := r.timer;
vabufi.data(94 downto 80) := (others => '0'); --ahbmi.hirq(15 downto 1);
vabufi.data(79) := tr.hwrite;
vabufi.data(78 downto 77) := tr.htrans;
vabufi.data(76 downto 74) := tr.hsize;
vabufi.data(73 downto 71) := tr.hburst;
vabufi.data(70 downto 67) := tr.hmaster;
vabufi.data(66) := tr.hmastlock;
vabufi.data(65 downto 64) := ahbmi.hresp;
if tr.hwrite = '1' then
vabufi.data(63 downto 32) := wdata(31 downto 0);
vabufi.data(223 downto 128) := wdata(127 downto 32);
else
vabufi.data(63 downto 32) := rdata(31 downto 0);
vabufi.data(223 downto 128) := rdata(127 downto 32);
end if;
vabufi.data(31 downto 0) := tr.haddr;
else
if bwidth = 32 then
vabufi.addr(TBUFABITS-1 downto 0) := r.slv.haddr(TBUFABITS+3 downto 4); --tr.haddr(TBUFABITS+3 downto 4);
else
vabufi.addr(TBUFABITS-1 downto 0) := r.slv.haddr(TBUFABITS+4 downto 5); --tr.haddr(TBUFABITS+4 downto 5);
end if;
-- Note: HWDATA from register i/f
vabufi.data(255 downto 0) := hwdata & hwdata & hwdata & hwdata & hwdata & hwdata & hwdata & hwdata;
end if;
-- filter and write trace buffer
if atact = '1' then
if ((tr.ahbactive and tahbsi2.hready) or tr.sample) = '1' then
if not (FILTEN and ahb_filt_hit(tr, tfr)) then
tv.aindex := aindex; tv.tbwr := '1';
vabufi.enable := '1'; vabufi.write := (others => '1');
elsif FILTEN then
for i in 1 to 2 loop
if tfr.bpfilt(i-1) = '1' then bphit(i) := '0'; end if;
end loop;
end if;
end if;
end if;
-- trigger AHB break/watchpoints
if orv(bphit) = '1' then
if (atact = '1') and (tr.dcnten = '0') and
(tr.delaycnt /= zero32(TBUFABITS-1 downto 0))
then tv.dcnten := '1';
else tv.enable := '0'; tv.tforce := '0'; tv.timeren := '0'; tv.bphit := tr.break; end if;
end if;
-- trace buffer delay counter handling
if (tr.dcnten = '1') then
if (tr.delaycnt = zero32(TBUFABITS-1 downto 0)) then
tv.enable := '0'; tv.dcnten := '0'; tv.bphit := tr.break;
end if;
if tr.tbwr = '1' then tv.delaycnt := tr.delaycnt - 1; end if;
end if;
-- AHB statistics
if PERFEN then
pv.hready := tahbsi2.hready;
pv.hresp := ahbmi.hresp;
pv.stat := dsu_astat_none;
if pr.hready = '1' then
case tr.htrans is
when HTRANS_IDLE => pv.stat.idle := '1';
when HTRANS_BUSY => pv.stat.busy := '1';
when HTRANS_NONSEQ => pv.stat.nseq := '1';
when others => pv.stat.seq := '1';
end case;
if tr.ahbactive = '1' then
pv.stat.read := not tr.hwrite;
pv.stat.write := tr.hwrite;
case tr.hsize is
when HSIZE_BYTE => pv.stat.hsize(0) := '1';
when HSIZE_HWORD => pv.stat.hsize(1) := '1';
when HSIZE_WORD => pv.stat.hsize(2) := '1';
when HSIZE_DWORD => pv.stat.hsize(3) := '1';
when HSIZE_4WORD => pv.stat.hsize(4) := '1';
when others => pv.stat.hsize(5) := '1';
end case;
end if;
pv.stat.hmaster := tr.hmaster;
end if;
if pr.hresp = HRESP_OKAY then
pv.stat.ws := not pr.hready;
end if;
-- It may also be interesting to count the maximum grant latency. That
-- is; the delay between asserting hbusreq and receiving hgrant. This
-- would require that all bus request signals were present in this
-- entity. This has been left as a possible future extension.
if pr.hready = '1' then
if pr.hresp = HRESP_SPLIT then
pv.stat.split := '1';
pv.split := '1';
if pr.split = '0' then
pv.splmst := tr.hmaster;
end if;
end if;
if pr.hresp = HRESP_RETRY then
pv.stat.retry := '1';
end if;
end if;
pv.stat.locked := tr.hmastlock;
if tfr.pf = '1' and ahb_filt_hit(tr, tfr) then
pv.stat := dsu_astat_none;
pv.split := pr.split; pv.splmst := pr.splmst;
end if;
-- Count cycles where master is in SPLIT
if pr.split = '1' then
for i in ahbmi.hgrant'range loop
if i = conv_integer(pr.splmst) and ahbmi.hgrant(i) = '1' then
pv.split := '0';
end if;
end loop;
pv.stat.spdel := pv.split;
end if;
end if;
-- save AHB transfer parameters
if (tahbsi2.hready or tr.sample) = '1' then
tv.haddr := tahbsi2.haddr; tv.hwrite := tahbsi2.hwrite; tv.htrans := tahbsi2.htrans;
tv.hsize := tahbsi2.hsize; tv.hburst := tahbsi2.hburst;
tv.hmaster := tahbsi2.hmaster; tv.hmastlock := tahbsi2.hmastlock;
tv.ahbactive := tahbsi2.htrans(1);
if FILTEN then tfv.shsel := tahbsi2.hsel; end if;
end if;
end if;
if r.slv.hsel = '1' then
if (clk2x = 0) then
v.cnt := r.cnt - 1;
else
if (r.cnt /= "111") or (hclken = '1') then v.cnt := r.cnt - 1; end if;
end if;
end if;
if (r.slv.hready and hclken) = '1' then
v.slv.hsel := '0'; --v.slv.act := '0';
end if;
for i in 0 to NCPU-1 loop
if dbgi(i).dsumode = '1' then
if r.dmsk(i) = '0' then
dbgmode := '1';
if hclken = '1' then v.act := '1'; end if;
end if;
v.bn(i) := '1';
else
tstop := '0';
end if;
end loop;
if ((r.dsuen(2) and not tstop) or tr.timeren) = '1' then v.timer := r.timer + 1; end if;
if (clk2x /= 0) then
if hclken = '1' then v.tstop := tstop; end if;
tstop := r.tstop;
end if;
cpwd := (others => '0');
for i in 0 to NCPU-1 loop
v.bn(i) := v.bn(i) or (dbgmode and r.bmsk(i)) or (r.dsubre(1) and not r.dsubre(2));
if TRACEN then v.bn(i) := v.bn(i) or (tr.bphit and not r.ss(i) and not r.act); end if;
v.pwd(i) := dbgi(i).idle and (not dbgi(i).ipend) and not v.bn(i);
end loop;
cpwd(NCPU-1 downto 0) := r.pwd;
if (ahbsi2.hready and ahbsi2.hsel(hindex)) = '1' then
if (ahbsi2.htrans(1) = '1') then
v.slv.hsel := '1';
v.slv.haddr := ahbsi2.haddr(PROC_H downto 0);
v.slv.hwrite := ahbsi2.hwrite;
v.cnt := "111";
end if;
end if;
for i in 0 to NCPU-1 loop
v.en(i) := r.dsuen(2) and dbgi(i).dsu;
end loop;
rawindex := conv_integer(r.slv.haddr(PROC_H downto PROC_L));
if ncpu = 1 then index := 0; else
if rawindex > ncpu then index := ncpu-1; else index := rawindex; end if;
end if;
hasel1 := r.slv.haddr(AREA_H-1 downto AREA_L);
hasel2 := r.slv.haddr(6 downto 2);
if r.slv.hsel = '1' then
case hasel1 is
when "000" => -- DSU registers
if r.cnt(2 downto 0) = "110" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
hrdata := (others => '0');
case hasel2 is
when "00000" =>
if r.slv.hwrite = '1' then
if hclken = '1' then
v.te(index) := hwdata(0);
v.be(index) := hwdata(1);
v.bw(index) := hwdata(2);
v.bs(index) := hwdata(3);
v.bx(index) := hwdata(4);
v.bz(index) := hwdata(5);
v.reset(index) := hwdata(9);
v.halt(index) := hwdata(10);
else v.reset := r.reset; end if;
end if;
hrdata(0) := r.te(index);
hrdata(1) := r.be(index);
hrdata(2) := r.bw(index);
hrdata(3) := r.bs(index);
hrdata(4) := r.bx(index);
hrdata(5) := r.bz(index);
hrdata(6) := dbgi(index).dsumode;
hrdata(7) := r.dsuen(2);
hrdata(8) := r.dsubre(2);
hrdata(9) := not dbgi(index).error;
hrdata(10) := dbgi(index).halt;
hrdata(11) := dbgi(index).pwd;
when "00010" => -- timer
if r.slv.hwrite = '1' then
if hclken = '1' then
v.timer := hwdata(tbits-1 downto 0);
else v.timer := r.timer; end if;
end if;
hrdata(tbits-1 downto 0) := r.timer;
when "01000" =>
if r.slv.hwrite = '1' then
if hclken = '1' then
v.bn := hwdata(NCPU-1 downto 0);
v.ss := hwdata(16+NCPU-1 downto 16);
else v.bn := r.bn; v.ss := r.ss; end if;
end if;
hrdata(NCPU-1 downto 0) := r.bn;
hrdata(16+NCPU-1 downto 16) := r.ss;
when "01001" =>
if (r.slv.hwrite and hclken) = '1' then
v.bmsk(NCPU-1 downto 0) := hwdata(NCPU-1 downto 0);
v.dmsk(NCPU-1 downto 0) := hwdata(NCPU-1+16 downto 16);
end if;
hrdata(NCPU-1 downto 0) := r.bmsk;
hrdata(NCPU-1+16 downto 16) := r.dmsk;
when "10000" =>
if TRACEN then
hrdata((TBUFABITS + 15) downto 16) := tr.delaycnt;
hrdata(6 downto 5) := tr.timeren & tr.tforce;
hrdata(4 downto 0) := conv_std_logic_vector(log2(bwidth/32), 2) & tr.break & tr.dcnten & tr.enable;
if r.slv.hwrite = '1' then
if hclken = '1' then
tv.delaycnt := hwdata((TBUFABITS+ 15) downto 16);
tv.sample := hwdata(7);
tv.timeren := hwdata(6);
tv.tforce := hwdata(5);
tv.break := hwdata(2);
tv.dcnten := hwdata(1);
tv.enable := hwdata(0);
else
tv.delaycnt := tr.delaycnt;
tv.sample := tr.sample; tv.timeren := tr.timeren;
tv.tforce := tr.tforce; tv.break := tr.break;
tv.dcnten := tr.dcnten; tv.enable := tr.enable;
end if;
end if;
end if;
when "10001" =>
if TRACEN then
hrdata((TBUFABITS - 1 + 4) downto 4) := tr.aindex;
if r.slv.hwrite = '1' then
if hclken = '1' then
tv.aindex := hwdata((TBUFABITS - 1 + 4) downto 4);
else tv.aindex := tr.aindex; end if;
end if;
end if;
when "10010" =>
if FILTEN then
hrdata(9 downto 8) := tfr.bpfilt;
hrdata(3 downto 0) := tfr.pf & tfr.af & tfr.fr & tfr.fw;
if r.slv.hwrite = '1' then
if hclken = '1' then
tfv.bpfilt := hwdata(9 downto 8);
tfv.pf := hwdata(3);
tfv.af := hwdata(2);
tfv.fr := hwdata(1);
tfv.fw := hwdata(0);
else
tfv.bpfilt := tfr.bpfilt;
tfv.pf := tfr.pf;
tfv.af := tfr.af;
tfv.fr := tfr.fr;
tfv.fw := tfr.fw;
end if;
end if;
end if;
when "10011" =>
if FILTEN then
hrdata := tfr.smask & tfr.mmask;
if r.slv.hwrite = '1' then
if hclken = '1' then
tfv.smask := hwdata(31 downto 16);
tfv.mmask := hwdata(15 downto 0);
else
tfv.smask := tfr.smask;
tfv.mmask := tfr.mmask;
end if;
end if;
end if;
when "10100" =>
if TRACEN then
hrdata(31 downto 2) := tr.tbreg1.addr;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg1.addr := hwdata(31 downto 2);
end if;
end if;
when "10101" =>
if TRACEN then
hrdata := tr.tbreg1.mask & tr.tbreg1.read & tr.tbreg1.write;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg1.mask := hwdata(31 downto 2);
tv.tbreg1.read := hwdata(1);
tv.tbreg1.write := hwdata(0);
end if;
end if;
when "10110" =>
if TRACEN then
hrdata(31 downto 2) := tr.tbreg2.addr;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg2.addr := hwdata(31 downto 2);
end if;
end if;
when "10111" =>
if TRACEN then
hrdata := tr.tbreg2.mask & tr.tbreg2.read & tr.tbreg2.write;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg2.mask := hwdata(31 downto 2);
tv.tbreg2.read := hwdata(1);
tv.tbreg2.write := hwdata(0);
end if;
end if;
when others =>
end case;
when "010" => -- AHB tbuf
if TRACEN then
if r.cnt(2 downto 0) = "101" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
vabufi.enable := not atact;
slvhaddr := r.slv.haddr(4 downto 2);
case slvhaddr is
when "000" =>
hrdata := tbo.data(127 downto 96);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(3) := vabufi.enable and v.slv.hready;
end if;
when "001" =>
hrdata := tbo.data(95 downto 64);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(2) := vabufi.enable and v.slv.hready;
end if;
when "010" =>
hrdata := tbo.data(63 downto 32);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(1) := vabufi.enable and v.slv.hready;
end if;
when "011" =>
hrdata := tbo.data(31 downto 0);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(0) := vabufi.enable and v.slv.hready;
end if;
when "100" =>
if bwidth > 32 then
hrdata := tbo.data(159 downto 128);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(7) := vabufi.enable and v.slv.hready;
end if;
else
hrdata := tbo.data(127 downto 96);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(3) := vabufi.enable and v.slv.hready;
end if;
end if;
when "101" =>
if bwidth > 32 then
if bwidth > 64 then
hrdata := tbo.data(223 downto 192);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(6) := vabufi.enable and v.slv.hready;
end if;
else hrdata := zero32; end if;
else
hrdata := tbo.data(95 downto 64);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(2) := vabufi.enable and v.slv.hready;
end if;
end if;
when "110" =>
if bwidth > 32 then
if bwidth > 64 then
hrdata := tbo.data(191 downto 160);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(5) := vabufi.enable and v.slv.hready;
end if;
else hrdata := zero32; end if;
else
hrdata := tbo.data(63 downto 32);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(1) := vabufi.enable and v.slv.hready;
end if;
end if;
when others =>
if bwidth > 32 then
hrdata := zero32;
else
hrdata := tbo.data(31 downto 0);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(0) := vabufi.enable and v.slv.hready;
end if;
end if;
end case;
else
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "011" | "001" => -- IU reg file, IU tbuf
iuacc := '1';
hrdata := dbgi(index).data;
if r.cnt(2 downto 0) = "101" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "100" => -- IU reg access
iuacc := '1';
hrdata := dbgi(index).data;
if r.cnt(1 downto 0) = "11" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "111" => -- DSU ASI
if r.cnt(2 downto 1) = "11" then iuacc := '1'; else iuacc := '0'; end if;
if (dbgi(index).crdy = '1') or (r.cnt = "000") then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
hrdata := dbgi(index).data;
when others =>
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end case;
if (r.slv.hready and hclken and not v.slv.hsel) = '1' then v.slv.hready := '0'; end if;
if (clk2x /= 0) and (r.slv.hready2 and hclken) = '1' then v.slv.hready := '1'; end if;
end if;
if r.slv.hsel = '1' then
if (r.slv.hwrite and hclken) = '1' then v.slv.hwdata := hwdata(31 downto 0); end if;
if (clk2x = 0) or ((r.slv.hready or r.slv.hready2) = '0') then
v.slv.hrdata := hrdata;
end if;
end if;
if ((ahbsi2.hready and ahbsi2.hsel(hindex)) = '1') and (ahbsi2.htrans(1) = '0') then
if (clk2x = 0) or (r.slv.hsel = '0') then
v.slv.hready := '1';
end if;
end if;
if (clk2x /= 0) and (r.slv.hready = '1') then v.slv.hready2 := '0'; end if;
if v.slv.hsel = '0' then v.slv.hready := '1'; end if;
vh.oen := '0';
if (clk2x /= 0) then
if (hclken and r.slv.hsel and (r.slv.hready2 or v.slv.hready)) = '1'
then vh.oen := '1'; end if;
if (r.slv.hsel = '1') and (r.cnt = "111") and (hclken = '0') then iuacc := '0'; end if;
end if;
if (not RESET_ALL) and (rst = '0') then
v.bn := (others => r.dsubre(2)); v.bmsk := (others => '0');
v.dmsk := (others => '0');
v.ss := (others => '0'); v.timer := (others => '0'); v.slv.hsel := '0';
for i in 0 to NCPU-1 loop
v.bw(i) := r.dsubre(2); v.be(i) := r.dsubre(2);
v.bx(i) := r.dsubre(2); v.bz(i) := r.dsubre(2);
v.bs(i) := '0'; v.te(i) := '0';
end loop;
tv.ahbactive := '0'; tv.enable := '0'; tv.tforce := '0'; tv.timeren := '0';
tv.dcnten := '0';
tv.tbreg1.read := '0'; tv.tbreg1.write := '0';
tv.tbreg2.read := '0'; tv.tbreg2.write := '0';
v.slv.hready := '1'; v.halt := (others => '0');
v.act := '0'; v.tstop := '0';
if FILTEN then
tfv.pf := '0'; tfv.af := '0'; tfv.fr := '0'; tfv.fw := '0';
tfv.smask := (others => '0'); tfv.mmask := (others => '0');
tfv.bpfilt := (others => '0');
end if;
if PERFEN then
pv.split := '0'; pv.splmst := (others => '0');
end if;
end if;
rin <= v; trin <= tv; tbi <= vabufi; tfrin <= tfv; prin <= pv;
for i in 0 to NCPU-1 loop
dbgo(i).tenable <= r.te(i);
dbgo(i).dsuen <= r.en(i);
dbgo(i).dbreak <= r.bn(i); -- or (dbgmode and r.bmsk(i));
if conv_integer(r.slv.haddr(PROC_H downto PROC_L)) = i then
dbgo(i).denable <= iuacc;
else
dbgo(i).denable <= '0';
end if;
dbgo(i).step <= r.ss(i);
dbgo(i).berror <= r.be(i);
dbgo(i).bsoft <= r.bs(i);
dbgo(i).bwatch <= r.bw(i);
dbgo(i).btrapa <= r.bx(i);
dbgo(i).btrape <= r.bz(i);
dbgo(i).daddr <= r.slv.haddr(PROC_L-1 downto 2);
dbgo(i).ddata <= r.slv.hwdata(31 downto 0);
dbgo(i).dwrite <= r.slv.hwrite;
dbgo(i).halt <= r.halt(i);
dbgo(i).reset <= r.reset(i);
dbgo(i).timer(tbits-1 downto 0) <= r.timer;
dbgo(i).timer(30 downto tbits) <= (others => '0');
end loop;
ahbso.hconfig <= hconfig;
ahbso.hresp <= HRESP_OKAY;
ahbso.hready <= r.slv.hready;
if (clk2x = 0) then
ahbso.hrdata <= ahbdrivedata(r.slv.hrdata);
else
ahbso.hrdata <= ahbdrivedata(hrdata2x);
end if;
ahbso.hsplit <= (others => '0');
ahbso.hirq <= hirq;
ahbso.hindex <= hindex;
dsuo.active <= r.act;
dsuo.tstop <= tstop;
dsuo.pwd <= cpwd;
if PERFEN then dsuo.astat <= pr.stat; else dsuo.astat <= dsu_astat_none; end if;
rhin <= vh;
end process;
comb2gen0 : if (clk2x /= 0) generate
-- register i/f
gen0 : for i in ahbsi.hsel'range generate
ag0 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hsel(i), hclken, ahbsi2.hsel(i));
end generate;
gen1 : for i in ahbsi.haddr'range generate
ag1 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.haddr(i), hclken, ahbsi2.haddr(i));
end generate;
ag2 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwrite, hclken, ahbsi2.hwrite);
gen3 : for i in ahbsi.htrans'range generate
ag3 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.htrans(i), hclken, ahbsi2.htrans(i));
end generate;
gen4 : for i in ahbsi.hwdata'range generate
ag4 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwdata(i), hclken, ahbsi2.hwdata(i));
end generate;
ag5 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hready, hclken, ahbsi2.hready);
-- not used by register i/f:
ahbsi2.hsize <= (others => '0');
ahbsi2.hburst <= (others => '0');
ahbsi2.hprot <= (others => '0');
ahbsi2.hmaster <= (others => '0');
ahbsi2.hmastlock <= '0';
ahbsi2.hmbsel <= (others => '0');
ahbsi2.hirq <= (others => '0');
ahbsi2.testen <= '0';
ahbsi2.testrst <= '0';
ahbsi2.scanen <= '0';
ahbsi2.testoen <= '0';
-- trace buffer:
gen6 : for i in tahbsi.haddr'range generate
ag6 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.haddr(i), hclken, tahbsi2.haddr(i));
end generate;
ag7 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hwrite, hclken, tahbsi2.hwrite);
gen8 : for i in tahbsi.htrans'range generate
ag8 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.htrans(i), hclken, tahbsi2.htrans(i));
end generate;
gen9 : for i in tahbsi.hsize'range generate
ag9 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hsize(i), hclken, tahbsi2.hsize(i));
end generate;
gen10 : for i in tahbsi.hburst'range generate
a10 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hburst(i), hclken, tahbsi2.hburst(i));
end generate;
gen11 : for i in tahbsi.hwdata'range generate
ag11 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hwdata(i), hclken, tahbsi2.hwdata(i));
end generate;
ag12 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hready, hclken, tahbsi2.hready);
gen12 : for i in tahbsi.hmaster'range generate
ag12 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hmaster(i), hclken, tahbsi2.hmaster(i));
end generate;
ag13 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hmastlock, hclken, tahbsi2.hmastlock);
gen14 : for i in tahbsi.hsel'range generate
ag14 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hsel(i), hclken, tahbsi2.hsel(i));
end generate;
-- not used by trace buffer:
tahbsi2.hprot <= (others => '0');
tahbsi2.hmbsel <= (others => '0');
tahbsi2.hirq <= (others => '0');
tahbsi2.testen <= '0';
tahbsi2.testrst <= '0';
tahbsi2.scanen <= '0';
tahbsi2.testoen <= '0';
gen15 : for i in hrdata2x'range generate
ag15 : clkand generic map (tech => 0, ren => 0) port map (r.slv.hrdata(i), rh.oen, hrdata2x(i));
end generate;
reg2 : process(hclk)
begin
if rising_edge(hclk) then rh <= rhin; end if;
end process;
end generate;
comb2gen1 : if (clk2x = 0) generate
ahbsi2 <= ahbsi; rh.irq <= '0'; rh.oen <= '0'; hrdata2x <= (others => '0');
tahbsi2 <= tahbsi;
end generate;
reg : process(cpuclk)
begin
if rising_edge(cpuclk) then
r <= rin;
if RESET_ALL and (rst = '0') then
r <= RRES;
for i in 0 to NCPU-1 loop
r.bn(i) <= r.dsubre(2); r.bw(i) <= r.dsubre(2);
r.be(i) <= r.dsubre(2); r.bx(i) <= r.dsubre(2);
r.bz(i) <= r.dsubre(2);
end loop;
r.dsubre <= rin.dsubre; -- Sync. regs.
r.dsuen <= rin.dsuen;
r.en <= rin.en;
end if;
end if;
end process;
tb0 : if TRACEN generate
treg : process(cpuclk)
begin
if rising_edge(cpuclk) then
tr <= trin;
if RESET_ALL and (rst = '0') then tr <= TRES; end if;
end if;
end process;
tpf : if FILTEN generate
pfreg : process(cpuclk)
begin
if rising_edge(cpuclk) then
tfr <= tfrin;
if RESET_ALL and (rst = '0') then tfr <= TFRES; end if;
end if;
end process;
end generate;
perf : if PERFEN generate
preg : process(cpuclk)
begin
if rising_edge(cpuclk) then
pr <= prin;
if RESET_ALL and (rst = '0') then pr <= PRES; end if;
end if;
end process;
end generate;
mem0 : tbufmem
generic map (tech => tech, tbuf => kbytes, dwidth => bwidth, testen => testen)
port map (cpuclk, tbi, tbo, ahbsi.testin
);
-- pragma translate_off
bootmsg : report_version
generic map ("dsu3_" & tost(hindex) &
": LEON3 Debug support unit + AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end generate;
notb : if not TRACEN generate
tbo.data <= (others => '0');
tr <= TRES;
-- pragma translate_off
bootmsg : report_version
generic map ("dsu3_" & tost(hindex) &
": LEON3 Debug support unit");
-- pragma translate_on
end generate;
notpf : if not FILTEN generate
tfr.shsel <= (others => '0');
tfr.pf <= '0';
tfr.af <= '0';
tfr.fr <= '0';
tfr.fw <= '0';
tfr.smask <= (others => '0');
tfr.mmask <= (others => '0');
tfr.bpfilt <= (others => '0');
end generate;
noperf : if not PERFEN generate
pr.stat <= dsu_astat_none;
pr.split <= '0';
pr.splmst <= (others => '0');
pr.hready <= '0';
pr.hresp <= (others => '0');
end generate;
end;
|
-- megafunction wizard: %LPM_MULT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_mult
-- ============================================================
-- File Name: lpm_mult_oe0.vhd
-- Megafunction Name(s):
-- lpm_mult
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_mult_oe0 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (26 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END lpm_mult_oe0;
ARCHITECTURE SYN OF lpm_mult_oe0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT lpm_mult
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_widtha : NATURAL;
lpm_widthb : NATURAL;
lpm_widthp : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (26 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
lpm_mult_component : lpm_mult
GENERIC MAP (
lpm_hint => "MAXIMIZE_SPEED=5",
lpm_representation => "SIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => 27,
lpm_widthb => 5,
lpm_widthp => 32
)
PORT MAP (
dataa => dataa,
datab => datab,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
-- Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedMult NUMERIC "1"
-- Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
-- Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
-- Retrieval info: PRIVATE: WidthA NUMERIC "27"
-- Retrieval info: PRIVATE: WidthB NUMERIC "5"
-- Retrieval info: PRIVATE: WidthP NUMERIC "32"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: optimize NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
-- Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "27"
-- Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "32"
-- Retrieval info: USED_PORT: dataa 0 0 27 0 INPUT NODEFVAL dataa[26..0]
-- Retrieval info: USED_PORT: datab 0 0 5 0 INPUT NODEFVAL datab[4..0]
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
-- Retrieval info: CONNECT: @dataa 0 0 27 0 dataa 0 0 27 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 5 0 datab 0 0 5 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_oe0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_oe0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_oe0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_oe0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_oe0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_oe0_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_oe0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.fqd_pkg.ALL;
ENTITY fqd_rtl_tb IS
END ENTITY fqd_rtl_tb;
ARCHITECTURE sim OF fqd_rtl_tb IS
--Sumulation Parameter:
CONSTANT main_period : TIME := 8 ns; -- 125MHz
CONSTANT velocity : REAL := 20000.0;--500.0; --1/s
CONSTANT direction : INTEGER := 1; -- forwards:1 backwards: -1
CONSTANT enc_tick_per_turn : REAL := 512.0;
CONSTANT wait_time : TIME := (1.0/velocity/enc_tick_per_turn/4.0)*1sec;
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '0';
SIGNAL sl_enc_A : STD_LOGIC := '0';
SIGNAL sl_enc_B : STD_LOGIC := '0';
SIGNAL usig_pos : UNSIGNED(15 DOWNTO 0) := (OTHERS => '0');
BEGIN
--create component
my_unit_under_test : fqd PORT MAP(
isl_clk => sl_clk,
isl_reset_n => sl_reset_n,
isl_enc_A => sl_enc_A,
isl_enc_B => sl_enc_B,
ousig_pos => usig_pos
);
sl_clk <= NOT sl_clk after main_period/2;
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '0';
WAIT FOR 2*main_period;
sl_reset_n <= '1';
WAIT FOR 1000*main_period;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
enc_sim : PROCESS
BEGIN
WHILE TRUE LOOP
IF direction >= 0 THEN
sl_enc_A <= '1';
WAIT FOR wait_time;
sl_enc_B <= '1';
WAIT FOR wait_time;
sl_enc_A <= '0';
WAIT FOR wait_time;
sl_enc_B <= '0';
WAIT FOR wait_time;
ELSE
sl_enc_B <= '1';
WAIT FOR wait_time;
sl_enc_A <= '1';
WAIT FOR wait_time;
sl_enc_B <= '0';
WAIT FOR wait_time;
sl_enc_A <= '0';
WAIT FOR wait_time;
END IF;
END LOOP;
END PROCESS enc_sim;
END ARCHITECTURE sim;
|
-------------------------------------------------------------------------------
-- $Id: brst_addr_cntr.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
-- brst_addr_cntr.vhd - vhdl design file for the entity and architecture
-- of the Mauna Loa IPIF Bus to IPIF Bus Address
-- multiplexer.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: brst_addr_cntr.vhd
--
-- Description: This counter provides the addresses and byte enables during
-- burst operations. It advances based on IP2Bus_addrAck.
-------------------------------------------------------------------------------
-- Structure:
--
--
-- brst_addr_cntr.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
--
-- ALS 11/21/03
-- ~~~~~~
-- Adapted from addr_reg_cntr_brst.vhd
-- ^^^^^^
-- ALS 12/24/03
-- ^^^^^^
-- Removed BE generation from this file
-- ~~~~~~~
-- GAB 04/14/04
-- ^^^^^^
-- Updated to proc_common_v2_00_a
-- ~~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity brst_addr_cntr is
generic (
C_CNTR_WIDTH : integer := 32;
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32
);
port (
-- Inputs
Address_in : in std_logic_vector(0 to C_OPB_AWIDTH-1);
Addr_load : in std_logic;
Addr_CntEn : in std_logic;
Byte_xfer : in std_logic;
Hw_xfer : in std_logic;
Fw_xfer : in std_logic;
-- Address Outputs
Address_Out : out std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_Clk : in std_logic
);
end brst_addr_cntr;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.proc_common_pkg.all;
use opb_v20_v1_10_d.direct_path_cntr_ai;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
architecture implementation of brst_addr_cntr is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-- Function set_cntr_width sets the counter width to generic C_CNTR_WIDTH if
-- it is >= 3, otherwise, the counter width is set to 3. This is due to the
-- fact that for OPB addresses, the counter must at least be of width 3 in order
-- to count byte, half-word, and word addresses
function set_cntr_width ( input_cntr_width : integer)
return integer is
begin
if input_cntr_width >= 3 then
return input_cntr_width;
else
return 3;
end if;
end function set_cntr_width;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CNTR_WIDTH : integer := set_cntr_width(C_CNTR_WIDTH);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal address_out_i : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal xfer_size : std_logic_vector(0 to CNTR_WIDTH-1);
signal addr_load_n : std_logic;
signal address_cnt : std_logic_vector(0 to CNTR_WIDTH-1);
-------------------------------------------------------------------------------
begin
-- Output assignments
Address_out <= address_out_i;
-----------------------------------------------------------------------
-- Determine the transfer size
ZERO_XFER_SIZE_GEN: if CNTR_WIDTH > 3 generate
xfer_size(0 to CNTR_WIDTH-4) <= (others => '0');
end generate ZERO_XFER_SIZE_GEN;
xfer_size(CNTR_WIDTH-3 to CNTR_WIDTH-1) <= Fw_xfer & Hw_xfer & Byte_xfer;
-------------------------------------------------------------------------------
-- Address Counter
--
-- Use the direct path counter so a clock delay is not incurred when the address
-- is loaded. Based on the xfer size, increment the counter by 1 ,2 , or 4
-------------------------------------------------------------------------------
addr_load_n <= not(Addr_load);
DIRECT_PATH_CNTR_I: entity opb_v20_v1_10_d.direct_path_cntr_ai
generic map (C_WIDTH => CNTR_WIDTH)
port map (
Clk => OPB_Clk,
Din => Address_in(C_OPB_AWIDTH-CNTR_WIDTH to C_OPB_AWIDTH-1),
Dout => address_cnt,
Load_n => addr_load_n,
Cnt_en => Addr_CntEn,
Delta => xfer_size
);
address_out_i <= address_in(0 to C_OPB_AWIDTH-CNTR_WIDTH-1) & address_cnt;
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: brst_addr_cntr.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
-- brst_addr_cntr.vhd - vhdl design file for the entity and architecture
-- of the Mauna Loa IPIF Bus to IPIF Bus Address
-- multiplexer.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: brst_addr_cntr.vhd
--
-- Description: This counter provides the addresses and byte enables during
-- burst operations. It advances based on IP2Bus_addrAck.
-------------------------------------------------------------------------------
-- Structure:
--
--
-- brst_addr_cntr.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
--
-- ALS 11/21/03
-- ~~~~~~
-- Adapted from addr_reg_cntr_brst.vhd
-- ^^^^^^
-- ALS 12/24/03
-- ^^^^^^
-- Removed BE generation from this file
-- ~~~~~~~
-- GAB 04/14/04
-- ^^^^^^
-- Updated to proc_common_v2_00_a
-- ~~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity brst_addr_cntr is
generic (
C_CNTR_WIDTH : integer := 32;
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32
);
port (
-- Inputs
Address_in : in std_logic_vector(0 to C_OPB_AWIDTH-1);
Addr_load : in std_logic;
Addr_CntEn : in std_logic;
Byte_xfer : in std_logic;
Hw_xfer : in std_logic;
Fw_xfer : in std_logic;
-- Address Outputs
Address_Out : out std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_Clk : in std_logic
);
end brst_addr_cntr;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.proc_common_pkg.all;
use opb_v20_v1_10_d.direct_path_cntr_ai;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
architecture implementation of brst_addr_cntr is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-- Function set_cntr_width sets the counter width to generic C_CNTR_WIDTH if
-- it is >= 3, otherwise, the counter width is set to 3. This is due to the
-- fact that for OPB addresses, the counter must at least be of width 3 in order
-- to count byte, half-word, and word addresses
function set_cntr_width ( input_cntr_width : integer)
return integer is
begin
if input_cntr_width >= 3 then
return input_cntr_width;
else
return 3;
end if;
end function set_cntr_width;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CNTR_WIDTH : integer := set_cntr_width(C_CNTR_WIDTH);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal address_out_i : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal xfer_size : std_logic_vector(0 to CNTR_WIDTH-1);
signal addr_load_n : std_logic;
signal address_cnt : std_logic_vector(0 to CNTR_WIDTH-1);
-------------------------------------------------------------------------------
begin
-- Output assignments
Address_out <= address_out_i;
-----------------------------------------------------------------------
-- Determine the transfer size
ZERO_XFER_SIZE_GEN: if CNTR_WIDTH > 3 generate
xfer_size(0 to CNTR_WIDTH-4) <= (others => '0');
end generate ZERO_XFER_SIZE_GEN;
xfer_size(CNTR_WIDTH-3 to CNTR_WIDTH-1) <= Fw_xfer & Hw_xfer & Byte_xfer;
-------------------------------------------------------------------------------
-- Address Counter
--
-- Use the direct path counter so a clock delay is not incurred when the address
-- is loaded. Based on the xfer size, increment the counter by 1 ,2 , or 4
-------------------------------------------------------------------------------
addr_load_n <= not(Addr_load);
DIRECT_PATH_CNTR_I: entity opb_v20_v1_10_d.direct_path_cntr_ai
generic map (C_WIDTH => CNTR_WIDTH)
port map (
Clk => OPB_Clk,
Din => Address_in(C_OPB_AWIDTH-CNTR_WIDTH to C_OPB_AWIDTH-1),
Dout => address_cnt,
Load_n => addr_load_n,
Cnt_en => Addr_CntEn,
Delta => xfer_size
);
address_out_i <= address_in(0 to C_OPB_AWIDTH-CNTR_WIDTH-1) & address_cnt;
end implementation;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_3_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_3_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_3_tb IS
END ENTITY;
ARCHITECTURE system_axi_dma_0_wrapper_fifo_generator_v9_3_3_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_3_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth
system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth_inst:system_axi_dma_0_wrapper_fifo_generator_v9_3_3_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 41
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0;
USE dist_mem_gen_v8_0.dist_mem_gen_v8_0;
ENTITY AST_ROM IS
PORT (
a : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END AST_ROM;
ARCHITECTURE AST_ROM_arch OF AST_ROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF AST_ROM_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF AST_ROM_arch: ARCHITECTURE IS "dist_mem_gen_v8_0,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF AST_ROM_arch : ARCHITECTURE IS "AST_ROM,dist_mem_gen_v8_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF AST_ROM_arch: ARCHITECTURE IS "AST_ROM,dist_mem_gen_v8_0,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_ADDR_WIDTH=14,C_DEFAULT_DATA=0,C_DEPTH=16384,C_HAS_CLK=0,C_HAS_D=0,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=0,C_MEM_INIT_FILE=AST_ROM.mif,C_ELABORATION_DIR=./,C_MEM_TYPE=0,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=1,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=8,C_PARSER_TYPE=1}";
BEGIN
U0 : dist_mem_gen_v8_0
GENERIC MAP (
C_FAMILY => "zynq",
C_ADDR_WIDTH => 14,
C_DEFAULT_DATA => "0",
C_DEPTH => 16384,
C_HAS_CLK => 0,
C_HAS_D => 0,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 0,
C_MEM_INIT_FILE => "AST_ROM.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 0,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 8,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
clk => '0',
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END AST_ROM_arch;
|
------------------------------------------------------------------------------
-- faultify_axi_wrapper.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: faultify_axi_wrapper.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Fri May 16 15:25:24 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library faultify_axi_wrapper_v1_00_a;
use faultify_axi_wrapper_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity faultify_axi_wrapper is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
numInj : integer := 178;
numIn : integer := 69;
numOut : integer := 5;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
faultify_clk_fast : in std_logic;
faultify_clk_slow_out : out std_logic;
s_axis_aresetn : in std_logic;
s_axis_input_tvalid : in std_logic;
s_axis_input_tdata : in std_logic_vector(31 downto 0);
s_axis_input_tlast : in std_logic;
s_axis_input_tready : out std_logic;
m_axis_output_tvalid : out std_logic;
m_axis_output_tdata : out std_logic_vector(31 downto 0);
m_axis_output_tlast : out std_logic;
m_axis_output_tready : in std_logic;
s_axis_ctrl_tvalid : in std_logic;
s_axis_ctrl_tdata : in std_logic_vector(31 downto 0);
s_axis_ctrl_tlast : in std_logic;
s_axis_ctrl_tready : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity faultify_axi_wrapper;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of faultify_axi_wrapper is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR, -- soft reset space high address
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant RST_NUM_CE : integer := 1;
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG + RST_NUM_CE;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (RST_NUM_CE), -- number of ce for soft reset space
1 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 8;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant RST_CS_INDEX : integer := 0;
constant RST_CE_INDEX : integer := USER_NUM_REG;
constant USER_SLV_CS_INDEX : integer := 1;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_Bus2IP_Reset : std_logic;
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal rst_Bus2IP_Reset_tmp : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal testvector : std_logic_vector(numIn-1 downto 0);
signal resultvector_o : std_logic_vector(numOut-1 downto 0);
signal resultvector_f : std_logic_vector(numOut-1 downto 0);
begin
testvector(0) <= s_axis_input_tvalid;
testvector(32 downto 1) <= s_axis_input_tdata;
testvector(33) <= s_axis_input_tlast;
s_axis_input_tready <= resultvector_o(0);
m_axis_output_tvalid <= resultvector_o(1);
m_axis_output_tdata(0) <= resultvector_o(2);
m_axis_output_tdata(1) <= resultvector_f(2);
m_axis_output_tdata(31 downto 2) <= (others => '0');
m_axis_output_tlast <= resultvector_o(3);
testvector(34) <= m_axis_output_tready;
testvector(35) <= s_axis_ctrl_tvalid;
testvector(67 downto 36) <= s_axis_ctrl_tdata;
testvector(68) <= s_axis_ctrl_tlast;
s_axis_ctrl_tready <= resultvector_o(4);
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity faultify_axi_wrapper_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
numInj => numInj,
numIn => numIn,
numOut => numOut,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
faultify_clk_fast => faultify_clk_fast,
faultify_clk_slow_out => faultify_clk_slow_out,
s_axis_aresetn => s_axis_aresetn,
resultvector_o => resultvector_o,
resultvector_f => resultvector_f,
testvector => testvector,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => rst_Bus2IP_Reset_tmp,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process(ipif_Bus2IP_CS, user_IP2Bus_Data) is
begin
case ipif_Bus2IP_CS (1 downto 0) is
when "01" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "10" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
ipif_Bus2IP_Reset <= not ipif_Bus2IP_Resetn;
rst_Bus2IP_Reset_tmp <= not rst_Bus2IP_Reset;
end IMP;
|
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from fp_addsub
-- VHDL created on Thu Feb 15 14:11:38 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_addsub is
port (
a : in std_logic_vector(31 downto 0); -- float32_m23
b : in std_logic_vector(31 downto 0); -- float32_m23
q : out std_logic_vector(31 downto 0); -- float32_m23
s : out std_logic_vector(31 downto 0); -- float32_m23
clk : in std_logic;
areset : in std_logic
);
end fp_addsub;
architecture normal of fp_addsub is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal expFracX_uid6_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (30 downto 0);
signal expFracY_uid7_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (30 downto 0);
signal xGTEy_uid8_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (32 downto 0);
signal xGTEy_uid8_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (32 downto 0);
signal xGTEy_uid8_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (32 downto 0);
signal xGTEy_uid8_fpFusedAddSubTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal siga_uid9_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal siga_uid9_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal sigb_uid10_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal sigb_uid10_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal cstAllOWE_uid11_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cstZeroWF_uid12_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal cstAllZWE_uid13_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal exp_siga_uid14_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (30 downto 0);
signal exp_siga_uid14_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal frac_siga_uid15_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (22 downto 0);
signal frac_siga_uid15_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_siga_uid9_uid16_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid17_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid18_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid19_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_siga_uid20_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_siga_uid21_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid22_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid23_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_siga_uid24_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal exp_sigb_uid28_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (30 downto 0);
signal exp_sigb_uid28_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal frac_sigb_uid29_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (22 downto 0);
signal frac_sigb_uid29_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_sigb_uid10_uid30_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid31_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid32_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid33_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_sigb_uid34_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_sigb_uid35_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid36_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid37_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_sigb_uid38_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sigA_uid43_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal sigB_uid44_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal effSub_uid45_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expAmExpB_uid48_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (8 downto 0);
signal expAmExpB_uid48_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal expAmExpB_uid48_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (8 downto 0);
signal expAmExpB_uid48_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal cWFP1_uid49_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal shiftedOut_uid51_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (10 downto 0);
signal shiftedOut_uid51_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (10 downto 0);
signal shiftedOut_uid51_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (10 downto 0);
signal shiftedOut_uid51_fpFusedAddSubTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal shiftOutConst_uid52_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal expAmExpBShiftRange_uid53_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (4 downto 0);
signal expAmExpBShiftRange_uid53_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal shiftValue_uid54_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal shiftValue_uid54_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal oFracB_uid56_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal oFracA_uid57_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal oFracBR_uid58_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal fracAOp_uid61_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal fracBOp_uid62_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (26 downto 0);
signal fracResSub_uid63_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (27 downto 0);
signal fracResSub_uid63_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (27 downto 0);
signal fracResSub_uid63_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (27 downto 0);
signal fracResSub_uid63_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal fracResAdd_uid64_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (27 downto 0);
signal fracResAdd_uid64_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (27 downto 0);
signal fracResAdd_uid64_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (27 downto 0);
signal fracResAdd_uid64_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (27 downto 0);
signal fracResSubNoSignExt_uid65_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (25 downto 0);
signal fracResSubNoSignExt_uid65_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (25 downto 0);
signal fracResAddNoSignExt_uid66_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (25 downto 0);
signal fracResAddNoSignExt_uid66_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (25 downto 0);
signal cAmA_uid71_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal aMinusA_uid72_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expInc_uid73_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (8 downto 0);
signal expInc_uid73_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal expInc_uid73_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (8 downto 0);
signal expInc_uid73_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal expPostNormSub_uid74_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNormSub_uid74_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNormSub_uid74_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNormSub_uid74_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNormAdd_uid75_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNormAdd_uid75_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNormAdd_uid75_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (9 downto 0);
signal expPostNormAdd_uid75_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal fracPostNormSubRndRange_uid76_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (24 downto 0);
signal fracPostNormSubRndRange_uid76_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal expFracRSub_uid77_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (33 downto 0);
signal fracPostNormAddRndRange_uid78_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (24 downto 0);
signal fracPostNormAddRndRange_uid78_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal expFracRAdd_uid79_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (33 downto 0);
signal wEP2AllOwE_uid80_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal rndExp_uid81_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal rOvf_uid82_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signedExp_uid83_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal rUdf_uid84_fpFusedAddSubTest_a : STD_LOGIC_VECTOR (11 downto 0);
signal rUdf_uid84_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (11 downto 0);
signal rUdf_uid84_fpFusedAddSubTest_o : STD_LOGIC_VECTOR (11 downto 0);
signal rUdf_uid84_fpFusedAddSubTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPreExcSub_uid85_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPreExcSub_uid85_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal expRPreExcSub_uid86_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal expRPreExcSub_uid86_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal fracRPreExcAdd_uid88_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPreExcAdd_uid88_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal expRPreExcAdd_uid89_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal expRPreExcAdd_uid89_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal regInputs_uid91_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRZeroVInC_uid92_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (5 downto 0);
signal excRZeroAdd_uid93_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRZeroSub_uid94_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal regInAndOvf_uid95_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal oneIsInf_uid96_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal oneIsInfOrZero_uid97_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal addIsAlsoInf_uid98_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRInfVInC_uid99_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (5 downto 0);
signal excRInfAdd_uid100_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRInfAddFull_uid101_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRInfSub_uid102_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRInfSubFull_uid103_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal infMinf_uid104_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaNA_uid105_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invEffSub_uid106_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal infPinfForSub_uid107_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaNS_uid108_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal concExcSub_uid109_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal concExcAdd_uid110_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal excREncSub_uid111_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal excREncAdd_uid112_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPreExcAddition_uid113_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPreExcAddition_uid113_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPreExcAddition_uid114_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal expRPreExcAddition_uid114_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal fracRPreExcSubtraction_uid115_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPreExcSubtraction_uid115_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPreExcSubtraction_uid116_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal expRPreExcSubtraction_uid116_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal oneFracRPostExc2_uid117_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal fracRPostExcAdd_uid120_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPostExcAdd_uid120_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPostExcAdd_uid124_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal expRPostExcAdd_uid124_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal invXGTEy_uid125_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invSigA_uid126_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signInputsZeroSwap_uid127_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invSignInputsZeroSwap_uid128_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invSigB_uid129_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signInputsZeroNoSwap_uid130_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invSignInputsZeroNoSwap_uid131_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal aMa_uid132_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invAMA_uid133_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExcRNaNA_uid134_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signRPostExc_uid135_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal RSum_uid136_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal fracRPostExcSub_uid140_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPostExcSub_uid140_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPostExcSub_uid144_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal expRPostExcSub_uid144_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal positiveExc_uid145_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invPositiveExc_uid146_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signInputsZeroForSub_uid147_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invSignInputsZeroForSub_uid148_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sigY_uid149_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal invSigY_uid150_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal yGTxYPos_uid152_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sigX_uid153_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal xGTyXNeg_uid154_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signRPostExcSub0_uid155_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExcRNaNS_uid156_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signRPostExcSub_uid157_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal RDiff_uid158_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (15 downto 0);
signal rVStage_uid162_lzCountValSub_uid67_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (15 downto 0);
signal vCount_uid163_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal mO_uid164_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (5 downto 0);
signal vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (9 downto 0);
signal vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal cStage_uid166_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (15 downto 0);
signal vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (15 downto 0);
signal vCount_uid171_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal vCount_uid177_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal vCount_uid183_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal rVStage_uid188_lzCountValSub_uid67_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal vCount_uid189_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal r_uid190_lzCountValSub_uid67_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal rVStage_uid193_lzCountValAdd_uid69_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (15 downto 0);
signal vCount_uid194_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (9 downto 0);
signal vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (9 downto 0);
signal cStage_uid197_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (15 downto 0);
signal vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (15 downto 0);
signal vCount_uid202_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal vCount_uid208_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal vCount_uid214_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal rVStage_uid219_lzCountValAdd_uid69_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal vCount_uid220_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal r_uid221_lzCountValAdd_uid69_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (4 downto 0);
signal rightShiftStage0Idx1Rng4_uid225_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (20 downto 0);
signal rightShiftStage0Idx1_uid227_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0Idx2Rng8_uid228_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (16 downto 0);
signal rightShiftStage0Idx2_uid230_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0Idx3Rng12_uid231_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (12 downto 0);
signal rightShiftStage0Idx3Pad12_uid232_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (11 downto 0);
signal rightShiftStage0Idx3_uid233_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0Idx4Rng16_uid234_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal rightShiftStage0Idx4_uid236_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0Idx5Rng20_uid237_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal rightShiftStage0Idx5Pad20_uid238_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (19 downto 0);
signal rightShiftStage0Idx5_uid239_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0Idx6Rng24_uid240_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal rightShiftStage0Idx6Pad24_uid241_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal rightShiftStage0Idx6_uid242_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0Idx7_uid243_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage1Idx1Rng1_uid246_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal rightShiftStage1Idx1_uid248_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage1Idx2Rng2_uid249_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal rightShiftStage1Idx2_uid251_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage1Idx3Rng3_uid252_alignmentShifter_uid59_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (21 downto 0);
signal rightShiftStage1Idx3Pad3_uid253_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal rightShiftStage1Idx3_uid254_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal leftShiftStage0Idx1Rng4_uid261_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (21 downto 0);
signal leftShiftStage0Idx1Rng4_uid261_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (21 downto 0);
signal leftShiftStage0Idx1_uid262_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx2Rng8_uid264_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (17 downto 0);
signal leftShiftStage0Idx2Rng8_uid264_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal leftShiftStage0Idx2_uid265_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx3Rng12_uid267_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (13 downto 0);
signal leftShiftStage0Idx3Rng12_uid267_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal leftShiftStage0Idx3_uid268_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx4_uid271_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx5Rng20_uid273_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal leftShiftStage0Idx5Rng20_uid273_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (5 downto 0);
signal leftShiftStage0Idx5_uid274_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx6Rng24_uid276_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0Idx6Rng24_uid276_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0Idx6_uid277_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx7_uid278_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1Idx1Rng1_uid282_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (24 downto 0);
signal leftShiftStage1Idx1Rng1_uid282_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (24 downto 0);
signal leftShiftStage1Idx1_uid283_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1Idx2Rng2_uid285_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal leftShiftStage1Idx2Rng2_uid285_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal leftShiftStage1Idx2_uid286_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1Idx3Rng3_uid288_fracPostNormSub_uid68_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (22 downto 0);
signal leftShiftStage1Idx3Rng3_uid288_fracPostNormSub_uid68_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal leftShiftStage1Idx3_uid289_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx1Rng4_uid296_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (21 downto 0);
signal leftShiftStage0Idx1Rng4_uid296_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (21 downto 0);
signal leftShiftStage0Idx1_uid297_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx2Rng8_uid299_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (17 downto 0);
signal leftShiftStage0Idx2Rng8_uid299_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal leftShiftStage0Idx2_uid300_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx3Rng12_uid302_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (13 downto 0);
signal leftShiftStage0Idx3Rng12_uid302_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal leftShiftStage0Idx3_uid303_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx4_uid306_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx5Rng20_uid308_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal leftShiftStage0Idx5Rng20_uid308_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (5 downto 0);
signal leftShiftStage0Idx5_uid309_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0Idx6Rng24_uid311_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0Idx6Rng24_uid311_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0Idx6_uid312_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1Idx1Rng1_uid317_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (24 downto 0);
signal leftShiftStage1Idx1Rng1_uid317_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (24 downto 0);
signal leftShiftStage1Idx1_uid318_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1Idx2Rng2_uid320_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal leftShiftStage1Idx2Rng2_uid320_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal leftShiftStage1Idx2_uid321_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1Idx3Rng3_uid323_fracPostNormAdd_uid70_fpFusedAddSubTest_in : STD_LOGIC_VECTOR (22 downto 0);
signal leftShiftStage1Idx3Rng3_uid323_fracPostNormAdd_uid70_fpFusedAddSubTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal leftShiftStage1Idx3_uid324_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_s : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_s : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q : STD_LOGIC_VECTOR (24 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_s : STD_LOGIC_VECTOR (0 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q : STD_LOGIC_VECTOR (24 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_s : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_s : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_s : STD_LOGIC_VECTOR (0 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_s : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_s : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q : STD_LOGIC_VECTOR (25 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_s : STD_LOGIC_VECTOR (0 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q : STD_LOGIC_VECTOR (25 downto 0);
signal rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (2 downto 0);
signal rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0);
signal rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (7 downto 0);
signal rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (7 downto 0);
signal rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (3 downto 0);
signal rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (3 downto 0);
signal rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0);
signal rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (2 downto 0);
signal leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0);
signal rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (7 downto 0);
signal rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (7 downto 0);
signal rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (3 downto 0);
signal rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (3 downto 0);
signal rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0);
signal rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select_b : STD_LOGIC_VECTOR (2 downto 0);
signal leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select_c : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0);
signal rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select_c : STD_LOGIC_VECTOR (0 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select_c : STD_LOGIC_VECTOR (0 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select_b : STD_LOGIC_VECTOR (1 downto 0);
signal leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select_c : STD_LOGIC_VECTOR (0 downto 0);
signal redist0_xIn_a_1_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist1_xIn_b_1_q : STD_LOGIC_VECTOR (31 downto 0);
begin
-- redist1_xIn_b_1(DELAY,355)
redist1_xIn_b_1 : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => b, xout => redist1_xIn_b_1_q, clk => clk, aclr => areset );
-- redist0_xIn_a_1(DELAY,354)
redist0_xIn_a_1 : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => a, xout => redist0_xIn_a_1_q, clk => clk, aclr => areset );
-- GND(CONSTANT,0)
GND_q <= "0";
-- expFracY_uid7_fpFusedAddSubTest(BITSELECT,6)@0
expFracY_uid7_fpFusedAddSubTest_b <= b(30 downto 0);
-- expFracX_uid6_fpFusedAddSubTest(BITSELECT,5)@0
expFracX_uid6_fpFusedAddSubTest_b <= a(30 downto 0);
-- xGTEy_uid8_fpFusedAddSubTest(COMPARE,7)@0 + 1
xGTEy_uid8_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("00" & expFracX_uid6_fpFusedAddSubTest_b);
xGTEy_uid8_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("00" & expFracY_uid7_fpFusedAddSubTest_b);
xGTEy_uid8_fpFusedAddSubTest_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xGTEy_uid8_fpFusedAddSubTest_o <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
xGTEy_uid8_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xGTEy_uid8_fpFusedAddSubTest_a) - UNSIGNED(xGTEy_uid8_fpFusedAddSubTest_b));
END IF;
END PROCESS;
xGTEy_uid8_fpFusedAddSubTest_n(0) <= not (xGTEy_uid8_fpFusedAddSubTest_o(32));
-- sigb_uid10_fpFusedAddSubTest(MUX,9)@1
sigb_uid10_fpFusedAddSubTest_s <= xGTEy_uid8_fpFusedAddSubTest_n;
sigb_uid10_fpFusedAddSubTest_combproc: PROCESS (sigb_uid10_fpFusedAddSubTest_s, redist0_xIn_a_1_q, redist1_xIn_b_1_q)
BEGIN
CASE (sigb_uid10_fpFusedAddSubTest_s) IS
WHEN "0" => sigb_uid10_fpFusedAddSubTest_q <= redist0_xIn_a_1_q;
WHEN "1" => sigb_uid10_fpFusedAddSubTest_q <= redist1_xIn_b_1_q;
WHEN OTHERS => sigb_uid10_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- sigB_uid44_fpFusedAddSubTest(BITSELECT,43)@1
sigB_uid44_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR(sigb_uid10_fpFusedAddSubTest_q(31 downto 31));
-- siga_uid9_fpFusedAddSubTest(MUX,8)@1
siga_uid9_fpFusedAddSubTest_s <= xGTEy_uid8_fpFusedAddSubTest_n;
siga_uid9_fpFusedAddSubTest_combproc: PROCESS (siga_uid9_fpFusedAddSubTest_s, redist1_xIn_b_1_q, redist0_xIn_a_1_q)
BEGIN
CASE (siga_uid9_fpFusedAddSubTest_s) IS
WHEN "0" => siga_uid9_fpFusedAddSubTest_q <= redist1_xIn_b_1_q;
WHEN "1" => siga_uid9_fpFusedAddSubTest_q <= redist0_xIn_a_1_q;
WHEN OTHERS => siga_uid9_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- sigA_uid43_fpFusedAddSubTest(BITSELECT,42)@1
sigA_uid43_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR(siga_uid9_fpFusedAddSubTest_q(31 downto 31));
-- cAmA_uid71_fpFusedAddSubTest(CONSTANT,70)
cAmA_uid71_fpFusedAddSubTest_q <= "11010";
-- zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest(CONSTANT,160)
zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest_q <= "0000000000000000";
-- rightShiftStage1Idx3Pad3_uid253_alignmentShifter_uid59_fpFusedAddSubTest(CONSTANT,252)
rightShiftStage1Idx3Pad3_uid253_alignmentShifter_uid59_fpFusedAddSubTest_q <= "000";
-- rightShiftStage1Idx3Rng3_uid252_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,251)@1
rightShiftStage1Idx3Rng3_uid252_alignmentShifter_uid59_fpFusedAddSubTest_b <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q(24 downto 3);
-- rightShiftStage1Idx3_uid254_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,253)@1
rightShiftStage1Idx3_uid254_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage1Idx3Pad3_uid253_alignmentShifter_uid59_fpFusedAddSubTest_q & rightShiftStage1Idx3Rng3_uid252_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest(CONSTANT,180)
zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest_q <= "00";
-- rightShiftStage1Idx2Rng2_uid249_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,248)@1
rightShiftStage1Idx2Rng2_uid249_alignmentShifter_uid59_fpFusedAddSubTest_b <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q(24 downto 2);
-- rightShiftStage1Idx2_uid251_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,250)@1
rightShiftStage1Idx2_uid251_alignmentShifter_uid59_fpFusedAddSubTest_q <= zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest_q & rightShiftStage1Idx2Rng2_uid249_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- rightShiftStage1Idx1Rng1_uid246_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,245)@1
rightShiftStage1Idx1Rng1_uid246_alignmentShifter_uid59_fpFusedAddSubTest_b <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q(24 downto 1);
-- rightShiftStage1Idx1_uid248_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,247)@1
rightShiftStage1Idx1_uid248_alignmentShifter_uid59_fpFusedAddSubTest_q <= GND_q & rightShiftStage1Idx1Rng1_uid246_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- rightShiftStage0Idx7_uid243_alignmentShifter_uid59_fpFusedAddSubTest(CONSTANT,242)
rightShiftStage0Idx7_uid243_alignmentShifter_uid59_fpFusedAddSubTest_q <= "0000000000000000000000000";
-- rightShiftStage0Idx6Pad24_uid241_alignmentShifter_uid59_fpFusedAddSubTest(CONSTANT,240)
rightShiftStage0Idx6Pad24_uid241_alignmentShifter_uid59_fpFusedAddSubTest_q <= "000000000000000000000000";
-- cstAllZWE_uid13_fpFusedAddSubTest(CONSTANT,12)
cstAllZWE_uid13_fpFusedAddSubTest_q <= "00000000";
-- exp_sigb_uid28_fpFusedAddSubTest(BITSELECT,27)@1
exp_sigb_uid28_fpFusedAddSubTest_in <= sigb_uid10_fpFusedAddSubTest_q(30 downto 0);
exp_sigb_uid28_fpFusedAddSubTest_b <= exp_sigb_uid28_fpFusedAddSubTest_in(30 downto 23);
-- excZ_sigb_uid10_uid30_fpFusedAddSubTest(LOGICAL,29)@1
excZ_sigb_uid10_uid30_fpFusedAddSubTest_q <= "1" WHEN exp_sigb_uid28_fpFusedAddSubTest_b = cstAllZWE_uid13_fpFusedAddSubTest_q ELSE "0";
-- InvExpXIsZero_uid37_fpFusedAddSubTest(LOGICAL,36)@1
InvExpXIsZero_uid37_fpFusedAddSubTest_q <= not (excZ_sigb_uid10_uid30_fpFusedAddSubTest_q);
-- frac_sigb_uid29_fpFusedAddSubTest(BITSELECT,28)@1
frac_sigb_uid29_fpFusedAddSubTest_in <= sigb_uid10_fpFusedAddSubTest_q(22 downto 0);
frac_sigb_uid29_fpFusedAddSubTest_b <= frac_sigb_uid29_fpFusedAddSubTest_in(22 downto 0);
-- oFracB_uid56_fpFusedAddSubTest(BITJOIN,55)@1
oFracB_uid56_fpFusedAddSubTest_q <= InvExpXIsZero_uid37_fpFusedAddSubTest_q & frac_sigb_uid29_fpFusedAddSubTest_b;
-- oFracBR_uid58_fpFusedAddSubTest(BITJOIN,57)@1
oFracBR_uid58_fpFusedAddSubTest_q <= oFracB_uid56_fpFusedAddSubTest_q & GND_q;
-- rightShiftStage0Idx6Rng24_uid240_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,239)@1
rightShiftStage0Idx6Rng24_uid240_alignmentShifter_uid59_fpFusedAddSubTest_b <= oFracBR_uid58_fpFusedAddSubTest_q(24 downto 24);
-- rightShiftStage0Idx6_uid242_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,241)@1
rightShiftStage0Idx6_uid242_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage0Idx6Pad24_uid241_alignmentShifter_uid59_fpFusedAddSubTest_q & rightShiftStage0Idx6Rng24_uid240_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- rightShiftStage0Idx5Pad20_uid238_alignmentShifter_uid59_fpFusedAddSubTest(CONSTANT,237)
rightShiftStage0Idx5Pad20_uid238_alignmentShifter_uid59_fpFusedAddSubTest_q <= "00000000000000000000";
-- rightShiftStage0Idx5Rng20_uid237_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,236)@1
rightShiftStage0Idx5Rng20_uid237_alignmentShifter_uid59_fpFusedAddSubTest_b <= oFracBR_uid58_fpFusedAddSubTest_q(24 downto 20);
-- rightShiftStage0Idx5_uid239_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,238)@1
rightShiftStage0Idx5_uid239_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage0Idx5Pad20_uid238_alignmentShifter_uid59_fpFusedAddSubTest_q & rightShiftStage0Idx5Rng20_uid237_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- rightShiftStage0Idx4Rng16_uid234_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,233)@1
rightShiftStage0Idx4Rng16_uid234_alignmentShifter_uid59_fpFusedAddSubTest_b <= oFracBR_uid58_fpFusedAddSubTest_q(24 downto 16);
-- rightShiftStage0Idx4_uid236_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,235)@1
rightShiftStage0Idx4_uid236_alignmentShifter_uid59_fpFusedAddSubTest_q <= zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest_q & rightShiftStage0Idx4Rng16_uid234_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1(MUX,330)@1
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_s <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select_b;
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_combproc: PROCESS (rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_s, rightShiftStage0Idx4_uid236_alignmentShifter_uid59_fpFusedAddSubTest_q, rightShiftStage0Idx5_uid239_alignmentShifter_uid59_fpFusedAddSubTest_q, rightShiftStage0Idx6_uid242_alignmentShifter_uid59_fpFusedAddSubTest_q, rightShiftStage0Idx7_uid243_alignmentShifter_uid59_fpFusedAddSubTest_q)
BEGIN
CASE (rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_s) IS
WHEN "00" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q <= rightShiftStage0Idx4_uid236_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN "01" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q <= rightShiftStage0Idx5_uid239_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN "10" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q <= rightShiftStage0Idx6_uid242_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN "11" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q <= rightShiftStage0Idx7_uid243_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN OTHERS => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q <= (others => '0');
END CASE;
END PROCESS;
-- rightShiftStage0Idx3Pad12_uid232_alignmentShifter_uid59_fpFusedAddSubTest(CONSTANT,231)
rightShiftStage0Idx3Pad12_uid232_alignmentShifter_uid59_fpFusedAddSubTest_q <= "000000000000";
-- rightShiftStage0Idx3Rng12_uid231_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,230)@1
rightShiftStage0Idx3Rng12_uid231_alignmentShifter_uid59_fpFusedAddSubTest_b <= oFracBR_uid58_fpFusedAddSubTest_q(24 downto 12);
-- rightShiftStage0Idx3_uid233_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,232)@1
rightShiftStage0Idx3_uid233_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage0Idx3Pad12_uid232_alignmentShifter_uid59_fpFusedAddSubTest_q & rightShiftStage0Idx3Rng12_uid231_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- rightShiftStage0Idx2Rng8_uid228_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,227)@1
rightShiftStage0Idx2Rng8_uid228_alignmentShifter_uid59_fpFusedAddSubTest_b <= oFracBR_uid58_fpFusedAddSubTest_q(24 downto 8);
-- rightShiftStage0Idx2_uid230_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,229)@1
rightShiftStage0Idx2_uid230_alignmentShifter_uid59_fpFusedAddSubTest_q <= cstAllZWE_uid13_fpFusedAddSubTest_q & rightShiftStage0Idx2Rng8_uid228_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest(CONSTANT,174)
zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest_q <= "0000";
-- rightShiftStage0Idx1Rng4_uid225_alignmentShifter_uid59_fpFusedAddSubTest(BITSELECT,224)@1
rightShiftStage0Idx1Rng4_uid225_alignmentShifter_uid59_fpFusedAddSubTest_b <= oFracBR_uid58_fpFusedAddSubTest_q(24 downto 4);
-- rightShiftStage0Idx1_uid227_alignmentShifter_uid59_fpFusedAddSubTest(BITJOIN,226)@1
rightShiftStage0Idx1_uid227_alignmentShifter_uid59_fpFusedAddSubTest_q <= zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest_q & rightShiftStage0Idx1Rng4_uid225_alignmentShifter_uid59_fpFusedAddSubTest_b;
-- rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0(MUX,329)@1
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_s <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select_b;
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_combproc: PROCESS (rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_s, oFracBR_uid58_fpFusedAddSubTest_q, rightShiftStage0Idx1_uid227_alignmentShifter_uid59_fpFusedAddSubTest_q, rightShiftStage0Idx2_uid230_alignmentShifter_uid59_fpFusedAddSubTest_q, rightShiftStage0Idx3_uid233_alignmentShifter_uid59_fpFusedAddSubTest_q)
BEGIN
CASE (rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_s) IS
WHEN "00" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q <= oFracBR_uid58_fpFusedAddSubTest_q;
WHEN "01" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q <= rightShiftStage0Idx1_uid227_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN "10" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q <= rightShiftStage0Idx2_uid230_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN "11" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q <= rightShiftStage0Idx3_uid233_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN OTHERS => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q <= (others => '0');
END CASE;
END PROCESS;
-- rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select(BITSELECT,351)@1
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select_b <= rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select_b(1 downto 0);
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select_c <= rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select_b(2 downto 2);
-- rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal(MUX,331)@1
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_s <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_selLSBs_merged_bit_select_c;
rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_combproc: PROCESS (rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_s, rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q, rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q)
BEGIN
CASE (rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_s) IS
WHEN "0" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_0_q;
WHEN "1" => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_msplit_1_q;
WHEN OTHERS => rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q <= (others => '0');
END CASE;
END PROCESS;
-- shiftOutConst_uid52_fpFusedAddSubTest(CONSTANT,51)
shiftOutConst_uid52_fpFusedAddSubTest_q <= "11001";
-- exp_siga_uid14_fpFusedAddSubTest(BITSELECT,13)@1
exp_siga_uid14_fpFusedAddSubTest_in <= siga_uid9_fpFusedAddSubTest_q(30 downto 0);
exp_siga_uid14_fpFusedAddSubTest_b <= exp_siga_uid14_fpFusedAddSubTest_in(30 downto 23);
-- expAmExpB_uid48_fpFusedAddSubTest(SUB,47)@1
expAmExpB_uid48_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("0" & exp_siga_uid14_fpFusedAddSubTest_b);
expAmExpB_uid48_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("0" & exp_sigb_uid28_fpFusedAddSubTest_b);
expAmExpB_uid48_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expAmExpB_uid48_fpFusedAddSubTest_a) - UNSIGNED(expAmExpB_uid48_fpFusedAddSubTest_b));
expAmExpB_uid48_fpFusedAddSubTest_q <= expAmExpB_uid48_fpFusedAddSubTest_o(8 downto 0);
-- expAmExpBShiftRange_uid53_fpFusedAddSubTest(BITSELECT,52)@1
expAmExpBShiftRange_uid53_fpFusedAddSubTest_in <= expAmExpB_uid48_fpFusedAddSubTest_q(4 downto 0);
expAmExpBShiftRange_uid53_fpFusedAddSubTest_b <= expAmExpBShiftRange_uid53_fpFusedAddSubTest_in(4 downto 0);
-- cWFP1_uid49_fpFusedAddSubTest(CONSTANT,48)
cWFP1_uid49_fpFusedAddSubTest_q <= "11000";
-- shiftedOut_uid51_fpFusedAddSubTest(COMPARE,50)@1
shiftedOut_uid51_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("000000" & cWFP1_uid49_fpFusedAddSubTest_q);
shiftedOut_uid51_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("00" & expAmExpB_uid48_fpFusedAddSubTest_q);
shiftedOut_uid51_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftedOut_uid51_fpFusedAddSubTest_a) - UNSIGNED(shiftedOut_uid51_fpFusedAddSubTest_b));
shiftedOut_uid51_fpFusedAddSubTest_c(0) <= shiftedOut_uid51_fpFusedAddSubTest_o(10);
-- shiftValue_uid54_fpFusedAddSubTest(MUX,53)@1
shiftValue_uid54_fpFusedAddSubTest_s <= shiftedOut_uid51_fpFusedAddSubTest_c;
shiftValue_uid54_fpFusedAddSubTest_combproc: PROCESS (shiftValue_uid54_fpFusedAddSubTest_s, expAmExpBShiftRange_uid53_fpFusedAddSubTest_b, shiftOutConst_uid52_fpFusedAddSubTest_q)
BEGIN
CASE (shiftValue_uid54_fpFusedAddSubTest_s) IS
WHEN "0" => shiftValue_uid54_fpFusedAddSubTest_q <= expAmExpBShiftRange_uid53_fpFusedAddSubTest_b;
WHEN "1" => shiftValue_uid54_fpFusedAddSubTest_q <= shiftOutConst_uid52_fpFusedAddSubTest_q;
WHEN OTHERS => shiftValue_uid54_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select(BITSELECT,342)@1
rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select_b <= shiftValue_uid54_fpFusedAddSubTest_q(4 downto 2);
rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select_c <= shiftValue_uid54_fpFusedAddSubTest_q(1 downto 0);
-- rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest(MUX,255)@1
rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_s <= rightShiftStageSel4Dto2_uid244_alignmentShifter_uid59_fpFusedAddSubTest_merged_bit_select_c;
rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_combproc: PROCESS (rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_s, rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q, rightShiftStage1Idx1_uid248_alignmentShifter_uid59_fpFusedAddSubTest_q, rightShiftStage1Idx2_uid251_alignmentShifter_uid59_fpFusedAddSubTest_q, rightShiftStage1Idx3_uid254_alignmentShifter_uid59_fpFusedAddSubTest_q)
BEGIN
CASE (rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_s) IS
WHEN "00" => rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage0_uid245_alignmentShifter_uid59_fpFusedAddSubTest_mfinal_q;
WHEN "01" => rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage1Idx1_uid248_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN "10" => rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage1Idx2_uid251_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN "11" => rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_q <= rightShiftStage1Idx3_uid254_alignmentShifter_uid59_fpFusedAddSubTest_q;
WHEN OTHERS => rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- fracBOp_uid62_fpFusedAddSubTest(BITJOIN,61)@1
fracBOp_uid62_fpFusedAddSubTest_q <= GND_q & GND_q & rightShiftStage1_uid256_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- frac_siga_uid15_fpFusedAddSubTest(BITSELECT,14)@1
frac_siga_uid15_fpFusedAddSubTest_in <= siga_uid9_fpFusedAddSubTest_q(22 downto 0);
frac_siga_uid15_fpFusedAddSubTest_b <= frac_siga_uid15_fpFusedAddSubTest_in(22 downto 0);
-- oFracA_uid57_fpFusedAddSubTest(BITJOIN,56)@1
oFracA_uid57_fpFusedAddSubTest_q <= VCC_q & frac_siga_uid15_fpFusedAddSubTest_b;
-- fracAOp_uid61_fpFusedAddSubTest(BITJOIN,60)@1
fracAOp_uid61_fpFusedAddSubTest_q <= oFracA_uid57_fpFusedAddSubTest_q & GND_q;
-- fracResSub_uid63_fpFusedAddSubTest(SUB,62)@1
fracResSub_uid63_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("000" & fracAOp_uid61_fpFusedAddSubTest_q);
fracResSub_uid63_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("0" & fracBOp_uid62_fpFusedAddSubTest_q);
fracResSub_uid63_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(fracResSub_uid63_fpFusedAddSubTest_a) - UNSIGNED(fracResSub_uid63_fpFusedAddSubTest_b));
fracResSub_uid63_fpFusedAddSubTest_q <= fracResSub_uid63_fpFusedAddSubTest_o(27 downto 0);
-- fracResSubNoSignExt_uid65_fpFusedAddSubTest(BITSELECT,64)@1
fracResSubNoSignExt_uid65_fpFusedAddSubTest_in <= fracResSub_uid63_fpFusedAddSubTest_q(25 downto 0);
fracResSubNoSignExt_uid65_fpFusedAddSubTest_b <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_in(25 downto 0);
-- rVStage_uid162_lzCountValSub_uid67_fpFusedAddSubTest(BITSELECT,161)@1
rVStage_uid162_lzCountValSub_uid67_fpFusedAddSubTest_b <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b(25 downto 10);
-- vCount_uid163_lzCountValSub_uid67_fpFusedAddSubTest(LOGICAL,162)@1
vCount_uid163_lzCountValSub_uid67_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid162_lzCountValSub_uid67_fpFusedAddSubTest_b = zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest_q ELSE "0";
-- vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest(BITSELECT,164)@1
vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest_in <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b(9 downto 0);
vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest_b <= vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest_in(9 downto 0);
-- mO_uid164_lzCountValSub_uid67_fpFusedAddSubTest(CONSTANT,163)
mO_uid164_lzCountValSub_uid67_fpFusedAddSubTest_q <= "111111";
-- cStage_uid166_lzCountValSub_uid67_fpFusedAddSubTest(BITJOIN,165)@1
cStage_uid166_lzCountValSub_uid67_fpFusedAddSubTest_q <= vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest_b & mO_uid164_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest(MUX,167)@1
vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_s <= vCount_uid163_lzCountValSub_uid67_fpFusedAddSubTest_q;
vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_s, rVStage_uid162_lzCountValSub_uid67_fpFusedAddSubTest_b, cStage_uid166_lzCountValSub_uid67_fpFusedAddSubTest_q)
BEGIN
CASE (vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_q <= rVStage_uid162_lzCountValSub_uid67_fpFusedAddSubTest_b;
WHEN "1" => vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_q <= cStage_uid166_lzCountValSub_uid67_fpFusedAddSubTest_q;
WHEN OTHERS => vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select(BITSELECT,343)@1
rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b <= vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_q(15 downto 8);
rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c <= vStagei_uid168_lzCountValSub_uid67_fpFusedAddSubTest_q(7 downto 0);
-- vCount_uid171_lzCountValSub_uid67_fpFusedAddSubTest(LOGICAL,170)@1
vCount_uid171_lzCountValSub_uid67_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b = cstAllZWE_uid13_fpFusedAddSubTest_q ELSE "0";
-- vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest(MUX,173)@1
vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_s <= vCount_uid171_lzCountValSub_uid67_fpFusedAddSubTest_q;
vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_s, rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b, rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c)
BEGIN
CASE (vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_q <= rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b;
WHEN "1" => vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_q <= rVStage_uid170_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c;
WHEN OTHERS => vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select(BITSELECT,344)@1
rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b <= vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_q(7 downto 4);
rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c <= vStagei_uid174_lzCountValSub_uid67_fpFusedAddSubTest_q(3 downto 0);
-- vCount_uid177_lzCountValSub_uid67_fpFusedAddSubTest(LOGICAL,176)@1
vCount_uid177_lzCountValSub_uid67_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b = zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest_q ELSE "0";
-- vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest(MUX,179)@1
vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_s <= vCount_uid177_lzCountValSub_uid67_fpFusedAddSubTest_q;
vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_s, rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b, rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c)
BEGIN
CASE (vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_q <= rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b;
WHEN "1" => vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_q <= rVStage_uid176_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c;
WHEN OTHERS => vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select(BITSELECT,345)@1
rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b <= vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_q(3 downto 2);
rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c <= vStagei_uid180_lzCountValSub_uid67_fpFusedAddSubTest_q(1 downto 0);
-- vCount_uid183_lzCountValSub_uid67_fpFusedAddSubTest(LOGICAL,182)@1
vCount_uid183_lzCountValSub_uid67_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b = zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest_q ELSE "0";
-- vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest(MUX,185)@1
vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_s <= vCount_uid183_lzCountValSub_uid67_fpFusedAddSubTest_q;
vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_s, rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b, rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c)
BEGIN
CASE (vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_q <= rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_b;
WHEN "1" => vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_q <= rVStage_uid182_lzCountValSub_uid67_fpFusedAddSubTest_merged_bit_select_c;
WHEN OTHERS => vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid188_lzCountValSub_uid67_fpFusedAddSubTest(BITSELECT,187)@1
rVStage_uid188_lzCountValSub_uid67_fpFusedAddSubTest_b <= vStagei_uid186_lzCountValSub_uid67_fpFusedAddSubTest_q(1 downto 1);
-- vCount_uid189_lzCountValSub_uid67_fpFusedAddSubTest(LOGICAL,188)@1
vCount_uid189_lzCountValSub_uid67_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid188_lzCountValSub_uid67_fpFusedAddSubTest_b = GND_q ELSE "0";
-- r_uid190_lzCountValSub_uid67_fpFusedAddSubTest(BITJOIN,189)@1
r_uid190_lzCountValSub_uid67_fpFusedAddSubTest_q <= vCount_uid163_lzCountValSub_uid67_fpFusedAddSubTest_q & vCount_uid171_lzCountValSub_uid67_fpFusedAddSubTest_q & vCount_uid177_lzCountValSub_uid67_fpFusedAddSubTest_q & vCount_uid183_lzCountValSub_uid67_fpFusedAddSubTest_q & vCount_uid189_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- aMinusA_uid72_fpFusedAddSubTest(LOGICAL,71)@1
aMinusA_uid72_fpFusedAddSubTest_q <= "1" WHEN r_uid190_lzCountValSub_uid67_fpFusedAddSubTest_q = cAmA_uid71_fpFusedAddSubTest_q ELSE "0";
-- cstAllOWE_uid11_fpFusedAddSubTest(CONSTANT,10)
cstAllOWE_uid11_fpFusedAddSubTest_q <= "11111111";
-- expXIsMax_uid17_fpFusedAddSubTest(LOGICAL,16)@1
expXIsMax_uid17_fpFusedAddSubTest_q <= "1" WHEN exp_siga_uid14_fpFusedAddSubTest_b = cstAllOWE_uid11_fpFusedAddSubTest_q ELSE "0";
-- invExpXIsMax_uid22_fpFusedAddSubTest(LOGICAL,21)@1
invExpXIsMax_uid22_fpFusedAddSubTest_q <= not (expXIsMax_uid17_fpFusedAddSubTest_q);
-- excZ_siga_uid9_uid16_fpFusedAddSubTest(LOGICAL,15)@1
excZ_siga_uid9_uid16_fpFusedAddSubTest_q <= "1" WHEN exp_siga_uid14_fpFusedAddSubTest_b = cstAllZWE_uid13_fpFusedAddSubTest_q ELSE "0";
-- InvExpXIsZero_uid23_fpFusedAddSubTest(LOGICAL,22)@1
InvExpXIsZero_uid23_fpFusedAddSubTest_q <= not (excZ_siga_uid9_uid16_fpFusedAddSubTest_q);
-- excR_siga_uid24_fpFusedAddSubTest(LOGICAL,23)@1
excR_siga_uid24_fpFusedAddSubTest_q <= InvExpXIsZero_uid23_fpFusedAddSubTest_q and invExpXIsMax_uid22_fpFusedAddSubTest_q;
-- positiveExc_uid145_fpFusedAddSubTest(LOGICAL,144)@1
positiveExc_uid145_fpFusedAddSubTest_q <= excR_siga_uid24_fpFusedAddSubTest_q and aMinusA_uid72_fpFusedAddSubTest_q and sigA_uid43_fpFusedAddSubTest_b and sigB_uid44_fpFusedAddSubTest_b;
-- invPositiveExc_uid146_fpFusedAddSubTest(LOGICAL,145)@1
invPositiveExc_uid146_fpFusedAddSubTest_q <= not (positiveExc_uid145_fpFusedAddSubTest_q);
-- signInputsZeroForSub_uid147_fpFusedAddSubTest(LOGICAL,146)@1
signInputsZeroForSub_uid147_fpFusedAddSubTest_q <= excZ_siga_uid9_uid16_fpFusedAddSubTest_q and excZ_sigb_uid10_uid30_fpFusedAddSubTest_q and sigA_uid43_fpFusedAddSubTest_b and sigB_uid44_fpFusedAddSubTest_b;
-- invSignInputsZeroForSub_uid148_fpFusedAddSubTest(LOGICAL,147)@1
invSignInputsZeroForSub_uid148_fpFusedAddSubTest_q <= not (signInputsZeroForSub_uid147_fpFusedAddSubTest_q);
-- sigY_uid149_fpFusedAddSubTest(BITSELECT,148)@1
sigY_uid149_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR(redist1_xIn_b_1_q(31 downto 31));
-- invSigY_uid150_fpFusedAddSubTest(LOGICAL,149)@1
invSigY_uid150_fpFusedAddSubTest_q <= not (sigY_uid149_fpFusedAddSubTest_b);
-- invXGTEy_uid125_fpFusedAddSubTest(LOGICAL,124)@1
invXGTEy_uid125_fpFusedAddSubTest_q <= not (xGTEy_uid8_fpFusedAddSubTest_n);
-- yGTxYPos_uid152_fpFusedAddSubTest(LOGICAL,151)@1
yGTxYPos_uid152_fpFusedAddSubTest_q <= invXGTEy_uid125_fpFusedAddSubTest_q and invSigY_uid150_fpFusedAddSubTest_q;
-- sigX_uid153_fpFusedAddSubTest(BITSELECT,152)@1
sigX_uid153_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR(redist0_xIn_a_1_q(31 downto 31));
-- xGTyXNeg_uid154_fpFusedAddSubTest(LOGICAL,153)@1
xGTyXNeg_uid154_fpFusedAddSubTest_q <= xGTEy_uid8_fpFusedAddSubTest_n and sigX_uid153_fpFusedAddSubTest_b;
-- signRPostExcSub0_uid155_fpFusedAddSubTest(LOGICAL,154)@1
signRPostExcSub0_uid155_fpFusedAddSubTest_q <= xGTyXNeg_uid154_fpFusedAddSubTest_q or yGTxYPos_uid152_fpFusedAddSubTest_q;
-- cstZeroWF_uid12_fpFusedAddSubTest(CONSTANT,11)
cstZeroWF_uid12_fpFusedAddSubTest_q <= "00000000000000000000000";
-- fracXIsZero_uid32_fpFusedAddSubTest(LOGICAL,31)@1
fracXIsZero_uid32_fpFusedAddSubTest_q <= "1" WHEN cstZeroWF_uid12_fpFusedAddSubTest_q = frac_sigb_uid29_fpFusedAddSubTest_b ELSE "0";
-- fracXIsNotZero_uid33_fpFusedAddSubTest(LOGICAL,32)@1
fracXIsNotZero_uid33_fpFusedAddSubTest_q <= not (fracXIsZero_uid32_fpFusedAddSubTest_q);
-- expXIsMax_uid31_fpFusedAddSubTest(LOGICAL,30)@1
expXIsMax_uid31_fpFusedAddSubTest_q <= "1" WHEN exp_sigb_uid28_fpFusedAddSubTest_b = cstAllOWE_uid11_fpFusedAddSubTest_q ELSE "0";
-- excN_sigb_uid35_fpFusedAddSubTest(LOGICAL,34)@1
excN_sigb_uid35_fpFusedAddSubTest_q <= expXIsMax_uid31_fpFusedAddSubTest_q and fracXIsNotZero_uid33_fpFusedAddSubTest_q;
-- fracXIsZero_uid18_fpFusedAddSubTest(LOGICAL,17)@1
fracXIsZero_uid18_fpFusedAddSubTest_q <= "1" WHEN cstZeroWF_uid12_fpFusedAddSubTest_q = frac_siga_uid15_fpFusedAddSubTest_b ELSE "0";
-- fracXIsNotZero_uid19_fpFusedAddSubTest(LOGICAL,18)@1
fracXIsNotZero_uid19_fpFusedAddSubTest_q <= not (fracXIsZero_uid18_fpFusedAddSubTest_q);
-- excN_siga_uid21_fpFusedAddSubTest(LOGICAL,20)@1
excN_siga_uid21_fpFusedAddSubTest_q <= expXIsMax_uid17_fpFusedAddSubTest_q and fracXIsNotZero_uid19_fpFusedAddSubTest_q;
-- effSub_uid45_fpFusedAddSubTest(LOGICAL,44)@1
effSub_uid45_fpFusedAddSubTest_q <= sigA_uid43_fpFusedAddSubTest_b xor sigB_uid44_fpFusedAddSubTest_b;
-- invEffSub_uid106_fpFusedAddSubTest(LOGICAL,105)@1
invEffSub_uid106_fpFusedAddSubTest_q <= not (effSub_uid45_fpFusedAddSubTest_q);
-- excI_sigb_uid34_fpFusedAddSubTest(LOGICAL,33)@1
excI_sigb_uid34_fpFusedAddSubTest_q <= expXIsMax_uid31_fpFusedAddSubTest_q and fracXIsZero_uid32_fpFusedAddSubTest_q;
-- excI_siga_uid20_fpFusedAddSubTest(LOGICAL,19)@1
excI_siga_uid20_fpFusedAddSubTest_q <= expXIsMax_uid17_fpFusedAddSubTest_q and fracXIsZero_uid18_fpFusedAddSubTest_q;
-- infPinfForSub_uid107_fpFusedAddSubTest(LOGICAL,106)@1
infPinfForSub_uid107_fpFusedAddSubTest_q <= excI_siga_uid20_fpFusedAddSubTest_q and excI_sigb_uid34_fpFusedAddSubTest_q and invEffSub_uid106_fpFusedAddSubTest_q;
-- excRNaNS_uid108_fpFusedAddSubTest(LOGICAL,107)@1
excRNaNS_uid108_fpFusedAddSubTest_q <= infPinfForSub_uid107_fpFusedAddSubTest_q or excN_siga_uid21_fpFusedAddSubTest_q or excN_sigb_uid35_fpFusedAddSubTest_q;
-- invExcRNaNS_uid156_fpFusedAddSubTest(LOGICAL,155)@1
invExcRNaNS_uid156_fpFusedAddSubTest_q <= not (excRNaNS_uid108_fpFusedAddSubTest_q);
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- signRPostExcSub_uid157_fpFusedAddSubTest(LOGICAL,156)@1
signRPostExcSub_uid157_fpFusedAddSubTest_q <= invExcRNaNS_uid156_fpFusedAddSubTest_q and signRPostExcSub0_uid155_fpFusedAddSubTest_q and invSignInputsZeroForSub_uid148_fpFusedAddSubTest_q and invPositiveExc_uid146_fpFusedAddSubTest_q;
-- fracResAdd_uid64_fpFusedAddSubTest(ADD,63)@1
fracResAdd_uid64_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("000" & fracAOp_uid61_fpFusedAddSubTest_q);
fracResAdd_uid64_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("0" & fracBOp_uid62_fpFusedAddSubTest_q);
fracResAdd_uid64_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(fracResAdd_uid64_fpFusedAddSubTest_a) + UNSIGNED(fracResAdd_uid64_fpFusedAddSubTest_b));
fracResAdd_uid64_fpFusedAddSubTest_q <= fracResAdd_uid64_fpFusedAddSubTest_o(27 downto 0);
-- fracResAddNoSignExt_uid66_fpFusedAddSubTest(BITSELECT,65)@1
fracResAddNoSignExt_uid66_fpFusedAddSubTest_in <= fracResAdd_uid64_fpFusedAddSubTest_q(25 downto 0);
fracResAddNoSignExt_uid66_fpFusedAddSubTest_b <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_in(25 downto 0);
-- rVStage_uid193_lzCountValAdd_uid69_fpFusedAddSubTest(BITSELECT,192)@1
rVStage_uid193_lzCountValAdd_uid69_fpFusedAddSubTest_b <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b(25 downto 10);
-- vCount_uid194_lzCountValAdd_uid69_fpFusedAddSubTest(LOGICAL,193)@1
vCount_uid194_lzCountValAdd_uid69_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid193_lzCountValAdd_uid69_fpFusedAddSubTest_b = zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest_q ELSE "0";
-- vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest(BITSELECT,195)@1
vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest_in <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b(9 downto 0);
vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest_b <= vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest_in(9 downto 0);
-- cStage_uid197_lzCountValAdd_uid69_fpFusedAddSubTest(BITJOIN,196)@1
cStage_uid197_lzCountValAdd_uid69_fpFusedAddSubTest_q <= vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest_b & mO_uid164_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest(MUX,198)@1
vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_s <= vCount_uid194_lzCountValAdd_uid69_fpFusedAddSubTest_q;
vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_s, rVStage_uid193_lzCountValAdd_uid69_fpFusedAddSubTest_b, cStage_uid197_lzCountValAdd_uid69_fpFusedAddSubTest_q)
BEGIN
CASE (vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_q <= rVStage_uid193_lzCountValAdd_uid69_fpFusedAddSubTest_b;
WHEN "1" => vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_q <= cStage_uid197_lzCountValAdd_uid69_fpFusedAddSubTest_q;
WHEN OTHERS => vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select(BITSELECT,347)@1
rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b <= vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_q(15 downto 8);
rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c <= vStagei_uid199_lzCountValAdd_uid69_fpFusedAddSubTest_q(7 downto 0);
-- vCount_uid202_lzCountValAdd_uid69_fpFusedAddSubTest(LOGICAL,201)@1
vCount_uid202_lzCountValAdd_uid69_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b = cstAllZWE_uid13_fpFusedAddSubTest_q ELSE "0";
-- vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest(MUX,204)@1
vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_s <= vCount_uid202_lzCountValAdd_uid69_fpFusedAddSubTest_q;
vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_s, rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b, rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c)
BEGIN
CASE (vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_q <= rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b;
WHEN "1" => vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_q <= rVStage_uid201_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c;
WHEN OTHERS => vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select(BITSELECT,348)@1
rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b <= vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_q(7 downto 4);
rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c <= vStagei_uid205_lzCountValAdd_uid69_fpFusedAddSubTest_q(3 downto 0);
-- vCount_uid208_lzCountValAdd_uid69_fpFusedAddSubTest(LOGICAL,207)@1
vCount_uid208_lzCountValAdd_uid69_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b = zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest_q ELSE "0";
-- vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest(MUX,210)@1
vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_s <= vCount_uid208_lzCountValAdd_uid69_fpFusedAddSubTest_q;
vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_s, rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b, rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c)
BEGIN
CASE (vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_q <= rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b;
WHEN "1" => vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_q <= rVStage_uid207_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c;
WHEN OTHERS => vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select(BITSELECT,349)@1
rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b <= vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_q(3 downto 2);
rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c <= vStagei_uid211_lzCountValAdd_uid69_fpFusedAddSubTest_q(1 downto 0);
-- vCount_uid214_lzCountValAdd_uid69_fpFusedAddSubTest(LOGICAL,213)@1
vCount_uid214_lzCountValAdd_uid69_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b = zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest_q ELSE "0";
-- vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest(MUX,216)@1
vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_s <= vCount_uid214_lzCountValAdd_uid69_fpFusedAddSubTest_q;
vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_combproc: PROCESS (vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_s, rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b, rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c)
BEGIN
CASE (vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_s) IS
WHEN "0" => vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_q <= rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_b;
WHEN "1" => vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_q <= rVStage_uid213_lzCountValAdd_uid69_fpFusedAddSubTest_merged_bit_select_c;
WHEN OTHERS => vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- rVStage_uid219_lzCountValAdd_uid69_fpFusedAddSubTest(BITSELECT,218)@1
rVStage_uid219_lzCountValAdd_uid69_fpFusedAddSubTest_b <= vStagei_uid217_lzCountValAdd_uid69_fpFusedAddSubTest_q(1 downto 1);
-- vCount_uid220_lzCountValAdd_uid69_fpFusedAddSubTest(LOGICAL,219)@1
vCount_uid220_lzCountValAdd_uid69_fpFusedAddSubTest_q <= "1" WHEN rVStage_uid219_lzCountValAdd_uid69_fpFusedAddSubTest_b = GND_q ELSE "0";
-- r_uid221_lzCountValAdd_uid69_fpFusedAddSubTest(BITJOIN,220)@1
r_uid221_lzCountValAdd_uid69_fpFusedAddSubTest_q <= vCount_uid194_lzCountValAdd_uid69_fpFusedAddSubTest_q & vCount_uid202_lzCountValAdd_uid69_fpFusedAddSubTest_q & vCount_uid208_lzCountValAdd_uid69_fpFusedAddSubTest_q & vCount_uid214_lzCountValAdd_uid69_fpFusedAddSubTest_q & vCount_uid220_lzCountValAdd_uid69_fpFusedAddSubTest_q;
-- expInc_uid73_fpFusedAddSubTest(ADD,72)@1
expInc_uid73_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("0" & exp_siga_uid14_fpFusedAddSubTest_b);
expInc_uid73_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expInc_uid73_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expInc_uid73_fpFusedAddSubTest_a) + UNSIGNED(expInc_uid73_fpFusedAddSubTest_b));
expInc_uid73_fpFusedAddSubTest_q <= expInc_uid73_fpFusedAddSubTest_o(8 downto 0);
-- expPostNormAdd_uid75_fpFusedAddSubTest(SUB,74)@1
expPostNormAdd_uid75_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("0" & expInc_uid73_fpFusedAddSubTest_q);
expPostNormAdd_uid75_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("00000" & r_uid221_lzCountValAdd_uid69_fpFusedAddSubTest_q);
expPostNormAdd_uid75_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expPostNormAdd_uid75_fpFusedAddSubTest_a) - UNSIGNED(expPostNormAdd_uid75_fpFusedAddSubTest_b));
expPostNormAdd_uid75_fpFusedAddSubTest_q <= expPostNormAdd_uid75_fpFusedAddSubTest_o(9 downto 0);
-- leftShiftStage1Idx3Rng3_uid323_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,322)@1
leftShiftStage1Idx3Rng3_uid323_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q(22 downto 0);
leftShiftStage1Idx3Rng3_uid323_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage1Idx3Rng3_uid323_fracPostNormAdd_uid70_fpFusedAddSubTest_in(22 downto 0);
-- leftShiftStage1Idx3_uid324_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,323)@1
leftShiftStage1Idx3_uid324_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage1Idx3Rng3_uid323_fracPostNormAdd_uid70_fpFusedAddSubTest_b & rightShiftStage1Idx3Pad3_uid253_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage1Idx2Rng2_uid320_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,319)@1
leftShiftStage1Idx2Rng2_uid320_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q(23 downto 0);
leftShiftStage1Idx2Rng2_uid320_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage1Idx2Rng2_uid320_fracPostNormAdd_uid70_fpFusedAddSubTest_in(23 downto 0);
-- leftShiftStage1Idx2_uid321_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,320)@1
leftShiftStage1Idx2_uid321_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage1Idx2Rng2_uid320_fracPostNormAdd_uid70_fpFusedAddSubTest_b & zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- leftShiftStage1Idx1Rng1_uid317_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,316)@1
leftShiftStage1Idx1Rng1_uid317_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q(24 downto 0);
leftShiftStage1Idx1Rng1_uid317_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage1Idx1Rng1_uid317_fracPostNormAdd_uid70_fpFusedAddSubTest_in(24 downto 0);
-- leftShiftStage1Idx1_uid318_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,317)@1
leftShiftStage1Idx1_uid318_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage1Idx1Rng1_uid317_fracPostNormAdd_uid70_fpFusedAddSubTest_b & GND_q;
-- leftShiftStage0Idx7_uid278_fracPostNormSub_uid68_fpFusedAddSubTest(CONSTANT,277)
leftShiftStage0Idx7_uid278_fracPostNormSub_uid68_fpFusedAddSubTest_q <= "00000000000000000000000000";
-- leftShiftStage0Idx6Rng24_uid311_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,310)@1
leftShiftStage0Idx6Rng24_uid311_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b(1 downto 0);
leftShiftStage0Idx6Rng24_uid311_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage0Idx6Rng24_uid311_fracPostNormAdd_uid70_fpFusedAddSubTest_in(1 downto 0);
-- leftShiftStage0Idx6_uid312_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,311)@1
leftShiftStage0Idx6_uid312_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage0Idx6Rng24_uid311_fracPostNormAdd_uid70_fpFusedAddSubTest_b & rightShiftStage0Idx6Pad24_uid241_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage0Idx5Rng20_uid308_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,307)@1
leftShiftStage0Idx5Rng20_uid308_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b(5 downto 0);
leftShiftStage0Idx5Rng20_uid308_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage0Idx5Rng20_uid308_fracPostNormAdd_uid70_fpFusedAddSubTest_in(5 downto 0);
-- leftShiftStage0Idx5_uid309_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,308)@1
leftShiftStage0Idx5_uid309_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage0Idx5Rng20_uid308_fracPostNormAdd_uid70_fpFusedAddSubTest_b & rightShiftStage0Idx5Pad20_uid238_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage0Idx4_uid306_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,305)@1
leftShiftStage0Idx4_uid306_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= vStage_uid196_lzCountValAdd_uid69_fpFusedAddSubTest_b & zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1(MUX,340)@1
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_s <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select_b;
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_combproc: PROCESS (leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_s, leftShiftStage0Idx4_uid306_fracPostNormAdd_uid70_fpFusedAddSubTest_q, leftShiftStage0Idx5_uid309_fracPostNormAdd_uid70_fpFusedAddSubTest_q, leftShiftStage0Idx6_uid312_fracPostNormAdd_uid70_fpFusedAddSubTest_q, leftShiftStage0Idx7_uid278_fracPostNormSub_uid68_fpFusedAddSubTest_q)
BEGIN
CASE (leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_s) IS
WHEN "00" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx4_uid306_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN "01" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx5_uid309_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN "10" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx6_uid312_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN "11" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx7_uid278_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN OTHERS => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q <= (others => '0');
END CASE;
END PROCESS;
-- leftShiftStage0Idx3Rng12_uid302_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,301)@1
leftShiftStage0Idx3Rng12_uid302_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b(13 downto 0);
leftShiftStage0Idx3Rng12_uid302_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage0Idx3Rng12_uid302_fracPostNormAdd_uid70_fpFusedAddSubTest_in(13 downto 0);
-- leftShiftStage0Idx3_uid303_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,302)@1
leftShiftStage0Idx3_uid303_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage0Idx3Rng12_uid302_fracPostNormAdd_uid70_fpFusedAddSubTest_b & rightShiftStage0Idx3Pad12_uid232_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage0Idx2Rng8_uid299_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,298)@1
leftShiftStage0Idx2Rng8_uid299_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b(17 downto 0);
leftShiftStage0Idx2Rng8_uid299_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage0Idx2Rng8_uid299_fracPostNormAdd_uid70_fpFusedAddSubTest_in(17 downto 0);
-- leftShiftStage0Idx2_uid300_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,299)@1
leftShiftStage0Idx2_uid300_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage0Idx2Rng8_uid299_fracPostNormAdd_uid70_fpFusedAddSubTest_b & cstAllZWE_uid13_fpFusedAddSubTest_q;
-- leftShiftStage0Idx1Rng4_uid296_fracPostNormAdd_uid70_fpFusedAddSubTest(BITSELECT,295)@1
leftShiftStage0Idx1Rng4_uid296_fracPostNormAdd_uid70_fpFusedAddSubTest_in <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b(21 downto 0);
leftShiftStage0Idx1Rng4_uid296_fracPostNormAdd_uid70_fpFusedAddSubTest_b <= leftShiftStage0Idx1Rng4_uid296_fracPostNormAdd_uid70_fpFusedAddSubTest_in(21 downto 0);
-- leftShiftStage0Idx1_uid297_fracPostNormAdd_uid70_fpFusedAddSubTest(BITJOIN,296)@1
leftShiftStage0Idx1_uid297_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage0Idx1Rng4_uid296_fracPostNormAdd_uid70_fpFusedAddSubTest_b & zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0(MUX,339)@1
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_s <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select_b;
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_combproc: PROCESS (leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_s, fracResAddNoSignExt_uid66_fpFusedAddSubTest_b, leftShiftStage0Idx1_uid297_fracPostNormAdd_uid70_fpFusedAddSubTest_q, leftShiftStage0Idx2_uid300_fracPostNormAdd_uid70_fpFusedAddSubTest_q, leftShiftStage0Idx3_uid303_fracPostNormAdd_uid70_fpFusedAddSubTest_q)
BEGIN
CASE (leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_s) IS
WHEN "00" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q <= fracResAddNoSignExt_uid66_fpFusedAddSubTest_b;
WHEN "01" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q <= leftShiftStage0Idx1_uid297_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN "10" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q <= leftShiftStage0Idx2_uid300_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN "11" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q <= leftShiftStage0Idx3_uid303_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN OTHERS => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q <= (others => '0');
END CASE;
END PROCESS;
-- leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select(BITSELECT,353)@1
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select_b <= leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select_b(1 downto 0);
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select_c <= leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select_b(2 downto 2);
-- leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal(MUX,341)@1
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_s <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_selLSBs_merged_bit_select_c;
leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_combproc: PROCESS (leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_s, leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q, leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q)
BEGIN
CASE (leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_s) IS
WHEN "0" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_0_q;
WHEN "1" => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_msplit_1_q;
WHEN OTHERS => leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q <= (others => '0');
END CASE;
END PROCESS;
-- leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select(BITSELECT,350)@1
leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select_b <= r_uid221_lzCountValAdd_uid69_fpFusedAddSubTest_q(4 downto 2);
leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select_c <= r_uid221_lzCountValAdd_uid69_fpFusedAddSubTest_q(1 downto 0);
-- leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest(MUX,325)@1
leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_s <= leftShiftStageSel4Dto2_uid314_fracPostNormAdd_uid70_fpFusedAddSubTest_merged_bit_select_c;
leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_combproc: PROCESS (leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_s, leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q, leftShiftStage1Idx1_uid318_fracPostNormAdd_uid70_fpFusedAddSubTest_q, leftShiftStage1Idx2_uid321_fracPostNormAdd_uid70_fpFusedAddSubTest_q, leftShiftStage1Idx3_uid324_fracPostNormAdd_uid70_fpFusedAddSubTest_q)
BEGIN
CASE (leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_s) IS
WHEN "00" => leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage0_uid315_fracPostNormAdd_uid70_fpFusedAddSubTest_mfinal_q;
WHEN "01" => leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage1Idx1_uid318_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN "10" => leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage1Idx2_uid321_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN "11" => leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= leftShiftStage1Idx3_uid324_fracPostNormAdd_uid70_fpFusedAddSubTest_q;
WHEN OTHERS => leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- fracPostNormAddRndRange_uid78_fpFusedAddSubTest(BITSELECT,77)@1
fracPostNormAddRndRange_uid78_fpFusedAddSubTest_in <= leftShiftStage1_uid326_fracPostNormAdd_uid70_fpFusedAddSubTest_q(24 downto 0);
fracPostNormAddRndRange_uid78_fpFusedAddSubTest_b <= fracPostNormAddRndRange_uid78_fpFusedAddSubTest_in(24 downto 1);
-- expFracRAdd_uid79_fpFusedAddSubTest(BITJOIN,78)@1
expFracRAdd_uid79_fpFusedAddSubTest_q <= expPostNormAdd_uid75_fpFusedAddSubTest_q & fracPostNormAddRndRange_uid78_fpFusedAddSubTest_b;
-- expRPreExcAdd_uid89_fpFusedAddSubTest(BITSELECT,88)@1
expRPreExcAdd_uid89_fpFusedAddSubTest_in <= expFracRAdd_uid79_fpFusedAddSubTest_q(31 downto 0);
expRPreExcAdd_uid89_fpFusedAddSubTest_b <= expRPreExcAdd_uid89_fpFusedAddSubTest_in(31 downto 24);
-- expPostNormSub_uid74_fpFusedAddSubTest(SUB,73)@1
expPostNormSub_uid74_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR("0" & expInc_uid73_fpFusedAddSubTest_q);
expPostNormSub_uid74_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR("00000" & r_uid190_lzCountValSub_uid67_fpFusedAddSubTest_q);
expPostNormSub_uid74_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expPostNormSub_uid74_fpFusedAddSubTest_a) - UNSIGNED(expPostNormSub_uid74_fpFusedAddSubTest_b));
expPostNormSub_uid74_fpFusedAddSubTest_q <= expPostNormSub_uid74_fpFusedAddSubTest_o(9 downto 0);
-- leftShiftStage1Idx3Rng3_uid288_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,287)@1
leftShiftStage1Idx3Rng3_uid288_fracPostNormSub_uid68_fpFusedAddSubTest_in <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q(22 downto 0);
leftShiftStage1Idx3Rng3_uid288_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage1Idx3Rng3_uid288_fracPostNormSub_uid68_fpFusedAddSubTest_in(22 downto 0);
-- leftShiftStage1Idx3_uid289_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,288)@1
leftShiftStage1Idx3_uid289_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage1Idx3Rng3_uid288_fracPostNormSub_uid68_fpFusedAddSubTest_b & rightShiftStage1Idx3Pad3_uid253_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage1Idx2Rng2_uid285_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,284)@1
leftShiftStage1Idx2Rng2_uid285_fracPostNormSub_uid68_fpFusedAddSubTest_in <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q(23 downto 0);
leftShiftStage1Idx2Rng2_uid285_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage1Idx2Rng2_uid285_fracPostNormSub_uid68_fpFusedAddSubTest_in(23 downto 0);
-- leftShiftStage1Idx2_uid286_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,285)@1
leftShiftStage1Idx2_uid286_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage1Idx2Rng2_uid285_fracPostNormSub_uid68_fpFusedAddSubTest_b & zs_uid181_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- leftShiftStage1Idx1Rng1_uid282_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,281)@1
leftShiftStage1Idx1Rng1_uid282_fracPostNormSub_uid68_fpFusedAddSubTest_in <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q(24 downto 0);
leftShiftStage1Idx1Rng1_uid282_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage1Idx1Rng1_uid282_fracPostNormSub_uid68_fpFusedAddSubTest_in(24 downto 0);
-- leftShiftStage1Idx1_uid283_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,282)@1
leftShiftStage1Idx1_uid283_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage1Idx1Rng1_uid282_fracPostNormSub_uid68_fpFusedAddSubTest_b & GND_q;
-- leftShiftStage0Idx6Rng24_uid276_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,275)@1
leftShiftStage0Idx6Rng24_uid276_fracPostNormSub_uid68_fpFusedAddSubTest_in <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b(1 downto 0);
leftShiftStage0Idx6Rng24_uid276_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage0Idx6Rng24_uid276_fracPostNormSub_uid68_fpFusedAddSubTest_in(1 downto 0);
-- leftShiftStage0Idx6_uid277_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,276)@1
leftShiftStage0Idx6_uid277_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage0Idx6Rng24_uid276_fracPostNormSub_uid68_fpFusedAddSubTest_b & rightShiftStage0Idx6Pad24_uid241_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage0Idx5Rng20_uid273_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,272)@1
leftShiftStage0Idx5Rng20_uid273_fracPostNormSub_uid68_fpFusedAddSubTest_in <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b(5 downto 0);
leftShiftStage0Idx5Rng20_uid273_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage0Idx5Rng20_uid273_fracPostNormSub_uid68_fpFusedAddSubTest_in(5 downto 0);
-- leftShiftStage0Idx5_uid274_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,273)@1
leftShiftStage0Idx5_uid274_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage0Idx5Rng20_uid273_fracPostNormSub_uid68_fpFusedAddSubTest_b & rightShiftStage0Idx5Pad20_uid238_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage0Idx4_uid271_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,270)@1
leftShiftStage0Idx4_uid271_fracPostNormSub_uid68_fpFusedAddSubTest_q <= vStage_uid165_lzCountValSub_uid67_fpFusedAddSubTest_b & zs_uid161_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1(MUX,335)@1
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_s <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select_b;
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_combproc: PROCESS (leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_s, leftShiftStage0Idx4_uid271_fracPostNormSub_uid68_fpFusedAddSubTest_q, leftShiftStage0Idx5_uid274_fracPostNormSub_uid68_fpFusedAddSubTest_q, leftShiftStage0Idx6_uid277_fracPostNormSub_uid68_fpFusedAddSubTest_q, leftShiftStage0Idx7_uid278_fracPostNormSub_uid68_fpFusedAddSubTest_q)
BEGIN
CASE (leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_s) IS
WHEN "00" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx4_uid271_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN "01" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx5_uid274_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN "10" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx6_uid277_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN "11" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q <= leftShiftStage0Idx7_uid278_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN OTHERS => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q <= (others => '0');
END CASE;
END PROCESS;
-- leftShiftStage0Idx3Rng12_uid267_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,266)@1
leftShiftStage0Idx3Rng12_uid267_fracPostNormSub_uid68_fpFusedAddSubTest_in <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b(13 downto 0);
leftShiftStage0Idx3Rng12_uid267_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage0Idx3Rng12_uid267_fracPostNormSub_uid68_fpFusedAddSubTest_in(13 downto 0);
-- leftShiftStage0Idx3_uid268_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,267)@1
leftShiftStage0Idx3_uid268_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage0Idx3Rng12_uid267_fracPostNormSub_uid68_fpFusedAddSubTest_b & rightShiftStage0Idx3Pad12_uid232_alignmentShifter_uid59_fpFusedAddSubTest_q;
-- leftShiftStage0Idx2Rng8_uid264_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,263)@1
leftShiftStage0Idx2Rng8_uid264_fracPostNormSub_uid68_fpFusedAddSubTest_in <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b(17 downto 0);
leftShiftStage0Idx2Rng8_uid264_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage0Idx2Rng8_uid264_fracPostNormSub_uid68_fpFusedAddSubTest_in(17 downto 0);
-- leftShiftStage0Idx2_uid265_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,264)@1
leftShiftStage0Idx2_uid265_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage0Idx2Rng8_uid264_fracPostNormSub_uid68_fpFusedAddSubTest_b & cstAllZWE_uid13_fpFusedAddSubTest_q;
-- leftShiftStage0Idx1Rng4_uid261_fracPostNormSub_uid68_fpFusedAddSubTest(BITSELECT,260)@1
leftShiftStage0Idx1Rng4_uid261_fracPostNormSub_uid68_fpFusedAddSubTest_in <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b(21 downto 0);
leftShiftStage0Idx1Rng4_uid261_fracPostNormSub_uid68_fpFusedAddSubTest_b <= leftShiftStage0Idx1Rng4_uid261_fracPostNormSub_uid68_fpFusedAddSubTest_in(21 downto 0);
-- leftShiftStage0Idx1_uid262_fracPostNormSub_uid68_fpFusedAddSubTest(BITJOIN,261)@1
leftShiftStage0Idx1_uid262_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage0Idx1Rng4_uid261_fracPostNormSub_uid68_fpFusedAddSubTest_b & zs_uid175_lzCountValSub_uid67_fpFusedAddSubTest_q;
-- leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0(MUX,334)@1
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_s <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select_b;
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_combproc: PROCESS (leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_s, fracResSubNoSignExt_uid65_fpFusedAddSubTest_b, leftShiftStage0Idx1_uid262_fracPostNormSub_uid68_fpFusedAddSubTest_q, leftShiftStage0Idx2_uid265_fracPostNormSub_uid68_fpFusedAddSubTest_q, leftShiftStage0Idx3_uid268_fracPostNormSub_uid68_fpFusedAddSubTest_q)
BEGIN
CASE (leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_s) IS
WHEN "00" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q <= fracResSubNoSignExt_uid65_fpFusedAddSubTest_b;
WHEN "01" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q <= leftShiftStage0Idx1_uid262_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN "10" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q <= leftShiftStage0Idx2_uid265_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN "11" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q <= leftShiftStage0Idx3_uid268_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN OTHERS => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q <= (others => '0');
END CASE;
END PROCESS;
-- leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select(BITSELECT,352)@1
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select_b <= leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select_b(1 downto 0);
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select_c <= leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select_b(2 downto 2);
-- leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal(MUX,336)@1
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_s <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_selLSBs_merged_bit_select_c;
leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_combproc: PROCESS (leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_s, leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q, leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q)
BEGIN
CASE (leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_s) IS
WHEN "0" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_0_q;
WHEN "1" => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_msplit_1_q;
WHEN OTHERS => leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q <= (others => '0');
END CASE;
END PROCESS;
-- leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select(BITSELECT,346)@1
leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select_b <= r_uid190_lzCountValSub_uid67_fpFusedAddSubTest_q(4 downto 2);
leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select_c <= r_uid190_lzCountValSub_uid67_fpFusedAddSubTest_q(1 downto 0);
-- leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest(MUX,290)@1
leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_s <= leftShiftStageSel4Dto2_uid279_fracPostNormSub_uid68_fpFusedAddSubTest_merged_bit_select_c;
leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_combproc: PROCESS (leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_s, leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q, leftShiftStage1Idx1_uid283_fracPostNormSub_uid68_fpFusedAddSubTest_q, leftShiftStage1Idx2_uid286_fracPostNormSub_uid68_fpFusedAddSubTest_q, leftShiftStage1Idx3_uid289_fracPostNormSub_uid68_fpFusedAddSubTest_q)
BEGIN
CASE (leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_s) IS
WHEN "00" => leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage0_uid280_fracPostNormSub_uid68_fpFusedAddSubTest_mfinal_q;
WHEN "01" => leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage1Idx1_uid283_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN "10" => leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage1Idx2_uid286_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN "11" => leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_q <= leftShiftStage1Idx3_uid289_fracPostNormSub_uid68_fpFusedAddSubTest_q;
WHEN OTHERS => leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- fracPostNormSubRndRange_uid76_fpFusedAddSubTest(BITSELECT,75)@1
fracPostNormSubRndRange_uid76_fpFusedAddSubTest_in <= leftShiftStage1_uid291_fracPostNormSub_uid68_fpFusedAddSubTest_q(24 downto 0);
fracPostNormSubRndRange_uid76_fpFusedAddSubTest_b <= fracPostNormSubRndRange_uid76_fpFusedAddSubTest_in(24 downto 1);
-- expFracRSub_uid77_fpFusedAddSubTest(BITJOIN,76)@1
expFracRSub_uid77_fpFusedAddSubTest_q <= expPostNormSub_uid74_fpFusedAddSubTest_q & fracPostNormSubRndRange_uid76_fpFusedAddSubTest_b;
-- expRPreExcSub_uid86_fpFusedAddSubTest(BITSELECT,85)@1
expRPreExcSub_uid86_fpFusedAddSubTest_in <= expFracRSub_uid77_fpFusedAddSubTest_q(31 downto 0);
expRPreExcSub_uid86_fpFusedAddSubTest_b <= expRPreExcSub_uid86_fpFusedAddSubTest_in(31 downto 24);
-- expRPreExcSubtraction_uid116_fpFusedAddSubTest(MUX,115)@1
expRPreExcSubtraction_uid116_fpFusedAddSubTest_s <= effSub_uid45_fpFusedAddSubTest_q;
expRPreExcSubtraction_uid116_fpFusedAddSubTest_combproc: PROCESS (expRPreExcSubtraction_uid116_fpFusedAddSubTest_s, expRPreExcSub_uid86_fpFusedAddSubTest_b, expRPreExcAdd_uid89_fpFusedAddSubTest_b)
BEGIN
CASE (expRPreExcSubtraction_uid116_fpFusedAddSubTest_s) IS
WHEN "0" => expRPreExcSubtraction_uid116_fpFusedAddSubTest_q <= expRPreExcSub_uid86_fpFusedAddSubTest_b;
WHEN "1" => expRPreExcSubtraction_uid116_fpFusedAddSubTest_q <= expRPreExcAdd_uid89_fpFusedAddSubTest_b;
WHEN OTHERS => expRPreExcSubtraction_uid116_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- wEP2AllOwE_uid80_fpFusedAddSubTest(CONSTANT,79)
wEP2AllOwE_uid80_fpFusedAddSubTest_q <= "0011111111";
-- rndExp_uid81_fpFusedAddSubTest(BITSELECT,80)@1
rndExp_uid81_fpFusedAddSubTest_b <= expFracRAdd_uid79_fpFusedAddSubTest_q(33 downto 24);
-- rOvf_uid82_fpFusedAddSubTest(LOGICAL,81)@1
rOvf_uid82_fpFusedAddSubTest_q <= "1" WHEN rndExp_uid81_fpFusedAddSubTest_b = wEP2AllOwE_uid80_fpFusedAddSubTest_q ELSE "0";
-- invExpXIsMax_uid36_fpFusedAddSubTest(LOGICAL,35)@1
invExpXIsMax_uid36_fpFusedAddSubTest_q <= not (expXIsMax_uid31_fpFusedAddSubTest_q);
-- excR_sigb_uid38_fpFusedAddSubTest(LOGICAL,37)@1
excR_sigb_uid38_fpFusedAddSubTest_q <= InvExpXIsZero_uid37_fpFusedAddSubTest_q and invExpXIsMax_uid36_fpFusedAddSubTest_q;
-- regInputs_uid91_fpFusedAddSubTest(LOGICAL,90)@1
regInputs_uid91_fpFusedAddSubTest_q <= excR_siga_uid24_fpFusedAddSubTest_q and excR_sigb_uid38_fpFusedAddSubTest_q;
-- regInAndOvf_uid95_fpFusedAddSubTest(LOGICAL,94)@1
regInAndOvf_uid95_fpFusedAddSubTest_q <= regInputs_uid91_fpFusedAddSubTest_q and rOvf_uid82_fpFusedAddSubTest_q;
-- excRInfVInC_uid99_fpFusedAddSubTest(BITJOIN,98)@1
excRInfVInC_uid99_fpFusedAddSubTest_q <= regInAndOvf_uid95_fpFusedAddSubTest_q & excZ_sigb_uid10_uid30_fpFusedAddSubTest_q & excZ_siga_uid9_uid16_fpFusedAddSubTest_q & excI_sigb_uid34_fpFusedAddSubTest_q & excI_siga_uid20_fpFusedAddSubTest_q & effSub_uid45_fpFusedAddSubTest_q;
-- excRInfSub_uid102_fpFusedAddSubTest(LOOKUP,101)@1
excRInfSub_uid102_fpFusedAddSubTest_combproc: PROCESS (excRInfVInC_uid99_fpFusedAddSubTest_q)
BEGIN
-- Begin reserved scope level
CASE (excRInfVInC_uid99_fpFusedAddSubTest_q) IS
WHEN "000000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "000001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "000010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "000011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "000100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "000101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "000110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "000111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "1";
WHEN "001000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "001001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "001010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "001011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "001100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "1";
WHEN "001101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "1";
WHEN "001110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "001111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "010000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "010001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "010010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "1";
WHEN "010011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "1";
WHEN "010100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "010101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "010110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "010111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "011111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "100000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "100001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "1";
WHEN "100010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "100011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "100100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "100101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "100110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "100111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "101111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "110111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111000" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111001" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111010" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111011" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111100" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111101" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111110" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN "111111" => excRInfSub_uid102_fpFusedAddSubTest_q <= "0";
WHEN OTHERS => -- unreachable
excRInfSub_uid102_fpFusedAddSubTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- oneIsInfOrZero_uid97_fpFusedAddSubTest(LOGICAL,96)@1
oneIsInfOrZero_uid97_fpFusedAddSubTest_q <= excR_siga_uid24_fpFusedAddSubTest_q or excR_sigb_uid38_fpFusedAddSubTest_q or excZ_siga_uid9_uid16_fpFusedAddSubTest_q or excZ_sigb_uid10_uid30_fpFusedAddSubTest_q;
-- oneIsInf_uid96_fpFusedAddSubTest(LOGICAL,95)@1
oneIsInf_uid96_fpFusedAddSubTest_q <= excI_siga_uid20_fpFusedAddSubTest_q or excI_sigb_uid34_fpFusedAddSubTest_q;
-- addIsAlsoInf_uid98_fpFusedAddSubTest(LOGICAL,97)@1
addIsAlsoInf_uid98_fpFusedAddSubTest_q <= oneIsInf_uid96_fpFusedAddSubTest_q and oneIsInfOrZero_uid97_fpFusedAddSubTest_q;
-- excRInfSubFull_uid103_fpFusedAddSubTest(LOGICAL,102)@1
excRInfSubFull_uid103_fpFusedAddSubTest_q <= addIsAlsoInf_uid98_fpFusedAddSubTest_q or excRInfSub_uid102_fpFusedAddSubTest_q;
-- signedExp_uid83_fpFusedAddSubTest(BITSELECT,82)@1
signedExp_uid83_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR(expFracRSub_uid77_fpFusedAddSubTest_q(33 downto 24));
-- rUdf_uid84_fpFusedAddSubTest(COMPARE,83)@1
rUdf_uid84_fpFusedAddSubTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "0000000000" & GND_q));
rUdf_uid84_fpFusedAddSubTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((11 downto 10 => signedExp_uid83_fpFusedAddSubTest_b(9)) & signedExp_uid83_fpFusedAddSubTest_b));
rUdf_uid84_fpFusedAddSubTest_o <= STD_LOGIC_VECTOR(SIGNED(rUdf_uid84_fpFusedAddSubTest_a) - SIGNED(rUdf_uid84_fpFusedAddSubTest_b));
rUdf_uid84_fpFusedAddSubTest_n(0) <= not (rUdf_uid84_fpFusedAddSubTest_o(11));
-- excRZeroVInC_uid92_fpFusedAddSubTest(BITJOIN,91)@1
excRZeroVInC_uid92_fpFusedAddSubTest_q <= effSub_uid45_fpFusedAddSubTest_q & aMinusA_uid72_fpFusedAddSubTest_q & rUdf_uid84_fpFusedAddSubTest_n & regInputs_uid91_fpFusedAddSubTest_q & excZ_sigb_uid10_uid30_fpFusedAddSubTest_q & excZ_siga_uid9_uid16_fpFusedAddSubTest_q;
-- excRZeroSub_uid94_fpFusedAddSubTest(LOOKUP,93)@1
excRZeroSub_uid94_fpFusedAddSubTest_combproc: PROCESS (excRZeroVInC_uid92_fpFusedAddSubTest_q)
BEGIN
-- Begin reserved scope level
CASE (excRZeroVInC_uid92_fpFusedAddSubTest_q) IS
WHEN "000000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "000001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "000010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "000011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "1";
WHEN "000100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "000101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "000110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "000111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "001000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "001001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "001010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "001011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "001100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "1";
WHEN "001101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "001110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "001111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "010000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "010001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "010010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "010011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "010100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "1";
WHEN "010101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "010110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "010111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "011000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "011001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "011010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "011011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "011100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "1";
WHEN "011101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "011110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "011111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "100111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "101111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "110111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111000" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111001" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111010" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111011" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111100" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111101" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111110" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN "111111" => excRZeroSub_uid94_fpFusedAddSubTest_q <= "0";
WHEN OTHERS => -- unreachable
excRZeroSub_uid94_fpFusedAddSubTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- concExcSub_uid109_fpFusedAddSubTest(BITJOIN,108)@1
concExcSub_uid109_fpFusedAddSubTest_q <= excRNaNS_uid108_fpFusedAddSubTest_q & excRInfSubFull_uid103_fpFusedAddSubTest_q & excRZeroSub_uid94_fpFusedAddSubTest_q;
-- excREncSub_uid111_fpFusedAddSubTest(LOOKUP,110)@1
excREncSub_uid111_fpFusedAddSubTest_combproc: PROCESS (concExcSub_uid109_fpFusedAddSubTest_q)
BEGIN
-- Begin reserved scope level
CASE (concExcSub_uid109_fpFusedAddSubTest_q) IS
WHEN "000" => excREncSub_uid111_fpFusedAddSubTest_q <= "01";
WHEN "001" => excREncSub_uid111_fpFusedAddSubTest_q <= "00";
WHEN "010" => excREncSub_uid111_fpFusedAddSubTest_q <= "10";
WHEN "011" => excREncSub_uid111_fpFusedAddSubTest_q <= "00";
WHEN "100" => excREncSub_uid111_fpFusedAddSubTest_q <= "11";
WHEN "101" => excREncSub_uid111_fpFusedAddSubTest_q <= "00";
WHEN "110" => excREncSub_uid111_fpFusedAddSubTest_q <= "00";
WHEN "111" => excREncSub_uid111_fpFusedAddSubTest_q <= "00";
WHEN OTHERS => -- unreachable
excREncSub_uid111_fpFusedAddSubTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- expRPostExcSub_uid144_fpFusedAddSubTest(MUX,143)@1
expRPostExcSub_uid144_fpFusedAddSubTest_s <= excREncSub_uid111_fpFusedAddSubTest_q;
expRPostExcSub_uid144_fpFusedAddSubTest_combproc: PROCESS (expRPostExcSub_uid144_fpFusedAddSubTest_s, cstAllZWE_uid13_fpFusedAddSubTest_q, expRPreExcSubtraction_uid116_fpFusedAddSubTest_q, cstAllOWE_uid11_fpFusedAddSubTest_q)
BEGIN
CASE (expRPostExcSub_uid144_fpFusedAddSubTest_s) IS
WHEN "00" => expRPostExcSub_uid144_fpFusedAddSubTest_q <= cstAllZWE_uid13_fpFusedAddSubTest_q;
WHEN "01" => expRPostExcSub_uid144_fpFusedAddSubTest_q <= expRPreExcSubtraction_uid116_fpFusedAddSubTest_q;
WHEN "10" => expRPostExcSub_uid144_fpFusedAddSubTest_q <= cstAllOWE_uid11_fpFusedAddSubTest_q;
WHEN "11" => expRPostExcSub_uid144_fpFusedAddSubTest_q <= cstAllOWE_uid11_fpFusedAddSubTest_q;
WHEN OTHERS => expRPostExcSub_uid144_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- oneFracRPostExc2_uid117_fpFusedAddSubTest(CONSTANT,116)
oneFracRPostExc2_uid117_fpFusedAddSubTest_q <= "00000000000000000000001";
-- fracRPreExcAdd_uid88_fpFusedAddSubTest(BITSELECT,87)@1
fracRPreExcAdd_uid88_fpFusedAddSubTest_in <= expFracRAdd_uid79_fpFusedAddSubTest_q(23 downto 0);
fracRPreExcAdd_uid88_fpFusedAddSubTest_b <= fracRPreExcAdd_uid88_fpFusedAddSubTest_in(23 downto 1);
-- fracRPreExcSub_uid85_fpFusedAddSubTest(BITSELECT,84)@1
fracRPreExcSub_uid85_fpFusedAddSubTest_in <= expFracRSub_uid77_fpFusedAddSubTest_q(23 downto 0);
fracRPreExcSub_uid85_fpFusedAddSubTest_b <= fracRPreExcSub_uid85_fpFusedAddSubTest_in(23 downto 1);
-- fracRPreExcSubtraction_uid115_fpFusedAddSubTest(MUX,114)@1
fracRPreExcSubtraction_uid115_fpFusedAddSubTest_s <= effSub_uid45_fpFusedAddSubTest_q;
fracRPreExcSubtraction_uid115_fpFusedAddSubTest_combproc: PROCESS (fracRPreExcSubtraction_uid115_fpFusedAddSubTest_s, fracRPreExcSub_uid85_fpFusedAddSubTest_b, fracRPreExcAdd_uid88_fpFusedAddSubTest_b)
BEGIN
CASE (fracRPreExcSubtraction_uid115_fpFusedAddSubTest_s) IS
WHEN "0" => fracRPreExcSubtraction_uid115_fpFusedAddSubTest_q <= fracRPreExcSub_uid85_fpFusedAddSubTest_b;
WHEN "1" => fracRPreExcSubtraction_uid115_fpFusedAddSubTest_q <= fracRPreExcAdd_uid88_fpFusedAddSubTest_b;
WHEN OTHERS => fracRPreExcSubtraction_uid115_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- fracRPostExcSub_uid140_fpFusedAddSubTest(MUX,139)@1
fracRPostExcSub_uid140_fpFusedAddSubTest_s <= excREncSub_uid111_fpFusedAddSubTest_q;
fracRPostExcSub_uid140_fpFusedAddSubTest_combproc: PROCESS (fracRPostExcSub_uid140_fpFusedAddSubTest_s, cstZeroWF_uid12_fpFusedAddSubTest_q, fracRPreExcSubtraction_uid115_fpFusedAddSubTest_q, oneFracRPostExc2_uid117_fpFusedAddSubTest_q)
BEGIN
CASE (fracRPostExcSub_uid140_fpFusedAddSubTest_s) IS
WHEN "00" => fracRPostExcSub_uid140_fpFusedAddSubTest_q <= cstZeroWF_uid12_fpFusedAddSubTest_q;
WHEN "01" => fracRPostExcSub_uid140_fpFusedAddSubTest_q <= fracRPreExcSubtraction_uid115_fpFusedAddSubTest_q;
WHEN "10" => fracRPostExcSub_uid140_fpFusedAddSubTest_q <= cstZeroWF_uid12_fpFusedAddSubTest_q;
WHEN "11" => fracRPostExcSub_uid140_fpFusedAddSubTest_q <= oneFracRPostExc2_uid117_fpFusedAddSubTest_q;
WHEN OTHERS => fracRPostExcSub_uid140_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- RDiff_uid158_fpFusedAddSubTest(BITJOIN,157)@1
RDiff_uid158_fpFusedAddSubTest_q <= signRPostExcSub_uid157_fpFusedAddSubTest_q & expRPostExcSub_uid144_fpFusedAddSubTest_q & fracRPostExcSub_uid140_fpFusedAddSubTest_q;
-- invSigA_uid126_fpFusedAddSubTest(LOGICAL,125)@1
invSigA_uid126_fpFusedAddSubTest_q <= not (sigA_uid43_fpFusedAddSubTest_b);
-- signInputsZeroSwap_uid127_fpFusedAddSubTest(LOGICAL,126)@1
signInputsZeroSwap_uid127_fpFusedAddSubTest_q <= excZ_siga_uid9_uid16_fpFusedAddSubTest_q and excZ_sigb_uid10_uid30_fpFusedAddSubTest_q and invSigA_uid126_fpFusedAddSubTest_q and sigB_uid44_fpFusedAddSubTest_b and invXGTEy_uid125_fpFusedAddSubTest_q;
-- invSignInputsZeroSwap_uid128_fpFusedAddSubTest(LOGICAL,127)@1
invSignInputsZeroSwap_uid128_fpFusedAddSubTest_q <= not (signInputsZeroSwap_uid127_fpFusedAddSubTest_q);
-- invSigB_uid129_fpFusedAddSubTest(LOGICAL,128)@1
invSigB_uid129_fpFusedAddSubTest_q <= not (sigB_uid44_fpFusedAddSubTest_b);
-- signInputsZeroNoSwap_uid130_fpFusedAddSubTest(LOGICAL,129)@1
signInputsZeroNoSwap_uid130_fpFusedAddSubTest_q <= excZ_siga_uid9_uid16_fpFusedAddSubTest_q and excZ_sigb_uid10_uid30_fpFusedAddSubTest_q and sigA_uid43_fpFusedAddSubTest_b and invSigB_uid129_fpFusedAddSubTest_q and xGTEy_uid8_fpFusedAddSubTest_n;
-- invSignInputsZeroNoSwap_uid131_fpFusedAddSubTest(LOGICAL,130)@1
invSignInputsZeroNoSwap_uid131_fpFusedAddSubTest_q <= not (signInputsZeroNoSwap_uid130_fpFusedAddSubTest_q);
-- aMa_uid132_fpFusedAddSubTest(LOGICAL,131)@1
aMa_uid132_fpFusedAddSubTest_q <= aMinusA_uid72_fpFusedAddSubTest_q and effSub_uid45_fpFusedAddSubTest_q;
-- invAMA_uid133_fpFusedAddSubTest(LOGICAL,132)@1
invAMA_uid133_fpFusedAddSubTest_q <= not (aMa_uid132_fpFusedAddSubTest_q);
-- infMinf_uid104_fpFusedAddSubTest(LOGICAL,103)@1
infMinf_uid104_fpFusedAddSubTest_q <= excI_siga_uid20_fpFusedAddSubTest_q and excI_sigb_uid34_fpFusedAddSubTest_q and effSub_uid45_fpFusedAddSubTest_q;
-- excRNaNA_uid105_fpFusedAddSubTest(LOGICAL,104)@1
excRNaNA_uid105_fpFusedAddSubTest_q <= infMinf_uid104_fpFusedAddSubTest_q or excN_siga_uid21_fpFusedAddSubTest_q or excN_sigb_uid35_fpFusedAddSubTest_q;
-- invExcRNaNA_uid134_fpFusedAddSubTest(LOGICAL,133)@1
invExcRNaNA_uid134_fpFusedAddSubTest_q <= not (excRNaNA_uid105_fpFusedAddSubTest_q);
-- signRPostExc_uid135_fpFusedAddSubTest(LOGICAL,134)@1
signRPostExc_uid135_fpFusedAddSubTest_q <= invExcRNaNA_uid134_fpFusedAddSubTest_q and sigA_uid43_fpFusedAddSubTest_b and invAMA_uid133_fpFusedAddSubTest_q and invSignInputsZeroNoSwap_uid131_fpFusedAddSubTest_q and invSignInputsZeroSwap_uid128_fpFusedAddSubTest_q;
-- expRPreExcAddition_uid114_fpFusedAddSubTest(MUX,113)@1
expRPreExcAddition_uid114_fpFusedAddSubTest_s <= effSub_uid45_fpFusedAddSubTest_q;
expRPreExcAddition_uid114_fpFusedAddSubTest_combproc: PROCESS (expRPreExcAddition_uid114_fpFusedAddSubTest_s, expRPreExcAdd_uid89_fpFusedAddSubTest_b, expRPreExcSub_uid86_fpFusedAddSubTest_b)
BEGIN
CASE (expRPreExcAddition_uid114_fpFusedAddSubTest_s) IS
WHEN "0" => expRPreExcAddition_uid114_fpFusedAddSubTest_q <= expRPreExcAdd_uid89_fpFusedAddSubTest_b;
WHEN "1" => expRPreExcAddition_uid114_fpFusedAddSubTest_q <= expRPreExcSub_uid86_fpFusedAddSubTest_b;
WHEN OTHERS => expRPreExcAddition_uid114_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- excRInfAdd_uid100_fpFusedAddSubTest(LOOKUP,99)@1
excRInfAdd_uid100_fpFusedAddSubTest_combproc: PROCESS (excRInfVInC_uid99_fpFusedAddSubTest_q)
BEGIN
-- Begin reserved scope level
CASE (excRInfVInC_uid99_fpFusedAddSubTest_q) IS
WHEN "000000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "000001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "000010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "000011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "000100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "000101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "000110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "1";
WHEN "000111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "001000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "001001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "001010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "001011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "001100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "1";
WHEN "001101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "1";
WHEN "001110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "001111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "010000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "010001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "010010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "1";
WHEN "010011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "1";
WHEN "010100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "010101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "010110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "010111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "011111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "100000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "1";
WHEN "100001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "100010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "100011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "100100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "100101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "100110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "100111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "101111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "110111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111000" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111001" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111010" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111011" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111100" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111101" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111110" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN "111111" => excRInfAdd_uid100_fpFusedAddSubTest_q <= "0";
WHEN OTHERS => -- unreachable
excRInfAdd_uid100_fpFusedAddSubTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- excRInfAddFull_uid101_fpFusedAddSubTest(LOGICAL,100)@1
excRInfAddFull_uid101_fpFusedAddSubTest_q <= addIsAlsoInf_uid98_fpFusedAddSubTest_q or excRInfAdd_uid100_fpFusedAddSubTest_q;
-- excRZeroAdd_uid93_fpFusedAddSubTest(LOOKUP,92)@1
excRZeroAdd_uid93_fpFusedAddSubTest_combproc: PROCESS (excRZeroVInC_uid92_fpFusedAddSubTest_q)
BEGIN
-- Begin reserved scope level
CASE (excRZeroVInC_uid92_fpFusedAddSubTest_q) IS
WHEN "000000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "000001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "000010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "000011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "1";
WHEN "000100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "000101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "000110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "000111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "001111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "010111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "011111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "100111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "101000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "101001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "101010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "101011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "101100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "1";
WHEN "101101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "101110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "101111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "110000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "110001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "110010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "110011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "110100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "1";
WHEN "110101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "110110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "110111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "111000" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "111001" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "111010" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "111011" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "111100" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "1";
WHEN "111101" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "111110" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN "111111" => excRZeroAdd_uid93_fpFusedAddSubTest_q <= "0";
WHEN OTHERS => -- unreachable
excRZeroAdd_uid93_fpFusedAddSubTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- concExcAdd_uid110_fpFusedAddSubTest(BITJOIN,109)@1
concExcAdd_uid110_fpFusedAddSubTest_q <= excRNaNA_uid105_fpFusedAddSubTest_q & excRInfAddFull_uid101_fpFusedAddSubTest_q & excRZeroAdd_uid93_fpFusedAddSubTest_q;
-- excREncAdd_uid112_fpFusedAddSubTest(LOOKUP,111)@1
excREncAdd_uid112_fpFusedAddSubTest_combproc: PROCESS (concExcAdd_uid110_fpFusedAddSubTest_q)
BEGIN
-- Begin reserved scope level
CASE (concExcAdd_uid110_fpFusedAddSubTest_q) IS
WHEN "000" => excREncAdd_uid112_fpFusedAddSubTest_q <= "01";
WHEN "001" => excREncAdd_uid112_fpFusedAddSubTest_q <= "00";
WHEN "010" => excREncAdd_uid112_fpFusedAddSubTest_q <= "10";
WHEN "011" => excREncAdd_uid112_fpFusedAddSubTest_q <= "00";
WHEN "100" => excREncAdd_uid112_fpFusedAddSubTest_q <= "11";
WHEN "101" => excREncAdd_uid112_fpFusedAddSubTest_q <= "00";
WHEN "110" => excREncAdd_uid112_fpFusedAddSubTest_q <= "00";
WHEN "111" => excREncAdd_uid112_fpFusedAddSubTest_q <= "00";
WHEN OTHERS => -- unreachable
excREncAdd_uid112_fpFusedAddSubTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- expRPostExcAdd_uid124_fpFusedAddSubTest(MUX,123)@1
expRPostExcAdd_uid124_fpFusedAddSubTest_s <= excREncAdd_uid112_fpFusedAddSubTest_q;
expRPostExcAdd_uid124_fpFusedAddSubTest_combproc: PROCESS (expRPostExcAdd_uid124_fpFusedAddSubTest_s, cstAllZWE_uid13_fpFusedAddSubTest_q, expRPreExcAddition_uid114_fpFusedAddSubTest_q, cstAllOWE_uid11_fpFusedAddSubTest_q)
BEGIN
CASE (expRPostExcAdd_uid124_fpFusedAddSubTest_s) IS
WHEN "00" => expRPostExcAdd_uid124_fpFusedAddSubTest_q <= cstAllZWE_uid13_fpFusedAddSubTest_q;
WHEN "01" => expRPostExcAdd_uid124_fpFusedAddSubTest_q <= expRPreExcAddition_uid114_fpFusedAddSubTest_q;
WHEN "10" => expRPostExcAdd_uid124_fpFusedAddSubTest_q <= cstAllOWE_uid11_fpFusedAddSubTest_q;
WHEN "11" => expRPostExcAdd_uid124_fpFusedAddSubTest_q <= cstAllOWE_uid11_fpFusedAddSubTest_q;
WHEN OTHERS => expRPostExcAdd_uid124_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- fracRPreExcAddition_uid113_fpFusedAddSubTest(MUX,112)@1
fracRPreExcAddition_uid113_fpFusedAddSubTest_s <= effSub_uid45_fpFusedAddSubTest_q;
fracRPreExcAddition_uid113_fpFusedAddSubTest_combproc: PROCESS (fracRPreExcAddition_uid113_fpFusedAddSubTest_s, fracRPreExcAdd_uid88_fpFusedAddSubTest_b, fracRPreExcSub_uid85_fpFusedAddSubTest_b)
BEGIN
CASE (fracRPreExcAddition_uid113_fpFusedAddSubTest_s) IS
WHEN "0" => fracRPreExcAddition_uid113_fpFusedAddSubTest_q <= fracRPreExcAdd_uid88_fpFusedAddSubTest_b;
WHEN "1" => fracRPreExcAddition_uid113_fpFusedAddSubTest_q <= fracRPreExcSub_uid85_fpFusedAddSubTest_b;
WHEN OTHERS => fracRPreExcAddition_uid113_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- fracRPostExcAdd_uid120_fpFusedAddSubTest(MUX,119)@1
fracRPostExcAdd_uid120_fpFusedAddSubTest_s <= excREncAdd_uid112_fpFusedAddSubTest_q;
fracRPostExcAdd_uid120_fpFusedAddSubTest_combproc: PROCESS (fracRPostExcAdd_uid120_fpFusedAddSubTest_s, cstZeroWF_uid12_fpFusedAddSubTest_q, fracRPreExcAddition_uid113_fpFusedAddSubTest_q, oneFracRPostExc2_uid117_fpFusedAddSubTest_q)
BEGIN
CASE (fracRPostExcAdd_uid120_fpFusedAddSubTest_s) IS
WHEN "00" => fracRPostExcAdd_uid120_fpFusedAddSubTest_q <= cstZeroWF_uid12_fpFusedAddSubTest_q;
WHEN "01" => fracRPostExcAdd_uid120_fpFusedAddSubTest_q <= fracRPreExcAddition_uid113_fpFusedAddSubTest_q;
WHEN "10" => fracRPostExcAdd_uid120_fpFusedAddSubTest_q <= cstZeroWF_uid12_fpFusedAddSubTest_q;
WHEN "11" => fracRPostExcAdd_uid120_fpFusedAddSubTest_q <= oneFracRPostExc2_uid117_fpFusedAddSubTest_q;
WHEN OTHERS => fracRPostExcAdd_uid120_fpFusedAddSubTest_q <= (others => '0');
END CASE;
END PROCESS;
-- RSum_uid136_fpFusedAddSubTest(BITJOIN,135)@1
RSum_uid136_fpFusedAddSubTest_q <= signRPostExc_uid135_fpFusedAddSubTest_q & expRPostExcAdd_uid124_fpFusedAddSubTest_q & fracRPostExcAdd_uid120_fpFusedAddSubTest_q;
-- xOut(GPOUT,4)@1
q <= RSum_uid136_fpFusedAddSubTest_q;
s <= RDiff_uid158_fpFusedAddSubTest_q;
END normal;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- opb_hwti.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ** YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE SOLELY **
-- ** WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR **
-- ** CREATE IP MODULES SOLELY FOR XILINX PROGRAMMABLE LOGIC DEVICES AND **
-- ** XILINX EDK SYSTEM. NO RIGHTS ARE GRANTED TO DISTRIBUTE ANY FILES **
-- ** UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: opb_hwti.vhd
-- Version: 2.00.a
-- Description: Top level design, instantiates IPIF and user logic.
-- Date: Mon Aug 15 10:20:24 2005 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.all;
library fsl_v20_v2_11_c;
use fsl_v20_v2_11_c.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_OPB_AWIDTH -- OPB address bus width
-- C_OPB_DWIDTH -- OPB data bus width
-- C_FAMILY -- Target FPGA architecture
--
-- Definition of Ports:
-- OPB_Clk -- OPB Clock
-- OPB_Rst -- OPB Reset
-- Sl_DBus -- Slave data bus
-- Sl_errAck -- Slave error acknowledge
-- Sl_retry -- Slave retry
-- Sl_toutSup -- Slave timeout suppress
-- Sl_xferAck -- Slave transfer acknowledge
-- OPB_ABus -- OPB address bus
-- OPB_BE -- OPB byte enable
-- OPB_DBus -- OPB data bus
-- OPB_RNW -- OPB read/not write
-- OPB_select -- OPB select
-- OPB_seqAddr -- OPB sequential address
-- M_ABus -- Master address bus
-- M_BE -- Master byte enables
-- M_busLock -- Master buslock
-- M_request -- Master bus request
-- M_RNW -- Master read, not write
-- M_select -- Master select
-- M_seqAddr -- Master sequential address
-- OPB_errAck -- OPB error acknowledge
-- OPB_MGrant -- OPB bus grant
-- OPB_retry -- OPB bus cycle retry
-- OPB_timeout -- OPB timeout error
-- OPB_xferAck -- OPB transfer acknowledge
------------------------------------------------------------------------------
entity opb_hwti is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_THREAD_MANAGER_BADDR : std_logic_vector(0 to 31) := x"6000_0000";
C_MUTEX_MANAGER_BADDR : std_logic_vector(0 to 31) := x"7500_0000";
C_CONVAR_MANAGER_BADDR : std_logic_vector(0 to 31) := x"7600_0000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"6300_0000";
C_HIGHADDR : std_logic_vector := X"6300_FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
OPBintrfc2thrd_value : out std_logic_vector(0 to 31);
OPBintrfc2thrd_function : out std_logic_vector(0 to 15);
OPBintrfc2thrd_goWait : out std_logic;
OPBthrd2intrfc_address : out std_logic_vector(0 to 31);
OPBthrd2intrfc_value : out std_logic_vector(0 to 31);
OPBthrd2intrfc_function : out std_logic_vector(0 to 15);
OPBthrd2intrfc_opcode : out std_logic_vector(0 to 5);
OPBM_ABus : out std_logic_vector(0 to 31);
OPBM_request :out std_logic;
OPBM_MGrant : out std_logic;
OPBM_xferAck : out std_logic;
OPBM_select : out std_logic ;
OPBtimer : out std_logic_vector(0 to 31);
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic;
FSL2_S_Read : out std_logic;
FSL2_S_Data : in std_logic_vector(0 to 31);
FSL2_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
FSL1_M_Write : out std_logic;
FSL1_M_Data : out std_logic_vector(0 to 31);
FSL1_M_Full : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
Sl_errAck : out std_logic;
Sl_retry : out std_logic;
Sl_toutSup : out std_logic;
Sl_xferAck : out std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
M_busLock : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_select : out std_logic;
M_seqAddr : out std_logic;
OPB_errAck : in std_logic;
OPB_MGrant : in std_logic;
OPB_retry : in std_logic;
OPB_timeout : in std_logic;
OPB_xferAck : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "Clk";
attribute SIGIS of OPB_Rst : signal is "Rst";
end entity opb_hwti;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of opb_hwti is
component user_logic_hwti is
generic (
C_BASEADDR : std_logic_vector := X"6300_0000";
C_HIGHADDR : std_logic_vector := X"6300_FFFF";
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_FAMILY : string := "virtex2p";
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_THREAD_MANAGER_BADDR : std_logic_vector(0 to 31) := x"6000_0000";
C_MUTEX_MANAGER_BADDR : std_logic_vector(0 to 31) := x"7500_0000";
C_CONVAR_MANAGER_BADDR : std_logic_vector(0 to 31) := x"7600_0000"
);
port
(
OPBtimer : out std_logic_vector(0 to 31);
--CONTROL : in STD_LOGIC_VECTOR(35 DOWNTO 0);
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Clk : in std_logic;
Bus2IP_CS : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_RdCE : in std_logic_vector(0 to 3);
Bus2IP_Reset : in std_logic;
Bus2IP_WrCE : in std_logic_vector(0 to 3);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_Ack : out std_logic;
IP2Bus_Data : out std_logic_vector(0 to 31);
IP2Bus_Error : out std_logic;
IP2Bus_PostedWrInh : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_ToutSup : out std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to 31);
IP2Bus_MstBE : out std_logic_vector(0 to 3);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to 31);
intrfc2thrd : out std_logic_vector(0 to 63);
thrd2intrfc : in std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic;
full : in std_logic
);
end component user_logic_hwti;
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant USER_MASTER : integer := USER_10;
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_MASTER -- user logic master space (ip master model registers)
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
-- constant MASTER_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant MASTER_BASEADDR : std_logic_vector := C_BASEADDR;
-- constant MASTER_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant MASTER_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & MASTER_BASEADDR, -- user logic master space base address
ZERO_ADDR_PAD & MASTER_HIGHADDR -- user logic master space high address
);
-- specify data width for each target address range.
constant USER_DWIDTH : integer := 32;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_DWIDTH -- user logic master space data width
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant USER_NUM_MASTER_CE : integer := 4;
constant USER_NUM_CE : integer := USER_NUM_MASTER_CE;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_NUM_MASTER_CE) -- number of chip enables for user logic master space (one per register)
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0) -- user logic master space dependent properties (none defined)
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the opb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- opb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 0;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 64.
constant DEV_MAX_BURST_SIZE : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a opb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of opb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify arbitration scheme if both dma and user-logic masters are present,
-- following schemes are supported:
-- 0 - FAIR
-- 1 - DMA_PRIORITY
-- 2 - IP_PRIORITY
constant MASTER_ARB_MODEL : integer := 0;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify the size (must be power of 2) of burst that dma uses to
-- tranfer data on the bus, a value of one causes dma to use single
-- transactions (burst disabled).
constant DMA_BURST_SIZE : integer := 16;
-- specify whether to transfer the dma remanining data as a series of
-- single transactions or as a short burst.
constant DMA_SHORT_BURST_REMAINDER : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma (usually left at
-- default value), apply to software design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000000;
-- specify period of the opb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant OPB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the opb data bus width.
constant IPIF_DWIDTH : integer := C_OPB_DWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_OPB_AWIDTH;
-- specify number of chip selects for user logic slave/master spaces.
constant USER_NUM_CS : integer := 1;
constant USER_CS_INDEX : integer := get_id_index(ARD_ID_ARRAY, USER_MASTER);
-- specify index for user logic slave/master spaces chip enable.
constant USER_MASTER_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, get_id_index(ARD_ID_ARRAY, USER_MASTER));
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iIP2Bus_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal iBus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
signal iBus2IP_Data : std_logic_vector(0 to IPIF_DWIDTH - 1);
signal iBus2IP_CS : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Data : std_logic_vector(0 to IPIF_DWIDTH-1) := (others => '0');
signal iIP2Bus_Ack : std_logic := '0';
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iIP2Bus_PostedWrInh : std_logic := '0';
signal iIP2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1) := (others => '0');
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to 31) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_MstBE : std_logic_vector(0 to (C_OPB_DWIDTH/8) - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal iBus2IP_BE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1);
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal iBus2IP_RNW : std_logic;
signal uBus2IP_BE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal uBus2IP_CS : std_logic_vector(0 to USER_NUM_CS-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
-- HWTI to HWTUL interconnect
signal intrfc2thrd : std_logic_vector(0 to 63);
signal thrd2intrfc : std_logic_vector( 0 to 95);
signal rd : std_logic;
signal wr : std_logic;
signal exist : std_logic;
signal full : std_logic;
signal internal_M_ABus : std_logic_vector(0 to 31);
signal internal_M_request : std_logic;
signal internal_M_select : std_logic;
signal internal_M_RNW : std_logic;
begin
OPBM_ABus <= internal_M_ABus ;
OPBM_request <= internal_M_request;
OPBM_select <= internal_M_RNW;
OPBM_MGrant <= OPB_MGrant;
OPBM_xferAck <= OPB_xferAck;
M_RNW <= internal_M_RNW;
M_ABus <= internal_M_ABus ;
M_request <= internal_M_request;
M_select <= internal_M_select;
OPBintrfc2thrd_value <= intrfc2thrd(0 to 31) ;
OPBintrfc2thrd_function <= intrfc2thrd (32 to 47);
OPBintrfc2thrd_goWait <= intrfc2thrd (48) ;
OPBthrd2intrfc_address <= thrd2intrfc (32 to 63);
OPBthrd2intrfc_value <= thrd2intrfc (0 to 31) ;
OPBthrd2intrfc_function <= thrd2intrfc (64 to 79);
OPBthrd2intrfc_opcode <= thrd2intrfc (80 to 85);
--=======================================================
thrd2intrfc <= FSL0_S_Data & FSL1_S_Data &FSL2_S_Data;
FSL0_M_Data <= intrfc2thrd(0 to 31);
FSL1_M_Data <= intrfc2thrd(32 to 63);
--=======================================================
full <= FSL0_M_Full or FSL1_M_Full ;
exist <= FSL0_S_Exists and FSL1_S_Exists and FSL2_S_Exists;
--=======================================================
FSL0_S_Read <= rd;
FSL1_S_Read <= rd;
FSL2_S_Read <= rd;
FSL0_M_Write <= wr;
FSL1_M_Write <= wr;
------------------------------------------
-- instantiate the OPB IPIF
------------------------------------------
OPB_IPIF_I : entity opb_ipif_v2_00_h.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_MASTER_ARB_MODEL => MASTER_ARB_MODEL,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_BURST_SIZE => DMA_BURST_SIZE,
C_DMA_SHORT_BURST_REMAINDER => DMA_SHORT_BURST_REMAINDER,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_CLK_PERIOD_PS => OPB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
OPB_ABus => OPB_ABus,
OPB_DBus => OPB_DBus,
Sln_DBus => Sl_DBus,
Mn_ABus => internal_M_ABus,
IP2Bus_Addr => iIP2Bus_Addr,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => iBus2IP_RNW,
Bus2IP_CS => iBus2IP_CS,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => iIP2Bus_PostedWrInh,
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2IP_Addr => iIP2IP_Addr,
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrReq => '0',
IP2RFIFO_WrRestore => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_IPMstTrans => open,
Bus2IP_Burst => open,
Mn_request => internal_M_request,
Mn_busLock => M_busLock,
Mn_select => internal_M_select,
Mn_RNW => internal_M_RNW,
Mn_BE => M_BE,
Mn_seqAddr => M_seqAddr,
OPB_MnGrant => OPB_MGrant,
OPB_xferAck => OPB_xferAck,
OPB_errAck => OPB_errAck,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
Freeze => '0',
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_BE => OPB_BE,
Sln_xferAck => Sl_xferAck,
Sln_errAck => Sl_errAck,
Sln_toutSup => Sl_toutSup,
Sln_retry => Sl_retry,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Data => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_DMA_Ack => open,
Bus2IP_Freeze => open,
Bus2IP_Reset => iBus2IP_Reset,
IP2Bus_Clk => '0',
IP2Bus_DMA_Req => '0',
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2INTC_Irpt => open,
OPB_Clk => OPB_Clk,
Reset => OPB_Rst
);
------------------------------------------
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_HWTI_I : user_logic_hwti
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_FAMILY => C_FAMILY,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_THREAD_MANAGER_BADDR => C_THREAD_MANAGER_BADDR,
C_MUTEX_MANAGER_BADDR => C_MUTEX_MANAGER_BADDR,
C_CONVAR_MANAGER_BADDR => C_CONVAR_MANAGER_BADDR
)
port map
(
OPBtimer => OPBtimer,
--CONTROL => CONTROL ,
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
-- Bus2IP_BE => uBus2IP_BE,
Bus2IP_CS => uBus2IP_CS(0),
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => iIP2Bus_PostedWrInh,
IP2Bus_Ack => iIP2Bus_Ack,
-- IP2Bus_RdAck => iIP2Bus_RdAck,
-- IP2Bus_WrAck => iIP2Bus_WrAck,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => uIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr,
intrfc2thrd => intrfc2thrd,
thrd2intrfc => thrd2intrfc,
rd => rd,
wr => wr,
exist => exist,
full => full
);
------------------------------------------
-- hooking up signal slicing
------------------------------------------
iIP2Bus_MstBE <= uIP2Bus_MstBE;
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE(0 to USER_DWIDTH/8-1);
uBus2IP_CS <= iBus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_CS-1);
uBus2IP_RdCE(0 to USER_NUM_MASTER_CE-1) <= iBus2IP_RdCE(USER_MASTER_CE_INDEX to USER_MASTER_CE_INDEX+USER_NUM_MASTER_CE-1);
uBus2IP_WrCE(0 to USER_NUM_MASTER_CE-1) <= iBus2IP_WrCE(USER_MASTER_CE_INDEX to USER_MASTER_CE_INDEX+USER_NUM_MASTER_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
iIP2Bus_RdAck <= iIP2Bus_Ack and iBus2IP_RNW;
iIP2Bus_WrAck <= iIP2Bus_Ack and (not iBus2IP_RNW);
end IMP;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
clock : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNVJUPFOX3 is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "000000000000000000000000";
WIDTH : positive := 24
);
port (
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector(24-1 downto 0);
output : out std_logic_vector(24-1 downto 0);
sclr : in std_logic
);
end component alt_dspbuilder_delay_GNVJUPFOX3;
begin
alt_dspbuilder_delay_GNVJUPFOX3_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "000000000000000000000000") and (WIDTH = 24)) generate
inst_alt_dspbuilder_delay_GNVJUPFOX3_0: alt_dspbuilder_delay_GNVJUPFOX3
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "000000000000000000000000", WIDTH => 24)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "000000000000000000000000") and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0);
clock : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNVJUPFOX3 is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "000000000000000000000000";
WIDTH : positive := 24
);
port (
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector(24-1 downto 0);
output : out std_logic_vector(24-1 downto 0);
sclr : in std_logic
);
end component alt_dspbuilder_delay_GNVJUPFOX3;
begin
alt_dspbuilder_delay_GNVJUPFOX3_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "000000000000000000000000") and (WIDTH = 24)) generate
inst_alt_dspbuilder_delay_GNVJUPFOX3_0: alt_dspbuilder_delay_GNVJUPFOX3
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "000000000000000000000000", WIDTH => 24)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "000000000000000000000000") and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_6 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_6;
architecture xilinx of blk_mem_gen_v8_3_6 is
begin
end
architecture xilinx;
|
----------------------------------------------------------------
-- CROSSBAR
-- --------------
-- DATA_AV ->| |
-- DATA_IN ->| |
-- DATA_ACK <-| |-> TX
-- SENDER ->| |-> DATA_OUT
-- FREE ->| |<- CREDIT_I
-- TAB_IN ->| |
-- TAB_OUT ->| |
-- --------------
----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.PhoenixPackage.all;
entity Phoenix_crossbar is
port(
data_av: in regNport;
data_in: in arrayNport_regflit;
data_ack: out regNport;
sender: in regNport;
free: in regNport;
tab_in: in arrayNport_reg3;
tab_out: in arrayNport_reg3;
tx: out regNport;
data_out: out arrayNport_regflit;
credit_i: in regNport;
retransmission_i: in regNport;
retransmission_in_buf: out regNport);
end Phoenix_crossbar;
architecture Phoenix_crossbar of Phoenix_crossbar is
begin
----------------------------------------------------------------------------------
-- PORTA LOCAL
----------------------------------------------------------------------------------
tx(LOCAL) <= data_av(EAST) when tab_out(LOCAL)="000" and free(LOCAL)='0' else
data_av(WEST) when tab_out(LOCAL)="001" and free(LOCAL)='0' else
data_av(NORTH) when tab_out(LOCAL)="010" and free(LOCAL)='0' else
data_av(SOUTH) when tab_out(LOCAL)="011" and free(LOCAL)='0' else
data_av(LOCAL) when tab_out(LOCAL)="100" and free(LOCAL)='0' else
'0';
data_out(LOCAL) <= data_in(EAST) when tab_out(LOCAL)="000" and free(LOCAL)='0' else
data_in(WEST) when tab_out(LOCAL)="001" and free(LOCAL)='0' else
data_in(NORTH) when tab_out(LOCAL)="010" and free(LOCAL)='0' else
data_in(SOUTH) when tab_out(LOCAL)="011" and free(LOCAL)='0' else
data_in(LOCAL) when tab_out(LOCAL)="100" and free(LOCAL)='0' else
(others=>'0');
data_ack(LOCAL) <= credit_i(EAST) when tab_in(LOCAL)="000" and data_av(LOCAL)='1' else
credit_i(WEST) when tab_in(LOCAL)="001" and data_av(LOCAL)='1' else
credit_i(NORTH) when tab_in(LOCAL)="010" and data_av(LOCAL)='1' else
credit_i(SOUTH) when tab_in(LOCAL)="011" and data_av(LOCAL)='1' else
credit_i(LOCAL) when tab_in(LOCAL)="100" and data_av(LOCAL)='1' else
'0';
retransmission_in_buf(LOCAL) <= retransmission_i(EAST) when tab_in(LOCAL)="000" and data_av(LOCAL)='1' else
retransmission_i(WEST) when tab_in(LOCAL)="001" and data_av(LOCAL)='1' else
retransmission_i(NORTH) when tab_in(LOCAL)="010" and data_av(LOCAL)='1' else
retransmission_i(SOUTH) when tab_in(LOCAL)="011" and data_av(LOCAL)='1' else
retransmission_i(LOCAL) when tab_in(LOCAL)="100" and data_av(LOCAL)='1' else
'0';
----------------------------------------------------------------------------------
-- PORTA EAST
----------------------------------------------------------------------------------
tx(EAST) <= data_av(WEST) when tab_out(EAST)="001" and free(EAST)='0' else
data_av(NORTH) when tab_out(EAST)="010" and free(EAST)='0' else
data_av(SOUTH) when tab_out(EAST)="011" and free(EAST)='0' else
data_av(LOCAL) when tab_out(EAST)="100" and free(EAST)='0' else
'0';
data_out(EAST) <= data_in(WEST) when tab_out(EAST)="001" and free(EAST)='0' else
data_in(NORTH) when tab_out(EAST)="010" and free(EAST)='0' else
data_in(SOUTH) when tab_out(EAST)="011" and free(EAST)='0' else
data_in(LOCAL) when tab_out(EAST)="100" and free(EAST)='0' else
(others=>'0');
data_ack(EAST) <= credit_i(WEST) when tab_in(EAST)="001" and data_av(EAST)='1' else
credit_i(NORTH) when tab_in(EAST)="010" and data_av(EAST)='1' else
credit_i(SOUTH) when tab_in(EAST)="011" and data_av(EAST)='1' else
credit_i(LOCAL) when tab_in(EAST)="100" and data_av(EAST)='1' else
'0';
retransmission_in_buf(EAST) <= retransmission_i(WEST) when tab_in(EAST)="001" and data_av(EAST)='1' else
retransmission_i(NORTH) when tab_in(EAST)="010" and data_av(EAST)='1' else
retransmission_i(SOUTH) when tab_in(EAST)="011" and data_av(EAST)='1' else
retransmission_i(LOCAL) when tab_in(EAST)="100" and data_av(EAST)='1' else
'0';
----------------------------------------------------------------------------------
-- PORTA WEST
----------------------------------------------------------------------------------
tx(WEST) <= data_av(EAST) when tab_out(WEST)="000" and free(WEST)='0' else
data_av(NORTH) when tab_out(WEST)="010" and free(WEST)='0' else
data_av(SOUTH) when tab_out(WEST)="011" and free(WEST)='0' else
data_av(LOCAL) when tab_out(WEST)="100" and free(WEST)='0' else
'0';
data_out(WEST) <= data_in(EAST) when tab_out(WEST)="000" and free(WEST)='0' else
data_in(NORTH) when tab_out(WEST)="010" and free(WEST)='0' else
data_in(SOUTH) when tab_out(WEST)="011" and free(WEST)='0' else
data_in(LOCAL) when tab_out(WEST)="100" and free(WEST)='0' else
(others=>'0');
data_ack(WEST) <= credit_i(EAST) when tab_in(WEST)="000" and data_av(WEST)='1' else
credit_i(NORTH) when tab_in(WEST)="010" and data_av(WEST)='1' else
credit_i(SOUTH) when tab_in(WEST)="011" and data_av(WEST)='1' else
credit_i(LOCAL) when tab_in(WEST)="100" and data_av(WEST)='1' else
'0';
retransmission_in_buf(WEST) <= retransmission_i(EAST) when tab_in(WEST)="000" and data_av(WEST)='1' else
retransmission_i(NORTH) when tab_in(WEST)="010" and data_av(WEST)='1' else
retransmission_i(SOUTH) when tab_in(WEST)="011" and data_av(WEST)='1' else
retransmission_i(LOCAL) when tab_in(WEST)="100" and data_av(WEST)='1' else
'0';
----------------------------------------------------------------------------------
-- PORTA NORTH
----------------------------------------------------------------------------------
tx(NORTH) <= data_av(EAST) when tab_out(NORTH)="000" and free(NORTH)='0' else
data_av(WEST) when tab_out(NORTH)="001" and free(NORTH)='0' else
data_av(SOUTH) when tab_out(NORTH)="011" and free(NORTH)='0' else
data_av(LOCAL) when tab_out(NORTH)="100" and free(NORTH)='0' else
'0';
data_out(NORTH) <= data_in(EAST) when tab_out(NORTH)="000" and free(NORTH)='0' else
data_in(WEST) when tab_out(NORTH)="001" and free(NORTH)='0' else
data_in(SOUTH) when tab_out(NORTH)="011" and free(NORTH)='0' else
data_in(LOCAL) when tab_out(NORTH)="100" and free(NORTH)='0' else
(others=>'0');
data_ack(NORTH) <= credit_i(EAST) when tab_in(NORTH)="000" and data_av(NORTH)='1' else
credit_i(WEST) when tab_in(NORTH)="001" and data_av(NORTH)='1' else
credit_i(SOUTH) when tab_in(NORTH)="011" and data_av(NORTH)='1' else
credit_i(LOCAL) when tab_in(NORTH)="100" and data_av(NORTH)='1' else
'0';
retransmission_in_buf(NORTH) <= retransmission_i(EAST) when tab_in(NORTH)="000" and data_av(NORTH)='1' else
retransmission_i(WEST) when tab_in(NORTH)="001" and data_av(NORTH)='1' else
retransmission_i(SOUTH) when tab_in(NORTH)="011" and data_av(NORTH)='1' else
retransmission_i(LOCAL) when tab_in(NORTH)="100" and data_av(NORTH)='1' else
'0';
----------------------------------------------------------------------------------
-- PORTA SOUTH
----------------------------------------------------------------------------------
tx(SOUTH) <= data_av(EAST) when tab_out(SOUTH)="000" and free(SOUTH)='0' else
data_av(WEST) when tab_out(SOUTH)="001" and free(SOUTH)='0' else
data_av(NORTH) when tab_out(SOUTH)="010" and free(SOUTH)='0' else
data_av(LOCAL) when tab_out(SOUTH)="100" and free(SOUTH)='0' else
'0';
data_out(SOUTH) <= data_in(EAST) when tab_out(SOUTH)="000" and free(SOUTH)='0' else
data_in(WEST) when tab_out(SOUTH)="001" and free(SOUTH)='0' else
data_in(NORTH) when tab_out(SOUTH)="010" and free(SOUTH)='0' else
data_in(LOCAL) when tab_out(SOUTH)="100" and free(SOUTH)='0' else
(others=>'0');
data_ack(SOUTH) <= credit_i(EAST) when tab_in(SOUTH)="000" and data_av(SOUTH)='1' else
credit_i(WEST) when tab_in(SOUTH)="001" and data_av(SOUTH)='1' else
credit_i(NORTH) when tab_in(SOUTH)="010" and data_av(SOUTH)='1' else
credit_i(LOCAL) when tab_in(SOUTH)="100" and data_av(SOUTH)='1' else
'0';
retransmission_in_buf(SOUTH) <= retransmission_i(EAST) when tab_in(SOUTH)="000" and data_av(SOUTH)='1' else
retransmission_i(WEST) when tab_in(SOUTH)="001" and data_av(SOUTH)='1' else
retransmission_i(NORTH) when tab_in(SOUTH)="010" and data_av(SOUTH)='1' else
retransmission_i(LOCAL) when tab_in(SOUTH)="100" and data_av(SOUTH)='1' else
'0';
end Phoenix_crossbar; |
-- File: BitSelectDemo_TB_V_VHDL.vhd
-- Generated by MyHDL 0.10
-- Date: Wed Aug 29 14:27:58 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_010.all;
entity BitSelectDemo_TB_V_VHDL is
end entity BitSelectDemo_TB_V_VHDL;
-- myHDL -> Verilog/VHDL Testbench
architecture MyHDL of BitSelectDemo_TB_V_VHDL is
signal Index: unsigned(3 downto 0) := 4X"0";
signal Res: unsigned(7 downto 0) := 8X"00";
signal SignRes: signed (7 downto 0) := 8X"00";
signal BitSelectDemo0_0_RefS: signed (7 downto 0);
signal BitSelectDemo0_0_Ref: unsigned(7 downto 0);
begin
BitSelectDemo0_0_RefS <= to_signed(-93, 8);
BitSelectDemo0_0_Ref <= to_unsigned(93, 8);
BITSELECTDEMO_TB_V_VHDL_PRINT_DATA: process (SignRes, Index, Res) is
variable L: line;
begin
write(L, to_hstring(Index));
write(L, string'(" "));
write(L, to_hstring(Res));
write(L, string'(" "));
write(L, to_hstring(unsigned(SignRes)));
writeline(output, L);
end process BITSELECTDEMO_TB_V_VHDL_PRINT_DATA;
BITSELECTDEMO_TB_V_VHDL_BITSELECTDEMO0_0_LOGIC: process (Index, BitSelectDemo0_0_RefS, BitSelectDemo0_0_Ref) is
begin
Res(to_integer(Index)) <= BitSelectDemo0_0_Ref(to_integer(Index));
SignRes(to_integer(Index)) <= BitSelectDemo0_0_RefS(to_integer(Index));
end process BITSELECTDEMO_TB_V_VHDL_BITSELECTDEMO0_0_LOGIC;
BITSELECTDEMO_TB_V_VHDL_STIMULES: process is
begin
for i in 0 to 7-1 loop
Index <= to_unsigned(i, 4);
wait for 1 * 1 ns;
end loop;
assert False report "End of Simulation" severity Failure;
wait;
end process BITSELECTDEMO_TB_V_VHDL_STIMULES;
end architecture MyHDL;
|
--------------------------------------------------------------------------------
--
-- Title : cl_mines.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game block for mines
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.ctrl_types_pkg.array8x8;
use work.ctrl_types_pkg.data3x8;
use work.ctrl_types_pkg.data8x8;
entity cl_mines is
generic(
constant yend : std_logic_vector(4 downto 0); --! Y end area
constant ystart : std_logic_vector(4 downto 0); --! Y start area
constant xend : std_logic_vector(6 downto 0); --! X end area
constant xstart : std_logic_vector(6 downto 0) --! X start area
);
port(
-- system signals:
clk : in std_logic; --! clock
reset : in std_logic; --! system reset
-- vga XoY coordinates:
show_disp : in array8x8; --! show square display
-- vga XoY coordinates:
addr_rnd : in std_logic_vector(4 downto 0); --! address round
display : in std_logic; --! games counter enable
x_char : in std_logic_vector(9 downto 0); --! X line: 0:79
y_char : in std_logic_vector(8 downto 0); --! Y line: 0:29
-- out color scheme:
data_out : out std_logic_vector(7 downto 0); --! send data
rgb : out std_logic_vector(2 downto 0) --! RGB Colour
);
end cl_mines;
architecture cl_mines of cl_mines is
component ctrl_rounds_rom is
port(
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(23 downto 0)
);
end component;
component ctrl_8x16_rom is
port(
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end component;
signal x_in : std_logic_vector(6 downto 0);
signal y_in : std_logic_vector(4 downto 0);
signal x_rev : std_logic_vector(2 downto 0);
signal x_del : std_logic_vector(2 downto 0);
signal x_z : std_logic_vector(2 downto 0);
signal y_charzz : std_logic_vector(3 downto 0);
signal y_charz : std_logic_vector(3 downto 0);
constant color2 : std_logic_vector(2 downto 0):="010";
signal addr_round : std_logic_vector(7 downto 0);
signal data_round : std_logic_vector(23 downto 0);
signal addr_rom2 : std_logic_vector(10 downto 0);
signal data_rom2 : std_logic_vector(7 downto 0);
signal data_box : std_logic_vector(7 downto 0);
signal data_disp : data8x8;
signal data2 : std_logic;
signal x_inz : std_logic_vector(6 downto 0);
signal y_inz : std_logic_vector(4 downto 0);
signal dataxy : std_logic;
begin
y_charz <= y_char(3 downto 0) when rising_edge(clk);
y_charzz <= y_charz when rising_edge(clk);
x_in <= x_char(9 downto 3);
y_in <= y_char(8 downto 4);
x_inz <= x_in after 1 ns when rising_edge(clk);
y_inz <= y_in after 1 ns when rising_edge(clk);
addr_round <= ((not addr_rnd) & (not y_in(2 downto 0))) when (y_in(4 downto 3) = "10");
x_rounds: ctrl_rounds_rom
port map(
clk => clk,
addr => addr_round,
data => data_round
);
x_char_rom2: ctrl_8x16_rom
port map(
clk => clk,
addr => addr_rom2,
data => data_rom2
);
x_gen_round: for ii in 0 to 7 generate
signal conv_3x8 : data3x8;
begin
conv_3x8(ii) <= data_round(23-3*ii downto 21-3*ii);
pr_round_box2: process(clk, reset) is
begin
if reset = '0' then
data_disp(ii) <= x"00";
elsif rising_edge(clk) then
case conv_3x8(ii) is
when "000" => data_disp(ii) <= x"30";
when "001" => data_disp(ii) <= x"31";
when "010" => data_disp(ii) <= x"32";
when "011" => data_disp(ii) <= x"33";
when "100" => data_disp(ii) <= x"34";
when "101" => data_disp(ii) <= x"35";
when "110" => data_disp(ii) <= x"36";
when others => data_disp(ii) <= x"0F";
end case;
end if;
end process;
end generate;
pr_select2: process(clk, reset) is
begin
if reset = '0' then
data_box <= x"00";
elsif rising_edge(clk) then
if (dataxy = '1') then
if (ystart <= y_inz) and (y_inz < yend) then
if x_inz(6 downto 3) = "0010" then
case x_inz(2 downto 0) is
when "000" => data_box <= data_disp(0);
when "001" => data_box <= data_disp(1);
when "010" => data_box <= data_disp(2);
when "011" => data_box <= data_disp(3);
when "100" => data_box <= data_disp(4);
when "101" => data_box <= data_disp(5);
when "110" => data_box <= data_disp(6);
when others => data_box <= data_disp(7);
end case;
else
data_box <= x"00";
end if;
else
data_box <= x"00";
end if;
else
data_box <= x"00";
end if;
end if;
end process;
addr_rom2 <= data_box(6 downto 0) & y_charzz(3 downto 0);
pr_select3: process(clk, reset) is
begin
if reset = '0' then
dataxy <= '0';
elsif rising_edge(clk) then
if display = '0' then
dataxy <= '0';
else
if ((xstart <= x_in) and (x_in < xend)) then
if ((ystart <= y_in) and (y_in < yend)) then
dataxy <= show_disp(conv_integer(x_in(2 downto 0)))(conv_integer(y_in(2 downto 0)));
else
dataxy <= '0';
end if;
else
dataxy <= '0';
end if;
end if;
end if;
end process;
data_out <= data_box;
g_rev: for ii in 0 to 2 generate
begin
x_rev(ii) <= not x_char(ii) when rising_edge(clk);
end generate;
x_del <= x_rev when rising_edge(clk);
x_z <= x_del when rising_edge(clk);
pr_sw_sel2: process(clk, reset) is
begin
if reset = '0' then
data2 <= '0';
elsif rising_edge(clk) then
data2 <= data_rom2(to_integer(unsigned(x_z)));
end if;
end process;
g_rgb2: for ii in 0 to 2 generate
begin
rgb(ii) <= data2 and color2(ii);
end generate;
end cl_mines; |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY internalromram IS
GENERIC
(
internal_rom : integer := 1;
internal_ram : integer := 16384
);
PORT(
clock : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
ROM_REQUEST_COMPLETE : out STD_LOGIC;
ROM_REQUEST : in std_logic;
ROM_DATA : out std_logic_vector(7 downto 0);
RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
RAM_WR_ENABLE : in std_logic;
RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
RAM_REQUEST_COMPLETE : out STD_LOGIC;
RAM_REQUEST : in std_logic;
RAM_DATA : out std_logic_vector(7 downto 0)
);
END internalromram;
architecture vhdl of internalromram is
signal rom_request_reg : std_logic;
signal ram_request_reg : std_logic;
signal ROM16_DATA : std_logic_vector(7 downto 0);
signal ROM8_DATA : std_logic_vector(7 downto 0);
signal ROM2_DATA : std_logic_vector(7 downto 0);
signal BASIC_DATA : std_logic_vector(7 downto 0);
begin
process(clock,reset_n)
begin
if (reset_n ='0') then
rom_request_reg <= '0';
ram_request_reg <= '0';
elsif (clock'event and clock='1') then
rom_request_reg <= rom_request;
ram_request_reg <= ram_request;
end if;
end process;
gen_internal_os_b : if internal_rom=3 generate
-- d800 to dfff (2k)
rom2 : entity work.os2
PORT MAP(clock => clock,
address => rom_addr(10 downto 0),
q => ROM2_data
);
-- e000 to ffff (8k)
rom10 : entity work.os8
PORT MAP(clock => clock,
address => rom_addr(12 downto 0),
q => ROM8_data
);
process(rom_addr)
begin
case rom_addr(13 downto 11) is
when "011" =>
ROM_DATA <= ROM2_data;
when "100"|"101"|"110"|"111" =>
ROM_DATA <= ROM8_data;
when others=>
ROM_DATA <= x"ff";
end case;
end process;
rom_request_complete <= rom_request_reg;
end generate;
gen_internal_os_loop : if internal_rom=2 generate
rom16a : entity work.os16_loop
PORT MAP(clock => clock,
address => rom_addr(13 downto 0),
q => ROM16_data
);
ROM_DATA <= ROM16_DATA;
rom_request_complete <= rom_request_reg;
end generate;
gen_internal_os : if internal_rom=1 generate
rom16a : entity work.os16
PORT MAP(clock => clock,
address => rom_addr(13 downto 0),
q => ROM16_data
);
basic1 : entity work.basic
PORT MAP(clock => clock,
address => rom_addr(12 downto 0),
q => BASIC_data
);
process(rom16_data,basic_data, rom_addr(15 downto 0))
begin
ROM_DATA <= ROM16_DATA;
if (rom_addr(15)='1') then
ROM_DATA <= BASIC_DATA;
end if;
end process;
rom_request_complete <= rom_request_reg;
end generate;
gen_no_internal_os : if internal_rom=0 generate
ROM16_data <= (others=>'0');
rom_request_complete <= '0';
end generate;
gen_internal_ram: if internal_ram>0 generate
ramint1 : entity work.generic_ram_infer
generic map
(
ADDRESS_WIDTH => 19,
SPACE => internal_ram,
DATA_WIDTH =>8
)
PORT MAP(clock => clock,
address => ram_addr,
data => ram_data_in(7 downto 0),
we => RAM_WR_ENABLE,
q => ram_data
);
ram_request_complete <= ram_request_reg;
end generate;
gen_no_internal_ram : if internal_ram=0 generate
ram_request_complete <='1';
ram_data <= (others=>'1');
end generate;
end vhdl;
|
entity call5 is
end;
use work.pkg.all;
architecture behav of call5 is
procedure p2 (s : string) is
begin
report natural'image (s'left);
report natural'image (s'right);
assert s'left = 1;
assert s'right = 4;
end;
procedure p1 (r : rec) is
begin
p2 (r.s);
end p1;
begin
process
variable v : rec_4dyn;
begin
p1 (v);
wait;
end process;
end behav;
|
entity call5 is
end;
use work.pkg.all;
architecture behav of call5 is
procedure p2 (s : string) is
begin
report natural'image (s'left);
report natural'image (s'right);
assert s'left = 1;
assert s'right = 4;
end;
procedure p1 (r : rec) is
begin
p2 (r.s);
end p1;
begin
process
variable v : rec_4dyn;
begin
p1 (v);
wait;
end process;
end behav;
|
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