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--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
|
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
|
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
|
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
|
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
|
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
|
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
|
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
|
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
|
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
|
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
|
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
|
-------------------------------------------------------------------------------
-- Title :
-------------------------------------------------------------------------------
-- File : UtilityPkg.vhd
-- Author : Kurtis Nishimura
-------------------------------------------------------------------------------
-- Description: A set of common useful definitions. Some of these ideas
-- originate from Ben Reese @ SLAC and his StdRtlPkg.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package UtilityPkg is
-- Shorthand names for common types
subtype sl is std_logic;
subtype slv is std_logic_vector;
-- Useful array types
type Word8Array is array (natural range <>) of slv( 7 downto 0);
type Word9Array is array (natural range <>) of slv( 8 downto 0);
type Word10Array is array (natural range <>) of slv( 9 downto 0);
type Word13Array is array (natural range <>) of slv(12 downto 0);
type Word16Array is array (natural range <>) of slv(15 downto 0);
type Word32Array is array (natural range <>) of slv(31 downto 0);
-----------------------
-- Function prototypes
-----------------------
-- Grab 1 byte of an input SLV
function getByte (byteNum : integer; input : slv) return slv;
-- Conditional selection of constants
function sel (conditional : boolean; if_true : natural; if_false : natural) return natural;
-- Count number of 1's in a std_logic_vector
function countOnes (input : slv) return integer;
-- Sum up number of bytes
function sumBytes (input : Word8Array) return integer;
-- Sum up an array of 2-byte inputs
function sum2Bytes (input : Word16Array) return integer;
end UtilityPkg;
package body UtilityPkg is
function getByte (byteNum : integer; input : slv) return slv is
variable retVar : slv(7 downto 0) := (others => '0');
begin
-- Make sure that we're not looking out of range of the input
assert(byteNum*8 <= input'length and byteNum >= 0) report "Byte number is out of range!" severity failure;
-- Calculate the byte we want
retVar := input(8*byteNum+7 downto 8*byteNum);
return retVar;
end function;
function sel (conditional : boolean; if_true : natural; if_false : natural) return natural is
begin
if (conditional = true) then
return(if_true);
else
return(if_false);
end if;
end function;
function countOnes (input : slv) return integer is
variable retVal : integer := 0;
begin
for i in input'range loop
if
input(i) = '1' then retVal := retVal + 1;
end if;
end loop;
return retVal;
end function;
function sumBytes (input : Word8Array) return integer is
variable retVal : integer := 0;
begin
for i in input'range loop
retVal := retVal + conv_integer(input(i));
end loop;
return retVal;
end function;
function sum2Bytes (input : Word16Array) return integer is
variable retVal : integer := 0;
begin
for i in input'range loop
retVal := retVal + conv_integer(input(i));
end loop;
return retVal;
end function;
end package body UtilityPkg;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_finals is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_finals is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_ST_pp0_stg2_fsm_2 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_pp0_stg3_fsm_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "10";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal nfa_finals_buckets_read_reg_59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_131 : BOOLEAN;
signal ap_sig_bdd_130 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))) then
nfa_finals_buckets_read_reg_59 <= nfa_finals_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_ce , nfa_finals_buckets_rsp_empty_n , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)))) then
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when ap_ST_pp0_stg2_fsm_2 =>
if (not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
end if;
when ap_ST_pp0_stg3_fsm_3 =>
if ((ap_const_logic_1 = ap_ce)) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_finals_buckets_rsp_empty_n)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_finals_buckets_read_reg_59;
ap_return_1 <= nfa_finals_buckets_datain;
-- ap_sig_bdd_130 assign process. --
ap_sig_bdd_130_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_130 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_131 assign process. --
ap_sig_bdd_131_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0)
begin
ap_sig_bdd_131 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_address assign process. --
nfa_finals_buckets_address_assign_proc : process(ap_CS_fsm, ap_sig_bdd_131, ap_sig_bdd_130)
begin
if (ap_sig_bdd_130) then
if ((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm)) then
nfa_finals_buckets_address <= ap_const_lv64_1(32 - 1 downto 0);
elsif (ap_sig_bdd_131) then
nfa_finals_buckets_address <= ap_const_lv32_0;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_finals_buckets_dataout <= ap_const_lv32_0;
nfa_finals_buckets_req_din <= ap_const_logic_0;
-- nfa_finals_buckets_req_write assign process. --
nfa_finals_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
nfa_finals_buckets_req_write <= ap_const_logic_1;
else
nfa_finals_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_rsp_read assign process. --
nfa_finals_buckets_rsp_read_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_finals_buckets_rsp_empty_n)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then
nfa_finals_buckets_rsp_read <= ap_const_logic_1;
else
nfa_finals_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_finals_buckets_size <= ap_const_lv32_1;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_finals is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_finals is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_ST_pp0_stg2_fsm_2 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_pp0_stg3_fsm_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "10";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal nfa_finals_buckets_read_reg_59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_131 : BOOLEAN;
signal ap_sig_bdd_130 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))) then
nfa_finals_buckets_read_reg_59 <= nfa_finals_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_ce , nfa_finals_buckets_rsp_empty_n , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)))) then
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when ap_ST_pp0_stg2_fsm_2 =>
if (not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
end if;
when ap_ST_pp0_stg3_fsm_3 =>
if ((ap_const_logic_1 = ap_ce)) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_finals_buckets_rsp_empty_n)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_finals_buckets_read_reg_59;
ap_return_1 <= nfa_finals_buckets_datain;
-- ap_sig_bdd_130 assign process. --
ap_sig_bdd_130_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_130 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_131 assign process. --
ap_sig_bdd_131_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0)
begin
ap_sig_bdd_131 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_address assign process. --
nfa_finals_buckets_address_assign_proc : process(ap_CS_fsm, ap_sig_bdd_131, ap_sig_bdd_130)
begin
if (ap_sig_bdd_130) then
if ((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm)) then
nfa_finals_buckets_address <= ap_const_lv64_1(32 - 1 downto 0);
elsif (ap_sig_bdd_131) then
nfa_finals_buckets_address <= ap_const_lv32_0;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_finals_buckets_dataout <= ap_const_lv32_0;
nfa_finals_buckets_req_din <= ap_const_logic_0;
-- nfa_finals_buckets_req_write assign process. --
nfa_finals_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
nfa_finals_buckets_req_write <= ap_const_logic_1;
else
nfa_finals_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_rsp_read assign process. --
nfa_finals_buckets_rsp_read_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_finals_buckets_rsp_empty_n)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then
nfa_finals_buckets_rsp_read <= ap_const_logic_1;
else
nfa_finals_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_finals_buckets_size <= ap_const_lv32_1;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_get_finals is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_get_finals is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_ST_pp0_stg1_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_ST_pp0_stg2_fsm_2 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_pp0_stg3_fsm_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "10";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal nfa_finals_buckets_read_reg_59 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppiten_pp0_it0_preg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal ap_sig_bdd_131 : BOOLEAN;
signal ap_sig_bdd_130 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0_preg assign process. --
ap_reg_ppiten_pp0_it0_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0_preg <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
ap_reg_ppiten_pp0_it0_preg <= ap_start;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it0)))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
elsif (((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))) then
nfa_finals_buckets_read_reg_59 <= nfa_finals_buckets_datain;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it1 , ap_ce , nfa_finals_buckets_rsp_empty_n , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))) and not(((ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_start))))) then
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
else
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
end if;
when ap_ST_pp0_stg1_fsm_1 =>
if ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and not((ap_const_logic_1 = ap_sig_pprstidle_pp0)))) then
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
elsif ((not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_sig_pprstidle_pp0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg1_fsm_1;
end if;
when ap_ST_pp0_stg2_fsm_2 =>
if (not((not((ap_const_logic_1 = ap_ce)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
else
ap_NS_fsm <= ap_ST_pp0_stg2_fsm_2;
end if;
when ap_ST_pp0_stg3_fsm_3 =>
if ((ap_const_logic_1 = ap_ce)) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_NS_fsm <= ap_ST_pp0_stg3_fsm_3;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_finals_buckets_rsp_empty_n)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0_preg)
begin
if ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm)) then
ap_reg_ppiten_pp0_it0 <= ap_start;
else
ap_reg_ppiten_pp0_it0 <= ap_reg_ppiten_pp0_it0_preg;
end if;
end process;
ap_return_0 <= nfa_finals_buckets_read_reg_59;
ap_return_1 <= nfa_finals_buckets_datain;
-- ap_sig_bdd_130 assign process. --
ap_sig_bdd_130_assign_proc : process(ap_reg_ppiten_pp0_it0, ap_ce)
begin
ap_sig_bdd_130 <= ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce));
end process;
-- ap_sig_bdd_131 assign process. --
ap_sig_bdd_131_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0)
begin
ap_sig_bdd_131 <= ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0))));
end process;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_address assign process. --
nfa_finals_buckets_address_assign_proc : process(ap_CS_fsm, ap_sig_bdd_131, ap_sig_bdd_130)
begin
if (ap_sig_bdd_130) then
if ((ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm)) then
nfa_finals_buckets_address <= ap_const_lv64_1(32 - 1 downto 0);
elsif (ap_sig_bdd_131) then
nfa_finals_buckets_address <= ap_const_lv32_0;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
nfa_finals_buckets_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_finals_buckets_dataout <= ap_const_lv32_0;
nfa_finals_buckets_req_din <= ap_const_logic_0;
-- nfa_finals_buckets_req_write assign process. --
nfa_finals_buckets_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_ce)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_ST_pp0_stg3_fsm_3 = ap_CS_fsm) and (ap_const_logic_1 = ap_ce)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)))))) then
nfa_finals_buckets_req_write <= ap_const_logic_1;
else
nfa_finals_buckets_req_write <= ap_const_logic_0;
end if;
end process;
-- nfa_finals_buckets_rsp_read assign process. --
nfa_finals_buckets_rsp_read_assign_proc : process(ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_ce, nfa_finals_buckets_rsp_empty_n)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg2_fsm_2 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_1 = ap_ce) and (ap_ST_pp0_stg1_fsm_1 = ap_CS_fsm) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and (nfa_finals_buckets_rsp_empty_n = ap_const_logic_0)))))) then
nfa_finals_buckets_rsp_read <= ap_const_logic_1;
else
nfa_finals_buckets_rsp_read <= ap_const_logic_0;
end if;
end process;
nfa_finals_buckets_size <= ap_const_lv32_1;
end behav;
|
package body fifo_pkg is
end package body fifo_pkg;
package body fifo is
end package body fifo;
|
--/*******************************************************************************
-- *
-- *
-- * File:
-- * counter.vhd
-- *
-- *
-- * Module:
-- * precise_timestamp
-- *
-- * Author:
-- * Mario Ruiz
-- *
-- *
-- * Copyright (C) 2015 - Mario Ruiz and HPCN-UAM High Performance Computing and Networking
-- *
-- * Licence:
-- * This file is part of the HPCN-NetFPGA 10G development base package.
-- *
-- * This file is free code: you can redistribute it and/or modify it under
-- * the terms of the GNU Lesser General Public License version 2.0 as
-- * published by the Free Software Foundation.
-- *
-- * This package is distributed in the hope that it will be useful, but
-- * WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- * Lesser General Public License for more details.
-- *
-- * You should have received a copy of the GNU Lesser General Public
-- * License along with the NetFPGA source package. If not, see
-- * http://www.gnu.org/licenses/.
-- *
-- */
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
generic (
constant width_counter : integer := 32;
constant max_count : std_logic_vector := x"3B9ACA00"; -- 1.000.000.000 ns
constant high_time_pps : std_logic_vector := x"05F5E100"; -- 100.000.000 ns
constant counter_increment : integer :=10 -- 10ns
);
port(
aclk : in std_logic;
aresetn : in std_logic;
timedrift : in std_logic_vector (1 downto 0);
pps : in std_logic;
pps_internal : out std_logic;
second : out std_logic_vector (width_counter-1 downto 0);
nanosecond : out std_logic_vector (width_counter-1 downto 0);
mode : in std_logic;
updatesec : in std_logic_vector (width_counter-1 downto 0)
);
end counter;
-- Mode
-- 0 Stop and load second
-- 1 Start Counting
architecture Behavioral of counter is
signal nsec_count,sec_count : std_logic_vector (width_counter-1 downto 0);
type state_t is (load, waiting, counting);
signal state : state_t := load;
signal next_state : state_t;
signal pps_ant : std_logic :='1';
begin
process (aclk)
begin
if rising_edge(aclk) then
if (aresetn='0') then
nsec_count <= (others => '0');
sec_count <= (others => '0');
pps_internal <= '0';
next_state <= load;
else
case (state) is
when load => -- load second
if (mode='0') then
sec_count <=updatesec;
nsec_count <= (others =>'0');
next_state <= load;
else
next_state <= waiting;
end if;
when waiting => -- wait for pps signal
if (pps_ant='0' and pps='1') then -- when rising_edge pps increment second and start normal counting
sec_count <=sec_count+1;
next_state <= counting;
elsif (mode = '0') then
next_state <= load;
else
next_state <= waiting;
end if;
pps_ant <=pps;
when counting => -- normal counting
case (timedrift) is -- check that correction is available
when "01" => -- advance counting
nsec_count <= nsec_count + counter_increment+1; -- nsec_count + 11
when "10" =>
nsec_count <= nsec_count + counter_increment-1; -- nsec_count + 9
when others => -- normal counting
nsec_count <= nsec_count + counter_increment; -- nsec_count + 10
end case;
if (nsec_count > max_count-10) then --
sec_count <= sec_count+1;
nsec_count <= (others =>'0');
pps_internal <='1';
elsif (nsec_count > high_time_pps) then
pps_internal <='0';
end if;
if (mode = '0') then
next_state <= load;
else
next_state <= counting;
end if;
end case;
end if;
end if;
end process;
state <= next_state;
second <= sec_count;
nanosecond <= nsec_count;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity reg_file_tb is
end entity reg_file_tb;
architecture tb of reg_file_tb is
constant T : time := 20 ns;
constant B : integer := 16;
constant R : integer := 4;
signal clk, rst, we_l : std_logic;
signal w_data, r_data_1, r_data_2 : std_logic_vector(B-1 downto 0);
signal w_addr, r_addr_1, r_addr_2 : std_logic_vector(R-1 downto 0);
begin
uut : entity work.reg_file
generic map(B => B,
R => R)
port map(clk => clk,
rst => rst,
we_l => we_l,
w_data => w_data,
w_addr => w_addr,
rd_addr_1 => r_addr_1,
rd_addr_2 => r_addr_2,
rd_data_1 => r_data_1,
rd_data_2 => r_data_2);
clk_gen : process is
begin
clk <= '0';
wait for T/2;
clk <= '1';
wait for T/2;
end process clk_gen;
rst <= '1', '0' after 3*T/4;
stim_gen : process is
begin
we_l <= '1';
r_addr_1 <= X"2";
r_addr_2 <= X"3";
wait for 4*T;
assert false report "Simulation over" severity failure;
end process stim_gen;
end architecture tb;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: test_image_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY test_image_tb IS
END ENTITY;
ARCHITECTURE test_image_tb_ARCH OF test_image_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
test_image_synth_inst:ENTITY work.test_image_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
end dspba_library_package;
|
-------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
-------------------------------------------------------------------------------
--
-- unit name: GN4124 core arbiter (arbiter.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 12-08-2010
--
-- version: 0.1
--
-- description: Arbitrates PCIe accesses between Wishbone master,
-- L2P DMA master and P2L DMA master
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- last changes: 23-09-2010 (mcattin) Add FF on data path and
-- change valid request logic
-- 26.02.2014 (theim) Changed priority order (swapped LDM <-> PDM)
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--use work.gn4124_core_pkg.all;
--use work.common_pkg.all;
entity l2p_arbiter is
generic(
axis_data_width_c : integer := 64
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
wbm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
wbm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
wbm_arb_tlast_i : in std_logic;
wbm_arb_tvalid_i : in std_logic;
wbm_arb_tready_o : out std_logic;
wbm_arb_req_i : in std_logic;
arb_wbm_gnt_o : out std_logic;
---------------------------------------------------------
-- From P2L DMA master (pdm) to arbiter (arb)
pdm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
pdm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
pdm_arb_tlast_i : in std_logic;
pdm_arb_tvalid_i : in std_logic;
pdm_arb_tready_o : out std_logic;
pdm_arb_req_i : in std_logic;
arb_pdm_gnt_o : out std_logic;
---------------------------------------------------------
-- From L2P DMA master (ldm) to arbiter (arb)
ldm_arb_tdata_i : in std_logic_vector (axis_data_width_c - 1 downto 0);
ldm_arb_tkeep_i : in std_logic_vector (axis_data_width_c/8 - 1 downto 0);
ldm_arb_tlast_i : in std_logic;
ldm_arb_tvalid_i : in std_logic;
ldm_arb_tready_o : out std_logic;
ldm_arb_req_i : in std_logic;
arb_ldm_gnt_o : out std_logic;
---------------------------------------------------------
-- From arbiter (arb) to pcie_tx (tx)
axis_tx_tdata_o : out STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
axis_tx_tkeep_o : out STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
axis_tx_tuser_o : out STD_LOGIC_VECTOR (3 downto 0);
axis_tx_tlast_o : out STD_LOGIC;
axis_tx_tvalid_o : out STD_LOGIC;
axis_tx_tready_i : in STD_LOGIC;
---------------------------------------------------------
-- Debug
eop_do : out std_logic
);
end l2p_arbiter;
architecture rtl of l2p_arbiter is
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal wbm_arb_req_valid : std_logic;
signal pdm_arb_req_valid : std_logic;
signal ldm_arb_req_valid : std_logic;
signal arb_wbm_gnt : std_logic;
signal arb_pdm_gnt : std_logic;
signal arb_ldm_gnt : std_logic;
signal eop : std_logic; -- End of packet
signal axis_tx_tvalid_t : std_logic;
signal axis_tx_tlast_t : std_logic;
signal axis_tx_tdata_t : std_logic_vector(axis_data_width_c - 1 downto 0);
signal axis_tx_tkeep_t : std_logic_vector(axis_data_width_c/8 - 1 downto 0);
constant c_RST_ACTIVE : std_logic := '0';
begin
-- A request is valid only if the access not already granted to another source
wbm_arb_req_valid <= wbm_arb_req_i and (not(arb_pdm_gnt) and not(arb_ldm_gnt));
pdm_arb_req_valid <= pdm_arb_req_i and (not(arb_wbm_gnt) and not(arb_ldm_gnt));
ldm_arb_req_valid <= ldm_arb_req_i and (not(arb_wbm_gnt) and not(arb_pdm_gnt));
eop_do <= eop;
-- Detect end of packet to delimit the arbitration phase
-- eop <= ((arb_wbm_gnt and not(wbm_arb_dframe_i) and wbm_arb_valid_i) or
-- (arb_pdm_gnt and not(pdm_arb_dframe_i) and pdm_arb_valid_i) or
-- (arb_ldm_gnt and not(ldm_arb_dframe_i) and ldm_arb_valid_i));
process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
eop <= '0';
elsif rising_edge(clk_i) then
if ((arb_wbm_gnt = '1' and wbm_arb_tlast_i = '1') or
(arb_pdm_gnt = '1' and pdm_arb_tlast_i = '1') or
(arb_ldm_gnt = '1' and ldm_arb_tlast_i = '1')) then
eop <= '1';
else
eop <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Arbitration is started when a valid request is present and ends when the
-- EOP condition is detected
--
-- Strict priority arbitration scheme
-- Highest : WBM request
-- : LDM request
-- Lowest : PDM request
-----------------------------------------------------------------------------
process (clk_i, rst_n_i)
begin
if(rst_n_i = c_RST_ACTIVE) then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif rising_edge(clk_i) then
--if (arb_req_valid = '1') then
if (eop = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif (wbm_arb_req_valid = '1') then
arb_wbm_gnt <= '1';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '0';
elsif (ldm_arb_req_valid = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '0';
arb_ldm_gnt <= '1';
elsif (pdm_arb_req_valid = '1') then
arb_wbm_gnt <= '0';
arb_pdm_gnt <= '1';
arb_ldm_gnt <= '0';
end if;
end if;
end process;
process (clk_i, rst_n_i)
begin
if rst_n_i = '0' then
axis_tx_tvalid_t <= '0';
axis_tx_tlast_t <= '0';
axis_tx_tdata_t <= (others => '0');
axis_tx_tkeep_t <= (others => '0');
elsif rising_edge(clk_i) then
if arb_wbm_gnt = '1' then
axis_tx_tvalid_t <= wbm_arb_tvalid_i;
axis_tx_tlast_t <= wbm_arb_tlast_i;
axis_tx_tdata_t <= wbm_arb_tdata_i;
axis_tx_tkeep_t <= wbm_arb_tkeep_i;
elsif arb_pdm_gnt = '1' then
axis_tx_tvalid_t <= pdm_arb_tvalid_i;
axis_tx_tlast_t <= pdm_arb_tlast_i;
axis_tx_tdata_t <= pdm_arb_tdata_i;
axis_tx_tkeep_t <= pdm_arb_tkeep_i;
elsif arb_ldm_gnt = '1' then
axis_tx_tvalid_t <= ldm_arb_tvalid_i;
axis_tx_tlast_t <= ldm_arb_tlast_i;
axis_tx_tdata_t <= ldm_arb_tdata_i;
axis_tx_tkeep_t <= ldm_arb_tkeep_i;
else
axis_tx_tvalid_t <= '0';
axis_tx_tlast_t <= '0';
axis_tx_tdata_t <= (others => '0');
axis_tx_tkeep_t <= (others => '0');
end if;
end if;
end process;
process (clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
axis_tx_tvalid_o <= '0';
axis_tx_tlast_o <= '0';
axis_tx_tdata_o <= (others => '0');
axis_tx_tkeep_o <= (others => '0');
elsif rising_edge(clk_i) then
axis_tx_tvalid_o <= axis_tx_tvalid_t;
axis_tx_tlast_o <= axis_tx_tlast_t;
axis_tx_tdata_o <= axis_tx_tdata_t;
axis_tx_tkeep_o <= axis_tx_tkeep_t;
end if;
end process;
arb_wbm_gnt_o <= arb_wbm_gnt;
arb_pdm_gnt_o <= arb_pdm_gnt;
arb_ldm_gnt_o <= arb_ldm_gnt;
wbm_arb_tready_o <= axis_tx_tready_i and arb_wbm_gnt;
pdm_arb_tready_o <= axis_tx_tready_i and arb_pdm_gnt;
ldm_arb_tready_o <= axis_tx_tready_i and arb_ldm_gnt;
axis_tx_tuser_o <= "0000";
end rtl;
|
-- Btrace 448
-- Up/down counter
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
generic(n: integer := 5);
port(clk, reset: in std_logic;
ld, up, down: in std_logic;
d: in std_logic_vector(n-1 downto 0);
q: out std_logic_vector(n-1 downto 0) := (others => '0'));
end counter;
architecture arch of counter is
signal q_next: std_logic_vector(n-1 downto 0);
begin
process(clk, reset)
begin
if (reset = '1') then
q_next <= (others => '0');
elsif rising_edge(clk) then
if (ld = '1') then
q_next <= d;
elsif (up = '1') then
q_next <= std_logic_vector(unsigned(q_next) + 1);
elsif (down = '1') then
q_next <= std_logic_vector(unsigned(q_next) - 1);
end if;
end if;
end process;
q <= q_next;
end arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mash is
generic (
g_order : positive := 2;
g_width : positive := 16 );
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
dac_in : in unsigned(g_width-1 downto 0);
dac_out : out integer range 0 to (2**g_order)-1);
end entity;
architecture gideon of mash is
type t_accu_array is array(natural range <>) of unsigned(g_width-1 downto 0);
signal accu : t_accu_array(0 to g_order-1);
signal carry : std_logic_vector(0 to g_order-1);
signal sum : t_accu_array(0 to g_order-1);
subtype t_delta_range is integer range -(2**(g_order-1)) to (2**(g_order-1));
type t_int_array is array(natural range <>) of t_delta_range;
signal delta : t_int_array(0 to g_order-1) := (others => 0);
signal delta_d : t_int_array(0 to g_order-1) := (others => 0);
procedure sum_with_carry(a, b : unsigned; y : out unsigned; c : out std_logic ) is
variable a_ext : unsigned(a'length downto 0);
variable b_ext : unsigned(a'length downto 0);
variable summed : unsigned(a'length downto 0);
begin
a_ext := '0' & a;
b_ext := '0' & b;
summed := a_ext + b_ext;
c := summed(summed'left);
y := summed(a'length-1 downto 0);
end procedure;
function count_deltas(a : std_logic; b : t_delta_range; c : t_delta_range) return t_delta_range is
begin
if a = '1' then
return 1 + b - c;
end if;
return b - c;
end function;
begin
process(accu, dac_in, carry, delta, delta_d, sum)
variable a : unsigned(dac_in'range);
variable y : unsigned(dac_in'range);
variable c : std_logic;
begin
for i in 0 to g_order-1 loop
if i=0 then
a := dac_in;
else
a := sum(i-1);
end if;
sum_with_carry(a, accu(i), y, c);
sum(i) <= y;
carry(i) <= c;
if i = g_order-1 then
delta(i) <= count_deltas(carry(i), 0, 0);
else
delta(i) <= count_deltas(carry(i), delta(i+1), delta_d(i+1));
end if;
end loop;
end process;
dac_out <= delta_d(0) + (2 ** (g_order-1) - 1);
process(clock)
begin
if rising_edge(clock) then
if enable='1' then
accu <= sum;
delta_d <= delta;
end if;
if reset='1' then
accu <= (others => (others => '0'));
delta_d <= (others => 0);
end if;
end if;
end process;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mash is
generic (
g_order : positive := 2;
g_width : positive := 16 );
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
dac_in : in unsigned(g_width-1 downto 0);
dac_out : out integer range 0 to (2**g_order)-1);
end entity;
architecture gideon of mash is
type t_accu_array is array(natural range <>) of unsigned(g_width-1 downto 0);
signal accu : t_accu_array(0 to g_order-1);
signal carry : std_logic_vector(0 to g_order-1);
signal sum : t_accu_array(0 to g_order-1);
subtype t_delta_range is integer range -(2**(g_order-1)) to (2**(g_order-1));
type t_int_array is array(natural range <>) of t_delta_range;
signal delta : t_int_array(0 to g_order-1) := (others => 0);
signal delta_d : t_int_array(0 to g_order-1) := (others => 0);
procedure sum_with_carry(a, b : unsigned; y : out unsigned; c : out std_logic ) is
variable a_ext : unsigned(a'length downto 0);
variable b_ext : unsigned(a'length downto 0);
variable summed : unsigned(a'length downto 0);
begin
a_ext := '0' & a;
b_ext := '0' & b;
summed := a_ext + b_ext;
c := summed(summed'left);
y := summed(a'length-1 downto 0);
end procedure;
function count_deltas(a : std_logic; b : t_delta_range; c : t_delta_range) return t_delta_range is
begin
if a = '1' then
return 1 + b - c;
end if;
return b - c;
end function;
begin
process(accu, dac_in, carry, delta, delta_d, sum)
variable a : unsigned(dac_in'range);
variable y : unsigned(dac_in'range);
variable c : std_logic;
begin
for i in 0 to g_order-1 loop
if i=0 then
a := dac_in;
else
a := sum(i-1);
end if;
sum_with_carry(a, accu(i), y, c);
sum(i) <= y;
carry(i) <= c;
if i = g_order-1 then
delta(i) <= count_deltas(carry(i), 0, 0);
else
delta(i) <= count_deltas(carry(i), delta(i+1), delta_d(i+1));
end if;
end loop;
end process;
dac_out <= delta_d(0) + (2 ** (g_order-1) - 1);
process(clock)
begin
if rising_edge(clock) then
if enable='1' then
accu <= sum;
delta_d <= delta;
end if;
if reset='1' then
accu <= (others => (others => '0'));
delta_d <= (others => 0);
end if;
end if;
end process;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mash is
generic (
g_order : positive := 2;
g_width : positive := 16 );
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
dac_in : in unsigned(g_width-1 downto 0);
dac_out : out integer range 0 to (2**g_order)-1);
end entity;
architecture gideon of mash is
type t_accu_array is array(natural range <>) of unsigned(g_width-1 downto 0);
signal accu : t_accu_array(0 to g_order-1);
signal carry : std_logic_vector(0 to g_order-1);
signal sum : t_accu_array(0 to g_order-1);
subtype t_delta_range is integer range -(2**(g_order-1)) to (2**(g_order-1));
type t_int_array is array(natural range <>) of t_delta_range;
signal delta : t_int_array(0 to g_order-1) := (others => 0);
signal delta_d : t_int_array(0 to g_order-1) := (others => 0);
procedure sum_with_carry(a, b : unsigned; y : out unsigned; c : out std_logic ) is
variable a_ext : unsigned(a'length downto 0);
variable b_ext : unsigned(a'length downto 0);
variable summed : unsigned(a'length downto 0);
begin
a_ext := '0' & a;
b_ext := '0' & b;
summed := a_ext + b_ext;
c := summed(summed'left);
y := summed(a'length-1 downto 0);
end procedure;
function count_deltas(a : std_logic; b : t_delta_range; c : t_delta_range) return t_delta_range is
begin
if a = '1' then
return 1 + b - c;
end if;
return b - c;
end function;
begin
process(accu, dac_in, carry, delta, delta_d, sum)
variable a : unsigned(dac_in'range);
variable y : unsigned(dac_in'range);
variable c : std_logic;
begin
for i in 0 to g_order-1 loop
if i=0 then
a := dac_in;
else
a := sum(i-1);
end if;
sum_with_carry(a, accu(i), y, c);
sum(i) <= y;
carry(i) <= c;
if i = g_order-1 then
delta(i) <= count_deltas(carry(i), 0, 0);
else
delta(i) <= count_deltas(carry(i), delta(i+1), delta_d(i+1));
end if;
end loop;
end process;
dac_out <= delta_d(0) + (2 ** (g_order-1) - 1);
process(clock)
begin
if rising_edge(clock) then
if enable='1' then
accu <= sum;
delta_d <= delta;
end if;
if reset='1' then
accu <= (others => (others => '0'));
delta_d <= (others => 0);
end if;
end if;
end process;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mash is
generic (
g_order : positive := 2;
g_width : positive := 16 );
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
dac_in : in unsigned(g_width-1 downto 0);
dac_out : out integer range 0 to (2**g_order)-1);
end entity;
architecture gideon of mash is
type t_accu_array is array(natural range <>) of unsigned(g_width-1 downto 0);
signal accu : t_accu_array(0 to g_order-1);
signal carry : std_logic_vector(0 to g_order-1);
signal sum : t_accu_array(0 to g_order-1);
subtype t_delta_range is integer range -(2**(g_order-1)) to (2**(g_order-1));
type t_int_array is array(natural range <>) of t_delta_range;
signal delta : t_int_array(0 to g_order-1) := (others => 0);
signal delta_d : t_int_array(0 to g_order-1) := (others => 0);
procedure sum_with_carry(a, b : unsigned; y : out unsigned; c : out std_logic ) is
variable a_ext : unsigned(a'length downto 0);
variable b_ext : unsigned(a'length downto 0);
variable summed : unsigned(a'length downto 0);
begin
a_ext := '0' & a;
b_ext := '0' & b;
summed := a_ext + b_ext;
c := summed(summed'left);
y := summed(a'length-1 downto 0);
end procedure;
function count_deltas(a : std_logic; b : t_delta_range; c : t_delta_range) return t_delta_range is
begin
if a = '1' then
return 1 + b - c;
end if;
return b - c;
end function;
begin
process(accu, dac_in, carry, delta, delta_d, sum)
variable a : unsigned(dac_in'range);
variable y : unsigned(dac_in'range);
variable c : std_logic;
begin
for i in 0 to g_order-1 loop
if i=0 then
a := dac_in;
else
a := sum(i-1);
end if;
sum_with_carry(a, accu(i), y, c);
sum(i) <= y;
carry(i) <= c;
if i = g_order-1 then
delta(i) <= count_deltas(carry(i), 0, 0);
else
delta(i) <= count_deltas(carry(i), delta(i+1), delta_d(i+1));
end if;
end loop;
end process;
dac_out <= delta_d(0) + (2 ** (g_order-1) - 1);
process(clock)
begin
if rising_edge(clock) then
if enable='1' then
accu <= sum;
delta_d <= delta;
end if;
if reset='1' then
accu <= (others => (others => '0'));
delta_d <= (others => 0);
end if;
end if;
end process;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mash is
generic (
g_order : positive := 2;
g_width : positive := 16 );
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
dac_in : in unsigned(g_width-1 downto 0);
dac_out : out integer range 0 to (2**g_order)-1);
end entity;
architecture gideon of mash is
type t_accu_array is array(natural range <>) of unsigned(g_width-1 downto 0);
signal accu : t_accu_array(0 to g_order-1);
signal carry : std_logic_vector(0 to g_order-1);
signal sum : t_accu_array(0 to g_order-1);
subtype t_delta_range is integer range -(2**(g_order-1)) to (2**(g_order-1));
type t_int_array is array(natural range <>) of t_delta_range;
signal delta : t_int_array(0 to g_order-1) := (others => 0);
signal delta_d : t_int_array(0 to g_order-1) := (others => 0);
procedure sum_with_carry(a, b : unsigned; y : out unsigned; c : out std_logic ) is
variable a_ext : unsigned(a'length downto 0);
variable b_ext : unsigned(a'length downto 0);
variable summed : unsigned(a'length downto 0);
begin
a_ext := '0' & a;
b_ext := '0' & b;
summed := a_ext + b_ext;
c := summed(summed'left);
y := summed(a'length-1 downto 0);
end procedure;
function count_deltas(a : std_logic; b : t_delta_range; c : t_delta_range) return t_delta_range is
begin
if a = '1' then
return 1 + b - c;
end if;
return b - c;
end function;
begin
process(accu, dac_in, carry, delta, delta_d, sum)
variable a : unsigned(dac_in'range);
variable y : unsigned(dac_in'range);
variable c : std_logic;
begin
for i in 0 to g_order-1 loop
if i=0 then
a := dac_in;
else
a := sum(i-1);
end if;
sum_with_carry(a, accu(i), y, c);
sum(i) <= y;
carry(i) <= c;
if i = g_order-1 then
delta(i) <= count_deltas(carry(i), 0, 0);
else
delta(i) <= count_deltas(carry(i), delta(i+1), delta_d(i+1));
end if;
end loop;
end process;
dac_out <= delta_d(0) + (2 ** (g_order-1) - 1);
process(clock)
begin
if rising_edge(clock) then
if enable='1' then
accu <= sum;
delta_d <= delta;
end if;
if reset='1' then
accu <= (others => (others => '0'));
delta_d <= (others => 0);
end if;
end if;
end process;
end gideon;
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity pipelines is
generic(
LENGTH : natural
);
port(
clk : in std_ulogic;
input : in std_ulogic_vector;
output : out std_ulogic_vector
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture pipelines_1 of pipelines is
begin
pipelines_core_1:
entity work.pipelines_core
generic map(
LENGTH => LENGTH,
INPUT_HIGH => input'high,
INPUT_LOW => input'low
)
port map(
clk => clk,
input => input,
output => output
);
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
entity output07 is
port (clk : std_logic;
i : std_logic;
o : out std_logic_vector (1 downto 0) := "10");
end output07;
architecture behav of output07 is
begin
process (clk)
begin
if rising_edge(clk) then
o (0) <= i;
o (1) <= not i;
end if;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rounder is
generic(
TOTAL_BITS:natural := 23;
EXP_BITS: natural := 6
);
port (
exponent_addition_cout: in std_logic;
man_in: in std_logic_vector(TOTAL_BITS - EXP_BITS downto 0);
exp_in: in std_logic_vector(EXP_BITS - 1 downto 0);
man_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_out : out std_logic_vector(EXP_BITS - 1 downto 0)
);
end;
architecture rounder_arq of rounder is
begin
process(man_in, exp_in, exponent_addition_cout)
variable tmp_exp : integer := 0;
variable bias_vector : std_logic_vector(EXP_BITS - 2 downto 0) := (others => '1');
variable bias : integer := 0;
variable extended_exponent : std_logic_vector(EXP_BITS downto 0) := (others => '0');
variable zero_man : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
variable zero_exp : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '0');
variable infinity_man : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '1');
variable infinity_exp : std_logic_vector(EXP_BITS - 2 downto 0) := (others => '1');
variable max_exp_vector : std_logic_vector(EXP_BITS - 1 downto 0) := (others => '1');
variable max_exp : integer := 0;
variable out_man : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0');
begin
extended_exponent := exponent_addition_cout & exp_in;
tmp_exp := to_integer(unsigned(extended_exponent));
bias := to_integer(unsigned('0' & bias_vector));
tmp_exp := tmp_exp - bias;
max_exp := to_integer(unsigned(max_exp_vector));
--Check if the exponent needs to be modified and the mantissa shifted
if(man_in(TOTAL_BITS - EXP_BITS) = '1') then
out_man := man_in(TOTAL_BITS - EXP_BITS - 1 downto 1);
tmp_exp := tmp_exp + 1;
else
out_man := man_in(TOTAL_BITS - EXP_BITS - 2 downto 0);
end if;
if(tmp_exp <= 0) then --round to 0
exp_out <= zero_exp;
man_out <= zero_man;
elsif(tmp_exp >= max_exp) then --round to infinity
exp_out <= infinity_exp & '0';
man_out <= infinity_man;
else
exp_out <= std_logic_vector(to_unsigned(tmp_exp, EXP_BITS));
man_out <= out_man;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : Wishbone Debugger SDB descriptor
-- Project : FMC DEL 1ns 4cha-stand-alone application (fmc-delay-1ns-4cha-sa)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Jose Jimenez <[email protected]>
-- Company : University of Granada
-- Created : 2014-07-31
-- Last update: 2014-07-36
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the WB Debugger and top level of the FMC used
-- on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_FMC_DEL_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "spec-fine-delay ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20140731",
syn_username => "jjimenez ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha-sa.git "
);
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "wb-debugger ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20140731",
syn_username => "jjimenez ");
end package synthesis_descriptor;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity convolve_kernel_control_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC
);
end entity convolve_kernel_control_s_axi;
-- ------------------------Address Info-------------------
-- 0x0 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x4 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x8 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0xc : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of convolve_kernel_control_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#0#;
constant ADDR_GIE : INTEGER := 16#4#;
constant ADDR_IER : INTEGER := 16#8#;
constant ADDR_ISR : INTEGER := 16#c#;
constant ADDR_BITS : INTEGER := 4;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
-- $Id: rb_sres_or_3.vhd 343 2010-12-05 21:24:38Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_3 - syn
-- Description: rbus result or, 3 input
--
-- Dependencies: rb_sres_or_mon [sim only]
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon
-- 2010-06-26 309 1.1 add rritb_sres_or_mon
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
-- 2008-01-20 113 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity rb_sres_or_3 is -- rbus result or, 3 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end rb_sres_or_3;
architecture syn of rb_sres_or_3 is
begin
proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3)
begin
RB_SRES_OR.ack <= RB_SRES_1.ack or
RB_SRES_2.ack or
RB_SRES_3.ack;
RB_SRES_OR.busy <= RB_SRES_1.busy or
RB_SRES_2.busy or
RB_SRES_3.busy;
RB_SRES_OR.err <= RB_SRES_1.err or
RB_SRES_2.err or
RB_SRES_3.err;
RB_SRES_OR.dout <= RB_SRES_1.dout or
RB_SRES_2.dout or
RB_SRES_3.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : rb_sres_or_mon
port map (
RB_SRES_1 => RB_SRES_1,
RB_SRES_2 => RB_SRES_2,
RB_SRES_3 => RB_SRES_3,
RB_SRES_4 => rb_sres_init
);
-- synthesis translate_on
end syn;
|
-- $Id: rb_sres_or_3.vhd 343 2010-12-05 21:24:38Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_3 - syn
-- Description: rbus result or, 3 input
--
-- Dependencies: rb_sres_or_mon [sim only]
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon
-- 2010-06-26 309 1.1 add rritb_sres_or_mon
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
-- 2008-01-20 113 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity rb_sres_or_3 is -- rbus result or, 3 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end rb_sres_or_3;
architecture syn of rb_sres_or_3 is
begin
proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3)
begin
RB_SRES_OR.ack <= RB_SRES_1.ack or
RB_SRES_2.ack or
RB_SRES_3.ack;
RB_SRES_OR.busy <= RB_SRES_1.busy or
RB_SRES_2.busy or
RB_SRES_3.busy;
RB_SRES_OR.err <= RB_SRES_1.err or
RB_SRES_2.err or
RB_SRES_3.err;
RB_SRES_OR.dout <= RB_SRES_1.dout or
RB_SRES_2.dout or
RB_SRES_3.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : rb_sres_or_mon
port map (
RB_SRES_1 => RB_SRES_1,
RB_SRES_2 => RB_SRES_2,
RB_SRES_3 => RB_SRES_3,
RB_SRES_4 => rb_sres_init
);
-- synthesis translate_on
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity ent;
architecture arch of ent is
signal test: natural;
constant e : natural := 3;
begin
LL: case e generate
when 0 =>
when 1 to 4 =>
test <= 1;
when l5: 5 | 7=>
test <= 2;
when others =>
end generate ll;
process
begin
wait for 0 ns;
assert test = 2;
wait;
end process;
end architecture arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
end entity ent;
architecture arch of ent is
signal test: natural;
constant e : natural := 3;
begin
LL: case e generate
when 0 =>
when 1 to 4 =>
test <= 1;
when l5: 5 | 7=>
test <= 2;
when others =>
end generate ll;
process
begin
wait for 0 ns;
assert test = 2;
wait;
end process;
end architecture arch;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Fri Jul 8 09:16:27 2016
-- Host : jalapeno running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim {/home/hhassan/git/GateKeeper/FPGA
-- Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/shd_fifo_sim_netlist.vhdl}
-- Design : shd_fifo
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7vx690tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_blk_mem_gen_prim_wrapper is
port (
D : out STD_LOGIC_VECTOR ( 71 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 71 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end shd_fifo_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of shd_fifo_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 72,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 72
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 6) => \gc0.count_d1_reg[8]\(8 downto 0),
ADDRARDADDR(5 downto 0) => B"111111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 6) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
ADDRBWRADDR(5 downto 0) => B"111111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => rd_clk,
CLKBWRCLK => wr_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 24) => din(34 downto 27),
DIADI(23 downto 16) => din(25 downto 18),
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 24) => din(70 downto 63),
DIBDI(23 downto 16) => din(61 downto 54),
DIBDI(15 downto 8) => din(52 downto 45),
DIBDI(7 downto 0) => din(43 downto 36),
DIPADIP(3) => din(35),
DIPADIP(2) => din(26),
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3) => din(71),
DIPBDIP(2) => din(62),
DIPBDIP(1) => din(53),
DIPBDIP(0) => din(44),
DOADO(31 downto 24) => D(34 downto 27),
DOADO(23 downto 16) => D(25 downto 18),
DOADO(15 downto 8) => D(16 downto 9),
DOADO(7 downto 0) => D(7 downto 0),
DOBDO(31 downto 24) => D(70 downto 63),
DOBDO(23 downto 16) => D(61 downto 54),
DOBDO(15 downto 8) => D(52 downto 45),
DOBDO(7 downto 0) => D(43 downto 36),
DOPADOP(3) => D(35),
DOPADOP(2) => D(26),
DOPADOP(1) => D(17),
DOPADOP(0) => D(8),
DOPBDOP(3) => D(71),
DOPBDOP(2) => D(62),
DOPBDOP(1) => D(53),
DOPBDOP(0) => D(44),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => tmp_ram_rd_en,
ENBWREN => E(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => Q(0),
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7) => E(0),
WEBWE(6) => E(0),
WEBWE(5) => E(0),
WEBWE(4) => E(0),
WEBWE(3) => E(0),
WEBWE(2) => E(0),
WEBWE(1) => E(0),
WEBWE(0) => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \shd_fifo_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 55 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 55 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \shd_fifo_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \shd_fifo_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \shd_fifo_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_61\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_69\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 72,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 72
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 6) => \gc0.count_d1_reg[8]\(8 downto 0),
ADDRARDADDR(5 downto 0) => B"111111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 6) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
ADDRBWRADDR(5 downto 0) => B"111111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => rd_clk,
CLKBWRCLK => wr_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30 downto 24) => din(27 downto 21),
DIADI(23) => '0',
DIADI(22 downto 16) => din(20 downto 14),
DIADI(15) => '0',
DIADI(14 downto 8) => din(13 downto 7),
DIADI(7) => '0',
DIADI(6 downto 0) => din(6 downto 0),
DIBDI(31) => '0',
DIBDI(30 downto 24) => din(55 downto 49),
DIBDI(23) => '0',
DIBDI(22 downto 16) => din(48 downto 42),
DIBDI(15) => '0',
DIBDI(14 downto 8) => din(41 downto 35),
DIBDI(7) => '0',
DIBDI(6 downto 0) => din(34 downto 28),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_21\,
DOADO(30 downto 24) => D(27 downto 21),
DOADO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_29\,
DOADO(22 downto 16) => D(20 downto 14),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_37\,
DOADO(14 downto 8) => D(13 downto 7),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_45\,
DOADO(6 downto 0) => D(6 downto 0),
DOBDO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_53\,
DOBDO(30 downto 24) => D(55 downto 49),
DOBDO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_61\,
DOBDO(22 downto 16) => D(48 downto 42),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_69\,
DOBDO(14 downto 8) => D(41 downto 35),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_77\,
DOBDO(6 downto 0) => D(34 downto 28),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_88\,
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => tmp_ram_rd_en,
ENBWREN => E(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => Q(0),
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7) => E(0),
WEBWE(6) => E(0),
WEBWE(5) => E(0),
WEBWE(4) => E(0),
WEBWE(3) => E(0),
WEBWE(2) => E(0),
WEBWE(1) => E(0),
WEBWE(0) => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_compare is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[8]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_compare : entity is "compare";
end shd_fifo_compare;
architecture STRUCTURE of shd_fifo_compare is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gic0.gc0.count_d1_reg[8]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_compare_0 is
port (
ram_full_i : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_reg[8]\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_0_out : in STD_LOGIC;
comp1 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_compare_0 : entity is "compare";
end shd_fifo_compare_0;
architecture STRUCTURE of shd_fifo_compare_0 is
signal comp2 : STD_LOGIC;
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp2,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gic0.gc0.count_reg[8]\
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FF08"
)
port map (
I0 => comp2,
I1 => wr_en,
I2 => p_0_out,
I3 => comp1,
I4 => rst_full_gen_i,
O => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_compare_1 is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wr_pntr_bin_reg[8]\ : in STD_LOGIC;
p_2_out : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_compare_1 : entity is "compare";
end shd_fifo_compare_1;
architecture STRUCTURE of shd_fifo_compare_1 is
signal comp0 : STD_LOGIC;
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \wr_pntr_bin_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBABBBAAAAAAAA"
)
port map (
I0 => comp0,
I1 => p_2_out,
I2 => \gpregsm1.curr_fwft_state_reg[1]\(0),
I3 => \gpregsm1.curr_fwft_state_reg[1]\(1),
I4 => rd_en,
I5 => comp1,
O => ram_empty_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_compare_2 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[8]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_compare_2 : entity is "compare";
end shd_fifo_compare_2;
architecture STRUCTURE of shd_fifo_compare_2 is
signal \gmux.gm[3].gms.ms_n_0\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gmux.gm[3].gms.ms_n_0\,
CO(2 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => \gmux.gm[3].gms.ms_n_0\,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gc0.count_reg[8]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_rd_bin_cntr is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 8 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_rd_bin_cntr : entity is "rd_bin_cntr";
end shd_fifo_rd_bin_cntr;
architecture STRUCTURE of shd_fifo_rd_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 8 to 8 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[8]_i_2\ : label is "soft_lutpair12";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8 downto 0);
Q(7 downto 0) <= \^q\(7 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(2),
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \^q\(4),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \gc0.count[8]_i_2_n_0\,
I3 => \^q\(5),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(7),
I1 => \^q\(5),
I2 => \gc0.count[8]_i_2_n_0\,
I3 => \^q\(4),
I4 => \^q\(6),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => rd_pntr_plus1(8),
I1 => \^q\(6),
I2 => \^q\(4),
I3 => \gc0.count[8]_i_2_n_0\,
I4 => \^q\(5),
I5 => \^q\(7),
O => plusOp(8)
);
\gc0.count[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
O => \gc0.count[8]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => rd_pntr_plus1(8),
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(8)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => plusOp(0),
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(6),
Q => \^q\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(7),
Q => \^q\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => plusOp(8),
Q => rd_pntr_plus1(8)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I1 => WR_PNTR_RD(1),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I3 => WR_PNTR_RD(0),
O => v1_reg(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(3),
I1 => WR_PNTR_RD(3),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(2),
I3 => WR_PNTR_RD(2),
O => v1_reg(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(5),
I1 => WR_PNTR_RD(5),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(4),
I3 => WR_PNTR_RD(4),
O => v1_reg(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(7),
I1 => WR_PNTR_RD(7),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(6),
I3 => WR_PNTR_RD(6),
O => v1_reg(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rd_pntr_plus1(8),
I1 => WR_PNTR_RD(8),
O => ram_empty_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_rd_fwft is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
\goreg_bm.dout_i_reg[127]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_2_out : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_rd_fwft : entity is "rd_fwft";
end shd_fifo_rd_fwft;
architecture STRUCTURE of shd_fifo_rd_fwft is
signal \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \gpregsm1.curr_fwft_state[0]_i_1_n_0\ : STD_LOGIC;
signal \gpregsm1.curr_fwft_state[1]_i_1_n_0\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair9";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[8]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair8";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(1 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1 downto 0);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAEFFF"
)
port map (
I0 => Q(0),
I1 => rd_en,
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I3 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I4 => p_2_out,
O => tmp_ram_rd_en
);
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"BA22"
)
port map (
I0 => empty_fwft_fb,
I1 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I2 => rd_en,
I3 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(1),
Q => empty
);
\gc0.count_d1[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => p_2_out,
I1 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I3 => rd_en,
O => E(0)
);
\goreg_bm.dout_i[127]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I1 => rd_en,
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
O => \goreg_bm.dout_i_reg[127]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I1 => rd_en,
I2 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
O => \gpregsm1.curr_fwft_state[0]_i_1_n_0\
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FF"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0),
I1 => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1),
I2 => rd_en,
I3 => p_2_out,
O => \gpregsm1.curr_fwft_state[1]_i_1_n_0\
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(1),
D => \gpregsm1.curr_fwft_state[0]_i_1_n_0\,
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(1),
D => \gpregsm1.curr_fwft_state[1]_i_1_n_0\,
Q => \^device_7series.no_bmm_info.sdp.wide_prim36_no_ecc.ram\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_reset_blk_ramfifo is
port (
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end shd_fifo_reset_blk_ramfifo;
architecture STRUCTURE of shd_fifo_reset_blk_ramfifo is
signal inverted_reset : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
begin
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => inverted_reset,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => inverted_reset,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_aresetn,
O => inverted_reset
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \shd_fifo_reset_blk_ramfifo__parameterized0\ is
port (
rst_full_ff_i : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \shd_fifo_reset_blk_ramfifo__parameterized0\ : entity is "reset_blk_ramfifo";
end \shd_fifo_reset_blk_ramfifo__parameterized0\;
architecture STRUCTURE of \shd_fifo_reset_blk_ramfifo__parameterized0\ is
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_full_ff_i <= rst_d2;
rst_full_gen_i <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg,
Q => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg_n_0\,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \gc0.count_reg[1]\(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \gc0.count_reg[1]\(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \gc0.count_reg[1]\(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg,
Q => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg_n_0\,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => Q(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_synchronizer_ff is
port (
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_synchronizer_ff : entity is "synchronizer_ff";
end shd_fifo_synchronizer_ff;
architecture STRUCTURE of shd_fifo_synchronizer_ff is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
begin
D(8 downto 0) <= Q_reg(8 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => Q_reg(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_synchronizer_ff_3 is
port (
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_synchronizer_ff_3 : entity is "synchronizer_ff";
end shd_fifo_synchronizer_ff_3;
architecture STRUCTURE of shd_fifo_synchronizer_ff_3 is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
begin
D(8 downto 0) <= Q_reg(8 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(8),
Q => Q_reg(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_synchronizer_ff_4 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wr_pntr_bin_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 8 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_synchronizer_ff_4 : entity is "synchronizer_ff";
end shd_fifo_synchronizer_ff_4;
architecture STRUCTURE of shd_fifo_synchronizer_ff_4 is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \wr_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
begin
\out\(0) <= Q_reg(8);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(8),
Q => Q_reg(8)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => \wr_pntr_bin[2]_i_2_n_0\,
I3 => Q_reg(3),
I4 => Q_reg(2),
I5 => Q_reg(8),
O => \wr_pntr_bin_reg[7]\(0)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \wr_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(3),
I2 => Q_reg(2),
I3 => Q_reg(8),
I4 => Q_reg(1),
O => \wr_pntr_bin_reg[7]\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(2),
I2 => Q_reg(3),
I3 => \wr_pntr_bin[2]_i_2_n_0\,
O => \wr_pntr_bin_reg[7]\(2)
);
\wr_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(5),
I3 => Q_reg(4),
O => \wr_pntr_bin[2]_i_2_n_0\
);
\wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => Q_reg(8),
I4 => Q_reg(6),
I5 => Q_reg(7),
O => \wr_pntr_bin_reg[7]\(3)
);
\wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(8),
I4 => Q_reg(7),
O => \wr_pntr_bin_reg[7]\(4)
);
\wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(5),
I2 => Q_reg(8),
I3 => Q_reg(7),
O => \wr_pntr_bin_reg[7]\(5)
);
\wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(8),
O => \wr_pntr_bin_reg[7]\(6)
);
\wr_pntr_bin[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(8),
O => \wr_pntr_bin_reg[7]\(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_synchronizer_ff_5 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\rd_pntr_bin_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
D : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_synchronizer_ff_5 : entity is "synchronizer_ff";
end shd_fifo_synchronizer_ff_5;
architecture STRUCTURE of shd_fifo_synchronizer_ff_5 is
signal Q_reg : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \rd_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
begin
\out\(0) <= Q_reg(8);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(8),
Q => Q_reg(8)
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => \rd_pntr_bin[2]_i_2_n_0\,
I3 => Q_reg(3),
I4 => Q_reg(2),
I5 => Q_reg(8),
O => \rd_pntr_bin_reg[7]\(0)
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \rd_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(3),
I2 => Q_reg(2),
I3 => Q_reg(8),
I4 => Q_reg(1),
O => \rd_pntr_bin_reg[7]\(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(2),
I2 => Q_reg(3),
I3 => \rd_pntr_bin[2]_i_2_n_0\,
O => \rd_pntr_bin_reg[7]\(2)
);
\rd_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(5),
I3 => Q_reg(4),
O => \rd_pntr_bin[2]_i_2_n_0\
);
\rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => Q_reg(8),
I4 => Q_reg(6),
I5 => Q_reg(7),
O => \rd_pntr_bin_reg[7]\(3)
);
\rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(8),
I4 => Q_reg(7),
O => \rd_pntr_bin_reg[7]\(4)
);
\rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(5),
I2 => Q_reg(8),
I3 => Q_reg(7),
O => \rd_pntr_bin_reg[7]\(5)
);
\rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(8),
O => \rd_pntr_bin_reg[7]\(6)
);
\rd_pntr_bin[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(8),
O => \rd_pntr_bin_reg[7]\(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_wr_bin_cntr is
port (
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_wr_bin_cntr : entity is "wr_bin_cntr";
end shd_fifo_wr_bin_cntr;
architecture STRUCTURE of shd_fifo_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gic0.gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \^gic0.gc0.count_d2_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 8 to 8 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[6]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[8]_i_2\ : label is "soft_lutpair15";
begin
Q(7 downto 0) <= \^q\(7 downto 0);
\gic0.gc0.count_d2_reg[7]_0\(7 downto 0) <= \^gic0.gc0.count_d2_reg[7]_0\(7 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
O => \plusOp__0\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(2),
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \^q\(4),
O => \plusOp__0\(5)
);
\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \gic0.gc0.count[8]_i_2_n_0\,
I3 => \^q\(5),
O => \plusOp__0\(6)
);
\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^q\(7),
I1 => \^q\(5),
I2 => \gic0.gc0.count[8]_i_2_n_0\,
I3 => \^q\(4),
I4 => \^q\(6),
O => \plusOp__0\(7)
);
\gic0.gc0.count[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => wr_pntr_plus2(8),
I1 => \^q\(6),
I2 => \^q\(4),
I3 => \gic0.gc0.count[8]_i_2_n_0\,
I4 => \^q\(5),
I5 => \^q\(7),
O => \plusOp__0\(8)
);
\gic0.gc0.count[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
O => \gic0.gc0.count[8]_i_2_n_0\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \^q\(0),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => \^gic0.gc0.count_d2_reg[7]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[7]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[7]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[7]_0\(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(4),
Q => \^gic0.gc0.count_d2_reg[7]_0\(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(5),
Q => \^gic0.gc0.count_d2_reg[7]_0\(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(6),
Q => \^gic0.gc0.count_d2_reg[7]_0\(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(7),
Q => \^gic0.gc0.count_d2_reg[7]_0\(7)
);
\gic0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => wr_pntr_plus2(8),
Q => p_12_out(8)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(7)
);
\gic0.gc0.count_d2_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(4),
Q => \^q\(4)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(5),
Q => \^q\(5)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(6),
Q => \^q\(6)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(7),
Q => \^q\(7)
);
\gic0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(8),
Q => wr_pntr_plus2(8)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_12_out(8),
I1 => RD_PNTR_WR(0),
O => ram_full_fb_i_reg
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => wr_pntr_plus2(8),
I1 => RD_PNTR_WR(0),
O => ram_full_fb_i_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_blk_mem_gen_prim_width is
port (
D : out STD_LOGIC_VECTOR ( 71 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 71 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end shd_fifo_blk_mem_gen_prim_width;
architecture STRUCTURE of shd_fifo_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.shd_fifo_blk_mem_gen_prim_wrapper
port map (
D(71 downto 0) => D(71 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(71 downto 0) => din(71 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \shd_fifo_blk_mem_gen_prim_width__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 55 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 55 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \shd_fifo_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \shd_fifo_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \shd_fifo_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\shd_fifo_blk_mem_gen_prim_wrapper__parameterized0\
port map (
D(55 downto 0) => D(55 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(55 downto 0) => din(55 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_clk_x_pntrs is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
WR_PNTR_RD : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_clk_x_pntrs : entity is "clk_x_pntrs";
end shd_fifo_clk_x_pntrs;
architecture STRUCTURE of shd_fifo_clk_x_pntrs is
signal \^wr_pntr_rd\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_8\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_in7_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal p_1_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal p_22_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_2_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[7]_i_1_n_0\ : STD_LOGIC;
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_gc[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rd_pntr_gc[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rd_pntr_gc[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rd_pntr_gc[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wr_pntr_gc[7]_i_1\ : label is "soft_lutpair3";
begin
WR_PNTR_RD(8 downto 0) <= \^wr_pntr_rd\(8 downto 0);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(1),
I1 => \gc0.count_reg[7]\(1),
I2 => \^wr_pntr_rd\(0),
I3 => \gc0.count_reg[7]\(0),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(1),
I1 => \gic0.gc0.count_d1_reg[7]\(1),
I2 => p_22_out(0),
I3 => \gic0.gc0.count_d1_reg[7]\(0),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(1),
I1 => \gic0.gc0.count_reg[7]\(1),
I2 => p_22_out(0),
I3 => \gic0.gc0.count_reg[7]\(0),
O => v1_reg_1(0)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(3),
I1 => \gc0.count_reg[7]\(3),
I2 => \^wr_pntr_rd\(2),
I3 => \gc0.count_reg[7]\(2),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(3),
I1 => \gic0.gc0.count_d1_reg[7]\(3),
I2 => p_22_out(2),
I3 => \gic0.gc0.count_d1_reg[7]\(2),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(3),
I1 => \gic0.gc0.count_reg[7]\(3),
I2 => p_22_out(2),
I3 => \gic0.gc0.count_reg[7]\(2),
O => v1_reg_1(1)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(5),
I1 => \gc0.count_reg[7]\(5),
I2 => \^wr_pntr_rd\(4),
I3 => \gc0.count_reg[7]\(4),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(5),
I1 => \gic0.gc0.count_d1_reg[7]\(5),
I2 => p_22_out(4),
I3 => \gic0.gc0.count_d1_reg[7]\(4),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(5),
I1 => \gic0.gc0.count_reg[7]\(5),
I2 => p_22_out(4),
I3 => \gic0.gc0.count_reg[7]\(4),
O => v1_reg_1(2)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^wr_pntr_rd\(7),
I1 => \gc0.count_reg[7]\(7),
I2 => \^wr_pntr_rd\(6),
I3 => \gc0.count_reg[7]\(6),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(7),
I1 => \gic0.gc0.count_d1_reg[7]\(7),
I2 => p_22_out(6),
I3 => \gic0.gc0.count_d1_reg[7]\(6),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(7),
I1 => \gic0.gc0.count_reg[7]\(7),
I2 => p_22_out(6),
I3 => \gic0.gc0.count_reg[7]\(6),
O => v1_reg_1(3)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wr_pntr_rd\(8),
I1 => Q(8),
O => ram_empty_fb_i_reg
);
\gsync_stage[1].rd_stg_inst\: entity work.shd_fifo_synchronizer_ff
port map (
D(8 downto 0) => p_3_out(8 downto 0),
Q(8 downto 0) => wr_pntr_gc(8 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gsync_stage[1].wr_stg_inst\: entity work.shd_fifo_synchronizer_ff_3
port map (
D(8 downto 0) => p_2_out(8 downto 0),
Q(8 downto 0) => rd_pntr_gc(8 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
wr_clk => wr_clk
);
\gsync_stage[2].rd_stg_inst\: entity work.shd_fifo_synchronizer_ff_4
port map (
D(8 downto 0) => p_3_out(8 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_1_out(8),
rd_clk => rd_clk,
\wr_pntr_bin_reg[7]\(7 downto 0) => p_0_in(7 downto 0)
);
\gsync_stage[2].wr_stg_inst\: entity work.shd_fifo_synchronizer_ff_5
port map (
D(8 downto 0) => p_2_out(8 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
\out\(0) => p_0_out(8),
\rd_pntr_bin_reg[7]\(7) => \gsync_stage[2].wr_stg_inst_n_1\,
\rd_pntr_bin_reg[7]\(6) => \gsync_stage[2].wr_stg_inst_n_2\,
\rd_pntr_bin_reg[7]\(5) => \gsync_stage[2].wr_stg_inst_n_3\,
\rd_pntr_bin_reg[7]\(4) => \gsync_stage[2].wr_stg_inst_n_4\,
\rd_pntr_bin_reg[7]\(3) => \gsync_stage[2].wr_stg_inst_n_5\,
\rd_pntr_bin_reg[7]\(2) => \gsync_stage[2].wr_stg_inst_n_6\,
\rd_pntr_bin_reg[7]\(1) => \gsync_stage[2].wr_stg_inst_n_7\,
\rd_pntr_bin_reg[7]\(0) => \gsync_stage[2].wr_stg_inst_n_8\,
wr_clk => wr_clk
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_8\,
Q => p_22_out(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_7\,
Q => p_22_out(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_6\,
Q => p_22_out(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_5\,
Q => p_22_out(3)
);
\rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_4\,
Q => p_22_out(4)
);
\rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_3\,
Q => p_22_out(5)
);
\rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_2\,
Q => p_22_out(6)
);
\rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_1\,
Q => p_22_out(7)
);
\rd_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_out(8),
Q => RD_PNTR_WR(0)
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => \rd_pntr_gc[0]_i_1_n_0\
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => \rd_pntr_gc[1]_i_1_n_0\
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => \rd_pntr_gc[2]_i_1_n_0\
);
\rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => \rd_pntr_gc[3]_i_1_n_0\
);
\rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => \rd_pntr_gc[4]_i_1_n_0\
);
\rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => \rd_pntr_gc[5]_i_1_n_0\
);
\rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => \rd_pntr_gc[6]_i_1_n_0\
);
\rd_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => Q(8),
O => \rd_pntr_gc[7]_i_1_n_0\
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[7]_i_1_n_0\,
Q => rd_pntr_gc(7)
);
\rd_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => rd_pntr_gc(8)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(0),
Q => \^wr_pntr_rd\(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(1),
Q => \^wr_pntr_rd\(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(2),
Q => \^wr_pntr_rd\(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(3),
Q => \^wr_pntr_rd\(3)
);
\wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(4),
Q => \^wr_pntr_rd\(4)
);
\wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(5),
Q => \^wr_pntr_rd\(5)
);
\wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(6),
Q => \^wr_pntr_rd\(6)
);
\wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(7),
Q => \^wr_pntr_rd\(7)
);
\wr_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_1_out(8),
Q => \^wr_pntr_rd\(8)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(0),
I1 => \gic0.gc0.count_d2_reg[8]\(1),
O => p_0_in7_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(1),
I1 => \gic0.gc0.count_d2_reg[8]\(2),
O => p_0_in7_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(2),
I1 => \gic0.gc0.count_d2_reg[8]\(3),
O => p_0_in7_out(2)
);
\wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(3),
I1 => \gic0.gc0.count_d2_reg[8]\(4),
O => p_0_in7_out(3)
);
\wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(4),
I1 => \gic0.gc0.count_d2_reg[8]\(5),
O => p_0_in7_out(4)
);
\wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(5),
I1 => \gic0.gc0.count_d2_reg[8]\(6),
O => p_0_in7_out(5)
);
\wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(6),
I1 => \gic0.gc0.count_d2_reg[8]\(7),
O => p_0_in7_out(6)
);
\wr_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[8]\(7),
I1 => \gic0.gc0.count_d2_reg[8]\(8),
O => p_0_in7_out(7)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(3),
Q => wr_pntr_gc(3)
);
\wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(4),
Q => wr_pntr_gc(4)
);
\wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(5),
Q => wr_pntr_gc(5)
);
\wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(6),
Q => wr_pntr_gc(6)
);
\wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in7_out(7),
Q => wr_pntr_gc(7)
);
\wr_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gic0.gc0.count_d2_reg[8]\(8),
Q => wr_pntr_gc(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_rd_status_flags_as is
port (
p_2_out : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wr_pntr_bin_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[8]\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_rd_status_flags_as : entity is "rd_status_flags_as";
end shd_fifo_rd_status_flags_as;
architecture STRUCTURE of shd_fifo_rd_status_flags_as is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal \^p_2_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
p_2_out <= \^p_2_out\;
c0: entity work.shd_fifo_compare_1
port map (
comp1 => comp1,
\gpregsm1.curr_fwft_state_reg[1]\(1 downto 0) => \gpregsm1.curr_fwft_state_reg[1]\(1 downto 0),
p_2_out => \^p_2_out\,
ram_empty_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0),
\wr_pntr_bin_reg[8]\ => \wr_pntr_bin_reg[8]\
);
c1: entity work.shd_fifo_compare_2
port map (
comp1 => comp1,
\gc0.count_reg[8]\ => \gc0.count_reg[8]\,
v1_reg(3 downto 0) => v1_reg(3 downto 0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => Q(0),
Q => \^p_2_out\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_wr_status_flags_as is
port (
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_reg[8]\ : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_wr_status_flags_as : entity is "wr_status_flags_as";
end shd_fifo_wr_status_flags_as;
architecture STRUCTURE of shd_fifo_wr_status_flags_as is
signal comp1 : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal ram_full_i : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => p_0_out,
O => E(0)
);
c1: entity work.shd_fifo_compare
port map (
comp1 => comp1,
\gic0.gc0.count_d1_reg[8]\ => \gic0.gc0.count_d1_reg[8]\,
v1_reg(3 downto 0) => v1_reg(3 downto 0)
);
c2: entity work.shd_fifo_compare_0
port map (
comp1 => comp1,
\gic0.gc0.count_reg[8]\ => \gic0.gc0.count_reg[8]\,
p_0_out => p_0_out,
ram_full_i => ram_full_i,
rst_full_gen_i => rst_full_gen_i,
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0),
wr_en => wr_en
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => p_0_out
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_blk_mem_gen_generic_cstr is
port (
D : out STD_LOGIC_VECTOR ( 127 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end shd_fifo_blk_mem_gen_generic_cstr;
architecture STRUCTURE of shd_fifo_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.shd_fifo_blk_mem_gen_prim_width
port map (
D(71 downto 0) => D(71 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(71 downto 0) => din(71 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
\ramloop[1].ram.r\: entity work.\shd_fifo_blk_mem_gen_prim_width__parameterized0\
port map (
D(55 downto 0) => D(127 downto 72),
E(0) => E(0),
Q(0) => Q(0),
din(55 downto 0) => din(127 downto 72),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_rd_logic is
port (
empty : out STD_LOGIC;
\gc0.count_d1_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\wr_pntr_bin_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_rd_logic : entity is "rd_logic";
end shd_fifo_rd_logic;
architecture STRUCTURE of shd_fifo_rd_logic is
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.rfwft_n_1\ : STD_LOGIC;
signal \gr1.rfwft_n_2\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rpntr_n_0 : STD_LOGIC;
begin
\gr1.rfwft\: entity work.shd_fifo_rd_fwft
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(1) => \gr1.rfwft_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(0) => curr_fwft_state(0),
E(0) => \gr1.rfwft_n_1\,
Q(1 downto 0) => Q(1 downto 0),
empty => empty,
\goreg_bm.dout_i_reg[127]\(0) => E(0),
p_2_out => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en,
tmp_ram_rd_en => tmp_ram_rd_en
);
\gras.rsts\: entity work.shd_fifo_rd_status_flags_as
port map (
Q(0) => Q(1),
\gc0.count_reg[8]\ => rpntr_n_0,
\gpregsm1.curr_fwft_state_reg[1]\(1) => \gr1.rfwft_n_2\,
\gpregsm1.curr_fwft_state_reg[1]\(0) => curr_fwft_state(0),
p_2_out => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en,
v1_reg(3 downto 0) => v1_reg(3 downto 0),
v1_reg_0(3 downto 0) => \c0/v1_reg\(3 downto 0),
\wr_pntr_bin_reg[8]\ => \wr_pntr_bin_reg[8]\
);
rpntr: entity work.shd_fifo_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0),
E(0) => \gr1.rfwft_n_1\,
Q(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
WR_PNTR_RD(8 downto 0) => WR_PNTR_RD(8 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => Q(1),
ram_empty_fb_i_reg => rpntr_n_0,
rd_clk => rd_clk,
v1_reg(3 downto 0) => \c0/v1_reg\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_wr_logic is
port (
full : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d1_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_wr_logic : entity is "wr_logic";
end shd_fifo_wr_logic;
architecture STRUCTURE of shd_fifo_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wpntr_n_0 : STD_LOGIC;
signal wpntr_n_1 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.shd_fifo_wr_status_flags_as
port map (
E(0) => \^e\(0),
full => full,
\gic0.gc0.count_d1_reg[8]\ => wpntr_n_0,
\gic0.gc0.count_reg[8]\ => wpntr_n_1,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
v1_reg(3 downto 0) => v1_reg(3 downto 0),
v1_reg_0(3 downto 0) => v1_reg_0(3 downto 0),
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.shd_fifo_wr_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0),
E(0) => \^e\(0),
Q(7 downto 0) => \gic0.gc0.count_d1_reg[7]\(7 downto 0),
RD_PNTR_WR(0) => RD_PNTR_WR(0),
\gic0.gc0.count_d2_reg[7]_0\(7 downto 0) => Q(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
ram_full_fb_i_reg => wpntr_n_0,
ram_full_fb_i_reg_0 => wpntr_n_1,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_blk_mem_gen_top is
port (
D : out STD_LOGIC_VECTOR ( 127 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_blk_mem_gen_top : entity is "blk_mem_gen_top";
end shd_fifo_blk_mem_gen_top;
architecture STRUCTURE of shd_fifo_blk_mem_gen_top is
begin
\valid.cstr\: entity work.shd_fifo_blk_mem_gen_generic_cstr
port map (
D(127 downto 0) => D(127 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(127 downto 0) => din(127 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_blk_mem_gen_v8_3_1_synth is
port (
D : out STD_LOGIC_VECTOR ( 127 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth";
end shd_fifo_blk_mem_gen_v8_3_1_synth;
architecture STRUCTURE of shd_fifo_blk_mem_gen_v8_3_1_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.shd_fifo_blk_mem_gen_top
port map (
D(127 downto 0) => D(127 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(127 downto 0) => din(127 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_blk_mem_gen_v8_3_1 is
port (
D : out STD_LOGIC_VECTOR ( 127 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1";
end shd_fifo_blk_mem_gen_v8_3_1;
architecture STRUCTURE of shd_fifo_blk_mem_gen_v8_3_1 is
begin
inst_blk_mem_gen: entity work.shd_fifo_blk_mem_gen_v8_3_1_synth
port map (
D(127 downto 0) => D(127 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(127 downto 0) => din(127 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_memory is
port (
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\gic0.gc0.count_d2_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_memory : entity is "memory";
end shd_fifo_memory;
architecture STRUCTURE of shd_fifo_memory is
signal doutb : STD_LOGIC_VECTOR ( 127 downto 0 );
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.shd_fifo_blk_mem_gen_v8_3_1
port map (
D(127 downto 0) => doutb(127 downto 0),
E(0) => E(0),
Q(0) => Q(0),
din(127 downto 0) => din(127 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => \gc0.count_d1_reg[8]\(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => \gic0.gc0.count_d2_reg[8]\(8 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
\goreg_bm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(0),
Q => dout(0),
R => Q(0)
);
\goreg_bm.dout_i_reg[100]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(100),
Q => dout(100),
R => Q(0)
);
\goreg_bm.dout_i_reg[101]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(101),
Q => dout(101),
R => Q(0)
);
\goreg_bm.dout_i_reg[102]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(102),
Q => dout(102),
R => Q(0)
);
\goreg_bm.dout_i_reg[103]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(103),
Q => dout(103),
R => Q(0)
);
\goreg_bm.dout_i_reg[104]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(104),
Q => dout(104),
R => Q(0)
);
\goreg_bm.dout_i_reg[105]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(105),
Q => dout(105),
R => Q(0)
);
\goreg_bm.dout_i_reg[106]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(106),
Q => dout(106),
R => Q(0)
);
\goreg_bm.dout_i_reg[107]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(107),
Q => dout(107),
R => Q(0)
);
\goreg_bm.dout_i_reg[108]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(108),
Q => dout(108),
R => Q(0)
);
\goreg_bm.dout_i_reg[109]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(109),
Q => dout(109),
R => Q(0)
);
\goreg_bm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(10),
Q => dout(10),
R => Q(0)
);
\goreg_bm.dout_i_reg[110]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(110),
Q => dout(110),
R => Q(0)
);
\goreg_bm.dout_i_reg[111]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(111),
Q => dout(111),
R => Q(0)
);
\goreg_bm.dout_i_reg[112]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(112),
Q => dout(112),
R => Q(0)
);
\goreg_bm.dout_i_reg[113]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(113),
Q => dout(113),
R => Q(0)
);
\goreg_bm.dout_i_reg[114]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(114),
Q => dout(114),
R => Q(0)
);
\goreg_bm.dout_i_reg[115]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(115),
Q => dout(115),
R => Q(0)
);
\goreg_bm.dout_i_reg[116]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(116),
Q => dout(116),
R => Q(0)
);
\goreg_bm.dout_i_reg[117]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(117),
Q => dout(117),
R => Q(0)
);
\goreg_bm.dout_i_reg[118]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(118),
Q => dout(118),
R => Q(0)
);
\goreg_bm.dout_i_reg[119]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(119),
Q => dout(119),
R => Q(0)
);
\goreg_bm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(11),
Q => dout(11),
R => Q(0)
);
\goreg_bm.dout_i_reg[120]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(120),
Q => dout(120),
R => Q(0)
);
\goreg_bm.dout_i_reg[121]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(121),
Q => dout(121),
R => Q(0)
);
\goreg_bm.dout_i_reg[122]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(122),
Q => dout(122),
R => Q(0)
);
\goreg_bm.dout_i_reg[123]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(123),
Q => dout(123),
R => Q(0)
);
\goreg_bm.dout_i_reg[124]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(124),
Q => dout(124),
R => Q(0)
);
\goreg_bm.dout_i_reg[125]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(125),
Q => dout(125),
R => Q(0)
);
\goreg_bm.dout_i_reg[126]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(126),
Q => dout(126),
R => Q(0)
);
\goreg_bm.dout_i_reg[127]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(127),
Q => dout(127),
R => Q(0)
);
\goreg_bm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(12),
Q => dout(12),
R => Q(0)
);
\goreg_bm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(13),
Q => dout(13),
R => Q(0)
);
\goreg_bm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(14),
Q => dout(14),
R => Q(0)
);
\goreg_bm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(15),
Q => dout(15),
R => Q(0)
);
\goreg_bm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(16),
Q => dout(16),
R => Q(0)
);
\goreg_bm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(17),
Q => dout(17),
R => Q(0)
);
\goreg_bm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(18),
Q => dout(18),
R => Q(0)
);
\goreg_bm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(19),
Q => dout(19),
R => Q(0)
);
\goreg_bm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(1),
Q => dout(1),
R => Q(0)
);
\goreg_bm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(20),
Q => dout(20),
R => Q(0)
);
\goreg_bm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(21),
Q => dout(21),
R => Q(0)
);
\goreg_bm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(22),
Q => dout(22),
R => Q(0)
);
\goreg_bm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(23),
Q => dout(23),
R => Q(0)
);
\goreg_bm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(24),
Q => dout(24),
R => Q(0)
);
\goreg_bm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(25),
Q => dout(25),
R => Q(0)
);
\goreg_bm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(26),
Q => dout(26),
R => Q(0)
);
\goreg_bm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(27),
Q => dout(27),
R => Q(0)
);
\goreg_bm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(28),
Q => dout(28),
R => Q(0)
);
\goreg_bm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(29),
Q => dout(29),
R => Q(0)
);
\goreg_bm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(2),
Q => dout(2),
R => Q(0)
);
\goreg_bm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(30),
Q => dout(30),
R => Q(0)
);
\goreg_bm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(31),
Q => dout(31),
R => Q(0)
);
\goreg_bm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(32),
Q => dout(32),
R => Q(0)
);
\goreg_bm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(33),
Q => dout(33),
R => Q(0)
);
\goreg_bm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(34),
Q => dout(34),
R => Q(0)
);
\goreg_bm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(35),
Q => dout(35),
R => Q(0)
);
\goreg_bm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(36),
Q => dout(36),
R => Q(0)
);
\goreg_bm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(37),
Q => dout(37),
R => Q(0)
);
\goreg_bm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(38),
Q => dout(38),
R => Q(0)
);
\goreg_bm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(39),
Q => dout(39),
R => Q(0)
);
\goreg_bm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(3),
Q => dout(3),
R => Q(0)
);
\goreg_bm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(40),
Q => dout(40),
R => Q(0)
);
\goreg_bm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(41),
Q => dout(41),
R => Q(0)
);
\goreg_bm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(42),
Q => dout(42),
R => Q(0)
);
\goreg_bm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(43),
Q => dout(43),
R => Q(0)
);
\goreg_bm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(44),
Q => dout(44),
R => Q(0)
);
\goreg_bm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(45),
Q => dout(45),
R => Q(0)
);
\goreg_bm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(46),
Q => dout(46),
R => Q(0)
);
\goreg_bm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(47),
Q => dout(47),
R => Q(0)
);
\goreg_bm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(48),
Q => dout(48),
R => Q(0)
);
\goreg_bm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(49),
Q => dout(49),
R => Q(0)
);
\goreg_bm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(4),
Q => dout(4),
R => Q(0)
);
\goreg_bm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(50),
Q => dout(50),
R => Q(0)
);
\goreg_bm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(51),
Q => dout(51),
R => Q(0)
);
\goreg_bm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(52),
Q => dout(52),
R => Q(0)
);
\goreg_bm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(53),
Q => dout(53),
R => Q(0)
);
\goreg_bm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(54),
Q => dout(54),
R => Q(0)
);
\goreg_bm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(55),
Q => dout(55),
R => Q(0)
);
\goreg_bm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(56),
Q => dout(56),
R => Q(0)
);
\goreg_bm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(57),
Q => dout(57),
R => Q(0)
);
\goreg_bm.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(58),
Q => dout(58),
R => Q(0)
);
\goreg_bm.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(59),
Q => dout(59),
R => Q(0)
);
\goreg_bm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(5),
Q => dout(5),
R => Q(0)
);
\goreg_bm.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(60),
Q => dout(60),
R => Q(0)
);
\goreg_bm.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(61),
Q => dout(61),
R => Q(0)
);
\goreg_bm.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(62),
Q => dout(62),
R => Q(0)
);
\goreg_bm.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(63),
Q => dout(63),
R => Q(0)
);
\goreg_bm.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(64),
Q => dout(64),
R => Q(0)
);
\goreg_bm.dout_i_reg[65]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(65),
Q => dout(65),
R => Q(0)
);
\goreg_bm.dout_i_reg[66]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(66),
Q => dout(66),
R => Q(0)
);
\goreg_bm.dout_i_reg[67]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(67),
Q => dout(67),
R => Q(0)
);
\goreg_bm.dout_i_reg[68]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(68),
Q => dout(68),
R => Q(0)
);
\goreg_bm.dout_i_reg[69]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(69),
Q => dout(69),
R => Q(0)
);
\goreg_bm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(6),
Q => dout(6),
R => Q(0)
);
\goreg_bm.dout_i_reg[70]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(70),
Q => dout(70),
R => Q(0)
);
\goreg_bm.dout_i_reg[71]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(71),
Q => dout(71),
R => Q(0)
);
\goreg_bm.dout_i_reg[72]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(72),
Q => dout(72),
R => Q(0)
);
\goreg_bm.dout_i_reg[73]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(73),
Q => dout(73),
R => Q(0)
);
\goreg_bm.dout_i_reg[74]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(74),
Q => dout(74),
R => Q(0)
);
\goreg_bm.dout_i_reg[75]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(75),
Q => dout(75),
R => Q(0)
);
\goreg_bm.dout_i_reg[76]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(76),
Q => dout(76),
R => Q(0)
);
\goreg_bm.dout_i_reg[77]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(77),
Q => dout(77),
R => Q(0)
);
\goreg_bm.dout_i_reg[78]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(78),
Q => dout(78),
R => Q(0)
);
\goreg_bm.dout_i_reg[79]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(79),
Q => dout(79),
R => Q(0)
);
\goreg_bm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(7),
Q => dout(7),
R => Q(0)
);
\goreg_bm.dout_i_reg[80]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(80),
Q => dout(80),
R => Q(0)
);
\goreg_bm.dout_i_reg[81]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(81),
Q => dout(81),
R => Q(0)
);
\goreg_bm.dout_i_reg[82]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(82),
Q => dout(82),
R => Q(0)
);
\goreg_bm.dout_i_reg[83]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(83),
Q => dout(83),
R => Q(0)
);
\goreg_bm.dout_i_reg[84]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(84),
Q => dout(84),
R => Q(0)
);
\goreg_bm.dout_i_reg[85]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(85),
Q => dout(85),
R => Q(0)
);
\goreg_bm.dout_i_reg[86]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(86),
Q => dout(86),
R => Q(0)
);
\goreg_bm.dout_i_reg[87]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(87),
Q => dout(87),
R => Q(0)
);
\goreg_bm.dout_i_reg[88]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(88),
Q => dout(88),
R => Q(0)
);
\goreg_bm.dout_i_reg[89]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(89),
Q => dout(89),
R => Q(0)
);
\goreg_bm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(8),
Q => dout(8),
R => Q(0)
);
\goreg_bm.dout_i_reg[90]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(90),
Q => dout(90),
R => Q(0)
);
\goreg_bm.dout_i_reg[91]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(91),
Q => dout(91),
R => Q(0)
);
\goreg_bm.dout_i_reg[92]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(92),
Q => dout(92),
R => Q(0)
);
\goreg_bm.dout_i_reg[93]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(93),
Q => dout(93),
R => Q(0)
);
\goreg_bm.dout_i_reg[94]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(94),
Q => dout(94),
R => Q(0)
);
\goreg_bm.dout_i_reg[95]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(95),
Q => dout(95),
R => Q(0)
);
\goreg_bm.dout_i_reg[96]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(96),
Q => dout(96),
R => Q(0)
);
\goreg_bm.dout_i_reg[97]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(97),
Q => dout(97),
R => Q(0)
);
\goreg_bm.dout_i_reg[98]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(98),
Q => dout(98),
R => Q(0)
);
\goreg_bm.dout_i_reg[99]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(99),
Q => dout(99),
R => Q(0)
);
\goreg_bm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => doutb(9),
Q => dout(9),
R => Q(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_fifo_generator_ramfifo is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end shd_fifo_fifo_generator_ramfifo;
architecture STRUCTURE of shd_fifo_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_0\ : STD_LOGIC;
signal \gras.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gwas.wsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gwas.wsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_17_out : STD_LOGIC;
signal p_21_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal p_22_out : STD_LOGIC_VECTOR ( 8 to 8 );
signal p_5_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.shd_fifo_clk_x_pntrs
port map (
Q(8 downto 0) => p_0_out(8 downto 0),
RD_PNTR_WR(0) => p_22_out(8),
WR_PNTR_RD(8 downto 0) => p_21_out(8 downto 0),
\gc0.count_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
\gic0.gc0.count_d1_reg[7]\(7 downto 0) => p_12_out(7 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => p_11_out(8 downto 0),
\gic0.gc0.count_reg[7]\(7 downto 0) => wr_pntr_plus2(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => wr_rst_i(0),
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_0\,
rd_clk => rd_clk,
v1_reg(3 downto 0) => \gras.rsts/c1/v1_reg\(3 downto 0),
v1_reg_0(3 downto 0) => \gwas.wsts/c1/v1_reg\(3 downto 0),
v1_reg_1(3 downto 0) => \gwas.wsts/c2/v1_reg\(3 downto 0),
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.shd_fifo_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => p_0_out(8 downto 0),
E(0) => p_5_out,
Q(1) => RD_RST,
Q(0) => rd_rst_i(0),
WR_PNTR_RD(8 downto 0) => p_21_out(8 downto 0),
empty => empty,
\gc0.count_d1_reg[7]\(7 downto 0) => rd_pntr_plus1(7 downto 0),
rd_clk => rd_clk,
rd_en => rd_en,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(3 downto 0) => \gras.rsts/c1/v1_reg\(3 downto 0),
\wr_pntr_bin_reg[8]\ => \gntv_or_sync_fifo.gcx.clkx_n_0\
);
\gntv_or_sync_fifo.gl0.wr\: entity work.shd_fifo_wr_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram\(8 downto 0) => p_11_out(8 downto 0),
E(0) => p_17_out,
Q(7 downto 0) => p_12_out(7 downto 0),
RD_PNTR_WR(0) => p_22_out(8),
full => full,
\gic0.gc0.count_d1_reg[7]\(7 downto 0) => wr_pntr_plus2(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \^rst\,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
v1_reg(3 downto 0) => \gwas.wsts/c1/v1_reg\(3 downto 0),
v1_reg_0(3 downto 0) => \gwas.wsts/c2/v1_reg\(3 downto 0),
wr_clk => wr_clk,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.shd_fifo_memory
port map (
E(0) => p_17_out,
Q(0) => rd_rst_i(0),
din(127 downto 0) => din(127 downto 0),
dout(127 downto 0) => dout(127 downto 0),
\gc0.count_d1_reg[8]\(8 downto 0) => p_0_out(8 downto 0),
\gic0.gc0.count_d2_reg[8]\(8 downto 0) => p_11_out(8 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => p_5_out,
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.\shd_fifo_reset_blk_ramfifo__parameterized0\
port map (
Q(1) => \^rst\,
Q(0) => wr_rst_i(0),
\gc0.count_reg[1]\(2) => RD_RST,
\gc0.count_reg[1]\(1 downto 0) => rd_rst_i(1 downto 0),
rd_clk => rd_clk,
rst => rst,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_fifo_generator_top is
port (
empty : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
rst : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_fifo_generator_top : entity is "fifo_generator_top";
end shd_fifo_fifo_generator_top;
architecture STRUCTURE of shd_fifo_fifo_generator_top is
begin
\grf.rf\: entity work.shd_fifo_fifo_generator_ramfifo
port map (
din(127 downto 0) => din(127 downto 0),
dout(127 downto 0) => dout(127 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_fifo_generator_v13_0_1_synth is
port (
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
rst : in STD_LOGIC;
wr_en : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_fifo_generator_v13_0_1_synth : entity is "fifo_generator_v13_0_1_synth";
end shd_fifo_fifo_generator_v13_0_1_synth;
architecture STRUCTURE of shd_fifo_fifo_generator_v13_0_1_synth is
begin
\gconvfifo.rf\: entity work.shd_fifo_fifo_generator_top
port map (
din(127 downto 0) => din(127 downto 0),
dout(127 downto 0) => dout(127 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
\reset_gen_ic.rstblk_cc\: entity work.shd_fifo_reset_blk_ramfifo
port map (
m_aclk => m_aclk,
s_aclk => s_aclk,
s_aresetn => s_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo_fifo_generator_v13_0_1 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 8 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 9;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of shd_fifo_fifo_generator_v13_0_1 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 128;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 128;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of shd_fifo_fifo_generator_v13_0_1 : entity is "virtex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of shd_fifo_fifo_generator_v13_0_1 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is 511;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of shd_fifo_fifo_generator_v13_0_1 : entity is 510;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 9;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of shd_fifo_fifo_generator_v13_0_1 : entity is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of shd_fifo_fifo_generator_v13_0_1 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of shd_fifo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 9;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of shd_fifo_fifo_generator_v13_0_1 : entity is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of shd_fifo_fifo_generator_v13_0_1 : entity is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of shd_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of shd_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of shd_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of shd_fifo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of shd_fifo_fifo_generator_v13_0_1 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of shd_fifo_fifo_generator_v13_0_1 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of shd_fifo_fifo_generator_v13_0_1 : entity is "fifo_generator_v13_0_1";
end shd_fifo_fifo_generator_v13_0_1;
architecture STRUCTURE of shd_fifo_fifo_generator_v13_0_1 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.shd_fifo_fifo_generator_v13_0_1_synth
port map (
din(127 downto 0) => din(127 downto 0),
dout(127 downto 0) => dout(127 downto 0),
empty => empty,
full => full,
m_aclk => m_aclk,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity shd_fifo is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 127 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of shd_fifo : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of shd_fifo : entity is "shd_fifo,fifo_generator_v13_0_1,{}";
attribute core_generation_info : string;
attribute core_generation_info of shd_fifo : entity is "shd_fifo,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=9,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=128,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=128,C_ENABLE_RLOCS=0,C_FAMILY=virtex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=511,C_PROG_FULL_THRESH_NEGATE_VAL=510,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=9,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=9,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of shd_fifo : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of shd_fifo : entity is "fifo_generator_v13_0_1,Vivado 2015.4";
end shd_fifo;
architecture STRUCTURE of shd_fifo is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 128;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 128;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "virtex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 511;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 510;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 512;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 9;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 9;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 512;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 9;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.shd_fifo_fifo_generator_v13_0_1
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(8 downto 0) => NLW_U0_data_count_UNCONNECTED(8 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(127 downto 0) => din(127 downto 0),
dout(127 downto 0) => dout(127 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(8 downto 0) => B"000000000",
prog_empty_thresh_assert(8 downto 0) => B"000000000",
prog_empty_thresh_negate(8 downto 0) => B"000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(8 downto 0) => B"000000000",
prog_full_thresh_assert(8 downto 0) => B"000000000",
prog_full_thresh_negate(8 downto 0) => B"000000000",
rd_clk => rd_clk,
rd_data_count(8 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(8 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(8 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(8 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2338.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02338ent IS
END c07s02b07x00p02n02i02338ent;
ARCHITECTURE c07s02b07x00p02n02i02338arch OF c07s02b07x00p02n02i02338ent IS
BEGIN
TESTING: PROCESS
type MEMORY is array(INTEGER range <>) of BIT;
variable MEMORYV : MEMORY( 0 to 31 );
variable INTV : INTEGER;
BEGIN
INTV := MEMORYV ** 2;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02338 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02338arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2338.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02338ent IS
END c07s02b07x00p02n02i02338ent;
ARCHITECTURE c07s02b07x00p02n02i02338arch OF c07s02b07x00p02n02i02338ent IS
BEGIN
TESTING: PROCESS
type MEMORY is array(INTEGER range <>) of BIT;
variable MEMORYV : MEMORY( 0 to 31 );
variable INTV : INTEGER;
BEGIN
INTV := MEMORYV ** 2;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02338 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02338arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2338.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02338ent IS
END c07s02b07x00p02n02i02338ent;
ARCHITECTURE c07s02b07x00p02n02i02338arch OF c07s02b07x00p02n02i02338ent IS
BEGIN
TESTING: PROCESS
type MEMORY is array(INTEGER range <>) of BIT;
variable MEMORYV : MEMORY( 0 to 31 );
variable INTV : INTEGER;
BEGIN
INTV := MEMORYV ** 2;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02338 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02338arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greths_mb
-- File: greths_mb.vhd
-- Authors: Andrea Gianarro
-- Description: Gigabit Ethernet Media Access Controller with Ethernet Debug
-- Communication Link, dual AHB master interfaces and Serial
-- GMII interface
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greths_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
fabtech : integer := 0;
memtech : integer := 0;
transtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
pcs_phyaddr : integer range 0 to 32 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- High-speed Serial Interface
clk_125 : in std_logic;
rst_125 : in std_logic;
eth_rx_p : in std_logic;
eth_rx_n : in std_logic := '0';
eth_tx_p : out std_logic;
eth_tx_n : out std_logic;
-- MDIO interface
reset : out std_logic;
mdio_o : out std_logic;
mdio_oe : out std_logic;
mdio_i : in std_logic;
mdc : out std_logic;
mdint : in std_logic;
-- Control signals
phyrstaddr : in std_logic_vector(4 downto 0);
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_logic;
edcldisable : in std_logic;
debug_pcs_mdio : in std_logic := '0';
-- added for igloo2_serdes
apbin : in apb_in_serdes := apb_in_serdes_none;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes := pad_in_serdes_none;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
rx_aligned : out std_logic
);
end entity;
architecture rtl of greths_mb is
-- GMII and MII signals between MAC and PCS
signal mac_ethi : eth_in_type;
signal pcs_ethi : eth_in_type;
signal mac_etho : eth_out_type;
signal pcs_etho : eth_out_type;
signal int_tx_rstn : std_logic;
signal int_rx_rstn : std_logic;
-- MDIO signals
signal mdio_o_pcs : std_logic;
signal mdio_oe_pcs : std_logic;
signal mdio_i_pcs : std_logic;
begin
-------------------------------------------------------------------------------
-- Ethernet MAC
-------------------------------------------------------------------------------
u0 : grethm_mb
generic map (
hindex => hindex,
ehindex => ehindex,
pindex => pindex,
paddr => paddr,
pmask => pmask,
pirq => pirq,
memtech => memtech,
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
sim => sim,
giga => giga,
oepol => oepol,
scanen => scanen,
ft => ft,
edclft => edclft,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahb => edclsepahbg,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => 1
)
port map (
rst => rst,
clk => clk,
ahbmi => ahbmi,
ahbmo => ahbmo,
ahbmi2 => ahbmi2,
ahbmo2 => ahbmo2,
apbi => apbi,
apbo => apbo,
ethi => mac_ethi,
etho => mac_etho
);
-------------------------------------------------------------------------------
-- 1000baseX-compliant SGMII bridge
-------------------------------------------------------------------------------
sgmii0: sgmii
generic map (
fabtech => fabtech,
memtech => memtech,
transtech => transtech,
phy_addr => pcs_phyaddr
)
port map(
clk_125 => clk_125,
rst_125 => rst_125,
ser_rx_p => eth_rx_p,
ser_rx_n => eth_rx_n,
ser_tx_p => eth_tx_p,
ser_tx_n => eth_tx_n,
txd => pcs_etho.txd,
tx_en => pcs_etho.tx_en,
tx_er => pcs_etho.tx_er,
tx_clk => pcs_ethi.gtx_clk,
tx_rstn => int_tx_rstn,
rxd => pcs_ethi.rxd,
rx_dv => pcs_ethi.rx_dv,
rx_er => pcs_ethi.rx_er,
rx_col => pcs_ethi.rx_col,
rx_crs => pcs_ethi.rx_crs,
rx_clk => pcs_ethi.rx_clk,
rx_rstn => int_rx_rstn,
-- optional MDIO interface to PCS
mdc => pcs_etho.mdc,
mdio_o => mdio_o_pcs,
mdio_oe => mdio_oe_pcs,
mdio_i => mdio_i_pcs,
-- added for igloo2_serdes
apbin => apbin,
apbout => apbout,
m2gl_padin => m2gl_padin,
m2gl_padout => m2gl_padout,
serdes_clk125 => serdes_clk125,
rx_aligned => rx_aligned
);
-- 10/100 Mbit GMII to MII adapter
adapt_10_100_0 : gmii_to_mii
port map (
tx_rstn => int_tx_rstn,
rx_rstn => int_rx_rstn,
gmiii => mac_ethi, -- OUT
gmiio => mac_etho, -- IN
miii => pcs_ethi, -- IN
miio => pcs_etho -- OUT
);
-- Drive MDIO signals (including PCS bypass to MAC)
reset <= pcs_etho.reset;
mdc <= pcs_etho.mdc;
mdio_oe <= '1' when debug_pcs_mdio = '1' else pcs_etho.mdio_oe;
mdio_o <= '0' when debug_pcs_mdio = '1' else pcs_etho.mdio_o;
mdio_oe_pcs <= pcs_etho.mdio_oe when debug_pcs_mdio = '1' else '1';
mdio_o_pcs <= pcs_etho.mdio_o when debug_pcs_mdio = '1' else '0';
pcs_ethi.mdint <= mdint;
pcs_ethi.mdio_i <= mdio_i_pcs when debug_pcs_mdio = '1' else mdio_i;
-- MAC input signals integration
pcs_ethi.tx_clk <= pcs_ethi.gtx_clk;
pcs_ethi.phyrstaddr <= phyrstaddr;
pcs_ethi.edcladdr <= edcladdr;
pcs_ethi.edclsepahb <= edclsepahb;
pcs_ethi.edcldisable <= edcldisable;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity MulticycleCPU is
port(
clk: in std_logic;
CarryOut, Overflow: out std_logic
);
end MulticycleCPU;
architecture Behavioral of MulticycleCPU is
component PCMulticycle is
port(
clk, d: in std_logic;
AddressIn: in std_logic_vector(31 downto 0);
AddressOut: out std_logic_vector(31 downto 0)
);
end component;
component Add
port(
x: in std_logic_vector(31 downto 0);
y: in std_logic_vector(31 downto 0);
z: out std_logic_vector(31 downto 0)
);
end component;
component SignExtend
port(
x: in std_logic_vector(15 downto 0);
y: out std_logic_vector(31 downto 0)
);
end component;
component ShiftLeft2
port(
x: in std_logic_vector(31 downto 0);
y: out std_logic_vector(31 downto 0)
);
end component;
component ShiftLeft2Jump
port(
x: in std_logic_vector(25 downto 0);
y: in std_logic_vector(3 downto 0);
z: out std_logic_vector(31 downto 0)
);
end component;
component Mux5
port(
x, y: in std_logic_vector (4 downto 0);
sel: in std_logic;
z :out std_logic_vector(4 downto 0)
);
end component;
component Mux32
port(
x, y: in std_logic_vector (31 downto 0);
sel: in std_logic;
z: out std_logic_vector(31 downto 0)
);
end component;
component And2
port(
a, b: in std_logic;
y: out std_logic
);
end component;
component Or2 is
port(
a, b: in std_logic;
y: out std_logic
);
end component;
component ALU
generic(
n: natural := 32
);
port(
a, b: in std_logic_vector(n-1 downto 0);
Oper: in std_logic_vector(3 downto 0);
Result: buffer std_logic_vector(n-1 downto 0);
Zero, CarryOut, Overflow: buffer std_logic
);
end component;
component IR is
port (
x: in std_logic_vector(31 downto 0);
clk, IRWrite: in std_logic;
y: out std_logic_vector(31 downto 0)
);
end component;
component RegistersMulticycle is
port(
RR1, RR2, WR: in std_logic_vector(4 downto 0);
WD: in std_logic_vector(31 downto 0);
RegWrite: in std_logic;
RD1, RD2: out std_logic_vector(31 downto 0)
);
end component;
component RegA is
port(
x: in std_logic_vector(31 downto 0);
clk: in std_logic;
y: out std_logic_vector(31 downto 0)
);
end component;
component RegB is
port(
x: in std_logic_vector(31 downto 0);
clk: in std_logic;
y: out std_logic_vector(31 downto 0)
);
end component;
component InstructionMemory
port (
Address: in std_logic_vector(31 downto 0);
ReadData: out std_logic_vector(31 downto 0)
);
end component;
component MDR is
port (
x: in std_logic_vector(31 downto 0);
clk: in std_logic;
y: out std_logic_vector(31 downto 0)
);
end component;
component DataMemoryMulticycle is
port(
WriteData: in std_logic_vector(31 downto 0);
Address: in std_logic_vector(31 downto 0);
MemRead, MemWrite: in std_logic;
ReadData: out std_logic_vector(31 downto 0)
);
end component;
component ALUControl
port(
ALUOp: in std_logic_vector(1 downto 0);
Funct: in std_logic_vector(5 downto 0);
Operation: out std_logic_vector(3 downto 0)
);
end component;
component MUX3Way is
port(
w, x, y: in std_logic_vector(31 downto 0);
sel: in std_logic_vector(1 downto 0);
z:out std_logic_vector(31 downto 0)
);
end component;
component MUX4Way is
port(
v, w, x, y: in std_logic_vector(31 downto 0);
sel: in std_logic_vector(1 downto 0);
z:out std_logic_vector(31 downto 0)
);
end component;
component MulticycleControl is
port(
Opcode: in std_logic_vector(5 downto 0);
clk: in std_logic;
RegDst, RegWrite, ALUSrcA, IRWrite, MemtoReg, MemWrite, MemRead, IorD, PCWrite, PCWriteCond: out std_logic;
ALUSrcB, ALUOp, PCSource: out std_logic_vector(1 downto 0)
);
end component;
signal D, PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, ALUSrcA, RegWrite, RegDst, Zero, W: std_logic := '0';
signal ALUOp, ALUSrcB, PCSource: std_logic_vector(1 downto 0) := "00";
signal Operation: std_logic_vector(3 downto 0) := "0000";
signal K: std_logic_vector(4 downto 0) := "00000";
signal C, E, F, G, H, I, J, L, M, N, P, Q, R, S, T, U, V, Instruction: std_logic_vector(31 downto 0) := X"00000000";
begin
PC_instance: PCMulticycle port map(clk, D, C, E);
Mux32_instance_0: Mux32 port map(E, F, IorD, G);
DataMemory_instance: DataMemoryMulticycle port map(H, G, MemRead, MemWrite, I);
IR_instance: IR port map(I, clk, IRWrite, Instruction);
Mux5_instance: Mux5 port map(Instruction(20 downto 16), Instruction(15 downto 11), RegDst, K);
MDR_instance: MDR port map(I, clk, J);
Mux32_instance_1: Mux32 port map(F, J, MemtoReg, L);
Registers_instance: RegistersMulticycle port map(Instruction(25 downto 21), Instruction(20 downto 16), K, L, RegWrite, M, N);
RegA_instance: RegA port map(M, clk, P);
RegA_instance_2: RegA port map(N, clk, H);
SignExtend_instance: SignExtend port map(Instruction(15 downto 0), Q);
ShiftLeft2_instance: ShiftLeft2 port map(Q, R);
MUX4Way_instance: MUX4Way port map(H, X"00000004", Q, R, ALUSrcB, T);
Mux32_instance_2: Mux32 port map(E, P, ALUSrcA, S);
ShiftLeft2Jump_instance: ShiftLeft2Jump port map(Instruction(25 downto 0), E(31 downto 28), V);
MUX3Way_instance: MUX3Way port map(U, F, V, PCSource, C);
And2_instance: And2 port map(Zero, PCWriteCond, W);
Or2_instance: Or2 port map(W, PCWrite, D);
ALU_instance: ALU port map(S, T, Operation, U, Zero, Carryout, Overflow);
ALUControl_instance: ALUControl port map(ALUOp, Instruction(5 downto 0), Operation);
ALUOut: RegB port map(U, clk, F);
Control_instance: MulticycleControl port map(Instruction(31 downto 26), clk, RegDst, RegWrite, ALUSrcA, IRWrite, MemtoReg, MemWrite, MemRead, IorD, PCWrite, PCWriteCond, ALUSrcB, ALUOp, PCSource);
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity aclkout is
port(
clk : in std_logic;
ddr_clk : out std_logic;
ddr_clkn: out std_logic
);
end;
architecture rtl of aclkout is
component stratixiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
clkhi : in std_logic := '0';
clklo : in std_logic := '0';
muxsel : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic --;
-- dfflo : out std_logic;
-- dffhi : out std_logic_vector(1 downto 0) -- changed in quartus 9.0
-- dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component stratixiii_pseudo_diff_out is
generic (
lpm_type : string := "stratixiii_pseudo_diff_out"
);
port (
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic
);
end component;
component stratixiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
port(
dynamicterminationcontrol : in std_logic := '0';
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic;
oe : in std_logic := '1'--;
--parallelterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0');
--seriesterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal clk_reg : std_logic;
signal clk_buf, clk_bufn : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
out_reg0 : stratixiii_ddio_out
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
half_rate_mode => "false",
use_new_clocking_model => "true",
lpm_type => "stratixiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => vcc,
clk => clk,
clkhi => clk,
clklo => clk,
muxsel => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => clk_reg
-- dfflo => open --,
-- dffhi => open--,
--devclrn => vcc,
--devpor => vcc
);
pseudo_diff0 : stratixiii_pseudo_diff_out
port map(
i => clk_reg,
o => clk_buf,
obar => clk_bufn
);
out_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => clk_buf,
oe => vcc,
dynamicterminationcontrol => gnd(0),
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => ddr_clk,
obar => open
);
out_bufn0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => clk_bufn,
oe => vcc,
dynamicterminationcontrol => gnd(0),
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => ddr_clkn,
obar => open
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity aclkout is
port(
clk : in std_logic;
ddr_clk : out std_logic;
ddr_clkn: out std_logic
);
end;
architecture rtl of aclkout is
component stratixiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
clkhi : in std_logic := '0';
clklo : in std_logic := '0';
muxsel : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic --;
-- dfflo : out std_logic;
-- dffhi : out std_logic_vector(1 downto 0) -- changed in quartus 9.0
-- dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component stratixiii_pseudo_diff_out is
generic (
lpm_type : string := "stratixiii_pseudo_diff_out"
);
port (
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic
);
end component;
component stratixiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
port(
dynamicterminationcontrol : in std_logic := '0';
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic;
oe : in std_logic := '1'--;
--parallelterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0');
--seriesterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal clk_reg : std_logic;
signal clk_buf, clk_bufn : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
out_reg0 : stratixiii_ddio_out
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
half_rate_mode => "false",
use_new_clocking_model => "true",
lpm_type => "stratixiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => vcc,
clk => clk,
clkhi => clk,
clklo => clk,
muxsel => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => clk_reg
-- dfflo => open --,
-- dffhi => open--,
--devclrn => vcc,
--devpor => vcc
);
pseudo_diff0 : stratixiii_pseudo_diff_out
port map(
i => clk_reg,
o => clk_buf,
obar => clk_bufn
);
out_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => clk_buf,
oe => vcc,
dynamicterminationcontrol => gnd(0),
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => ddr_clk,
obar => open
);
out_bufn0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => clk_bufn,
oe => vcc,
dynamicterminationcontrol => gnd(0),
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => ddr_clkn,
obar => open
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity aclkout is
port(
clk : in std_logic;
ddr_clk : out std_logic;
ddr_clkn: out std_logic
);
end;
architecture rtl of aclkout is
component stratixiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
clkhi : in std_logic := '0';
clklo : in std_logic := '0';
muxsel : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic --;
-- dfflo : out std_logic;
-- dffhi : out std_logic_vector(1 downto 0) -- changed in quartus 9.0
-- dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component stratixiii_pseudo_diff_out is
generic (
lpm_type : string := "stratixiii_pseudo_diff_out"
);
port (
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic
);
end component;
component stratixiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
port(
dynamicterminationcontrol : in std_logic := '0';
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic;
oe : in std_logic := '1'--;
--parallelterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0');
--seriesterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal clk_reg : std_logic;
signal clk_buf, clk_bufn : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
out_reg0 : stratixiii_ddio_out
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
half_rate_mode => "false",
use_new_clocking_model => "true",
lpm_type => "stratixiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => vcc,
clk => clk,
clkhi => clk,
clklo => clk,
muxsel => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => clk_reg
-- dfflo => open --,
-- dffhi => open--,
--devclrn => vcc,
--devpor => vcc
);
pseudo_diff0 : stratixiii_pseudo_diff_out
port map(
i => clk_reg,
o => clk_buf,
obar => clk_bufn
);
out_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => clk_buf,
oe => vcc,
dynamicterminationcontrol => gnd(0),
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => ddr_clk,
obar => open
);
out_bufn0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => clk_bufn,
oe => vcc,
dynamicterminationcontrol => gnd(0),
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => ddr_clkn,
obar => open
);
end;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_APB3_PPE_IF is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
TDM_CNT : in vl_logic_vector(2 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PADDR : in vl_logic_vector(11 downto 0);
PWDATA : in vl_logic_vector(31 downto 0);
PRDATA : out vl_logic_vector(15 downto 0);
PREADY : out vl_logic;
PSLVERR : out vl_logic;
PPE_PSEL : in vl_logic;
PPE_PENABLE : in vl_logic;
PPE_PWRITE : in vl_logic;
PPE_PADDR : in vl_logic_vector(11 downto 0);
PPE_PWDATA : in vl_logic_vector(15 downto 0);
PPE_PRDATA : out vl_logic_vector(15 downto 0);
PPE_PREADY : out vl_logic;
PPE_PSLVERR : out vl_logic;
SSE_RWB : out vl_logic;
SSE_ADDR : out vl_logic_vector(9 downto 0);
SSE_WDATA : out vl_logic_vector(15 downto 0);
SSE_RDATA : in vl_logic_vector(15 downto 0);
PDMA_decode : out vl_logic
);
end F2DSS_SSE_APB3_PPE_IF;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_APB3_PPE_IF is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
TDM_CNT : in vl_logic_vector(2 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PADDR : in vl_logic_vector(11 downto 0);
PWDATA : in vl_logic_vector(31 downto 0);
PRDATA : out vl_logic_vector(15 downto 0);
PREADY : out vl_logic;
PSLVERR : out vl_logic;
PPE_PSEL : in vl_logic;
PPE_PENABLE : in vl_logic;
PPE_PWRITE : in vl_logic;
PPE_PADDR : in vl_logic_vector(11 downto 0);
PPE_PWDATA : in vl_logic_vector(15 downto 0);
PPE_PRDATA : out vl_logic_vector(15 downto 0);
PPE_PREADY : out vl_logic;
PPE_PSLVERR : out vl_logic;
SSE_RWB : out vl_logic;
SSE_ADDR : out vl_logic_vector(9 downto 0);
SSE_WDATA : out vl_logic_vector(15 downto 0);
SSE_RDATA : in vl_logic_vector(15 downto 0);
PDMA_decode : out vl_logic
);
end F2DSS_SSE_APB3_PPE_IF;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_SSE_APB3_PPE_IF is
port(
PRESETN : in vl_logic;
PCLK : in vl_logic;
TDM_CNT : in vl_logic_vector(2 downto 0);
PSEL : in vl_logic;
PENABLE : in vl_logic;
PWRITE : in vl_logic;
PADDR : in vl_logic_vector(11 downto 0);
PWDATA : in vl_logic_vector(31 downto 0);
PRDATA : out vl_logic_vector(15 downto 0);
PREADY : out vl_logic;
PSLVERR : out vl_logic;
PPE_PSEL : in vl_logic;
PPE_PENABLE : in vl_logic;
PPE_PWRITE : in vl_logic;
PPE_PADDR : in vl_logic_vector(11 downto 0);
PPE_PWDATA : in vl_logic_vector(15 downto 0);
PPE_PRDATA : out vl_logic_vector(15 downto 0);
PPE_PREADY : out vl_logic;
PPE_PSLVERR : out vl_logic;
SSE_RWB : out vl_logic;
SSE_ADDR : out vl_logic_vector(9 downto 0);
SSE_WDATA : out vl_logic_vector(15 downto 0);
SSE_RDATA : in vl_logic_vector(15 downto 0);
PDMA_decode : out vl_logic
);
end F2DSS_SSE_APB3_PPE_IF;
|
entity bot is
generic ( N : integer );
end entity;
architecture test of bot is
constant k : integer := N;
signal x, y : natural;
begin
p1: process (y) is
begin
x <= y + 5;
end process;
p2: process is
begin
assert << constant ^.^.g(N).uut.k : integer >> = N;
<< signal ^.^.g(N).uut.x : integer >> <= force 1;
wait for 1 ns;
assert << signal ^.^.g(N).uut.x : integer >> = 1;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity ename4 is
end entity;
architecture test of ename4 is
begin
g: for i in 1 to 3 generate
uut: entity work.bot generic map (N => i);
end generate;
end architecture;
|
-- ApsCmdConstants.vhd
--
-- This provides menmonic definitions for the command word fields
--
--
-- REVISIONS
--
-- 7/9/2013 CRJ
-- Created
--
-- 8/13/2013 CRJ
-- Initial release
--
-- END REVISIONS
--
library ieee;
use ieee.std_logic_1164.all;
package ApsCmdConstants is
-- Constants used in the command packets from the host
-- Command Word Format:
--
-- D<31> ACK Flag
-- D<30> SEQ Error Flag
-- D<29> Channel select 0/1
-- D<28> R/!W
-- D<27:24> CMD<3:0>, Command
-- D<23:16> MODE from host (command mode) / STAT from APS (command completion status)
-- D<15:0> CNT<15:0>, 32-bit read or write count. For writes, CNT data words follow the address
-- Define the bit fields in the command word
constant APS_ACK_BIT : natural := 31;
constant APS_SEQ_BIT : natural := 30;
constant APS_CHAN_BIT : natural := 29;
constant APS_RW_BIT : natural := 28;
constant APS_NOACK_BIT : natural := 27;
-- Define the bit ranges in the command word
subtype APS_CMD_RANGE is natural range 26 downto 24;
subtype APS_MODE_RANGE is natural range 23 downto 16;
subtype APS_STAT_RANGE is natural range 23 downto 16;
subtype APS_CNT_RANGE is natural range 15 downto 0;
-- Define the bit ranges in the User CIF
subtype CIF_CNT_RANGE is natural range 15 downto 0;
subtype CIF_MODE_RANGE is natural range 23 downto 16;
subtype CIF_ADDR_RANGE is natural range 56 downto 25;
constant CIF_RW_BIT : natural := 24;
-- Define the bit ranges in the User COF
subtype COF_CNT_RANGE is natural range 15 downto 0;
subtype COF_STAT_RANGE is natural range 23 downto 16;
-- Define the command values
constant APS_PKT_RESET : std_logic_vector(2 downto 0) := "000";
constant APS_PKT_USRIO : std_logic_vector(2 downto 0) := "001";
constant APS_PKT_EPIO : std_logic_vector(2 downto 0) := "010";
constant APS_PKT_CFGIO : std_logic_vector(2 downto 0) := "011";
constant APS_PKT_CFGRUN : std_logic_vector(2 downto 0) := "100";
constant APS_PKT_CFGDAT : std_logic_vector(2 downto 0) := "101";
constant APS_PKT_CFGCTL : std_logic_vector(2 downto 0) := "110";
constant APS_PKT_STAT : std_logic_vector(2 downto 0) := "111";
end package ApsCmdConstants;
|
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|
-- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- This file provides a template for integrating the window generator into
-- a datapath. Note that this is not a functional example and is instead
-- used solely for explaining how to interface an input source with the
-- generator, and how to handle outputs from the generator.
--
-- The code has various TODO markers that should be updated when using a
-- specific application.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.math_custom.all;
use work.window_gen_pkg.all;
entity template is
generic (
IN_RAM_WORDS : positive;
OUT_RAM_WORDS : positive;
IN_DATA_WIDTH : positive;
OUT_DATA_WIDTH : positive;
MAX_WINDOW_ROWS : positive;
MAX_WINDOW_COLS : positive;
MAX_IMAGE_ROWS : positive;
MAX_IMAGE_COLS : positive;
NUM_PIPELINES : positive);
port (
clk : in std_logic;
rst : in std_logic;
go : in std_logic;
window_rows : in std_logic_vector(bitsNeeded(MAX_WINDOW_ROWS)-1 downto 0);
window_cols : in std_logic_vector(bitsNeeded(MAX_WINDOW_COLS)-1 downto 0);
image_cols : in std_logic_vector(bitsNeeded(MAX_IMAGE_COLS)-1 downto 0);
image_rows : in std_logic_vector(bitsNeeded(MAX_IMAGE_ROWS)-1 downto 0)
-- TODO: add application specific I/O
);
end template;
architecture default of template is
constant WINDOW_BITS : positive := MAX_WINDOW_ROWS*MAX_WINDOW_COLS*IN_DATA_WIDTH;
-- 2D array representing a window
type window_t is array(0 to MAX_WINDOW_ROWS-1, 0 to MAX_WINDOW_COLS-1) of std_logic_vector(IN_DATA_WIDTH-1 downto 0);
-- 1D array of 2D windows
type window_array_t is array (0 to NUM_PIPELINES-1) of window_t;
-- a huge vectorized version of all NUM_PIPELINE windows
signal wg_out : std_logic_vector(MAX_WINDOW_ROWS*(MAX_WINDOW_COLS+NUM_PIPELINES-1)*IN_DATA_WIDTH-1 downto 0);
-- all of the windows in 2D format
signal windows : window_array_t;
signal window_valid : std_logic_vector(NUM_PIPELINES-1 downto 0);
signal wg_done : std_logic;
signal wg_empty : std_logic;
signal wg_ready : std_logic;
signal read_windows : std_logic;
signal input_valid : std_logic;
signal pipe_valid_in : std_logic_vector(NUM_PIPELINES-1 downto 0);
signal in_ram_wen : std_logic;
signal in_ram_waddr : std_logic_vector(bitsNeeded(IN_RAM_WORDS)-1 downto 0);
signal in_ram_wdata : std_logic_vector(IN_DATA_WIDTH-1 downto 0);
signal in_ram_raddr : std_logic_vector(bitsNeeded(IN_RAM_WORDS)-1 downto 0);
signal in_ram_rdata : std_logic_vector(IN_DATA_WIDTH-1 downto 0);
signal out_ram_wen : std_logic;
signal out_ram_waddr : std_logic_vector(bitsNeeded(OUT_RAM_WORDS)-1 downto 0);
signal out_ram_wdata : std_logic_vector(OUT_DATA_WIDTH-1 downto 0);
signal out_ram_raddr : std_logic_vector(bitsNeeded(OUT_RAM_WORDS)-1 downto 0);
signal out_ram_rdata : std_logic_vector(OUT_DATA_WIDTH-1 downto 0);
type state_t is (WAIT_FOR_GO, GENERATE_ADDRESS);
signal state : state_t;
-----------------------------------------------------------------------
-- Procedure devectorizeWindow
-- Description: convert a 1D vectorized representation of an output window
-- into a corresponding 2D array for easier processing. Note
-- that this always determines a window of size
-- MAX_WINDOW_ROWS X MAX_WINDOW_COLS. For smaller windows,
-- just ignore the extra rows and columns.
--
-- Parameters:
-- vector : The 1D-vectorized version of the 2D array, stored in row-major
-- order. Index (0,0) starts at the MSB in the vector, with the
-- LSB storing the end of index (total_rows-1, total_cols-1)
-- window : the window as a 2D array (t_window)
-- index : In case multiple windows are specified in the output, index
-- specifies which one to get
--
-- Preconditions: index < PARALLEL_IO, vector must be the
-- appropriate size with data stored as described above.
-----------------------------------------------------------------------
procedure devectorizeWindow(signal vector : std_logic_vector;
window : out window_t;
index : natural) is
begin
for i in 0 to MAX_WINDOW_ROWS-1 loop
for j in index to MAX_WINDOW_COLS+index-1 loop
window(i, j-index) := getVectorElement(vector, i, j, MAX_WINDOW_ROWS, MAX_WINDOW_COLS+NUM_PIPELINES-1, IN_DATA_WIDTH);
end loop;
end loop;
end devectorizeWindow;
begin -- STR
-------------------------------------------------------------------------
-- Input Source
-- Notes: Inputs can be provided to the sliding-window generator from
-- potentially any source. In this example, we instantiate a block RAM with
-- a word width equivalent to the number of replicated pipelines we would
-- like to use. For example, if NUM_PIPELINES is 4, this RAM can provide 4
-- inputs to the window generator every cycle, which will later output up
-- to 4 windows per cycle.
--
-- If using an external RAM as the input source, this RAM would likely be
-- replaced with a FIFO that has a read port width of the same size as this
-- RAM word width. In most cases, that FIFO will have a write port width
-- equivalent to the width of the external memory's data bus. For example,
-- if reading from a memory with a 128-bit data bus into a window generator
-- that reads 64 bits per cycle, you would use a FIFO with a 128-bit write
-- port and 64-bit read port.
--
-- A third possibility for the input source is to connect the window
-- generator directly to the output of another entity. e.g. a chain
-- of filters, where each filter uses a sliding-window generator followed
-- by a pipeline that provides input to the next window generator.
-------------------------------------------------------------------------
U_INPUT_RAM : entity work.RAM(SYNC_READ)
generic map(
num_words => IN_RAM_WORDS,
word_width => IN_DATA_WIDTH*NUM_PIPELINES,
addr_width => bitsNeeded(IN_RAM_WORDS))
port map (
clk => clk,
wen => in_ram_wen,
waddr => in_ram_waddr,
wdata => in_ram_wdata,
raddr => in_ram_raddr,
rdata => in_ram_rdata);
-- example addressing logic for the input RAM
-- The exact logic depends on the type input source, the timing of the
-- input source, etc. This example is simply meant to illustrate the
-- basic concept for generating an input stream for the for the window
-- generator.
process(clk, rst)
begin
if (rst = '1') then
in_ram_raddr <= (others => '0');
input_valid <= '0';
state <= WAIT_FOR_GO;
elsif (rising_edge(clk)) then
case state is
when WAIT_FOR_GO =>
in_ram_raddr <= (others => '0');
input_valid <= '0';
if (go = '1') then
state <= GENERATE_ADDRESS;
end if;
when GENERATE_ADDRESS =>
if (wg_ready = '1') then
in_ram_raddr <= std_logic_vector(unsigned(in_ram_raddr) + 1);
-- TODO: Update timing depending on latency of input source
input_valid <= '1';
end if;
-- TODO: Add completion logic
when others => null;
end case;
end if;
end process;
-------------------------------------------------------------------------
-- Sliding-window generator
-------------------------------------------------------------------------
U_WINDOW_GEN : entity work.window_gen
generic map (
PARALLEL_IO => NUM_PIPELINES,
MAX_WINDOW_ROWS => MAX_WINDOW_ROWS,
MAX_WINDOW_COLS => MAX_WINDOW_COLS,
MAX_IMAGE_ROWS => MAX_IMAGE_ROWS,
MAX_IMAGE_COLS => MAX_IMAGE_COLS,
INPUT0_AT_MSB => false, -- RAM likely stores first input at LSB
DATA_WIDTH => IN_DATA_WIDTH)
port map (
clk => clk,
rst => rst,
go => go,
ready => wg_ready,
read_enable => read_windows,
empty => wg_empty,
image_rows => image_rows,
image_cols => image_cols,
window_rows => window_rows,
window_cols => window_cols,
input => in_ram_rdata, -- input from RAM
input_valid => input_valid, -- TODO: Make sure this logic is timed
-- appropriately.
output => wg_out,
window_valid => window_valid,
done => wg_done
);
-- The output of the window buffer is a huge std_logic_vector that
-- represents all NUM_PIPELINES windows. This code converts the huge vector
-- into an 2D array representation that is easier to work with.
--
-- This would be made much easier by VHDL 2008, where the generator could
-- output this array itself. Once 2008 is more widely supported, we plan to
-- add a 2008 wrapper around the window generator to provide a more
-- convenient interface.
process(wg_out)
variable temp_window : window_t;
begin
for i in 0 to NUM_PIPELINES-1 loop
devectorizeWindow(wg_out, temp_window, i);
windows(i) <= temp_window;
end loop;
end process;
-- read/remove the current windows when the generator isn't empty
-- TODO: add pipeline enable here if necessary (e.g. likely shouldn't read
-- if the pipeline is stalled)
read_windows <= not wg_empty;
-------------------------------------------------------------------------
-- Replicated Pipelines
-- TODO: Add sliding-window function here for each window.
-------------------------------------------------------------------------
U_PIPELINES : for i in 0 to NUM_PIPELINES-1 generate
-- determine the validity of each pipeline input (i.e. window)
-- TODO: add pipeline enable here if necessary (e.g., if the window
-- wasn't read from the generator, you might not want to tell the
-- pipeline the input is valid)
pipe_valid_in(i) <= window_valid(i);
-- TODO: INSTANTIATE SLIDING-WINDOW FUNCTION PIPELINES
-- FOR EACH WIDOW window(i)
end generate;
-------------------------------------------------------------------------
-- Output
-- Notes: Like the input source, the output can potentially be any circuit
-- that can accept a stream of pipeline outputs.
--
-- One additional challenge for storing outputs is that there are cases
-- where the window generator will output less than NUM_PIPELINES windows,
-- in which case some of the pipeline outputs will be invalid while others
-- are valid.
--
-- To deal with this situation, we recommend several possibilities. One
-- simple solution if storing to memory is to also store the invalid
-- outputs and then use softwareto filter out the invalid outputs.
-- A second option is to use a FIFO-like entity that can accept a
-- variable number of inputs (i.e. pipeline outputs) every cycle.
-- In this case, the FIFO will only store the valid outputs,
-- which filters out the invalid outputs. If connecting the pipeline
-- outputs to another downstream entity, it may also be convenient to
-- filter out the invalid outputs there.
-------------------------------------------------------------------------
U_OUTPUT_RAM : entity work.RAM(SYNC_READ)
generic map(
num_words => OUT_RAM_WORDS,
word_width => OUT_DATA_WIDTH,
addr_width => bitsNeeded(OUT_RAM_WORDS))
port map (
clk => clk,
wen => out_ram_wen,
waddr => out_ram_waddr,
wdata => out_ram_wdata,
raddr => out_ram_raddr,
rdata => out_ram_rdata);
end default;
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- globals for projects using my modules
package globals is
constant FPGA_CLK_FREQ : integer := 100000000; -- 100 MHz
subtype byte_t is std_logic_vector(7 downto 0);
-- register interface
constant REG_ADDR_W : integer := 5;
subtype reg_addr_t is std_logic_vector(REG_ADDR_W - 1 downto 0);
constant reg_addr_invl : std_logic_vector(REG_ADDR_W - 1 downto 0) := ( others => '1' );
type reg_bus_t is record
wr : std_logic;
data : byte_t;
addr : reg_addr_t;
end record reg_bus_t;
end globals;
package body globals is
end globals;
|
library verilog;
use verilog.vl_types.all;
entity MUX4_1_IControl is
port(
Sel : in vl_logic_vector(1 downto 0);
S0 : in vl_logic_vector(31 downto 0);
S1 : in vl_logic_vector(31 downto 0);
S2 : in vl_logic_vector(31 downto 0);
S3 : in vl_logic_vector(31 downto 0);
\out\ : out vl_logic_vector(31 downto 0)
);
end MUX4_1_IControl;
|
--------------------------------------------------------------------------------------
-- The configuration settings choose by the user are read here. If a modification is
-- detected, a configuration is started with the new values.
-- This bloc generates the triggers to acquire data at the sample rate define by user.
--------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.mpu_pkg.all;
entity mpu_acqui is
port (
clk_proc : in std_logic;
reset : in std_logic;
sda : inout std_logic;
scl : inout std_logic;
AD0 : out std_logic;
parameters : in param;
accelero : out flow;
gyroscope : out flow;
compass : out flow
);
end mpu_acqui;
architecture RTL of mpu_acqui is
signal en : std_logic;
signal spl_rate : std_logic_vector(7 downto 0);
signal gyro_config : std_logic_vector(1 downto 0);
signal accel_config : std_logic_vector(1 downto 0);
signal gain_compass : std_logic_vector(2 downto 0);
signal freq_compass : std_logic_vector(2 downto 0);
signal trigger : std_logic;
signal config_button : std_logic;
signal wr_en : std_logic;
signal rd_en : std_logic;
signal rd_en_dl : std_logic;
signal data_fifo_in : std_logic_vector(7 downto 0);
signal count_fifo : std_logic_vector(5 downto 0);
signal wr_en_dl : std_logic;
signal wr_en_flag : std_logic;
signal reset_fifo_buffer: std_logic;
signal trigger_auto : std_logic;
signal config_change : std_logic;
signal en_dl : std_logic;
signal spl_rate_dl : std_logic_vector(7 downto 0);
signal gyro_config_dl : std_logic_vector(1 downto 0);
signal accel_config_dl : std_logic_vector(1 downto 0);
signal gain_compass_dl : std_logic_vector(2 downto 0);
signal freq_compass_dl : std_logic_vector(2 downto 0);
signal run_conf : std_logic;
signal not_reset : std_logic;
signal data_fifo_out : std_logic_vector(7 downto 0);
signal rd_accel,rd_gyro : std_logic;
signal rd_comp : std_logic;
signal count_rst_fifo : unsigned(3 downto 0);
signal count_param : integer range 0 TO 30_000_000;
signal spl_ratex2 : unsigned(8 downto 0);
signal COUNT_ONE_ACQUI : INTEGER RANGE 0 TO 30_000_000;
signal spl_rate_mpu : std_logic_vector(7 downto 0);
signal rd_fifo_count : std_logic;
signal rd_comp_dl : std_logic;
signal ready : std_logic;
signal rd_ready_f : std_logic;
signal fifo_mpu_count : std_logic_vector(15 downto 0);
signal fifo_mpu_res : unsigned(15 downto 0);
signal data_read : std_logic_vector(7 downto 0);
signal wr_en_fifo : std_logic;
begin
mpu_i2c_inst : entity work.mpu_i2c(behavioral) port map (
clk => clk_proc,
en => en,
reset_n => reset,
config_button => config_button,
trigger => trigger,
data_read => data_read,
fifo_wr_en => wr_en,
spl_rate => spl_rate_mpu,
gyro_config => gyro_config,
accel_config => accel_config,
gain_compass => gain_compass,
freq_compass => freq_compass,
reset_fifo_buffer => reset_fifo_buffer,
run_conf => run_conf,
rd_fifo_count => rd_fifo_count,
sda => sda,
scl => scl
);
mpu_fifo_inst_1 : entity work.mpu_fifo(syn) port map (
aclr => not_reset,
data => data_fifo_in,
rdclk => clk_proc,
rdreq => rd_en,
wrclk => clk_proc,
wrreq => wr_en_fifo,
q => data_fifo_out,
rdempty => open,
rdusedw => count_fifo,
wrfull => open
);
mpu_off_inst : entity work.offset_correction(RTL) port map (
clk => clk_proc,
reset => reset,
enable => en,
rd_fifo_count => rd_fifo_count,
parameters => parameters,
wr_en_flag => wr_en_flag,
wr_fifo => wr_en_fifo,
data_i => data_read,
data_o => data_fifo_in
);
------ Generates triggers in order to read data from mpu. Check the mpu internal FIFO count bytes between each trigger
process(clk_proc,reset)
begin
if reset='0' then
trigger_auto <= '0';
reset_fifo_buffer <= '0';
count_param <= 0;
count_rst_fifo <= x"0";
rd_fifo_count <= '0';
elsif clk_proc'event and clk_proc='1' then ----- Generates triggers for reading data from mpu
if en='1' then
if spl_rate <= x"0F" then
spl_rate_mpu <= x"84"; --60.15hz
elsif spl_rate <= x"1E" then
spl_rate_mpu <= x"57"; --90.9hz
elsif spl_rate <= x"3C" then
spl_rate_mpu <= x"34"; --150.9hz
else
spl_rate_mpu <= x"19";
end if;
if run_conf='0' then
count_param <= count_param + 1;
if count_param < COUNT_ONE_ACQUI-TRIGGER_OR_RST_FIFO_T then
rd_fifo_count <= '0';
if count_rst_fifo = x"1" then
trigger_auto <= '1';
reset_fifo_buffer <= '0';
else
trigger_auto <= '0';
reset_fifo_buffer <= '1';
end if;
elsif count_param <= COUNT_ONE_ACQUI-COUNT_FIFO_BYTES_T then
reset_fifo_buffer <= '0';
trigger_auto <= '0';
if count_rst_fifo=x"0" then
rd_fifo_count <= '1';
end if;
elsif count_param <= COUNT_ONE_ACQUI then
if count_param = COUNT_ONE_ACQUI then
count_rst_fifo <= count_rst_fifo+1;
count_param <= 0;
if count_rst_fifo = x"1" then
count_rst_fifo <= x"0";
end if;
end if;
end if;
else
count_rst_fifo <= x"0";
count_param <= 0;
trigger_auto <= '0';
reset_fifo_buffer <= '0';
rd_fifo_count <= '0';
end if;
else
count_rst_fifo <= x"0";
count_param <= 0;
trigger_auto <= '0';
reset_fifo_buffer <= '0';
rd_fifo_count <= '0';
end if;
end if;
end process;
------ Get the parameters set by user.
process(clk_proc,reset)
begin
if reset='0' then
spl_rate_dl <= x"00";
accel_config_dl <= "00";
gyro_config_dl <= "00";
gain_compass_dl <= "000";
freq_compass_dl <= "000";
en_dl <= '0';
elsif clk_proc'event and clk_proc='1' then
----- Assignation of the parameters
en <= parameters(0)(31);
spl_rate <= parameters(0)(30 downto 23);
gyro_config <= parameters(0)(22 downto 21);
accel_config <= parameters(0)(20 downto 19);
gain_compass <= parameters(0)(18 downto 16);
freq_compass <= parameters(0)(15 downto 13);
config_button <= config_change;
----- Keep data to detect a change on the configuration
spl_rate_dl <= spl_rate;
accel_config_dl <= accel_config;
gyro_config_dl <= gyro_config;
gain_compass_dl <= gain_compass;
freq_compass_dl <= freq_compass;
en_dl <= en;
end if;
end process;
------ Set Read and Write flags for the FIFO and set data_valid/flow_valid for each flow.
process(clk_proc,reset)
begin
if reset='0' then
rd_en_dl <= '0';
rd_en <= '0';
rd_accel <= '0';
rd_gyro <= '0';
rd_comp <= '0';
wr_en_dl <= '0';
wr_en_flag <= '0';
elsif clk_proc'event and clk_proc='1' then
wr_en_dl <= wr_en;
wr_en_flag <= wr_en and not wr_en_dl;
rd_en_dl <= rd_en;
rd_comp_dl <= rd_comp;
----- Reading FIFO and set data_valid and flow_valid for each flow
if rd_fifo_count='1' then
if count_fifo = "000010" then
rd_en <= '1';
elsif count_fifo = "000001" then
rd_en <= '0';
end if;
else
if rd_en='1' then
if count_fifo = "010100" then
rd_accel <= '1';
elsif count_fifo = "001111" then
rd_accel <= '0';
elsif count_fifo = "001101" then
rd_gyro <= '1';
elsif count_fifo = "000111" then
rd_comp <= '1';
rd_gyro <= '0';
elsif count_fifo = "000010" then
rd_en <= '0';
rd_gyro <= '0';
end if;
else
if count_fifo = "010100" then
rd_en <= '1';
elsif count_fifo = "000000" then
rd_comp <= '0';
end if;
end if;
end if;
end if;
end process;
------ After reading how many bytes are in the FIFO of the mpu, we look if there are only full samples.
------ If one sample is not full, then the data is not read (flag 'ready'=0).
process(clk_proc,reset)
begin
if reset = '0' then
ready <= '0';
fifo_mpu_res <= x"0000";
fifo_mpu_count <= x"0000";
elsif clk_proc'event and clk_proc = '1' then ----- Generate write enable flag for the FIFO
if rd_ready_f='1' then
fifo_mpu_count <= fifo_mpu_count(7 downto 0) & data_fifo_out;
else
fifo_mpu_res <= unsigned(fifo_mpu_count) rem 20;
end if;
if fifo_mpu_res=x"0000" then
ready <= '1';
else
ready <= '0';
end if;
end if;
end process;
AD0 <= AD0_value; -- For mpu i2c address
not_reset <= not reset; -- Fifo asynchronous reset
trigger <= trigger_auto when en='1' else '0'; -- Set trigger when enable
rd_ready_f <= rd_en_dl and rd_fifo_count and rd_en; -- Reading Fifo count bytes from mpu
----- Determine the time between each trigger
spl_ratex2 <= unsigned(spl_rate)&'0';
COUNT_ONE_ACQUI <= to_integer(clk_50M/spl_ratex2);
----- Detecting a modification of the configuration
config_change <= '1' when (spl_rate/=spl_rate_dl or gyro_config/=gyro_config_dl or accel_config/=accel_config_dl
or gain_compass/=gain_compass_dl or freq_compass/=freq_compass_dl) or en/=en_dl
else '0';
----- Set output flows
accelero.dv <= rd_accel and ready;
accelero.fv <= rd_accel and ready;
accelero.data <= data_fifo_out;
gyroscope.dv <= rd_gyro and ready;
gyroscope.fv <= rd_gyro and ready;
gyroscope.data <= data_fifo_out;
compass.dv <= rd_comp and rd_en_dl and ready;
compass.fv <= rd_comp and rd_en_dl and ready;
compass.data <= data_fifo_out;
end RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity CoPro6502papilio is
generic (
UseT65Core : boolean := false;
UseJensCore : boolean := false;
UseAlanDCore : boolean := true
);
port (
-- GOP Signals
fastclk : in std_logic;
-- Tube signals
h_phi2 : in std_logic;
h_addr : in std_logic_vector(2 downto 0);
h_data : inout std_logic_vector(7 downto 0);
h_rdnw : in std_logic;
h_cs_b : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
-- Ram Signals
ram_cs : out std_logic;
ram_oe : out std_logic;
ram_wr : out std_logic;
ram_addr : out std_logic_vector (18 downto 0);
ram_data : inout std_logic_vector (7 downto 0);
led_ram : out std_logic;
led_halt : out std_logic
);
end CoPro6502papilio;
architecture BEHAVIORAL of CoPro6502papilio is
component dcm_32_16
port (
CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component tuberom_65c102
port (
CLK : in std_logic;
ADDR : in std_logic_vector(10 downto 0);
DATA : out std_logic_vector(7 downto 0));
end component;
component T65
port(
Mode : in std_logic_vector(1 downto 0);
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
DI : in std_logic_vector(7 downto 0);
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end component;
component r65c02_tc
port(
clk_clk_i : in std_logic;
d_i : in std_logic_vector(7 downto 0);
irq_n_i : in std_logic;
nmi_n_i : in std_logic;
rdy_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector(15 downto 0);
d_o : out std_logic_vector(7 downto 0);
rd_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic
);
end component;
component r65c02
port(
reset : in std_logic;
clk : in std_logic;
enable : in std_logic;
nmi_n : in std_logic;
irq_n : in std_logic;
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
nwe : out std_logic;
sync : out std_logic;
sync_irq : out std_logic
);
end component;
component tube
port(
h_addr : in std_logic_vector(2 downto 0);
h_cs_b : in std_logic;
h_data : inout std_logic_vector(7 downto 0);
h_phi2 : in std_logic;
h_rdnw : in std_logic;
h_rst_b : in std_logic;
h_irq_b : inout std_logic;
p_addr : in std_logic_vector(2 downto 0);
p_cs_b : in std_logic;
p_data_in : in std_logic_vector(7 downto 0);
p_data_out : out std_logic_vector(7 downto 0);
p_rdnw : in std_logic;
p_phi2 : in std_logic;
p_rst_b : out std_logic;
p_nmi_b : inout std_logic;
p_irq_b : inout std_logic
);
end component;
-------------------------------------------------
-- clock and reset signals
-------------------------------------------------
signal clk_16M00 : std_logic;
signal phi0 : std_logic;
signal phi1 : std_logic;
signal phi2 : std_logic;
signal phi3 : std_logic;
signal cpu_clken : std_logic;
signal bootmode : std_logic;
signal RSTn : std_logic;
signal RSTn_sync : std_logic;
signal clken_counter : std_logic_vector (1 downto 0);
signal reset_counter : std_logic_vector (8 downto 0);
signal led_counter : std_logic_vector (23 downto 0);
-------------------------------------------------
-- parasite signals
-------------------------------------------------
signal p_cs_b : std_logic;
signal gated_p_cs_b : std_logic;
signal p_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- ram/rom signals
-------------------------------------------------
signal ram_cs_b : std_logic;
signal ram_oe_int : std_logic;
signal ram_wr_int : std_logic;
signal rom_cs_b : std_logic;
signal rom_data_out : std_logic_vector (7 downto 0);
-------------------------------------------------
-- cpu signals
-------------------------------------------------
signal cpu_R_W_n : std_logic;
signal cpu_addr : std_logic_vector (23 downto 0);
signal cpu_addr_us: unsigned (23 downto 0);
signal cpu_din : std_logic_vector (7 downto 0);
signal cpu_dout : std_logic_vector (7 downto 0);
signal cpu_dout_us: unsigned (7 downto 0);
signal cpu_IRQ_n : std_logic;
signal cpu_NMI_n : std_logic;
signal cpu_IRQ_n_sync : std_logic;
signal cpu_NMI_n_sync : std_logic;
signal sync : std_logic;
begin
---------------------------------------------------------------------
-- instantiated components
---------------------------------------------------------------------
inst_dcm_32_16 : dcm_32_16 port map (
CLKIN_IN => fastclk,
CLK0_OUT => clk_16M00,
CLK0_OUT1 => open,
CLK2X_OUT => open
);
inst_tuberom : tuberom_65c102 port map (
CLK => clk_16M00,
ADDR => cpu_addr(10 downto 0),
DATA => rom_data_out
);
GenT65Core: if UseT65Core generate
inst_T65 : T65 port map (
Mode => "01",
Abort_n => '1',
SO_n => '1',
Res_n => RSTn_sync,
Enable => cpu_clken,
Clk => clk_16M00,
Rdy => '1',
IRQ_n => cpu_IRQ_n_sync,
NMI_n => cpu_NMI_n_sync,
R_W_n => cpu_R_W_n,
Sync => sync,
A(23 downto 0) => cpu_addr,
DI(7 downto 0) => cpu_din,
DO(7 downto 0) => cpu_dout
);
end generate;
GenJensCore: if UseJensCore generate
Inst_r65c02_tc: r65c02_tc PORT MAP(
clk_clk_i => phi0,
d_i => cpu_din,
irq_n_i => cpu_IRQ_n_sync,
nmi_n_i => cpu_NMI_n_sync,
rdy_i => '1',
rst_rst_n_i => RSTn_sync,
so_n_i => '1',
a_o => cpu_addr(15 downto 0),
d_o => cpu_dout,
rd_o => open,
sync_o => sync,
wr_n_o => cpu_R_W_n,
wr_o => open
);
end generate;
GenAlanDCore: if UseAlanDCore generate
inst_r65c02: r65c02 port map(
reset => RSTn_sync,
clk => clk_16M00,
enable => cpu_clken,
nmi_n => cpu_NMI_n_sync,
irq_n => cpu_IRQ_n_sync,
di => unsigned(cpu_din),
do => cpu_dout_us,
addr => cpu_addr_us(15 downto 0),
nwe => cpu_R_W_n,
sync => sync,
sync_irq => open
);
cpu_dout <= std_logic_vector(cpu_dout_us);
cpu_addr <= std_logic_vector(cpu_addr_us);
end generate;
inst_tube: tube port map (
h_addr => h_addr,
h_cs_b => h_cs_b,
h_data => h_data,
h_phi2 => h_phi2,
h_rdnw => h_rdnw,
h_rst_b => h_rst_b,
h_irq_b => h_irq_b,
p_addr => cpu_addr(2 downto 0),
p_cs_b => gated_p_cs_b,
p_data_in => cpu_dout,
p_data_out => p_data_out,
p_rdnw => cpu_R_W_n,
p_phi2 => clk_16M00,
p_rst_b => RSTn,
p_nmi_b => cpu_NMI_n,
p_irq_b => cpu_IRQ_n
);
gated_p_cs_b <= not((not p_cs_b) and cpu_clken);
p_cs_b <= '0' when cpu_addr(15 downto 3) = "1111111011111" else '1';
rom_cs_b <= '0' when cpu_addr(15 downto 11) = "11111" and cpu_R_W_n = '1' and bootmode = '1' else '1';
ram_cs_b <= '0' when p_cs_b = '1' and rom_cs_b = '1' else '1';
cpu_din <=
p_data_out when p_cs_b = '0' else
rom_data_out when rom_cs_b = '0' else
ram_data when ram_cs_b = '0' else
x"f1";
ram_cs <= ram_cs_b;
ram_oe_int <= not ((not ram_cs_b) and cpu_R_W_n);
ram_oe <= ram_oe_int;
ram_wr_int <= not ((not ram_cs_b) and (not cpu_R_W_n) and phi1);
ram_wr <= ram_wr_int;
-- for an AS6C1008 A17 connects to CE2 which needs to be high
ram_addr <= "111" & cpu_addr(15 downto 0);
ram_data <= cpu_dout when cpu_R_W_n = '0' else "ZZZZZZZZ";
--------------------------------------------------------
-- boot mode generator
--------------------------------------------------------
boot_gen : process(clk_16M00, RSTn_sync)
begin
if RSTn_sync = '0' then
bootmode <= '1';
elsif rising_edge(clk_16M00) then
if p_cs_b = '0' then
bootmode <= '0';
end if;
end if;
end process;
--------------------------------------------------------
-- power up reset
--------------------------------------------------------
reset_gen : process(clk_16M00)
begin
if rising_edge(clk_16M00) then
if (reset_counter(8) = '0') then
reset_counter <= reset_counter + 1;
end if;
RSTn_sync <= RSTn AND reset_counter(8);
end if;
end process;
--------------------------------------------------------
-- interrupt synchronization
--------------------------------------------------------
sync_gen : process(clk_16M00, RSTn_sync)
begin
if RSTn_sync = '0' then
cpu_NMI_n_sync <= '1';
cpu_IRQ_n_sync <= '1';
elsif rising_edge(clk_16M00) then
if (cpu_clken = '1') then
cpu_NMI_n_sync <= cpu_NMI_n;
cpu_IRQ_n_sync <= cpu_IRQ_n;
end if;
end if;
end process;
--------------------------------------------------------
-- clock enable generator
-- 4MHz
-- cpu_clken active on cycle 0, 4, 8, 12
-- address/data changes on cycle 1, 5, 9, 13
-- phi0 active on cycle 1..2
-- phi1 active on cycle 2..3
-- phi2 active on cycle 3..0
-- phi3 active on cycle 0..1
--------------------------------------------------------
clk_gen : process(clk_16M00, RSTn)
begin
if rising_edge(clk_16M00) then
clken_counter <= clken_counter + 1;
cpu_clken <= clken_counter(0) and clken_counter(1);
phi0 <= not clken_counter(1);
phi1 <= phi0;
phi2 <= phi1;
phi3 <= phi2;
end if;
end process;
--------------------------------------------------------
-- led generator
--------------------------------------------------------
led_gen : process(clk_16M00, RSTn)
begin
if rising_edge(clk_16M00) then
led_counter <= led_counter + 1;
led_ram <= led_counter(23);
led_halt <= not led_counter(23);
end if;
end process;
end BEHAVIORAL;
|
context c1 is
library ieee;
end context c1;
-- try multiline
context c1
is
library ieee;
end context c1;
context
c1
is library ieee;
end context
c1
;
context
c1
is
library ieee;
end
;
context
c1
is
library ieee;
end --comment
context
;
-- Try single line
context c1 is library ieee; use ieee.std_logic_1164;
end;
context c1 is library ieee; use ieee.std_logic_1164;
end context;
context c1 is library ieee; use ieee.std_logic_1164;
end context c1;
-- Check comments
context -- comment 1
c1 -- comment 2
is -- comment 3
library ieee; -- comment 4
end -- comment 5
context -- comment 6
c1 -- comment 7
; -- comment 8
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: grpci2_ahb_mst
-- File: grpci2_ahb_mst.vhd
-- Author: Nils-Johan Wessman - Aeroflex Gaisler
-- Description: GRPCI2 AHB master interface
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
use work.pcilib2.all;
entity grpci2_ahb_mst is
generic(
hindex : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
dmai0 : in dma_ahb_in_type;
dmao0 : out dma_ahb_out_type;
dmai1 : in dma_ahb_in_type;
dmao1 : out dma_ahb_out_type
);
end entity;
architecture rtl of grpci2_ahb_mst is
type reg_type is record
bg : std_ulogic; --bus granted
bo : std_ulogic; --bus owner, 0=dma0, 1=dma1
ba : std_ulogic; --bus active
bb : std_ulogic; --1kB burst boundary detected
retry : std_ulogic;
end record;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, 0),
others => zero32);
signal r, rin : reg_type;
begin
comb : process(rst, r, dmai1, dmai0, ahbmi) is
variable v : reg_type;
variable htrans : std_logic_vector(1 downto 0);
variable hbusreq : std_ulogic;
variable hwrite : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable nbo : std_ulogic;
variable retry1 : std_ulogic;
variable retry0 : std_ulogic;
variable ready0 : std_ulogic;
variable ready1 : std_ulogic;
variable error0 : std_ulogic;
variable error1 : std_ulogic;
variable grant1 : std_ulogic;
variable grant0 : std_ulogic;
variable hsize : std_logic_vector(2 downto 0);
variable hburst : std_logic_vector(2 downto 0);
begin
v := r; htrans := HTRANS_IDLE; ready0 := '0'; ready1 := '0'; retry1 := '0';
retry0 := '0'; error0 := '0'; error1 := '0'; grant1 := '0'; grant0 := '0';
hsize := HSIZE_WORD;
hburst := HBURST_INCR;
if r.bo = '0' then hwdata := dmai0.data;
else hwdata := dmai1.data; end if;
hbusreq := dmai1.req or dmai0.req;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
if r.retry = '0' then
nbo := dmai1.req and not (dmai0.req and not r.bo);
else
nbo := r.bo;
end if;
if nbo = '0' then
haddr := dmai0.addr; hwrite := dmai0.write; hsize := '0' & dmai0.size;
if dmai0.burst = '0' then hburst := HBURST_SINGLE; end if;
if (dmai0.req and r.ba
and not r.bo and not r.retry and dmai0.size(1)) = '1' and dmai0.burst = '1' then
htrans := HTRANS_SEQ;
end if;
if (dmai0.req and r.bg and ahbmi.hready and not r.retry) = '1'
then grant0 := '1'; end if;
else
haddr := dmai1.addr; hwrite := dmai1.write; hsize := '0' & dmai1.size;
if dmai1.burst = '0' then hburst := HBURST_SINGLE; end if;
if (dmai1.req and r.ba
and r.bo and not r.retry and dmai1.size(1)) = '1' and dmai1.burst = '1' then
htrans := HTRANS_SEQ;
end if;
if (dmai1.req and r.bg and ahbmi.hready and not r.retry) = '1'
then grant1 := '1'; end if;
end if;
--1 kB burst boundary
if ahbmi.hready = '1' then
if haddr(9 downto 2) = "11111111"
then
v.bb := '1';
if htrans = HTRANS_SEQ then hbusreq := '0'; end if;
elsif ((dmai0.noreq and grant0) or (dmai1.noreq and grant1)) = '1' then
v.bb := '1';
hbusreq := '0';
else
v.bb := '0';
end if;
end if;
if (r.bb = '1') and (htrans /= HTRANS_IDLE) then
htrans := HTRANS_NONSEQ;
end if;
if r.bo = '0' then
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => ready0 := '1';
when HRESP_SPLIT | HRESP_RETRY => retry0 := '1';
when HRESP_ERROR => error0 := '1';
when others => null;
end case;
end if;
end if;
else
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => ready1 := '1';
when HRESP_SPLIT | HRESP_RETRY => retry1 := '1';
when HRESP_ERROR => error1 := '1';
when others => null;
end case;
end if;
end if;
end if;
if (r.ba = '1') and
((ahbmi.hresp = HRESP_RETRY) or (ahbmi.hresp = HRESP_SPLIT) or (ahbmi.hresp = HRESP_ERROR))
then v.retry := not ahbmi.hready; else v.retry := '0'; end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if ahbmi.hready = '1' then
v.bo := nbo; v.bg := ahbmi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else
v.ba := '0';
end if;
end if;
if rst = '0' then
v.bg := '0'; v.ba := '0'; v.bo := '0'; v.bb := '0';
end if;
rin <= v;
dmao1.data <= ahbreadword(ahbmi.hrdata);
dmao0.data <= ahbreadword(ahbmi.hrdata);
dmao1.error <= error1;
dmao1.retry <= retry1;
dmao1.ready <= ready1;
dmao0.error <= error0;
dmao0.retry <= retry0;
dmao0.ready <= ready0;
dmao1.grant <= grant1;
dmao0.grant <= grant0;
ahbmo.htrans <= htrans;
ahbmo.hsize <= hsize;
ahbmo.hbusreq <= hbusreq;
ahbmo.haddr <= haddr;
ahbmo.hwrite <= hwrite;
ahbmo.hwdata <= ahbdrivedata(hwdata);
ahbmo.hburst <= hburst;
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
ahbmo.hlock <= '0';
ahbmo.hprot <= "0011";
ahbmo.hirq <= (others => '0');
end architecture;
|
--???21EDA??
--?????:A-C8V4
--www.21eda.com
--??LED???LED??????0??????1???
--????????21EDA????????
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY LEDA is
PORT(
clk:in STD_LOGIC; --System Clk
led1:out STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END LEDA ;
ARCHITECTURE light OF LEDA IS
SIGNAL clk1 :std_logic;
BEGIN
PROCESS( clk )
VARIABLE Count : integer range 0 to 65535;
BEGIN
IF( clk'EVENT AND clk='1' ) THEN
IF( Count > 50000 ) THEN
Count := 0;
clk1 <= '1';
ELSE
Count := Count + 1;
clk1 <= '0';
END IF;
END IF;
END PROCESS;
---------------------------------------------------------
P2:PROCESS(clk)
variable count1:INTEGER RANGE 0 TO 7;
BEGIN
IF clk'event AND clk='1'THEN
if (clk1 = '1') then
if count1<=4 then
if count1=4 then
count1:=0;
end if;
CASE count1 IS
WHEN 0=>led1<="0111";
WHEN 1=>led1<="1011";
WHEN 2=>led1<="1101";
WHEN 3=>led1<="1110";
WHEN OTHERS=>led1<="1111";
END CASE;
count1:=count1+1;
end if;
end if;
end if;
end process;
END light; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: vcomponents
-- File: vcomponents.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declartions of some XILINX primitives
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package vcomponents is
component ramb4_s16 port (
do : out std_logic_vector (15 downto 0);
addr : in std_logic_vector (7 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (15 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S8
port (do : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (8 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (7 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S4
port (do : out std_logic_vector (3 downto 0);
addr : in std_logic_vector (9 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (3 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S2
port (do : out std_logic_vector (1 downto 0);
addr : in std_logic_vector (10 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (1 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1
port (do : out std_logic_vector (0 downto 0);
addr : in std_logic_vector (11 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (0 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1_S1
port (
doa : out std_logic_vector (0 downto 0);
dob : out std_logic_vector (0 downto 0);
addra : in std_logic_vector (11 downto 0);
addrb : in std_logic_vector (11 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (0 downto 0);
dib : in std_logic_vector (0 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S2_S2
port (
doa : out std_logic_vector (1 downto 0);
dob : out std_logic_vector (1 downto 0);
addra : in std_logic_vector (10 downto 0);
addrb : in std_logic_vector (10 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (1 downto 0);
dib : in std_logic_vector (1 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S4_S4
port (
doa : out std_logic_vector (3 downto 0);
dob : out std_logic_vector (3 downto 0);
addra : in std_logic_vector (9 downto 0);
addrb : in std_logic_vector (9 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (3 downto 0);
dib : in std_logic_vector (3 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S8_S8
port (
doa : out std_logic_vector (7 downto 0);
dob : out std_logic_vector (7 downto 0);
addra : in std_logic_vector (8 downto 0);
addrb : in std_logic_vector (8 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (7 downto 0);
dib : in std_logic_vector (7 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S16_S16
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB16_S1
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S2
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S9
-- pragma translate_off
generic
(
INIT : bit_vector := X"000";
SRVAL : bit_vector := X"000";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S18
-- pragma translate_off
generic
(
INIT : bit_vector := X"00000";
SRVAL : bit_vector := X"00000";
write_mode : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S36
-- pragma translate_off
generic
(
INIT : bit_vector := X"000000000";
SRVAL : bit_vector := X"000000000";
WRITE_MODE : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4_S4
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S1_S1
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S2_S2
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S9_S9
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000";
INIT_B : bit_vector := X"000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000";
SRVAL_B : bit_vector := X"000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S18_S18
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"00000";
INIT_B : bit_vector := X"00000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"00000";
SRVAL_B : bit_vector := X"00000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S36_S36
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000000000";
INIT_B : bit_vector := X"000000000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000000000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component DCM_SP
generic (
TimingChecksOn : boolean := true;
InstancePath : string := "*";
Xon : boolean := true;
MsgOn : boolean := false;
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0; --non-simulatable
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; --non-simulatable
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE"; --non-simulatable
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080"; --non-simulatable
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false --non-simulatable
);
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
CLK2X180 : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
CLKFX : out std_ulogic := '0';
CLKFX180 : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
STATUS : out std_logic_vector(7 downto 0) := "00000000";
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
DSSEN : in std_ulogic := '0';
PSCLK : in std_ulogic := '0';
PSEN : in std_ulogic := '0';
PSINCDEC : in std_ulogic := '0';
RST : in std_ulogic := '0'
);
end component;
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGP port (O : out std_logic; I : in std_logic); end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
component IBUFG generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_logic; I : in std_logic); end component;
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
component IOBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); end component;
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
component OBUFT generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I, T : in std_ulogic); end component;
component CLKDLL
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
LOCKED : out std_ulogic;
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component CLKDLLHF
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
RST : in std_ulogic := '0');
end component;
component BSCAN_VIRTEX
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
component BSCAN_VIRTEX2
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
component BSCAN_SPARTAN3
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
component BSCAN_VIRTEX4 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
component BSCAN_VIRTEX5 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
component IBUFDS
generic (
CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE;
IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO";
IOSTANDARD : string := "DEFAULT");
port (
O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
component IBUFDS_LVDS_25
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_25
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component IOBUFDS
generic(
CAPACITANCE : string := "DONT_CARE";
IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO";
IOSTANDARD : string := "DEFAULT");
port (
O : out std_ulogic;
IO : inout std_ulogic;
IOB : inout std_ulogic;
I : in std_ulogic;
T : in std_ulogic
);
end component;
component OBUFDS
generic(
CAPACITANCE : string := "DONT_CARE";
IOSTANDARD : string := "DEFAULT"
);
port(
O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic
);
end component;
component OBUFDS_LVDS_25
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic);
end component;
component OBUFTDS_LVDS_25
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic;
T : in std_ulogic);
end component;
component IBUFGDS is
generic( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT");
port (O : out std_logic; I, IB : in std_logic);
end component;
component IBUFDS_LVDS_33
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_33
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component OBUFDS_LVDS_33
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic);
end component;
component OBUFTDS_LVDS_33
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic;
T : in std_ulogic);
end component;
component FDCPE
generic ( INIT : bit := '0');
port (
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic);
end component;
component IDDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ODDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT : bit := '0';
SRTYPE : string := "SYNC");
port (
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component IFDDRRSE
port (
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component OFDDRRSE
port (
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FDDRRSE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component IDELAY
generic ( IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0);
port ( O : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
I : in std_ulogic;
INC : in std_ulogic;
RST : in std_ulogic);
end component;
component IDELAYCTRL
port ( RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic);
end component;
component BUFIO
port ( O : out std_ulogic;
I : in std_ulogic);
end component;
component BUFR
generic ( BUFR_DIVIDE : string := "BYPASS";
SIM_DEVICE : string := "VIRTEX4");
port ( O : out std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
I : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component SYSMON
generic
(
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt"
);
port
(
ALM : out std_logic_vector(2 downto 0);
BUSY : out std_ulogic;
CHANNEL : out std_logic_vector(4 downto 0);
DO : out std_logic_vector(15 downto 0);
DRDY : out std_ulogic;
EOC : out std_ulogic;
EOS : out std_ulogic;
JTAGBUSY : out std_ulogic;
JTAGLOCKED : out std_ulogic;
JTAGMODIFIED : out std_ulogic;
OT : out std_ulogic;
CONVST : in std_ulogic;
CONVSTCLK : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
RESET : in std_ulogic;
VAUXN : in std_logic_vector(15 downto 0);
VAUXP : in std_logic_vector(15 downto 0);
VN : in std_ulogic;
VP : in std_ulogic
);
end component;
component FDRSE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FDR
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic);
end component;
component FDRE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component FDRS
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FDE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic);
end component;
component MUXF5
port ( O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic);
end component;
component VCC
port ( P : out std_ulogic := '1');
end component;
component GND
port ( G : out std_ulogic := '0');
end component;
component INV
port
(
O : out std_ulogic;
I : in std_ulogic
);
end component;
component LUT2_L
generic
(
INIT : bit_vector := X"0"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component LUT4
generic
(
INIT : bit_vector := X"0000"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic
);
end component;
component LUT3
generic
(
INIT : bit_vector := X"00"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
component LUT2
generic
(
INIT : bit_vector := X"0"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component FDC
generic
(
INIT : bit := '0'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end component;
component LUT3_L
generic
(
INIT : bit_vector := X"00"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
component LUT1
generic
(
INIT : bit_vector := X"0"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic
);
end component;
component LUT4_L
generic
(
INIT : bit_vector := X"0000"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic
);
end component;
component FDCE
generic
(
INIT : bit := '0'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end component;
component FDC_1
generic
(
INIT : bit := '0'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end component;
component FDP
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic
);
end component;
component FDS
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component LUT1_L
generic
(
INIT : bit_vector := X"0"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic
);
end component;
component MUXF6
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF5_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
component MUXCY_L
port
(
LO : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component FDSE
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
component MULT_AND
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component SRL16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component ROM256X1
generic
(
INIT : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
port
(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
A7 : in std_ulogic
);
end component;
component FDPE
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic
);
end component;
component MULT18X18
port
(
P : out std_logic_vector (35 downto 0);
A : in std_logic_vector (17 downto 0);
B : in std_logic_vector (17 downto 0)
);
end component;
component MULT18X18S
port
(
P : out std_logic_vector (35 downto 0);
A : in std_logic_vector (17 downto 0);
B : in std_logic_vector (17 downto 0);
C : in std_ulogic;
CE : in std_ulogic;
R : in std_ulogic
);
end component;
component MUXF7
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component IODELAY
generic
(
DELAY_SRC : string := "I";
HIGH_PERFORMANCE_MODE : boolean := true;
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
REFCLK_FREQUENCY : real := 200.0;
SIGNAL_PATTERN : string := "DATA"
);
port
(
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component ISERDES
generic
(
BITSLIP_ENABLE : boolean := false;
DATA_RATE : string := "DDR";
DATA_WIDTH : integer := 4;
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
INIT_Q3 : bit := '0';
INIT_Q4 : bit := '0';
INTERFACE_TYPE : string := "MEMORY";
IOBDELAY : string := "NONE";
IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0;
NUM_CE : integer := 2;
SERDES_MODE : string := "MASTER";
SRVAL_Q1 : bit := '0';
SRVAL_Q2 : bit := '0';
SRVAL_Q3 : bit := '0';
SRVAL_Q4 : bit := '0'
);
port
(
O : out std_ulogic;
Q1 : out std_ulogic;
Q2 : out std_ulogic;
Q3 : out std_ulogic;
Q4 : out std_ulogic;
Q5 : out std_ulogic;
Q6 : out std_ulogic;
SHIFTOUT1 : out std_ulogic;
SHIFTOUT2 : out std_ulogic;
BITSLIP : in std_ulogic;
CE1 : in std_ulogic;
CE2 : in std_ulogic;
CLK : in std_ulogic;
CLKDIV : in std_ulogic;
D : in std_ulogic;
DLYCE : in std_ulogic;
DLYINC : in std_ulogic;
DLYRST : in std_ulogic;
OCLK : in std_ulogic;
REV : in std_ulogic;
SHIFTIN1 : in std_ulogic;
SHIFTIN2 : in std_ulogic;
SR : in std_ulogic
);
end component;
component RAM16X1S
generic
(
INIT : bit_vector(15 downto 0) := X"0000"
);
port
(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAM16X1D
generic
(
INIT : bit_vector(15 downto 0) := X"0000"
);
port
(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component ROM32X1
generic
(
INIT : bit_vector := X"00000000"
);
port
(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic
);
end component;
component DSP48
generic
(
AREG : integer := 1;
B_INPUT : string := "DIRECT";
BREG : integer := 1;
CARRYINREG : integer := 1;
CARRYINSELREG : integer := 1;
CREG : integer := 1;
LEGACY_MODE : string := "MULT18X18S";
MREG : integer := 1;
OPMODEREG : integer := 1;
PREG : integer := 1;
SUBTRACTREG : integer := 1
);
port
(
BCOUT : out std_logic_vector(17 downto 0);
P : out std_logic_vector(47 downto 0);
PCOUT : out std_logic_vector(47 downto 0);
A : in std_logic_vector(17 downto 0);
B : in std_logic_vector(17 downto 0);
BCIN : in std_logic_vector(17 downto 0);
C : in std_logic_vector(47 downto 0);
CARRYIN : in std_ulogic;
CARRYINSEL : in std_logic_vector(1 downto 0);
CEA : in std_ulogic;
CEB : in std_ulogic;
CEC : in std_ulogic;
CECARRYIN : in std_ulogic;
CECINSUB : in std_ulogic;
CECTRL : in std_ulogic;
CEM : in std_ulogic;
CEP : in std_ulogic;
CLK : in std_ulogic;
OPMODE : in std_logic_vector(6 downto 0);
PCIN : in std_logic_vector(47 downto 0);
RSTA : in std_ulogic;
RSTB : in std_ulogic;
RSTC : in std_ulogic;
RSTCARRYIN : in std_ulogic;
RSTCTRL : in std_ulogic;
RSTM : in std_ulogic;
RSTP : in std_ulogic;
SUBTRACT : in std_ulogic
);
end component;
component RAMB16
generic
(
DOA_REG : integer := 0;
DOB_REG : integer := 0;
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000000000";
INIT_B : bit_vector := X"000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INVERT_CLK_DOA_REG : boolean := false;
INVERT_CLK_DOB_REG : boolean := false;
RAM_EXTENSION_A : string := "NONE";
RAM_EXTENSION_B : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000000000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0
);
port
(
CASCADEOUTA : out std_ulogic;
CASCADEOUTB : out std_ulogic;
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (14 downto 0);
ADDRB : in std_logic_vector (14 downto 0);
CASCADEINA : in std_ulogic;
CASCADEINB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector (3 downto 0);
WEB : in std_logic_vector (3 downto 0)
);
end component;
component MUXF8
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component RAM64X1D
generic ( INIT : bit_vector(63 downto 0) := X"0000000000000000");
port
(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
DPRA4 : in std_ulogic;
DPRA5 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component BUF
port
(
O : out std_ulogic;
I : in std_ulogic
);
end component;
component LUT5
generic
(
INIT : bit_vector := X"00000000"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic
);
end component;
component LUT5_L
generic
(
INIT : bit_vector := X"00000000"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic
);
end component;
component LUT6
generic
(
INIT : bit_vector := X"0000000000000000"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic;
I5 : in std_ulogic
);
end component;
component LUT6_L
generic
(
INIT : bit_vector := X"0000000000000000"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic;
I5 : in std_ulogic
);
end component;
component RAM128X1S
generic (
INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000"
);
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: vcomponents
-- File: vcomponents.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declartions of some XILINX primitives
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package vcomponents is
component ramb4_s16 port (
do : out std_logic_vector (15 downto 0);
addr : in std_logic_vector (7 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (15 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S8
port (do : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (8 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (7 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S4
port (do : out std_logic_vector (3 downto 0);
addr : in std_logic_vector (9 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (3 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S2
port (do : out std_logic_vector (1 downto 0);
addr : in std_logic_vector (10 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (1 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1
port (do : out std_logic_vector (0 downto 0);
addr : in std_logic_vector (11 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (0 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1_S1
port (
doa : out std_logic_vector (0 downto 0);
dob : out std_logic_vector (0 downto 0);
addra : in std_logic_vector (11 downto 0);
addrb : in std_logic_vector (11 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (0 downto 0);
dib : in std_logic_vector (0 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S2_S2
port (
doa : out std_logic_vector (1 downto 0);
dob : out std_logic_vector (1 downto 0);
addra : in std_logic_vector (10 downto 0);
addrb : in std_logic_vector (10 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (1 downto 0);
dib : in std_logic_vector (1 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S4_S4
port (
doa : out std_logic_vector (3 downto 0);
dob : out std_logic_vector (3 downto 0);
addra : in std_logic_vector (9 downto 0);
addrb : in std_logic_vector (9 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (3 downto 0);
dib : in std_logic_vector (3 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S8_S8
port (
doa : out std_logic_vector (7 downto 0);
dob : out std_logic_vector (7 downto 0);
addra : in std_logic_vector (8 downto 0);
addrb : in std_logic_vector (8 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (7 downto 0);
dib : in std_logic_vector (7 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S16_S16
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB16_S1
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S2
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4
-- pragma translate_off
generic
(
INIT : bit_vector := X"0";
SRVAL : bit_vector := X"0";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S9
-- pragma translate_off
generic
(
INIT : bit_vector := X"000";
SRVAL : bit_vector := X"000";
WRITE_MODE : string := "WRITE_FIRST";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S18
-- pragma translate_off
generic
(
INIT : bit_vector := X"00000";
SRVAL : bit_vector := X"00000";
write_mode : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S36
-- pragma translate_off
generic
(
INIT : bit_vector := X"000000000";
SRVAL : bit_vector := X"000000000";
WRITE_MODE : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
-- pragma translate_on
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4_S4
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S1_S1
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S2_S2
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"0";
INIT_B : bit_vector := X"0";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"0";
SRVAL_B : bit_vector := X"0";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S9_S9
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000";
INIT_B : bit_vector := X"000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000";
SRVAL_B : bit_vector := X"000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S18_S18
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"00000";
INIT_B : bit_vector := X"00000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"00000";
SRVAL_B : bit_vector := X"00000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S36_S36
-- pragma translate_off
generic
(
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000000000";
INIT_B : bit_vector := X"000000000";
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000000000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST"
);
-- pragma translate_on
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component DCM_SP
generic (
TimingChecksOn : boolean := true;
InstancePath : string := "*";
Xon : boolean := true;
MsgOn : boolean := false;
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0; --non-simulatable
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; --non-simulatable
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE"; --non-simulatable
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080"; --non-simulatable
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false --non-simulatable
);
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
CLK2X180 : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
CLKFX : out std_ulogic := '0';
CLKFX180 : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
STATUS : out std_logic_vector(7 downto 0) := "00000000";
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
DSSEN : in std_ulogic := '0';
PSCLK : in std_ulogic := '0';
PSEN : in std_ulogic := '0';
PSINCDEC : in std_ulogic := '0';
RST : in std_ulogic := '0'
);
end component;
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGP port (O : out std_logic; I : in std_logic); end component;
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
component IBUFG generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_logic; I : in std_logic); end component;
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
component IOBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); end component;
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
component OBUFT generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I, T : in std_ulogic); end component;
component CLKDLL
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
LOCKED : out std_ulogic;
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component CLKDLLHF
port (
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
RST : in std_ulogic := '0');
end component;
component BSCAN_VIRTEX
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
component BSCAN_VIRTEX2
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
component BSCAN_SPARTAN3
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
component BSCAN_VIRTEX4 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
component BSCAN_VIRTEX5 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
component IBUFDS
generic (
CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE;
IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO";
IOSTANDARD : string := "DEFAULT");
port (
O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
component IBUFDS_LVDS_25
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_25
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component IOBUFDS
generic(
CAPACITANCE : string := "DONT_CARE";
IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO";
IOSTANDARD : string := "DEFAULT");
port (
O : out std_ulogic;
IO : inout std_ulogic;
IOB : inout std_ulogic;
I : in std_ulogic;
T : in std_ulogic
);
end component;
component OBUFDS
generic(
CAPACITANCE : string := "DONT_CARE";
IOSTANDARD : string := "DEFAULT"
);
port(
O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic
);
end component;
component OBUFDS_LVDS_25
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic);
end component;
component OBUFTDS_LVDS_25
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic;
T : in std_ulogic);
end component;
component IBUFGDS is
generic( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT");
port (O : out std_logic; I, IB : in std_logic);
end component;
component IBUFDS_LVDS_33
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_33
port ( O : out std_ulogic;
I : in std_ulogic;
IB : in std_ulogic);
end component;
component OBUFDS_LVDS_33
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic);
end component;
component OBUFTDS_LVDS_33
port ( O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic;
T : in std_ulogic);
end component;
component FDCPE
generic ( INIT : bit := '0');
port (
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic);
end component;
component IDDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ODDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT : bit := '0';
SRTYPE : string := "SYNC");
port (
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component IFDDRRSE
port (
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component OFDDRRSE
port (
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FDDRRSE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component IDELAY
generic ( IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0);
port ( O : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
I : in std_ulogic;
INC : in std_ulogic;
RST : in std_ulogic);
end component;
component IDELAYCTRL
port ( RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic);
end component;
component BUFIO
port ( O : out std_ulogic;
I : in std_ulogic);
end component;
component BUFR
generic ( BUFR_DIVIDE : string := "BYPASS";
SIM_DEVICE : string := "VIRTEX4");
port ( O : out std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
I : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component SYSMON
generic
(
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt"
);
port
(
ALM : out std_logic_vector(2 downto 0);
BUSY : out std_ulogic;
CHANNEL : out std_logic_vector(4 downto 0);
DO : out std_logic_vector(15 downto 0);
DRDY : out std_ulogic;
EOC : out std_ulogic;
EOS : out std_ulogic;
JTAGBUSY : out std_ulogic;
JTAGLOCKED : out std_ulogic;
JTAGMODIFIED : out std_ulogic;
OT : out std_ulogic;
CONVST : in std_ulogic;
CONVSTCLK : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
RESET : in std_ulogic;
VAUXN : in std_logic_vector(15 downto 0);
VAUXP : in std_logic_vector(15 downto 0);
VN : in std_ulogic;
VP : in std_ulogic
);
end component;
component FDRSE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FDR
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic);
end component;
component FDRE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component FDRS
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FDE
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic);
end component;
component MUXF5
port ( O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic);
end component;
component VCC
port ( P : out std_ulogic := '1');
end component;
component GND
port ( G : out std_ulogic := '0');
end component;
component INV
port
(
O : out std_ulogic;
I : in std_ulogic
);
end component;
component LUT2_L
generic
(
INIT : bit_vector := X"0"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component LUT4
generic
(
INIT : bit_vector := X"0000"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic
);
end component;
component LUT3
generic
(
INIT : bit_vector := X"00"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
component LUT2
generic
(
INIT : bit_vector := X"0"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component FDC
generic
(
INIT : bit := '0'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end component;
component LUT3_L
generic
(
INIT : bit_vector := X"00"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic
);
end component;
component LUT1
generic
(
INIT : bit_vector := X"0"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic
);
end component;
component LUT4_L
generic
(
INIT : bit_vector := X"0000"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic
);
end component;
component FDCE
generic
(
INIT : bit := '0'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end component;
component FDC_1
generic
(
INIT : bit := '0'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic
);
end component;
component FDP
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic
);
end component;
component FDS
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component LUT1_L
generic
(
INIT : bit_vector := X"0"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic
);
end component;
component MUXF6
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF5_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
component MUXCY_L
port
(
LO : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component FDSE
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
component MULT_AND
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic
);
end component;
component SRL16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component ROM256X1
generic
(
INIT : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
port
(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
A7 : in std_ulogic
);
end component;
component FDPE
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic
);
end component;
component MULT18X18
port
(
P : out std_logic_vector (35 downto 0);
A : in std_logic_vector (17 downto 0);
B : in std_logic_vector (17 downto 0)
);
end component;
component MULT18X18S
port
(
P : out std_logic_vector (35 downto 0);
A : in std_logic_vector (17 downto 0);
B : in std_logic_vector (17 downto 0);
C : in std_ulogic;
CE : in std_ulogic;
R : in std_ulogic
);
end component;
component MUXF7
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component IODELAY
generic
(
DELAY_SRC : string := "I";
HIGH_PERFORMANCE_MODE : boolean := true;
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
REFCLK_FREQUENCY : real := 200.0;
SIGNAL_PATTERN : string := "DATA"
);
port
(
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component ISERDES
generic
(
BITSLIP_ENABLE : boolean := false;
DATA_RATE : string := "DDR";
DATA_WIDTH : integer := 4;
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
INIT_Q3 : bit := '0';
INIT_Q4 : bit := '0';
INTERFACE_TYPE : string := "MEMORY";
IOBDELAY : string := "NONE";
IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0;
NUM_CE : integer := 2;
SERDES_MODE : string := "MASTER";
SRVAL_Q1 : bit := '0';
SRVAL_Q2 : bit := '0';
SRVAL_Q3 : bit := '0';
SRVAL_Q4 : bit := '0'
);
port
(
O : out std_ulogic;
Q1 : out std_ulogic;
Q2 : out std_ulogic;
Q3 : out std_ulogic;
Q4 : out std_ulogic;
Q5 : out std_ulogic;
Q6 : out std_ulogic;
SHIFTOUT1 : out std_ulogic;
SHIFTOUT2 : out std_ulogic;
BITSLIP : in std_ulogic;
CE1 : in std_ulogic;
CE2 : in std_ulogic;
CLK : in std_ulogic;
CLKDIV : in std_ulogic;
D : in std_ulogic;
DLYCE : in std_ulogic;
DLYINC : in std_ulogic;
DLYRST : in std_ulogic;
OCLK : in std_ulogic;
REV : in std_ulogic;
SHIFTIN1 : in std_ulogic;
SHIFTIN2 : in std_ulogic;
SR : in std_ulogic
);
end component;
component RAM16X1S
generic
(
INIT : bit_vector(15 downto 0) := X"0000"
);
port
(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAM16X1D
generic
(
INIT : bit_vector(15 downto 0) := X"0000"
);
port
(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component ROM32X1
generic
(
INIT : bit_vector := X"00000000"
);
port
(
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic
);
end component;
component DSP48
generic
(
AREG : integer := 1;
B_INPUT : string := "DIRECT";
BREG : integer := 1;
CARRYINREG : integer := 1;
CARRYINSELREG : integer := 1;
CREG : integer := 1;
LEGACY_MODE : string := "MULT18X18S";
MREG : integer := 1;
OPMODEREG : integer := 1;
PREG : integer := 1;
SUBTRACTREG : integer := 1
);
port
(
BCOUT : out std_logic_vector(17 downto 0);
P : out std_logic_vector(47 downto 0);
PCOUT : out std_logic_vector(47 downto 0);
A : in std_logic_vector(17 downto 0);
B : in std_logic_vector(17 downto 0);
BCIN : in std_logic_vector(17 downto 0);
C : in std_logic_vector(47 downto 0);
CARRYIN : in std_ulogic;
CARRYINSEL : in std_logic_vector(1 downto 0);
CEA : in std_ulogic;
CEB : in std_ulogic;
CEC : in std_ulogic;
CECARRYIN : in std_ulogic;
CECINSUB : in std_ulogic;
CECTRL : in std_ulogic;
CEM : in std_ulogic;
CEP : in std_ulogic;
CLK : in std_ulogic;
OPMODE : in std_logic_vector(6 downto 0);
PCIN : in std_logic_vector(47 downto 0);
RSTA : in std_ulogic;
RSTB : in std_ulogic;
RSTC : in std_ulogic;
RSTCARRYIN : in std_ulogic;
RSTCTRL : in std_ulogic;
RSTM : in std_ulogic;
RSTP : in std_ulogic;
SUBTRACT : in std_ulogic
);
end component;
component RAMB16
generic
(
DOA_REG : integer := 0;
DOB_REG : integer := 0;
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := X"000000000";
INIT_B : bit_vector := X"000000000";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INVERT_CLK_DOA_REG : boolean := false;
INVERT_CLK_DOB_REG : boolean := false;
RAM_EXTENSION_A : string := "NONE";
RAM_EXTENSION_B : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
SRVAL_A : bit_vector := X"000000000";
SRVAL_B : bit_vector := X"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0
);
port
(
CASCADEOUTA : out std_ulogic;
CASCADEOUTB : out std_ulogic;
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (14 downto 0);
ADDRB : in std_logic_vector (14 downto 0);
CASCADEINA : in std_ulogic;
CASCADEINB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector (3 downto 0);
WEB : in std_logic_vector (3 downto 0)
);
end component;
component MUXF8
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component RAM64X1D
generic ( INIT : bit_vector(63 downto 0) := X"0000000000000000");
port
(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
DPRA4 : in std_ulogic;
DPRA5 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
component BUF
port
(
O : out std_ulogic;
I : in std_ulogic
);
end component;
component LUT5
generic
(
INIT : bit_vector := X"00000000"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic
);
end component;
component LUT5_L
generic
(
INIT : bit_vector := X"00000000"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic
);
end component;
component LUT6
generic
(
INIT : bit_vector := X"0000000000000000"
);
port
(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic;
I5 : in std_ulogic
);
end component;
component LUT6_L
generic
(
INIT : bit_vector := X"0000000000000000"
);
port
(
LO : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
I3 : in std_ulogic;
I4 : in std_ulogic;
I5 : in std_ulogic
);
end component;
component RAM128X1S
generic (
INIT : bit_vector(127 downto 0) := X"00000000000000000000000000000000"
);
port (
O : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
D : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
end;
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- Avalon MM interface for PWM --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE info_device_pkg IS
CONSTANT c_int_number_of_descr_register: INTEGER := 7;
CONSTANT info_device_address_width : INTEGER := 5;
COMPONENT info_device IS
GENERIC (
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
description: STD_LOGIC_VECTOR (c_int_number_of_descr_register*c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
dev_size: INTEGER := 0
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(info_device_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0)
);
END COMPONENT;
CONSTANT info_device_subtype_id : INTEGER := 0;
CONSTANT info_device_interface_version : INTEGER := 0;
CONSTANT c_usig_typdef_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_typdef_address,info_device_address_width);
CONSTANT c_usig_mem_size_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_mem_size_address,info_device_address_width);
CONSTANT c_usig_unique_id_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_unique_id_address,info_device_address_width);
CONSTANT c_usig_dev_size_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers, info_device_address_width);
CONSTANT c_usig_description_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := c_usig_dev_size_address + 1;
CONSTANT c_usig_max_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := c_usig_dev_size_address + c_int_number_of_descr_register;
END PACKAGE info_device_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.info_device_pkg.ALL;
USE work.fLink_definitions.ALL;
ENTITY info_device IS
GENERIC (
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
description: STD_LOGIC_VECTOR (c_int_number_of_descr_register*c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
dev_size: INTEGER := 0
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(info_device_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0)
);
END ENTITY info_device;
ARCHITECTURE rtl OF info_device IS
BEGIN
-- combinatoric process
comb_proc : PROCESS (isl_reset_n,isl_avs_write,islv_avs_address,isl_avs_read,islv_avs_write_data,isl_clk)
VARIABLE description_part: INTEGER := 0;
VARIABLE address: UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(0,info_device_address_width);
BEGIN
--type conversion
address := UNSIGNED(islv_avs_address);
--standard values
oslv_avs_read_data <= (OTHERS => '0');
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE address IS
WHEN c_usig_typdef_address =>
oslv_avs_read_data ((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length - 1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_info_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= STD_LOGIC_VECTOR(to_unsigned(info_device_subtype_id,c_fLink_subtype_length));
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(info_device_interface_version,c_fLink_interface_version_length));
WHEN c_usig_mem_size_address =>
oslv_avs_read_data(info_device_address_width+2) <= '1';
WHEN c_usig_unique_id_address =>
oslv_avs_read_data <= unique_id;
WHEN c_usig_dev_size_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(dev_size,c_fLink_avs_data_width));
WHEN OTHERS =>
IF address >= c_usig_description_address AND address <= c_usig_max_address THEN
description_part := to_integer(address - c_usig_description_address);
oslv_avs_read_data <= description(((c_int_number_of_descr_register-description_part))*32-1 DOWNTO (c_int_number_of_descr_register-description_part-1)*32);
END IF;
END CASE;
END IF;
END PROCESS comb_proc;
osl_avs_waitrequest <= '0';
END rtl;
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- Avalon MM interface for PWM --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE info_device_pkg IS
CONSTANT c_int_number_of_descr_register: INTEGER := 7;
CONSTANT info_device_address_width : INTEGER := 5;
COMPONENT info_device IS
GENERIC (
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
description: STD_LOGIC_VECTOR (c_int_number_of_descr_register*c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
dev_size: INTEGER := 0
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(info_device_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0)
);
END COMPONENT;
CONSTANT info_device_subtype_id : INTEGER := 0;
CONSTANT info_device_interface_version : INTEGER := 0;
CONSTANT c_usig_typdef_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_typdef_address,info_device_address_width);
CONSTANT c_usig_mem_size_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_mem_size_address,info_device_address_width);
CONSTANT c_usig_unique_id_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_unique_id_address,info_device_address_width);
CONSTANT c_usig_dev_size_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers, info_device_address_width);
CONSTANT c_usig_description_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := c_usig_dev_size_address + 1;
CONSTANT c_usig_max_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := c_usig_dev_size_address + c_int_number_of_descr_register;
END PACKAGE info_device_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.info_device_pkg.ALL;
USE work.fLink_definitions.ALL;
ENTITY info_device IS
GENERIC (
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
description: STD_LOGIC_VECTOR (c_int_number_of_descr_register*c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
dev_size: INTEGER := 0
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(info_device_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0)
);
END ENTITY info_device;
ARCHITECTURE rtl OF info_device IS
BEGIN
-- combinatoric process
comb_proc : PROCESS (isl_reset_n,isl_avs_write,islv_avs_address,isl_avs_read,islv_avs_write_data,isl_clk)
VARIABLE description_part: INTEGER := 0;
VARIABLE address: UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(0,info_device_address_width);
BEGIN
--type conversion
address := UNSIGNED(islv_avs_address);
--standard values
oslv_avs_read_data <= (OTHERS => '0');
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE address IS
WHEN c_usig_typdef_address =>
oslv_avs_read_data ((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length - 1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_info_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= STD_LOGIC_VECTOR(to_unsigned(info_device_subtype_id,c_fLink_subtype_length));
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(info_device_interface_version,c_fLink_interface_version_length));
WHEN c_usig_mem_size_address =>
oslv_avs_read_data(info_device_address_width+2) <= '1';
WHEN c_usig_unique_id_address =>
oslv_avs_read_data <= unique_id;
WHEN c_usig_dev_size_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(dev_size,c_fLink_avs_data_width));
WHEN OTHERS =>
IF address >= c_usig_description_address AND address <= c_usig_max_address THEN
description_part := to_integer(address - c_usig_description_address);
oslv_avs_read_data <= description(((c_int_number_of_descr_register-description_part))*32-1 DOWNTO (c_int_number_of_descr_register-description_part-1)*32);
END IF;
END CASE;
END IF;
END PROCESS comb_proc;
osl_avs_waitrequest <= '0';
END rtl;
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- Avalon MM interface for PWM --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE info_device_pkg IS
CONSTANT c_int_number_of_descr_register: INTEGER := 7;
CONSTANT info_device_address_width : INTEGER := 5;
COMPONENT info_device IS
GENERIC (
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
description: STD_LOGIC_VECTOR (c_int_number_of_descr_register*c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
dev_size: INTEGER := 0
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(info_device_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0)
);
END COMPONENT;
CONSTANT info_device_subtype_id : INTEGER := 0;
CONSTANT info_device_interface_version : INTEGER := 0;
CONSTANT c_usig_typdef_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_typdef_address,info_device_address_width);
CONSTANT c_usig_mem_size_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_mem_size_address,info_device_address_width);
CONSTANT c_usig_unique_id_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_unique_id_address,info_device_address_width);
CONSTANT c_usig_dev_size_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers, info_device_address_width);
CONSTANT c_usig_description_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := c_usig_dev_size_address + 1;
CONSTANT c_usig_max_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := c_usig_dev_size_address + c_int_number_of_descr_register;
END PACKAGE info_device_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.info_device_pkg.ALL;
USE work.fLink_definitions.ALL;
ENTITY info_device IS
GENERIC (
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
description: STD_LOGIC_VECTOR (c_int_number_of_descr_register*c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
dev_size: INTEGER := 0
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(info_device_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0)
);
END ENTITY info_device;
ARCHITECTURE rtl OF info_device IS
BEGIN
-- combinatoric process
comb_proc : PROCESS (isl_reset_n,isl_avs_write,islv_avs_address,isl_avs_read,islv_avs_write_data,isl_clk)
VARIABLE description_part: INTEGER := 0;
VARIABLE address: UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(0,info_device_address_width);
BEGIN
--type conversion
address := UNSIGNED(islv_avs_address);
--standard values
oslv_avs_read_data <= (OTHERS => '0');
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE address IS
WHEN c_usig_typdef_address =>
oslv_avs_read_data ((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length - 1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_info_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= STD_LOGIC_VECTOR(to_unsigned(info_device_subtype_id,c_fLink_subtype_length));
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(info_device_interface_version,c_fLink_interface_version_length));
WHEN c_usig_mem_size_address =>
oslv_avs_read_data(info_device_address_width+2) <= '1';
WHEN c_usig_unique_id_address =>
oslv_avs_read_data <= unique_id;
WHEN c_usig_dev_size_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(dev_size,c_fLink_avs_data_width));
WHEN OTHERS =>
IF address >= c_usig_description_address AND address <= c_usig_max_address THEN
description_part := to_integer(address - c_usig_description_address);
oslv_avs_read_data <= description(((c_int_number_of_descr_register-description_part))*32-1 DOWNTO (c_int_number_of_descr_register-description_part-1)*32);
END IF;
END CASE;
END IF;
END PROCESS comb_proc;
osl_avs_waitrequest <= '0';
END rtl;
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- Avalon MM interface for PWM --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE info_device_pkg IS
CONSTANT c_int_number_of_descr_register: INTEGER := 7;
CONSTANT info_device_address_width : INTEGER := 5;
COMPONENT info_device IS
GENERIC (
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
description: STD_LOGIC_VECTOR (c_int_number_of_descr_register*c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
dev_size: INTEGER := 0
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(info_device_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0)
);
END COMPONENT;
CONSTANT info_device_subtype_id : INTEGER := 0;
CONSTANT info_device_interface_version : INTEGER := 0;
CONSTANT c_usig_typdef_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_typdef_address,info_device_address_width);
CONSTANT c_usig_mem_size_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_mem_size_address,info_device_address_width);
CONSTANT c_usig_unique_id_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_unique_id_address,info_device_address_width);
CONSTANT c_usig_dev_size_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers, info_device_address_width);
CONSTANT c_usig_description_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := c_usig_dev_size_address + 1;
CONSTANT c_usig_max_address : UNSIGNED(info_device_address_width-1 DOWNTO 0) := c_usig_dev_size_address + c_int_number_of_descr_register;
END PACKAGE info_device_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.info_device_pkg.ALL;
USE work.fLink_definitions.ALL;
ENTITY info_device IS
GENERIC (
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
description: STD_LOGIC_VECTOR (c_int_number_of_descr_register*c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0');
dev_size: INTEGER := 0
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(info_device_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0)
);
END ENTITY info_device;
ARCHITECTURE rtl OF info_device IS
BEGIN
-- combinatoric process
comb_proc : PROCESS (isl_reset_n,isl_avs_write,islv_avs_address,isl_avs_read,islv_avs_write_data,isl_clk)
VARIABLE description_part: INTEGER := 0;
VARIABLE address: UNSIGNED(info_device_address_width-1 DOWNTO 0) := to_unsigned(0,info_device_address_width);
BEGIN
--type conversion
address := UNSIGNED(islv_avs_address);
--standard values
oslv_avs_read_data <= (OTHERS => '0');
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE address IS
WHEN c_usig_typdef_address =>
oslv_avs_read_data ((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length - 1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_info_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= STD_LOGIC_VECTOR(to_unsigned(info_device_subtype_id,c_fLink_subtype_length));
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(info_device_interface_version,c_fLink_interface_version_length));
WHEN c_usig_mem_size_address =>
oslv_avs_read_data(info_device_address_width+2) <= '1';
WHEN c_usig_unique_id_address =>
oslv_avs_read_data <= unique_id;
WHEN c_usig_dev_size_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(dev_size,c_fLink_avs_data_width));
WHEN OTHERS =>
IF address >= c_usig_description_address AND address <= c_usig_max_address THEN
description_part := to_integer(address - c_usig_description_address);
oslv_avs_read_data <= description(((c_int_number_of_descr_register-description_part))*32-1 DOWNTO (c_int_number_of_descr_register-description_part-1)*32);
END IF;
END CASE;
END IF;
END PROCESS comb_proc;
osl_avs_waitrequest <= '0';
END rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3073.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03073pkg is
type positive_cons_vector is array (15 downto 0) of positive;
constant C19 : positive_cons_vector := (others => 3);
end c12s06b02x00p06n01i03073pkg;
use work.c12s06b02x00p06n01i03073pkg.all;
ENTITY c12s06b02x00p06n01i03073ent_a IS
PORT
(
F1: OUT integer ;
F3: IN positive_cons_vector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03073ent_a;
ARCHITECTURE c12s06b02x00p06n01i03073arch_a OF c12s06b02x00p06n01i03073ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03073arch_a;
use work.c12s06b02x00p06n01i03073pkg.all;
ENTITY c12s06b02x00p06n01i03073ent IS
END c12s06b02x00p06n01i03073ent;
ARCHITECTURE c12s06b02x00p06n01i03073arch OF c12s06b02x00p06n01i03073ent IS
function scalar_complex(s : integer) return positive_cons_vector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN positive_cons_vector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03073ent_a(c12s06b02x00p06n01i03073arch_a);
signal S1 : positive_cons_vector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03073"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03073 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03073arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3073.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03073pkg is
type positive_cons_vector is array (15 downto 0) of positive;
constant C19 : positive_cons_vector := (others => 3);
end c12s06b02x00p06n01i03073pkg;
use work.c12s06b02x00p06n01i03073pkg.all;
ENTITY c12s06b02x00p06n01i03073ent_a IS
PORT
(
F1: OUT integer ;
F3: IN positive_cons_vector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03073ent_a;
ARCHITECTURE c12s06b02x00p06n01i03073arch_a OF c12s06b02x00p06n01i03073ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03073arch_a;
use work.c12s06b02x00p06n01i03073pkg.all;
ENTITY c12s06b02x00p06n01i03073ent IS
END c12s06b02x00p06n01i03073ent;
ARCHITECTURE c12s06b02x00p06n01i03073arch OF c12s06b02x00p06n01i03073ent IS
function scalar_complex(s : integer) return positive_cons_vector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN positive_cons_vector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03073ent_a(c12s06b02x00p06n01i03073arch_a);
signal S1 : positive_cons_vector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03073"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03073 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03073arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3073.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03073pkg is
type positive_cons_vector is array (15 downto 0) of positive;
constant C19 : positive_cons_vector := (others => 3);
end c12s06b02x00p06n01i03073pkg;
use work.c12s06b02x00p06n01i03073pkg.all;
ENTITY c12s06b02x00p06n01i03073ent_a IS
PORT
(
F1: OUT integer ;
F3: IN positive_cons_vector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03073ent_a;
ARCHITECTURE c12s06b02x00p06n01i03073arch_a OF c12s06b02x00p06n01i03073ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03073arch_a;
use work.c12s06b02x00p06n01i03073pkg.all;
ENTITY c12s06b02x00p06n01i03073ent IS
END c12s06b02x00p06n01i03073ent;
ARCHITECTURE c12s06b02x00p06n01i03073arch OF c12s06b02x00p06n01i03073ent IS
function scalar_complex(s : integer) return positive_cons_vector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN positive_cons_vector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03073ent_a(c12s06b02x00p06n01i03073arch_a);
signal S1 : positive_cons_vector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03073"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03073 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03073arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity stratix3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of stratix3_pll is
component altpll
generic (
intended_device_family : string := "Stratix III" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0";
inclk0_input_frequency : positive;
width_clock : positive := 10;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (9 downto 0);
signal inclk : std_logic_vector (1 downto 0);
signal fb : std_logic;
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 3) <= (others => '0');
clkena(0) <= '1';
clkena(1) <= '1' when sdramen = 1 else '0';
clkena(2) <= '1' when clk2xen = 1 else '0';
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(2); e0 <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix III",
--operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
width_clock => 10, compensate_clock => "CLK1",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix III",
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
width_clock => 10,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_stratixiii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
tech : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_stratixiii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
component stratix3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : stratix3_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_stratixiii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_stratixiii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PIT IS
PORT(
clk : in std_logic;
rst : in std_logic;
bus_dq : inout std_logic_vector(15 downto 0);
bus_rw : in std_logic;
bus_req : in std_logic;
bus_addr : in std_logic_vector(15 downto 0);
int : out std_logic_vector(2 downto 0);
bus_ack : out std_logic_vector(2 downto 0)
);
END PIT;
ARCHITECTURE behavioral OF PIT IS
-- Internal Registers
signal div1 : unsigned(15 downto 0) := x"ffff";
signal div1c : unsigned(15 downto 0):= x"0000";
signal f1 : std_logic :='0';
signal div2 : unsigned(15 downto 0):= x"ffff";
signal div2c : unsigned(15 downto 0):= x"0000";
signal f2 : std_logic:='0';
signal div3 : unsigned(15 downto 0):= x"ffff";
signal div3c : unsigned(15 downto 0):= x"0000";
signal f3 : std_logic:='0';
signal controller : std_logic_vector(15 downto 0) := x"0000";
signal counter1 : unsigned(15 downto 0):= x"000A";
signal counter2 : unsigned(15 downto 0):= x"0064";
signal counter3 : unsigned(15 downto 0):= x"03E8";
signal inta : std_logic_vector(2 downto 0);
BEGIN
process(clk, rst)
begin
if(rst='1') then
controller <= (others => '0');
div1 <= (others => '1');
div2 <= (others => '1');
div3 <= (others => '1');
elsif(rising_edge(clk)) then
bus_ack <= "000";
if(bus_req = '1') then
case bus_addr is
when x"0990" =>
if(bus_rw = '1') then
bus_dq <= (others => 'Z');
div1 <= unsigned(bus_dq);
else
bus_dq <= std_logic_vector(counter1);
bus_ack <= "001";
end if;
when x"0991" =>
if(bus_rw = '1') then
bus_dq <= (others => 'Z');
div2 <= unsigned(bus_dq);
else
bus_dq <=std_logic_vector(counter2);
bus_ack <= "010";
end if;
when x"0992" =>
if(bus_rw = '1') then
bus_dq <= (others => 'Z');
div3 <= unsigned(bus_dq);
else
bus_dq <=std_logic_vector(counter3);
bus_ack <= "100";
end if;
when x"0993" =>
if(bus_rw = '1') then
bus_dq <= (others => 'Z');
controller <= bus_dq;
else
bus_dq <= (others => '0');
end if;
when others =>
end case;
end if;
end if;
end process;
--geradore de clock
process(clk, rst)
begin
if(rst = '1') then
div1c <= x"0000";
elsif(rising_edge(clk)) then
IF div1c < div1 THEN
div1c <= div1c + '1';
ELSE
div1c <= x"0000";
f1 <= not f1;
END IF;
IF div2c < div2 THEN
div2c <= div2c + '1';
ELSE
div2c <= x"0000";
f2 <= not f2;
END IF;
IF div3c < div3 THEN
div3c <= div3c + '1';
ELSE
div3c <= x"0000";
f3 <= not f3;
END IF;
end if;
end process;
process(f1, div1, rst)
begin
if(rst='1') then
counter1 <= x"000A";
elsif(rising_edge(f1)) then
counter1 <= counter1 - 1;
if(std_logic_vector(counter1) = x"0000") then
counter1 <= x"000A";
end if;
end if;
end process;
process(f2, div2, rst)
begin
if(rst = '1') then
counter2<= x"0064";
elsif(rising_edge(f2)) then
counter2 <= counter2 - 1;
if(std_logic_vector(counter2) = x"0000") then
counter2 <= x"0064";
end if;
end if;
end process;
process(f3, div3, rst)
begin
if(rst = '1') then
counter3 <= x"03E8";
elsif(rising_edge(f3)) then
counter3 <= counter3 - 1;
if(std_logic_vector(counter3) = x"0000") then
counter3 <= x"03E8";
end if;
end if;
end process;
process(rst, clk)
begin
if(rst = '1') then
int <= "000";
elsif(rising_edge(clk))then
int <= "000";
if(std_logic_vector(counter1) = x"0000") then
if(controller(0) = '1' and inta(0) = '0') then
int(0) <= '1';
inta(0) <= '1';
end if;
else
inta(0) <= '0';
end if;
if(std_logic_vector(counter2) = x"0000") then
if(controller(1) = '1' and inta(1) = '0') then
int(1) <= '1';
inta(1) <= '1';
end if;
else
inta(1) <= '0';
end if;
if(std_logic_vector(counter3) = x"0000") then
if(controller(2) = '1' and inta(2) = '0') then
int(2) <= '1';
inta(2) <= '1';
end if;
else
inta(2) <= '0';
end if;
end if;
end process;
END behavioral; |
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DAHnAwe7U0rkTCXQORy9FD0VKxcyXnWY/eoi5uzhlazrj8hEKjtKQSbzUfoV7xx1s8i22GrBql7D
dw==
`protect end_protected
|
package pack1 is
type ma_t is array(1 downto 0) of bit_vector(1 downto 0);
end pack1;
use work.pack1.all;
entity arraysub is
generic(par1: bit_vector(3 downto 0) := "1111");
end entity;
architecture test of arraysub is
signal s1, s2: ma_t;
begin
s1(1)<=par1(1 downto 0);
s1(0)<=par1(3 downto 2);
s2(1 downto 1) <= ( 0 => par1(3 downto 2) );
s2(0 downto 0) <= ( 0 => par1(1 downto 0) );
process is
begin
wait for 1 ns;
assert s1 = ( "11", "11" );
wait;
end process;
end architecture;
|
package pack1 is
type ma_t is array(1 downto 0) of bit_vector(1 downto 0);
end pack1;
use work.pack1.all;
entity arraysub is
generic(par1: bit_vector(3 downto 0) := "1111");
end entity;
architecture test of arraysub is
signal s1, s2: ma_t;
begin
s1(1)<=par1(1 downto 0);
s1(0)<=par1(3 downto 2);
s2(1 downto 1) <= ( 0 => par1(3 downto 2) );
s2(0 downto 0) <= ( 0 => par1(1 downto 0) );
process is
begin
wait for 1 ns;
assert s1 = ( "11", "11" );
wait;
end process;
end architecture;
|
package pack1 is
type ma_t is array(1 downto 0) of bit_vector(1 downto 0);
end pack1;
use work.pack1.all;
entity arraysub is
generic(par1: bit_vector(3 downto 0) := "1111");
end entity;
architecture test of arraysub is
signal s1, s2: ma_t;
begin
s1(1)<=par1(1 downto 0);
s1(0)<=par1(3 downto 2);
s2(1 downto 1) <= ( 0 => par1(3 downto 2) );
s2(0 downto 0) <= ( 0 => par1(1 downto 0) );
process is
begin
wait for 1 ns;
assert s1 = ( "11", "11" );
wait;
end process;
end architecture;
|
package pack1 is
type ma_t is array(1 downto 0) of bit_vector(1 downto 0);
end pack1;
use work.pack1.all;
entity arraysub is
generic(par1: bit_vector(3 downto 0) := "1111");
end entity;
architecture test of arraysub is
signal s1, s2: ma_t;
begin
s1(1)<=par1(1 downto 0);
s1(0)<=par1(3 downto 2);
s2(1 downto 1) <= ( 0 => par1(3 downto 2) );
s2(0 downto 0) <= ( 0 => par1(1 downto 0) );
process is
begin
wait for 1 ns;
assert s1 = ( "11", "11" );
wait;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 28.11.2013 13:51:50
-- Design Name:
-- Module Name: aeg1500_tb - Behavioral
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado
--
-- Description: test automotive ethernet gateway
-- test one port in a user side loopback
-- the number of test frames and the frames size are arbitrary
----------------------------------------------------------------------------------
entity aeg_tb is
end aeg_tb;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture testbench of aeg_tb is
-- aeg_tb properties
constant NR_TEST_FRAMES : integer := 20; -- number of frames sent
constant FRAME_LENGTH : integer := 64; -- ethernet frame size
constant MAX_FRAME_LENGTH : integer := 1522;
constant PAYLOAD_LENGTH : integer := FRAME_LENGTH - 18;
-- aeg constants
constant RECEIVER_DATA_WIDTH : integer := 8;
constant NR_PORTS : integer := 4;
constant GMII_DATA_WIDTH : integer := 8;
constant TX_IFG_DELAY_WIDTH : integer := 8;
constant PAUSE_VAL_WIDTH : integer := 16;
------------------------------------------------------------------------------
-- Component Declaration for Device Under Test (DUT).
------------------------------------------------------------------------------
component automotive_ethernet_gateway
Generic (
RECEIVER_DATA_WIDTH : integer;
NR_PORTS : integer;
GMII_DATA_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer
);
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- 200MHz clock input from board
clk_in_p : in std_logic;
clk_in_n : in std_logic;
phy_resetn : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic--;
-- Main example design controls
-------------------------------
--reset_error : in std_logic
);
end component;
------------------------------------------------------------------------------
-- types to support frame data
------------------------------------------------------------------------------
-- Tx Data and Data_valid record
type data_typ is record
data : std_logic_vector(7 downto 0); -- data
valid : std_logic; -- data_valid
error : std_logic; -- data_error
end record;
type frame_of_data_typ is array (natural range <>) of data_typ;
-- Tx Data, Data_valid and underrun record
type frame_typ is record
columns : frame_of_data_typ(0 to MAX_FRAME_LENGTH);-- data field
end record;
------------------------------------------------------------------------------
-- Stimulus - Frame data
------------------------------------------------------------------------------
shared variable frame_data : frame_typ;
------------------------------------------------------------------------------
-- CRC engine
------------------------------------------------------------------------------
function calc_crc (data : in std_logic_vector;
fcs : in std_logic_vector)
return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable crc_feedback : std_logic;
begin
crc := not fcs;
for I in 0 to 7 loop
crc_feedback := crc(0) xor data(I);
crc(4 downto 0) := crc(5 downto 1);
crc(5) := crc(6) xor crc_feedback;
crc(7 downto 6) := crc(8 downto 7);
crc(8) := crc(9) xor crc_feedback;
crc(9) := crc(10) xor crc_feedback;
crc(14 downto 10) := crc(15 downto 11);
crc(15) := crc(16) xor crc_feedback;
crc(18 downto 16) := crc(19 downto 17);
crc(19) := crc(20) xor crc_feedback;
crc(20) := crc(21) xor crc_feedback;
crc(21) := crc(22) xor crc_feedback;
crc(22) := crc(23);
crc(23) := crc(24) xor crc_feedback;
crc(24) := crc(25) xor crc_feedback;
crc(25) := crc(26);
crc(26) := crc(27) xor crc_feedback;
crc(27) := crc(28) xor crc_feedback;
crc(28) := crc(29);
crc(29) := crc(30) xor crc_feedback;
crc(30) := crc(31) xor crc_feedback;
crc(31) := crc_feedback;
end loop;
-- return the CRC result
return not crc;
end calc_crc;
------------------------------------------------------------------------------
-- Test Bench signals and constants
------------------------------------------------------------------------------
-- Delay to provide setup and hold timing at the GMII/RGMII.
constant dly : time := 4.8 ns;
constant gtx_period : time := 2.5 ns;
shared variable counter : integer := 0;
-- testbench signals
signal gtx_clk : std_logic;
signal gtx_clkn : std_logic;
signal reset : std_logic := '0';
signal demo_mode_error : std_logic := '0';
signal frames_received : std_logic_vector(7 downto 0) := x"00";
signal mdc : std_logic;
signal mdio : std_logic;
signal mdio_count : unsigned(5 downto 0) := (others => '0');
signal last_mdio : std_logic;
signal mdio_read : std_logic;
signal mdio_addr : std_logic;
signal mdio_fail : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0) := (others => '0');
signal gmii_rx_clk : std_logic;
signal gmii_rx_dv : std_logic := '0';
signal gmii_rx_er : std_logic := '0';
signal gmii_rxd : std_logic_vector(7 downto 0) := (others => '0');
signal mii_tx_clk : std_logic := '0';
-- testbench control signals
signal tx_monitor_finished_1G : boolean := false;
signal management_config_finished : boolean := false;
signal rx_stimulus_finished : boolean := false;
signal send_complete : std_logic := '0';
signal phy_speed : std_logic_vector(1 downto 0) := "10";
signal mac_speed : std_logic_vector(1 downto 0) := "10";
signal update_speed : std_logic := '0';
signal serial_response : std_logic;
signal enable_phy_loopback : std_logic := '0';
begin
------------------------------------------------------------------------------
-- Wire up Device Under Test
------------------------------------------------------------------------------
dut: automotive_ethernet_gateway
Generic map (
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
NR_PORTS => NR_PORTS,
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
TX_IFG_DELAY_WIDTH => TX_IFG_DELAY_WIDTH,
PAUSE_VAL_WIDTH => PAUSE_VAL_WIDTH
)
port map (
-- asynchronous reset
--------------------------------
glbl_rst => reset,
-- 200MHz clock input from board
clk_in_p => gtx_clk,
clk_in_n => gtx_clkn,
phy_resetn => open,
-- GMII Interface
--------------------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
mdc => mdc,
mdio => mdio
);
------------------------------------------------------------------------------
-- If the simulation is still going after delay below
-- then something has gone wrong: terminate with an error
------------------------------------------------------------------------------
p_timebomb : process
begin
wait for 300 us;
assert false
report "ERROR - Simulation running forever!"
severity failure;
end process p_timebomb;
------------------------------------------------------------------------------
-- Clock drivers
------------------------------------------------------------------------------
-- drives input to an MMCM at 200MHz which creates gtx_clk at 125 MHz
p_gtx_clk : process
begin
gtx_clk <= '0';
gtx_clkn <= '1';
wait for 80 ns;
loop
wait for gtx_period;
gtx_clk <= '1';
gtx_clkn <= '0';
wait for gtx_period;
gtx_clk <= '0';
gtx_clkn <= '1';
end loop;
end process p_gtx_clk;
gmii_rx_clk <= gmii_tx_clk;
-----------------------------------------------------------------------------
-- reset process.
-----------------------------------------------------------------------------
p_init : process
procedure mac_reset is
begin
assert false
report "Resetting core..." & cr
severity note;
reset <= '1';
wait for 200 ns;
reset <= '0';
assert false
report "Timing checks are valid" & cr
severity note;
end procedure mac_reset;
procedure init_frame is
variable length_type : std_logic_vector(15 downto 0);
variable data_byte : std_logic_vector(15 downto 0);
variable i : integer;
begin
frame_data.columns(0) := ( DATA => X"12", VALID => '1', ERROR => '0'); -- Destination Address (DA)'),
frame_data.columns(1) := ( DATA => X"34", VALID => '1', ERROR => '0');
frame_data.columns(2) := ( DATA => X"56", VALID => '1', ERROR => '0');
frame_data.columns(3) := ( DATA => X"78", VALID => '1', ERROR => '0');
frame_data.columns(4) := ( DATA => X"00", VALID => '1', ERROR => '0');
frame_data.columns(5) := ( DATA => X"00", VALID => '1', ERROR => '0');
frame_data.columns(6) := ( DATA => X"5A", VALID => '1', ERROR => '0'); -- Source Address (5A)
frame_data.columns(7) := ( DATA => X"02", VALID => '1', ERROR => '0');
frame_data.columns(8) := ( DATA => X"03", VALID => '1', ERROR => '0');
frame_data.columns(9) := ( DATA => X"04", VALID => '1', ERROR => '0');
frame_data.columns(10) := ( DATA => X"05", VALID => '1', ERROR => '0');
frame_data.columns(11) := ( DATA => X"06", VALID => '1', ERROR => '0');
length_type := std_logic_vector(to_unsigned(PAYLOAD_LENGTH,length_type'length));
frame_data.columns(12) := ( DATA => length_type(15 downto 8), VALID => '1', ERROR => '0');
frame_data.columns(13) := ( DATA => length_type(7 downto 0), VALID => '1', ERROR => '0'); -- Length/Type
i := 14;
while i < PAYLOAD_LENGTH + 14 loop
data_byte := std_logic_vector(to_unsigned(i-13 ,data_byte'length));
frame_data.columns(i) := ( DATA => data_byte(7 downto 0), VALID => '1', ERROR => '0'); -- Payload
i := i+1;
end loop;
while i < 60 loop
frame_data.columns(i) := ( DATA => X"00", VALID => '1', ERROR => '0'); -- Padding
i := i+1;
end loop;
frame_data.columns(i) := ( DATA => X"00", VALID => '0', ERROR => '0'); -- Stop writing
end procedure init_frame;
begin
assert false
report "Timing checks are not valid" & cr
severity note;
mac_speed <= "10";
phy_speed <= "10";
update_speed <= '0';
wait for 800 ns;
mac_reset;
init_frame;
management_config_finished <= true;
wait;
end process p_init;
------------------------------------------------------------------------------
-- Stimulus process. This process will inject frames of data into the
-- PHY side of the receiver.
------------------------------------------------------------------------------
p_stimulus : process
----------------------------------------------------------
-- Procedure to inject a frame into the receiver at 1Gb/s
----------------------------------------------------------
procedure send_frame_1g is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd <= "01010101" after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd <= "11010101" after dly;
gmii_rx_dv <= '1' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := 0;
gmii_rxd <= frame_data.columns(current_col).data after dly;
gmii_rx_dv <= frame_data.columns(current_col).valid after dly;
gmii_rx_er <= frame_data.columns(current_col).error after dly;
fcs := calc_crc(frame_data.columns(current_col).data, fcs);
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data.columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd <= frame_data.columns(current_col).data after dly;
gmii_rx_dv <= frame_data.columns(current_col).valid after dly;
gmii_rx_er <= frame_data.columns(current_col).error after dly;
fcs := calc_crc(frame_data.columns(current_col).data, fcs);
current_col := current_col + 1;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd <= fcs(((8*j)+7) downto (8*j)) after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Clear the data lines.
gmii_rxd <= (others => '0') after dly;
gmii_rx_dv <= '0' after dly;
-- Adding the minimum Interframe gap for a receiver (8 idles)
for j in 0 to 7 loop
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
end send_frame_1g;
begin
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
-- inject 256 frames back to back
for dest_address6 in 0 to NR_TEST_FRAMES-1 loop
frame_data.columns(5).data := std_logic_vector(to_unsigned(dest_address6, frame_data.columns(5).data'length));
if dest_address6 = NR_TEST_FRAMES-3 then
frame_data.columns(40).error := '1';
else
frame_data.columns(40).error := '0';
end if;
send_frame_1g;
end loop;
send_complete <= '1';
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
rx_stimulus_finished <= true;
-- Our work here is done
if (demo_mode_error = '0') then
assert false
report "Test completed successfully"
severity note;
end if;
assert false
report "Simulation stopped"
severity failure;
end process p_stimulus;
------------------------------------------------------------------------------
-- Monitor process. This process checks the data coming out of the
-- transmitter to make sure that it matches that inserted into the
-- receiver.
------------------------------------------------------------------------------
p_monitor : process
procedure check_frame_1g(dest_address6 : integer) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
variable addr_comp_reg : std_logic_vector(95 downto 0);
begin
-- Reset the FCS calculation
fcs := (others => '0');
while current_col < 12 loop
addr_comp_reg((current_col*8 + 7) downto (current_col*8)) := frame_data.columns(current_col).data;
current_col := current_col + 1;
end loop;
current_col := 0;
-- Parse over the preamble field
while gmii_tx_en /= '1' or gmii_txd = "01010101" loop
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd /= "11010101") then
demo_mode_error <= '1';
assert false
report "SFD not present" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
-- frame has started, loop over columns of frame
while ((frame_data.columns(current_col).valid)='1') loop
if gmii_tx_en /= frame_data.columns(current_col).valid then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect" & cr
severity error;
end if;
if gmii_tx_en = '1' then
-- The transmitted Destination Address was the Source Address of the injected frame
if current_col < 5 then
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Destination Address field" & cr
severity error;
end if;
elsif current_col = 5 then
if gmii_txd(7 downto 0) /= std_logic_vector(to_unsigned(dest_address6, gmii_txd'length)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during 6th Destination Address field" & cr
severity error;
end if;
elsif current_col >= 6 and current_col < 12 then
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Source Address field" & cr
severity error;
end if;
-- for remainder of frame
else
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect" & cr
severity error;
end if;
end if;
end if;
-- calculate expected crc for the frame
fcs := calc_crc(gmii_txd, fcs);
-- wait for next column of data
current_col := current_col + 1;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en = '0' then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect during FCS field" & cr
severity error;
end if;
if gmii_txd /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during FCS field" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- j
end check_frame_1g;
begin -- process p_monitor
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until management_config_finished;
wait for 100 ns;
for dest_address6 in 0 to NR_TEST_FRAMES-1 loop
if dest_address6 mod 4 /= 3 and dest_address6 /= NR_TEST_FRAMES-3 then
check_frame_1g(dest_address6);
counter := counter + 1;
frames_received <= std_logic_vector(to_unsigned(counter,frames_received'length));
end if;
end loop;
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_1G <= true;
wait;
end process p_monitor;
end testbench;
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 28.11.2013 13:51:50
-- Design Name:
-- Module Name: aeg1500_tb - Behavioral
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado
--
-- Description: test automotive ethernet gateway
-- test one port in a user side loopback
-- the number of test frames and the frames size are arbitrary
----------------------------------------------------------------------------------
entity aeg_tb is
end aeg_tb;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture testbench of aeg_tb is
-- aeg_tb properties
constant NR_TEST_FRAMES : integer := 20; -- number of frames sent
constant FRAME_LENGTH : integer := 64; -- ethernet frame size
constant MAX_FRAME_LENGTH : integer := 1522;
constant PAYLOAD_LENGTH : integer := FRAME_LENGTH - 18;
-- aeg constants
constant RECEIVER_DATA_WIDTH : integer := 8;
constant NR_PORTS : integer := 4;
constant GMII_DATA_WIDTH : integer := 8;
constant TX_IFG_DELAY_WIDTH : integer := 8;
constant PAUSE_VAL_WIDTH : integer := 16;
------------------------------------------------------------------------------
-- Component Declaration for Device Under Test (DUT).
------------------------------------------------------------------------------
component automotive_ethernet_gateway
Generic (
RECEIVER_DATA_WIDTH : integer;
NR_PORTS : integer;
GMII_DATA_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer
);
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- 200MHz clock input from board
clk_in_p : in std_logic;
clk_in_n : in std_logic;
phy_resetn : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic--;
-- Main example design controls
-------------------------------
--reset_error : in std_logic
);
end component;
------------------------------------------------------------------------------
-- types to support frame data
------------------------------------------------------------------------------
-- Tx Data and Data_valid record
type data_typ is record
data : std_logic_vector(7 downto 0); -- data
valid : std_logic; -- data_valid
error : std_logic; -- data_error
end record;
type frame_of_data_typ is array (natural range <>) of data_typ;
-- Tx Data, Data_valid and underrun record
type frame_typ is record
columns : frame_of_data_typ(0 to MAX_FRAME_LENGTH);-- data field
end record;
------------------------------------------------------------------------------
-- Stimulus - Frame data
------------------------------------------------------------------------------
shared variable frame_data : frame_typ;
------------------------------------------------------------------------------
-- CRC engine
------------------------------------------------------------------------------
function calc_crc (data : in std_logic_vector;
fcs : in std_logic_vector)
return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable crc_feedback : std_logic;
begin
crc := not fcs;
for I in 0 to 7 loop
crc_feedback := crc(0) xor data(I);
crc(4 downto 0) := crc(5 downto 1);
crc(5) := crc(6) xor crc_feedback;
crc(7 downto 6) := crc(8 downto 7);
crc(8) := crc(9) xor crc_feedback;
crc(9) := crc(10) xor crc_feedback;
crc(14 downto 10) := crc(15 downto 11);
crc(15) := crc(16) xor crc_feedback;
crc(18 downto 16) := crc(19 downto 17);
crc(19) := crc(20) xor crc_feedback;
crc(20) := crc(21) xor crc_feedback;
crc(21) := crc(22) xor crc_feedback;
crc(22) := crc(23);
crc(23) := crc(24) xor crc_feedback;
crc(24) := crc(25) xor crc_feedback;
crc(25) := crc(26);
crc(26) := crc(27) xor crc_feedback;
crc(27) := crc(28) xor crc_feedback;
crc(28) := crc(29);
crc(29) := crc(30) xor crc_feedback;
crc(30) := crc(31) xor crc_feedback;
crc(31) := crc_feedback;
end loop;
-- return the CRC result
return not crc;
end calc_crc;
------------------------------------------------------------------------------
-- Test Bench signals and constants
------------------------------------------------------------------------------
-- Delay to provide setup and hold timing at the GMII/RGMII.
constant dly : time := 4.8 ns;
constant gtx_period : time := 2.5 ns;
shared variable counter : integer := 0;
-- testbench signals
signal gtx_clk : std_logic;
signal gtx_clkn : std_logic;
signal reset : std_logic := '0';
signal demo_mode_error : std_logic := '0';
signal frames_received : std_logic_vector(7 downto 0) := x"00";
signal mdc : std_logic;
signal mdio : std_logic;
signal mdio_count : unsigned(5 downto 0) := (others => '0');
signal last_mdio : std_logic;
signal mdio_read : std_logic;
signal mdio_addr : std_logic;
signal mdio_fail : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0) := (others => '0');
signal gmii_rx_clk : std_logic;
signal gmii_rx_dv : std_logic := '0';
signal gmii_rx_er : std_logic := '0';
signal gmii_rxd : std_logic_vector(7 downto 0) := (others => '0');
signal mii_tx_clk : std_logic := '0';
-- testbench control signals
signal tx_monitor_finished_1G : boolean := false;
signal management_config_finished : boolean := false;
signal rx_stimulus_finished : boolean := false;
signal send_complete : std_logic := '0';
signal phy_speed : std_logic_vector(1 downto 0) := "10";
signal mac_speed : std_logic_vector(1 downto 0) := "10";
signal update_speed : std_logic := '0';
signal serial_response : std_logic;
signal enable_phy_loopback : std_logic := '0';
begin
------------------------------------------------------------------------------
-- Wire up Device Under Test
------------------------------------------------------------------------------
dut: automotive_ethernet_gateway
Generic map (
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
NR_PORTS => NR_PORTS,
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
TX_IFG_DELAY_WIDTH => TX_IFG_DELAY_WIDTH,
PAUSE_VAL_WIDTH => PAUSE_VAL_WIDTH
)
port map (
-- asynchronous reset
--------------------------------
glbl_rst => reset,
-- 200MHz clock input from board
clk_in_p => gtx_clk,
clk_in_n => gtx_clkn,
phy_resetn => open,
-- GMII Interface
--------------------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
mdc => mdc,
mdio => mdio
);
------------------------------------------------------------------------------
-- If the simulation is still going after delay below
-- then something has gone wrong: terminate with an error
------------------------------------------------------------------------------
p_timebomb : process
begin
wait for 300 us;
assert false
report "ERROR - Simulation running forever!"
severity failure;
end process p_timebomb;
------------------------------------------------------------------------------
-- Clock drivers
------------------------------------------------------------------------------
-- drives input to an MMCM at 200MHz which creates gtx_clk at 125 MHz
p_gtx_clk : process
begin
gtx_clk <= '0';
gtx_clkn <= '1';
wait for 80 ns;
loop
wait for gtx_period;
gtx_clk <= '1';
gtx_clkn <= '0';
wait for gtx_period;
gtx_clk <= '0';
gtx_clkn <= '1';
end loop;
end process p_gtx_clk;
gmii_rx_clk <= gmii_tx_clk;
-----------------------------------------------------------------------------
-- reset process.
-----------------------------------------------------------------------------
p_init : process
procedure mac_reset is
begin
assert false
report "Resetting core..." & cr
severity note;
reset <= '1';
wait for 200 ns;
reset <= '0';
assert false
report "Timing checks are valid" & cr
severity note;
end procedure mac_reset;
procedure init_frame is
variable length_type : std_logic_vector(15 downto 0);
variable data_byte : std_logic_vector(15 downto 0);
variable i : integer;
begin
frame_data.columns(0) := ( DATA => X"12", VALID => '1', ERROR => '0'); -- Destination Address (DA)'),
frame_data.columns(1) := ( DATA => X"34", VALID => '1', ERROR => '0');
frame_data.columns(2) := ( DATA => X"56", VALID => '1', ERROR => '0');
frame_data.columns(3) := ( DATA => X"78", VALID => '1', ERROR => '0');
frame_data.columns(4) := ( DATA => X"00", VALID => '1', ERROR => '0');
frame_data.columns(5) := ( DATA => X"00", VALID => '1', ERROR => '0');
frame_data.columns(6) := ( DATA => X"5A", VALID => '1', ERROR => '0'); -- Source Address (5A)
frame_data.columns(7) := ( DATA => X"02", VALID => '1', ERROR => '0');
frame_data.columns(8) := ( DATA => X"03", VALID => '1', ERROR => '0');
frame_data.columns(9) := ( DATA => X"04", VALID => '1', ERROR => '0');
frame_data.columns(10) := ( DATA => X"05", VALID => '1', ERROR => '0');
frame_data.columns(11) := ( DATA => X"06", VALID => '1', ERROR => '0');
length_type := std_logic_vector(to_unsigned(PAYLOAD_LENGTH,length_type'length));
frame_data.columns(12) := ( DATA => length_type(15 downto 8), VALID => '1', ERROR => '0');
frame_data.columns(13) := ( DATA => length_type(7 downto 0), VALID => '1', ERROR => '0'); -- Length/Type
i := 14;
while i < PAYLOAD_LENGTH + 14 loop
data_byte := std_logic_vector(to_unsigned(i-13 ,data_byte'length));
frame_data.columns(i) := ( DATA => data_byte(7 downto 0), VALID => '1', ERROR => '0'); -- Payload
i := i+1;
end loop;
while i < 60 loop
frame_data.columns(i) := ( DATA => X"00", VALID => '1', ERROR => '0'); -- Padding
i := i+1;
end loop;
frame_data.columns(i) := ( DATA => X"00", VALID => '0', ERROR => '0'); -- Stop writing
end procedure init_frame;
begin
assert false
report "Timing checks are not valid" & cr
severity note;
mac_speed <= "10";
phy_speed <= "10";
update_speed <= '0';
wait for 800 ns;
mac_reset;
init_frame;
management_config_finished <= true;
wait;
end process p_init;
------------------------------------------------------------------------------
-- Stimulus process. This process will inject frames of data into the
-- PHY side of the receiver.
------------------------------------------------------------------------------
p_stimulus : process
----------------------------------------------------------
-- Procedure to inject a frame into the receiver at 1Gb/s
----------------------------------------------------------
procedure send_frame_1g is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd <= "01010101" after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd <= "11010101" after dly;
gmii_rx_dv <= '1' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := 0;
gmii_rxd <= frame_data.columns(current_col).data after dly;
gmii_rx_dv <= frame_data.columns(current_col).valid after dly;
gmii_rx_er <= frame_data.columns(current_col).error after dly;
fcs := calc_crc(frame_data.columns(current_col).data, fcs);
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data.columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd <= frame_data.columns(current_col).data after dly;
gmii_rx_dv <= frame_data.columns(current_col).valid after dly;
gmii_rx_er <= frame_data.columns(current_col).error after dly;
fcs := calc_crc(frame_data.columns(current_col).data, fcs);
current_col := current_col + 1;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd <= fcs(((8*j)+7) downto (8*j)) after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Clear the data lines.
gmii_rxd <= (others => '0') after dly;
gmii_rx_dv <= '0' after dly;
-- Adding the minimum Interframe gap for a receiver (8 idles)
for j in 0 to 7 loop
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
end send_frame_1g;
begin
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
-- inject 256 frames back to back
for dest_address6 in 0 to NR_TEST_FRAMES-1 loop
frame_data.columns(5).data := std_logic_vector(to_unsigned(dest_address6, frame_data.columns(5).data'length));
if dest_address6 = NR_TEST_FRAMES-3 then
frame_data.columns(40).error := '1';
else
frame_data.columns(40).error := '0';
end if;
send_frame_1g;
end loop;
send_complete <= '1';
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
rx_stimulus_finished <= true;
-- Our work here is done
if (demo_mode_error = '0') then
assert false
report "Test completed successfully"
severity note;
end if;
assert false
report "Simulation stopped"
severity failure;
end process p_stimulus;
------------------------------------------------------------------------------
-- Monitor process. This process checks the data coming out of the
-- transmitter to make sure that it matches that inserted into the
-- receiver.
------------------------------------------------------------------------------
p_monitor : process
procedure check_frame_1g(dest_address6 : integer) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
variable addr_comp_reg : std_logic_vector(95 downto 0);
begin
-- Reset the FCS calculation
fcs := (others => '0');
while current_col < 12 loop
addr_comp_reg((current_col*8 + 7) downto (current_col*8)) := frame_data.columns(current_col).data;
current_col := current_col + 1;
end loop;
current_col := 0;
-- Parse over the preamble field
while gmii_tx_en /= '1' or gmii_txd = "01010101" loop
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd /= "11010101") then
demo_mode_error <= '1';
assert false
report "SFD not present" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
-- frame has started, loop over columns of frame
while ((frame_data.columns(current_col).valid)='1') loop
if gmii_tx_en /= frame_data.columns(current_col).valid then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect" & cr
severity error;
end if;
if gmii_tx_en = '1' then
-- The transmitted Destination Address was the Source Address of the injected frame
if current_col < 5 then
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Destination Address field" & cr
severity error;
end if;
elsif current_col = 5 then
if gmii_txd(7 downto 0) /= std_logic_vector(to_unsigned(dest_address6, gmii_txd'length)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during 6th Destination Address field" & cr
severity error;
end if;
elsif current_col >= 6 and current_col < 12 then
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Source Address field" & cr
severity error;
end if;
-- for remainder of frame
else
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect" & cr
severity error;
end if;
end if;
end if;
-- calculate expected crc for the frame
fcs := calc_crc(gmii_txd, fcs);
-- wait for next column of data
current_col := current_col + 1;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en = '0' then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect during FCS field" & cr
severity error;
end if;
if gmii_txd /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during FCS field" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- j
end check_frame_1g;
begin -- process p_monitor
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until management_config_finished;
wait for 100 ns;
for dest_address6 in 0 to NR_TEST_FRAMES-1 loop
if dest_address6 mod 4 /= 3 and dest_address6 /= NR_TEST_FRAMES-3 then
check_frame_1g(dest_address6);
counter := counter + 1;
frames_received <= std_logic_vector(to_unsigned(counter,frames_received'length));
end if;
end loop;
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_1G <= true;
wait;
end process p_monitor;
end testbench;
|
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