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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57632)
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`protect end_protected
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`protect end_protected
|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57632)
`protect data_block
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VYEsBss=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57632)
`protect data_block
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`protect end_protected
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`protect end_protected
|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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VYEsBss=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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b42uF+Colw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57632)
`protect data_block
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`protect end_protected
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`protect end_protected
|
`protect begin_protected
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`protect data_block
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`protect end_protected
|
-- Copyright (c) 2015 by David Goncalves <[email protected]>
-- See LICENCE.txt for details
--
-- Signal conversion and debounce
library UNISIM;
library IEEE;
use UNISIM.VComponents.all;
use IEEE.STD_LOGIC_1164.all;
entity io_pads is
port (
clk : in STD_LOGIC;
clk_i : out STD_LOGIC;
lvds_p : in STD_LOGIC;
lvds_n : in STD_LOGIC;
comp_i : out STD_LOGIC;
reset : in STD_LOGIC;
reset_i : out STD_LOGIC;
adc_fb : out STD_LOGIC;
adc_fb_i : in STD_LOGIC;
dac_out : out STD_LOGIC;
dac_out_i : in STD_LOGIC;
test : inout STD_LOGIC_VECTOR(7 downto 0);
test_i : inout STD_LOGIC_VECTOR(7 downto 0)
);
end io_pads;
architecture RTL of io_pads is
component IBUFDS is
generic (IOSTANDARD : string);
port (
I : in STD_LOGIC;
IB : in STD_LOGIC;
O : out STD_LOGIC
);
end component;
begin
-- Converts difference between LVDS inputs into a STD_LOGIC signal
LVDS_buf : IBUFDS
generic map(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "LVDS25"
)
port map(
I => lvds_p,
IB => lvds_n,
O => comp_i
);
-- signal pass-throughs
clk_i <= clk;
reset_i <= reset;
adc_fb_i <= adc_fb;
dac_out_i <= dac_out;
test_i <= test;
end RTL;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
entity aclkout is
port(
clk : in std_logic;
ddr_clk : out std_logic;
ddr_clkn: out std_logic
);
end;
architecture rtl of aclkout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component cycloneiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
port(
i : in std_logic := '0';
oe : in std_logic := '1';
--devoe : in std_logic := '1';
o : out std_logic;
obar : out std_logic--;
--seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal clk_reg, clkn_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
out_reg0 : cycloneiii_ddio_out
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => vcc,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => clk_reg,
dfflo => open,
dffhi => open--,
--devclrn => vcc,
--devpor => vcc
);
outn_reg0 : cycloneiii_ddio_out
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => vcc,
datainhi => gnd(0),
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => clkn_reg,
dfflo => open,
dffhi => open--,
--devclrn => vcc,
--devpor => vcc
);
out_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => clk_reg,
oe => vcc,
--devoe => vcc,
o => ddr_clk,
obar => open
--seriesterminationcontrol => gnd,
);
outn_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => clkn_reg,
oe => vcc,
--devoe => vcc,
o => ddr_clkn,
obar => open
--seriesterminationcontrol => gnd,
);
end;
|
architecture rtl of fifo is
signal rd_en : std_logic;
signal wr_en : std_logic;
begin
end architecture rtl;
architecture rtl of fifo is
signal rd_en:std_logic;
signal wr_en:std_logic;
begin
end architecture rtl;
architecture rtl of fifo is
signal rd_en : std_logic;
signal wr_en : std_logic;
begin
end architecture rtl;
|
architecture rtl of fifo is
signal rd_en : std_logic;
signal wr_en : std_logic;
begin
end architecture rtl;
architecture rtl of fifo is
signal rd_en:std_logic;
signal wr_en:std_logic;
begin
end architecture rtl;
architecture rtl of fifo is
signal rd_en : std_logic;
signal wr_en : std_logic;
begin
end architecture rtl;
|
-- $Id: tb_cmoda7_sram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_cmoda7_sram - sim
-- Description: Test bench for cmoda7 (base+sram)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_cmoda7_core
-- serport/tb/serport_master_tb
-- cmoda7_sram_aif [UUT]
-- simlib/simbididly
-- bplib/issi/is61wv5128bll
--
-- To test: generic, any cmoda7_sram_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2016.4-2018.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.0.1 use sfs_gsim_core
-- 2017-06-04 906 1.0 Initial version (derived from tb_nexys4_cram)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.cmoda7lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_cmoda7_sram is
end tb_cmoda7_sram;
architecture sim of tb_cmoda7_sram is
signal CLKOSC : slbit := '0'; -- board clock (12 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_BTN : slv2 := (others=>'0');
signal O_LED : slv2 := (others=>'0');
signal O_RGBLED0_N : slv3 := (others=>'0');
signal TB_MEM_CE_N : slbit := '1';
signal TB_MEM_WE_N : slbit := '1';
signal TB_MEM_OE_N : slbit := '1';
signal TB_MEM_ADDR : slv19 := (others=>'Z');
signal TB_MEM_DATA : slv8 := (others=>'0');
signal MM_MEM_CE_N : slbit := '1';
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADDR : slv19 := (others=>'Z');
signal MM_MEM_DATA : slv8 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 83.333 ns;
constant clock_offset : Delay_length := 2000 ns;
constant pcb_delay : Delay_length := 1 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
C7CORE : entity work.tb_cmoda7_core
port map (
I_BTN => I_BTN
);
UUT : cmoda7_sram_aif
port map (
I_CLK12 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_BTN => I_BTN,
O_LED => O_LED,
O_RGBLED0_N => O_RGBLED0_N,
O_MEM_CE_N => TB_MEM_CE_N,
O_MEM_WE_N => TB_MEM_WE_N,
O_MEM_OE_N => TB_MEM_OE_N,
O_MEM_ADDR => TB_MEM_ADDR,
IO_MEM_DATA => TB_MEM_DATA
);
MM_MEM_CE_N <= TB_MEM_CE_N after pcb_delay;
MM_MEM_WE_N <= TB_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= TB_MEM_OE_N after pcb_delay;
MM_MEM_ADDR <= TB_MEM_ADDR after pcb_delay;
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 8)
port map (
A => TB_MEM_DATA,
B => MM_MEM_DATA);
MEM : entity work.is61wv5128bll
port map (
CE_N => MM_MEM_CE_N,
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
--
-- Notes on portsel and XON control:
-- - most cmoda7 designs will use hardwired XON=1
-- - but some (especially basis tests) might not use flow control
-- - that's why XON flow control must be optional and configurable !
--
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1940.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01940ent IS
END c07s02b01x00p01n04i01940ent;
ARCHITECTURE c07s02b01x00p01n04i01940arch OF c07s02b01x00p01n04i01940ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a nor b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01940 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01940arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1940.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01940ent IS
END c07s02b01x00p01n04i01940ent;
ARCHITECTURE c07s02b01x00p01n04i01940arch OF c07s02b01x00p01n04i01940ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a nor b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01940 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01940arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1940.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01940ent IS
END c07s02b01x00p01n04i01940ent;
ARCHITECTURE c07s02b01x00p01n04i01940arch OF c07s02b01x00p01n04i01940ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a nor b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01940 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01940arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY DCDPRAM16x1280WC IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END DCDPRAM16x1280WC;
ARCHITECTURE DCDPRAM16x1280WC_arch OF DCDPRAM16x1280WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DCDPRAM16x1280WC_arch : ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=DCDPRAM16x1280WC.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=1280,C_READ_DEPTH_A=1280,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=1280,C_READ_DEPTH_B=1280,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.7744999999999997 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "DCDPRAM16x1280WC.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 1280,
C_READ_DEPTH_A => 1280,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 1280,
C_READ_DEPTH_B => 1280,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.7744999999999997 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END DCDPRAM16x1280WC_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY DCDPRAM16x1280WC IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END DCDPRAM16x1280WC;
ARCHITECTURE DCDPRAM16x1280WC_arch OF DCDPRAM16x1280WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DCDPRAM16x1280WC_arch : ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=DCDPRAM16x1280WC.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=1280,C_READ_DEPTH_A=1280,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=1280,C_READ_DEPTH_B=1280,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.7744999999999997 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "DCDPRAM16x1280WC.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 1280,
C_READ_DEPTH_A => 1280,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 1280,
C_READ_DEPTH_B => 1280,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.7744999999999997 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END DCDPRAM16x1280WC_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY DCDPRAM16x1280WC IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END DCDPRAM16x1280WC;
ARCHITECTURE DCDPRAM16x1280WC_arch OF DCDPRAM16x1280WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DCDPRAM16x1280WC_arch : ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=DCDPRAM16x1280WC.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=1280,C_READ_DEPTH_A=1280,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=1280,C_READ_DEPTH_B=1280,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.7744999999999997 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "DCDPRAM16x1280WC.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 1280,
C_READ_DEPTH_A => 1280,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 1280,
C_READ_DEPTH_B => 1280,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.7744999999999997 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END DCDPRAM16x1280WC_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY DCDPRAM16x1280WC IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END DCDPRAM16x1280WC;
ARCHITECTURE DCDPRAM16x1280WC_arch OF DCDPRAM16x1280WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DCDPRAM16x1280WC_arch : ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=DCDPRAM16x1280WC.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=1280,C_READ_DEPTH_A=1280,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=1280,C_READ_DEPTH_B=1280,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.7744999999999997 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "DCDPRAM16x1280WC.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 1280,
C_READ_DEPTH_A => 1280,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 1280,
C_READ_DEPTH_B => 1280,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.7744999999999997 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END DCDPRAM16x1280WC_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY DCDPRAM16x1280WC IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END DCDPRAM16x1280WC;
ARCHITECTURE DCDPRAM16x1280WC_arch OF DCDPRAM16x1280WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DCDPRAM16x1280WC_arch : ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=DCDPRAM16x1280WC.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=1280,C_READ_DEPTH_A=1280,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=1280,C_READ_DEPTH_B=1280,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.7744999999999997 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "DCDPRAM16x1280WC.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 1280,
C_READ_DEPTH_A => 1280,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 1280,
C_READ_DEPTH_B => 1280,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.7744999999999997 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END DCDPRAM16x1280WC_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY DCDPRAM16x1280WC IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END DCDPRAM16x1280WC;
ARCHITECTURE DCDPRAM16x1280WC_arch OF DCDPRAM16x1280WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DCDPRAM16x1280WC_arch : ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=DCDPRAM16x1280WC.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=1280,C_READ_DEPTH_A=1280,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=1280,C_READ_DEPTH_B=1280,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.7744999999999997 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "DCDPRAM16x1280WC.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 1280,
C_READ_DEPTH_A => 1280,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 1280,
C_READ_DEPTH_B => 1280,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.7744999999999997 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END DCDPRAM16x1280WC_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY DCDPRAM16x1280WC IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END DCDPRAM16x1280WC;
ARCHITECTURE DCDPRAM16x1280WC_arch OF DCDPRAM16x1280WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DCDPRAM16x1280WC_arch : ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=DCDPRAM16x1280WC.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=1280,C_READ_DEPTH_A=1280,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=1280,C_READ_DEPTH_B=1280,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.7744999999999997 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "DCDPRAM16x1280WC.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 1280,
C_READ_DEPTH_A => 1280,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 1280,
C_READ_DEPTH_B => 1280,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.7744999999999997 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END DCDPRAM16x1280WC_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY DCDPRAM16x1280WC IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END DCDPRAM16x1280WC;
ARCHITECTURE DCDPRAM16x1280WC_arch OF DCDPRAM16x1280WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DCDPRAM16x1280WC_arch : ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DCDPRAM16x1280WC_arch: ARCHITECTURE IS "DCDPRAM16x1280WC,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=DCDPRAM16x1280WC.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=1280,C_READ_DEPTH_A=1280,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=1280,C_READ_DEPTH_B=1280,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.7744999999999997 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "DCDPRAM16x1280WC.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 1280,
C_READ_DEPTH_A => 1280,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 1280,
C_READ_DEPTH_B => 1280,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.7744999999999997 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END DCDPRAM16x1280WC_arch;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Simple Actel RAM and pad component declarations
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package components is
-- Axcellerator rams
component RAM64K36
port(
WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10,
WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6,
WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19,
WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32,
WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK,
RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10,
RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic;
RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13,
RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26,
RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic);
end component;
attribute syn_black_box : boolean;
attribute syn_black_box of RAM64K36 : component is true;
attribute syn_tco1 : string;
attribute syn_tco2 : string;
attribute syn_tco1 of RAM64K36 : component is
"RCLK->RD0,RD1,RD2,RD3,RD4,RD5,RD6,RD7,RD8,RD9,RD10,RD11,RD12,RD13,RD14,RD15,RD16,RD17,RD18,RD19,RD20,RD21,RD22,RD23,RD24,RD25,RD26,RD27,RD28,RD29,RD30,RD31,RD32,RD33,RD34,RD35 = 4.0";
-- Buffers
component inbuf_lvds port(Y : out std_logic; PADP : in std_logic; PADN : in std_logic); end component;
component outbuf_lvds port(D : in std_logic; PADP : out std_logic; PADN : out std_logic); end component;
component hclkbuf
port( pad : in std_logic; y : out std_logic); end component;
component clkbuf port(pad : in std_logic; y : out std_logic); end component;
component inbuf port(pad :in std_logic; y : out std_logic); end component;
component bibuf port(
d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end component;
component outbuf port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_8 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_12 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_16 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_24 port(d : in std_logic; pad : out std_logic); end component;
component tribuff port(d, e : in std_logic; pad : out std_logic); end component;
component hclkint port(a : in std_ulogic; y : out std_ulogic); end component;
component clkint port(a : in std_ulogic; y : out std_ulogic); end component;
component hclkbuf_pci
port( pad : in std_logic; y : out std_logic); end component;
component clkbuf_pci port(pad : in std_logic; y : out std_logic); end component;
component inbuf_pci port(pad :in std_logic; y : out std_logic); end component;
attribute syn_tpd11 : string;
attribute syn_tpd11 of inbuf_pci : component is "pad -> y = 2.0";
component bibuf_pci port(
d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end component;
attribute syn_tpd12 : string;
attribute syn_tpd12 of bibuf_pci : component is "pad -> y = 2.0";
component outbuf_pci port(d : in std_logic; pad : out std_logic); end component;
attribute syn_tpd13 : string;
attribute syn_tpd13 of outbuf_pci : component is "d -> pad = 2.0";
component tribuff_pci port(d, e : in std_logic; pad : out std_logic); end component;
attribute syn_tpd14 : string;
attribute syn_tpd14 of tribuff_pci : component is "d,e -> pad = 2.0";
-- 1553 -------------------------------
component add1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end component add1;
component and2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component and2;
component and2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component and2a;
component and2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component and2b;
component and3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3;
component and3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3a;
component and3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3b;
component and3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3c;
component and4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4;
component and4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4a;
component and4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4b;
component and4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4c;
component buff is
port(
a : in std_logic;
y : out std_logic);
end component buff;
component cm8 is
port(
d0 : in std_logic;
d1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
s00 : in std_logic;
s01 : in std_logic;
s10 : in std_logic;
s11 : in std_logic;
y : out std_logic);
end component cm8;
component cm8inv is
port(
a : in std_logic;
y : out std_logic);
end component cm8inv;
component df1 is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end component df1;
component dfc1b is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfc1b;
component dfc1c is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfc1c;
component dfc1d is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfc1d;
component dfe1b is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
q : out std_logic);
end component dfe1b;
component dfe3c is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfe3c;
component dfe4f is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfe4f;
component dfp1 is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfp1;
component dfp1b is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfp1b;
component dfp1d is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfp1d;
component dfm
port(
clk : in std_logic;
s : in std_logic;
a : in std_logic;
b : in std_logic;
q : out std_logic);
end component;
component gnd is
port(
y : out std_logic);
end component gnd;
component inv is
port(
a : in std_logic;
y : out std_logic);
end component inv;
component nand4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component nand4;
component or2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component or2;
component or2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component or2a;
component or2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component or2b;
component or3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3;
component or3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3a;
component or3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3b;
component or3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3c;
component or4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4;
component or4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4a;
component or4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4b;
component or4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4c;
component or4d is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4d;
component sub1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end component sub1;
component vcc is
port(
y : out std_logic);
end component vcc;
component xa1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component xa1;
component xnor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component xnor2;
component xor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component xor2;
component xor4 is
port(a,b,c,d : in std_logic;
y : out std_logic);
end component xor4;
component mx2
port(
a : in std_logic;
s : in std_logic;
b : in std_logic;
y : out std_logic);
end component;
component ax1c
port(
a: in std_logic;
b: in std_logic;
c: in std_logic;
y: out std_logic);
end component;
component df1b
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end component;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Simple Actel RAM and pad component declarations
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package components is
-- Axcellerator rams
component RAM64K36
port(
WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10,
WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6,
WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19,
WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32,
WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK,
RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10,
RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic;
RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13,
RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26,
RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic);
end component;
attribute syn_black_box : boolean;
attribute syn_black_box of RAM64K36 : component is true;
attribute syn_tco1 : string;
attribute syn_tco2 : string;
attribute syn_tco1 of RAM64K36 : component is
"RCLK->RD0,RD1,RD2,RD3,RD4,RD5,RD6,RD7,RD8,RD9,RD10,RD11,RD12,RD13,RD14,RD15,RD16,RD17,RD18,RD19,RD20,RD21,RD22,RD23,RD24,RD25,RD26,RD27,RD28,RD29,RD30,RD31,RD32,RD33,RD34,RD35 = 4.0";
-- Buffers
component inbuf_lvds port(Y : out std_logic; PADP : in std_logic; PADN : in std_logic); end component;
component outbuf_lvds port(D : in std_logic; PADP : out std_logic; PADN : out std_logic); end component;
component hclkbuf
port( pad : in std_logic; y : out std_logic); end component;
component clkbuf port(pad : in std_logic; y : out std_logic); end component;
component inbuf port(pad :in std_logic; y : out std_logic); end component;
component bibuf port(
d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end component;
component outbuf port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_8 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_12 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_16 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_24 port(d : in std_logic; pad : out std_logic); end component;
component tribuff port(d, e : in std_logic; pad : out std_logic); end component;
component hclkint port(a : in std_ulogic; y : out std_ulogic); end component;
component clkint port(a : in std_ulogic; y : out std_ulogic); end component;
component hclkbuf_pci
port( pad : in std_logic; y : out std_logic); end component;
component clkbuf_pci port(pad : in std_logic; y : out std_logic); end component;
component inbuf_pci port(pad :in std_logic; y : out std_logic); end component;
attribute syn_tpd11 : string;
attribute syn_tpd11 of inbuf_pci : component is "pad -> y = 2.0";
component bibuf_pci port(
d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end component;
attribute syn_tpd12 : string;
attribute syn_tpd12 of bibuf_pci : component is "pad -> y = 2.0";
component outbuf_pci port(d : in std_logic; pad : out std_logic); end component;
attribute syn_tpd13 : string;
attribute syn_tpd13 of outbuf_pci : component is "d -> pad = 2.0";
component tribuff_pci port(d, e : in std_logic; pad : out std_logic); end component;
attribute syn_tpd14 : string;
attribute syn_tpd14 of tribuff_pci : component is "d,e -> pad = 2.0";
-- 1553 -------------------------------
component add1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end component add1;
component and2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component and2;
component and2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component and2a;
component and2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component and2b;
component and3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3;
component and3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3a;
component and3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3b;
component and3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3c;
component and4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4;
component and4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4a;
component and4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4b;
component and4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4c;
component buff is
port(
a : in std_logic;
y : out std_logic);
end component buff;
component cm8 is
port(
d0 : in std_logic;
d1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
s00 : in std_logic;
s01 : in std_logic;
s10 : in std_logic;
s11 : in std_logic;
y : out std_logic);
end component cm8;
component cm8inv is
port(
a : in std_logic;
y : out std_logic);
end component cm8inv;
component df1 is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end component df1;
component dfc1b is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfc1b;
component dfc1c is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfc1c;
component dfc1d is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfc1d;
component dfe1b is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
q : out std_logic);
end component dfe1b;
component dfe3c is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfe3c;
component dfe4f is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfe4f;
component dfp1 is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfp1;
component dfp1b is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfp1b;
component dfp1d is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfp1d;
component dfm
port(
clk : in std_logic;
s : in std_logic;
a : in std_logic;
b : in std_logic;
q : out std_logic);
end component;
component gnd is
port(
y : out std_logic);
end component gnd;
component inv is
port(
a : in std_logic;
y : out std_logic);
end component inv;
component nand4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component nand4;
component or2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component or2;
component or2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component or2a;
component or2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component or2b;
component or3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3;
component or3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3a;
component or3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3b;
component or3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3c;
component or4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4;
component or4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4a;
component or4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4b;
component or4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4c;
component or4d is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4d;
component sub1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end component sub1;
component vcc is
port(
y : out std_logic);
end component vcc;
component xa1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component xa1;
component xnor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component xnor2;
component xor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component xor2;
component xor4 is
port(a,b,c,d : in std_logic;
y : out std_logic);
end component xor4;
component mx2
port(
a : in std_logic;
s : in std_logic;
b : in std_logic;
y : out std_logic);
end component;
component ax1c
port(
a: in std_logic;
b: in std_logic;
c: in std_logic;
y: out std_logic);
end component;
component df1b
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end component;
end;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Wed Apr 30 22:30:36 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim
-- /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/clk_adc/clk_adc_funcsim.vhdl
-- Design : clk_adc
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_adcclk_adc_clk_wiz is
port (
clk_in1_p : in STD_LOGIC;
clk_in1_n : in STD_LOGIC;
clk_250Mhz : out STD_LOGIC;
locked : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_adcclk_adc_clk_wiz : entity is "clk_adc_clk_wiz";
end clk_adcclk_adc_clk_wiz;
architecture STRUCTURE of clk_adcclk_adc_clk_wiz is
signal clk_250Mhz_clk_adc : STD_LOGIC;
signal clk_in1_clk_adc : STD_LOGIC;
signal clkfbout_buf_clk_adc : STD_LOGIC;
signal clkfbout_clk_adc : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute box_type : string;
attribute box_type of clkf_buf : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufgds : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufgds : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufgds : label is "AUTO";
attribute box_type of clkin1_ibufgds : label is "PRIMITIVE";
attribute box_type of clkout1_buf : label is "PRIMITIVE";
attribute box_type of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_adc,
O => clkfbout_buf_clk_adc
);
clkin1_ibufgds: unisim.vcomponents.IBUFDS
generic map(
DQS_BIAS => "FALSE",
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1_p,
IB => clk_in1_n,
O => clk_in1_clk_adc
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_250Mhz_clk_adc,
O => clk_250Mhz
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 4.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 4.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 4.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 236.250000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.000000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_adc,
CLKFBOUT => clkfbout_clk_adc,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_clk_adc,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_250Mhz_clk_adc,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6) => '0',
DADDR(5) => '0',
DADDR(4) => '0',
DADDR(3) => '0',
DADDR(2) => '0',
DADDR(1) => '0',
DADDR(0) => '0',
DCLK => '0',
DEN => '0',
DI(15) => '0',
DI(14) => '0',
DI(13) => '0',
DI(12) => '0',
DI(11) => '0',
DI(10) => '0',
DI(9) => '0',
DI(8) => '0',
DI(7) => '0',
DI(6) => '0',
DI(5) => '0',
DI(4) => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_adc is
port (
clk_in1_p : in STD_LOGIC;
clk_in1_n : in STD_LOGIC;
clk_250Mhz : out STD_LOGIC;
locked : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_adc : entity is true;
attribute core_generation_info : string;
attribute core_generation_info of clk_adc : entity is "clk_adc,clk_wiz_v5_1,{component_name=clk_adc,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=4.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_adc;
architecture STRUCTURE of clk_adc is
begin
U0: entity work.clk_adcclk_adc_clk_wiz
port map (
clk_250Mhz => clk_250Mhz,
clk_in1_n => clk_in1_n,
clk_in1_p => clk_in1_p,
locked => locked
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
entity test is
end entity;
architecture a of test is
type RegisterNames is (
LENGTH,
PATTERN_0, PATTERN_1,
COLOR_0, COLOR_1, COLOR_2, COLOR_3
);
type RegisterFile is array(RegisterNames) of std_logic_vector(31 downto 0);
signal Reg : RegisterFile := (
LENGTH => 32d"4",
PATTERN_0 => (
1 downto 0 => "01", -- line 18: can't match string literal with type anonymous enumeration subtype defined at std_logic_1164.v08:89:32
3 downto 2 => "11", -- line 19: can't match string literal with type anonymous enumeration subtype defined at std_logic_1164.v08:89:32
5 downto 4 => "01", -- line 20: can't match string literal with type anonymous enumeration subtype defined at std_logic_1164.v08:89:32
7 downto 6 => "10", -- line 21: can't match string literal with type anonymous enumeration subtype defined at std_logic_1164.v08:89:32
others => '0'
),
COLOR_0 => x"----_00_00",
COLOR_1 => x"----_00_FF",
COLOR_2 => x"----_FF_33",
COLOR_3 => x"----_CC_99",
others => (others => '0')
);
begin
end architecture;
|
architecture ARCH of ENTITY is
begin
a <= sig1 when b = '1' else
sig2 when b = '0' else
sig3;
process
begin
d <= sig1 when b = '1' else--This is a comment
sig2 when c = '0' else -- This is a comment
sig3 when d = '1' else
sig4;
end process;
-- Violations below
a <= sig1 when b = '1' else
sig2 when b = '0' else
sig3;
process
begin
d <= sig1 when b = '1' else--This is a comment
sig2 when c = '0' else -- This is a comment
sig3 when d = '1' else
sig4;
end process;
a <= b when (c = '1')else d;
a <= b when (c = '1'else d;
end architecture ARCH;
|
-- #############################################################################
-- soc_system_top.vhd
--
-- BOARD : DE1-SoC from Terasic
-- Authors : Antonio Carpeño and Mariano Ruiz
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity soc_system_top is
port(
-- -- ADC
-- ADC_CS_n : out std_logic;
-- ADC_DIN : out std_logic;
-- ADC_DOUT : in std_logic;
-- ADC_SCLK : out std_logic;
-- -- Audio
-- AUD_ADCDAT : in std_logic;
-- AUD_ADCLRCK : inout std_logic;
-- AUD_BCLK : inout std_logic;
-- AUD_DACDAT : out std_logic;
-- AUD_DACLRCK : inout std_logic;
-- AUD_XCK : out std_logic;
-- -- CLOCK
CLOCK_50 : in std_logic;
-- CLOCK2_50 : in std_logic;
-- CLOCK3_50 : in std_logic;
-- CLOCK4_50 : in std_logic;
-- -- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_LDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_WE_N : out std_logic;
-- -- I2C for Audio and Video-In
-- FPGA_I2C_SCLK : out std_logic;
-- FPGA_I2C_SDAT : inout std_logic;
-- -- SEG7
HEX0_N : out std_logic_vector(6 downto 0);
HEX1_N : out std_logic_vector(6 downto 0);
HEX2_N : out std_logic_vector(6 downto 0);
HEX3_N : out std_logic_vector(6 downto 0);
HEX4_N : out std_logic_vector(6 downto 0);
HEX5_N : out std_logic_vector(6 downto 0);
-- -- IR
-- IRDA_RXD : in std_logic;
-- IRDA_TXD : out std_logic;
-- -- KEY_N
KEY_N : in std_logic_vector(3 downto 0);
-- -- LED
LEDR : out std_logic_vector(9 downto 0);
-- -- PS2
-- PS2_CLK : inout std_logic;
-- PS2_CLK2 : inout std_logic;
-- PS2_DAT : inout std_logic;
-- PS2_DAT2 : inout std_logic;
-- -- SW
SW : in std_logic_vector(9 downto 0);
-- -- Video-In
-- TD_CLK27 : inout std_logic;
-- TD_DATA : out std_logic_vector(7 downto 0);
-- TD_HS : out std_logic;
-- TD_RESET_N : out std_logic;
-- TD_VS : out std_logic;
-- -- VGA
-- VGA_B : out std_logic_vector(7 downto 0);
-- VGA_BLANK_N : out std_logic;
-- VGA_CLK : out std_logic;
-- VGA_G : out std_logic_vector(7 downto 0);
-- VGA_HS : out std_logic;
-- VGA_R : out std_logic_vector(7 downto 0);
-- VGA_SYNC_N : out std_logic;
-- VGA_VS : out std_logic;
-- -- GPIO_0
-- GPIO_0 : inout std_logic_vector(35 downto 0);
-- -- GPIO_1
-- GPIO_1 : inout std_logic_vector(35 downto 0);
-- -- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
HPS_FLASH_DCLK : out std_logic;
HPS_FLASH_NCSO : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C_CONTROL : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_I2C2_SCLK : inout std_logic;
HPS_I2C2_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity soc_system_top;
architecture rtl of soc_system_top is
signal hps_fpga_reset_n: std_logic;
signal displays_ena_n: std_logic_vector(5 downto 0);
component soc_system is
port(
clk_clk : in std_logic := 'X';
hps_0_h2f_reset_reset_n : out std_logic; -- reset_n
hps_0_io_hps_io_emac1_inst_TX_CLK : out std_logic;
hps_0_io_hps_io_emac1_inst_TX_CTL : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD0 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD1 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD2 : out std_logic;
hps_0_io_hps_io_emac1_inst_TXD3 : out std_logic;
hps_0_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X';
hps_0_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X';
hps_0_io_hps_io_emac1_inst_MDC : out std_logic;
hps_0_io_hps_io_qspi_inst_CLK : out std_logic;
hps_0_io_hps_io_qspi_inst_SS0 : out std_logic;
hps_0_io_hps_io_qspi_inst_IO0 : inout std_logic := 'X';
hps_0_io_hps_io_qspi_inst_IO1 : inout std_logic := 'X';
hps_0_io_hps_io_qspi_inst_IO2 : inout std_logic := 'X';
hps_0_io_hps_io_qspi_inst_IO3 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_CLK : out std_logic;
hps_0_io_hps_io_sdio_inst_CMD : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D0 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D1 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D2 : inout std_logic := 'X';
hps_0_io_hps_io_sdio_inst_D3 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_CLK : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_STP : out std_logic;
hps_0_io_hps_io_usb1_inst_DIR : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_NXT : in std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D0 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D1 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D2 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D3 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D4 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D5 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D6 : inout std_logic := 'X';
hps_0_io_hps_io_usb1_inst_D7 : inout std_logic := 'X';
hps_0_io_hps_io_spim1_inst_CLK : out std_logic;
hps_0_io_hps_io_spim1_inst_MOSI : out std_logic;
hps_0_io_hps_io_spim1_inst_MISO : in std_logic := 'X';
hps_0_io_hps_io_spim1_inst_SS0 : out std_logic;
hps_0_io_hps_io_uart0_inst_RX : in std_logic := 'X';
hps_0_io_hps_io_uart0_inst_TX : out std_logic;
hps_0_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X';
hps_0_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X';
hps_0_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X';
hps_0_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X';
hps_0_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X';
hps_0_ddr_mem_a : out std_logic_vector(14 downto 0); -- mem_a
hps_0_ddr_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
hps_0_ddr_mem_ck : out std_logic; -- mem_ck
hps_0_ddr_mem_ck_n : out std_logic; -- mem_ck_n
hps_0_ddr_mem_cke : out std_logic; -- mem_cke
hps_0_ddr_mem_cs_n : out std_logic; -- mem_cs_n
hps_0_ddr_mem_ras_n : out std_logic; -- mem_ras_n
hps_0_ddr_mem_cas_n : out std_logic; -- mem_cas_n
hps_0_ddr_mem_we_n : out std_logic; -- mem_we_n
hps_0_ddr_mem_reset_n : out std_logic; -- mem_reset_n
hps_0_ddr_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
hps_0_ddr_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
hps_0_ddr_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
hps_0_ddr_mem_odt : out std_logic; -- mem_odt
hps_0_ddr_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
hps_0_ddr_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
reset_reset_n : in std_logic := 'X'
);
end component soc_system;
begin
soc_system_inst : component soc_system
port map(
clk_clk => CLOCK_50,
hps_0_io_hps_io_emac1_inst_TX_CLK => HPS_ENET_GTX_CLK,
hps_0_io_hps_io_emac1_inst_TX_CTL => HPS_ENET_TX_EN,
hps_0_io_hps_io_emac1_inst_TXD0 => HPS_ENET_TX_DATA(0),
hps_0_io_hps_io_emac1_inst_TXD1 => HPS_ENET_TX_DATA(1),
hps_0_io_hps_io_emac1_inst_TXD2 => HPS_ENET_TX_DATA(2),
hps_0_io_hps_io_emac1_inst_TXD3 => HPS_ENET_TX_DATA(3),
hps_0_io_hps_io_emac1_inst_RX_CLK => HPS_ENET_RX_CLK,
hps_0_io_hps_io_emac1_inst_RX_CTL => HPS_ENET_RX_DV,
hps_0_io_hps_io_emac1_inst_RXD0 => HPS_ENET_RX_DATA(0),
hps_0_io_hps_io_emac1_inst_RXD1 => HPS_ENET_RX_DATA(1),
hps_0_io_hps_io_emac1_inst_RXD2 => HPS_ENET_RX_DATA(2),
hps_0_io_hps_io_emac1_inst_RXD3 => HPS_ENET_RX_DATA(3),
hps_0_io_hps_io_emac1_inst_MDIO => HPS_ENET_MDIO,
hps_0_io_hps_io_emac1_inst_MDC => HPS_ENET_MDC,
hps_0_io_hps_io_qspi_inst_CLK => HPS_FLASH_DCLK,
hps_0_io_hps_io_qspi_inst_SS0 => HPS_FLASH_NCSO,
hps_0_io_hps_io_qspi_inst_IO0 => HPS_FLASH_DATA(0),
hps_0_io_hps_io_qspi_inst_IO1 => HPS_FLASH_DATA(1),
hps_0_io_hps_io_qspi_inst_IO2 => HPS_FLASH_DATA(2),
hps_0_io_hps_io_qspi_inst_IO3 => HPS_FLASH_DATA(3),
hps_0_io_hps_io_sdio_inst_CLK => HPS_SD_CLK,
hps_0_io_hps_io_sdio_inst_CMD => HPS_SD_CMD,
hps_0_io_hps_io_sdio_inst_D0 => HPS_SD_DATA(0),
hps_0_io_hps_io_sdio_inst_D1 => HPS_SD_DATA(1),
hps_0_io_hps_io_sdio_inst_D2 => HPS_SD_DATA(2),
hps_0_io_hps_io_sdio_inst_D3 => HPS_SD_DATA(3),
hps_0_io_hps_io_usb1_inst_CLK => HPS_USB_CLKOUT,
hps_0_io_hps_io_usb1_inst_STP => HPS_USB_STP,
hps_0_io_hps_io_usb1_inst_DIR => HPS_USB_DIR,
hps_0_io_hps_io_usb1_inst_NXT => HPS_USB_NXT,
hps_0_io_hps_io_usb1_inst_D0 => HPS_USB_DATA(0),
hps_0_io_hps_io_usb1_inst_D1 => HPS_USB_DATA(1),
hps_0_io_hps_io_usb1_inst_D2 => HPS_USB_DATA(2),
hps_0_io_hps_io_usb1_inst_D3 => HPS_USB_DATA(3),
hps_0_io_hps_io_usb1_inst_D4 => HPS_USB_DATA(4),
hps_0_io_hps_io_usb1_inst_D5 => HPS_USB_DATA(5),
hps_0_io_hps_io_usb1_inst_D6 => HPS_USB_DATA(6),
hps_0_io_hps_io_usb1_inst_D7 => HPS_USB_DATA(7),
hps_0_io_hps_io_spim1_inst_CLK => HPS_SPIM_CLK,
hps_0_io_hps_io_spim1_inst_MOSI => HPS_SPIM_MOSI,
hps_0_io_hps_io_spim1_inst_MISO => HPS_SPIM_MISO,
hps_0_io_hps_io_spim1_inst_SS0 => HPS_SPIM_SS,
hps_0_io_hps_io_uart0_inst_RX => HPS_UART_RX,
hps_0_io_hps_io_uart0_inst_TX => HPS_UART_TX,
hps_0_io_hps_io_i2c0_inst_SDA => HPS_I2C1_SDAT,
hps_0_io_hps_io_i2c0_inst_SCL => HPS_I2C1_SCLK,
hps_0_io_hps_io_i2c1_inst_SDA => HPS_I2C2_SDAT,
hps_0_io_hps_io_i2c1_inst_SCL => HPS_I2C2_SCLK,
hps_0_io_hps_io_gpio_inst_GPIO09 => HPS_CONV_USB_N,
hps_0_io_hps_io_gpio_inst_GPIO35 => HPS_ENET_INT_N,
hps_0_io_hps_io_gpio_inst_GPIO40 => HPS_LTC_GPIO,
hps_0_io_hps_io_gpio_inst_GPIO48 => HPS_I2C_CONTROL,
hps_0_io_hps_io_gpio_inst_GPIO53 => HPS_LED,
hps_0_io_hps_io_gpio_inst_GPIO54 => HPS_KEY_N,
hps_0_io_hps_io_gpio_inst_GPIO61 => HPS_GSENSOR_INT,
hps_0_ddr_mem_a => HPS_DDR3_ADDR,
hps_0_ddr_mem_ba => HPS_DDR3_BA,
hps_0_ddr_mem_ck => HPS_DDR3_CK_P,
hps_0_ddr_mem_ck_n => HPS_DDR3_CK_N,
hps_0_ddr_mem_cke => HPS_DDR3_CKE,
hps_0_ddr_mem_cs_n => HPS_DDR3_CS_N,
hps_0_ddr_mem_ras_n => HPS_DDR3_RAS_N,
hps_0_ddr_mem_cas_n => HPS_DDR3_CAS_N,
hps_0_ddr_mem_we_n => HPS_DDR3_WE_N,
hps_0_ddr_mem_reset_n => HPS_DDR3_RESET_N,
hps_0_ddr_mem_dq => HPS_DDR3_DQ,
hps_0_ddr_mem_dqs => HPS_DDR3_DQS_P,
hps_0_ddr_mem_dqs_n => HPS_DDR3_DQS_N,
hps_0_ddr_mem_odt => HPS_DDR3_ODT,
hps_0_ddr_mem_dm => HPS_DDR3_DM,
hps_0_ddr_oct_rzqin => HPS_DDR3_RZQ,
reset_reset_n => '1'
);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic
);
end router_credit_based_PD_C;
architecture behavior of router_credit_based_PD_C is
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end COMPONENT;
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty:out std_logic
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 0;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
begin
Faulty_N_out <= sig_Faulty_N_out;
Faulty_E_out <= sig_Faulty_E_out;
Faulty_W_out <= sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out;
-- all the counter_threshold modules
CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N,
Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out);
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L);
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--- all the LBDRs
LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_N,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_E,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_W,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_S,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_L,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
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-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
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-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
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-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic
);
end router_credit_based_PD_C;
architecture behavior of router_credit_based_PD_C is
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end COMPONENT;
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty:out std_logic
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 0;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
begin
Faulty_N_out <= sig_Faulty_N_out;
Faulty_E_out <= sig_Faulty_E_out;
Faulty_W_out <= sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out;
-- all the counter_threshold modules
CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N,
Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out);
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L);
------------------------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------------------------
--- all the LBDRs
LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_N,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_E,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_W,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_S,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_L,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic
);
end router_credit_based_PD_C;
architecture behavior of router_credit_based_PD_C is
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end COMPONENT;
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty:out std_logic
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 0;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Rxy_reconf: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
begin
Faulty_N_out <= sig_Faulty_N_out;
Faulty_E_out <= sig_Faulty_E_out;
Faulty_W_out <= sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out;
-- all the counter_threshold modules
CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N,
Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out);
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
--- all the LBDRs
LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_N,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_E,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_W,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_S,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, Rxy_reconf => Rxy_reconf, Reconfig => Reconfig,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(NoC_size downto 1) ,
packet_drop_order => packet_drop_order_L,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20912)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20912)
`protect data_block
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`protect end_protected
|
library stack;
use stack.OneHotStack.all;
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity mrom_tb is
end mrom_tb;
architecture TB_ARCHITECTURE of mrom_tb is
-- Component declaration of the tested unit
component mrom
port(
RE : in STD_LOGIC;
ADDR : in mem_addr;
DOUT : out command );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal RE : STD_LOGIC;
signal ADDR : mem_addr;
-- Observed signals - signals mapped to the output ports of tested entity
signal DOUT : command;
constant WAIT_period: time := 10 ns;
begin
-- Unit Under Test port map
UUT : mrom
port map (
RE => RE,
ADDR => ADDR,
DOUT => DOUT
);
-- Add your stimulus here ...
main: process
begin
re <= '0';
addr <= "00010";
wait for 1 * WAIT_period;
re <= '1';
wait for 1 * WAIT_period;
addr <= "00000";
re <= '1';
wait for 1 * WAIT_period;
re <= '0';
wait for 100 * WAIT_period;
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_mrom of mrom_tb is
for TB_ARCHITECTURE
for UUT : mrom
use entity work.mrom(beh_stack);
end for;
end for;
end TESTBENCH_FOR_mrom;
|
entity comparison is
port (
a : in integer;
b : in integer;
q : out boolean );
end comparison;
architecture rtl of comparison is
begin
q <= a = b;
end architecture;
-------------------------------------------------------------------------------
entity comparison_tb is
generic ( delay : delay_length );
end entity;
architecture sim of comparison_tb is
signal a : integer;
signal b : integer;
signal q : boolean;
component comparison
port (
a : in integer;
b : in integer;
q : out boolean );
end component;
procedure result(a, b : in integer; q : in boolean) is
begin
report integer'image(a) & " <=> " & integer'image(b)
& " = " & boolean'image(q);
end procedure;
begin
DUT: component comparison
port map ( a, b, q );
SEQUENCER_PROC: process
begin
wait for delay;
a <= 4;
b <= 2;
wait for 1 ns;
result(a, b, q);
b <= 7;
wait for 1 ns;
result(a, b, q);
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity greater_than is
port (
a : in integer;
b : in integer;
q : out boolean );
end greater_than;
architecture rtl of greater_than is
begin
q <= a > b;
end architecture;
-------------------------------------------------------------------------------
configuration eq of comparison_tb is
for sim
end for;
end configuration;
-------------------------------------------------------------------------------
configuration gt of comparison_tb is
for sim
for DUT : comparison
use entity work.greater_than(rtl);
end for;
end for;
end configuration;
-------------------------------------------------------------------------------
configuration lt of comparison_tb is
for sim
for DUT : comparison
use entity work.greater_than(rtl)
port map ( b, a, q );
end for;
end for;
end configuration;
-------------------------------------------------------------------------------
entity conf2 is
end entity;
architecture test of conf2 is
begin
uut1: configuration work.lt
generic map ( delay => 0 ns );
uut2: configuration work.gt
generic map ( delay => 10 ns );
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DC_CTL is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (3 downto 0);
RB : in STD_LOGIC_VECTOR (3 downto 0);
RA0 : in STD_LOGIC_VECTOR (3 downto 0);
RA1 : in STD_LOGIC_VECTOR (3 downto 0);
RA2 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB0 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB1 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB2 : in STD_LOGIC_VECTOR (3 downto 0);
OPC : in STD_LOGIC_VECTOR (3 downto 0);
OP1_SEL : out STD_LOGIC_VECTOR (1 downto 0);
OP2_SEL : out STD_LOGIC_VECTOR (1 downto 0));
end DC_CTL;
architecture Mixed of DC_CTL is
signal OP1, OP2 : STD_LOGIC_VECTOR (1 downto 0) := (OTHERS => '0');
begin
process(RA, RB, RA0, RA1, RA2)
begin
-- if (rising_edge(CLK)) then
if (RA = RA0) then
OP1 <= "01";
-- OP1_SEL <= OP1;
elsif (RA = RA1) then
OP1 <= "10";
-- OP1_SEL <= OP1;
elsif (RA = RA2) then
OP1 <= "11";
-- OP1_SEL <= OP1;
else
OP1 <= "00";
-- OP1_SEL <= OP1;
end if;
-- OP1_SEL <= OP1;
if (RB = RA0) then
OP2 <= "01";
elsif (RB = RA1) then
OP2 <= "10";
elsif (RB = RA2) then
OP2 <= "11";
else
OP2 <= "00";
end if;
-- end if;
end process;
OP1_SEL <= OP1;
with OPC select OP2_SEL <=
OP2 when "0000" | "0001" | "0010" | "0011" | "0100",
"00" when "0101" | "0110" | "0111" | "1000" | "1001" | "1010",
"00" when OTHERS;
end Mixed;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DC_CTL is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (3 downto 0);
RB : in STD_LOGIC_VECTOR (3 downto 0);
RA0 : in STD_LOGIC_VECTOR (3 downto 0);
RA1 : in STD_LOGIC_VECTOR (3 downto 0);
RA2 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB0 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB1 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB2 : in STD_LOGIC_VECTOR (3 downto 0);
OPC : in STD_LOGIC_VECTOR (3 downto 0);
OP1_SEL : out STD_LOGIC_VECTOR (1 downto 0);
OP2_SEL : out STD_LOGIC_VECTOR (1 downto 0));
end DC_CTL;
architecture Mixed of DC_CTL is
signal OP1, OP2 : STD_LOGIC_VECTOR (1 downto 0) := (OTHERS => '0');
begin
process(RA, RB, RA0, RA1, RA2)
begin
-- if (rising_edge(CLK)) then
if (RA = RA0) then
OP1 <= "01";
-- OP1_SEL <= OP1;
elsif (RA = RA1) then
OP1 <= "10";
-- OP1_SEL <= OP1;
elsif (RA = RA2) then
OP1 <= "11";
-- OP1_SEL <= OP1;
else
OP1 <= "00";
-- OP1_SEL <= OP1;
end if;
-- OP1_SEL <= OP1;
if (RB = RA0) then
OP2 <= "01";
elsif (RB = RA1) then
OP2 <= "10";
elsif (RB = RA2) then
OP2 <= "11";
else
OP2 <= "00";
end if;
-- end if;
end process;
OP1_SEL <= OP1;
with OPC select OP2_SEL <=
OP2 when "0000" | "0001" | "0010" | "0011" | "0100",
"00" when "0101" | "0110" | "0111" | "1000" | "1001" | "1010",
"00" when OTHERS;
end Mixed;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DC_CTL is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (3 downto 0);
RB : in STD_LOGIC_VECTOR (3 downto 0);
RA0 : in STD_LOGIC_VECTOR (3 downto 0);
RA1 : in STD_LOGIC_VECTOR (3 downto 0);
RA2 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB0 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB1 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB2 : in STD_LOGIC_VECTOR (3 downto 0);
OPC : in STD_LOGIC_VECTOR (3 downto 0);
OP1_SEL : out STD_LOGIC_VECTOR (1 downto 0);
OP2_SEL : out STD_LOGIC_VECTOR (1 downto 0));
end DC_CTL;
architecture Mixed of DC_CTL is
signal OP1, OP2 : STD_LOGIC_VECTOR (1 downto 0) := (OTHERS => '0');
begin
process(RA, RB, RA0, RA1, RA2)
begin
-- if (rising_edge(CLK)) then
if (RA = RA0) then
OP1 <= "01";
-- OP1_SEL <= OP1;
elsif (RA = RA1) then
OP1 <= "10";
-- OP1_SEL <= OP1;
elsif (RA = RA2) then
OP1 <= "11";
-- OP1_SEL <= OP1;
else
OP1 <= "00";
-- OP1_SEL <= OP1;
end if;
-- OP1_SEL <= OP1;
if (RB = RA0) then
OP2 <= "01";
elsif (RB = RA1) then
OP2 <= "10";
elsif (RB = RA2) then
OP2 <= "11";
else
OP2 <= "00";
end if;
-- end if;
end process;
OP1_SEL <= OP1;
with OPC select OP2_SEL <=
OP2 when "0000" | "0001" | "0010" | "0011" | "0100",
"00" when "0101" | "0110" | "0111" | "1000" | "1001" | "1010",
"00" when OTHERS;
end Mixed;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DC_CTL is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (3 downto 0);
RB : in STD_LOGIC_VECTOR (3 downto 0);
RA0 : in STD_LOGIC_VECTOR (3 downto 0);
RA1 : in STD_LOGIC_VECTOR (3 downto 0);
RA2 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB0 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB1 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB2 : in STD_LOGIC_VECTOR (3 downto 0);
OPC : in STD_LOGIC_VECTOR (3 downto 0);
OP1_SEL : out STD_LOGIC_VECTOR (1 downto 0);
OP2_SEL : out STD_LOGIC_VECTOR (1 downto 0));
end DC_CTL;
architecture Mixed of DC_CTL is
signal OP1, OP2 : STD_LOGIC_VECTOR (1 downto 0) := (OTHERS => '0');
begin
process(RA, RB, RA0, RA1, RA2)
begin
-- if (rising_edge(CLK)) then
if (RA = RA0) then
OP1 <= "01";
-- OP1_SEL <= OP1;
elsif (RA = RA1) then
OP1 <= "10";
-- OP1_SEL <= OP1;
elsif (RA = RA2) then
OP1 <= "11";
-- OP1_SEL <= OP1;
else
OP1 <= "00";
-- OP1_SEL <= OP1;
end if;
-- OP1_SEL <= OP1;
if (RB = RA0) then
OP2 <= "01";
elsif (RB = RA1) then
OP2 <= "10";
elsif (RB = RA2) then
OP2 <= "11";
else
OP2 <= "00";
end if;
-- end if;
end process;
OP1_SEL <= OP1;
with OPC select OP2_SEL <=
OP2 when "0000" | "0001" | "0010" | "0011" | "0100",
"00" when "0101" | "0110" | "0111" | "1000" | "1001" | "1010",
"00" when OTHERS;
end Mixed;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DC_CTL is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (3 downto 0);
RB : in STD_LOGIC_VECTOR (3 downto 0);
RA0 : in STD_LOGIC_VECTOR (3 downto 0);
RA1 : in STD_LOGIC_VECTOR (3 downto 0);
RA2 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB0 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB1 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB2 : in STD_LOGIC_VECTOR (3 downto 0);
OPC : in STD_LOGIC_VECTOR (3 downto 0);
OP1_SEL : out STD_LOGIC_VECTOR (1 downto 0);
OP2_SEL : out STD_LOGIC_VECTOR (1 downto 0));
end DC_CTL;
architecture Mixed of DC_CTL is
signal OP1, OP2 : STD_LOGIC_VECTOR (1 downto 0) := (OTHERS => '0');
begin
process(RA, RB, RA0, RA1, RA2)
begin
-- if (rising_edge(CLK)) then
if (RA = RA0) then
OP1 <= "01";
-- OP1_SEL <= OP1;
elsif (RA = RA1) then
OP1 <= "10";
-- OP1_SEL <= OP1;
elsif (RA = RA2) then
OP1 <= "11";
-- OP1_SEL <= OP1;
else
OP1 <= "00";
-- OP1_SEL <= OP1;
end if;
-- OP1_SEL <= OP1;
if (RB = RA0) then
OP2 <= "01";
elsif (RB = RA1) then
OP2 <= "10";
elsif (RB = RA2) then
OP2 <= "11";
else
OP2 <= "00";
end if;
-- end if;
end process;
OP1_SEL <= OP1;
with OPC select OP2_SEL <=
OP2 when "0000" | "0001" | "0010" | "0011" | "0100",
"00" when "0101" | "0110" | "0111" | "1000" | "1001" | "1010",
"00" when OTHERS;
end Mixed;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DC_CTL is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (3 downto 0);
RB : in STD_LOGIC_VECTOR (3 downto 0);
RA0 : in STD_LOGIC_VECTOR (3 downto 0);
RA1 : in STD_LOGIC_VECTOR (3 downto 0);
RA2 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB0 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB1 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB2 : in STD_LOGIC_VECTOR (3 downto 0);
OPC : in STD_LOGIC_VECTOR (3 downto 0);
OP1_SEL : out STD_LOGIC_VECTOR (1 downto 0);
OP2_SEL : out STD_LOGIC_VECTOR (1 downto 0));
end DC_CTL;
architecture Mixed of DC_CTL is
signal OP1, OP2 : STD_LOGIC_VECTOR (1 downto 0) := (OTHERS => '0');
begin
process(RA, RB, RA0, RA1, RA2)
begin
-- if (rising_edge(CLK)) then
if (RA = RA0) then
OP1 <= "01";
-- OP1_SEL <= OP1;
elsif (RA = RA1) then
OP1 <= "10";
-- OP1_SEL <= OP1;
elsif (RA = RA2) then
OP1 <= "11";
-- OP1_SEL <= OP1;
else
OP1 <= "00";
-- OP1_SEL <= OP1;
end if;
-- OP1_SEL <= OP1;
if (RB = RA0) then
OP2 <= "01";
elsif (RB = RA1) then
OP2 <= "10";
elsif (RB = RA2) then
OP2 <= "11";
else
OP2 <= "00";
end if;
-- end if;
end process;
OP1_SEL <= OP1;
with OPC select OP2_SEL <=
OP2 when "0000" | "0001" | "0010" | "0011" | "0100",
"00" when "0101" | "0110" | "0111" | "1000" | "1001" | "1010",
"00" when OTHERS;
end Mixed;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "peripheral_register"
-------------------------------------------------------------------------------
-- Author : Calle <calle@Alukiste>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity peripheral_register_tb is
end peripheral_register_tb;
-------------------------------------------------------------------------------
architecture tb of peripheral_register_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#0100#;
-- component ports
signal reg : std_logic_vector(15 downto 0) := (others => '0');
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal clk : std_logic := '0';
signal reg_readback : std_logic_vector(15 downto 0);
-- comments for the wave view of the testbench
type comment_type is (idle,
read_wrong_addr,
read_correct_addr,
write_wrong_addr,
write_correct_addr,
sequential_cycles);
signal comment : comment_type := idle;
begin
reg_readback <= not reg;
-- component instantiation
DUT : peripheral_register
generic map (
BASE_ADDRESS => BASE_ADDRESS)
port map (
dout_p => reg,
din_p => reg_readback, -- read back the written values
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
waveform : process
begin
wait for 20 ns;
-- Read from wrong address
comment <= read_wrong_addr;
readWord(addr => 16#0020#, bus_i => bus_i, clk => clk);
-- Read from correct address
comment <= read_correct_addr;
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
-- Write to wrong address
comment <= write_wrong_addr;
writeWord(addr => BASE_ADDRESS + 1, data => 16#affe#, bus_i => bus_i, clk => clk);
-- Write to correct address
comment <= write_correct_addr;
writeWord(addr => BASE_ADDRESS, data => 16#54af#, bus_i => bus_i, clk => clk);
-- Read from wrong address
comment <= read_wrong_addr;
readWord(addr => 16#0020#, bus_i => bus_i, clk => clk);
-- Read from correct address
comment <= read_correct_addr;
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
-- Read from wrong address
comment <= read_wrong_addr;
readWord(addr => 16#0020#, bus_i => bus_i, clk => clk);
wait until rising_edge(clk);
-- generate two read cycles directly following each other
comment <= sequential_cycles;
bus_i.re <= '1';
wait until rising_edge(clk);
wait until rising_edge(clk);
bus_i.re <= '0';
wait until rising_edge(clk);
bus_i.data <= x"4321";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait until rising_edge(clk);
bus_i.re <= '1';
wait until rising_edge(clk);
bus_i.re <= '0';
end process waveform;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddrsp64a is
generic (
memtech : integer := 0;
hindex : integer := 3;
haddr : integer := 1024;
hmask : integer := 3072;
ioaddr : integer := 1;
iomask : integer := 4095;
MHz : integer := 90;
col : integer := 9;
Mbyte : integer := 256;
fast : integer := 0;
pwron : integer := 1;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of ddrsp64a is
constant REVISION : integer := 0;
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant abuf : integer := 6;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDRSP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, ext, leadout);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4a, wr4, wr5, sidle, ioreg1, ioreg2);
type icycletype is (iidle, pre, ref1, ref2, emode, lmode, finish);
constant NAHBMST : integer := 16; -- maximum AHB masters
constant NAHBSLV : integer := 16; -- maximum AHB slaves
constant NAPBSLV : integer := 16; -- maximum APB slaves
constant NAHBIRQ : integer := 32; -- maximum interrupts
constant NAHBAMR : integer := 4; -- maximum address mapping registers
constant NAHBIR : integer := 4; -- maximum AHB identification registers
constant NAHBCFG : integer := NAHBIR + NAHBAMR; -- words in AHB config block
constant NAPBIR : integer := 1; -- maximum APB configuration words
constant NAPBAMR : integer := 1; -- maximum APB configuration words
constant NAPBCFG : integer := NAPBIR + NAPBAMR; -- words in APB config block
constant NBUS : integer := 4;
subtype amba_config_word is std_logic_vector(31 downto 0);
type ahb_config_type is array (0 to NAHBCFG-1) of amba_config_word;
type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
-- AHB master inputs
type ahb_mst_in_type is record
hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
hcache : std_ulogic; -- cacheable
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
end record;
-- AHB master outputs
type ahb_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBMST-1; -- diagnostic use only
end record;
-- AHB slave inputs
type ahb_slv_in_type is record
hsel : std_logic_vector(0 to NAHBSLV-1); -- slave select
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
htrans : std_logic_vector(1 downto 0); -- transfer type
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hwdata : std_logic_vector(31 downto 0); -- write data bus
hprot : std_logic_vector(3 downto 0); -- protection control
hready : std_ulogic; -- transfer done
hmaster : std_logic_vector(3 downto 0); -- current master
hmastlock : std_ulogic; -- locked access
hmbsel : std_logic_vector(0 to NAHBAMR-1); -- memory bank select
hcache : std_ulogic; -- cacheable
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
end record;
-- AHB slave outputs
type ahb_slv_out_type is record
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
hsplit : std_logic_vector(15 downto 0); -- split completion
hcache : std_ulogic; -- cacheable
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBSLV-1; -- diagnostic use only
end record;
-- array types
type ahb_mst_out_vector_type is array (natural range <>) of ahb_mst_out_type;
type ahb_slv_out_vector_type is array (natural range <>) of ahb_slv_out_type;
subtype ahb_mst_out_vector is ahb_mst_out_vector_type(NAHBMST-1 downto 0);
subtype ahb_slv_out_vector is ahb_slv_out_vector_type(NAHBSLV-1 downto 0);
type ahb_mst_out_bus_vector is array (0 to NBUS-1) of ahb_mst_out_vector;
type ahb_slv_out_bus_vector is array (0 to NBUS-1) of ahb_slv_out_vector;
-- constants
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_BUSY: std_logic_vector(1 downto 0) := "01";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_SINGLE: std_logic_vector(2 downto 0) := "000";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HBURST_WRAP4: std_logic_vector(2 downto 0) := "010";
constant HBURST_INCR4: std_logic_vector(2 downto 0) := "011";
constant HBURST_WRAP8: std_logic_vector(2 downto 0) := "100";
constant HBURST_INCR8: std_logic_vector(2 downto 0) := "101";
constant HBURST_WRAP16: std_logic_vector(2 downto 0) := "110";
constant HBURST_INCR16: std_logic_vector(2 downto 0) := "111";
constant HSIZE_BYTE: std_logic_vector(2 downto 0) := "000";
constant HSIZE_HWORD: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HSIZE_DWORD: std_logic_vector(2 downto 0) := "011";
constant HSIZE_4WORD: std_logic_vector(2 downto 0) := "100";
constant HSIZE_8WORD: std_logic_vector(2 downto 0) := "101";
constant HSIZE_16WORD: std_logic_vector(2 downto 0) := "110";
constant HSIZE_32WORD: std_logic_vector(2 downto 0) := "111";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
-- APB slave inputs
type apb_slv_in_type is record
psel : std_logic_vector(0 to NAPBSLV-1); -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
end record;
-- APB slave outputs
type apb_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
pconfig : apb_config_type; -- memory access reg.
pindex : integer range 0 to NAPBSLV -1; -- diag use only
end record;
-- array types
type apb_slv_out_vector is array (0 to NAPBSLV-1) of apb_slv_out_type;
-- support for plug&play configuration
constant AMBA_CONFIG_VER0 : std_logic_vector(1 downto 0) := "00";
subtype amba_vendor_type is integer range 0 to 16#ff#;
subtype amba_device_type is integer range 0 to 16#3ff#;
subtype amba_version_type is integer range 0 to 16#3f#;
subtype amba_cfgver_type is integer range 0 to 3;
subtype amba_irq_type is integer range 0 to NAHBIRQ-1;
subtype ahb_addr_type is integer range 0 to 16#fff#;
constant zx : std_logic_vector(31 downto 0) := (others => '0');
constant zxirq : std_logic_vector(NAHBIRQ-1 downto 0) := (others => '0');
constant zy : std_logic_vector(0 to 31) := (others => '0');
constant apb_none : apb_slv_out_type :=
(zx, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbm_none : ahb_mst_out_type := ( '0', '0', "00", zx,
'0', "000", "000", "0000", zx, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbs_none : ahb_slv_out_type := (
'1', "00", zx, zx(15 downto 0), '0', zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbs_in_none : ahb_slv_in_type := (
zy(0 to NAHBSLV-1), zx, '0', "00", "000", "000", zx,
"0000", '1', "0000", '0', zy(0 to NAHBAMR-1), '0', zxirq(NAHBIRQ-1 downto 0),
'0', '0', '0', '0');
constant ahbsv_none : ahb_slv_out_vector := (others => ahbs_none);
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bwidth : std_logic_vector(1 downto 0);
sd : std_logic_vector(63 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
edac : std_logic;
end record;
type memory_out_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
sddata : std_logic_vector(63 downto 0);
ramsn : std_logic_vector(7 downto 0);
ramoen : std_logic_vector(7 downto 0);
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector(3 downto 0);
iosn : std_logic;
romsn : std_logic_vector(7 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
vbdrive : std_logic_vector(31 downto 0); --vector bus drive
svbdrive : std_logic_vector(63 downto 0); --vector bus drive sdram
read : std_logic;
sa : std_logic_vector(14 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
vcdrive : std_logic_vector(7 downto 0); --vector bus drive cb
svcdrive : std_logic_vector(7 downto 0); --vector bus drive cb sdram
ce : std_ulogic;
end record;
type sdctrl_in_type is record
wprot : std_ulogic;
data : std_logic_vector (127 downto 0); -- data in
cb : std_logic_vector(15 downto 0);
end record;
type sdctrl_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 15 downto 0); -- data i/o mask
bdrive : std_ulogic; -- bus drive
qdrive : std_ulogic; -- bus drive
vbdrive : std_logic_vector(31 downto 0); -- vector bus drive
address : std_logic_vector (16 downto 2); -- address out
data : std_logic_vector (127 downto 0); -- data out
cb : std_logic_vector(15 downto 0);
ce : std_ulogic;
ba : std_logic_vector ( 1 downto 0); -- bank address
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay
cal_rst : std_logic; -- calibration reset
odt : std_logic_vector(1 downto 0);
end record;
type sdram_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 7 downto 0); -- data i/o mask
end record;
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
end record;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
end record;
-- local registers
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
ready : std_ulogic;
ready2 : std_ulogic;
write : std_logic_vector(3 downto 0);
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(1 downto 0);
acc : access_param;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
startsdold : std_ulogic;
burst : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector(2 downto 0);
refresh : std_logic_vector(11 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(15 downto 0);
address : std_logic_vector(15 downto 2); -- memory address
ba : std_logic_vector( 1 downto 0);
waddr : std_logic_vector(abuf-1 downto 0);
cfg : sdram_cfg_type;
hrdata : std_logic_vector(127 downto 0);
end record;
signal vcc : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rdata, wdata : std_logic_vector(127 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
vcc <= '1';
ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
variable v : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dout : std_logic_vector(31 downto 0);
begin
v := ra; v.hresp := HRESP_OKAY; v.write := "0000";
case ra.raddr(1 downto 0) is
when "00" => v.hrdata := rdata(127 downto 96);
when "01" => v.hrdata := rdata(95 downto 64);
when "10" => v.hrdata := rdata(63 downto 32);
when others => v.hrdata := rdata(31 downto 0);
end case;
v.ready := not (ra.startsd xor r.startsdold);
v.ready2 := ra.ready;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- if (ra.hsel and ra.hio and not ra.hready) = '1' then v.hready := '1'; end if;
case ra.state is
when midle =>
if ((v.hsel and v.htrans(1)) = '1') then
if v.hwrite = '0' then
v.state := rhold; v.startsd := not ra.startsd;
else
v.state := dwrite; v.hready := '1';
-- v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
v.write := decode(v.haddr(3 downto 2));
end if;
end if;
v.raddr := ra.haddr(7 downto 2);
v.ready := '0'; v.ready2 := '0';
-- if not ((ra.hsel and ra.htrans(1) and not ra.htrans(0)) = '1') then
if ahbsi.hready = '1' then
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
when rhold =>
v.raddr := ra.haddr(7 downto 2);
if ra.ready2 = '1' then
v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
end if;
when dread =>
v.raddr := ra.raddr + 1; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
(ra.raddr(2 downto 0) = "000")
then v.state := midle; v.hready := '0'; end if;
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
when dwrite =>
v.raddr := ra.haddr(7 downto 2); v.hready := '1';
-- v.write(0) := not v.haddr(2); v.write(1) := v.haddr(2);
v.write := decode(v.haddr(3 downto 2));
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
(ra.haddr(4 downto 2) = "111")
then
v.startsd := not ra.startsd; v.state := whold1;
v.write := "0000"; v.hready := '0';
end if;
when whold1 =>
v.state := whold2; v.ready := '0';
when whold2 =>
if ra.ready = '1' then
v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
end case;
v.hwdata := ahbsi.hwdata;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
dout := ra.hrdata(31 downto 0);
if rst = '0' then
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.hio := '0';
end if;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
end process;
ddr_ctrl : process(rst, r, ra, sdi, rbdrive, wdata)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dqm : std_logic_vector(15 downto 0);
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable writecfg: std_ulogic;
variable regsd1 : std_logic_vector(31 downto 0); -- data from registers
variable regsd2 : std_logic_vector(31 downto 0); -- data from registers
begin
-- Variable default settings to avoid latches
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
v.hrdata := sdi.data; v.qdrive :='0';
regsd1 := (others => '0');
regsd1(31 downto 15) := r.cfg.refon & r.cfg.trp & r.cfg.trfc &
r.cfg.trcd & r.cfg.bsize & r.cfg.csize & r.cfg.command &
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd1(11 downto 0) := r.cfg.refresh;
regsd2 := (others => '0');
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd2(14 downto 12) := conv_std_logic_vector(3, 3);
-- generate DQM from address and write size
case ra.acc.size is
when "00" =>
case ra.acc.haddr(3 downto 0) is
when "0000" => dqm := "0111111111111111";
when "0001" => dqm := "1011111111111111";
when "0010" => dqm := "1101111111111111";
when "0011" => dqm := "1110111111111111";
when "0100" => dqm := "1111011111111111";
when "0101" => dqm := "1111101111111111";
when "0110" => dqm := "1111110111111111";
when "0111" => dqm := "1111111011111111";
when "1000" => dqm := "1111111101111111";
when "1001" => dqm := "1111111110111111";
when "1010" => dqm := "1111111111011111";
when "1011" => dqm := "1111111111101111";
when "1100" => dqm := "1111111111110111";
when "1101" => dqm := "1111111111111011";
when "1110" => dqm := "1111111111111101";
when others => dqm := "1111111111111110";
end case;
when "01" =>
case ra.acc.haddr(3 downto 1) is
when "000" => dqm := "0011111111111111";
when "001" => dqm := "1100111111111111";
when "010" => dqm := "1111001111111111";
when "011" => dqm := "1111110011111111";
when "100" => dqm := "1111111100111111";
when "101" => dqm := "1111111111001111";
when "110" => dqm := "1111111111110011";
when others => dqm := "1111111111111100";
end case;
when others =>
dqm := "0000000000000000";
end case;
v.startsd := ra.startsd;
-- main FSM
case r.mstate is
when midle =>
if r.startsd = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "000") and
(r.cmstate = midle)
then
startsd := '1'; v.mstate := active;
end if;
end if;
when others => null;
end case;
startsd := r.startsd xor r.startsdold;
-- generate row and column address size
haddr := ra.acc.haddr;
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
case r.cfg.csize is
when "00" => raddr := haddr(25 downto 12);
when "01" => raddr := haddr(26 downto 13);
when "10" => raddr := haddr(27 downto 14);
when others => raddr := haddr(28 downto 15);
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
genmux(r.cfg.bsize, haddr(28 downto 21));
-- generate chip select
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
and (r.istate = finish)
then
v.address := raddr; v.ba := ba;
if ra.acc.hio = '0' then
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
else v.sdstate := ioreg1; end if;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.trcd = '1' then v.sdstate := act2; else
v.sdstate := act3; v.hready := ra.acc.hwrite;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act2 =>
v.sdstate := act3; v.hready := ra.acc.hwrite;
when act3 =>
v.casn := '0';
v.address := ra.acc.haddr(15 downto 13) & '0' & ra.acc.haddr(12 downto 4) & '0';
v.dqm := dqm;
if ra.acc.hwrite = '1' then
v.waddr := r.waddr + 4; v.waddr(1 downto 0) := "00";
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0'; v.qdrive := '1';
if (r.waddr /= ra.raddr) then v.hready := '1';
if (r.waddr(5 downto 2) = ra.raddr(5 downto 2)) then
if r.waddr(1) = '1' then v.dqm(15 downto 8) := (others => '1');
else
case ra.raddr(1 downto 0) is
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
v.dqm(15 downto 12) := (others => r.waddr(0));
when others => v.dqm(15 downto 12) := (others => r.waddr(0));
end case;
end if;
else
case r.waddr(1 downto 0) is
when "01" => v.dqm(15 downto 12) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1');
when "11" => v.dqm(15 downto 4) := (others => '1');
when others => null;
end case;
end if;
else
case r.waddr(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(15 downto 12) := (others => '1'); v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(15 downto 8) := (others => '1'); v.dqm(3 downto 0) := (others => '1');
when others => v.dqm(15 downto 4) := (others => '1');
end case;
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
v.waddr := r.waddr + 4; v.dqm := (others => '0');
v.address(8 downto 3) := r.waddr;
if (r.waddr <= ra.raddr) and (r.waddr(5 downto 2) /= "0000") and (r.hready = '1')
then
v.hready := '1';
if (r.hready = '1') and (r.waddr(2 downto 0) = "000") then
v.sdwen := '0'; v.casn := '0';
end if;
if (r.waddr(5 downto 2) = ra.raddr(5 downto 2)) and (r.waddr /= "000000") then
case ra.raddr(1 downto 0) is
when "00" => v.dqm(11 downto 0) := (others => '1');
when "01" => v.dqm(7 downto 0) := (others => '1');
when "10" => v.dqm(3 downto 0) := (others => '1');
when others => null;
end case;
end if;
else
v.sdstate := wr2;
v.dqm := (others => '1'); --v.bdrive := '1';
v.startsdold := r.startsd;
end if;
when wr2 =>
v.sdstate := wr3; v.qdrive := '1';
when wr3 =>
v.sdstate := wr4a; v.qdrive := '1';
when wr4a =>
v.bdrive := '1';
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
v.sdstate := wr5;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
-- if ra.acc.haddr(4 downto 2) = "011" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
when rd7 =>
v.casn := '1'; v.sdstate := rd2;
-- if ra.acc.haddr(4 downto 2) = "010" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
-- if ra.acc.haddr(4 downto 2) = "001" then
-- v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
-- end if;
-- if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
if fast = 0 then v.startsdold := r.startsd; end if;
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
-- if r.sdwen = '0' then
-- v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
-- elsif ra.acc.haddr(4 downto 2) = "000" then
-- v.casn := '0'; v.burst := '1'; v.address(5) := '1';
-- v.waddr := v.address(8 downto 3);
-- end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
-- if (r.sdcsn /= "11") and (r.waddr(1 downto 0) = "11") and (r.burst = '1')
-- then
-- v.burst := '0';
if (r.sdcsn = "11") or (r.waddr(2 downto 2) = "1") then
v.dqm := (others => '1'); v.burst := '0';
if fast /= 0 then v.startsdold := r.startsd; end if;
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
end if;
if v.hready = '1' then v.waddr := r.waddr + 4; end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when ioreg1 =>
v.hrdata(127 downto 64) := regsd1 & regsd2; v.sdstate := ioreg2;
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
when ioreg2 =>
writecfg := ra.acc.hwrite and not r.waddr(0); v.startsdold := r.startsd;
v.sdstate := sidle;
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when CMD_PRE => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when CMD_REF => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when CMD_EMR => -- load-ext-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "01";
v.address := "00000000000000";
when CMD_LMR => -- load-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
-- v.address := "00000" & r.cfg.dllrst & "0" & "01" & r.cfg.trcd & "0011";
v.address := "00000" & r.cfg.dllrst & "0" & "01" & "00010";
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "000";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when others =>
if r.trfc = "000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.cke := '1'; v.cfg.dllrst := '1';
if r.cfg.cke = '1' then v.istate := pre; v.cfg.command := CMD_PRE; end if; v.ba := "00";
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
if r.cfg.dllrst = '1' then v.istate := emode; else v.istate := lmode; end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := lmode; v.cfg.command := CMD_LMR;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.dllrst = '1' then
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
v.cfg.command := CMD_PRE; v.istate := ref1;
end if;
else
v.istate := finish; --v.cfg.command := CMD_LMR;
v.cfg.refon := '1'; v.cfg.renable := '0';
end if;
end if;
when ref1 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
end if;
when ref2 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.istate := pre;
end if;
when others =>
if r.cfg.renable = '1' then
v.istate := iidle; v.cfg.dllrst := '1';
end if;
end case;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if ((r.cfg.refon = '1') and (r.istate = finish)) or
(r.cfg.dllrst = '1')
then
v.refresh := r.refresh - 1;
if (v.refresh(11) and not r.refresh(11)) = '1' then
v.refresh := r.cfg.refresh;
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
end if;
end if;
-- AHB register access
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
v.cfg.refresh := wdata(11+96 downto 0+96);
v.cfg.cke := wdata(15+96);
v.cfg.renable := wdata(16+96);
v.cfg.dllrst := wdata(17+96);
v.cfg.command := wdata(20+96 downto 18+96);
v.cfg.csize := wdata(22+96 downto 21+96);
v.cfg.bsize := wdata(25+96 downto 23+96);
v.cfg.trcd := wdata(26+96);
v.cfg.trfc := wdata(29+96 downto 27+96);
v.cfg.trp := wdata(30+96);
v.cfg.refon := wdata(31+96);
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector(col-9, 2);
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
if MHz > 100 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 3);
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
v.refresh := (others => '0');
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
if MHz > 100 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
end if;
ri <= v;
ribdrive <= vbdrive;
end process;
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbregs : process(clk_ahb) begin
if rising_edge(clk_ahb) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst) begin
if rising_edge(clk_ddr) then
r <= ri; rbdrive <= ribdrive;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
r.cfg.cke <= '0';
end if;
end process;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
sdo.data <= wdata;
read_buff : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 128, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr(5 downto 2),
dataout => rdata, wclk => clk_ddr, write => ri.hready,
waddress => r.waddr(5 downto 2), datain => ri.hrdata);
write_buff1 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(127 downto 96), wclk => clk_ahb, write => ra.write(0),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff2 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(95 downto 64), wclk => clk_ahb, write => ra.write(1),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff3 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(63 downto 32), wclk => clk_ahb, write => ra.write(2),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
write_buff4 : syncram_2p
generic map (tech => memtech, abits => 4, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr(5 downto 2),
dataout => wdata(31 downto 0), wclk => clk_ahb, write => ra.write(3),
waddress => ra.haddr(7 downto 4), datain => ahbsi.hwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddrsp" & tost(hindex) & ": 64-bit DDR266 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
---------------------------------------------------------------------
-- LXP32 testbench package
--
-- Part of the LXP32 testbench
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Auxiliary package declaration for the LXP32 testbench
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package tb_pkg is
constant c_max_program_size: integer:=8192;
type soc_globals_type is record
rst_i: std_logic;
cpu_rst_i: std_logic;
end record;
type soc_wbs_in_type is record
cyc: std_logic;
stb: std_logic;
we: std_logic;
sel: std_logic_vector(3 downto 0);
adr: std_logic_vector(31 downto 2);
dat: std_logic_vector(31 downto 0);
end record;
type soc_wbs_out_type is record
ack: std_logic;
dat: std_logic_vector(31 downto 0);
end record;
type soc_wbm_in_type is record
ack: std_logic;
dat: std_logic_vector(31 downto 0);
end record;
type soc_wbm_out_type is record
cyc: std_logic;
stb: std_logic;
we: std_logic;
sel: std_logic_vector(3 downto 0);
adr: std_logic_vector(27 downto 2);
dat: std_logic_vector(31 downto 0);
end record;
type monitor_out_type is record
data: std_logic_vector(31 downto 0);
valid: std_logic;
end record;
procedure load_ram(
filename: string;
signal clk: in std_logic;
signal soc_in: out soc_wbs_in_type;
signal soc_out: in soc_wbs_out_type
);
procedure run_test(
filename: string;
signal clk: in std_logic;
signal globals: out soc_globals_type;
signal soc_in: out soc_wbs_in_type;
signal soc_out: in soc_wbs_out_type;
signal result: in monitor_out_type
);
end package;
|
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: alu-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 18:52:07 $
--
--------------------------------------------------------------------------
--
-- Behavioural architecture of ALU.
--
architecture behaviour of alu is
begin
alu_op: process (s1, s2, latch_en, func)
use work.bv_arithmetic.all;
variable stored_s1, stored_s2 : dlx_word;
variable temp_result : dlx_word;
variable temp_overflow : boolean;
begin
if latch_en = '1' then
stored_s1 := s1;
stored_s2 := s2;
end if;
case func is
when alu_pass_s1 =>
temp_result := stored_s1;
when alu_pass_s2 =>
temp_result := stored_s2;
when alu_and =>
temp_result := stored_s1 and stored_s2;
when alu_or =>
temp_result := stored_s1 or stored_s2;
when alu_xor =>
temp_result := stored_s1 xor stored_s2;
when alu_sll =>
temp_result := bv_sll(stored_s1, bv_to_natural(stored_s2(27 to 31)));
when alu_srl =>
temp_result := bv_srl(stored_s1, bv_to_natural(stored_s2(27 to 31)));
when alu_sra =>
temp_result := bv_sra(stored_s1, bv_to_natural(stored_s2(27 to 31)));
when alu_add =>
bv_add(stored_s1, stored_s2, temp_result, temp_overflow);
when alu_addu =>
bv_addu(stored_s1, stored_s2, temp_result, temp_overflow);
when alu_sub =>
bv_sub(stored_s1, stored_s2, temp_result, temp_overflow);
when alu_subu =>
bv_subu(stored_s1, stored_s2, temp_result, temp_overflow);
end case;
result <= temp_result after Tpd;
zero <= bit'val(boolean'pos(temp_result = dlx_word'(X"0000_0000"))) after Tpd;
negative <= temp_result(0) after Tpd;
overflow <= bit'val(boolean'pos(temp_overflow)) after Tpd;
end process alu_op;
end behaviour;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkbuf_xilinx
-- File: clkbuf_xilinx.vhd
-- Author: Marko Isomaki, Jiri GAisler - Gaisler Research
-- Description: Clock buffer generator for Xilinx devices
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
use unisim.BUFG;
-- pragma translate_on
entity clkbuf_xilinx is
generic(
buftype : integer range 0 to 3 := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkbuf_xilinx is
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal gnd : std_ulogic;
signal x : std_ulogic;
attribute syn_noclockbuf : boolean;
attribute syn_noclockbuf of x : signal is true;
begin
gnd <= '0';
buf0 : if (buftype = 0) or (buftype > 2) generate
x <= i; o <= x;
end generate;
buf1 : if buftype = 1 generate
buf : bufgmux port map(S => gnd, I0 => i, I1 => gnd, O => o);
end generate;
buf2 : if (buftype = 2) generate
buf : bufg port map(I => i, O => o);
end generate;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkmux_xilinx is
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkmux_xilinx is
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
begin
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
end architecture;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: rom_8192x32_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY rom_8192x32_tb IS
END ENTITY;
ARCHITECTURE rom_8192x32_tb_ARCH OF rom_8192x32_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
rom_8192x32_synth_inst:ENTITY work.rom_8192x32_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
library verilog;
use verilog.vl_types.all;
entity setLT is
port(
busSLT : out vl_logic_vector(31 downto 0);
busA : in vl_logic_vector(31 downto 0);
busB : in vl_logic_vector(31 downto 0);
zSLT : out vl_logic;
oSLT : out vl_logic;
cSLT : out vl_logic;
nSLT : out vl_logic
);
end setLT;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity syncram_1r1w is
generic (
addr_bits : natural := 5;
data_bits : natural := 32;
write_first : boolean := true
);
port (
clk : in std_ulogic;
we : in std_ulogic;
waddr : in std_ulogic_vector((addr_bits-1) downto 0);
wdata : in std_ulogic_vector((data_bits-1) downto 0);
re : in std_ulogic;
raddr : in std_ulogic_vector((addr_bits-1) downto 0);
rdata : out std_ulogic_vector((data_bits-1) downto 0)
);
end;
|
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <[email protected]>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: Key schedule only for 128-bit keys
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity KEYSCHED128 is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
kl_in : in STD_LOGIC_VECTOR (0 to 127);
kl_out : out STD_LOGIC_VECTOR (0 to 127);
ka_out : out STD_LOGIC_VECTOR (0 to 127)
);
end KEYSCHED128;
architecture RTL of KEYSCHED128 is
component F is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
-- f inputs
signal f1_in : STD_LOGIC_VECTOR (0 to 63);
signal f2_in : STD_LOGIC_VECTOR (0 to 63);
signal f3_in : STD_LOGIC_VECTOR (0 to 63);
signal f4_in : STD_LOGIC_VECTOR (0 to 63);
-- f outputs
signal f1_out : STD_LOGIC_VECTOR (0 to 63);
signal f2_out : STD_LOGIC_VECTOR (0 to 63);
signal f3_out : STD_LOGIC_VECTOR (0 to 63);
signal f4_out : STD_LOGIC_VECTOR (0 to 63);
-- intermediate registers
signal reg1_l : STD_LOGIC_VECTOR (0 to 63);
signal reg1_r : STD_LOGIC_VECTOR (0 to 63);
signal reg1_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg2_l : STD_LOGIC_VECTOR (0 to 63);
signal reg2_r : STD_LOGIC_VECTOR (0 to 63);
signal reg2_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg3_l : STD_LOGIC_VECTOR (0 to 63);
signal reg3_r : STD_LOGIC_VECTOR (0 to 63);
signal reg3_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg4_l : STD_LOGIC_VECTOR (0 to 63);
signal reg4_r : STD_LOGIC_VECTOR (0 to 63);
signal reg4_kl : STD_LOGIC_VECTOR (0 to 127);
-- constant keys
constant k1 : STD_LOGIC_VECTOR (0 to 63) := X"A09E667F3BCC908B";
constant k2 : STD_LOGIC_VECTOR (0 to 63) := X"B67AE8584CAA73B2";
constant k3 : STD_LOGIC_VECTOR (0 to 63) := X"C6EF372FE94F82BE";
constant k4 : STD_LOGIC_VECTOR (0 to 63) := X"54FF53A5F1D36F1C";
-- intermediate signal
signal inter : STD_LOGIC_VECTOR (0 to 127);
begin
F1 : F
port map(reset, clk, f1_in, k1, f1_out);
F2 : F
port map(reset, clk, f2_in, k2, f2_out);
F3 : F
port map(reset, clk, f3_in, k3, f3_out);
F4 : F
port map(reset, clk, f4_in, k4, f4_out);
REG : process(reset, clk)
begin
if (reset = '1') then
reg1_l <= (others=>'0');
reg1_r <= (others=>'0');
reg1_kl <= (others=>'0');
reg2_l <= (others=>'0');
reg2_r <= (others=>'0');
reg2_kl <= (others=>'0');
reg3_l <= (others=>'0');
reg3_r <= (others=>'0');
reg3_kl <= (others=>'0');
reg4_l <= (others=>'0');
reg4_r <= (others=>'0');
reg4_kl <= (others=>'0');
else
if (rising_edge(clk)) then -- rising clock edge
reg1_l <= f1_in;
reg1_r <= kl_in(64 to 127);
reg1_kl <= kl_in;
reg2_l <= f2_in;
reg2_r <= reg1_l;
reg2_kl <= reg1_kl;
reg3_l <= f3_in;
reg3_r <= inter(64 to 127);
reg3_kl <= reg2_kl;
reg4_l <= f4_in;
reg4_r <= reg3_l;
reg4_kl <= reg3_kl;
end if;
end if;
end process;
inter <= ((f2_out xor reg2_r) & reg2_l) xor reg2_kl;
-- f inputs
f1_in <= kl_in(0 to 63);
f2_in <= f1_out xor reg1_r;
f3_in <= inter(0 to 63);
f4_in <= f3_out xor reg3_r;
-- output
kl_out <= reg4_kl;
ka_out <= (f4_out xor reg4_r) & reg4_l;
end RTL;
|
-- $Id: tbd_rlink_sp1c.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_rlink_sp1c - syn
-- Description: Wrapper for rlink_core plus rlink_serport with an interface
-- compatible to the rlink_core only module.
-- NOTE: this implementation is a hack, should be redone
-- using configurations.
--
-- Dependencies: tbu_rlink_sp1c [UUT]
-- serport_uart_tx
-- serport_uart_rx
-- byte2cdata
-- cdata2byte
--
-- To test: rlink_sp1c
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-22 442 3.1 renamed and retargeted to tbu_rlink_sp1c
-- 2011-11-19 427 3.0.5 now numeric_std clean
-- 2010-12-28 350 3.0.4 use CLKDIV/CDINIT=0;
-- 2010-12-26 348 3.0.3 add RTS/CTS ports for tbu_;
-- 2010-12-24 347 3.0.2 rename: CP_*->RL->*
-- 2010-12-22 346 3.0.1 removed proc_moni, use .rlmon cmd in test bench
-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol;
-- 2010-06-06 301 2.3 use NCOMM=4 (new eop,nak commas)
-- 2010-05-02 287 2.2.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-24 281 2.2.1 use serport_uart_[tr]x directly again
-- 2010-04-03 274 2.2 add CE_USEC
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2007-11-25 98 1.1 added RP_IINT support; use entity rather arch
-- name to switch core/serport;
-- use serport_uart_[tr]x_tb to allow that UUT is a
-- [sft]sim model compiled with keep hierarchy
-- 2007-07-02 63 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.comlib.all;
use work.serport.all;
use work.simlib.all;
use work.simbus.all;
entity tbd_rlink_sp1c is -- rlink_sp1c tb design
-- implements tbd_rlink_gen
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : out slbit; -- rlink: data busy
RL_DO : out slv9; -- rlink: data out
RL_VAL : out slbit; -- rlink: data valid
RL_HOLD : in slbit; -- rlink: data hold
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv8; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
TXRXACT : out slbit -- txrx active flag
);
end entity tbd_rlink_sp1c;
architecture syn of tbd_rlink_sp1c is
constant CDWIDTH : positive := 13;
constant c_cdinit : natural := 0; -- NOTE: change in tbu_rlink_sp1c !!
signal RRI_RXSD : slbit := '0';
signal RRI_TXSD : slbit := '0';
signal RTS_N : slbit := '0';
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal CLKDIV : slv13 := slv(to_unsigned(c_cdinit,CDWIDTH));
component tbu_rlink_sp1c is -- rlink core+serport combo
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv8; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end component;
begin
UUT : tbu_rlink_sp1c
port map (
CLK => CLK,
CE_INT => CE_INT,
CE_USEC => CE_USEC,
CE_MSEC => '1',
RESET => RESET,
RXSD => RRI_RXSD,
TXSD => RRI_TXSD,
CTS_N => '0',
RTS_N => RTS_N,
RB_MREQ_aval => RB_MREQ_aval,
RB_MREQ_re => RB_MREQ_re,
RB_MREQ_we => RB_MREQ_we,
RB_MREQ_initt=> RB_MREQ_initt,
RB_MREQ_addr => RB_MREQ_addr,
RB_MREQ_din => RB_MREQ_din,
RB_SRES_ack => RB_SRES_ack,
RB_SRES_busy => RB_SRES_busy,
RB_SRES_err => RB_SRES_err,
RB_SRES_dout => RB_SRES_dout,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
UARTRX : serport_uart_rx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RRI_TXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => open,
RXACT => RXACT
);
UARTTX : serport_uart_tx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
TXSD => RRI_RXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
TXRXACT <= RXACT or TXBUSY;
B2CD : byte2cdata -- byte stream -> 9bit comma,data
generic map (
CPREF => c_rlink_cpref,
NCOMM => c_rlink_ncomm)
port map (
CLK => CLK,
RESET => RESET,
DI => RXDATA,
ENA => RXVAL,
BUSY => open,
DO => RL_DO,
VAL => RL_VAL,
HOLD => RL_HOLD
);
CD2B : cdata2byte -- 9bit comma,data -> byte stream
generic map (
CPREF => c_rlink_cpref,
NCOMM => c_rlink_ncomm)
port map (
CLK => CLK,
RESET => RESET,
DI => RL_DI,
ENA => RL_ENA,
BUSY => RL_BUSY,
DO => TXDATA,
VAL => TXENA,
HOLD => TXBUSY
);
proc_moni: process
variable oline : line;
variable rts_last : slbit := '0';
variable ncycle : integer := 0;
begin
loop
wait until rising_edge(CLK); -- check at end of clock cycle
if RTS_N /= rts_last then
writetimestamp(oline, SB_CLKCYCLE, ": rts ");
write(oline, string'(" RTS_N "));
write(oline, rts_last, right, 1);
write(oline, string'(" -> "));
write(oline, RTS_N, right, 1);
write(oline, string'(" after "));
write(oline, ncycle, right, 5);
write(oline, string'(" cycles"));
writeline(output, oline);
rts_last := RTS_N;
ncycle := 0;
end if;
ncycle := ncycle + 1;
end loop;
end process proc_moni;
end syn;
|
----------------------------------------------------------------------------------
-- Company: @Home
-- Engineer: Zoltan Pekic ([email protected])
--
-- Create Date: 11:26:14 02/14/2016
-- Design Name:
-- Module Name: counterwithlimit - Behavioral
-- Project Name: Alarm Clock
-- Target Devices: Mercury FPGA + Baseboard (http://www.micro-nova.com/mercury/)
-- Tool versions: Xilinx ISE 14.7 (nt64)
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counterwithlimit is
Port ( clock : in STD_LOGIC;
clear : in STD_LOGIC;
up : in STD_LOGIC;
down : in STD_LOGIC;
set : in STD_LOGIC;
set_value : in STD_LOGIC_VECTOR(3 downto 0);
limit : in STD_LOGIC_VECTOR (3 downto 0);
out_count : out STD_LOGIC_VECTOR (3 downto 0);
out_zero : out STD_LOGIC;
out_limit : out STD_LOGIC);
end counterwithlimit;
architecture Behavioral of counterwithlimit is
signal cnt: unsigned(3 downto 0);
begin
out_count <= std_logic_vector(cnt);
out_zero <= '1' when cnt = X"0" else '0';
out_limit <= '1' when cnt = unsigned(limit) else '0';
count: process(clock, clear, set, up, down)
begin
if clear = '1' then
cnt <= "0000";
else
if (clock'event and clock = '1') then
if (set = '1') then
cnt <= unsigned(set_value); -- setting to a value keyed in
else
if up = '1' then
if cnt >= unsigned(limit) then
cnt <= "0000";
else
cnt <= cnt + 1;
end if;
end if;
if down = '1' then
if cnt = "0000" then
cnt <= unsigned(limit);
else
cnt <= cnt - 1;
end if;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
package FIFO_PKG is
procedure AVERAGE_SAMPLES;
procedure AVERAGE_SAMPLES (constant a : in integer := 0; signal b : in std_logic := 'X'; variable c : in std_logic := 'X');
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable c : in std_logic := 'X';
some_sig : inout t_some_type := '0');
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable ccc : in std_logic := 'X';
some_sig : inout t_some_type := '0');
end package FIFO_PKG;
package body FIFO_PKG is
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable c : in std_logic := 'X') is
begin
end procedure AVERAGE_SAMPLES;
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable ccc : in std_logic := 'X') is
begin
end procedure AVERAGE_SAMPLES;
end package body FIFO_PKG;
architecture RTL of ENT is
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable c : in std_logic := 'X') is
begin
end procedure AVERAGE_SAMPLES;
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable ccc : in std_logic := 'X') is
begin
end procedure AVERAGE_SAMPLES;
begin
TEST_PROCESS : process
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable c : in std_logic := 'X') is
begin
end procedure AVERAGE_SAMPLES;
-- Violations below this line
procedure AVERAGE_SAMPLES (
constant a : in integer := 0;
signal b : in std_logic := 'X';
variable ccc : in std_logic := 'X') is
begin
end procedure AVERAGE_SAMPLES;
begin
end process TEST_PROCESS;
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1074.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n04i01074ent IS
END c06s04b00x00p03n04i01074ent;
ARCHITECTURE c06s04b00x00p03n04i01074arch OF c06s04b00x00p03n04i01074ent IS
BEGIN
TESTING: PROCESS
constant C1 : STRING := "ABCDEFGH";
variable V1 : CHARACTER;
variable q : integer := 9;
BEGIN
V1 := C1(1);
assert V1 = 'A'
report "FAIL: first index";
V1 := C1(q); -- should result in index error
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n04i01074- Index value should belong to the range of the corresponding index range of the array."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n04i01074arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1074.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n04i01074ent IS
END c06s04b00x00p03n04i01074ent;
ARCHITECTURE c06s04b00x00p03n04i01074arch OF c06s04b00x00p03n04i01074ent IS
BEGIN
TESTING: PROCESS
constant C1 : STRING := "ABCDEFGH";
variable V1 : CHARACTER;
variable q : integer := 9;
BEGIN
V1 := C1(1);
assert V1 = 'A'
report "FAIL: first index";
V1 := C1(q); -- should result in index error
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n04i01074- Index value should belong to the range of the corresponding index range of the array."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n04i01074arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1074.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n04i01074ent IS
END c06s04b00x00p03n04i01074ent;
ARCHITECTURE c06s04b00x00p03n04i01074arch OF c06s04b00x00p03n04i01074ent IS
BEGIN
TESTING: PROCESS
constant C1 : STRING := "ABCDEFGH";
variable V1 : CHARACTER;
variable q : integer := 9;
BEGIN
V1 := C1(1);
assert V1 = 'A'
report "FAIL: first index";
V1 := C1(q); -- should result in index error
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n04i01074- Index value should belong to the range of the corresponding index range of the array."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n04i01074arch;
|
library ieee;
use ieee.std_logic_1164.all;
-- Module Generates Video Sync signals for Video Monitor Interface
-- RGB and Sync outputs tie directly to monitor connector pins
entity vga_timing_generator is
generic (
H_COUNT_MAX: integer := 800;
V_COUNT_MAX: integer := 525
);
port(
vga_clock_in: in std_logic;
horiz_sync_out: out std_logic;
vert_sync_out : out std_logic;
video_on: out std_logic;
pixel_row: out integer range 0 to V_COUNT_MAX;
pixel_column: out integer range 0 to H_COUNT_MAX
);
end vga_timing_generator;
architecture behavior of vga_timing_generator is
-- Horizontal Timing constants
constant H_PIXELS_COUNT: integer := 640;
constant H_FRONT_PORCH_LENGTH: integer := 16;
constant H_SYNC_PULSE_LENGTH: integer := 96;
constant H_COUNT_SYNC_LOW: integer := H_PIXELS_COUNT + H_FRONT_PORCH_LENGTH;
constant H_COUNT_SYNC_HIGH: integer := H_COUNT_SYNC_LOW + H_SYNC_PULSE_LENGTH;
-- Vertical Timing constants
constant V_PIXELS_COUNT: integer := 480;
constant V_FRONT_PORCH_LENGTH: integer := 9; -- 11;
constant V_SYNC_PULSE_LENGTH: integer := 2;
constant V_COUNT_SYNC_LOW: integer := V_PIXELS_COUNT + V_FRONT_PORCH_LENGTH;
constant V_COUNT_SYNC_HIGH: integer := V_COUNT_SYNC_LOW + V_SYNC_PULSE_LENGTH;
signal horiz_sync, vert_sync: std_logic;
signal video_on_v, video_on_h : std_logic;
signal h_count: integer range 0 to H_COUNT_MAX;
signal v_count: integer range 0 to V_COUNT_MAX;
begin
-- video_on is high only when RGB pixel data is being displayed
-- used to blank color signals at screen edges during retrace
video_on <= video_on_H and video_on_V;
process
begin
wait until rising_edge(vga_clock_in);
--Generate Horizontal and Vertical Timing signals for Video signal
-- H_count counts pixels (#pixels across + extra time for sync signals)
--
-- Horiz_sync ------------------------------------__________--------
-- H_count 0 #pixels sync low end
if (h_count = H_COUNT_MAX) then
h_count <= 0;
else
h_count <= h_count + 1;
end if;
--Generate Horizontal Sync signal using H_count
if (h_count <= H_COUNT_SYNC_HIGH) and (h_count >= H_COUNT_SYNC_LOW) then
horiz_sync <= '0';
else
horiz_sync <= '1';
end if;
--V_count counts rows of pixels (#pixel rows down + extra time for V sync signal)
--
-- Vert_sync -----------------------------------------------_______------------
-- V_count 0 last pixel row V sync low end
--
if (v_count >= V_COUNT_MAX) and (h_count >= H_COUNT_SYNC_LOW) then
v_count <= 0;
elsif (h_count = H_COUNT_SYNC_LOW) then
v_count <= v_count + 1;
end if;
-- Generate Vertical Sync signal using V_count
if (v_count <= V_COUNT_SYNC_HIGH) and (v_count >= V_COUNT_SYNC_LOW) then
vert_sync <= '0';
else
vert_sync <= '1';
end if;
-- Generate Video on Screen signals for Pixel Data
-- Video on = 1 indicates pixel are being displayed
-- Video on = 0 retrace - user logic can update pixel
-- memory without needing to read memory for display
if (h_count < H_PIXELS_COUNT) then
video_on_h <= '1';
pixel_column <= h_count;
else
video_on_h <= '0';
end if;
if (v_count <= V_PIXELS_COUNT) then
video_on_v <= '1';
pixel_row <= v_count;
else
video_on_v <= '0';
end if;
-- Put all video signals through DFFs to eliminate any small timing
-- delays that cause a blurry image
horiz_sync_out <= horiz_sync;
vert_sync_out <= vert_sync;
end process;
end Behavior;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => out1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net1,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net3
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net3,
G => vbias4,
S => gnd
);
end simple;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => out1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net1,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net3
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net3,
G => vbias4,
S => gnd
);
end simple;
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY mux_2x1_busInput IS
GENERIC(size: INTEGER);
PORT(a, b: IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
ctrl: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0));
END mux_2x1_busInput;
ARCHITECTURE dataflow OF mux_2x1_busInput IS
BEGIN
q<=a when ctrl='0' else b;
END dataflow; |
-- file : test_fb.vhdl
-- created by Yann Guidon / ygdes.com
-- version 2010/06/05
library work;
use work.fb_ghdl.all;
entity test_fb is
end test_fb;
architecture test of test_fb is
begin
process
begin
report " x=" & integer'image(fbx);
report " y=" & integer'image(fby);
report "xv=" & integer'image(fbxv);
report "yv=" & integer'image(fbyv);
-- Warning : fbp was available in a previous
-- version of the code, it is now useless
-- affiche un pixel vert+bleu
-- fbp.all := 65535;
wait;
end process;
end test;
|
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
begin
end architecture RTL;
|
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
begin
end architecture RTL;
|
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
begin
end architecture RTL;
|
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
begin
end architecture RTL;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 22-02-2016
-- Module Name: process.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity process_t is
end entity;
architecture arch_process_t of process_t is
signal a, b : std_logic := '0';
signal y_normal, y_fun : std_logic := '0';
signal w_normal, w_fun, w_var : std_logic := '0';
begin
a <= '0', '1' after 500 ns, '0' after 1000 ns;
b <= '0';
-- checkout when w_normal signal updated.
process (a, b, y_normal)
begin
y_normal <= a xor b;
w_normal <= y_normal;
end process;
-- checkout when w_fun signal updated.
process (a, b)
begin
y_fun <= a xor b;
w_fun <= y_fun;
end process;
-- checkout when w_var signal updated.
process (a, b)
variable y_var : std_logic;
begin
y_var := a xor b;
w_var <= y_var;
end process;
end architecture arch_process_t;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: virage_simprims
-- File: virage_simprims.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Simple simulation models for VIRAGE RAMs
-----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
package virage_simprims is
component virage_syncram_sim
generic ( abits : integer := 10; dbits : integer := 8 );
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end component;
-- synchronous 2-port ram
component virage_2pram_sim
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end component;
component virage_dpram_sim
generic (
abits : integer := 8;
dbits : integer := 32
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end component;
end;
-- 1-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_syncram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end;
architecture behavioral of virage_syncram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clk, oe, me)
variable memarr : mem;-- := (others => (others => '0'));
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clk) and (me = '1') and not is_x(addr) then
if (we = '1') then memarr(to_integer(unsigned(addr))) := di; end if;
doint := memarr(to_integer(unsigned(addr)));
end if;
-- if (me and oe) = '1' then do <= doint;
if oe = '1' then do <= doint;
else do <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous 2-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_2pram_sim is
generic (
abits : integer := 10;
dbits : integer := 8;
words : integer := 1024
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end;
architecture behavioral of virage_2pram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (words-1)) of word;
begin
main : process(clka, clkb, oeb, mea, meb, wea)
variable memarr : mem;
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra)) mod words) := dia; end if;
end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
doint := memarr(to_integer(unsigned(addrb)) mod words);
end if;
if oeb = '1' then dob <= doint;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous dual-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_dpram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end;
architecture behavioral of virage_dpram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clka, oea, mea, clkb, oeb, meb)
variable memarr : mem;
variable dointa, dointb : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra))) := dia; end if;
dointa := memarr(to_integer(unsigned(addra)));
end if;
if oea = '1' then doa <= dointa;
else doa <= (others => 'Z'); end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
if (web = '1') then memarr(to_integer(unsigned(addrb))) := dib; end if;
dointb := memarr(to_integer(unsigned(addrb)));
end if;
if oeb = '1' then dob <= dointb;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_128x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_128x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 7, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_256x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_256x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 8, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x38cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(37 downto 0);
do : out std_logic_vector(37 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x38cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 38)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_1024x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_1024x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 10, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_2048x32cm8sw0ab is
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_2048x32cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 11, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_4096x36cm8sw0ab is
port (
addr, taddr : in std_logic_vector(11 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(35 downto 0);
do : out std_logic_vector(35 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_4096x36cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 12, dbits => 36)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_16384x8cm16sw0 is
port (
addr : in std_logic_vector(13 downto 0);
clk : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
me, oe, we : in std_logic
);
end;
architecture behavioral of hdss1_16384x8cm16sw0 is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 14, dbits => 8)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
-- 2-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x40cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(39 downto 0);
dob : out std_logic_vector(39 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x40cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 40, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_168x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_168x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 168)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
-- dual-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_64x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_64x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 6, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_128x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_128x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 7, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_256x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_256x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 8, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x38cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(37 downto 0);
dib, tdib : in std_logic_vector(37 downto 0);
doa, dob : out std_logic_vector(37 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x38cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 38)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_8192x8cm16sw0ab is
port (
addra, taddra : in std_logic_vector(12 downto 0);
addrb, taddrb : in std_logic_vector(12 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(7 downto 0);
dib, tdib : in std_logic_vector(7 downto 0);
doa, dob : out std_logic_vector(7 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_8192x8cm16sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 13, dbits => 8)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
-- pragma translate_on
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
clk : in std_ulogic;
-- onBoard Cellular RAM, Numonyx StrataFlash and Numonyx Quad Flash
MemOE : out std_ulogic;
MemWR : out std_ulogic;
RamAdv : out std_ulogic;
RamCS : out std_ulogic;
RamClk : out std_ulogic;
RamCRE : out std_ulogic;
RamLB : out std_ulogic;
RamUB : out std_ulogic;
RamWait : out std_ulogic;
FlashRp : out std_ulogic;
FlashCS : out std_ulogic;
QuadSpiFlashCS : out std_ulogic;
QuadSpiFlashSck : out std_ulogic;
QuadSpiFlashDB : inout std_logic_vector(0 downto 0);
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
-- 7 segment display
--seg : out std_logic_vector(7 downto 0);
--an : out std_logic_vector(3 downto 0);
-- LEDs
led : out std_logic_vector(7 downto 0);
-- Switches
sw : in std_logic_vector(7 downto 0);
-- Buttons
btn : in std_logic_vector(4 downto 0); -- reset on btn0
-- VGA Connector
--vgaRed : out std_logic_vector(2 downto 0);
--vgaGreen : out std_logic_vector(2 downto 0);
--vgaBlue : out std_logic_vector(2 downto 1);
--Hsync : out std_ulogic;
--Vsync : out std_ulogic;
-- 12 pin connectors
--ja : inout std_logic_vector(7 downto 0);
--jb : inout std_logic_vector(7 downto 0);
--jc : inout std_logic_vector(7 downto 0);
--jd : inout std_logic_vector(7 downto 0);
-- SMSC ethernet PHY
PhyRstn : out std_ulogic;
PhyCrs : in std_ulogic;
PhyCol : in std_ulogic;
PhyClk25Mhz : out std_ulogic;
PhyTxd : out std_logic_vector(3 downto 0);
PhyTxEn : out std_ulogic;
PhyTxClk : in std_ulogic;
PhyTxEr : out std_ulogic;
PhyRxd : in std_logic_vector(3 downto 0);
PhyRxDv : in std_ulogic;
PhyRxEr : in std_ulogic;
PhyRxClk : in std_ulogic;
PhyMdc : out std_ulogic;
PhyMdio : inout std_logic;
-- Pic USB-HID interface
--PS2KeyboardData : inout std_logic;
--PS2KeyboardClk : inout std_logic;
--PS2MouseData : inout std_logic;
--PS2MouseClk : inout std_logic;
--PicGpio : out std_logic_vector(1 downto 0);
-- USB-RS232 interface
RsRx : in std_logic;
RsTx : out std_logic
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 100000; -- CLK input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
led(7 downto 4) <= (others =>'0'); -- unused leds off
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
rst0 : rstgen generic map (acthigh => 1)
port map (btn(0), clkm, lock, rstn, rstraw);
lock <= cgo.clklock;
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (clk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
led(3) <= not dbgo(0).error;
led(2) <= not dsuo.active;
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (RsRx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (RsTx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, iomask => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,srbanks=>1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "01";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 26)
port map (address, memo.address(26 downto 1));
oen_pad : outpad generic map (tech => padtech)
port map (MemOE, memo.oen);
cs_pad : outpad generic map (tech => padtech)
port map (RamCS, memo.ramsn(0));
lb_pad : outpad generic map (tech => padtech)
port map (RamLB, memo.mben(0));
ub_pad : outpad generic map (tech => padtech)
port map (RamUB, memo.mben(1));
wri_pad : outpad generic map (tech => padtech)
port map (MemWR, memo.writen);
fce_pad : outpad generic map (tech => padtech)
port map (FlashCS, memo.romsn(0));
frp_pad : outpad generic map (tech => padtech)
port map (FlashRp, memo.writen);
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(23 downto 16),
memo.bdrive(1), memi.data(23 downto 16));
bdr2 : iopadv generic map (tech => padtech, width => 8)
port map (data(15 downto 8), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
RamCRE <= '0';
RamClk <= '0';
RamAdv <= '0';
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- Console UART.
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
-- The USB UART is curently mapped to ahbuart.
-- serrx_pad : inpad generic map (tech => padtech) port map (RsRx, rxd1);
-- sertx_pad : outpad generic map (tech => padtech) port map (RsTx, txd1);
-- led(0) <= not rxd1;
-- led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
PhyRstn<=rstn;
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (PhyMdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (PhyTxClk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (PhyRxClk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (PhyRxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (PhyRxDv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (PhyRxEr, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (PhyCol, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (PhyCrs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (PhyTxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (PhyTxEn, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (PhyTxEr, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (PhyMdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- Test report module, only used for simulation ----------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Digilent NEXYS 3 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : pcie_command_send_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
--
-- Counter
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.numeric.all;
entity Counter is
generic (
DEPTH : positive:=8
);
port (
clk_i : in std_logic; -- Clock
rst_i : in std_logic; -- Reset
ena_i : in std_logic; -- Input Enable
count_o : out std_logic_vector(clog2(DEPTH)-1 downto 0); -- Counter value
last_o : out std_logic -- Last value
);
end entity Counter;
architecture RTL of Counter is
constant AWIDTH : positive:=clog2(DEPTH);
signal count : unsigned(AWIDTH-1 downto 0):=(others => '0');
begin
count_p:
process (clk_i)
begin
if rising_edge(clk_i) then
last_o <= '0';
if rst_i='1' then
count <= (others => '0');
else
if ena_i='1' then
if count < DEPTH-1 then
count <= count + 1;
if count = DEPTH-2 then
last_o <= '1';
end if;
else
count <= (others => '0');
end if;
end if;
end if;
end if;
end process count_p;
count_o <= std_logic_vector(count);
end architecture RTL;
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity qcounter is
generic (
buswidth : integer := 32
);
port (
obus: out std_logic_vector (buswidth-1 downto 0);
ibus: in std_logic_vector (buswidth-1 downto 0);
quada: in std_logic;
quadb: in std_logic;
index: in std_logic;
loadccr: in std_logic;
readccr: in std_logic;
readcount: in std_logic;
countclear: in std_logic;
timestamp: in std_logic_vector (15 downto 0);
indexmask: in std_logic;
filterrate: in std_logic;
clk: in std_logic
);
end qcounter;
architecture behavioral of qcounter is
signal count: std_logic_vector (15 downto 0);
signal up: std_logic;
signal down: std_logic;
signal countlatch: std_logic_vector (15 downto 0);
signal timestamplatch: std_logic_vector (15 downto 0);
signal quadadel: std_logic;
signal quada1: std_logic;
signal quada2: std_logic;
signal quadacnt: std_logic_vector (3 downto 0);
signal quadafilt: std_logic;
signal quadbdel: std_logic;
signal quadb1: std_logic;
signal quadb2: std_logic;
signal quadbcnt: std_logic_vector (3 downto 0);
signal quadbfilt: std_logic;
signal indexdel: std_logic;
signal index1: std_logic;
signal index2: std_logic;
signal indexdet: std_logic;
signal indexcnt: std_logic_vector (3 downto 0);
signal indexfilt: std_logic;
signal qcountup: std_logic;
signal qcountdown: std_logic;
signal udcountup: std_logic;
signal udcountdown: std_logic;
signal doclear: std_logic;
signal clearonindex: std_logic; -- ccr register bits...
signal latchonindex:std_logic;
signal justonce: std_logic;
signal abgateindex: std_logic;
signal indexsrc: std_logic;
signal quadfilter: std_logic;
signal countermode: std_logic;
signal quaderror: std_logic;
signal indexpol: std_logic;
signal fixedindexmask: std_logic;
signal indexmaskpol: std_logic;
signal useindexmask: std_logic;
signal abmaskpol: std_logic;
signal flimit: std_logic_vector(3 downto 0);
begin
aqcounter: process (clk,abgateindex, indexpol, indexdel, abmaskpol,
quadadel, quadbdel, indexmaskpol, indexmask,
quadfilter, countermode, doclear, quada2,
quada1, quadb2, quadb1, index1, index2,
useindexmask, readcount, timestamplatch, count,
readccr, countlatch, quaderror, justonce,
clearonindex, latchonindex)
begin
-- new index logic 02/09/2006 PCW
if abgateindex = '0' then -- not gated by A,B
if indexpol = '1' then
indexsrc <= indexdel;
else
indexsrc <= not indexdel;
end if;
else -- gated by A,B
if indexpol = '1' then -- normal index
if abmaskpol = '1' then
indexsrc <= quadadel and quadbdel and indexdel; -- enable by A,B high
else
indexsrc <= (not (quadadel or quadbdel)) and indexdel; -- enable by A,B low
end if;
else -- inverted index
if abmaskpol = '1' then
indexsrc <= quadadel and quadbdel and (not indexdel); -- enable by A,B high
else
indexsrc <= (not (quadadel or quadbdel)) and (not indexdel);-- enable by A,B low
end if;
end if;
end if;
if indexmaskpol = '1' then
fixedindexmask <= indexmask;
else
fixedindexmask <= not indexmask;
end if;
if quadfilter = '1' then
flimit <= "1111";
else
flimit <= "0011";
end if;
if countermode = '0' and doclear = '0' and (
(quada2 = '0' and quada1 = '1' and quadb2 = '0' and quadb1 = '0') or
(quada2 = '0' and quada1 = '0' and quadb2 = '1' and quadb1 = '0') or
(quada2 = '1' and quada1 = '1' and quadb2 = '0' and quadb1 = '1') or
(quada2 = '1' and quada1 = '0' and quadb2 = '1' and quadb1 = '1')) then
qcountup <= '1';
else
qcountup <= '0';
end if;
if (countermode = '1' and doclear = '0' and
quadb2 = '1' and quada2 = '0' and quada1 = '1') then -- up down mode: count up on rising edge of A when B is high
udcountup <= '1';
else
udcountup <= '0';
end if;
if countermode = '0' and doclear = '0' and (
(quada2 = '0' and quada1 = '0' and quadb2 = '0' and quadb1 = '1') or
(quada2 = '0' and quada1 = '1' and quadb2 = '1' and quadb1 = '1') or
(quada2 = '1' and quada1 = '0' and quadb2 = '0' and quadb1 = '0') or
(quada2 = '1' and quada1 = '1' and quadb2 = '1' and quadb1 = '0')) then
qcountdown <= '1';
else
qcountdown <= '0';
end if;
if (countermode = '1' and doclear = '0' and
quadb2 = '0' and quada2 = '0' and quada1 = '1') then
udcountdown <= '1';
else
udcountdown <= '0';
end if;
if rising_edge(clk) then
quadadel <= quada;
quada1 <= quadafilt;
quada2 <= quada1;
quadbdel <= quadb;
quadb1 <= quadbfilt;
quadb2 <= quadb1;
indexdel <= index;
index1 <= indexfilt;
index2 <= index1;
if filterrate = '1' then
-- deadended counter for A input filter --
if (quadadel = '1') and (quadacnt < flimit) then
quadacnt <= quadacnt + 1;
end if;
if (quadadel = '0') and (quadacnt /= 0) then
quadacnt <= quadacnt -1;
end if;
if quadacnt >= flimit then
quadafilt<= '1';
end if;
if quadacnt = 0 then
quadafilt<= '0';
end if;
-- deadended counter for A input filter --
if (quadbdel = '1') and (quadbcnt < flimit ) then
quadbcnt <= quadbcnt + 1;
end if;
if (quadbdel = '0') and (quadbcnt /= 0) then
quadbcnt <= quadbcnt -1;
end if;
if quadbcnt >= flimit then
quadbfilt<= '1';
end if;
if quadbcnt = 0 then
quadbfilt <= '0';
end if;
-- deadended counter for index input filter --
if (indexsrc = '1') and (indexcnt < flimit ) then
indexcnt <= indexcnt + 1;
end if;
if (indexsrc = '0') and (indexcnt /= 0) then
indexcnt <= indexcnt -1;
end if;
if indexcnt >= flimit then
indexfilt<= '1';
end if;
if indexcnt = 0 then
indexfilt<= '0';
end if;
end if;
if (countclear = '1') or
((clearonindex = '1') and (indexdet = '1')) then -- rising edge of conditioned index
doclear <= '1';
if justonce = '1' then
clearonindex <= '0';
end if;
else
doclear <= '0';
end if;
if ((latchonindex = '1') and (indexdet = '1') ) then -- rising edge of conditioned index
countlatch <= count;
if justonce = '1' then
latchonindex <= '0';
end if;
end if;
if countermode = '0' and (
(quada2 = '0' and quada1 = '1' and quadb2 = '0' and quadb1 = '1') or -- any time both a,b change at same time
(quada2 = '1' and quada1 = '0' and quadb2 = '1' and quadb1 = '0') or -- indicates a quadrature count error
(quada2 = '0' and quada1 = '1' and quadb2 = '1' and quadb1 = '0') or
(quada2 = '1' and quada1 = '0' and quadb2 = '0' and quadb1 = '1')) then
quaderror <= '1';
end if;
if up /= down then
timestamplatch <= timestamp; -- time stamp whenever we count
if up = '1' then
count <= count + 1;
else
count <= count - 1;
end if;
end if;
if doclear = '1' then
count <= x"0000";
end if;
if loadccr = '1' then
quaderror <= ibus(15);
abmaskpol <= ibus(14);
-- latchonprobe (bit 13);
-- probepol (bit 12);
quadfilter <= ibus(11);
countermode <= ibus(10);
useindexmask <= ibus(9);
indexmaskpol <= ibus(8);
abgateindex <= ibus(7);
justonce <= ibus(6);
clearonindex <= ibus(5);
latchonindex <= ibus(4);
indexpol <= ibus(3);
end if;
end if; --(clock edge)
if (index1 = '1') and (index2 = '0') and ((fixedindexmask = '1') or (useindexmask = '0')) then
indexdet <= '1';
else
indexdet <= '0';
end if;
if (qcountup = '1' or udcountup = '1' ) and doclear = '0' then
up <= '1';
else
up <= '0';
end if;
if (qcountdown = '1' or udcountdown = '1' ) and doclear = '0' then
down <= '1';
else
down <= '0';
end if;
obus <= (others => 'Z');
if (readcount = '1') then
obus(31 downto 16) <= timestamplatch;
obus(15 downto 0) <= count;
end if;
if (readccr = '1') then
obus(31 downto 16) <= countlatch;
obus(15) <= quaderror;
obus(14) <= abmaskpol;
obus(11) <= quadfilter;
obus(10) <= countermode;
obus(9) <= useindexmask;
obus(8) <= indexmaskpol;
obus(7) <= abgateindex;
obus(6) <= justonce;
obus(5) <= clearonindex;
obus(4) <= latchonindex;
obus(3) <= indexpol;
obus(2) <= index1;
obus(1) <= quadb1;
obus(0) <= quada1;
end if;
end process;
end behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2263.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p11n01i02263ent IS
END c07s02b06x00p11n01i02263ent;
ARCHITECTURE c07s02b06x00p11n01i02263arch OF c07s02b06x00p11n01i02263ent IS
BEGIN
TESTING: PROCESS
variable V1,V2,V3 : Integer ;
variable A : Integer := 10 ;
variable B : Integer := 5 ;
BEGIN
V1 := (-A)/B ;
V2 := -(A/B) ;
assert NOT(V1 = V2)
report "***PASSED TEST: c07s02b06x00p11n01i02263"
severity NOTE;
assert (V1 = V2)
report "***FAILED TEST: c07s02b06x00p11n01i02263 - Integer division satisfies the following identity: (-A)/B = -(A/B) = A/(-B)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p11n01i02263arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2263.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p11n01i02263ent IS
END c07s02b06x00p11n01i02263ent;
ARCHITECTURE c07s02b06x00p11n01i02263arch OF c07s02b06x00p11n01i02263ent IS
BEGIN
TESTING: PROCESS
variable V1,V2,V3 : Integer ;
variable A : Integer := 10 ;
variable B : Integer := 5 ;
BEGIN
V1 := (-A)/B ;
V2 := -(A/B) ;
assert NOT(V1 = V2)
report "***PASSED TEST: c07s02b06x00p11n01i02263"
severity NOTE;
assert (V1 = V2)
report "***FAILED TEST: c07s02b06x00p11n01i02263 - Integer division satisfies the following identity: (-A)/B = -(A/B) = A/(-B)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p11n01i02263arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2263.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p11n01i02263ent IS
END c07s02b06x00p11n01i02263ent;
ARCHITECTURE c07s02b06x00p11n01i02263arch OF c07s02b06x00p11n01i02263ent IS
BEGIN
TESTING: PROCESS
variable V1,V2,V3 : Integer ;
variable A : Integer := 10 ;
variable B : Integer := 5 ;
BEGIN
V1 := (-A)/B ;
V2 := -(A/B) ;
assert NOT(V1 = V2)
report "***PASSED TEST: c07s02b06x00p11n01i02263"
severity NOTE;
assert (V1 = V2)
report "***FAILED TEST: c07s02b06x00p11n01i02263 - Integer division satisfies the following identity: (-A)/B = -(A/B) = A/(-B)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p11n01i02263arch;
|
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arr1DTgm2x2XGFwofS3KAWTtelllIMKajryQ3MIvD/Td0jMgayEVj/sI5OAGYTd07Ii3HSJTU7k8
9UVH9V/n7wo1UnZsYmiZ9bsF/nnApgDfmUnDvfNQW/ZF77fLFaC+eHJryDA+RAehbowj/uG5KFTX
WqqPsOjwyRfDI7ANxi+WtJdbvB39dGSDPYXncMYHNNFK959SkMKOVg91MhswMzvq5BfNVtmz1FPd
9dNWWJtK4lLFsU+ct36avX4yZ/jlSbUmOyR0LzKYQMzZFbG6ysncM6Z+4/8EibbumHshC3mfBvJb
vS454B4YXltOrZWbxzn/IXUEdqGZcUPFgJd8swMavI5MkFca5DQ6j9PDSW9749yzEo0AZ1KzjUAZ
zqCfWFmWXryWsAM3bp6KDhy8x0FN1ZM/QZIhvhm8/c6tMUalePXNm7W+5+fZsSCbWvQWQQ9LG2cO
AG77N01CuD289a/JzhbdX4fgfXJYhoRPw1784GCWdInHGS0TMZnbjVgCjKdT4lFSmhvuJ6AHp6Yu
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OUMyVbblJIH2ktGAl/niKjc/hJd6RPJ93Gr7/JDcCVOt0QopXhDOQ/yQff41HpL5t1tW3BpaU0VU
1p4HfEWQbntG7tLW34gcDS3qbANqNmzmCr88Q51zddVw+hTqOscK7C9A7X/1Snwnavsgq5I1KECg
apKfZl6hw1SR6s4qCE5zNER/ERgk4nX4lGEGhC5pqePuEa76ok0QNJpa9wndF88A+7ACrXBYPMjT
/i8QrMvVjjsP1uuc9yUZ6d2XT6PIvyuZ8vgAr4dOIKY6KbYYJvMifCSAcs8Pm5lek8SAldBlr15k
PFz7a0F15XF0dJyxHRzjQwitAqyU065cmXnL550GguYV/KdASg7WLbJjuJmh8KPQbzBsBM3+o7mg
YLiEVCwt/uMN1nTYjbqwdjsEX3UT4xWvlzHv/UDA7myIjshl2ejRnECcQcTPE19gER7RpuUOC2e1
sPyGFaxNP8YWdu7lqTfYR8qc46zoDVj13PdAjVF7bXCJZCK+ihAxZBmDwmyrK3BTlTZJj+Qjs2JW
pyaGhDYVGaBIhy4b/hETnXL+S9gw38HBBlsOTEoQyR7zluPBphxl272SGbyGmMmdB83ASz+cFmYc
3tIqlnTTsIpg9yibtb43+tNZyx1PQisJO/PPB8yLPQOM/2E7w0a4oFp5Va49gqnmh0n9wCa9wgUu
ARFM/M/HsK7v2yNjikQGmVsN5Rtg+tMFttSgIWCSE3FaXJHyGFshFOh/V/eiBOJej1KDuAl55I7V
YaZyCYZyxZU/Tbmk/4bdhsvc9CPoQ5/bf/KXrKUwYcMRvFxJibqdFoM7qW2buWzRg1M6s4gVG+L+
c5Kubfdo4IIO1rCvc8slJbObt+VDUFjXeIvrRpRudEauk8muYPn/myJqwd/BVM4hCLLDlP98r+dx
WWGhmfm/H6kiuMpPrX5Do+IDhp34U5h1Zniz9GFfNdVlg9v0U2eqqI7rbCQxpqGsWg1/f4xkY5Lw
vtxiDfdAC2L2wwJUUANjhEqkL5PaHa3bf/pk
`protect end_protected
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use gaisler.jtagtst.all;
library dare;
use work.config.all; -- configuration
entity testbench_netlist is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 1000; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 20; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2; -- number of ram banks
testen : integer := 0;
scanen : integer := 0;
testrst : integer := 0;
testoen : integer := 0
);
end;
architecture behav of testbench_netlist is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal cb : std_logic_vector(15 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdogn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_ulogic := '0';
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal roen, roout, nandout, promedac : std_ulogic;
constant lresp : boolean := false;
signal gnd : std_logic_vector(3 downto 0);
signal clksel : std_logic_vector(1 downto 0);
signal promwidth: std_logic_vector(1 downto 0);
signal spw_clksel : std_logic_vector(1 downto 0);
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
begin
-- clock and reset
test <= '0' when testen = 0 else '1';
rxd1 <= '1' when (testen = 1) and (testoen = 1) else
'0' when (testen = 1) and (testoen = 0) else txd1;
dsuen <= '1' when (testen = 1) and (testrst = 1) else
'0' when (testen = 1) and (testrst = 0) else '1';
dsubre <= '1' when (testen = 1) and (scanen = 1) else
'0' when (testen = 1) and (scanen = 0) else '0';
clksel <= "00";
spw_clksel <= "00";
error <= 'H';
gnd <= "0000";
clk <= not clk after ct * 1 ns;
spw_clk <= not spw_clk after 10 ns;
rst <= dsurst;
bexcn <= '1'; wdogn <= 'H';
gpio(2 downto 0) <= "HHL";
-- gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
gpio(15 downto 11) <= "HLLHH"; --19
gpio(10 downto 8) <= "HLL"; --4
gpio(7 downto 0) <= (others => 'L');
cb(15 downto 8) <= "HHHHHHHH";
spw_rxdp <= spw_txdp; spw_rxsp <= spw_txsp;
spw_rxdn <= spw_txdn; spw_rxsn <= spw_txsn;
roen <= '0';
promedac <= '0';
promwidth <= "10";
rxd2 <= txd2;
d3 : entity dare.leon3mp
port map (rst, clksel, clk, error, wdogn, address, data,
cb(7 downto 0), sdclk, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact,
txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn, gpio,
promwidth, promedac,
spw_clksel, spw_clk, spw_rxdp, spw_rxdn, spw_rxsp, spw_rxsn, spw_txdp, spw_txdn,
spw_txsp, spw_txsn, gnd(0), roen, roout, nandout, test);
-- optional sdram
sd0 : if (CFG_MCTRLFT_SDEN = 1) and (CFG_MCTRLFT_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb0: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
PORT MAP(
Dq => cb(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb1: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
PORT MAP(
Dq => cb(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
promcb0 : sramft generic map (index => 7, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), cb(7 downto 0), romsn(0), writen, oen);
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
sramcb0 : sramft generic map (index => 7, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), cb(7 downto 0), ramsn(0), rwen(0), ramoen(0));
iuerr : process
begin
wait for (100*clkperiod) * 1 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data), (others => 'H') after 250 ns;
cb <= buskeep(cb), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := clkperiod*16 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait; -- remove to run the DSU UART
wait for 5010 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#06#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Sat Oct 31 15:04:15 2015
-- Host : cascade.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.1 (Maipo)
-- Command : write_vhdl -force -mode synth_stub
-- /afs/ece.cmu.edu/usr/rmrobert/Private/18545/Atari7800/Atari7800/Atari7800.srcs/sources_1/ip/BIOS_ROM/BIOS_ROM_stub.vhdl
-- Design : BIOS_ROM
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BIOS_ROM is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end BIOS_ROM;
architecture stub of BIOS_ROM is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[11:0],dina[7:0],douta[7:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_2,Vivado 2015.2";
begin
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_sfifo_15x128_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_sfifo_15x128_pkg.ALL;
ENTITY k7_sfifo_15x128_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF k7_sfifo_15x128_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:k7_sfifo_15x128_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
-- Title : includeModuleVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleVHDL.vhdl Author : Adrian Fiergolski <[email protected]> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleVHDL is
end entity includeModuleVHDL;
architecture Behavioral of includeModuleVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library stack;
use stack.OneHotStack.all;
entity MRAM is
port (
CLK: in std_logic;
RW: in std_logic;
ADDR: in mem_addr;
DIN: in operand;
DOUT: out operand
);
end MRAM;
architecture Beh of MRAM is
type tRAM is array (0 to 31) of operand;
signal RAM: tRAM:= (
-- | BIN | ADR BIN
"0000000000000000", -- | 00000 |
"0000000000000000", -- | 00001 |
"0000000000000000", -- | 00010 |
"0000000000000000", -- | 00011 |
"0000000000000000", -- | 00100 |
"0000000000000000", -- | 00101 |
"0000000000000000", -- | 00110 |
"0000000000000000", -- | 00111 |
"0000000000000000", -- | 01000 |
"0000000000000000", -- | 01001 |
"0000000000000000", -- | 01010 |
"0000000000000000", -- | 01011 |
"0000000000000000", -- | 01100 |
"0000000000000000", -- | 01101 |
"0000000000000000", -- | 01110 |
"0000000000000000", -- | 01111 |
"0000000000001000", -- | 10000 |
"0000000000000000", -- | 10001 |
"0000000000000000", -- | 10010 |
"0000000000000001", -- | 10011 |
"0000000000000000", -- | 10100 |
"0000000000000001", -- | 10101 |
others => "0000000000000000"
);
signal data_in: operand;
signal data_out: operand;
Begin
data_in <= Din;
WRITE: process (CLK, RW, ADDR, data_in)
begin
if (RW = '0') then
if (rising_edge(CLK)) then
RAM(conv_integer(ADDR)) <= data_in;
end if;
end if;
end process;
data_out <= RAM (conv_integer(ADDR));
RDP: process (RW, RAM, data_out)
begin
if (RW = '1') then
DOUT <= data_out;
else
DOUT <= (others => 'Z');
end if;
end process;
end Beh; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc665.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:57 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:25 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:36 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00665ent IS
END c03s04b01x00p01n01i00665ent;
ARCHITECTURE c03s04b01x00p01n01i00665arch OF c03s04b01x00p01n01i00665ent IS
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_std_file is file of array_rec_std;
constant C26 : record_std_package := (true,'1','s',note,3,3.0,3 ns,3,3);
constant C57 : array_rec_std(0 to 7) := (others => C26);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : array_rec_std_file open read_mode is "iofile.11";
variable v : array_rec_std(0 to 7);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 8) report "wrong length passed during read operation";
if (v /= C57) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00665"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00665 - File reading of array_rec_std_file operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00665arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc665.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:57 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:25 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:36 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00665ent IS
END c03s04b01x00p01n01i00665ent;
ARCHITECTURE c03s04b01x00p01n01i00665arch OF c03s04b01x00p01n01i00665ent IS
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_std_file is file of array_rec_std;
constant C26 : record_std_package := (true,'1','s',note,3,3.0,3 ns,3,3);
constant C57 : array_rec_std(0 to 7) := (others => C26);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : array_rec_std_file open read_mode is "iofile.11";
variable v : array_rec_std(0 to 7);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 8) report "wrong length passed during read operation";
if (v /= C57) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00665"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00665 - File reading of array_rec_std_file operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00665arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc665.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:57 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:25 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:36 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00665ent IS
END c03s04b01x00p01n01i00665ent;
ARCHITECTURE c03s04b01x00p01n01i00665arch OF c03s04b01x00p01n01i00665ent IS
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_std_file is file of array_rec_std;
constant C26 : record_std_package := (true,'1','s',note,3,3.0,3 ns,3,3);
constant C57 : array_rec_std(0 to 7) := (others => C26);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : array_rec_std_file open read_mode is "iofile.11";
variable v : array_rec_std(0 to 7);
variable len : natural;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v,len);
assert(len = 8) report "wrong length passed during read operation";
if (v /= C57) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00665"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00665 - File reading of array_rec_std_file operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00665arch;
|
entity driver1 is
end entity;
architecture test of driver1 is
signal s : bit_vector(1 to 3);
begin
p1: process is
begin
if 3 < 2 then -- Cannot delete this
s(5) <= '1'; -- Error
else
s(7) <= '0'; -- Error
end if;
while false loop
s(-1) <= '0'; -- Error
end loop;
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY edgeDet IS
PORT (
din : IN STD_LOGIC;
rising : OUT STD_LOGIC;
falling : OUT STD_LOGIC;
any : OUT STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC
);
END ENTITY edgeDet;
ARCHITECTURE rtl OF edgeDet IS
signal RegDin, RegDinL : std_logic;
BEGIN
any <= RegDinL xor RegDin;
falling <= RegDinL and not RegDin;
rising <= not RegDinL and RegDin;
process(clk)
begin
if rising_edge(clk) then
RegDin <= din;
RegDinL <= RegDin;
end if;
end process;
END ARCHITECTURE rtl;
|
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY edgeDet IS
PORT (
din : IN STD_LOGIC;
rising : OUT STD_LOGIC;
falling : OUT STD_LOGIC;
any : OUT STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC
);
END ENTITY edgeDet;
ARCHITECTURE rtl OF edgeDet IS
signal RegDin, RegDinL : std_logic;
BEGIN
any <= RegDinL xor RegDin;
falling <= RegDinL and not RegDin;
rising <= not RegDinL and RegDin;
process(clk)
begin
if rising_edge(clk) then
RegDin <= din;
RegDinL <= RegDin;
end if;
end process;
END ARCHITECTURE rtl;
|
------------------------------------------------------------------------------
-- "fixed_pkg" package contains functions for fixed point math.
-- Please see the documentation for the fixed point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_pkg.all;
-- Last Modified: $Date: 2006/05/09 19:21:24 $
-- RCS ID: $Id: fixed_pkg_c.vhd,v 1.1 2006/05/09 19:21:24 sandeepd Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- synthesis translate_off
use std.textio.all;
-- synthesis translate_on
package fixed_pkg is
--%%% Uncomment the Generics
-- new work.fixed_generic_pkg
-- generic map (
-- fixed_round_style => true; -- fixed_round
-- fixed_overflow_style => true; -- fixed_saturate
-- fixed_guard_bits => 3; -- number of guard bits
-- no_warning => false -- show warnings
-- );
--%%% REMOVE THE REST OF THIS FILE.
constant fixed_round_style : BOOLEAN := true; -- round
constant fixed_overflow_style : BOOLEAN := true; -- saturate
constant fixed_guard_bits : NATURAL := 3; -- number of guard bits
constant no_warning : BOOLEAN := false; -- issue warnings
-- Author David Bishop ([email protected])
-- These 5 constants are used as defaults.
-- There is a mechanism to override them in every function
constant fixed_round : BOOLEAN := true; -- Turn on rounding routine
constant fixed_truncate : BOOLEAN := false; -- Trun off rounding routine
constant fixed_saturate : BOOLEAN := true; -- Saturate large numbers
constant fixed_wrap : BOOLEAN := false; -- Wrap large numbers
constant fixedsynth_or_real : BOOLEAN; -- differed constant
-- base Unsigned fixed point type, downto direction assumed
type ufixed is array (INTEGER range <>) of STD_LOGIC;
-- base Signed fixed point type, downto direction assumed
type sfixed is array (INTEGER range <>) of STD_LOGIC;
-----------------------------------------------------------------------------
-- Fixed point type is defined as follows:
-- 0000000000
-- 4321012345
-- 4 0 -5
-- The decimal point is assumed between the "0" and "-1" index
-- Thus "0011010000" = 6.5 and would be written as 00110.10000
-- All types are assumed to be in the "downto" direction.
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
-- Modify the sign of the number, 2's complement
function "abs" (arg : sfixed) return sfixed;
function "-" (arg : sfixed)return sfixed;
-- Convert a signed fixed to an unsigned fixed
function "abs" (arg : sfixed) return ufixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(max(a,c)+1 downto min(b,d))
function "+" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(max(a,c)+1 downto min(b,d))
function "+" (l, r : sfixed) return sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(max(a,c)+1 downto min(b,d))
function "-" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(max(a,c)+1 downto min(b,d))
function "-" (l, r : sfixed) return sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : sfixed) return sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : sfixed) return sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (l, r : ufixed) return ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (l, r : sfixed) return sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (l, r : ufixed) return ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (l, r : sfixed) return sfixed;
----------------------------------------------------------------------------
-- Overload routines. In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : ufixed; r : REAL) return ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : ufixed) return ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto min(0,b))
function "+" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d))
function "+" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : ufixed; r : REAL) return ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : ufixed) return ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto min(0,b))
function "-" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d))
function "-" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : ufixed; r : REAL) return ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : ufixed) return ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : ufixed; r : REAL) return ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : ufixed) return ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : ufixed; r : REAL) return ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : ufixed) return ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto min(b,0))
function "rem" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto min(d,0))
function "rem" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : ufixed; r : REAL) return ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : ufixed) return ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto min(b,0))
function "mod" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto min(d,0))
function "mod" (l : NATURAL; r : ufixed) return ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto min(0,b))
function "+" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto min(0,d))
function "+" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto min(0,b))
function "-" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto min(0,d))
function "-" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : sfixed; r : REAL) return sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : sfixed) return sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto min(b,0))
function "rem" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto min(d,0))
function "rem" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : sfixed; r : REAL) return sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : sfixed) return sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto min(b,0))
function "mod" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto min(d,0))
function "mod" (l : INTEGER; r : sfixed) return sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : sfixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : sfixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style)
return ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : sfixed;
constant round_style : BOOLEAN := fixed_round_style)
return sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style)
return ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : sfixed;
constant overflow_style : BOOLEAN := fixed_overflow_style;
constant round_style : BOOLEAN := fixed_round_style)
return sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (max(a,c) downto min(b,d))
procedure add_carry (
L, R : in ufixed;
c_in : in STD_ULOGIC;
result : out ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (max(a,c) downto min(b,d))
procedure add_carry (
L, R : in sfixed;
c_in : in STD_ULOGIC;
result : out sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : ufixed; N : integer) return ufixed;
function scalb (y : ufixed; N : SIGNED) return ufixed;
function scalb (y : sfixed; N : integer) return sfixed;
function scalb (y : sfixed; N : SIGNED) return sfixed;
function Is_Negative (arg : sfixed) return BOOLEAN;
--===========================================================================
-- Comparison Operators
--===========================================================================
function ">" (l, r : ufixed) return BOOLEAN;
function ">" (l, r : sfixed) return BOOLEAN;
function "<" (l, r : ufixed) return BOOLEAN;
function "<" (l, r : sfixed) return BOOLEAN;
function "<=" (l, r : ufixed) return BOOLEAN;
function "<=" (l, r : sfixed) return BOOLEAN;
function ">=" (l, r : ufixed) return BOOLEAN;
function ">=" (l, r : sfixed) return BOOLEAN;
function "=" (l, r : ufixed) return BOOLEAN;
function "=" (l, r : sfixed) return BOOLEAN;
function "/=" (l, r : ufixed) return BOOLEAN;
function "/=" (l, r : sfixed) return BOOLEAN;
--%%% Uncomment the following (new syntax)
-- function "?=" (L, R : ufixed) return BOOLEAN;
-- function "?=" (L, R : sfixed) return BOOLEAN;
-- --%%% remove the following (old syntax)
function \?=\ (L, R : ufixed) return STD_ULOGIC;
function \?=\ (L, R : sfixed) return STD_ULOGIC;
-- These need to be overloaded for sfixed and ufixed
function \?/=\ (L, R : ufixed) return STD_ULOGIC;
function \?>\ (L, R : ufixed) return STD_ULOGIC;
function \?>=\ (L, R : ufixed) return STD_ULOGIC;
function \?<\ (L, R : ufixed) return STD_ULOGIC;
function \?<=\ (L, R : ufixed) return STD_ULOGIC;
function \?/=\ (L, R : sfixed) return STD_ULOGIC;
function \?>\ (L, R : sfixed) return STD_ULOGIC;
function \?>=\ (L, R : sfixed) return STD_ULOGIC;
function \?<\ (L, R : sfixed) return STD_ULOGIC;
function \?<=\ (L, R : sfixed) return STD_ULOGIC;
-- %%% Replace with the following (new syntax)
-- function "?=" (L, R : ufixed) return STD_ULOGIC;
-- function "?/=" (L, R : ufixed) return STD_ULOGIC;
-- function "?>" (L, R : ufixed) return STD_ULOGIC;
-- function "?>=" (L, R : ufixed) return STD_ULOGIC;
-- function "?<" (L, R : ufixed) return STD_ULOGIC;
-- function "?<=" (L, R : ufixed) return STD_ULOGIC;
-- function "?=" (L, R : sfixed) return STD_ULOGIC;
-- function "?/=" (L, R : sfixed) return STD_ULOGIC;
-- function "?>" (L, R : sfixed) return STD_ULOGIC;
-- function "?>=" (L, R : sfixed) return STD_ULOGIC;
-- function "?<" (L, R : sfixed) return STD_ULOGIC;
-- function "?<=" (L, R : sfixed) return STD_ULOGIC;
function std_match (L, R : ufixed) return BOOLEAN;
function std_match (L, R : sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : ufixed) return ufixed;
function minimum (l, r : ufixed) return ufixed;
function maximum (l, r : sfixed) return sfixed;
function minimum (l, r : sfixed) return sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "max(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : ufixed) return BOOLEAN;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : ufixed; r : REAL) return BOOLEAN;
function "/=" (l : ufixed; r : REAL) return BOOLEAN;
function ">=" (l : ufixed; r : REAL) return BOOLEAN;
function "<=" (l : ufixed; r : REAL) return BOOLEAN;
function ">" (l : ufixed; r : REAL) return BOOLEAN;
function "<" (l : ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : ufixed) return BOOLEAN;
function "/=" (l : REAL; r : ufixed) return BOOLEAN;
function ">=" (l : REAL; r : ufixed) return BOOLEAN;
function "<=" (l : REAL; r : ufixed) return BOOLEAN;
function ">" (l : REAL; r : ufixed) return BOOLEAN;
function "<" (l : REAL; r : ufixed) return BOOLEAN;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "max(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : sfixed) return BOOLEAN;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : sfixed; r : REAL) return BOOLEAN;
function "/=" (l : sfixed; r : REAL) return BOOLEAN;
function ">=" (l : sfixed; r : REAL) return BOOLEAN;
function "<=" (l : sfixed; r : REAL) return BOOLEAN;
function ">" (l : sfixed; r : REAL) return BOOLEAN;
function "<" (l : sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : sfixed) return BOOLEAN;
function "/=" (l : REAL; r : sfixed) return BOOLEAN;
function ">=" (l : REAL; r : sfixed) return BOOLEAN;
function "<=" (l : REAL; r : sfixed) return BOOLEAN;
function ">" (l : REAL; r : sfixed) return BOOLEAN;
function "<" (l : REAL; r : sfixed) return BOOLEAN;
--===========================================================================
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--===========================================================================
function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed;
function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed;
function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed;
function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : ufixed) return ufixed;
function "and" (L, R : ufixed) return ufixed;
function "or" (L, R : ufixed) return ufixed;
function "nand" (L, R : ufixed) return ufixed;
function "nor" (L, R : ufixed) return ufixed;
function "xor" (L, R : ufixed) return ufixed;
function "xnor" (L, R : ufixed) return ufixed;
function "not" (L : sfixed) return sfixed;
function "and" (L, R : sfixed) return sfixed;
function "or" (L, R : sfixed) return sfixed;
function "nand" (L, R : sfixed) return sfixed;
function "nor" (L, R : sfixed) return sfixed;
function "xor" (L, R : sfixed) return sfixed;
function "xnor" (L, R : sfixed) return sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "and" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "or" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "or" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "and" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "and" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "or" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "or" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed;
-- Reduction operators, same as numeric_std functions
-- %%% remove 12 functions (old syntax)
function and_reduce(arg : ufixed) return STD_ULOGIC;
function nand_reduce(arg : ufixed) return STD_ULOGIC;
function or_reduce(arg : ufixed) return STD_ULOGIC;
function nor_reduce(arg : ufixed) return STD_ULOGIC;
function xor_reduce(arg : ufixed) return STD_ULOGIC;
function xnor_reduce(arg : ufixed) return STD_ULOGIC;
function and_reduce(arg : sfixed) return STD_ULOGIC;
function nand_reduce(arg : sfixed) return STD_ULOGIC;
function or_reduce(arg : sfixed) return STD_ULOGIC;
function nor_reduce(arg : sfixed) return STD_ULOGIC;
function xor_reduce(arg : sfixed) return STD_ULOGIC;
function xnor_reduce(arg : sfixed) return STD_ULOGIC;
-- %%% Uncomment the following 12 functions (new syntax)
-- function "and" ( arg : ufixed ) RETURN std_ulogic;
-- function "nand" ( arg : ufixed ) RETURN std_ulogic;
-- function "or" ( arg : ufixed ) RETURN std_ulogic;
-- function "nor" ( arg : ufixed ) RETURN std_ulogic;
-- function "xor" ( arg : ufixed ) RETURN std_ulogic;
-- function "xnor" ( arg : ufixed ) RETURN std_ulogic;
-- function "and" ( arg : sfixed ) RETURN std_ulogic;
-- function "nand" ( arg : sfixed ) RETURN std_ulogic;
-- function "or" ( arg : sfixed ) RETURN std_ulogic;
-- function "nor" ( arg : sfixed ) RETURN std_ulogic;
-- function "xor" ( arg : sfixed ) RETURN std_ulogic;
-- function "xnor" ( arg : sfixed ) RETURN std_ulogic;
-- returns arg'low-1 if not found
function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER;
function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER;
-- returns arg'high+1 if not found
function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER;
function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER;
--===========================================================================
-- RESIZE Functions
--===========================================================================
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is true, then the result will be rounded. If the MSB
-- of the remainder is a "1" AND the LSB of the unround result is a '1' or
-- the lower bits of the remainder include a '1' then the result will be
-- increased by the smallest representable number for that type.
-- The default is "true" for round_style.
-- "overflow_style" can be "true" (saturate mode) or "false" (wrap mode).
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed;
-- "size_res" functions create the size of the output from the length
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : ufixed; -- input
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
function resize (
arg : sfixed; -- input
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
--===========================================================================
-- Conversion Functions
--===========================================================================
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding
return ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding
return ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return ufixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return ufixed;
-- Performs a casting. ufixed (arg'range) is returned
function to_ufixed (
arg : UNSIGNED) -- unsigned
return ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : ufixed; -- fixed point input
size_res : UNSIGNED; -- used for length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : ufixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return NATURAL;
-- Integer to sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed;
-- signed to sfixed
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : SIGNED) -- signed
return sfixed;
-- unsigned fixed point to signed fixed point (adds a "0" sign bit)
function add_sign (
arg : ufixed) -- unsigned fixed point
return sfixed;
-- signed fixed point to signed
function to_signed (
arg : sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED;
-- signed fixed point to signed
function to_signed (
arg : sfixed; -- fixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED;
-- signed fixed point to real
function to_real (
arg : sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : sfixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return INTEGER;
-- Because of the farily complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER;
function ufixed_low (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER;
function sfixed_high (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER;
function sfixed_low (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function saturate (
size_res : ufixed) -- only the size of this is used
return ufixed;
function saturate (
size_res : sfixed) -- only the size of this is used
return sfixed;
--===========================================================================
-- Translation Functions
--===========================================================================
-- Maps meta-logical values
function to_01 (
s : ufixed; -- fixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return ufixed;
-- maps meta-logical values
function to_01 (
s : sfixed; -- fixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return sfixed;
function Is_X (arg : ufixed) return BOOLEAN;
function Is_X (arg : sfixed) return BOOLEAN;
function to_X01 (arg : ufixed) return ufixed;
function to_X01 (arg : sfixed) return sfixed;
function to_X01Z (arg : ufixed) return ufixed;
function to_X01Z (arg : sfixed) return sfixed;
function to_UX01 (arg : ufixed) return ufixed;
function to_UX01 (arg : sfixed) return sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not cast these vectors because of their negative index.
function to_slv (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR;
-- alias to_StdLogicVector is to_slv [ufixed return STD_LOGIC_VECTOR];
-- alias to_Std_Logic_Vector is to_slv [ufixed return STD_LOGIC_VECTOR];
function to_slv (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR;
-- alias to_StdLogicVector is to_slv [sfixed return STD_LOGIC_VECTOR];
-- alias to_Std_Logic_Vector is to_slv [sfixed return STD_LOGIC_VECTOR];
function to_sulv (
arg : ufixed) -- fp vector
return STD_ULOGIC_VECTOR;
-- alias to_StdULogicVector is to_sulv [ufixed return STD_ULOGIC_VECTOR];
-- alias to_Std_ULogic_Vector is to_sulv [ufixed return STD_ULOGIC_VECTOR];
function to_sulv (
arg : sfixed) -- fp vector
return STD_ULOGIC_VECTOR;
-- alias to_StdULogicVector is to_sulv [sfixed return STD_ULOGIC_VECTOR];
-- alias to_Std_ULogic_Vector is to_sulv [sfixed return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return ufixed;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
--===========================================================================
-- string and textio Functions
--===========================================================================
-- rtl_synthesis off
-- synthesis translate_off
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out ufixed);
procedure READ(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out sfixed);
procedure READ(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, ufixed, SIDE, width];
alias bwrite is WRITE [LINE, sfixed, SIDE, width];
alias bread is READ [LINE, ufixed];
alias bread is READ [LINE, ufixed, BOOLEAN];
alias bread is READ [LINE, sfixed];
alias bread is READ [LINE, sfixed, BOOLEAN];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out ufixed);
procedure OREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out sfixed);
procedure OREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN);
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out ufixed);
procedure HREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out sfixed);
procedure HREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN);
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (
value : ufixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
alias to_bstring is to_string [ufixed, SIDE, width return STRING];
function to_ostring (
value : ufixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function to_hstring (
value : ufixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function to_string (
value : sfixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
alias to_bstring is to_string [sfixed, SIDE, width return STRING];
function to_ostring (
value : sfixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function to_hstring (
value : sfixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER return ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER return sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : ufixed)
return ufixed;
alias from_bstring is from_string [STRING, ufixed return ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : ufixed)
return ufixed;
function from_hstring (
hstring : STRING; -- hex string
size_res : ufixed)
return ufixed;
function from_string (
bstring : STRING; -- binary string
size_res : sfixed)
return sfixed;
alias from_bstring is from_string [STRING, sfixed return sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : sfixed)
return sfixed;
function from_hstring (
hstring : STRING; -- hex string
size_res : sfixed)
return sfixed;
-- Direct converstion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return ufixed;
alias from_bstring is from_string [STRING return ufixed];
-- Direct octal and hex converstion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return ufixed;
function from_hstring (
hstring : STRING) -- hex string
return ufixed;
function from_string (
bstring : STRING) -- binary string
return sfixed;
alias from_bstring is from_string [STRING return sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return sfixed;
function from_hstring (
hstring : STRING) -- hex string
return sfixed;
-- synthesis translate_on
-- rtl_synthesis on
-- This type is here for the floating point package.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round to positive
round_neginf, -- Round to negate
round_zero); -- Round towards zero
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
function to_StdLogicVector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR;
function to_Std_Logic_Vector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR;
function to_StdLogicVector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR;
function to_Std_Logic_Vector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR;
end package fixed_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_textio.all; -- %%% for testing only
package body fixed_pkg is
-- Author David Bishop ([email protected])
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : ufixed (0 downto 1) := (others => '0');
constant NASF : sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
--%%% Can be removed in vhdl-200x, will be implicit.
-- purpose: To find the largest of 2 numbers
function maximum (l, r : INTEGER)
return INTEGER is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
function minimum (l, r : INTEGER)
return INTEGER is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
-- %%% Remove the following function (duplicates of new numeric_std)
function "sra" (arg : SIGNED; count : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(arg, count);
else
return SHIFT_LEFT(arg, -count);
end if;
end function "sra";
-- %%% Replace or_reducex with "or", and_reducex with "and", and
-- %%% xor_reducex with "xor", then remove the following 3 functions
-- purpose: OR all of the bits in a vector together
-- This is a copy of the proposed "or_reduce" from 1076.3
function or_reducex (arg : STD_LOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_LOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_LOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reducex (BUS_int (BUS_int'left downto Half));
Lower := or_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reducex;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reducex (arg : STD_LOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_LOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_LOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reducex (BUS_int (BUS_int'left downto Half));
Lower := and_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reducex;
function xor_reducex (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reducex (BUS_int (BUS_int'left downto Half));
Lower := xor_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reducex;
--%%% remove the following function and table
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% end remove
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (L = INTEGER'low or R = INTEGER'low) then
return 0; -- error condition
end if;
return minimum (L, R);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (L = INTEGER'low or R = INTEGER'low) then
report "FIXED_GENERIC_PKG: Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : sfixed) -- input
return sfixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : sfixed (arg'range);
begin -- function cleanvec
assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low))
report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : ufixed) -- input
return ufixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : ufixed (arg'range);
begin -- function cleanvec
assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low))
report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type cast a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
-- variable j : INTEGER := arg'high; -- index for arg
begin -- function to_fixed
result := ufixed(arg);
-- floop : for i in result'range loop
-- result(i) := arg(j); -- res(4) := arg (4 + 3)
-- j := j - 1;
-- end loop floop;
return result;
end function to_fixed;
-- Type cast a "signed" into an "sfixed", used internally
function to_fixed (
arg : SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
-- variable j : INTEGER := arg'high; -- index for arg
begin -- function to_fixed
result := sfixed(arg);
-- floop : for i in result'range loop
-- result(i) := arg(j); -- res(4) := arg (4 + 3)
-- j := j - 1;
-- end loop floop;
return result;
end function to_fixed;
-- Type cast a "ufixed" into an "unsigned", used internally
function to_uns (
arg : ufixed) -- fp vector
return UNSIGNED is
subtype t is UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
-- floop : for i in slv'range loop
-- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3)
-- end loop floop;
return UNSIGNED(to_X01(std_logic_vector(slv)));
end function to_uns;
-- Type cast an "sfixed" into a "signed", used internally
function to_s (
arg : sfixed) -- fp vector
return SIGNED is
subtype t is SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
-- floop : for i in slv'range loop
-- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3)
-- end loop floop;
return SIGNED(to_X01(std_logic_vector(slv)));
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in ufixed;
result : out ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0) :=
(others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in sfixed;
result : out sfixed;
overflowx : out BOOLEAN) is
variable args, ress : SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or_reducex (STD_LOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : ufixed;
remainder : ufixed;
overflow_style : BOOLEAN := fixed_overflow_style)
return ufixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reducex (to_slv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : sfixed;
remainder : sfixed;
overflow_style : BOOLEAN := fixed_overflow_style)
return sfixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reducex (to_slv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- else
-- result(result'high) := arg(arg'high); -- fix sign bit in wrap
end if;
end if;
return result;
end function round_fixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- casting functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_slv (
arg : ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0);
variable slv : t;
begin
if arg'length < 1 then
return NSLV;
end if;
slv := t (arg);
return slv;
end function to_slv;
function to_slv (
arg : sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0);
variable slv : t;
begin
if arg'length < 1 then
return NSLV;
end if;
slv := t (arg);
return slv;
end function to_slv;
function to_sulv (
arg : ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
begin
return to_stdulogicvector (to_slv(arg));
end function to_sulv;
function to_sulv (
arg : sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
begin
return to_stdulogicvector (to_slv(arg));
end function to_sulv;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_UFIXED (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_SFIXED (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
begin
return to_ufixed (arg => to_stdlogicvector(arg),
left_index => left_index,
right_index => right_index);
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
begin
return to_sfixed (arg => to_stdlogicvector(arg),
left_index => left_index,
right_index => right_index);
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : sfixed) -- fixed point input
return sfixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : sfixed) -- fixed point input
return sfixed is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
function "abs" (arg : sfixed) return ufixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : sfixed(left_index+1 downto right_index);
variable result : ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := ufixed (xarg (left_index downto right_index));
return result;
end function "abs";
-- Addition
function "+" (
l, r : ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return ufixed is -- ufixed(a+c+1 downto b+d)
variable lslv : UNSIGNED (l'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (r'length+l'length-1 downto 0);
variable result : ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return sfixed is -- sfixed(a+c+1 downto b+d)
variable lslv : SIGNED (l'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (r'length+l'length-1 downto 0);
variable result : sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed is
variable result : ufixed (l'high - mine(r'low, r'low)
downto mine (l'low, l'low) - r'high -1);
variable dresult : ufixed (result'high downto result'low -guard_bits);
variable lresize : ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (l, lresize'high, lresize'low);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
round_style => round_style,
overflow_style => fixed_wrap); -- overflow impossible
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : sfixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed is
variable result : sfixed (l'high - mine(r'low, r'low)+1
downto mine (l'low, l'low) - r'high);
variable dresult : sfixed (result'high downto result'low-guard_bits);
variable lresize : sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : SIGNED (lresize'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (l, lresize'high, lresize'low);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
round_style => round_style,
overflow_style => fixed_wrap); -- overflow impossible
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed is
constant one : ufixed (0 downto 0) := "1";
begin
return divide(l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : sfixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed is
constant one : sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide(l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : ufixed) -- fixed point input
return ufixed is
begin
return remainder (l => l,
r => r,
round_style => fixed_round_style);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : sfixed) -- fixed point input
return sfixed is
begin
return remainder (l => l,
r => r,
round_style => fixed_round_style);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style)
return ufixed is
variable result : ufixed (minimum(l'high, r'high) downto mine(l'low, r'low));
variable dresult : ufixed (r'high downto r'low);
variable lresize : ufixed (maximum(l'high, r'low) downto mins(r'low, r'low));
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rslv := to_uns (cleanvec(r));
if (rslv = 0) then
report "FIXED_GENERIC_PKG.rem uFixed point Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap,
round_style => round_style);
-- result(result'high downto r'low) := dresult(result'high downto r'low);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : sfixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style)
return sfixed is
variable l_abs : ufixed (l'range);
variable r_abs : ufixed (r'range);
variable result : sfixed (minimum(r'high, l'high) downto mine(r'low, l'low));
variable neg_result : sfixed (minimum(r'high, l'high)+1 downto mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := abs(l);
r_abs := abs(r);
result := sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : ufixed) -- fixed point input
return ufixed is
begin
return modulo (l => l,
r => r,
round_style => fixed_round_style);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : sfixed) -- fixed point input
return sfixed is
begin
return modulo(l => l,
r => r,
round_style => fixed_round_style);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style)
return ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : sfixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style;
constant round_style : BOOLEAN := fixed_round_style)
return sfixed is
variable l_abs : ufixed (l'range);
variable r_abs : ufixed (r'range);
variable result : sfixed (r'high downto
mine(r'low, l'low));
variable dresult : sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := abs(l);
r_abs := abs(r);
dresult := "0" & sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in ufixed;
c_in : in STD_ULOGIC;
result : out ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
variable cx : UNSIGNED (0 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in sfixed;
c_in : in STD_ULOGIC;
result : out sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index
downto 0);
variable result_slv : SIGNED (left_index-right_index
downto 0);
variable cx : SIGNED (1 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : ufixed; N : integer) return ufixed is
variable result : ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : ufixed; N : SIGNED) return ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : sfixed; N : integer) return sfixed is
variable result : sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : sfixed; N : SIGNED) return sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'low to arg'high loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_lsb;
function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'high downto arg'low loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_msb;
function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'low to arg'high loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_lsb;
function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'high downto arg'low loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_msb;
function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_slv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) and to_slv(R);
else
report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) or to_slv(R);
else
report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nand to_slv(R);
else
report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nor to_slv(R);
else
report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xnor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_slv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) and to_slv(R);
else
report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) or to_slv(R);
else
report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nand to_slv(R);
else
report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nor to_slv(R);
else
report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xnor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operators, same as numeric_std functions
-- %%% remove 12 functions (old syntax)
function and_reduce(arg : ufixed) return STD_ULOGIC is
begin
return and_reducex (to_slv(arg));
end function and_reduce;
function nand_reduce(arg : ufixed) return STD_ULOGIC is
begin
return not and_reducex (to_slv(arg));
end function nand_reduce;
function or_reduce(arg : ufixed) return STD_ULOGIC is
begin
return or_reducex (to_slv(arg));
end function or_reduce;
function nor_reduce(arg : ufixed) return STD_ULOGIC is
begin
return not or_reducex (to_slv(arg));
end function nor_reduce;
function xor_reduce(arg : ufixed) return STD_ULOGIC is
begin
return xor_reducex (to_slv(arg));
end function xor_reduce;
function xnor_reduce(arg : ufixed) return STD_ULOGIC is
begin
return not xor_reducex (to_slv(arg));
end function xnor_reduce;
function and_reduce(arg : sfixed) return STD_ULOGIC is
begin
return and_reducex (to_slv(arg));
end function and_reduce;
function nand_reduce(arg : sfixed) return STD_ULOGIC is
begin
return not and_reducex (to_slv(arg));
end function nand_reduce;
function or_reduce(arg : sfixed) return STD_ULOGIC is
begin
return or_reducex (to_slv(arg));
end function or_reduce;
function nor_reduce(arg : sfixed) return STD_ULOGIC is
begin
return not or_reducex (to_slv(arg));
end function nor_reduce;
function xor_reduce(arg : sfixed) return STD_ULOGIC is
begin
return xor_reducex (to_slv(arg));
end function xor_reduce;
function xnor_reduce(arg : sfixed) return STD_ULOGIC is
begin
return not xor_reducex (to_slv(arg));
end function xnor_reduce;
-- %%% Uncomment the following 12 functions (new syntax)
-- function "and" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return and to_slv(arg);
-- end function "and";
-- function "nand" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return nand to_slv(arg);
-- end function "nand";;
-- function "or" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return or to_slv(arg);
-- end function "or";
-- function "nor" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return nor to_slv(arg);
-- end function "nor";
-- function "xor" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return xor to_slv(arg);
-- end function "xor";
-- function "xnor" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return xnor to_slv(arg);
-- end function "xnor";
-- function "and" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return and to_slv(arg);
-- end function "and";;
-- function "nand" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return nand to_slv(arg);
-- end function "nand";;
-- function "or" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return or to_slv(arg);
-- end function "or";
-- function "nor" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return nor to_slv(arg);
-- end function "nor";
-- function "xor" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return xor to_slv(arg);
-- end function "xor";
-- function "xnor" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return xnor to_slv(arg);
-- end function "xnor";
-- %%% Replace with the following (new syntax)
-- function "?=" (L, R : ufixed) return STD_ULOGIC is
function \?=\ (L, R : ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '1';
for i in lresize'reverse_range loop
result1 := \?=\(lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- end function "?=";
-- function "?/=" (L, R : ufixed) return STD_ULOGIC is
function \?/=\ (L, R : ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?/=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '0';
for i in lresize'reverse_range loop
result1 := \?/=\ (lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- end function "?/=";
-- function "?>" (L, R : ufixed) return STD_ULOGIC is
function \?>\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- end function "?>";
-- function "?>=" (L, R : ufixed) return STD_ULOGIC is
function \?>=\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- end function "?>=";
-- function "?<" (L, R : ufixed) return STD_ULOGIC is
function \?<\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- end function "?<";
-- function "?<=" (L, R : ufixed) return STD_ULOGIC is
function \?<=\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- end function "?<=";
-- function "?=" (L, R : sfixed) return STD_ULOGIC is
function \?=\ (L, R : sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '1';
for i in lresize'reverse_range loop
result1 := \?=\ (lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- end function "?=";
-- function "?/=" (L, R : sfixed) return STD_ULOGIC is
function \?/=\ (L, R : sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?/=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '0';
for i in lresize'reverse_range loop
result1 := \?/=\ (lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- end function "?/=";
-- function "?>" (L, R : sfixed) return STD_ULOGIC is
function \?>\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- end function "?>";
-- function "?>=" (L, R : sfixed) return STD_ULOGIC is
function \?>=\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- end function "?>=";
-- function "?<" (L, R : sfixed) return STD_ULOGIC is
function \?<\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- end function "?<";
-- function "?<=" (L, R : sfixed) return STD_ULOGIC is
function \?<=\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- end function "?<=";
-- %%% end replace
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_slv(L), to_slv(R));
else
report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_slv(L), to_slv(R));
else
report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
--%%% end remove
-- compare functions
function "=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : ufixed) return ufixed is
begin
if l > r then return l;
else return r;
end if;
end function maximum;
function maximum (l, r : sfixed) return sfixed is
begin
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (l, r : ufixed) return ufixed is
begin
if l > r then return r;
else return l;
end if;
end function minimum;
function minimum (l, r : sfixed) return sfixed is
begin
if l > r then return r;
else return l;
end if;
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return ufixed is
variable argx : INTEGER;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : ufixed (left_index downto fw) := (others => '0');
variable sresult : UNSIGNED (left_index downto 0); -- integer portion
variable bound : NATURAL; -- find the numerical bounds
begin
if (left_index < fw) then
return NAUF;
end if;
if left_index >= 0 then
if (left_index < 30) then
bound := 2**(left_index+1);
else
bound := INTEGER'high;
end if;
end if;
if (arg /= 0) then
if arg >= bound or left_index < 0 then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_UFIXED(NATURAL): vector truncated"
severity warning;
if (overflow_style = fixed_wrap) then -- wrap
if bound = 0 then
argx := 0;
else
argx := arg mod bound;
end if;
else -- saturate
return saturate (result'high, result'low);
end if;
else
argx := arg;
end if;
else
return result; -- return zero
end if;
sresult := to_unsigned (argx, sresult'high+1);
result := resize (arg => ufixed (sresult),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
variable argx : INTEGER;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : sfixed (left_index downto fw) := (others => '0');
variable sresult : SIGNED (left_index+1 downto 0); -- integer portion
variable bound : NATURAL := 0;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if left_index >= 0 then
if (left_index < 30) then
bound := 2**(left_index);
else
bound := INTEGER'high;
end if;
end if;
if (arg /= 0) then
if (arg >= bound or arg < -bound or left_index < 0) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_wrap then -- wrap
if bound = 0 then -- negative integer_range trap
argx := 0;
else -- shift off the top bits
argx := arg rem (bound*2);
end if;
else -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
else
argx := arg;
end if;
else
return result; -- return zero
end if;
sresult := to_signed (argx, sresult'length);
result := resize (arg => sfixed (sresult),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed is
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : ufixed (left_index downto fw) := (others => '0');
variable Xresult : ufixed (left_index downto fw-guard_bits) := (others => '0');
variable presult : REAL;
variable overflow_needed : BOOLEAN;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
report "FIXED_GENERIC_PKG.TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert NO_WARNING report "FIXED_GENERIC_PKG.TO_UFIXED(REAL): vector truncated"
severity warning;
overflow_needed := (overflow_style = fixed_saturate);
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed is
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : sfixed (left_index downto fw) := (others => '0');
variable Xresult : sfixed (left_index+1 downto fw-guard_bits) := (others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert NO_WARNING report "FIXED_GENERIC_PKG.TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : ufixed (left_index downto fw);
begin
if arg'length < 1 or (left_index < fw) then
return NAUF;
end if;
result := resize (arg => ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- casted version
function to_ufixed (
arg : UNSIGNED) -- unsigned
return ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NAUF;
end if;
return ufixed(xarg);
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : sfixed (left_index downto fw);
begin
if arg'length < 1 or (left_index < fw) then
return NASF;
end if;
result := resize (arg => sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- casted version
function to_sfixed (
arg : SIGNED) -- signed
return sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NASF;
end if;
return sfixed(xarg);
end function to_sfixed;
function add_sign (arg : ufixed) return sfixed is
variable result : sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function add_sign;
-- Because of the farily complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
constant sat : ufixed (left_index downto right_index) := (others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable sat : sfixed (left_index downto right_index) := (others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : ufixed) -- only the size of this is used
return ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : sfixed) -- only the size of this is used
return sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return ufixed is
variable result : ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_UFIX (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return sfixed is
variable result : sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_SFIX (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : ufixed; -- ufixed point input
size_res : UNSIGNED; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : sfixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : sfixed; -- ufixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : ufixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := cleanvec(arg);
if (Is_X(arg_int)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : sfixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := cleanvec(arg);
if (Is_X(arg_int)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := abs(arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : ufixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return NATURAL is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNSIGNED (minimum(31, left_index+1) downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : sfixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return INTEGER is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable arg_s : SIGNED (minimum(31, left_index+1) downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : ufixed; -- ufixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return ufixed is
variable result : ufixed (s'range); -- result
begin
for i in s'range loop
case s(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := XMAP;
end case;
end loop;
return result;
end function to_01;
function to_01 (
s : sfixed; -- ufixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return sfixed is
variable result : sfixed (s'range);
begin
for i in s'range loop
case s(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := XMAP;
end case;
end loop;
return result;
end function to_01;
function Is_X (
arg : ufixed)
return BOOLEAN is
variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_slv(arg);
return Is_X(argslv);
end function Is_X;
function Is_X (
arg : sfixed)
return BOOLEAN is
variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_slv(arg);
return Is_X(argslv);
end function Is_X;
function To_X01 (
arg : ufixed)
return ufixed is
begin
return to_ufixed (To_X01(to_slv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : sfixed)
return sfixed is
begin
return to_sfixed (To_X01(to_slv(arg)), arg'high, arg'low);
end function To_X01;
function To_X01Z (
arg : ufixed)
return ufixed is
begin
return to_ufixed (To_X01Z(to_slv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : sfixed)
return sfixed is
begin
return to_sfixed (To_X01Z(to_slv(arg)), arg'high, arg'low);
end function To_X01Z;
function To_UX01 (
arg : ufixed)
return ufixed is
begin
return to_ufixed (To_UX01(to_slv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : sfixed)
return sfixed is
begin
return to_sfixed (To_UX01(to_slv(arg)), arg'high, arg'low);
end function To_UX01;
function resize (
arg : ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : ufixed (arghigh downto arglow);
variable result : ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or_reducex(to_slv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style and
or_reducex(to_slv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return sfixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : sfixed (arghigh downto arglow);
variable result : sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style) then
reduced := or_reducex(to_slv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or_reducex(to_slv(invec(arghigh-1 downto
left_index)));
if overflow_style and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and_reducex(to_slv(invec(arghigh-1 downto
left_index)));
if overflow_style and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => to_stdlogicvector(arg),
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => to_stdlogicvector(arg),
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : ufixed; -- input
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : sfixed; -- input
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded functions
function "+" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l +
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "+";
function "+" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
+ r);
end function "+";
function "+" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l +
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "+";
function "+" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
+ r);
end function "+";
-- Overloaded functions
function "-" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l -
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "-";
function "-" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
- r);
end function "-";
function "-" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l -
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "-";
function "-" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
- r);
end function "-";
-- Overloaded functions
function "*" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l *
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "*";
function "*" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
* r);
end function "*";
function "*" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l *
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "*";
function "*" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
* r);
end function "*";
-- Overloaded functions
function "/" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l /
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/";
function "/" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/ r);
end function "/";
function "/" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l /
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/";
function "/" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/ r);
end function "/";
-- Overloaded functions
function "rem" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l rem
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "rem";
function "rem" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
rem r);
end function "rem";
function "rem" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l rem
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "rem";
function "rem" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
rem r);
end function "rem";
function "mod" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l mod
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "mod";
function "mod" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
mod r);
end function "mod";
function "mod" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l mod
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "mod";
function "mod" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
mod r);
end function "mod";
-- Overloaded functions for integers
function "+" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l + to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)); -- rounding not needed
end function "+";
function "+" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
+ r);
end function "+";
function "+" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l + to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "+";
function "+" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
+ r);
end function "+";
-- Overloaded functions
function "-" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l - to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "-";
function "-" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
- r);
end function "-";
function "-" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l - to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "-";
function "-" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
- r);
end function "-";
-- Overloaded functions
function "*" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l * to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "*";
function "*" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
* r);
end function "*";
function "*" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l * to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "*";
function "*" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
* r);
end function "*";
-- Overloaded functions
function "/" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l / to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/";
function "/" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/ r);
end function "/";
function "/" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l / to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/";
function "/" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/ r);
end function "/";
-- Overloaded functions
function "rem" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l rem to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "rem";
function "rem" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
rem r);
end function "rem";
function "rem" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l rem to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "rem";
function "rem" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
rem r);
end function "rem";
function "mod" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l mod to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "mod";
function "mod" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
mod r);
end function "mod";
function "mod" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l mod to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "mod";
function "mod" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
mod r);
end function "mod";
-- overloaded compare functions
function "=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "=";
function "/=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/=";
function ">=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">=";
function "<=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<=";
function ">" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">";
function "<" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<";
function "=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
= r);
end function "=";
function "/=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/= r);
end function "/=";
function ">=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
>= r);
end function ">=";
function "<=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
<= r);
end function "<=";
function ">" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
> r);
end function ">";
function "<" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
< r);
end function "<";
function "=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l =
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "=";
function "/=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l /=
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/=";
function ">=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >=
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">=";
function "<=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <=
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<=";
function ">" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">";
function "<" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<";
function "=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
= r);
end function "=";
function "/=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/= r);
end function "/=";
function ">=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
>= r);
end function ">=";
function "<=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
<= r);
end function "<=";
function ">" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
> r);
end function ">";
function "<" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
< r);
end function "<";
function "=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l = to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "=";
function "/=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l /= to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/=";
function ">=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l >= to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">=";
function "<=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l <= to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<=";
function ">" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l > to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">";
function "<" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l < to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<";
function "=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
= r);
end function "=";
function "/=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/= r);
end function "/=";
function ">=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
>= r);
end function ">=";
function "<=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
<= r);
end function "<=";
function ">" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
> r);
end function ">";
function "<" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
< r);
end function "<";
function "=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l =
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "=";
function "/=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l /=
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/=";
function ">=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >=
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">=";
function "<=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <=
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<=";
function ">" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">";
function "<" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<";
function "=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
= r);
end function "=";
function "/=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/= r);
end function "/=";
function ">=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
>= r);
end function ">=";
function "<=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
<= r);
end function "<=";
function ">" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
> r);
end function ">";
function "<" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
< r);
end function "<";
-- rtl_synthesis off
-- synthesis translate_off
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
write(l, s, justified, field);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
write(l, s, justified, field);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable s : STRING(1 to value'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Error: end of string encountered"
severity error;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
assert i = value'low
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Warning: Value truncated " severity warning;
return;
elsif c = '.' then -- separator, ignore
assert (i = -1)
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Warning: Decimal point does not match number format "
severity warning;
elsif (char_to_MVL9plus(c) = error) then
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
good := true;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
good := false;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done
good := false;
return;
elsif c = '.' then -- separator, ignore
good := (i = -1);
elsif (char_to_MVL9plus(c) = error) then
good := false;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out sfixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Error end of string encountered"
severity error;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
assert i = value'low
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Warning: Value truncated " severity warning;
return;
elsif c = '.' then -- separator, ignore
assert (i = -1)
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Warning: Decimal point does not match number format "
severity warning;
elsif (char_to_MVL9plus(c) = error) then
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
good := true;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
good := false;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done
good := false;
return;
elsif c = '.' then -- separator, ignore
good := (i = -1);
elsif (char_to_MVL9plus(c) = error) then
good := false;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"FIXED_GENERIC_PKG.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD(L : inout LINE;
VALUE : out ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(ufixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2triBits(c, nybble, igood, true);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(ufixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.OREAD(ufixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2TriBits(c, nybble, igood, true);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')
report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2triBits(c, nybble, igood, false);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2TriBits(c, nybble, igood, false);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0');
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(sfixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2triBits(c, nybble, igood, true);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(sfixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.OREAD(sfixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2TriBits(c, nybble, igood, true);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))
report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2triBits(c, nybble, igood, false);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2TriBits(c, nybble, igood, false);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end if;
end loop;
good := igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'));
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"FIXED_GENERIC_PKG.HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD(L : inout LINE;
VALUE : out ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(ufixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2QuadBits(c, nybble, igood, true);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(ufixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.HREAD(ufixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2QuadBits(c, nybble, igood, true);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')
report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2QuadBits(c, nybble, igood, false);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2QuadBits(c, nybble, igood, false);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0');
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(sfixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2QuadBits(c, nybble, igood, true);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(sfixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.HREAD(sfixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2QuadBits(c, nybble, igood, true);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))
report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2QuadBits(c, nybble, igood, false);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2QuadBits(c, nybble, igood, false);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'));
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
-----------------------------------------------------------------------------
-- %%% Remove the following 3 functions. They are a duplicate needed for
-- testing
-----------------------------------------------------------------------------
-- purpose: Justify a string to the right
function justify (
value : STRING;
justified : SIDE := right;
field : width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function to_ostring (
value : STD_LOGIC_VECTOR;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return justify(result, justified, field);
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (
value : STD_LOGIC_VECTOR;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return justify(result, justified, field);
end if;
end function to_hstring;
-- %%% End remove here
function to_string (
value : ufixed;
justified : SIDE := right;
field : width := 0
) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low), justified, field);
elsif value'low > 0 then
return to_string (resize (value, value'high, -1), justified, field);
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
return justify(s, justified, field);
end if;
end if;
end function to_string;
function to_string (
value : sfixed;
justified : SIDE := right;
field : width := 0
) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low), justified, field);
elsif value'low > 0 then
return to_string (resize (value, value'high, -1), justified, field);
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
return justify(s, justified, field);
end if;
end if;
end function to_string;
function to_ostring (
value : ufixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant lne : INTEGER := (-VALUE'low+2)/3;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_ostring (resize (value, 2, value'low), justified, field);
elsif value'low > 0 then
return to_ostring (resize (value, value'high, -3), justified, field);
else
slv := to_slv (value);
return justify(to_ostring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
justified, field);
end if;
end if;
end function to_ostring;
function to_hstring (
value : ufixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant lne : INTEGER := (-VALUE'low+3)/4;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_hstring (resize (value, 3, value'low), justified, field);
elsif value'low > 0 then
return to_hstring (resize (value, value'high, -4), justified, field);
else
slv := to_slv (value);
return justify(to_hstring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
justified, field);
end if;
end if;
end function to_hstring;
function to_ostring (
value : sfixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+2)/3;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
begin
if value'length < 1 then
return NUS;
else
pad := (others => value(value'high));
if value'high < 0 then
return to_ostring (resize (value, 2, value'low), justified, field);
elsif value'low > 0 then
return to_ostring (resize (value, value'high, -3), justified, field);
else
slv := to_slv (value);
return justify(to_ostring(pad
& slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0)
& lpad),
justified, field);
end if;
end if;
end function to_ostring;
function to_hstring (
value : sfixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+3)/4;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
pad := (others => value(value'high));
if value'high < 0 then
return to_hstring (resize (value, 3, value'low), justified, field);
elsif value'low > 0 then
return to_hstring (resize (value, value'high, -4), justified, field);
else
slv := to_slv (value);
return justify(to_hstring(pad&slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
justified, field);
end if;
end if;
end function to_hstring;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : ufixed)
return ufixed is
variable result : ufixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : ufixed)
return ufixed is
variable result : ufixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : ufixed)
return ufixed is
variable result : ufixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : sfixed)
return sfixed is
variable result : sfixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : sfixed)
return sfixed is
variable result : sfixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : sfixed)
return sfixed is
variable result : sfixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- purpose: find a dot in a string, return -1 if no dot (internal function)
function finddot (
arg : STRING)
return INTEGER is
alias xarg : STRING (arg'length downto 1) is arg; -- make it a downto
begin
for i in xarg'reverse_range loop
if (xarg(i) = '.') then
return i-1;
end if;
end loop;
return -1;
end function finddot;
-- Direct converstion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return ufixed is
variable result : ufixed (bstring'length-2 downto 0);
variable result_nodot : ufixed (bstring'length-1 downto 0);
variable bstring_nodot : STRING (1 to bstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(bstring);
if (dot = -1) then
L := new STRING'(bstring);
read (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return result_nodot;
else
j := 1;
for i in 1 to bstring'high loop
if (bstring(i) /= '.') then
bstring_nodot(j) := bstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(bstring_nodot);
read (L, result, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return to_ufixed(to_slv(result), bstring'length-dot-2, -dot);
end if;
end function from_string;
-- Direct octal and hex converstion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return ufixed is
variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0);
variable ostring_nodot : STRING (1 to ostring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(ostring);
if (dot = -1) then
L := new STRING'(ostring);
oread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_ufixed(UNSIGNED(result_nodot));
else
j := 1;
for i in 1 to ostring'high loop
if (ostring(i) /= '.') then
ostring_nodot(j) := ostring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(ostring_nodot);
oread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_ufixed(result, (ostring'length-1-dot)*3-1, -dot*3);
end if;
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return ufixed is
variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0);
variable hstring_nodot : STRING (1 to hstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(hstring);
if (dot = -1) then
L := new STRING'(hstring);
hread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return to_ufixed(UNSIGNED(result_nodot));
else
j := 1;
for i in 1 to hstring'high loop
if (hstring(i) /= '.') then
hstring_nodot(j) := hstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(hstring_nodot);
hread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return to_ufixed(result, (hstring'length-1-dot)*4-1, -dot*4);
end if;
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return sfixed is
variable result : sfixed (bstring'length-2 downto 0);
variable result_nodot : sfixed (bstring'length-1 downto 0);
variable bstring_nodot : STRING (1 to bstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(bstring);
if (dot = -1) then
L := new STRING'(bstring);
read (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return result_nodot;
else
j := 1;
for i in 1 to bstring'high loop
if (bstring(i) /= '.') then
bstring_nodot(j) := bstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(bstring_nodot);
read (L, result, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return to_sfixed(to_slv(result), bstring'length-dot-2, -dot);
end if;
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return sfixed is
variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0);
variable ostring_nodot : STRING (1 to ostring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(ostring);
if (dot = -1) then
L := new STRING'(ostring);
oread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_sfixed(SIGNED(result_nodot));
else
j := 1;
for i in 1 to ostring'high loop
if (ostring(i) /= '.') then
ostring_nodot(j) := ostring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(ostring_nodot);
oread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_sfixed(result, (ostring'length-1-dot)*3-1, -dot*3);
end if;
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return sfixed is
variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0);
variable hstring_nodot : STRING (1 to hstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(hstring);
if (dot = -1) then
L := new STRING'(hstring);
hread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return sfixed(SIGNED(result_nodot));
else
j := 1;
for i in 1 to hstring'high loop
if (hstring(i) /= '.') then
hstring_nodot(j) := hstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(hstring_nodot);
hread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return to_sfixed(result, (hstring'length-1-dot)*4-1, -dot*4);
end if;
end function from_hstring;
-- synthesis translate_on
-- rtl_synthesis on
function to_StdLogicVector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_StdLogicVector;
function to_Std_Logic_Vector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_Std_Logic_Vector;
function to_StdLogicVector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_StdLogicVector;
function to_Std_Logic_Vector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_Std_Logic_Vector;
function to_StdULogicVector (
arg : ufixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_StdULogicVector;
function to_Std_ULogic_Vector (
arg : ufixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_Std_ULogic_Vector;
function to_StdULogicVector (
arg : sfixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_StdULogicVector;
function to_Std_ULogic_Vector (
arg : sfixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_Std_ULogic_Vector;
end package body fixed_pkg;
|
------------------------------------------------------------------------------
-- "fixed_pkg" package contains functions for fixed point math.
-- Please see the documentation for the fixed point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_pkg.all;
-- Last Modified: $Date: 2006/05/09 19:21:24 $
-- RCS ID: $Id: fixed_pkg_c.vhd,v 1.1 2006/05/09 19:21:24 sandeepd Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- synthesis translate_off
use std.textio.all;
-- synthesis translate_on
package fixed_pkg is
--%%% Uncomment the Generics
-- new work.fixed_generic_pkg
-- generic map (
-- fixed_round_style => true; -- fixed_round
-- fixed_overflow_style => true; -- fixed_saturate
-- fixed_guard_bits => 3; -- number of guard bits
-- no_warning => false -- show warnings
-- );
--%%% REMOVE THE REST OF THIS FILE.
constant fixed_round_style : BOOLEAN := true; -- round
constant fixed_overflow_style : BOOLEAN := true; -- saturate
constant fixed_guard_bits : NATURAL := 3; -- number of guard bits
constant no_warning : BOOLEAN := false; -- issue warnings
-- Author David Bishop ([email protected])
-- These 5 constants are used as defaults.
-- There is a mechanism to override them in every function
constant fixed_round : BOOLEAN := true; -- Turn on rounding routine
constant fixed_truncate : BOOLEAN := false; -- Trun off rounding routine
constant fixed_saturate : BOOLEAN := true; -- Saturate large numbers
constant fixed_wrap : BOOLEAN := false; -- Wrap large numbers
constant fixedsynth_or_real : BOOLEAN; -- differed constant
-- base Unsigned fixed point type, downto direction assumed
type ufixed is array (INTEGER range <>) of STD_LOGIC;
-- base Signed fixed point type, downto direction assumed
type sfixed is array (INTEGER range <>) of STD_LOGIC;
-----------------------------------------------------------------------------
-- Fixed point type is defined as follows:
-- 0000000000
-- 4321012345
-- 4 0 -5
-- The decimal point is assumed between the "0" and "-1" index
-- Thus "0011010000" = 6.5 and would be written as 00110.10000
-- All types are assumed to be in the "downto" direction.
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
-- Modify the sign of the number, 2's complement
function "abs" (arg : sfixed) return sfixed;
function "-" (arg : sfixed)return sfixed;
-- Convert a signed fixed to an unsigned fixed
function "abs" (arg : sfixed) return ufixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(max(a,c)+1 downto min(b,d))
function "+" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(max(a,c)+1 downto min(b,d))
function "+" (l, r : sfixed) return sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(max(a,c)+1 downto min(b,d))
function "-" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(max(a,c)+1 downto min(b,d))
function "-" (l, r : sfixed) return sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : sfixed) return sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : sfixed) return sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (l, r : ufixed) return ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (l, r : sfixed) return sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (l, r : ufixed) return ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (l, r : sfixed) return sfixed;
----------------------------------------------------------------------------
-- Overload routines. In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : ufixed; r : REAL) return ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : ufixed) return ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto min(0,b))
function "+" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d))
function "+" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : ufixed; r : REAL) return ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : ufixed) return ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto min(0,b))
function "-" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d))
function "-" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : ufixed; r : REAL) return ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : ufixed) return ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : ufixed; r : REAL) return ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : ufixed) return ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : ufixed; r : REAL) return ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : ufixed) return ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto min(b,0))
function "rem" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto min(d,0))
function "rem" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : ufixed; r : REAL) return ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : ufixed) return ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto min(b,0))
function "mod" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto min(d,0))
function "mod" (l : NATURAL; r : ufixed) return ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto min(0,b))
function "+" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto min(0,d))
function "+" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto min(0,b))
function "-" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto min(0,d))
function "-" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : sfixed; r : REAL) return sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : sfixed) return sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto min(b,0))
function "rem" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto min(d,0))
function "rem" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : sfixed; r : REAL) return sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : sfixed) return sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto min(b,0))
function "mod" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto min(d,0))
function "mod" (l : INTEGER; r : sfixed) return sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : sfixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : sfixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style)
return ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : sfixed;
constant round_style : BOOLEAN := fixed_round_style)
return sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style)
return ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : sfixed;
constant overflow_style : BOOLEAN := fixed_overflow_style;
constant round_style : BOOLEAN := fixed_round_style)
return sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (max(a,c) downto min(b,d))
procedure add_carry (
L, R : in ufixed;
c_in : in STD_ULOGIC;
result : out ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (max(a,c) downto min(b,d))
procedure add_carry (
L, R : in sfixed;
c_in : in STD_ULOGIC;
result : out sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : ufixed; N : integer) return ufixed;
function scalb (y : ufixed; N : SIGNED) return ufixed;
function scalb (y : sfixed; N : integer) return sfixed;
function scalb (y : sfixed; N : SIGNED) return sfixed;
function Is_Negative (arg : sfixed) return BOOLEAN;
--===========================================================================
-- Comparison Operators
--===========================================================================
function ">" (l, r : ufixed) return BOOLEAN;
function ">" (l, r : sfixed) return BOOLEAN;
function "<" (l, r : ufixed) return BOOLEAN;
function "<" (l, r : sfixed) return BOOLEAN;
function "<=" (l, r : ufixed) return BOOLEAN;
function "<=" (l, r : sfixed) return BOOLEAN;
function ">=" (l, r : ufixed) return BOOLEAN;
function ">=" (l, r : sfixed) return BOOLEAN;
function "=" (l, r : ufixed) return BOOLEAN;
function "=" (l, r : sfixed) return BOOLEAN;
function "/=" (l, r : ufixed) return BOOLEAN;
function "/=" (l, r : sfixed) return BOOLEAN;
--%%% Uncomment the following (new syntax)
-- function "?=" (L, R : ufixed) return BOOLEAN;
-- function "?=" (L, R : sfixed) return BOOLEAN;
-- --%%% remove the following (old syntax)
function \?=\ (L, R : ufixed) return STD_ULOGIC;
function \?=\ (L, R : sfixed) return STD_ULOGIC;
-- These need to be overloaded for sfixed and ufixed
function \?/=\ (L, R : ufixed) return STD_ULOGIC;
function \?>\ (L, R : ufixed) return STD_ULOGIC;
function \?>=\ (L, R : ufixed) return STD_ULOGIC;
function \?<\ (L, R : ufixed) return STD_ULOGIC;
function \?<=\ (L, R : ufixed) return STD_ULOGIC;
function \?/=\ (L, R : sfixed) return STD_ULOGIC;
function \?>\ (L, R : sfixed) return STD_ULOGIC;
function \?>=\ (L, R : sfixed) return STD_ULOGIC;
function \?<\ (L, R : sfixed) return STD_ULOGIC;
function \?<=\ (L, R : sfixed) return STD_ULOGIC;
-- %%% Replace with the following (new syntax)
-- function "?=" (L, R : ufixed) return STD_ULOGIC;
-- function "?/=" (L, R : ufixed) return STD_ULOGIC;
-- function "?>" (L, R : ufixed) return STD_ULOGIC;
-- function "?>=" (L, R : ufixed) return STD_ULOGIC;
-- function "?<" (L, R : ufixed) return STD_ULOGIC;
-- function "?<=" (L, R : ufixed) return STD_ULOGIC;
-- function "?=" (L, R : sfixed) return STD_ULOGIC;
-- function "?/=" (L, R : sfixed) return STD_ULOGIC;
-- function "?>" (L, R : sfixed) return STD_ULOGIC;
-- function "?>=" (L, R : sfixed) return STD_ULOGIC;
-- function "?<" (L, R : sfixed) return STD_ULOGIC;
-- function "?<=" (L, R : sfixed) return STD_ULOGIC;
function std_match (L, R : ufixed) return BOOLEAN;
function std_match (L, R : sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : ufixed) return ufixed;
function minimum (l, r : ufixed) return ufixed;
function maximum (l, r : sfixed) return sfixed;
function minimum (l, r : sfixed) return sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "max(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : ufixed) return BOOLEAN;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : ufixed; r : REAL) return BOOLEAN;
function "/=" (l : ufixed; r : REAL) return BOOLEAN;
function ">=" (l : ufixed; r : REAL) return BOOLEAN;
function "<=" (l : ufixed; r : REAL) return BOOLEAN;
function ">" (l : ufixed; r : REAL) return BOOLEAN;
function "<" (l : ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : ufixed) return BOOLEAN;
function "/=" (l : REAL; r : ufixed) return BOOLEAN;
function ">=" (l : REAL; r : ufixed) return BOOLEAN;
function "<=" (l : REAL; r : ufixed) return BOOLEAN;
function ">" (l : REAL; r : ufixed) return BOOLEAN;
function "<" (l : REAL; r : ufixed) return BOOLEAN;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "max(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : sfixed) return BOOLEAN;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : sfixed; r : REAL) return BOOLEAN;
function "/=" (l : sfixed; r : REAL) return BOOLEAN;
function ">=" (l : sfixed; r : REAL) return BOOLEAN;
function "<=" (l : sfixed; r : REAL) return BOOLEAN;
function ">" (l : sfixed; r : REAL) return BOOLEAN;
function "<" (l : sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : sfixed) return BOOLEAN;
function "/=" (l : REAL; r : sfixed) return BOOLEAN;
function ">=" (l : REAL; r : sfixed) return BOOLEAN;
function "<=" (l : REAL; r : sfixed) return BOOLEAN;
function ">" (l : REAL; r : sfixed) return BOOLEAN;
function "<" (l : REAL; r : sfixed) return BOOLEAN;
--===========================================================================
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--===========================================================================
function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed;
function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed;
function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed;
function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : ufixed) return ufixed;
function "and" (L, R : ufixed) return ufixed;
function "or" (L, R : ufixed) return ufixed;
function "nand" (L, R : ufixed) return ufixed;
function "nor" (L, R : ufixed) return ufixed;
function "xor" (L, R : ufixed) return ufixed;
function "xnor" (L, R : ufixed) return ufixed;
function "not" (L : sfixed) return sfixed;
function "and" (L, R : sfixed) return sfixed;
function "or" (L, R : sfixed) return sfixed;
function "nand" (L, R : sfixed) return sfixed;
function "nor" (L, R : sfixed) return sfixed;
function "xor" (L, R : sfixed) return sfixed;
function "xnor" (L, R : sfixed) return sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "and" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "or" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "or" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "and" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "and" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "or" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "or" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed;
-- Reduction operators, same as numeric_std functions
-- %%% remove 12 functions (old syntax)
function and_reduce(arg : ufixed) return STD_ULOGIC;
function nand_reduce(arg : ufixed) return STD_ULOGIC;
function or_reduce(arg : ufixed) return STD_ULOGIC;
function nor_reduce(arg : ufixed) return STD_ULOGIC;
function xor_reduce(arg : ufixed) return STD_ULOGIC;
function xnor_reduce(arg : ufixed) return STD_ULOGIC;
function and_reduce(arg : sfixed) return STD_ULOGIC;
function nand_reduce(arg : sfixed) return STD_ULOGIC;
function or_reduce(arg : sfixed) return STD_ULOGIC;
function nor_reduce(arg : sfixed) return STD_ULOGIC;
function xor_reduce(arg : sfixed) return STD_ULOGIC;
function xnor_reduce(arg : sfixed) return STD_ULOGIC;
-- %%% Uncomment the following 12 functions (new syntax)
-- function "and" ( arg : ufixed ) RETURN std_ulogic;
-- function "nand" ( arg : ufixed ) RETURN std_ulogic;
-- function "or" ( arg : ufixed ) RETURN std_ulogic;
-- function "nor" ( arg : ufixed ) RETURN std_ulogic;
-- function "xor" ( arg : ufixed ) RETURN std_ulogic;
-- function "xnor" ( arg : ufixed ) RETURN std_ulogic;
-- function "and" ( arg : sfixed ) RETURN std_ulogic;
-- function "nand" ( arg : sfixed ) RETURN std_ulogic;
-- function "or" ( arg : sfixed ) RETURN std_ulogic;
-- function "nor" ( arg : sfixed ) RETURN std_ulogic;
-- function "xor" ( arg : sfixed ) RETURN std_ulogic;
-- function "xnor" ( arg : sfixed ) RETURN std_ulogic;
-- returns arg'low-1 if not found
function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER;
function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER;
-- returns arg'high+1 if not found
function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER;
function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER;
--===========================================================================
-- RESIZE Functions
--===========================================================================
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is true, then the result will be rounded. If the MSB
-- of the remainder is a "1" AND the LSB of the unround result is a '1' or
-- the lower bits of the remainder include a '1' then the result will be
-- increased by the smallest representable number for that type.
-- The default is "true" for round_style.
-- "overflow_style" can be "true" (saturate mode) or "false" (wrap mode).
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed;
-- "size_res" functions create the size of the output from the length
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : ufixed; -- input
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
function resize (
arg : sfixed; -- input
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
--===========================================================================
-- Conversion Functions
--===========================================================================
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding
return ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding
return ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return ufixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return ufixed;
-- Performs a casting. ufixed (arg'range) is returned
function to_ufixed (
arg : UNSIGNED) -- unsigned
return ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : ufixed; -- fixed point input
size_res : UNSIGNED; -- used for length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : ufixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return NATURAL;
-- Integer to sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed;
-- signed to sfixed
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : SIGNED) -- signed
return sfixed;
-- unsigned fixed point to signed fixed point (adds a "0" sign bit)
function add_sign (
arg : ufixed) -- unsigned fixed point
return sfixed;
-- signed fixed point to signed
function to_signed (
arg : sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED;
-- signed fixed point to signed
function to_signed (
arg : sfixed; -- fixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED;
-- signed fixed point to real
function to_real (
arg : sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : sfixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return INTEGER;
-- Because of the farily complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER;
function ufixed_low (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER;
function sfixed_high (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER;
function sfixed_low (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function saturate (
size_res : ufixed) -- only the size of this is used
return ufixed;
function saturate (
size_res : sfixed) -- only the size of this is used
return sfixed;
--===========================================================================
-- Translation Functions
--===========================================================================
-- Maps meta-logical values
function to_01 (
s : ufixed; -- fixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return ufixed;
-- maps meta-logical values
function to_01 (
s : sfixed; -- fixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return sfixed;
function Is_X (arg : ufixed) return BOOLEAN;
function Is_X (arg : sfixed) return BOOLEAN;
function to_X01 (arg : ufixed) return ufixed;
function to_X01 (arg : sfixed) return sfixed;
function to_X01Z (arg : ufixed) return ufixed;
function to_X01Z (arg : sfixed) return sfixed;
function to_UX01 (arg : ufixed) return ufixed;
function to_UX01 (arg : sfixed) return sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not cast these vectors because of their negative index.
function to_slv (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR;
-- alias to_StdLogicVector is to_slv [ufixed return STD_LOGIC_VECTOR];
-- alias to_Std_Logic_Vector is to_slv [ufixed return STD_LOGIC_VECTOR];
function to_slv (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR;
-- alias to_StdLogicVector is to_slv [sfixed return STD_LOGIC_VECTOR];
-- alias to_Std_Logic_Vector is to_slv [sfixed return STD_LOGIC_VECTOR];
function to_sulv (
arg : ufixed) -- fp vector
return STD_ULOGIC_VECTOR;
-- alias to_StdULogicVector is to_sulv [ufixed return STD_ULOGIC_VECTOR];
-- alias to_Std_ULogic_Vector is to_sulv [ufixed return STD_ULOGIC_VECTOR];
function to_sulv (
arg : sfixed) -- fp vector
return STD_ULOGIC_VECTOR;
-- alias to_StdULogicVector is to_sulv [sfixed return STD_ULOGIC_VECTOR];
-- alias to_Std_ULogic_Vector is to_sulv [sfixed return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return ufixed;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
--===========================================================================
-- string and textio Functions
--===========================================================================
-- rtl_synthesis off
-- synthesis translate_off
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out ufixed);
procedure READ(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out sfixed);
procedure READ(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, ufixed, SIDE, width];
alias bwrite is WRITE [LINE, sfixed, SIDE, width];
alias bread is READ [LINE, ufixed];
alias bread is READ [LINE, ufixed, BOOLEAN];
alias bread is READ [LINE, sfixed];
alias bread is READ [LINE, sfixed, BOOLEAN];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out ufixed);
procedure OREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out sfixed);
procedure OREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN);
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out ufixed);
procedure HREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out sfixed);
procedure HREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN);
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (
value : ufixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
alias to_bstring is to_string [ufixed, SIDE, width return STRING];
function to_ostring (
value : ufixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function to_hstring (
value : ufixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function to_string (
value : sfixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
alias to_bstring is to_string [sfixed, SIDE, width return STRING];
function to_ostring (
value : sfixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function to_hstring (
value : sfixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER return ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER return sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : ufixed)
return ufixed;
alias from_bstring is from_string [STRING, ufixed return ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : ufixed)
return ufixed;
function from_hstring (
hstring : STRING; -- hex string
size_res : ufixed)
return ufixed;
function from_string (
bstring : STRING; -- binary string
size_res : sfixed)
return sfixed;
alias from_bstring is from_string [STRING, sfixed return sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : sfixed)
return sfixed;
function from_hstring (
hstring : STRING; -- hex string
size_res : sfixed)
return sfixed;
-- Direct converstion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return ufixed;
alias from_bstring is from_string [STRING return ufixed];
-- Direct octal and hex converstion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return ufixed;
function from_hstring (
hstring : STRING) -- hex string
return ufixed;
function from_string (
bstring : STRING) -- binary string
return sfixed;
alias from_bstring is from_string [STRING return sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return sfixed;
function from_hstring (
hstring : STRING) -- hex string
return sfixed;
-- synthesis translate_on
-- rtl_synthesis on
-- This type is here for the floating point package.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round to positive
round_neginf, -- Round to negate
round_zero); -- Round towards zero
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
function to_StdLogicVector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR;
function to_Std_Logic_Vector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR;
function to_StdLogicVector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR;
function to_Std_Logic_Vector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR;
end package fixed_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_textio.all; -- %%% for testing only
package body fixed_pkg is
-- Author David Bishop ([email protected])
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : ufixed (0 downto 1) := (others => '0');
constant NASF : sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
--%%% Can be removed in vhdl-200x, will be implicit.
-- purpose: To find the largest of 2 numbers
function maximum (l, r : INTEGER)
return INTEGER is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
function minimum (l, r : INTEGER)
return INTEGER is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
-- %%% Remove the following function (duplicates of new numeric_std)
function "sra" (arg : SIGNED; count : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(arg, count);
else
return SHIFT_LEFT(arg, -count);
end if;
end function "sra";
-- %%% Replace or_reducex with "or", and_reducex with "and", and
-- %%% xor_reducex with "xor", then remove the following 3 functions
-- purpose: OR all of the bits in a vector together
-- This is a copy of the proposed "or_reduce" from 1076.3
function or_reducex (arg : STD_LOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_LOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_LOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reducex (BUS_int (BUS_int'left downto Half));
Lower := or_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reducex;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reducex (arg : STD_LOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_LOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_LOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reducex (BUS_int (BUS_int'left downto Half));
Lower := and_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reducex;
function xor_reducex (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reducex (BUS_int (BUS_int'left downto Half));
Lower := xor_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reducex;
--%%% remove the following function and table
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% end remove
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (L = INTEGER'low or R = INTEGER'low) then
return 0; -- error condition
end if;
return minimum (L, R);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (L = INTEGER'low or R = INTEGER'low) then
report "FIXED_GENERIC_PKG: Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : sfixed) -- input
return sfixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : sfixed (arg'range);
begin -- function cleanvec
assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low))
report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : ufixed) -- input
return ufixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : ufixed (arg'range);
begin -- function cleanvec
assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low))
report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type cast a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
-- variable j : INTEGER := arg'high; -- index for arg
begin -- function to_fixed
result := ufixed(arg);
-- floop : for i in result'range loop
-- result(i) := arg(j); -- res(4) := arg (4 + 3)
-- j := j - 1;
-- end loop floop;
return result;
end function to_fixed;
-- Type cast a "signed" into an "sfixed", used internally
function to_fixed (
arg : SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
-- variable j : INTEGER := arg'high; -- index for arg
begin -- function to_fixed
result := sfixed(arg);
-- floop : for i in result'range loop
-- result(i) := arg(j); -- res(4) := arg (4 + 3)
-- j := j - 1;
-- end loop floop;
return result;
end function to_fixed;
-- Type cast a "ufixed" into an "unsigned", used internally
function to_uns (
arg : ufixed) -- fp vector
return UNSIGNED is
subtype t is UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
-- floop : for i in slv'range loop
-- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3)
-- end loop floop;
return UNSIGNED(to_X01(std_logic_vector(slv)));
end function to_uns;
-- Type cast an "sfixed" into a "signed", used internally
function to_s (
arg : sfixed) -- fp vector
return SIGNED is
subtype t is SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
-- floop : for i in slv'range loop
-- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3)
-- end loop floop;
return SIGNED(to_X01(std_logic_vector(slv)));
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in ufixed;
result : out ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0) :=
(others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in sfixed;
result : out sfixed;
overflowx : out BOOLEAN) is
variable args, ress : SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or_reducex (STD_LOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : ufixed;
remainder : ufixed;
overflow_style : BOOLEAN := fixed_overflow_style)
return ufixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reducex (to_slv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : sfixed;
remainder : sfixed;
overflow_style : BOOLEAN := fixed_overflow_style)
return sfixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reducex (to_slv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- else
-- result(result'high) := arg(arg'high); -- fix sign bit in wrap
end if;
end if;
return result;
end function round_fixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- casting functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_slv (
arg : ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0);
variable slv : t;
begin
if arg'length < 1 then
return NSLV;
end if;
slv := t (arg);
return slv;
end function to_slv;
function to_slv (
arg : sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0);
variable slv : t;
begin
if arg'length < 1 then
return NSLV;
end if;
slv := t (arg);
return slv;
end function to_slv;
function to_sulv (
arg : ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
begin
return to_stdulogicvector (to_slv(arg));
end function to_sulv;
function to_sulv (
arg : sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
begin
return to_stdulogicvector (to_slv(arg));
end function to_sulv;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_UFIXED (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_SFIXED (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
begin
return to_ufixed (arg => to_stdlogicvector(arg),
left_index => left_index,
right_index => right_index);
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
begin
return to_sfixed (arg => to_stdlogicvector(arg),
left_index => left_index,
right_index => right_index);
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : sfixed) -- fixed point input
return sfixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : sfixed) -- fixed point input
return sfixed is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
function "abs" (arg : sfixed) return ufixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : sfixed(left_index+1 downto right_index);
variable result : ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := ufixed (xarg (left_index downto right_index));
return result;
end function "abs";
-- Addition
function "+" (
l, r : ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return ufixed is -- ufixed(a+c+1 downto b+d)
variable lslv : UNSIGNED (l'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (r'length+l'length-1 downto 0);
variable result : ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return sfixed is -- sfixed(a+c+1 downto b+d)
variable lslv : SIGNED (l'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (r'length+l'length-1 downto 0);
variable result : sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed is
variable result : ufixed (l'high - mine(r'low, r'low)
downto mine (l'low, l'low) - r'high -1);
variable dresult : ufixed (result'high downto result'low -guard_bits);
variable lresize : ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (l, lresize'high, lresize'low);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
round_style => round_style,
overflow_style => fixed_wrap); -- overflow impossible
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : sfixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed is
variable result : sfixed (l'high - mine(r'low, r'low)+1
downto mine (l'low, l'low) - r'high);
variable dresult : sfixed (result'high downto result'low-guard_bits);
variable lresize : sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : SIGNED (lresize'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (l, lresize'high, lresize'low);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
round_style => round_style,
overflow_style => fixed_wrap); -- overflow impossible
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed is
constant one : ufixed (0 downto 0) := "1";
begin
return divide(l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : sfixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed is
constant one : sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide(l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : ufixed) -- fixed point input
return ufixed is
begin
return remainder (l => l,
r => r,
round_style => fixed_round_style);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : sfixed) -- fixed point input
return sfixed is
begin
return remainder (l => l,
r => r,
round_style => fixed_round_style);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style)
return ufixed is
variable result : ufixed (minimum(l'high, r'high) downto mine(l'low, r'low));
variable dresult : ufixed (r'high downto r'low);
variable lresize : ufixed (maximum(l'high, r'low) downto mins(r'low, r'low));
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rslv := to_uns (cleanvec(r));
if (rslv = 0) then
report "FIXED_GENERIC_PKG.rem uFixed point Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap,
round_style => round_style);
-- result(result'high downto r'low) := dresult(result'high downto r'low);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : sfixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style)
return sfixed is
variable l_abs : ufixed (l'range);
variable r_abs : ufixed (r'range);
variable result : sfixed (minimum(r'high, l'high) downto mine(r'low, l'low));
variable neg_result : sfixed (minimum(r'high, l'high)+1 downto mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := abs(l);
r_abs := abs(r);
result := sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : ufixed) -- fixed point input
return ufixed is
begin
return modulo (l => l,
r => r,
round_style => fixed_round_style);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : sfixed) -- fixed point input
return sfixed is
begin
return modulo(l => l,
r => r,
round_style => fixed_round_style);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style)
return ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : sfixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style;
constant round_style : BOOLEAN := fixed_round_style)
return sfixed is
variable l_abs : ufixed (l'range);
variable r_abs : ufixed (r'range);
variable result : sfixed (r'high downto
mine(r'low, l'low));
variable dresult : sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := abs(l);
r_abs := abs(r);
dresult := "0" & sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in ufixed;
c_in : in STD_ULOGIC;
result : out ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
variable cx : UNSIGNED (0 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in sfixed;
c_in : in STD_ULOGIC;
result : out sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index
downto 0);
variable result_slv : SIGNED (left_index-right_index
downto 0);
variable cx : SIGNED (1 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : ufixed; N : integer) return ufixed is
variable result : ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : ufixed; N : SIGNED) return ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : sfixed; N : integer) return sfixed is
variable result : sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : sfixed; N : SIGNED) return sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'low to arg'high loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_lsb;
function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'high downto arg'low loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_msb;
function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'low to arg'high loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_lsb;
function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'high downto arg'low loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_msb;
function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_slv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) and to_slv(R);
else
report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) or to_slv(R);
else
report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nand to_slv(R);
else
report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nor to_slv(R);
else
report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xnor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_slv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) and to_slv(R);
else
report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) or to_slv(R);
else
report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nand to_slv(R);
else
report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nor to_slv(R);
else
report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xnor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operators, same as numeric_std functions
-- %%% remove 12 functions (old syntax)
function and_reduce(arg : ufixed) return STD_ULOGIC is
begin
return and_reducex (to_slv(arg));
end function and_reduce;
function nand_reduce(arg : ufixed) return STD_ULOGIC is
begin
return not and_reducex (to_slv(arg));
end function nand_reduce;
function or_reduce(arg : ufixed) return STD_ULOGIC is
begin
return or_reducex (to_slv(arg));
end function or_reduce;
function nor_reduce(arg : ufixed) return STD_ULOGIC is
begin
return not or_reducex (to_slv(arg));
end function nor_reduce;
function xor_reduce(arg : ufixed) return STD_ULOGIC is
begin
return xor_reducex (to_slv(arg));
end function xor_reduce;
function xnor_reduce(arg : ufixed) return STD_ULOGIC is
begin
return not xor_reducex (to_slv(arg));
end function xnor_reduce;
function and_reduce(arg : sfixed) return STD_ULOGIC is
begin
return and_reducex (to_slv(arg));
end function and_reduce;
function nand_reduce(arg : sfixed) return STD_ULOGIC is
begin
return not and_reducex (to_slv(arg));
end function nand_reduce;
function or_reduce(arg : sfixed) return STD_ULOGIC is
begin
return or_reducex (to_slv(arg));
end function or_reduce;
function nor_reduce(arg : sfixed) return STD_ULOGIC is
begin
return not or_reducex (to_slv(arg));
end function nor_reduce;
function xor_reduce(arg : sfixed) return STD_ULOGIC is
begin
return xor_reducex (to_slv(arg));
end function xor_reduce;
function xnor_reduce(arg : sfixed) return STD_ULOGIC is
begin
return not xor_reducex (to_slv(arg));
end function xnor_reduce;
-- %%% Uncomment the following 12 functions (new syntax)
-- function "and" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return and to_slv(arg);
-- end function "and";
-- function "nand" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return nand to_slv(arg);
-- end function "nand";;
-- function "or" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return or to_slv(arg);
-- end function "or";
-- function "nor" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return nor to_slv(arg);
-- end function "nor";
-- function "xor" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return xor to_slv(arg);
-- end function "xor";
-- function "xnor" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return xnor to_slv(arg);
-- end function "xnor";
-- function "and" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return and to_slv(arg);
-- end function "and";;
-- function "nand" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return nand to_slv(arg);
-- end function "nand";;
-- function "or" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return or to_slv(arg);
-- end function "or";
-- function "nor" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return nor to_slv(arg);
-- end function "nor";
-- function "xor" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return xor to_slv(arg);
-- end function "xor";
-- function "xnor" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return xnor to_slv(arg);
-- end function "xnor";
-- %%% Replace with the following (new syntax)
-- function "?=" (L, R : ufixed) return STD_ULOGIC is
function \?=\ (L, R : ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '1';
for i in lresize'reverse_range loop
result1 := \?=\(lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- end function "?=";
-- function "?/=" (L, R : ufixed) return STD_ULOGIC is
function \?/=\ (L, R : ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?/=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '0';
for i in lresize'reverse_range loop
result1 := \?/=\ (lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- end function "?/=";
-- function "?>" (L, R : ufixed) return STD_ULOGIC is
function \?>\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- end function "?>";
-- function "?>=" (L, R : ufixed) return STD_ULOGIC is
function \?>=\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- end function "?>=";
-- function "?<" (L, R : ufixed) return STD_ULOGIC is
function \?<\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- end function "?<";
-- function "?<=" (L, R : ufixed) return STD_ULOGIC is
function \?<=\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- end function "?<=";
-- function "?=" (L, R : sfixed) return STD_ULOGIC is
function \?=\ (L, R : sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '1';
for i in lresize'reverse_range loop
result1 := \?=\ (lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- end function "?=";
-- function "?/=" (L, R : sfixed) return STD_ULOGIC is
function \?/=\ (L, R : sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?/=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '0';
for i in lresize'reverse_range loop
result1 := \?/=\ (lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- end function "?/=";
-- function "?>" (L, R : sfixed) return STD_ULOGIC is
function \?>\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- end function "?>";
-- function "?>=" (L, R : sfixed) return STD_ULOGIC is
function \?>=\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- end function "?>=";
-- function "?<" (L, R : sfixed) return STD_ULOGIC is
function \?<\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- end function "?<";
-- function "?<=" (L, R : sfixed) return STD_ULOGIC is
function \?<=\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- end function "?<=";
-- %%% end replace
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_slv(L), to_slv(R));
else
report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_slv(L), to_slv(R));
else
report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
--%%% end remove
-- compare functions
function "=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : ufixed) return ufixed is
begin
if l > r then return l;
else return r;
end if;
end function maximum;
function maximum (l, r : sfixed) return sfixed is
begin
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (l, r : ufixed) return ufixed is
begin
if l > r then return r;
else return l;
end if;
end function minimum;
function minimum (l, r : sfixed) return sfixed is
begin
if l > r then return r;
else return l;
end if;
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return ufixed is
variable argx : INTEGER;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : ufixed (left_index downto fw) := (others => '0');
variable sresult : UNSIGNED (left_index downto 0); -- integer portion
variable bound : NATURAL; -- find the numerical bounds
begin
if (left_index < fw) then
return NAUF;
end if;
if left_index >= 0 then
if (left_index < 30) then
bound := 2**(left_index+1);
else
bound := INTEGER'high;
end if;
end if;
if (arg /= 0) then
if arg >= bound or left_index < 0 then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_UFIXED(NATURAL): vector truncated"
severity warning;
if (overflow_style = fixed_wrap) then -- wrap
if bound = 0 then
argx := 0;
else
argx := arg mod bound;
end if;
else -- saturate
return saturate (result'high, result'low);
end if;
else
argx := arg;
end if;
else
return result; -- return zero
end if;
sresult := to_unsigned (argx, sresult'high+1);
result := resize (arg => ufixed (sresult),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
variable argx : INTEGER;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : sfixed (left_index downto fw) := (others => '0');
variable sresult : SIGNED (left_index+1 downto 0); -- integer portion
variable bound : NATURAL := 0;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if left_index >= 0 then
if (left_index < 30) then
bound := 2**(left_index);
else
bound := INTEGER'high;
end if;
end if;
if (arg /= 0) then
if (arg >= bound or arg < -bound or left_index < 0) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_wrap then -- wrap
if bound = 0 then -- negative integer_range trap
argx := 0;
else -- shift off the top bits
argx := arg rem (bound*2);
end if;
else -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
else
argx := arg;
end if;
else
return result; -- return zero
end if;
sresult := to_signed (argx, sresult'length);
result := resize (arg => sfixed (sresult),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed is
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : ufixed (left_index downto fw) := (others => '0');
variable Xresult : ufixed (left_index downto fw-guard_bits) := (others => '0');
variable presult : REAL;
variable overflow_needed : BOOLEAN;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
report "FIXED_GENERIC_PKG.TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert NO_WARNING report "FIXED_GENERIC_PKG.TO_UFIXED(REAL): vector truncated"
severity warning;
overflow_needed := (overflow_style = fixed_saturate);
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed is
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : sfixed (left_index downto fw) := (others => '0');
variable Xresult : sfixed (left_index+1 downto fw-guard_bits) := (others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert NO_WARNING report "FIXED_GENERIC_PKG.TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : ufixed (left_index downto fw);
begin
if arg'length < 1 or (left_index < fw) then
return NAUF;
end if;
result := resize (arg => ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- casted version
function to_ufixed (
arg : UNSIGNED) -- unsigned
return ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NAUF;
end if;
return ufixed(xarg);
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : sfixed (left_index downto fw);
begin
if arg'length < 1 or (left_index < fw) then
return NASF;
end if;
result := resize (arg => sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- casted version
function to_sfixed (
arg : SIGNED) -- signed
return sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NASF;
end if;
return sfixed(xarg);
end function to_sfixed;
function add_sign (arg : ufixed) return sfixed is
variable result : sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function add_sign;
-- Because of the farily complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
constant sat : ufixed (left_index downto right_index) := (others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable sat : sfixed (left_index downto right_index) := (others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : ufixed) -- only the size of this is used
return ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : sfixed) -- only the size of this is used
return sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return ufixed is
variable result : ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_UFIX (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return sfixed is
variable result : sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_SFIX (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : ufixed; -- ufixed point input
size_res : UNSIGNED; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : sfixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : sfixed; -- ufixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : ufixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := cleanvec(arg);
if (Is_X(arg_int)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : sfixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := cleanvec(arg);
if (Is_X(arg_int)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := abs(arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : ufixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return NATURAL is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNSIGNED (minimum(31, left_index+1) downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : sfixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return INTEGER is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable arg_s : SIGNED (minimum(31, left_index+1) downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : ufixed; -- ufixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return ufixed is
variable result : ufixed (s'range); -- result
begin
for i in s'range loop
case s(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := XMAP;
end case;
end loop;
return result;
end function to_01;
function to_01 (
s : sfixed; -- ufixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return sfixed is
variable result : sfixed (s'range);
begin
for i in s'range loop
case s(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := XMAP;
end case;
end loop;
return result;
end function to_01;
function Is_X (
arg : ufixed)
return BOOLEAN is
variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_slv(arg);
return Is_X(argslv);
end function Is_X;
function Is_X (
arg : sfixed)
return BOOLEAN is
variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_slv(arg);
return Is_X(argslv);
end function Is_X;
function To_X01 (
arg : ufixed)
return ufixed is
begin
return to_ufixed (To_X01(to_slv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : sfixed)
return sfixed is
begin
return to_sfixed (To_X01(to_slv(arg)), arg'high, arg'low);
end function To_X01;
function To_X01Z (
arg : ufixed)
return ufixed is
begin
return to_ufixed (To_X01Z(to_slv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : sfixed)
return sfixed is
begin
return to_sfixed (To_X01Z(to_slv(arg)), arg'high, arg'low);
end function To_X01Z;
function To_UX01 (
arg : ufixed)
return ufixed is
begin
return to_ufixed (To_UX01(to_slv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : sfixed)
return sfixed is
begin
return to_sfixed (To_UX01(to_slv(arg)), arg'high, arg'low);
end function To_UX01;
function resize (
arg : ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : ufixed (arghigh downto arglow);
variable result : ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or_reducex(to_slv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style and
or_reducex(to_slv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return sfixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : sfixed (arghigh downto arglow);
variable result : sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style) then
reduced := or_reducex(to_slv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or_reducex(to_slv(invec(arghigh-1 downto
left_index)));
if overflow_style and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and_reducex(to_slv(invec(arghigh-1 downto
left_index)));
if overflow_style and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => to_stdlogicvector(arg),
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => to_stdlogicvector(arg),
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : ufixed; -- input
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : sfixed; -- input
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded functions
function "+" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l +
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "+";
function "+" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
+ r);
end function "+";
function "+" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l +
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "+";
function "+" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
+ r);
end function "+";
-- Overloaded functions
function "-" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l -
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "-";
function "-" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
- r);
end function "-";
function "-" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l -
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "-";
function "-" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
- r);
end function "-";
-- Overloaded functions
function "*" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l *
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "*";
function "*" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
* r);
end function "*";
function "*" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l *
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "*";
function "*" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
* r);
end function "*";
-- Overloaded functions
function "/" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l /
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/";
function "/" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/ r);
end function "/";
function "/" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l /
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/";
function "/" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/ r);
end function "/";
-- Overloaded functions
function "rem" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l rem
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "rem";
function "rem" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
rem r);
end function "rem";
function "rem" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l rem
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "rem";
function "rem" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
rem r);
end function "rem";
function "mod" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l mod
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "mod";
function "mod" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
mod r);
end function "mod";
function "mod" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l mod
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "mod";
function "mod" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
mod r);
end function "mod";
-- Overloaded functions for integers
function "+" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l + to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)); -- rounding not needed
end function "+";
function "+" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
+ r);
end function "+";
function "+" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l + to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "+";
function "+" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
+ r);
end function "+";
-- Overloaded functions
function "-" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l - to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "-";
function "-" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
- r);
end function "-";
function "-" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l - to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "-";
function "-" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
- r);
end function "-";
-- Overloaded functions
function "*" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l * to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "*";
function "*" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
* r);
end function "*";
function "*" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l * to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "*";
function "*" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
* r);
end function "*";
-- Overloaded functions
function "/" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l / to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/";
function "/" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/ r);
end function "/";
function "/" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l / to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/";
function "/" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/ r);
end function "/";
-- Overloaded functions
function "rem" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l rem to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "rem";
function "rem" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
rem r);
end function "rem";
function "rem" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l rem to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "rem";
function "rem" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
rem r);
end function "rem";
function "mod" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l mod to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "mod";
function "mod" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
mod r);
end function "mod";
function "mod" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l mod to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "mod";
function "mod" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
mod r);
end function "mod";
-- overloaded compare functions
function "=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "=";
function "/=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/=";
function ">=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">=";
function "<=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<=";
function ">" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">";
function "<" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<";
function "=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
= r);
end function "=";
function "/=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/= r);
end function "/=";
function ">=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
>= r);
end function ">=";
function "<=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
<= r);
end function "<=";
function ">" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
> r);
end function ">";
function "<" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
< r);
end function "<";
function "=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l =
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "=";
function "/=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l /=
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/=";
function ">=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >=
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">=";
function "<=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <=
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<=";
function ">" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">";
function "<" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<";
function "=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
= r);
end function "=";
function "/=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/= r);
end function "/=";
function ">=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
>= r);
end function ">=";
function "<=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
<= r);
end function "<=";
function ">" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
> r);
end function ">";
function "<" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
< r);
end function "<";
function "=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l = to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "=";
function "/=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l /= to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/=";
function ">=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l >= to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">=";
function "<=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l <= to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<=";
function ">" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l > to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">";
function "<" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l < to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<";
function "=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
= r);
end function "=";
function "/=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/= r);
end function "/=";
function ">=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
>= r);
end function ">=";
function "<=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
<= r);
end function "<=";
function ">" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
> r);
end function ">";
function "<" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
< r);
end function "<";
function "=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l =
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "=";
function "/=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l /=
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/=";
function ">=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >=
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">=";
function "<=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <=
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<=";
function ">" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">";
function "<" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<";
function "=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
= r);
end function "=";
function "/=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/= r);
end function "/=";
function ">=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
>= r);
end function ">=";
function "<=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
<= r);
end function "<=";
function ">" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
> r);
end function ">";
function "<" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
< r);
end function "<";
-- rtl_synthesis off
-- synthesis translate_off
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
write(l, s, justified, field);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
write(l, s, justified, field);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable s : STRING(1 to value'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Error: end of string encountered"
severity error;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
assert i = value'low
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Warning: Value truncated " severity warning;
return;
elsif c = '.' then -- separator, ignore
assert (i = -1)
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Warning: Decimal point does not match number format "
severity warning;
elsif (char_to_MVL9plus(c) = error) then
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
good := true;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
good := false;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done
good := false;
return;
elsif c = '.' then -- separator, ignore
good := (i = -1);
elsif (char_to_MVL9plus(c) = error) then
good := false;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out sfixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Error end of string encountered"
severity error;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
assert i = value'low
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Warning: Value truncated " severity warning;
return;
elsif c = '.' then -- separator, ignore
assert (i = -1)
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Warning: Decimal point does not match number format "
severity warning;
elsif (char_to_MVL9plus(c) = error) then
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
good := true;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
good := false;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done
good := false;
return;
elsif c = '.' then -- separator, ignore
good := (i = -1);
elsif (char_to_MVL9plus(c) = error) then
good := false;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"FIXED_GENERIC_PKG.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD(L : inout LINE;
VALUE : out ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(ufixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2triBits(c, nybble, igood, true);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(ufixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.OREAD(ufixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2TriBits(c, nybble, igood, true);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')
report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2triBits(c, nybble, igood, false);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2TriBits(c, nybble, igood, false);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0');
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(sfixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2triBits(c, nybble, igood, true);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(sfixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.OREAD(sfixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2TriBits(c, nybble, igood, true);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))
report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2triBits(c, nybble, igood, false);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2TriBits(c, nybble, igood, false);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end if;
end loop;
good := igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'));
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"FIXED_GENERIC_PKG.HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD(L : inout LINE;
VALUE : out ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(ufixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2QuadBits(c, nybble, igood, true);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(ufixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.HREAD(ufixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2QuadBits(c, nybble, igood, true);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')
report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2QuadBits(c, nybble, igood, false);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2QuadBits(c, nybble, igood, false);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0');
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(sfixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2QuadBits(c, nybble, igood, true);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(sfixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.HREAD(sfixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2QuadBits(c, nybble, igood, true);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))
report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2QuadBits(c, nybble, igood, false);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2QuadBits(c, nybble, igood, false);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'));
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
-----------------------------------------------------------------------------
-- %%% Remove the following 3 functions. They are a duplicate needed for
-- testing
-----------------------------------------------------------------------------
-- purpose: Justify a string to the right
function justify (
value : STRING;
justified : SIDE := right;
field : width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function to_ostring (
value : STD_LOGIC_VECTOR;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return justify(result, justified, field);
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (
value : STD_LOGIC_VECTOR;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return justify(result, justified, field);
end if;
end function to_hstring;
-- %%% End remove here
function to_string (
value : ufixed;
justified : SIDE := right;
field : width := 0
) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low), justified, field);
elsif value'low > 0 then
return to_string (resize (value, value'high, -1), justified, field);
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
return justify(s, justified, field);
end if;
end if;
end function to_string;
function to_string (
value : sfixed;
justified : SIDE := right;
field : width := 0
) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low), justified, field);
elsif value'low > 0 then
return to_string (resize (value, value'high, -1), justified, field);
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
return justify(s, justified, field);
end if;
end if;
end function to_string;
function to_ostring (
value : ufixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant lne : INTEGER := (-VALUE'low+2)/3;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_ostring (resize (value, 2, value'low), justified, field);
elsif value'low > 0 then
return to_ostring (resize (value, value'high, -3), justified, field);
else
slv := to_slv (value);
return justify(to_ostring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
justified, field);
end if;
end if;
end function to_ostring;
function to_hstring (
value : ufixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant lne : INTEGER := (-VALUE'low+3)/4;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_hstring (resize (value, 3, value'low), justified, field);
elsif value'low > 0 then
return to_hstring (resize (value, value'high, -4), justified, field);
else
slv := to_slv (value);
return justify(to_hstring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
justified, field);
end if;
end if;
end function to_hstring;
function to_ostring (
value : sfixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+2)/3;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
begin
if value'length < 1 then
return NUS;
else
pad := (others => value(value'high));
if value'high < 0 then
return to_ostring (resize (value, 2, value'low), justified, field);
elsif value'low > 0 then
return to_ostring (resize (value, value'high, -3), justified, field);
else
slv := to_slv (value);
return justify(to_ostring(pad
& slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0)
& lpad),
justified, field);
end if;
end if;
end function to_ostring;
function to_hstring (
value : sfixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+3)/4;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
pad := (others => value(value'high));
if value'high < 0 then
return to_hstring (resize (value, 3, value'low), justified, field);
elsif value'low > 0 then
return to_hstring (resize (value, value'high, -4), justified, field);
else
slv := to_slv (value);
return justify(to_hstring(pad&slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
justified, field);
end if;
end if;
end function to_hstring;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : ufixed)
return ufixed is
variable result : ufixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : ufixed)
return ufixed is
variable result : ufixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : ufixed)
return ufixed is
variable result : ufixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : sfixed)
return sfixed is
variable result : sfixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : sfixed)
return sfixed is
variable result : sfixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : sfixed)
return sfixed is
variable result : sfixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- purpose: find a dot in a string, return -1 if no dot (internal function)
function finddot (
arg : STRING)
return INTEGER is
alias xarg : STRING (arg'length downto 1) is arg; -- make it a downto
begin
for i in xarg'reverse_range loop
if (xarg(i) = '.') then
return i-1;
end if;
end loop;
return -1;
end function finddot;
-- Direct converstion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return ufixed is
variable result : ufixed (bstring'length-2 downto 0);
variable result_nodot : ufixed (bstring'length-1 downto 0);
variable bstring_nodot : STRING (1 to bstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(bstring);
if (dot = -1) then
L := new STRING'(bstring);
read (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return result_nodot;
else
j := 1;
for i in 1 to bstring'high loop
if (bstring(i) /= '.') then
bstring_nodot(j) := bstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(bstring_nodot);
read (L, result, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return to_ufixed(to_slv(result), bstring'length-dot-2, -dot);
end if;
end function from_string;
-- Direct octal and hex converstion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return ufixed is
variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0);
variable ostring_nodot : STRING (1 to ostring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(ostring);
if (dot = -1) then
L := new STRING'(ostring);
oread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_ufixed(UNSIGNED(result_nodot));
else
j := 1;
for i in 1 to ostring'high loop
if (ostring(i) /= '.') then
ostring_nodot(j) := ostring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(ostring_nodot);
oread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_ufixed(result, (ostring'length-1-dot)*3-1, -dot*3);
end if;
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return ufixed is
variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0);
variable hstring_nodot : STRING (1 to hstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(hstring);
if (dot = -1) then
L := new STRING'(hstring);
hread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return to_ufixed(UNSIGNED(result_nodot));
else
j := 1;
for i in 1 to hstring'high loop
if (hstring(i) /= '.') then
hstring_nodot(j) := hstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(hstring_nodot);
hread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return to_ufixed(result, (hstring'length-1-dot)*4-1, -dot*4);
end if;
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return sfixed is
variable result : sfixed (bstring'length-2 downto 0);
variable result_nodot : sfixed (bstring'length-1 downto 0);
variable bstring_nodot : STRING (1 to bstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(bstring);
if (dot = -1) then
L := new STRING'(bstring);
read (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return result_nodot;
else
j := 1;
for i in 1 to bstring'high loop
if (bstring(i) /= '.') then
bstring_nodot(j) := bstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(bstring_nodot);
read (L, result, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return to_sfixed(to_slv(result), bstring'length-dot-2, -dot);
end if;
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return sfixed is
variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0);
variable ostring_nodot : STRING (1 to ostring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(ostring);
if (dot = -1) then
L := new STRING'(ostring);
oread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_sfixed(SIGNED(result_nodot));
else
j := 1;
for i in 1 to ostring'high loop
if (ostring(i) /= '.') then
ostring_nodot(j) := ostring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(ostring_nodot);
oread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_sfixed(result, (ostring'length-1-dot)*3-1, -dot*3);
end if;
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return sfixed is
variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0);
variable hstring_nodot : STRING (1 to hstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(hstring);
if (dot = -1) then
L := new STRING'(hstring);
hread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return sfixed(SIGNED(result_nodot));
else
j := 1;
for i in 1 to hstring'high loop
if (hstring(i) /= '.') then
hstring_nodot(j) := hstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(hstring_nodot);
hread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return to_sfixed(result, (hstring'length-1-dot)*4-1, -dot*4);
end if;
end function from_hstring;
-- synthesis translate_on
-- rtl_synthesis on
function to_StdLogicVector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_StdLogicVector;
function to_Std_Logic_Vector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_Std_Logic_Vector;
function to_StdLogicVector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_StdLogicVector;
function to_Std_Logic_Vector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_Std_Logic_Vector;
function to_StdULogicVector (
arg : ufixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_StdULogicVector;
function to_Std_ULogic_Vector (
arg : ufixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_Std_ULogic_Vector;
function to_StdULogicVector (
arg : sfixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_StdULogicVector;
function to_Std_ULogic_Vector (
arg : sfixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_Std_ULogic_Vector;
end package body fixed_pkg;
|
------------------------------------------------------------------------------
-- "fixed_pkg" package contains functions for fixed point math.
-- Please see the documentation for the fixed point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_pkg.all;
-- Last Modified: $Date: 2006/05/09 19:21:24 $
-- RCS ID: $Id: fixed_pkg_c.vhd,v 1.1 2006/05/09 19:21:24 sandeepd Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- synthesis translate_off
use std.textio.all;
-- synthesis translate_on
package fixed_pkg is
--%%% Uncomment the Generics
-- new work.fixed_generic_pkg
-- generic map (
-- fixed_round_style => true; -- fixed_round
-- fixed_overflow_style => true; -- fixed_saturate
-- fixed_guard_bits => 3; -- number of guard bits
-- no_warning => false -- show warnings
-- );
--%%% REMOVE THE REST OF THIS FILE.
constant fixed_round_style : BOOLEAN := true; -- round
constant fixed_overflow_style : BOOLEAN := true; -- saturate
constant fixed_guard_bits : NATURAL := 3; -- number of guard bits
constant no_warning : BOOLEAN := false; -- issue warnings
-- Author David Bishop ([email protected])
-- These 5 constants are used as defaults.
-- There is a mechanism to override them in every function
constant fixed_round : BOOLEAN := true; -- Turn on rounding routine
constant fixed_truncate : BOOLEAN := false; -- Trun off rounding routine
constant fixed_saturate : BOOLEAN := true; -- Saturate large numbers
constant fixed_wrap : BOOLEAN := false; -- Wrap large numbers
constant fixedsynth_or_real : BOOLEAN; -- differed constant
-- base Unsigned fixed point type, downto direction assumed
type ufixed is array (INTEGER range <>) of STD_LOGIC;
-- base Signed fixed point type, downto direction assumed
type sfixed is array (INTEGER range <>) of STD_LOGIC;
-----------------------------------------------------------------------------
-- Fixed point type is defined as follows:
-- 0000000000
-- 4321012345
-- 4 0 -5
-- The decimal point is assumed between the "0" and "-1" index
-- Thus "0011010000" = 6.5 and would be written as 00110.10000
-- All types are assumed to be in the "downto" direction.
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
-- Modify the sign of the number, 2's complement
function "abs" (arg : sfixed) return sfixed;
function "-" (arg : sfixed)return sfixed;
-- Convert a signed fixed to an unsigned fixed
function "abs" (arg : sfixed) return ufixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(max(a,c)+1 downto min(b,d))
function "+" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(max(a,c)+1 downto min(b,d))
function "+" (l, r : sfixed) return sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(max(a,c)+1 downto min(b,d))
function "-" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(max(a,c)+1 downto min(b,d))
function "-" (l, r : sfixed) return sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : sfixed) return sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : sfixed) return sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (l, r : ufixed) return ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (l, r : sfixed) return sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (l, r : ufixed) return ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (l, r : sfixed) return sfixed;
----------------------------------------------------------------------------
-- Overload routines. In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : ufixed; r : REAL) return ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : ufixed) return ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto min(0,b))
function "+" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d))
function "+" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : ufixed; r : REAL) return ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : ufixed) return ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto min(0,b))
function "-" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d))
function "-" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : ufixed; r : REAL) return ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : ufixed) return ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : ufixed; r : REAL) return ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : ufixed) return ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : ufixed; r : REAL) return ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : ufixed) return ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto min(b,0))
function "rem" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto min(d,0))
function "rem" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : ufixed; r : REAL) return ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : ufixed) return ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto min(b,0))
function "mod" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto min(d,0))
function "mod" (l : NATURAL; r : ufixed) return ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto min(0,b))
function "+" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto min(0,d))
function "+" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto min(0,b))
function "-" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto min(0,d))
function "-" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : sfixed; r : REAL) return sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : sfixed) return sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto min(b,0))
function "rem" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto min(d,0))
function "rem" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : sfixed; r : REAL) return sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : sfixed) return sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto min(b,0))
function "mod" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto min(d,0))
function "mod" (l : INTEGER; r : sfixed) return sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : sfixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : sfixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style)
return ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : sfixed;
constant round_style : BOOLEAN := fixed_round_style)
return sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style)
return ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : sfixed;
constant overflow_style : BOOLEAN := fixed_overflow_style;
constant round_style : BOOLEAN := fixed_round_style)
return sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (max(a,c) downto min(b,d))
procedure add_carry (
L, R : in ufixed;
c_in : in STD_ULOGIC;
result : out ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (max(a,c) downto min(b,d))
procedure add_carry (
L, R : in sfixed;
c_in : in STD_ULOGIC;
result : out sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : ufixed; N : integer) return ufixed;
function scalb (y : ufixed; N : SIGNED) return ufixed;
function scalb (y : sfixed; N : integer) return sfixed;
function scalb (y : sfixed; N : SIGNED) return sfixed;
function Is_Negative (arg : sfixed) return BOOLEAN;
--===========================================================================
-- Comparison Operators
--===========================================================================
function ">" (l, r : ufixed) return BOOLEAN;
function ">" (l, r : sfixed) return BOOLEAN;
function "<" (l, r : ufixed) return BOOLEAN;
function "<" (l, r : sfixed) return BOOLEAN;
function "<=" (l, r : ufixed) return BOOLEAN;
function "<=" (l, r : sfixed) return BOOLEAN;
function ">=" (l, r : ufixed) return BOOLEAN;
function ">=" (l, r : sfixed) return BOOLEAN;
function "=" (l, r : ufixed) return BOOLEAN;
function "=" (l, r : sfixed) return BOOLEAN;
function "/=" (l, r : ufixed) return BOOLEAN;
function "/=" (l, r : sfixed) return BOOLEAN;
--%%% Uncomment the following (new syntax)
-- function "?=" (L, R : ufixed) return BOOLEAN;
-- function "?=" (L, R : sfixed) return BOOLEAN;
-- --%%% remove the following (old syntax)
function \?=\ (L, R : ufixed) return STD_ULOGIC;
function \?=\ (L, R : sfixed) return STD_ULOGIC;
-- These need to be overloaded for sfixed and ufixed
function \?/=\ (L, R : ufixed) return STD_ULOGIC;
function \?>\ (L, R : ufixed) return STD_ULOGIC;
function \?>=\ (L, R : ufixed) return STD_ULOGIC;
function \?<\ (L, R : ufixed) return STD_ULOGIC;
function \?<=\ (L, R : ufixed) return STD_ULOGIC;
function \?/=\ (L, R : sfixed) return STD_ULOGIC;
function \?>\ (L, R : sfixed) return STD_ULOGIC;
function \?>=\ (L, R : sfixed) return STD_ULOGIC;
function \?<\ (L, R : sfixed) return STD_ULOGIC;
function \?<=\ (L, R : sfixed) return STD_ULOGIC;
-- %%% Replace with the following (new syntax)
-- function "?=" (L, R : ufixed) return STD_ULOGIC;
-- function "?/=" (L, R : ufixed) return STD_ULOGIC;
-- function "?>" (L, R : ufixed) return STD_ULOGIC;
-- function "?>=" (L, R : ufixed) return STD_ULOGIC;
-- function "?<" (L, R : ufixed) return STD_ULOGIC;
-- function "?<=" (L, R : ufixed) return STD_ULOGIC;
-- function "?=" (L, R : sfixed) return STD_ULOGIC;
-- function "?/=" (L, R : sfixed) return STD_ULOGIC;
-- function "?>" (L, R : sfixed) return STD_ULOGIC;
-- function "?>=" (L, R : sfixed) return STD_ULOGIC;
-- function "?<" (L, R : sfixed) return STD_ULOGIC;
-- function "?<=" (L, R : sfixed) return STD_ULOGIC;
function std_match (L, R : ufixed) return BOOLEAN;
function std_match (L, R : sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : ufixed) return ufixed;
function minimum (l, r : ufixed) return ufixed;
function maximum (l, r : sfixed) return sfixed;
function minimum (l, r : sfixed) return sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "max(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : ufixed) return BOOLEAN;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : ufixed; r : REAL) return BOOLEAN;
function "/=" (l : ufixed; r : REAL) return BOOLEAN;
function ">=" (l : ufixed; r : REAL) return BOOLEAN;
function "<=" (l : ufixed; r : REAL) return BOOLEAN;
function ">" (l : ufixed; r : REAL) return BOOLEAN;
function "<" (l : ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : ufixed) return BOOLEAN;
function "/=" (l : REAL; r : ufixed) return BOOLEAN;
function ">=" (l : REAL; r : ufixed) return BOOLEAN;
function "<=" (l : REAL; r : ufixed) return BOOLEAN;
function ">" (l : REAL; r : ufixed) return BOOLEAN;
function "<" (l : REAL; r : ufixed) return BOOLEAN;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "max(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : sfixed) return BOOLEAN;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : sfixed; r : REAL) return BOOLEAN;
function "/=" (l : sfixed; r : REAL) return BOOLEAN;
function ">=" (l : sfixed; r : REAL) return BOOLEAN;
function "<=" (l : sfixed; r : REAL) return BOOLEAN;
function ">" (l : sfixed; r : REAL) return BOOLEAN;
function "<" (l : sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : sfixed) return BOOLEAN;
function "/=" (l : REAL; r : sfixed) return BOOLEAN;
function ">=" (l : REAL; r : sfixed) return BOOLEAN;
function "<=" (l : REAL; r : sfixed) return BOOLEAN;
function ">" (l : REAL; r : sfixed) return BOOLEAN;
function "<" (l : REAL; r : sfixed) return BOOLEAN;
--===========================================================================
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--===========================================================================
function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed;
function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed;
function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed;
function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : ufixed) return ufixed;
function "and" (L, R : ufixed) return ufixed;
function "or" (L, R : ufixed) return ufixed;
function "nand" (L, R : ufixed) return ufixed;
function "nor" (L, R : ufixed) return ufixed;
function "xor" (L, R : ufixed) return ufixed;
function "xnor" (L, R : ufixed) return ufixed;
function "not" (L : sfixed) return sfixed;
function "and" (L, R : sfixed) return sfixed;
function "or" (L, R : sfixed) return sfixed;
function "nand" (L, R : sfixed) return sfixed;
function "nor" (L, R : sfixed) return sfixed;
function "xor" (L, R : sfixed) return sfixed;
function "xnor" (L, R : sfixed) return sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "and" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "or" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "or" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "and" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "and" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "or" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "or" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed;
-- Reduction operators, same as numeric_std functions
-- %%% remove 12 functions (old syntax)
function and_reduce(arg : ufixed) return STD_ULOGIC;
function nand_reduce(arg : ufixed) return STD_ULOGIC;
function or_reduce(arg : ufixed) return STD_ULOGIC;
function nor_reduce(arg : ufixed) return STD_ULOGIC;
function xor_reduce(arg : ufixed) return STD_ULOGIC;
function xnor_reduce(arg : ufixed) return STD_ULOGIC;
function and_reduce(arg : sfixed) return STD_ULOGIC;
function nand_reduce(arg : sfixed) return STD_ULOGIC;
function or_reduce(arg : sfixed) return STD_ULOGIC;
function nor_reduce(arg : sfixed) return STD_ULOGIC;
function xor_reduce(arg : sfixed) return STD_ULOGIC;
function xnor_reduce(arg : sfixed) return STD_ULOGIC;
-- %%% Uncomment the following 12 functions (new syntax)
-- function "and" ( arg : ufixed ) RETURN std_ulogic;
-- function "nand" ( arg : ufixed ) RETURN std_ulogic;
-- function "or" ( arg : ufixed ) RETURN std_ulogic;
-- function "nor" ( arg : ufixed ) RETURN std_ulogic;
-- function "xor" ( arg : ufixed ) RETURN std_ulogic;
-- function "xnor" ( arg : ufixed ) RETURN std_ulogic;
-- function "and" ( arg : sfixed ) RETURN std_ulogic;
-- function "nand" ( arg : sfixed ) RETURN std_ulogic;
-- function "or" ( arg : sfixed ) RETURN std_ulogic;
-- function "nor" ( arg : sfixed ) RETURN std_ulogic;
-- function "xor" ( arg : sfixed ) RETURN std_ulogic;
-- function "xnor" ( arg : sfixed ) RETURN std_ulogic;
-- returns arg'low-1 if not found
function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER;
function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER;
-- returns arg'high+1 if not found
function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER;
function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER;
--===========================================================================
-- RESIZE Functions
--===========================================================================
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is true, then the result will be rounded. If the MSB
-- of the remainder is a "1" AND the LSB of the unround result is a '1' or
-- the lower bits of the remainder include a '1' then the result will be
-- increased by the smallest representable number for that type.
-- The default is "true" for round_style.
-- "overflow_style" can be "true" (saturate mode) or "false" (wrap mode).
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed;
-- "size_res" functions create the size of the output from the length
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : ufixed; -- input
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
function resize (
arg : sfixed; -- input
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
--===========================================================================
-- Conversion Functions
--===========================================================================
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding
return ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding
return ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return ufixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return ufixed;
-- Performs a casting. ufixed (arg'range) is returned
function to_ufixed (
arg : UNSIGNED) -- unsigned
return ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : ufixed; -- fixed point input
size_res : UNSIGNED; -- used for length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : ufixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return NATURAL;
-- Integer to sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed;
-- signed to sfixed
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : SIGNED) -- signed
return sfixed;
-- unsigned fixed point to signed fixed point (adds a "0" sign bit)
function add_sign (
arg : ufixed) -- unsigned fixed point
return sfixed;
-- signed fixed point to signed
function to_signed (
arg : sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED;
-- signed fixed point to signed
function to_signed (
arg : sfixed; -- fixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED;
-- signed fixed point to real
function to_real (
arg : sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : sfixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return INTEGER;
-- Because of the farily complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER;
function ufixed_low (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER;
function sfixed_high (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER;
function sfixed_low (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function saturate (
size_res : ufixed) -- only the size of this is used
return ufixed;
function saturate (
size_res : sfixed) -- only the size of this is used
return sfixed;
--===========================================================================
-- Translation Functions
--===========================================================================
-- Maps meta-logical values
function to_01 (
s : ufixed; -- fixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return ufixed;
-- maps meta-logical values
function to_01 (
s : sfixed; -- fixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return sfixed;
function Is_X (arg : ufixed) return BOOLEAN;
function Is_X (arg : sfixed) return BOOLEAN;
function to_X01 (arg : ufixed) return ufixed;
function to_X01 (arg : sfixed) return sfixed;
function to_X01Z (arg : ufixed) return ufixed;
function to_X01Z (arg : sfixed) return sfixed;
function to_UX01 (arg : ufixed) return ufixed;
function to_UX01 (arg : sfixed) return sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not cast these vectors because of their negative index.
function to_slv (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR;
-- alias to_StdLogicVector is to_slv [ufixed return STD_LOGIC_VECTOR];
-- alias to_Std_Logic_Vector is to_slv [ufixed return STD_LOGIC_VECTOR];
function to_slv (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR;
-- alias to_StdLogicVector is to_slv [sfixed return STD_LOGIC_VECTOR];
-- alias to_Std_Logic_Vector is to_slv [sfixed return STD_LOGIC_VECTOR];
function to_sulv (
arg : ufixed) -- fp vector
return STD_ULOGIC_VECTOR;
-- alias to_StdULogicVector is to_sulv [ufixed return STD_ULOGIC_VECTOR];
-- alias to_Std_ULogic_Vector is to_sulv [ufixed return STD_ULOGIC_VECTOR];
function to_sulv (
arg : sfixed) -- fp vector
return STD_ULOGIC_VECTOR;
-- alias to_StdULogicVector is to_sulv [sfixed return STD_ULOGIC_VECTOR];
-- alias to_Std_ULogic_Vector is to_sulv [sfixed return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return ufixed;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
--===========================================================================
-- string and textio Functions
--===========================================================================
-- rtl_synthesis off
-- synthesis translate_off
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out ufixed);
procedure READ(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out sfixed);
procedure READ(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, ufixed, SIDE, width];
alias bwrite is WRITE [LINE, sfixed, SIDE, width];
alias bread is READ [LINE, ufixed];
alias bread is READ [LINE, ufixed, BOOLEAN];
alias bread is READ [LINE, sfixed];
alias bread is READ [LINE, sfixed, BOOLEAN];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out ufixed);
procedure OREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out sfixed);
procedure OREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN);
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out ufixed);
procedure HREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out sfixed);
procedure HREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN);
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (
value : ufixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
alias to_bstring is to_string [ufixed, SIDE, width return STRING];
function to_ostring (
value : ufixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function to_hstring (
value : ufixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function to_string (
value : sfixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
alias to_bstring is to_string [sfixed, SIDE, width return STRING];
function to_ostring (
value : sfixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function to_hstring (
value : sfixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER return ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER return sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : ufixed)
return ufixed;
alias from_bstring is from_string [STRING, ufixed return ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : ufixed)
return ufixed;
function from_hstring (
hstring : STRING; -- hex string
size_res : ufixed)
return ufixed;
function from_string (
bstring : STRING; -- binary string
size_res : sfixed)
return sfixed;
alias from_bstring is from_string [STRING, sfixed return sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : sfixed)
return sfixed;
function from_hstring (
hstring : STRING; -- hex string
size_res : sfixed)
return sfixed;
-- Direct converstion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return ufixed;
alias from_bstring is from_string [STRING return ufixed];
-- Direct octal and hex converstion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return ufixed;
function from_hstring (
hstring : STRING) -- hex string
return ufixed;
function from_string (
bstring : STRING) -- binary string
return sfixed;
alias from_bstring is from_string [STRING return sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return sfixed;
function from_hstring (
hstring : STRING) -- hex string
return sfixed;
-- synthesis translate_on
-- rtl_synthesis on
-- This type is here for the floating point package.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round to positive
round_neginf, -- Round to negate
round_zero); -- Round towards zero
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
function to_StdLogicVector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR;
function to_Std_Logic_Vector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR;
function to_StdLogicVector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR;
function to_Std_Logic_Vector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR;
end package fixed_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_textio.all; -- %%% for testing only
package body fixed_pkg is
-- Author David Bishop ([email protected])
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : ufixed (0 downto 1) := (others => '0');
constant NASF : sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
--%%% Can be removed in vhdl-200x, will be implicit.
-- purpose: To find the largest of 2 numbers
function maximum (l, r : INTEGER)
return INTEGER is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
function minimum (l, r : INTEGER)
return INTEGER is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
-- %%% Remove the following function (duplicates of new numeric_std)
function "sra" (arg : SIGNED; count : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(arg, count);
else
return SHIFT_LEFT(arg, -count);
end if;
end function "sra";
-- %%% Replace or_reducex with "or", and_reducex with "and", and
-- %%% xor_reducex with "xor", then remove the following 3 functions
-- purpose: OR all of the bits in a vector together
-- This is a copy of the proposed "or_reduce" from 1076.3
function or_reducex (arg : STD_LOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_LOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_LOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reducex (BUS_int (BUS_int'left downto Half));
Lower := or_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reducex;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reducex (arg : STD_LOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_LOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_LOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reducex (BUS_int (BUS_int'left downto Half));
Lower := and_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reducex;
function xor_reducex (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reducex (BUS_int (BUS_int'left downto Half));
Lower := xor_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reducex;
--%%% remove the following function and table
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% end remove
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (L = INTEGER'low or R = INTEGER'low) then
return 0; -- error condition
end if;
return minimum (L, R);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (L = INTEGER'low or R = INTEGER'low) then
report "FIXED_GENERIC_PKG: Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : sfixed) -- input
return sfixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : sfixed (arg'range);
begin -- function cleanvec
assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low))
report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : ufixed) -- input
return ufixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : ufixed (arg'range);
begin -- function cleanvec
assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low))
report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type cast a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
-- variable j : INTEGER := arg'high; -- index for arg
begin -- function to_fixed
result := ufixed(arg);
-- floop : for i in result'range loop
-- result(i) := arg(j); -- res(4) := arg (4 + 3)
-- j := j - 1;
-- end loop floop;
return result;
end function to_fixed;
-- Type cast a "signed" into an "sfixed", used internally
function to_fixed (
arg : SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
-- variable j : INTEGER := arg'high; -- index for arg
begin -- function to_fixed
result := sfixed(arg);
-- floop : for i in result'range loop
-- result(i) := arg(j); -- res(4) := arg (4 + 3)
-- j := j - 1;
-- end loop floop;
return result;
end function to_fixed;
-- Type cast a "ufixed" into an "unsigned", used internally
function to_uns (
arg : ufixed) -- fp vector
return UNSIGNED is
subtype t is UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
-- floop : for i in slv'range loop
-- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3)
-- end loop floop;
return UNSIGNED(to_X01(std_logic_vector(slv)));
end function to_uns;
-- Type cast an "sfixed" into a "signed", used internally
function to_s (
arg : sfixed) -- fp vector
return SIGNED is
subtype t is SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
-- floop : for i in slv'range loop
-- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3)
-- end loop floop;
return SIGNED(to_X01(std_logic_vector(slv)));
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in ufixed;
result : out ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0) :=
(others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in sfixed;
result : out sfixed;
overflowx : out BOOLEAN) is
variable args, ress : SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or_reducex (STD_LOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : ufixed;
remainder : ufixed;
overflow_style : BOOLEAN := fixed_overflow_style)
return ufixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reducex (to_slv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : sfixed;
remainder : sfixed;
overflow_style : BOOLEAN := fixed_overflow_style)
return sfixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reducex (to_slv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- else
-- result(result'high) := arg(arg'high); -- fix sign bit in wrap
end if;
end if;
return result;
end function round_fixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- casting functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_slv (
arg : ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0);
variable slv : t;
begin
if arg'length < 1 then
return NSLV;
end if;
slv := t (arg);
return slv;
end function to_slv;
function to_slv (
arg : sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0);
variable slv : t;
begin
if arg'length < 1 then
return NSLV;
end if;
slv := t (arg);
return slv;
end function to_slv;
function to_sulv (
arg : ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
begin
return to_stdulogicvector (to_slv(arg));
end function to_sulv;
function to_sulv (
arg : sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
begin
return to_stdulogicvector (to_slv(arg));
end function to_sulv;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_UFIXED (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_SFIXED (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
begin
return to_ufixed (arg => to_stdlogicvector(arg),
left_index => left_index,
right_index => right_index);
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
begin
return to_sfixed (arg => to_stdlogicvector(arg),
left_index => left_index,
right_index => right_index);
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : sfixed) -- fixed point input
return sfixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : sfixed) -- fixed point input
return sfixed is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
function "abs" (arg : sfixed) return ufixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : sfixed(left_index+1 downto right_index);
variable result : ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := ufixed (xarg (left_index downto right_index));
return result;
end function "abs";
-- Addition
function "+" (
l, r : ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return ufixed is -- ufixed(a+c+1 downto b+d)
variable lslv : UNSIGNED (l'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (r'length+l'length-1 downto 0);
variable result : ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return sfixed is -- sfixed(a+c+1 downto b+d)
variable lslv : SIGNED (l'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (r'length+l'length-1 downto 0);
variable result : sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed is
variable result : ufixed (l'high - mine(r'low, r'low)
downto mine (l'low, l'low) - r'high -1);
variable dresult : ufixed (result'high downto result'low -guard_bits);
variable lresize : ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (l, lresize'high, lresize'low);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
round_style => round_style,
overflow_style => fixed_wrap); -- overflow impossible
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : sfixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed is
variable result : sfixed (l'high - mine(r'low, r'low)+1
downto mine (l'low, l'low) - r'high);
variable dresult : sfixed (result'high downto result'low-guard_bits);
variable lresize : sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : SIGNED (lresize'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (l, lresize'high, lresize'low);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
round_style => round_style,
overflow_style => fixed_wrap); -- overflow impossible
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed is
constant one : ufixed (0 downto 0) := "1";
begin
return divide(l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : sfixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed is
constant one : sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide(l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : ufixed) -- fixed point input
return ufixed is
begin
return remainder (l => l,
r => r,
round_style => fixed_round_style);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : sfixed) -- fixed point input
return sfixed is
begin
return remainder (l => l,
r => r,
round_style => fixed_round_style);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style)
return ufixed is
variable result : ufixed (minimum(l'high, r'high) downto mine(l'low, r'low));
variable dresult : ufixed (r'high downto r'low);
variable lresize : ufixed (maximum(l'high, r'low) downto mins(r'low, r'low));
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rslv := to_uns (cleanvec(r));
if (rslv = 0) then
report "FIXED_GENERIC_PKG.rem uFixed point Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap,
round_style => round_style);
-- result(result'high downto r'low) := dresult(result'high downto r'low);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : sfixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style)
return sfixed is
variable l_abs : ufixed (l'range);
variable r_abs : ufixed (r'range);
variable result : sfixed (minimum(r'high, l'high) downto mine(r'low, l'low));
variable neg_result : sfixed (minimum(r'high, l'high)+1 downto mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := abs(l);
r_abs := abs(r);
result := sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : ufixed) -- fixed point input
return ufixed is
begin
return modulo (l => l,
r => r,
round_style => fixed_round_style);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : sfixed) -- fixed point input
return sfixed is
begin
return modulo(l => l,
r => r,
round_style => fixed_round_style);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style)
return ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : sfixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style;
constant round_style : BOOLEAN := fixed_round_style)
return sfixed is
variable l_abs : ufixed (l'range);
variable r_abs : ufixed (r'range);
variable result : sfixed (r'high downto
mine(r'low, l'low));
variable dresult : sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := abs(l);
r_abs := abs(r);
dresult := "0" & sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in ufixed;
c_in : in STD_ULOGIC;
result : out ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
variable cx : UNSIGNED (0 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in sfixed;
c_in : in STD_ULOGIC;
result : out sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index
downto 0);
variable result_slv : SIGNED (left_index-right_index
downto 0);
variable cx : SIGNED (1 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : ufixed; N : integer) return ufixed is
variable result : ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : ufixed; N : SIGNED) return ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : sfixed; N : integer) return sfixed is
variable result : sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : sfixed; N : SIGNED) return sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'low to arg'high loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_lsb;
function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'high downto arg'low loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_msb;
function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'low to arg'high loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_lsb;
function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'high downto arg'low loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_msb;
function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_slv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) and to_slv(R);
else
report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) or to_slv(R);
else
report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nand to_slv(R);
else
report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nor to_slv(R);
else
report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xnor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_slv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) and to_slv(R);
else
report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) or to_slv(R);
else
report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nand to_slv(R);
else
report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nor to_slv(R);
else
report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xnor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operators, same as numeric_std functions
-- %%% remove 12 functions (old syntax)
function and_reduce(arg : ufixed) return STD_ULOGIC is
begin
return and_reducex (to_slv(arg));
end function and_reduce;
function nand_reduce(arg : ufixed) return STD_ULOGIC is
begin
return not and_reducex (to_slv(arg));
end function nand_reduce;
function or_reduce(arg : ufixed) return STD_ULOGIC is
begin
return or_reducex (to_slv(arg));
end function or_reduce;
function nor_reduce(arg : ufixed) return STD_ULOGIC is
begin
return not or_reducex (to_slv(arg));
end function nor_reduce;
function xor_reduce(arg : ufixed) return STD_ULOGIC is
begin
return xor_reducex (to_slv(arg));
end function xor_reduce;
function xnor_reduce(arg : ufixed) return STD_ULOGIC is
begin
return not xor_reducex (to_slv(arg));
end function xnor_reduce;
function and_reduce(arg : sfixed) return STD_ULOGIC is
begin
return and_reducex (to_slv(arg));
end function and_reduce;
function nand_reduce(arg : sfixed) return STD_ULOGIC is
begin
return not and_reducex (to_slv(arg));
end function nand_reduce;
function or_reduce(arg : sfixed) return STD_ULOGIC is
begin
return or_reducex (to_slv(arg));
end function or_reduce;
function nor_reduce(arg : sfixed) return STD_ULOGIC is
begin
return not or_reducex (to_slv(arg));
end function nor_reduce;
function xor_reduce(arg : sfixed) return STD_ULOGIC is
begin
return xor_reducex (to_slv(arg));
end function xor_reduce;
function xnor_reduce(arg : sfixed) return STD_ULOGIC is
begin
return not xor_reducex (to_slv(arg));
end function xnor_reduce;
-- %%% Uncomment the following 12 functions (new syntax)
-- function "and" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return and to_slv(arg);
-- end function "and";
-- function "nand" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return nand to_slv(arg);
-- end function "nand";;
-- function "or" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return or to_slv(arg);
-- end function "or";
-- function "nor" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return nor to_slv(arg);
-- end function "nor";
-- function "xor" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return xor to_slv(arg);
-- end function "xor";
-- function "xnor" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return xnor to_slv(arg);
-- end function "xnor";
-- function "and" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return and to_slv(arg);
-- end function "and";;
-- function "nand" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return nand to_slv(arg);
-- end function "nand";;
-- function "or" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return or to_slv(arg);
-- end function "or";
-- function "nor" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return nor to_slv(arg);
-- end function "nor";
-- function "xor" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return xor to_slv(arg);
-- end function "xor";
-- function "xnor" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return xnor to_slv(arg);
-- end function "xnor";
-- %%% Replace with the following (new syntax)
-- function "?=" (L, R : ufixed) return STD_ULOGIC is
function \?=\ (L, R : ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '1';
for i in lresize'reverse_range loop
result1 := \?=\(lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- end function "?=";
-- function "?/=" (L, R : ufixed) return STD_ULOGIC is
function \?/=\ (L, R : ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?/=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '0';
for i in lresize'reverse_range loop
result1 := \?/=\ (lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- end function "?/=";
-- function "?>" (L, R : ufixed) return STD_ULOGIC is
function \?>\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- end function "?>";
-- function "?>=" (L, R : ufixed) return STD_ULOGIC is
function \?>=\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- end function "?>=";
-- function "?<" (L, R : ufixed) return STD_ULOGIC is
function \?<\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- end function "?<";
-- function "?<=" (L, R : ufixed) return STD_ULOGIC is
function \?<=\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- end function "?<=";
-- function "?=" (L, R : sfixed) return STD_ULOGIC is
function \?=\ (L, R : sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '1';
for i in lresize'reverse_range loop
result1 := \?=\ (lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- end function "?=";
-- function "?/=" (L, R : sfixed) return STD_ULOGIC is
function \?/=\ (L, R : sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?/=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '0';
for i in lresize'reverse_range loop
result1 := \?/=\ (lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- end function "?/=";
-- function "?>" (L, R : sfixed) return STD_ULOGIC is
function \?>\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- end function "?>";
-- function "?>=" (L, R : sfixed) return STD_ULOGIC is
function \?>=\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- end function "?>=";
-- function "?<" (L, R : sfixed) return STD_ULOGIC is
function \?<\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- end function "?<";
-- function "?<=" (L, R : sfixed) return STD_ULOGIC is
function \?<=\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- end function "?<=";
-- %%% end replace
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_slv(L), to_slv(R));
else
report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_slv(L), to_slv(R));
else
report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
--%%% end remove
-- compare functions
function "=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : ufixed) return ufixed is
begin
if l > r then return l;
else return r;
end if;
end function maximum;
function maximum (l, r : sfixed) return sfixed is
begin
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (l, r : ufixed) return ufixed is
begin
if l > r then return r;
else return l;
end if;
end function minimum;
function minimum (l, r : sfixed) return sfixed is
begin
if l > r then return r;
else return l;
end if;
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return ufixed is
variable argx : INTEGER;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : ufixed (left_index downto fw) := (others => '0');
variable sresult : UNSIGNED (left_index downto 0); -- integer portion
variable bound : NATURAL; -- find the numerical bounds
begin
if (left_index < fw) then
return NAUF;
end if;
if left_index >= 0 then
if (left_index < 30) then
bound := 2**(left_index+1);
else
bound := INTEGER'high;
end if;
end if;
if (arg /= 0) then
if arg >= bound or left_index < 0 then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_UFIXED(NATURAL): vector truncated"
severity warning;
if (overflow_style = fixed_wrap) then -- wrap
if bound = 0 then
argx := 0;
else
argx := arg mod bound;
end if;
else -- saturate
return saturate (result'high, result'low);
end if;
else
argx := arg;
end if;
else
return result; -- return zero
end if;
sresult := to_unsigned (argx, sresult'high+1);
result := resize (arg => ufixed (sresult),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
variable argx : INTEGER;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : sfixed (left_index downto fw) := (others => '0');
variable sresult : SIGNED (left_index+1 downto 0); -- integer portion
variable bound : NATURAL := 0;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if left_index >= 0 then
if (left_index < 30) then
bound := 2**(left_index);
else
bound := INTEGER'high;
end if;
end if;
if (arg /= 0) then
if (arg >= bound or arg < -bound or left_index < 0) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_wrap then -- wrap
if bound = 0 then -- negative integer_range trap
argx := 0;
else -- shift off the top bits
argx := arg rem (bound*2);
end if;
else -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
else
argx := arg;
end if;
else
return result; -- return zero
end if;
sresult := to_signed (argx, sresult'length);
result := resize (arg => sfixed (sresult),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed is
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : ufixed (left_index downto fw) := (others => '0');
variable Xresult : ufixed (left_index downto fw-guard_bits) := (others => '0');
variable presult : REAL;
variable overflow_needed : BOOLEAN;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
report "FIXED_GENERIC_PKG.TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert NO_WARNING report "FIXED_GENERIC_PKG.TO_UFIXED(REAL): vector truncated"
severity warning;
overflow_needed := (overflow_style = fixed_saturate);
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed is
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : sfixed (left_index downto fw) := (others => '0');
variable Xresult : sfixed (left_index+1 downto fw-guard_bits) := (others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert NO_WARNING report "FIXED_GENERIC_PKG.TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : ufixed (left_index downto fw);
begin
if arg'length < 1 or (left_index < fw) then
return NAUF;
end if;
result := resize (arg => ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- casted version
function to_ufixed (
arg : UNSIGNED) -- unsigned
return ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NAUF;
end if;
return ufixed(xarg);
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : sfixed (left_index downto fw);
begin
if arg'length < 1 or (left_index < fw) then
return NASF;
end if;
result := resize (arg => sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- casted version
function to_sfixed (
arg : SIGNED) -- signed
return sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NASF;
end if;
return sfixed(xarg);
end function to_sfixed;
function add_sign (arg : ufixed) return sfixed is
variable result : sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function add_sign;
-- Because of the farily complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
constant sat : ufixed (left_index downto right_index) := (others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable sat : sfixed (left_index downto right_index) := (others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : ufixed) -- only the size of this is used
return ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : sfixed) -- only the size of this is used
return sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return ufixed is
variable result : ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_UFIX (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return sfixed is
variable result : sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_SFIX (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : ufixed; -- ufixed point input
size_res : UNSIGNED; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : sfixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : sfixed; -- ufixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : ufixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := cleanvec(arg);
if (Is_X(arg_int)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : sfixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := cleanvec(arg);
if (Is_X(arg_int)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := abs(arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : ufixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return NATURAL is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNSIGNED (minimum(31, left_index+1) downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : sfixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return INTEGER is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable arg_s : SIGNED (minimum(31, left_index+1) downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : ufixed; -- ufixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return ufixed is
variable result : ufixed (s'range); -- result
begin
for i in s'range loop
case s(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := XMAP;
end case;
end loop;
return result;
end function to_01;
function to_01 (
s : sfixed; -- ufixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return sfixed is
variable result : sfixed (s'range);
begin
for i in s'range loop
case s(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := XMAP;
end case;
end loop;
return result;
end function to_01;
function Is_X (
arg : ufixed)
return BOOLEAN is
variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_slv(arg);
return Is_X(argslv);
end function Is_X;
function Is_X (
arg : sfixed)
return BOOLEAN is
variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_slv(arg);
return Is_X(argslv);
end function Is_X;
function To_X01 (
arg : ufixed)
return ufixed is
begin
return to_ufixed (To_X01(to_slv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : sfixed)
return sfixed is
begin
return to_sfixed (To_X01(to_slv(arg)), arg'high, arg'low);
end function To_X01;
function To_X01Z (
arg : ufixed)
return ufixed is
begin
return to_ufixed (To_X01Z(to_slv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : sfixed)
return sfixed is
begin
return to_sfixed (To_X01Z(to_slv(arg)), arg'high, arg'low);
end function To_X01Z;
function To_UX01 (
arg : ufixed)
return ufixed is
begin
return to_ufixed (To_UX01(to_slv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : sfixed)
return sfixed is
begin
return to_sfixed (To_UX01(to_slv(arg)), arg'high, arg'low);
end function To_UX01;
function resize (
arg : ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : ufixed (arghigh downto arglow);
variable result : ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or_reducex(to_slv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style and
or_reducex(to_slv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return sfixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : sfixed (arghigh downto arglow);
variable result : sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style) then
reduced := or_reducex(to_slv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or_reducex(to_slv(invec(arghigh-1 downto
left_index)));
if overflow_style and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and_reducex(to_slv(invec(arghigh-1 downto
left_index)));
if overflow_style and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => to_stdlogicvector(arg),
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => to_stdlogicvector(arg),
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : ufixed; -- input
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : sfixed; -- input
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded functions
function "+" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l +
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "+";
function "+" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
+ r);
end function "+";
function "+" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l +
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "+";
function "+" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
+ r);
end function "+";
-- Overloaded functions
function "-" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l -
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "-";
function "-" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
- r);
end function "-";
function "-" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l -
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "-";
function "-" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
- r);
end function "-";
-- Overloaded functions
function "*" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l *
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "*";
function "*" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
* r);
end function "*";
function "*" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l *
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "*";
function "*" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
* r);
end function "*";
-- Overloaded functions
function "/" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l /
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/";
function "/" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/ r);
end function "/";
function "/" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l /
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/";
function "/" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/ r);
end function "/";
-- Overloaded functions
function "rem" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l rem
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "rem";
function "rem" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
rem r);
end function "rem";
function "rem" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l rem
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "rem";
function "rem" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
rem r);
end function "rem";
function "mod" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l mod
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "mod";
function "mod" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
mod r);
end function "mod";
function "mod" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l mod
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "mod";
function "mod" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
mod r);
end function "mod";
-- Overloaded functions for integers
function "+" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l + to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)); -- rounding not needed
end function "+";
function "+" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
+ r);
end function "+";
function "+" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l + to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "+";
function "+" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
+ r);
end function "+";
-- Overloaded functions
function "-" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l - to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "-";
function "-" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
- r);
end function "-";
function "-" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l - to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "-";
function "-" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
- r);
end function "-";
-- Overloaded functions
function "*" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l * to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "*";
function "*" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
* r);
end function "*";
function "*" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l * to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "*";
function "*" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
* r);
end function "*";
-- Overloaded functions
function "/" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l / to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/";
function "/" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/ r);
end function "/";
function "/" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l / to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/";
function "/" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/ r);
end function "/";
-- Overloaded functions
function "rem" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l rem to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "rem";
function "rem" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
rem r);
end function "rem";
function "rem" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l rem to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "rem";
function "rem" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
rem r);
end function "rem";
function "mod" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l mod to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "mod";
function "mod" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
mod r);
end function "mod";
function "mod" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l mod to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "mod";
function "mod" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
mod r);
end function "mod";
-- overloaded compare functions
function "=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "=";
function "/=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/=";
function ">=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">=";
function "<=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<=";
function ">" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">";
function "<" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<";
function "=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
= r);
end function "=";
function "/=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/= r);
end function "/=";
function ">=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
>= r);
end function ">=";
function "<=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
<= r);
end function "<=";
function ">" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
> r);
end function ">";
function "<" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
< r);
end function "<";
function "=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l =
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "=";
function "/=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l /=
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/=";
function ">=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >=
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">=";
function "<=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <=
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<=";
function ">" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">";
function "<" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<";
function "=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
= r);
end function "=";
function "/=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/= r);
end function "/=";
function ">=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
>= r);
end function ">=";
function "<=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
<= r);
end function "<=";
function ">" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
> r);
end function ">";
function "<" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
< r);
end function "<";
function "=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l = to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "=";
function "/=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l /= to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/=";
function ">=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l >= to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">=";
function "<=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l <= to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<=";
function ">" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l > to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">";
function "<" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l < to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<";
function "=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
= r);
end function "=";
function "/=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/= r);
end function "/=";
function ">=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
>= r);
end function ">=";
function "<=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
<= r);
end function "<=";
function ">" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
> r);
end function ">";
function "<" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
< r);
end function "<";
function "=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l =
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "=";
function "/=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l /=
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/=";
function ">=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >=
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">=";
function "<=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <=
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<=";
function ">" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">";
function "<" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<";
function "=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
= r);
end function "=";
function "/=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/= r);
end function "/=";
function ">=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
>= r);
end function ">=";
function "<=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
<= r);
end function "<=";
function ">" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
> r);
end function ">";
function "<" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
< r);
end function "<";
-- rtl_synthesis off
-- synthesis translate_off
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
write(l, s, justified, field);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
write(l, s, justified, field);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable s : STRING(1 to value'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Error: end of string encountered"
severity error;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
assert i = value'low
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Warning: Value truncated " severity warning;
return;
elsif c = '.' then -- separator, ignore
assert (i = -1)
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Warning: Decimal point does not match number format "
severity warning;
elsif (char_to_MVL9plus(c) = error) then
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
good := true;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
good := false;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done
good := false;
return;
elsif c = '.' then -- separator, ignore
good := (i = -1);
elsif (char_to_MVL9plus(c) = error) then
good := false;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out sfixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Error end of string encountered"
severity error;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
assert i = value'low
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Warning: Value truncated " severity warning;
return;
elsif c = '.' then -- separator, ignore
assert (i = -1)
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Warning: Decimal point does not match number format "
severity warning;
elsif (char_to_MVL9plus(c) = error) then
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
good := true;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
good := false;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done
good := false;
return;
elsif c = '.' then -- separator, ignore
good := (i = -1);
elsif (char_to_MVL9plus(c) = error) then
good := false;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"FIXED_GENERIC_PKG.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD(L : inout LINE;
VALUE : out ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(ufixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2triBits(c, nybble, igood, true);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(ufixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.OREAD(ufixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2TriBits(c, nybble, igood, true);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')
report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2triBits(c, nybble, igood, false);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2TriBits(c, nybble, igood, false);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0');
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(sfixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2triBits(c, nybble, igood, true);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(sfixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.OREAD(sfixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2TriBits(c, nybble, igood, true);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))
report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2triBits(c, nybble, igood, false);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2TriBits(c, nybble, igood, false);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end if;
end loop;
good := igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'));
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"FIXED_GENERIC_PKG.HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD(L : inout LINE;
VALUE : out ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(ufixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2QuadBits(c, nybble, igood, true);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(ufixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.HREAD(ufixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2QuadBits(c, nybble, igood, true);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')
report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2QuadBits(c, nybble, igood, false);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2QuadBits(c, nybble, igood, false);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0');
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(sfixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2QuadBits(c, nybble, igood, true);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(sfixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.HREAD(sfixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2QuadBits(c, nybble, igood, true);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))
report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2QuadBits(c, nybble, igood, false);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2QuadBits(c, nybble, igood, false);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'));
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
-----------------------------------------------------------------------------
-- %%% Remove the following 3 functions. They are a duplicate needed for
-- testing
-----------------------------------------------------------------------------
-- purpose: Justify a string to the right
function justify (
value : STRING;
justified : SIDE := right;
field : width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function to_ostring (
value : STD_LOGIC_VECTOR;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return justify(result, justified, field);
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (
value : STD_LOGIC_VECTOR;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return justify(result, justified, field);
end if;
end function to_hstring;
-- %%% End remove here
function to_string (
value : ufixed;
justified : SIDE := right;
field : width := 0
) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low), justified, field);
elsif value'low > 0 then
return to_string (resize (value, value'high, -1), justified, field);
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
return justify(s, justified, field);
end if;
end if;
end function to_string;
function to_string (
value : sfixed;
justified : SIDE := right;
field : width := 0
) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low), justified, field);
elsif value'low > 0 then
return to_string (resize (value, value'high, -1), justified, field);
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
return justify(s, justified, field);
end if;
end if;
end function to_string;
function to_ostring (
value : ufixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant lne : INTEGER := (-VALUE'low+2)/3;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_ostring (resize (value, 2, value'low), justified, field);
elsif value'low > 0 then
return to_ostring (resize (value, value'high, -3), justified, field);
else
slv := to_slv (value);
return justify(to_ostring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
justified, field);
end if;
end if;
end function to_ostring;
function to_hstring (
value : ufixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant lne : INTEGER := (-VALUE'low+3)/4;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_hstring (resize (value, 3, value'low), justified, field);
elsif value'low > 0 then
return to_hstring (resize (value, value'high, -4), justified, field);
else
slv := to_slv (value);
return justify(to_hstring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
justified, field);
end if;
end if;
end function to_hstring;
function to_ostring (
value : sfixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+2)/3;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
begin
if value'length < 1 then
return NUS;
else
pad := (others => value(value'high));
if value'high < 0 then
return to_ostring (resize (value, 2, value'low), justified, field);
elsif value'low > 0 then
return to_ostring (resize (value, value'high, -3), justified, field);
else
slv := to_slv (value);
return justify(to_ostring(pad
& slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0)
& lpad),
justified, field);
end if;
end if;
end function to_ostring;
function to_hstring (
value : sfixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+3)/4;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
pad := (others => value(value'high));
if value'high < 0 then
return to_hstring (resize (value, 3, value'low), justified, field);
elsif value'low > 0 then
return to_hstring (resize (value, value'high, -4), justified, field);
else
slv := to_slv (value);
return justify(to_hstring(pad&slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
justified, field);
end if;
end if;
end function to_hstring;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : ufixed)
return ufixed is
variable result : ufixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : ufixed)
return ufixed is
variable result : ufixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : ufixed)
return ufixed is
variable result : ufixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : sfixed)
return sfixed is
variable result : sfixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : sfixed)
return sfixed is
variable result : sfixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : sfixed)
return sfixed is
variable result : sfixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- purpose: find a dot in a string, return -1 if no dot (internal function)
function finddot (
arg : STRING)
return INTEGER is
alias xarg : STRING (arg'length downto 1) is arg; -- make it a downto
begin
for i in xarg'reverse_range loop
if (xarg(i) = '.') then
return i-1;
end if;
end loop;
return -1;
end function finddot;
-- Direct converstion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return ufixed is
variable result : ufixed (bstring'length-2 downto 0);
variable result_nodot : ufixed (bstring'length-1 downto 0);
variable bstring_nodot : STRING (1 to bstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(bstring);
if (dot = -1) then
L := new STRING'(bstring);
read (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return result_nodot;
else
j := 1;
for i in 1 to bstring'high loop
if (bstring(i) /= '.') then
bstring_nodot(j) := bstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(bstring_nodot);
read (L, result, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return to_ufixed(to_slv(result), bstring'length-dot-2, -dot);
end if;
end function from_string;
-- Direct octal and hex converstion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return ufixed is
variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0);
variable ostring_nodot : STRING (1 to ostring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(ostring);
if (dot = -1) then
L := new STRING'(ostring);
oread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_ufixed(UNSIGNED(result_nodot));
else
j := 1;
for i in 1 to ostring'high loop
if (ostring(i) /= '.') then
ostring_nodot(j) := ostring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(ostring_nodot);
oread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_ufixed(result, (ostring'length-1-dot)*3-1, -dot*3);
end if;
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return ufixed is
variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0);
variable hstring_nodot : STRING (1 to hstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(hstring);
if (dot = -1) then
L := new STRING'(hstring);
hread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return to_ufixed(UNSIGNED(result_nodot));
else
j := 1;
for i in 1 to hstring'high loop
if (hstring(i) /= '.') then
hstring_nodot(j) := hstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(hstring_nodot);
hread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return to_ufixed(result, (hstring'length-1-dot)*4-1, -dot*4);
end if;
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return sfixed is
variable result : sfixed (bstring'length-2 downto 0);
variable result_nodot : sfixed (bstring'length-1 downto 0);
variable bstring_nodot : STRING (1 to bstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(bstring);
if (dot = -1) then
L := new STRING'(bstring);
read (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return result_nodot;
else
j := 1;
for i in 1 to bstring'high loop
if (bstring(i) /= '.') then
bstring_nodot(j) := bstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(bstring_nodot);
read (L, result, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return to_sfixed(to_slv(result), bstring'length-dot-2, -dot);
end if;
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return sfixed is
variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0);
variable ostring_nodot : STRING (1 to ostring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(ostring);
if (dot = -1) then
L := new STRING'(ostring);
oread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_sfixed(SIGNED(result_nodot));
else
j := 1;
for i in 1 to ostring'high loop
if (ostring(i) /= '.') then
ostring_nodot(j) := ostring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(ostring_nodot);
oread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_sfixed(result, (ostring'length-1-dot)*3-1, -dot*3);
end if;
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return sfixed is
variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0);
variable hstring_nodot : STRING (1 to hstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(hstring);
if (dot = -1) then
L := new STRING'(hstring);
hread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return sfixed(SIGNED(result_nodot));
else
j := 1;
for i in 1 to hstring'high loop
if (hstring(i) /= '.') then
hstring_nodot(j) := hstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(hstring_nodot);
hread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return to_sfixed(result, (hstring'length-1-dot)*4-1, -dot*4);
end if;
end function from_hstring;
-- synthesis translate_on
-- rtl_synthesis on
function to_StdLogicVector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_StdLogicVector;
function to_Std_Logic_Vector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_Std_Logic_Vector;
function to_StdLogicVector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_StdLogicVector;
function to_Std_Logic_Vector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_Std_Logic_Vector;
function to_StdULogicVector (
arg : ufixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_StdULogicVector;
function to_Std_ULogic_Vector (
arg : ufixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_Std_ULogic_Vector;
function to_StdULogicVector (
arg : sfixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_StdULogicVector;
function to_Std_ULogic_Vector (
arg : sfixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_Std_ULogic_Vector;
end package body fixed_pkg;
|
package p1 is
constant c1 : integer := 1;
end package;
package p2 is
constant c2 : integer := 2;
end package;
package p3 is
constant c3 : integer := 3;
end package;
package p4 is
constant c4 : integer := 4;
end package;
package p5 is
constant c5 : integer := 5;
end package;
package p6 is
constant c6 : integer := 6;
end package;
entity issue225 is
use work.p1.all;
end entity issue225;
architecture test of issue225 is
use work.p2.all; -- doesn't work
begin
g1: if true generate
use work.p3.all; -- doesn't work
begin
b1: block
use work.p4.all; -- doesn't work
begin
pp1: process
use work.p5.all; -- doesn't work
procedure doit is
use work.p6.all; -- doesn't work
variable x : integer;
begin
x := c1 + c2 + c3 + c4 + c5 + c6;
wait;
end procedure doit;
begin
doit;
end process pp1;
end block b1;
end generate g1;
end architecture test;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Author: Richard Pender, Pender Electronic Design
-- Description: Clock generators for Virtex and Virtex-2 fpgas
------------------------------------------------------------------------------
------------------------------------------------------------------
-- Virtex5 clock generator ---------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use unisim.BUFG;
use unisim.DCM;
--use unisim.BUFGDLL;
use unisim.BUFGMUX;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex5 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end;
architecture struct of clkgen_virtex5 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
-- component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
--constant CLKIN_PERIOD_ST : string := "20.0";
constant FREQ_MHZ : integer := freq/1000;
--attribute CLKIN_PERIOD : string;
--attribute CLKIN_PERIOD of dll0: label is CLKIN_PERIOD_ST;
signal gnd, clk_i, clk_j, clk_k, clk_l, clk_m, lsdclk : std_logic;
signal clk_x, clk_n, clk_o, clk_p, clk_i2, clk_sd, clk_r: std_logic;
signal dll0rst, dll0lock, dll1lock, dll2xlock : std_logic;
signal dll1rst, dll2xrst : std_logic_vector(0 to 3);
signal clk0B, clkint, pciclkint : std_logic;
begin
gnd <= '0';
clk <= clk_i when (CLK2XEN = 0) else clk_p;
clkn <= clk_m; clk2x <= clk_i2;
c0 : if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate;
c2 : if PCIEN /= 0 generate
pciclkint <= pciclkin;
p3 : if PCISYSCLK = 1 generate clkint <= pciclkint; end generate;
p0 : if PCIDLL = 1 generate
-- x1 : BUFGDLL port map (I => pciclkint, O => pciclk);
--pragma translate_off
assert false report "PCIDLL = 1 currently not supported for virtex5_clkgen"
severity failure;
--pragma translate_on
end generate;
p1 : if PCIDLL = 0 generate
x1 : BUFG port map (I => pciclkint, O => pciclk);
end generate;
end generate;
c3 : if PCIEN = 0 generate
pciclk <= '0';
end generate;
clk1xu <= clk_k;
clk2xu <= clk_x;
bufg0 : BUFG port map (I => clk0B, O => clk_i);
bufg1 : BUFG port map (I => clk_j, O => clk_k);
bufg2 : BUFG port map (I => clk_l, O => clk_m);
buf34gen : if (CLK2XEN /= 0) generate
cs0 : if (clksel = 0) generate
bufg3 : BUFG port map (I => clk_n, O => clk_i2);
end generate;
cs1 : if (clksel /= 0) generate
bufg3 : BUFGMUX port map (S => cgi.clksel(0), I0 => clk_o, I1 => clk_n, O => clk_i2);
end generate;
bufg4 : BUFG port map (I => clk_o, O => clk_p);
end generate;
dll0rst <= not cgi.pllrst;
-- HMODE_dll0 : if (((FREQ_MHZ*clk_mul)/clk_div >= 140) or (FREQ_MHZ >= 120)) generate
-- dll0 : DCM
-- generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
-- DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
-- port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
-- CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
-- end generate;
-- LMODE_dll0 : if not (((FREQ_MHZ*clk_mul)/clk_div >= 140) or (FREQ_MHZ >= 120)) generate
dll0 : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clkint, CLKFB => clk_k, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => clk_j,
CLKFX => clk0B, CLK2X => clk_x, CLKFX180 => clk_l, LOCKED => dll0lock);
-- end generate;
clk2xgen : if (CLK2XEN /= 0) generate
-- HMODE_dll2x : if ((FREQ_MHZ*clk_mul)/clk_div >= 120) generate
-- dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
-- DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
-- port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
-- CLK2X => clk_n, LOCKED => dll2xlock);
-- end generate;
-- LMODE_dll2x : if not ((FREQ_MHZ*clk_mul)/clk_div >= 120) generate
dll2x : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk_i, CLKFB => clk_p, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2xrst(0), CLK0 => clk_o,
CLK2X => clk_n, LOCKED => dll2xlock);
-- end generate;
rstdel2x : process (clk_i, dll0lock)
begin
if dll0lock = '0' then dll2xrst <= (others => '1');
elsif rising_edge(clk_i) then
dll2xrst <= dll2xrst(1 to 3) & '0';
end if;
end process;
end generate;
clk_sd1 : if (CLK2XEN = 0) generate
clk_i2 <= clk_x;
dll2xlock <= dll0lock;
clk_sd <= clk_i;
end generate;
clk_sd2 : if (CLK2XEN = 1) generate clk_sd <= clk_p; end generate;
clk_sd3 : if (CLK2XEN = 2) generate clk_sd <= clk_i2; end generate;
sd0 : if (SDRAMEN /= 0) and (NOCLKFB=0) generate
cgo.clklock <= dll1lock;
-- HMODE_dll1 : if ((FREQ_MHZ*clk_mul)/clk_div >= (120-60*(CLK2XEN/2))) generate
-- dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
-- DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH",
-- DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
-- port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => lsdclk, --CLK2X => clk2x,
-- LOCKED => dll1lock);
-- end generate;
-- LMODE_dll1 : if not ((FREQ_MHZ*clk_mul)/clk_div >= (120-60*(CLK2XEN/2))) generate
dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW",
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => clk_sd, CLKFB => cgi.pllref, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll1rst(0), CLK0 => lsdclk, --CLK2X => clk2x,
LOCKED => dll1lock);
-- end generate;
bufgx : BUFG port map (I => lsdclk, O => sdclk);
rstdel : process (clk_sd, dll2xlock)
begin
if dll2xlock = '0' then dll1rst <= (others => '1');
elsif rising_edge(clk_sd) then
dll1rst <= dll1rst(1 to 3) & '0';
end if;
end process;
end generate;
sd1 : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN /= 2) generate
sdclk <= clk_i;
cgo.clklock <= dll0lock when (CLK2XEN = 0) else dll2xlock;
end generate;
sd1_2x : if ((SDRAMEN = 0) or (NOCLKFB = 1)) and (CLK2XEN = 2) generate
sdclk <= clk_i2;
cgo.clklock <= dll2xlock;
end generate;
cgo.pcilock <= '1';
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex5" & ": virtex-5 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex5" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
------------------------------------------------------------------
-- Virtex7 clock generator ---------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
library unisim;
use UNISIM.vcomponents.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_virtex7 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
freq : integer := 200000 -- clock frequency in KHz
);
port (
clkin : in std_ulogic;
clk : out std_ulogic; -- main clock
clk90 : out std_ulogic; -- main clock 90deg
clkio : out std_ulogic; -- IO ref clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type
);
end;
architecture struct of clkgen_virtex7 is
component BUFG port (O : out std_logic; I : in std_logic); end component;
----- component PLLE2_ADV -----
component PLLE2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.0;
CLKIN1_PERIOD : real := 0.0;
CLKIN2_PERIOD : real := 0.0;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
constant VERSION : integer := 1;
constant period : real := 1000000.0/real(freq);
constant clkio_div : integer := freq*clk_mul/200000;
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal int_rst : std_logic;
signal clk_nobuf : std_logic;
signal clk90_nobuf : std_logic;
signal clkio_nobuf : std_logic;
begin
CLKFBIN <= CLKFBOUT;
int_rst <= not cgi.pllrst;
PLLE2_ADV_inst : PLLE2_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => clk_mul, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => period,
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => clk_div,
CLKOUT1_DIVIDE => clk_div,
CLKOUT2_DIVIDE => clkio_div,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => clk_nobuf,
CLKOUT1 => clk90_nobuf,
CLKOUT2 => clkio_nobuf,
CLKOUT3 => OPEN,
CLKOUT4 => OPEN,
CLKOUT5 => OPEN,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => OPEN,
DRDY => OPEN,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => cgo.clklock,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => clkin,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => int_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
cgo.pcilock <= '0';
bufgclk0 : BUFG port map (I => clk_nobuf, O => clk);
bufgclk90 : BUFG port map (I => clk90_nobuf, O => clk90);
bufgclkio : BUFG port map (I => clkio_nobuf, O => clkio);
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_virtex7" & ": virtex-7 sdram/pci clock generator, version " & tost(VERSION),
"clkgen_virtex7" & ": Frequency " & tost(freq) & " KHz, DCM divisor " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkand_unisim is
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkand_unisim is
component BUFGCE
port(
O : out STD_ULOGIC;
CE: in STD_ULOGIC;
I : in STD_ULOGIC
);
end component;
begin
buf : bufgce port map(I => i, CE => en, O => o);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkmux_unisim is
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkmux_unisim is
component bufgmux is
port(
i0, i1 : in std_ulogic;
s : in std_ulogic;
o : out std_ulogic);
end component;
signal sel0, sel1, cg0, cg1 : std_ulogic;
begin
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
end architecture;
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