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-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:55:15 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_0_0/system_vga_gaussian_blur_0_0_stub.vhdl
-- Design : system_vga_gaussian_blur_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_gaussian_blur_0_0 is
Port (
clk_25 : in STD_LOGIC;
hsync_in : in STD_LOGIC;
vsync_in : in STD_LOGIC;
rgb_in : in STD_LOGIC_VECTOR ( 23 downto 0 );
hsync_out : out STD_LOGIC;
vsync_out : out STD_LOGIC;
rgb_blur : out STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_pass : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_vga_gaussian_blur_0_0;
architecture stub of system_vga_gaussian_blur_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_25,hsync_in,vsync_in,rgb_in[23:0],hsync_out,vsync_out,rgb_blur[23:0],rgb_pass[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_gaussian_blur,Vivado 2016.4";
begin
end;
|
library ieee;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
--use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use work.math_real.all;
library lpm;
use lpm.lpm_components.all;
entity test_module is
Generic( WIDTH_IN : integer := 8
);
Port( N : in integer; --Number
Exp : in real; --Exponent
M : in unsigned(WIDTH_IN-1 downto 0); --Modulus
--latch_in: in std_logic;
clk : in std_logic;
reset : in std_logic;
C : out unsigned(WIDTH_IN-1 downto 0)
);
end entity;
architecture structural of test_module is
signal result : real;
signal result2 : unsigned(WIDTH_IN*WIDTH_IN-1 downto 0);
begin
--divide: LPM_DIVIDE
-- generic map(
-- LPM_WIDTHN => 2*WIDTH_IN,
-- LPM_WIDTHD => WIDTH_IN
-- );
-- port map(
-- numer => ,
-- denom => ,
-- remain =>
-- );
--
--
-- mult : LPM_MULT
-- generic(LPM_WIDTHA : WIDTH_IN;
-- LPM_WIDTHB : WIDTH_IN;
-- LPM_WIDTHS : natural := 1;
-- LPM_WIDTHP : 2*WIDTH_IN;
-- LPM_REPRESENTATION : string := "UNSIGNED";
-- LPM_TYPE: string := L_MULT;
-- LPM_HINT : string := "UNUSED"
-- );
-- port(DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
-- DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
-- ACLR : in std_logic := '0';
-- CLOCK : in std_logic := '0';
-- CLKEN : in std_logic := '1';
-- SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0');
-- RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0)
--);
--
result <= N**Exp;
result2 <= to_unsigned(integer(result), WIDTH_IN*WIDTH_IN);
C <= result2 mod M;
end architecture; |
-- jtagtestrw.vhd
-- Generated using ACDS version 16.1 200
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity jtagtestrw is
port (
tdi : out std_logic; -- jtag.tdi
tdo : in std_logic := '0'; -- .tdo
ir_in : out std_logic_vector(2 downto 0); -- .ir_in
ir_out : in std_logic_vector(2 downto 0) := (others => '0'); -- .ir_out
virtual_state_cdr : out std_logic; -- .virtual_state_cdr
virtual_state_sdr : out std_logic; -- .virtual_state_sdr
virtual_state_e1dr : out std_logic; -- .virtual_state_e1dr
virtual_state_pdr : out std_logic; -- .virtual_state_pdr
virtual_state_e2dr : out std_logic; -- .virtual_state_e2dr
virtual_state_udr : out std_logic; -- .virtual_state_udr
virtual_state_cir : out std_logic; -- .virtual_state_cir
virtual_state_uir : out std_logic; -- .virtual_state_uir
tck : out std_logic -- tck.clk
);
end entity jtagtestrw;
architecture rtl of jtagtestrw is
component sld_virtual_jtag is
generic (
sld_auto_instance_index : string := "YES";
sld_instance_index : integer := 0;
sld_ir_width : integer := 1
);
port (
tdi : out std_logic; -- tdi
tdo : in std_logic := 'X'; -- tdo
ir_in : out std_logic_vector(2 downto 0); -- ir_in
ir_out : in std_logic_vector(2 downto 0) := (others => 'X'); -- ir_out
virtual_state_cdr : out std_logic; -- virtual_state_cdr
virtual_state_sdr : out std_logic; -- virtual_state_sdr
virtual_state_e1dr : out std_logic; -- virtual_state_e1dr
virtual_state_pdr : out std_logic; -- virtual_state_pdr
virtual_state_e2dr : out std_logic; -- virtual_state_e2dr
virtual_state_udr : out std_logic; -- virtual_state_udr
virtual_state_cir : out std_logic; -- virtual_state_cir
virtual_state_uir : out std_logic; -- virtual_state_uir
tck : out std_logic -- clk
);
end component sld_virtual_jtag;
begin
virtual_jtag_0 : component sld_virtual_jtag
generic map (
sld_auto_instance_index => "NO",
sld_instance_index => 0,
sld_ir_width => 3
)
port map (
tdi => tdi, -- jtag.tdi
tdo => tdo, -- .tdo
ir_in => ir_in, -- .ir_in
ir_out => ir_out, -- .ir_out
virtual_state_cdr => virtual_state_cdr, -- .virtual_state_cdr
virtual_state_sdr => virtual_state_sdr, -- .virtual_state_sdr
virtual_state_e1dr => virtual_state_e1dr, -- .virtual_state_e1dr
virtual_state_pdr => virtual_state_pdr, -- .virtual_state_pdr
virtual_state_e2dr => virtual_state_e2dr, -- .virtual_state_e2dr
virtual_state_udr => virtual_state_udr, -- .virtual_state_udr
virtual_state_cir => virtual_state_cir, -- .virtual_state_cir
virtual_state_uir => virtual_state_uir, -- .virtual_state_uir
tck => tck -- tck.clk
);
end architecture rtl; -- of jtagtestrw
|
-- jtagtestrw.vhd
-- Generated using ACDS version 16.1 200
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity jtagtestrw is
port (
tdi : out std_logic; -- jtag.tdi
tdo : in std_logic := '0'; -- .tdo
ir_in : out std_logic_vector(2 downto 0); -- .ir_in
ir_out : in std_logic_vector(2 downto 0) := (others => '0'); -- .ir_out
virtual_state_cdr : out std_logic; -- .virtual_state_cdr
virtual_state_sdr : out std_logic; -- .virtual_state_sdr
virtual_state_e1dr : out std_logic; -- .virtual_state_e1dr
virtual_state_pdr : out std_logic; -- .virtual_state_pdr
virtual_state_e2dr : out std_logic; -- .virtual_state_e2dr
virtual_state_udr : out std_logic; -- .virtual_state_udr
virtual_state_cir : out std_logic; -- .virtual_state_cir
virtual_state_uir : out std_logic; -- .virtual_state_uir
tck : out std_logic -- tck.clk
);
end entity jtagtestrw;
architecture rtl of jtagtestrw is
component sld_virtual_jtag is
generic (
sld_auto_instance_index : string := "YES";
sld_instance_index : integer := 0;
sld_ir_width : integer := 1
);
port (
tdi : out std_logic; -- tdi
tdo : in std_logic := 'X'; -- tdo
ir_in : out std_logic_vector(2 downto 0); -- ir_in
ir_out : in std_logic_vector(2 downto 0) := (others => 'X'); -- ir_out
virtual_state_cdr : out std_logic; -- virtual_state_cdr
virtual_state_sdr : out std_logic; -- virtual_state_sdr
virtual_state_e1dr : out std_logic; -- virtual_state_e1dr
virtual_state_pdr : out std_logic; -- virtual_state_pdr
virtual_state_e2dr : out std_logic; -- virtual_state_e2dr
virtual_state_udr : out std_logic; -- virtual_state_udr
virtual_state_cir : out std_logic; -- virtual_state_cir
virtual_state_uir : out std_logic; -- virtual_state_uir
tck : out std_logic -- clk
);
end component sld_virtual_jtag;
begin
virtual_jtag_0 : component sld_virtual_jtag
generic map (
sld_auto_instance_index => "NO",
sld_instance_index => 0,
sld_ir_width => 3
)
port map (
tdi => tdi, -- jtag.tdi
tdo => tdo, -- .tdo
ir_in => ir_in, -- .ir_in
ir_out => ir_out, -- .ir_out
virtual_state_cdr => virtual_state_cdr, -- .virtual_state_cdr
virtual_state_sdr => virtual_state_sdr, -- .virtual_state_sdr
virtual_state_e1dr => virtual_state_e1dr, -- .virtual_state_e1dr
virtual_state_pdr => virtual_state_pdr, -- .virtual_state_pdr
virtual_state_e2dr => virtual_state_e2dr, -- .virtual_state_e2dr
virtual_state_udr => virtual_state_udr, -- .virtual_state_udr
virtual_state_cir => virtual_state_cir, -- .virtual_state_cir
virtual_state_uir => virtual_state_uir, -- .virtual_state_uir
tck => tck -- tck.clk
);
end architecture rtl; -- of jtagtestrw
|
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- This file contains a testbench for RioPcsUart.
--
-- To Do:
-- -
--
-- Author(s):
-- - Magnus Rosenius, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TestRioPcsUart.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for TestRioPcsUart.
-------------------------------------------------------------------------------
entity TestRioPcsUart is
end entity;
-------------------------------------------------------------------------------
-- Architecture for TestUart.
-------------------------------------------------------------------------------
architecture TestRioPcsUartImpl of TestRioPcsUart is
component RioFifo1 is
generic(
WIDTH : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
empty_o : out std_logic;
read_i : in std_logic;
data_o : out std_logic_vector(WIDTH-1 downto 0);
full_o : out std_logic;
write_i : in std_logic;
data_i : in std_logic_vector(WIDTH-1 downto 0));
end component;
component RioSymbolConverter is
port(
clk : in std_logic;
areset_n : in std_logic;
portInitialized_o : out std_logic;
outboundSymbolEmpty_i : in std_logic;
outboundSymbolRead_o : out std_logic;
outboundSymbol_i : in std_logic_vector(33 downto 0);
inboundSymbolFull_i : in std_logic;
inboundSymbolWrite_o : out std_logic;
inboundSymbol_o : out std_logic_vector(33 downto 0);
uartEmpty_i : in std_logic;
uartRead_o : out std_logic;
uartData_i : in std_logic_vector(7 downto 0);
uartFull_i : in std_logic;
uartWrite_o : out std_logic;
uartData_o : out std_logic_vector(7 downto 0));
end component;
signal clk : std_logic;
signal areset_n : std_logic;
signal portInitialized : std_logic;
signal outboundSymbolEmpty : std_logic;
signal outboundSymbolRead : std_logic;
signal outboundSymbolReadData : std_logic_vector(33 downto 0);
signal outboundSymbolFull : std_logic;
signal outboundSymbolWrite : std_logic;
signal outboundSymbolWriteData : std_logic_vector(33 downto 0);
signal inboundSymbolFull : std_logic;
signal inboundSymbolWrite : std_logic;
signal inboundSymbolWriteData : std_logic_vector(33 downto 0);
signal uartInboundEmpty : std_logic;
signal uartInboundRead : std_logic;
signal uartInboundReadData : std_logic_vector(7 downto 0);
signal uartInboundFull : std_logic;
signal uartInboundWrite : std_logic;
signal uartInboundWriteData : std_logic_vector(7 downto 0);
signal uartOutboundFull : std_logic;
signal uartOutboundWrite : std_logic;
signal uartOutboundWriteData : std_logic_vector(7 downto 0);
begin
-----------------------------------------------------------------------------
-- Clock generation.
-----------------------------------------------------------------------------
ClockGenerator: process
begin
clk <= '0';
wait for 20 ns;
clk <= '1';
wait for 20 ns;
end process;
-----------------------------------------------------------------------------
-- Serial protocol test driver.
-----------------------------------------------------------------------------
TestDriver: process
---------------------------------------------------------------------------
-- Procedure to read a symbol.
---------------------------------------------------------------------------
procedure ReadSymbol(
constant symbolType : in std_logic_vector(1 downto 0);
constant symbolContent : in std_logic_vector(31 downto 0) := x"00000000") is
begin
inboundSymbolFull <= '0';
wait until inboundSymbolWrite = '1' and clk'event and clk = '1';
inboundSymbolFull <= '1';
assert symbolType = inboundSymbolWriteData(33 downto 32)
report "Missmatching symbol type:expected=" &
integer'image(to_integer(unsigned(symbolType))) &
" got=" &
integer'image(to_integer(unsigned(outboundSymbolWriteData(33 downto 32))))
severity error;
if (symbolType = SYMBOL_CONTROL) then
assert symbolContent(31 downto 8) = inboundSymbolWriteData(31 downto 8)
report "Missmatching symbol content:expected=" &
integer'image(to_integer(unsigned(symbolContent(31 downto 8)))) &
" got=" &
integer'image(to_integer(unsigned(inboundSymbolWriteData(31 downto 8))))
severity error;
elsif (symbolType = SYMBOL_DATA) then
assert symbolContent(31 downto 0) = inboundSymbolWriteData(31 downto 0)
report "Missmatching symbol content:expected=" &
integer'image(to_integer(unsigned(symbolContent(31 downto 0)))) &
" got=" &
integer'image(to_integer(unsigned(inboundSymbolWriteData(31 downto 0))))
severity error;
end if;
end procedure;
---------------------------------------------------------------------------
-- Procedure to write a symbol.
---------------------------------------------------------------------------
procedure WriteSymbol(
constant symbolType : in std_logic_vector(1 downto 0);
constant symbolContent : in std_logic_vector(31 downto 0) := x"00000000") is
begin
wait until outboundSymbolFull = '0' and clk'event and clk = '1';
outboundSymbolWrite <= '1';
outboundSymbolWriteData <= symbolType & symbolContent;
wait until clk'event and clk = '1';
outboundSymbolWrite <= '0';
end procedure;
---------------------------------------------------------------------------
-- Procedure to read an octet.
---------------------------------------------------------------------------
procedure ReadOctet(
constant octet : in std_logic_vector(7 downto 0) := x"00") is
begin
uartOutboundFull <= '0';
wait until uartOutboundWrite = '1' and clk'event and clk = '1';
uartOutboundFull <= '1';
assert uartOutboundWriteData = octet
report "Missmatching octet content:expected=" &
integer'image(to_integer(unsigned(octet))) &
" got=" &
integer'image(to_integer(unsigned(uartOutboundWriteData)))
severity error;
end procedure;
---------------------------------------------------------------------------
-- Procedure to send a symbol.
---------------------------------------------------------------------------
procedure WriteOctet(
constant octet : in std_logic_vector(7 downto 0) := x"00") is
begin
wait until uartInboundFull = '0' and clk'event and clk = '1';
uartInboundWrite <= '1';
uartInboundWriteData <= octet;
wait until clk'event and clk = '1';
uartInboundWrite <= '0';
end procedure;
---------------------------------------------------------------------------
-- Process variables.
---------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Test case initialization.
---------------------------------------------------------------------------
uartOutboundFull <= '1';
uartInboundWrite <= '0';
inboundSymbolFull <= '1';
outboundSymbolWrite <= '0';
-- Generate a startup reset pulse.
areset_n <= '0';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
areset_n <= '1';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioPcsUart");
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioPcsUart-TC1");
PrintS("Description: Check initial silence time.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC1-Step1");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_IDLE);
uartOutboundFull <= '0';
for i in 0 to 4095 loop
wait until clk'event and clk = '1';
assert uartOutboundWrite = '0' report "Sending during silence time."
severity error;
end loop;
ReadOctet(x"7e");
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioPcsUart-TC2");
PrintS("Description: Check outbound symbol generation.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step1");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_IDLE);
ReadOctet(x"7e");
WriteSymbol(SYMBOL_IDLE);
ReadOctet(x"7e");
WriteSymbol(SYMBOL_IDLE);
ReadOctet(x"7e");
---------------------------------------------------------------------------
PrintS("Step 2:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step2");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_CONTROL, x"123456" & "XXXXXXXX");
ReadOctet(x"12");
ReadOctet(x"34");
ReadOctet(x"56");
ReadOctet(x"7e");
---------------------------------------------------------------------------
PrintS("Step 3:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step3");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_CONTROL, x"7d7d7d" & "XXXXXXXX");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7e");
---------------------------------------------------------------------------
PrintS("Step 4:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step4");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_CONTROL, x"7e7e7e" & "XXXXXXXX");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7e");
---------------------------------------------------------------------------
PrintS("Step 5:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step5");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_CONTROL, x"7d7f7e" & "XXXXXXXX");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7f");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7e");
---------------------------------------------------------------------------
PrintS("Step 6:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step6");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_DATA, x"12345678");
ReadOctet(x"12");
ReadOctet(x"34");
ReadOctet(x"56");
ReadOctet(x"78");
---------------------------------------------------------------------------
PrintS("Step 7:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step7");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_DATA, x"7d7d7d7d");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7d");
ReadOctet(x"5d");
---------------------------------------------------------------------------
PrintS("Step 8:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step8");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_DATA, x"7e7e7e7e");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7d");
ReadOctet(x"5e");
---------------------------------------------------------------------------
PrintS("Step 9:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step9");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_DATA, x"7d7f7e7f");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7f");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7f");
---------------------------------------------------------------------------
PrintS("Step 10:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step10");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_IDLE);
ReadOctet(x"7e");
WriteSymbol(SYMBOL_CONTROL, x"123456" & "XXXXXXXX");
ReadOctet(x"12");
ReadOctet(x"34");
ReadOctet(x"56");
ReadOctet(x"7e");
WriteSymbol(SYMBOL_DATA, x"789abcde");
ReadOctet(x"78");
ReadOctet(x"9a");
ReadOctet(x"bc");
ReadOctet(x"de");
WriteSymbol(SYMBOL_CONTROL, x"123456" & "XXXXXXXX");
ReadOctet(x"12");
ReadOctet(x"34");
ReadOctet(x"56");
ReadOctet(x"7e");
WriteSymbol(SYMBOL_DATA, x"789abcde");
ReadOctet(x"78");
ReadOctet(x"9a");
ReadOctet(x"bc");
ReadOctet(x"de");
WriteSymbol(SYMBOL_DATA, x"789abcde");
ReadOctet(x"78");
ReadOctet(x"9a");
ReadOctet(x"bc");
ReadOctet(x"de");
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioPcsUart-TC3");
PrintS("Description: Check inbound symbol generation.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step1");
---------------------------------------------------------------------------
WriteOctet(x"7e");
WriteOctet(x"7e");
ReadSymbol(SYMBOL_IDLE);
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"12");
WriteOctet(x"7e");
ReadSymbol(SYMBOL_IDLE);
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"34");
WriteOctet(x"56");
WriteOctet(x"7e");
ReadSymbol(SYMBOL_IDLE);
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"78");
WriteOctet(x"9a");
WriteOctet(x"bc");
WriteOctet(x"7e");
ReadSymbol(SYMBOL_CONTROL, x"789abc" & "XXXXXXXX");
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"7d");
WriteOctet(x"5d");
WriteOctet(x"7d");
WriteOctet(x"5d");
WriteOctet(x"7d");
WriteOctet(x"5d");
WriteOctet(x"7e");
ReadSymbol(SYMBOL_CONTROL, x"7d7d7d" & "XXXXXXXX");
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"7d");
WriteOctet(x"5e");
WriteOctet(x"7d");
WriteOctet(x"5e");
WriteOctet(x"7d");
WriteOctet(x"5e");
WriteOctet(x"7e");
ReadSymbol(SYMBOL_CONTROL, x"7e7e7e" & "XXXXXXXX");
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"f1");
WriteOctet(x"11");
WriteOctet(x"22");
WriteOctet(x"33");
ReadSymbol(SYMBOL_DATA, x"f1112233");
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"7e");
ReadSymbol(SYMBOL_IDLE);
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"7d");
WriteOctet(x"5d");
WriteOctet(x"7d");
WriteOctet(x"5d");
WriteOctet(x"7d");
WriteOctet(x"5d");
WriteOctet(x"7d");
WriteOctet(x"5d");
ReadSymbol(SYMBOL_DATA, x"7d7d7d7d");
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"7d");
WriteOctet(x"5e");
WriteOctet(x"7d");
WriteOctet(x"5e");
WriteOctet(x"7d");
WriteOctet(x"5e");
WriteOctet(x"7d");
WriteOctet(x"5e");
ReadSymbol(SYMBOL_DATA, x"7e7e7e7e");
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"44");
WriteOctet(x"55");
WriteOctet(x"66");
WriteOctet(x"77");
ReadSymbol(SYMBOL_DATA, x"44556677");
WriteOctet(x"88");
WriteOctet(x"99");
WriteOctet(x"aa");
WriteOctet(x"bb");
ReadSymbol(SYMBOL_DATA, x"8899aabb");
---------------------------------------------------------------------------
-- Test completed.
---------------------------------------------------------------------------
TestEnd;
end process;
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
OutboundSymbolFifo: RioFifo1
generic map(WIDTH=>34)
port map(
clk=>clk, areset_n=>areset_n,
empty_o=>outboundSymbolEmpty, read_i=>outboundSymbolRead, data_o=>outboundSymbolReadData,
full_o=>outboundSymbolFull, write_i=>outboundSymbolWrite, data_i=>outboundSymbolWriteData);
InboundOctetFifo: RioFifo1
generic map(WIDTH=>8)
port map(
clk=>clk, areset_n=>areset_n,
empty_o=>uartInboundEmpty, read_i=>uartInboundRead, data_o=>uartInboundReadData,
full_o=>uartInboundFull, write_i=>uartInboundWrite, data_i=>uartInboundWriteData);
TestSymbolConverter: RioSymbolConverter
port map(
clk=>clk, areset_n=>areset_n,
portInitialized_o=>portInitialized,
outboundSymbolEmpty_i=>outboundSymbolEmpty,
outboundSymbolRead_o=>outboundSymbolRead, outboundSymbol_i=>outboundSymbolReadData,
inboundSymbolFull_i=>inboundSymbolFull,
inboundSymbolWrite_o=>inboundSymbolWrite, inboundSymbol_o=>inboundSymbolWriteData,
uartEmpty_i=>uartInboundEmpty, uartRead_o=>uartInboundRead, uartData_i=>uartInboundReadData,
uartFull_i=>uartOutboundFull, uartWrite_o=>uartOutboundWrite, uartData_o=>uartOutboundWriteData);
end architecture;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_mm2s_basic_wrap;
use axi_sg_v4_1_3.axi_sg_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_sg_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0) ;
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_MM2S_ADDR_WIDTH+40)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+40)-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_sg_datamover;
architecture implementation of axi_sg_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
-- coverage off
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
-- coverage on
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
-- coverage off
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
-- coverage on
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
-- coverage off
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
-- coverage on
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
-- coverage off
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
-- coverage on
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
-- coverage off
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
-- coverage on
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
-- coverage off
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
-- coverage on
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_sg_v4_1_3.axi_sg_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
sg_ctl => sg_ctl ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_sg_v4_1_3.axi_sg_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
sg_ctl => sg_ctl ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.ROCACHE_PKG.all;
-- Instruction memory for DLX
-- Memory filled by a process which reads from a file
-- file name is "test.asm.mem"
entity ROMEM is
generic (
file_path : -- string(1 to 37) := "C://DLX//dlx-master//rocache//hex.txt";
string(1 to 87) := "/home/gandalf/Documents/Universita/Postgrad/Modules/Microelectronic/dlx/rocache/hex.txt";
ENTRIES : integer := 128;
WORD_SIZE : integer := 32;
data_delay : natural := 2
);
port (
CLK : in std_logic;
RST : in std_logic;
ADDRESS : in std_logic_vector(WORD_SIZE - 1 downto 0);
ENABLE : in std_logic;
DATA_READY : out std_logic;
DATA : out std_logic_vector(2*WORD_SIZE - 1 downto 0)
);
end ROMEM;
architecture Behavioral of ROMEM is
type RAM is array (0 to ENTRIES-1) of integer;
signal Memory : RAM;
signal valid : std_logic;
signal idout : std_logic_vector(2*WORD_SIZE-1 downto 0);
signal count: integer range 0 to (data_delay + 1);
begin
-- purpose: This process is in charge of filling the Instruction RAM with the firmware
FILL_MEM_P: process (RST,CLK,ENABLE,ADDRESS)
file mem_fp: text;
variable file_line : line;
variable index : integer := 0;
variable tmp_data_u : std_logic_vector(WORD_SIZE-1 downto 0);
begin -- process FILL_MEM_P
if (Rst = '1') then
file_open(
mem_fp,
file_path,
READ_MODE
);
while (not endfile(mem_fp)) loop
readline(mem_fp,file_line);
hread(file_line,tmp_data_u);
Memory(index) <= conv_integer(unsigned(tmp_data_u));
index := index + 1;
end loop;
file_close(mem_fp);
count <= 0;
elsif CLK'event and clk= '1' then
if (ENABLE = '1' ) then
count <= count + 1;
if (count = data_delay) then
count <= 0;
valid <= '1';
idout <=
conv_std_logic_vector(Memory(conv_integer(unsigned(ADDRESS))+1),WORD_SIZE) &
conv_std_logic_vector(Memory(conv_integer(unsigned(ADDRESS))),WORD_SIZE
);
end if;
else
count <= 0;
valid <= '0';
end if;
end if;
end process FILL_MEM_P;
DATA_READY <= valid;
DATA <= idout when valid = '1' else (others => 'Z');
end Behavioral;
|
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publication of this
-- design is not authorized without written consent from Avnet.
--
-- Please direct any questions to: [email protected]
--
-- Disclaimer:
-- Avnet, Inc. makes no warranty for the use of this code or design.
-- This code is provided "As Is". Avnet, Inc assumes no responsibility for
-- any errors, which may appear in this code, nor does it make a commitment
-- to update the information contained herein. Avnet, Inc specifically
-- disclaims any implied warranties of fitness for a particular purpose.
-- Copyright(c) 2012 Avnet, Inc.
-- All rights reserved.
--
------------------------------------------------------------------
--
-- Create Date: Apr 23, 2012
-- Design Name: FMC-IMAGEON
-- Module Name: iserdes_interface_s6.vhd
-- Project Name: FMC-IMAGEON
-- Target Devices: Spartan 6
-- Avnet Boards: FMC-IMAGEON
-- Tool versions: ISE 13.4
-- Description: Spartan 6 10:1 iSerDes Top
--
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
library work;
use work.all;
library unisim;
use unisim.vcomponents.all;
entity iserdes_interface_s6 is
port (
CLOCK : in std_logic;
RESET : in std_logic;
-- serdes clock, directly connected to bondpads
SCLKP : in std_logic;
SCLKN : in std_logic;
-- serdes data, directly connected to bondpads
SDATAP : in std_logic_vector(4 downto 0);
SDATAN : in std_logic_vector(4 downto 0);
-- control
ALIGN_START : in std_logic;
FIFO_EN : in std_logic;
TRAINING : in std_logic_vector(9 downto 0);
MANUAL_TAP : in std_logic_vector(9 downto 0);
-- status
PLL_LOCKED : out std_logic;
ALIGN_BUSY : out std_logic;
ALIGNED : out std_logic;
-- parallel data out
FIFO_RDEN : in std_logic;
FIFO_EMPTY : out std_logic;
FIFO_DATAOUT : out std_logic_vector(49 downto 0)
);
end iserdes_interface_s6;
architecture rtl of iserdes_interface_s6 is
component iserdes_datadeser_s6 is
port (
RESET : in std_logic;
CLOCK : in std_logic;
PCLK01x : in std_logic;
PCLK02x : in std_logic;
PCLK10x : in std_logic;
STROBE : in std_logic;
SDATAP : in std_logic;
SDATAN : in std_logic;
ALIGN_START : in std_logic;
FIFO_EN : in std_logic;
TRAINING : in std_logic_vector(9 downto 0);
MANUAL_TAP : in std_logic_vector(9 downto 0);
ALIGN_BUSY : out std_logic;
ALIGNED : out std_logic;
FIFO_RDEN : in std_logic;
FIFO_EMPTY : out std_logic;
FIFO_DATAOUT : out std_logic_vector(9 downto 0)
);
end component;
signal RXCLKINT : std_logic;
signal RXCLK : std_logic;
signal PLL_CLKFBOUT : std_logic;
signal PLL_CLKOUT0 : std_logic;
signal PLL_CLKOUT1 : std_logic;
signal PLL_CLKOUT2 : std_logic;
signal PLL_LOCKED_i : std_logic;
signal PCLK01x : std_logic;
signal PCLK02x : std_logic;
signal PCLK10x : std_logic;
signal BUFPLL_LOCKED : std_logic;
signal SERDES_STROBE : std_logic;
signal SERDES_RESET : std_logic;
signal ALIGN_BUSY_i : std_logic_vector(4 downto 0);
signal ALIGNED_i : std_logic_vector(4 downto 0);
signal FIFO_EMPTY_i : std_logic_vector(4 downto 0);
begin
-- Signal Assignment
PLL_LOCKED <= PLL_LOCKED_i;
SERDES_RESET <= not BUFPLL_LOCKED;
-- Electrical I/O Interface
IBUFDS_RXCLK : IBUFDS
generic map (
IOSTANDARD => "TMDS_33" ,
DIFF_TERM => FALSE
)
port map (
I => SCLKP ,
IB => SCLKN ,
O => RXCLKINT
);
BUFIO2_RXCLK : BUFIO2
generic map (
DIVIDE_BYPASS => TRUE ,
DIVIDE => 1
)
port map (
I => RXCLKINT ,
SERDESSTROBE => open ,
IOCLK => open ,
DIVCLK => RXCLK
);
-- PLL
PLL_BASE_ISERDES : PLL_BASE
generic map (
CLKIN_PERIOD => 5.0 ,
CLKFBOUT_MULT => 2 , -- DDR CLK
CLKOUT0_DIVIDE => 1 , -- 2x DDR CLK 10x CLKIN
CLKOUT1_DIVIDE => 10 , -- 5/ DDR CLK 1x CLKIN
CLKOUT2_DIVIDE => 5 , -- 2.5/ DDR CLK 2x CLKIN
COMPENSATION => "INTERNAL"
)
port map
(
CLKFBOUT => PLL_CLKFBOUT ,
CLKOUT0 => PLL_CLKOUT0 ,
CLKOUT1 => PLL_CLKOUT1 ,
CLKOUT2 => PLL_CLKOUT2 ,
CLKOUT3 => open ,
CLKOUT4 => open ,
CLKOUT5 => open ,
LOCKED => PLL_LOCKED_i ,
CLKFBIN => PLL_CLKFBOUT ,
CLKIN => RXCLK ,
RST => RESET
);
-- Clock Buffers
BUFG_PCLK01x : BUFG
port map (
I => PLL_CLKOUT1 ,
O => PCLK01x
);
BUFG_PCLK02x : BUFG
port map (
I => PLL_CLKOUT2 ,
O => PCLK02x
);
BUFPLL_PCLK10x : BUFPLL
generic map (
DIVIDE => 5
)
port map (
PLLIN => PLL_CLKOUT0 ,
GCLK => PCLK02x ,
LOCKED => PLL_LOCKED_i ,
IOCLK => PCLK10x ,
SERDESSTROBE => SERDES_STROBE ,
LOCK => BUFPLL_LOCKED
);
SERDESPATHGEN: for i in 0 to 4 generate
ISERDES_DATADESER_PATH : iserdes_datadeser_s6
port map (
RESET => SERDES_RESET ,
CLOCK => CLOCK ,
PCLK01x => PCLK01x ,
PCLK02x => PCLK02x ,
PCLK10x => PCLK10x ,
STROBE => SERDES_STROBE ,
SDATAP => SDATAP(i) ,
SDATAN => SDATAN(i) ,
ALIGN_START => ALIGN_START ,
FIFO_EN => FIFO_EN ,
TRAINING => TRAINING ,
MANUAL_TAP => MANUAL_TAP ,
ALIGN_BUSY => ALIGN_BUSY_i(i) ,
ALIGNED => ALIGNED_i(i) ,
FIFO_RDEN => FIFO_RDEN ,
FIFO_EMPTY => FIFO_EMPTY_i(i) ,
FIFO_DATAOUT => FIFO_DATAOUT(((i * 10) + 9) downto (i * 10))
);
end generate;
process (ALIGN_BUSY_i)
variable TEMP : std_logic;
begin
TEMP := '0';
for i in ALIGN_BUSY_i'low to ALIGN_BUSY_i'high loop
TEMP := TEMP or ALIGN_BUSY_i(i);
end loop;
ALIGN_BUSY <= TEMP;
end process;
process (ALIGNED_i)
variable TEMP : std_logic;
begin
TEMP := '1';
for i in ALIGNED_i'low to ALIGNED_i'high loop
TEMP := TEMP and ALIGNED_i(i);
end loop;
ALIGNED <= TEMP;
end process;
process (FIFO_EMPTY_i)
variable TEMP : std_logic;
begin
TEMP := '0';
for i in FIFO_EMPTY_i'low to FIFO_EMPTY_i'high loop
TEMP := TEMP or FIFO_EMPTY_i(i);
end loop;
FIFO_EMPTY <= TEMP;
end process;
end rtl; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dilate_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_value : out std_logic_vector(15 downto 0);
di00_reg_m00 : out std_logic_vector(7 downto 0);
di01_reg_m01 : out std_logic_vector(7 downto 0);
di02_reg_m02 : out std_logic_vector(7 downto 0);
di10_reg_m10 : out std_logic_vector(7 downto 0);
di11_reg_m11 : out std_logic_vector(7 downto 0);
di12_reg_m12 : out std_logic_vector(7 downto 0);
di20_reg_m20 : out std_logic_vector(7 downto 0);
di21_reg_m21 : out std_logic_vector(7 downto 0);
di22_reg_m22 : out std_logic_vector(7 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end dilate_slave;
architecture rtl of dilate_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
constant DI00_REG_REG_ADDR : natural := 3;
constant DI01_REG_REG_ADDR : natural := 4;
constant DI02_REG_REG_ADDR : natural := 5;
constant DI10_REG_REG_ADDR : natural := 6;
constant DI11_REG_REG_ADDR : natural := 7;
constant DI12_REG_REG_ADDR : natural := 8;
constant DI20_REG_REG_ADDR : natural := 9;
constant DI21_REG_REG_ADDR : natural := 10;
constant DI22_REG_REG_ADDR : natural := 11;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_value_reg : std_logic_vector (15 downto 0);
signal di00_reg_m00_reg : std_logic_vector (7 downto 0);
signal di01_reg_m01_reg : std_logic_vector (7 downto 0);
signal di02_reg_m02_reg : std_logic_vector (7 downto 0);
signal di10_reg_m10_reg : std_logic_vector (7 downto 0);
signal di11_reg_m11_reg : std_logic_vector (7 downto 0);
signal di12_reg_m12_reg : std_logic_vector (7 downto 0);
signal di20_reg_m20_reg : std_logic_vector (7 downto 0);
signal di21_reg_m21_reg : std_logic_vector (7 downto 0);
signal di22_reg_m22_reg : std_logic_vector (7 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_value_reg <= "0000000000000000";
di00_reg_m00_reg <= "00000000";
di01_reg_m01_reg <= "00000000";
di02_reg_m02_reg <= "00000000";
di10_reg_m10_reg <= "00000000";
di11_reg_m11_reg <= "00000000";
di12_reg_m12_reg <= "00000000";
di20_reg_m20_reg <= "00000000";
di21_reg_m21_reg <= "00000000";
di22_reg_m22_reg <= "00000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
status_reg_enable_bit_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
widthimg_reg_value_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI00_REG_REG_ADDR, 4))=>
di00_reg_m00_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI01_REG_REG_ADDR, 4))=>
di01_reg_m01_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI02_REG_REG_ADDR, 4))=>
di02_reg_m02_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI10_REG_REG_ADDR, 4))=>
di10_reg_m10_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI11_REG_REG_ADDR, 4))=>
di11_reg_m11_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI12_REG_REG_ADDR, 4))=>
di12_reg_m12_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI20_REG_REG_ADDR, 4))=>
di20_reg_m20_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI21_REG_REG_ADDR, 4))=>
di21_reg_m21_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(DI22_REG_REG_ADDR, 4))=>
di22_reg_m22_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000" & widthimg_reg_value_reg(15) & widthimg_reg_value_reg(14) & widthimg_reg_value_reg(13) & widthimg_reg_value_reg(12) & widthimg_reg_value_reg(11) & widthimg_reg_value_reg(10) & widthimg_reg_value_reg(9) & widthimg_reg_value_reg(8) & widthimg_reg_value_reg(7) & widthimg_reg_value_reg(6) & widthimg_reg_value_reg(5) & widthimg_reg_value_reg(4) & widthimg_reg_value_reg(3) & widthimg_reg_value_reg(2) & widthimg_reg_value_reg(1) & widthimg_reg_value_reg(0);
when std_logic_vector(to_unsigned(DI00_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di00_reg_m00_reg(7) & di00_reg_m00_reg(6) & di00_reg_m00_reg(5) & di00_reg_m00_reg(4) & di00_reg_m00_reg(3) & di00_reg_m00_reg(2) & di00_reg_m00_reg(1) & di00_reg_m00_reg(0);
when std_logic_vector(to_unsigned(DI01_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di01_reg_m01_reg(7) & di01_reg_m01_reg(6) & di01_reg_m01_reg(5) & di01_reg_m01_reg(4) & di01_reg_m01_reg(3) & di01_reg_m01_reg(2) & di01_reg_m01_reg(1) & di01_reg_m01_reg(0);
when std_logic_vector(to_unsigned(DI02_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di02_reg_m02_reg(7) & di02_reg_m02_reg(6) & di02_reg_m02_reg(5) & di02_reg_m02_reg(4) & di02_reg_m02_reg(3) & di02_reg_m02_reg(2) & di02_reg_m02_reg(1) & di02_reg_m02_reg(0);
when std_logic_vector(to_unsigned(DI10_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di10_reg_m10_reg(7) & di10_reg_m10_reg(6) & di10_reg_m10_reg(5) & di10_reg_m10_reg(4) & di10_reg_m10_reg(3) & di10_reg_m10_reg(2) & di10_reg_m10_reg(1) & di10_reg_m10_reg(0);
when std_logic_vector(to_unsigned(DI11_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di11_reg_m11_reg(7) & di11_reg_m11_reg(6) & di11_reg_m11_reg(5) & di11_reg_m11_reg(4) & di11_reg_m11_reg(3) & di11_reg_m11_reg(2) & di11_reg_m11_reg(1) & di11_reg_m11_reg(0);
when std_logic_vector(to_unsigned(DI12_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di12_reg_m12_reg(7) & di12_reg_m12_reg(6) & di12_reg_m12_reg(5) & di12_reg_m12_reg(4) & di12_reg_m12_reg(3) & di12_reg_m12_reg(2) & di12_reg_m12_reg(1) & di12_reg_m12_reg(0);
when std_logic_vector(to_unsigned(DI20_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di20_reg_m20_reg(7) & di20_reg_m20_reg(6) & di20_reg_m20_reg(5) & di20_reg_m20_reg(4) & di20_reg_m20_reg(3) & di20_reg_m20_reg(2) & di20_reg_m20_reg(1) & di20_reg_m20_reg(0);
when std_logic_vector(to_unsigned(DI21_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di21_reg_m21_reg(7) & di21_reg_m21_reg(6) & di21_reg_m21_reg(5) & di21_reg_m21_reg(4) & di21_reg_m21_reg(3) & di21_reg_m21_reg(2) & di21_reg_m21_reg(1) & di21_reg_m21_reg(0);
when std_logic_vector(to_unsigned(DI22_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & di22_reg_m22_reg(7) & di22_reg_m22_reg(6) & di22_reg_m22_reg(5) & di22_reg_m22_reg(4) & di22_reg_m22_reg(3) & di22_reg_m22_reg(2) & di22_reg_m22_reg(1) & di22_reg_m22_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_value <= widthimg_reg_value_reg;
di00_reg_m00 <= di00_reg_m00_reg;
di01_reg_m01 <= di01_reg_m01_reg;
di02_reg_m02 <= di02_reg_m02_reg;
di10_reg_m10 <= di10_reg_m10_reg;
di11_reg_m11 <= di11_reg_m11_reg;
di12_reg_m12 <= di12_reg_m12_reg;
di20_reg_m20 <= di20_reg_m20_reg;
di21_reg_m21 <= di21_reg_m21_reg;
di22_reg_m22 <= di22_reg_m22_reg;
end rtl;
|
architecture a of e is
alias foo is bar;
alias blah : integer is boo;
alias funci is func [integer, boolean return boolean];
alias proci is proc [integer];
alias proce is proc [];
alias funce is func [return integer];
begin
end architecture;
|
architecture a of e is
alias foo is bar;
alias blah : integer is boo;
alias funci is func [integer, boolean return boolean];
alias proci is proc [integer];
alias proce is proc [];
alias funce is func [return integer];
begin
end architecture;
|
architecture a of e is
alias foo is bar;
alias blah : integer is boo;
alias funci is func [integer, boolean return boolean];
alias proci is proc [integer];
alias proce is proc [];
alias funce is func [return integer];
begin
end architecture;
|
architecture a of e is
alias foo is bar;
alias blah : integer is boo;
alias funci is func [integer, boolean return boolean];
alias proci is proc [integer];
alias proce is proc [];
alias funce is func [return integer];
begin
end architecture;
|
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
END procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
END procedure proc_name;
function func1 return integer is begin End function func1;
begin
end architecture RTL;
|
----------------------------------------------------------------------
-- OscXtlCnt
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Blink 8 LEDs using external Xtal Clock.
-- Use External Xtal, adjust its signal to some MHz and
-- add a bunch of registers for the FlipFlip toggle counter.
-- See "brdConst_pkg.vhd" for specific BRD_OSC_CLK_MHZ values.
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
entity OscXtlCnt is
port( OSC_CLK : in std_logic;
DEVRST_N : in std_logic;
PB1 : in std_logic;
PB2 : in std_logic;
LED0 : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
LED3 : out std_logic;
LED4 : out std_logic;
LED5 : out std_logic;
LED6 : out std_logic;
LED7 : out std_logic;
UART_RXD : in std_logic;
UART_TXD : out std_logic );
end OscXtlCnt;
----------------------------------------------------------------------
architecture rtl of OscXtlCnt is
component brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end component;
component brdRstClk
port ( i_rst_n, i_clk : in std_logic;
o_rst_n, o_clk : out std_logic );
end component;
component myDffCnt
generic (N : Integer);
port ( i_rst_n, i_clk : in std_logic;
o_q : out std_logic_vector(N-1 downto 0) );
end component;
signal s_clk, s_rst_n, s_lex, s_pbx : std_logic;
signal s_cnt : std_logic_vector(28 downto 0);
signal s_led : std_logic_vector(7 downto 0);
begin
brdRstClk_0 : brdRstClk
port map(
i_rst_n => DEVRST_N,
i_clk => OSC_CLK,
o_rst_n => s_rst_n,
o_clk => s_clk );
brdLexSwx_0 : brdLexSwx
port map(
o_lex => s_lex,
o_pbx => s_pbx );
myDffCnt_0 : myDffCnt
generic map( N => s_cnt'high+1 )
port map(
i_rst_n => s_rst_n,
i_clk => s_clk,
o_q => s_cnt );
s_led <= s_cnt(s_cnt'high downto s_cnt'high-7);
LED0 <= s_led(0) xor s_lex;
LED1 <= s_led(1) xor s_lex;
LED2 <= s_led(2) xor s_lex;
LED3 <= s_led(3) xor s_lex;
LED4 <= s_led(4) xor s_lex;
LED5 <= s_led(5) xor s_lex;
LED6 <= (s_led(6) xor s_lex) xor (PB2 xor s_pbx);
LED7 <= (s_led(7) xor s_lex) xor (PB1 xor s_pbx);
UART_TXD <= UART_RXD; -- dummy
end rtl;
----------------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2774.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity AFTER is
end AFTER;
ENTITY c13s09b00x00p99n01i02774ent IS
END c13s09b00x00p99n01i02774ent;
ARCHITECTURE c13s09b00x00p99n01i02774arch OF c13s09b00x00p99n01i02774ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02774 - Reserved word AFTER can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02774arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2774.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity AFTER is
end AFTER;
ENTITY c13s09b00x00p99n01i02774ent IS
END c13s09b00x00p99n01i02774ent;
ARCHITECTURE c13s09b00x00p99n01i02774arch OF c13s09b00x00p99n01i02774ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02774 - Reserved word AFTER can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02774arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2774.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity AFTER is
end AFTER;
ENTITY c13s09b00x00p99n01i02774ent IS
END c13s09b00x00p99n01i02774ent;
ARCHITECTURE c13s09b00x00p99n01i02774arch OF c13s09b00x00p99n01i02774ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02774 - Reserved word AFTER can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02774arch;
|
--This should pass
context con1 is
end context con1;
context con2 is
end context;
--This should fail
context con3 is
end;
context con4 is
end
;
-- Split declaration across lines
context
con5
is
end
context
;
|
-- Hi Emacs, this is -*- mode: vhdl -*-
----------------------------------------------------------------------------------
-- Unidirectional PS2 Interface (device -> host)
-- For connect mouse/keyboard
--
-- The PS/2 mouse and keyboard implement a bidirectional synchronous serial
-- protocol. The bus is "idle" when both lines are high (open-collector).
-- THIS A *UNIDIRECTIONAL* INTERFACE (DEVICE -> HOST)
--
-- Javier Valcarce García, [email protected]
-- $Id$
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.utils.all;
entity interface_ps2 is
port (
reset : in std_logic;
clk : in std_logic; -- faster than kbclk
kbdata : in std_logic;
kbclk : in std_logic;
newdata : out std_logic; -- one clock cycle pulse, notify a new byte has arrived
do : out std_logic_vector(7 downto 0)
);
end interface_ps2;
-------------------------------------------------------------------------------
architecture behavioral of interface_ps2 is
signal st : std_logic;
signal sh : std_logic;
signal s1 : std_logic;
signal s2 : std_logic;
signal kbclk_fe : std_logic;
signal shift9 : std_logic_vector(8 downto 0);
signal error : std_logic;
begin
-------------------------------------------------------------------------------
-- Edge detector
-------------------------------------------------------------------------------
process (reset, clk)
begin
if reset = '1' then
s1 <= '0';
s2 <= '0';
elsif rising_edge(clk) then
s2 <= s1;
s1 <= kbclk;
end if;
end process;
kbclk_fe <= '1' when s1 = '0' and s2 = '1' else '0';
-------------------------------------------------------------------------------
-- 9-bit shift register to store received data
-- 11-bit frame, LSB first: 1 start bit, 8 data bits, 1 parity bit, 1 stop bit
-------------------------------------------------------------------------------
process (reset, clk)
begin
if reset = '1' then
shift9 <= "000000000";
elsif rising_edge(clk) then
if sh = '1' then
shift9(7 downto 0) <= shift9(8 downto 1);
shift9(8) <= kbdata;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Output register
-------------------------------------------------------------------------------
process (reset, clk)
begin
if reset = '1' then
do <= "00000000";
elsif rising_edge(clk) then
if st = '1' then
do <= shift9(7 downto 0);
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- parity error detector (XOR gate) The parity bit is at shift9(8)
-------------------------------------------------------------------------------
error <= not (shift9(0) xor shift9(1) xor shift9(2) xor shift9(3) xor shift9(4) xor
shift9(5) xor shift9(6) xor shift9(7) xor shift9(8));
-------------------------------------------------------------------------------
-- Control Unit
-------------------------------------------------------------------------------
CTL : block
type state_type is (idle, start, bit_1a, bit_1b, bit_2a, bit_2b,
bit_3a, bit_3b, bit_4a, bit_4b, bit_5a, bit_5b,
bit_6a, bit_6b, bit_7a, bit_7b, bit_8a, bit_8b,
bit_9a, bit_9b, stop, store, notify);
signal state : state_type;
signal op : std_logic_vector(2 downto 0);
begin
-- 2 procesos para separar la parte secuencial de la combinacional, de
-- esta forma las salidas no son registros ("registered outputs") y por
-- tanto no hay un ciclo de reloj de espera
process (reset, clk)
begin
if reset = '1' then
state <= idle;
elsif rising_edge(clk) then
case (state) is
when idle =>
if kbclk_fe = '1' and kbdata = '0' then
state <= start; --e0; --DEBUG
end if;
when start =>
if kbclk_fe = '1' then
state <= bit_1a;
end if;
when bit_1a => state <= bit_1b;
when bit_1b => if kbclk_fe = '1' then state <= bit_2a; end if;
when bit_2a => state <= bit_2b;
when bit_2b => if kbclk_fe = '1' then state <= bit_3a; end if;
when bit_3a => state <= bit_3b;
when bit_3b => if kbclk_fe = '1' then state <= bit_4a; end if;
when bit_4a => state <= bit_4b;
when bit_4b => if kbclk_fe = '1' then state <= bit_5a; end if;
when bit_5a => state <= bit_5b;
when bit_5b => if kbclk_fe = '1' then state <= bit_6a; end if;
when bit_6a => state <= bit_6b;
when bit_6b => if kbclk_fe = '1' then state <= bit_7a; end if;
when bit_7a => state <= bit_7b;
when bit_7b => if kbclk_fe = '1' then state <= bit_8a; end if;
when bit_8a => state <= bit_8b;
when bit_8b => if kbclk_fe = '1' then state <= bit_9a; end if;
when bit_9a => state <= bit_9b;
when bit_9b =>
if kbclk_fe = '1' then
if kbdata = '1' then
state <= stop;
else
state <= idle;
end if;
end if;
when stop =>
if error = '0' then
state <= store;
else
state <= idle;
end if;
when store => state <= notify;
when notify => state <= idle;
end case;
end if;
end process;
-- 13 uórdenes para la ruta de datos:
-- Agrupamos todas las uórdenes en el vector op para que el código quede más
-- compacto y legible
sh <= op(2);
st <= op(1);
newdata <= op(0); --out port, actually
process (state)
begin
-- La función TRIM elimina los espacios de la cadena y devuelve un tipo
-- std_logic_vector con los elementos restantes (definida en work.conf)
case state is
--SH ST NEW
when idle => op <= STRTRIM("0 0 0");
when start => op <= STRTRIM("0 0 0");
when bit_1a => op <= STRTRIM("1 0 0");
when bit_1b => op <= STRTRIM("0 0 0");
when bit_2a => op <= STRTRIM("1 0 0");
when bit_2b => op <= STRTRIM("0 0 0");
when bit_3a => op <= STRTRIM("1 0 0");
when bit_3b => op <= STRTRIM("0 0 0");
when bit_4a => op <= STRTRIM("1 0 0");
when bit_4b => op <= STRTRIM("0 0 0");
when bit_5a => op <= STRTRIM("1 0 0");
when bit_5b => op <= STRTRIM("0 0 0");
when bit_6a => op <= STRTRIM("1 0 0");
when bit_6b => op <= STRTRIM("0 0 0");
when bit_7a => op <= STRTRIM("1 0 0");
when bit_7b => op <= STRTRIM("0 0 0");
when bit_8a => op <= STRTRIM("1 0 0");
when bit_8b => op <= STRTRIM("0 0 0");
when bit_9a => op <= STRTRIM("1 0 0");
when bit_9b => op <= STRTRIM("0 0 0");
when stop => op <= STRTRIM("0 0 0");
when store => op <= STRTRIM("0 1 0");
when notify => op <= STRTRIM("0 0 1");
end case;
end process;
end block CTL;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end behavioral;
|
-------------------------------------------------------------------------------
-- Title : Synchronous FIFO
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: A very plain FIFO, synchronous interfaces.
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
package fifo_sync_pkg is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component fifo_sync
generic (
data_width : natural := 8;
address_width : natural := 4);
port (
di : in std_logic_vector(data_width -1 downto 0);
wr : in std_logic;
full : out std_logic;
do : out std_logic_vector(data_width -1 downto 0);
rd : in std_logic;
empty : out std_logic;
valid : out std_logic;
clk : in std_logic);
end component;
end fifo_sync_pkg;
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : Synchronous FIFO
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: A very plain FIFO, synchronous interfaces.
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
package fifo_sync_pkg is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component fifo_sync
generic (
data_width : natural := 8;
address_width : natural := 4);
port (
di : in std_logic_vector(data_width -1 downto 0);
wr : in std_logic;
full : out std_logic;
do : out std_logic_vector(data_width -1 downto 0);
rd : in std_logic;
empty : out std_logic;
valid : out std_logic;
clk : in std_logic);
end component;
end fifo_sync_pkg;
-------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RegA is
port(
x: in std_logic_vector(31 downto 0);
clk: in std_logic;
y: out std_logic_vector(31 downto 0)
);
end RegA;
architecture Structural of RegA is
signal temp: std_logic_vector(31 downto 0) := X"00000000";
begin
y <= temp;
process(clk)
begin
if falling_edge(clk) then
temp <= x;
end if;
end process;
end Structural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc746.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00746pkg is
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(1 to 7);
k:bit_vector(0 to 3);
end record;
type array_rec_std is array (integer range <>) of record_std_package;
function F1(inp : boolean_vector(0 to 15)) return boolean ;
function F2(inp : bit_vector(0 to 3)) return bit ;
function F3(inp : string(1 to 7)) return character ;
function F4(inp : severity_level_vector(0 to 15)) return severity_level ;
function F5(inp : integer_vector(0 to 15)) return integer ;
function F6(inp : real_vector(0 to 15)) return real ;
function F7(inp : time_vector(0 to 15)) return time ;
function F8(inp : natural_vector(0 to 15)) return natural ;
function F9(inp : positive_vector(0 to 15)) return positive ;
function F10(inp: array_rec_std(0 to 7)) return record_std_package ;
end c01s01b01x01p05n02i00746pkg;
package body c01s01b01x01p05n02i00746pkg is
function F1(inp : boolean_vector(0 to 15)) return boolean is
begin
for i in 0 to 15 loop
assert(inp(i) = true) report"wrong initialization of S1" severity error;
end loop;
return false;
end F1;
function F2(inp : bit_vector(0 to 3)) return bit is
begin
for i in 0 to 3 loop
assert(inp(i) = '0') report"wrong initialization of S2" severity error;
end loop;
return '0';
end F2;
function F3(inp : string(1 to 7)) return character is
begin
for i in 1 to 7 loop
assert(inp(i) = 's') report"wrong initialization of S3" severity error;
end loop;
return 'h';
end F3;
function F4(inp : severity_level_vector(0 to 15)) return severity_level is
begin
for i in 0 to 15 loop
assert(inp(i) = note) report"wrong initialization of S4" severity error;
end loop;
return error;
end F4;
function F5(inp : integer_vector(0 to 15)) return integer is
begin
for i in 0 to 15 loop
assert(inp(i) = 3) report"wrong initialization of S5" severity error;
end loop;
return 6;
end F5;
function F6(inp : real_vector(0 to 15)) return real is
begin
for i in 0 to 15 loop
assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
end loop;
return 6.0;
end F6;
function F7(inp : time_vector(0 to 15)) return time is
begin
for i in 0 to 15 loop
assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
end loop;
return 6 ns;
end F7;
function F8(inp : natural_vector(0 to 15)) return natural is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S8" severity error;
end loop;
return 6;
end F8;
function F9(inp : positive_vector(0 to 15)) return positive is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S9" severity error;
end loop;
return 6;
end F9;
function F10(inp : array_rec_std(0 to 7)) return record_std_package is
begin
for i in 0 to 7 loop
assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
end loop;
return (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100");
end F10;
end c01s01b01x01p05n02i00746pkg;
use work.c01s01b01x01p05n02i00746pkg.all;
ENTITY c01s01b01x01p05n02i00746ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "sssssss";
C11 : bit_vector := B"0000";
C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
);
port(
S1 : boolean_vector(zero to fifteen) := (others => C1);
S2 : severity_level_vector(zero to fifteen) := (others => C4);
S3 : integer_vector(zero to fifteen) := (others => C5);
S4 : real_vector(zero to fifteen) := (others => C6);
S5 : time_vector (zero to fifteen) := (others => C7);
S6 : natural_vector(zero to fifteen) := (others => C8);
S7 : positive_vector(zero to fifteen) := (others => C9);
S8 : string(one to seven) := C10;
S9 : bit_vector(zero to three) := C11;
S48: array_rec_std(zero to seven) := (others => C48)
);
END c01s01b01x01p05n02i00746ent;
ARCHITECTURE c01s01b01x01p05n02i00746arch OF c01s01b01x01p05n02i00746ent IS
BEGIN
TESTING: PROCESS
variable var1 : boolean;
variable var4 : severity_level;
variable var5 : integer;
variable var6 : real;
variable var7 : time;
variable var8 : natural;
variable var9 : positive;
variable var2 : bit;
variable var3 : character;
variable var48: record_std_package;
BEGIN
var1 := F1(S1);
var2 := F2(S9);
var3 := F3(S8);
var4 := F4(S2);
var5 := F5(S3);
var6 := F6(S4);
var7 := F7(S5);
var8 := F8(S6);
var9 := F9(S7);
var48 := F10(S48);
wait for 1 ns;
assert(var1 = false) report "wrong assignment in the function F1" severity error;
assert(var2 = '0') report "wrong assignment in the function F2" severity error;
assert(var3 = 'h') report "wrong assignment in the function F3" severity error;
assert(var4 = error) report "wrong assignment in the function F4" severity error;
assert(var5 = 6) report "wrong assignment in the function F5" severity error;
assert(var6 = 6.0) report "wrong assignment in the function F6" severity error;
assert(var7 = 6 ns) report "wrong assignment in the function F7" severity error;
assert(var8 = 6) report "wrong assignment in the function F8" severity error;
assert(var9 = 6) report "wrong assignment in the function F9" severity error;
assert(var48 = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")) report "wrong assignment in the function F10" severity error;
assert NOT( var1 = F1(S1) and
var2 = F2(S9) and
var3 = F3(S8) and
var4 = F4(S2) and
var5 = F5(S3) and
var6 = F6(S4) and
var7 = F7(S5) and
var8 = F8(S6) and
var9 = F9(S7) and
var48 = F10(S48) )
report "***PASSED TEST: c01s01b01x01p05n02i00746"
severity NOTE;
assert ( var1 = F1(S1) and
var2 = F2(S9) and
var3 = F3(S8) and
var4 = F4(S2) and
var5 = F5(S3) and
var6 = F6(S4) and
var7 = F7(S5) and
var8 = F8(S6) and
var9 = F9(S7) and
var48 = F10(S48) )
report "***FAILED TEST: c01s01b01x01p05n02i00746 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00746arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc746.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00746pkg is
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(1 to 7);
k:bit_vector(0 to 3);
end record;
type array_rec_std is array (integer range <>) of record_std_package;
function F1(inp : boolean_vector(0 to 15)) return boolean ;
function F2(inp : bit_vector(0 to 3)) return bit ;
function F3(inp : string(1 to 7)) return character ;
function F4(inp : severity_level_vector(0 to 15)) return severity_level ;
function F5(inp : integer_vector(0 to 15)) return integer ;
function F6(inp : real_vector(0 to 15)) return real ;
function F7(inp : time_vector(0 to 15)) return time ;
function F8(inp : natural_vector(0 to 15)) return natural ;
function F9(inp : positive_vector(0 to 15)) return positive ;
function F10(inp: array_rec_std(0 to 7)) return record_std_package ;
end c01s01b01x01p05n02i00746pkg;
package body c01s01b01x01p05n02i00746pkg is
function F1(inp : boolean_vector(0 to 15)) return boolean is
begin
for i in 0 to 15 loop
assert(inp(i) = true) report"wrong initialization of S1" severity error;
end loop;
return false;
end F1;
function F2(inp : bit_vector(0 to 3)) return bit is
begin
for i in 0 to 3 loop
assert(inp(i) = '0') report"wrong initialization of S2" severity error;
end loop;
return '0';
end F2;
function F3(inp : string(1 to 7)) return character is
begin
for i in 1 to 7 loop
assert(inp(i) = 's') report"wrong initialization of S3" severity error;
end loop;
return 'h';
end F3;
function F4(inp : severity_level_vector(0 to 15)) return severity_level is
begin
for i in 0 to 15 loop
assert(inp(i) = note) report"wrong initialization of S4" severity error;
end loop;
return error;
end F4;
function F5(inp : integer_vector(0 to 15)) return integer is
begin
for i in 0 to 15 loop
assert(inp(i) = 3) report"wrong initialization of S5" severity error;
end loop;
return 6;
end F5;
function F6(inp : real_vector(0 to 15)) return real is
begin
for i in 0 to 15 loop
assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
end loop;
return 6.0;
end F6;
function F7(inp : time_vector(0 to 15)) return time is
begin
for i in 0 to 15 loop
assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
end loop;
return 6 ns;
end F7;
function F8(inp : natural_vector(0 to 15)) return natural is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S8" severity error;
end loop;
return 6;
end F8;
function F9(inp : positive_vector(0 to 15)) return positive is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S9" severity error;
end loop;
return 6;
end F9;
function F10(inp : array_rec_std(0 to 7)) return record_std_package is
begin
for i in 0 to 7 loop
assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
end loop;
return (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100");
end F10;
end c01s01b01x01p05n02i00746pkg;
use work.c01s01b01x01p05n02i00746pkg.all;
ENTITY c01s01b01x01p05n02i00746ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "sssssss";
C11 : bit_vector := B"0000";
C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
);
port(
S1 : boolean_vector(zero to fifteen) := (others => C1);
S2 : severity_level_vector(zero to fifteen) := (others => C4);
S3 : integer_vector(zero to fifteen) := (others => C5);
S4 : real_vector(zero to fifteen) := (others => C6);
S5 : time_vector (zero to fifteen) := (others => C7);
S6 : natural_vector(zero to fifteen) := (others => C8);
S7 : positive_vector(zero to fifteen) := (others => C9);
S8 : string(one to seven) := C10;
S9 : bit_vector(zero to three) := C11;
S48: array_rec_std(zero to seven) := (others => C48)
);
END c01s01b01x01p05n02i00746ent;
ARCHITECTURE c01s01b01x01p05n02i00746arch OF c01s01b01x01p05n02i00746ent IS
BEGIN
TESTING: PROCESS
variable var1 : boolean;
variable var4 : severity_level;
variable var5 : integer;
variable var6 : real;
variable var7 : time;
variable var8 : natural;
variable var9 : positive;
variable var2 : bit;
variable var3 : character;
variable var48: record_std_package;
BEGIN
var1 := F1(S1);
var2 := F2(S9);
var3 := F3(S8);
var4 := F4(S2);
var5 := F5(S3);
var6 := F6(S4);
var7 := F7(S5);
var8 := F8(S6);
var9 := F9(S7);
var48 := F10(S48);
wait for 1 ns;
assert(var1 = false) report "wrong assignment in the function F1" severity error;
assert(var2 = '0') report "wrong assignment in the function F2" severity error;
assert(var3 = 'h') report "wrong assignment in the function F3" severity error;
assert(var4 = error) report "wrong assignment in the function F4" severity error;
assert(var5 = 6) report "wrong assignment in the function F5" severity error;
assert(var6 = 6.0) report "wrong assignment in the function F6" severity error;
assert(var7 = 6 ns) report "wrong assignment in the function F7" severity error;
assert(var8 = 6) report "wrong assignment in the function F8" severity error;
assert(var9 = 6) report "wrong assignment in the function F9" severity error;
assert(var48 = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")) report "wrong assignment in the function F10" severity error;
assert NOT( var1 = F1(S1) and
var2 = F2(S9) and
var3 = F3(S8) and
var4 = F4(S2) and
var5 = F5(S3) and
var6 = F6(S4) and
var7 = F7(S5) and
var8 = F8(S6) and
var9 = F9(S7) and
var48 = F10(S48) )
report "***PASSED TEST: c01s01b01x01p05n02i00746"
severity NOTE;
assert ( var1 = F1(S1) and
var2 = F2(S9) and
var3 = F3(S8) and
var4 = F4(S2) and
var5 = F5(S3) and
var6 = F6(S4) and
var7 = F7(S5) and
var8 = F8(S6) and
var9 = F9(S7) and
var48 = F10(S48) )
report "***FAILED TEST: c01s01b01x01p05n02i00746 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00746arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc746.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00746pkg is
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(1 to 7);
k:bit_vector(0 to 3);
end record;
type array_rec_std is array (integer range <>) of record_std_package;
function F1(inp : boolean_vector(0 to 15)) return boolean ;
function F2(inp : bit_vector(0 to 3)) return bit ;
function F3(inp : string(1 to 7)) return character ;
function F4(inp : severity_level_vector(0 to 15)) return severity_level ;
function F5(inp : integer_vector(0 to 15)) return integer ;
function F6(inp : real_vector(0 to 15)) return real ;
function F7(inp : time_vector(0 to 15)) return time ;
function F8(inp : natural_vector(0 to 15)) return natural ;
function F9(inp : positive_vector(0 to 15)) return positive ;
function F10(inp: array_rec_std(0 to 7)) return record_std_package ;
end c01s01b01x01p05n02i00746pkg;
package body c01s01b01x01p05n02i00746pkg is
function F1(inp : boolean_vector(0 to 15)) return boolean is
begin
for i in 0 to 15 loop
assert(inp(i) = true) report"wrong initialization of S1" severity error;
end loop;
return false;
end F1;
function F2(inp : bit_vector(0 to 3)) return bit is
begin
for i in 0 to 3 loop
assert(inp(i) = '0') report"wrong initialization of S2" severity error;
end loop;
return '0';
end F2;
function F3(inp : string(1 to 7)) return character is
begin
for i in 1 to 7 loop
assert(inp(i) = 's') report"wrong initialization of S3" severity error;
end loop;
return 'h';
end F3;
function F4(inp : severity_level_vector(0 to 15)) return severity_level is
begin
for i in 0 to 15 loop
assert(inp(i) = note) report"wrong initialization of S4" severity error;
end loop;
return error;
end F4;
function F5(inp : integer_vector(0 to 15)) return integer is
begin
for i in 0 to 15 loop
assert(inp(i) = 3) report"wrong initialization of S5" severity error;
end loop;
return 6;
end F5;
function F6(inp : real_vector(0 to 15)) return real is
begin
for i in 0 to 15 loop
assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
end loop;
return 6.0;
end F6;
function F7(inp : time_vector(0 to 15)) return time is
begin
for i in 0 to 15 loop
assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
end loop;
return 6 ns;
end F7;
function F8(inp : natural_vector(0 to 15)) return natural is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S8" severity error;
end loop;
return 6;
end F8;
function F9(inp : positive_vector(0 to 15)) return positive is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S9" severity error;
end loop;
return 6;
end F9;
function F10(inp : array_rec_std(0 to 7)) return record_std_package is
begin
for i in 0 to 7 loop
assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
end loop;
return (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100");
end F10;
end c01s01b01x01p05n02i00746pkg;
use work.c01s01b01x01p05n02i00746pkg.all;
ENTITY c01s01b01x01p05n02i00746ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "sssssss";
C11 : bit_vector := B"0000";
C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
);
port(
S1 : boolean_vector(zero to fifteen) := (others => C1);
S2 : severity_level_vector(zero to fifteen) := (others => C4);
S3 : integer_vector(zero to fifteen) := (others => C5);
S4 : real_vector(zero to fifteen) := (others => C6);
S5 : time_vector (zero to fifteen) := (others => C7);
S6 : natural_vector(zero to fifteen) := (others => C8);
S7 : positive_vector(zero to fifteen) := (others => C9);
S8 : string(one to seven) := C10;
S9 : bit_vector(zero to three) := C11;
S48: array_rec_std(zero to seven) := (others => C48)
);
END c01s01b01x01p05n02i00746ent;
ARCHITECTURE c01s01b01x01p05n02i00746arch OF c01s01b01x01p05n02i00746ent IS
BEGIN
TESTING: PROCESS
variable var1 : boolean;
variable var4 : severity_level;
variable var5 : integer;
variable var6 : real;
variable var7 : time;
variable var8 : natural;
variable var9 : positive;
variable var2 : bit;
variable var3 : character;
variable var48: record_std_package;
BEGIN
var1 := F1(S1);
var2 := F2(S9);
var3 := F3(S8);
var4 := F4(S2);
var5 := F5(S3);
var6 := F6(S4);
var7 := F7(S5);
var8 := F8(S6);
var9 := F9(S7);
var48 := F10(S48);
wait for 1 ns;
assert(var1 = false) report "wrong assignment in the function F1" severity error;
assert(var2 = '0') report "wrong assignment in the function F2" severity error;
assert(var3 = 'h') report "wrong assignment in the function F3" severity error;
assert(var4 = error) report "wrong assignment in the function F4" severity error;
assert(var5 = 6) report "wrong assignment in the function F5" severity error;
assert(var6 = 6.0) report "wrong assignment in the function F6" severity error;
assert(var7 = 6 ns) report "wrong assignment in the function F7" severity error;
assert(var8 = 6) report "wrong assignment in the function F8" severity error;
assert(var9 = 6) report "wrong assignment in the function F9" severity error;
assert(var48 = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")) report "wrong assignment in the function F10" severity error;
assert NOT( var1 = F1(S1) and
var2 = F2(S9) and
var3 = F3(S8) and
var4 = F4(S2) and
var5 = F5(S3) and
var6 = F6(S4) and
var7 = F7(S5) and
var8 = F8(S6) and
var9 = F9(S7) and
var48 = F10(S48) )
report "***PASSED TEST: c01s01b01x01p05n02i00746"
severity NOTE;
assert ( var1 = F1(S1) and
var2 = F2(S9) and
var3 = F3(S8) and
var4 = F4(S2) and
var5 = F5(S3) and
var6 = F6(S4) and
var7 = F7(S5) and
var8 = F8(S6) and
var9 = F9(S7) and
var48 = F10(S48) )
report "***FAILED TEST: c01s01b01x01p05n02i00746 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00746arch;
|
-------------------------------------------------------------------------------
-- system_microblaze_0_d_bram_ctrl_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_10_a;
use lmb_bram_if_cntlr_v3_10_a.all;
entity system_microblaze_0_d_bram_ctrl_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to 31);
LMB1_WriteDBus : in std_logic_vector(0 to 31);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to 3);
Sl1_DBus : out std_logic_vector(0 to 31);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to 31);
LMB2_WriteDBus : in std_logic_vector(0 to 31);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to 3);
Sl2_DBus : out std_logic_vector(0 to 31);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to 31);
LMB3_WriteDBus : in std_logic_vector(0 to 31);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to 3);
Sl3_DBus : out std_logic_vector(0 to 31);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_microblaze_0_d_bram_ctrl_wrapper : entity is "lmb_bram_if_cntlr_v3_10_a";
end system_microblaze_0_d_bram_ctrl_wrapper;
architecture STRUCTURE of system_microblaze_0_d_bram_ctrl_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_MASK1 : std_logic_vector(0 to 31);
C_MASK2 : std_logic_vector(0 to 31);
C_MASK3 : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_NUM_LMB : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
UE : out std_logic;
CE : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
microblaze_0_d_bram_ctrl : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00007fff",
C_FAMILY => "spartan6",
C_MASK => X"40000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_NUM_LMB => 1,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
UE => UE,
CE => CE,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity alu is
port (
clk: in std_logic;
rst: in std_logic;
a: in unsigned(31 downto 0);
b: in unsigned(31 downto 0);
o: out unsigned(31 downto 0);
y: out unsigned(31 downto 0);
op: in alu_op_type;
en: in std_logic;
ci: in std_logic;
cen: in std_logic; -- Carry enable
busy: out std_logic;
valid: out std_logic;
co: out std_logic;
zero: out std_logic;
ovf: out std_logic;
sign: out std_logic
);
end entity;
architecture behave of alu is
signal alu_a, alu_b, alu_r: unsigned(32 downto 0);
signal alu_add_r, alu_sub_r: unsigned(32 downto 0);
signal carryext: unsigned (32 downto 0);
signal modify_flags: boolean;
component mult is
port (
clk: in std_logic;
rst: in std_logic;
lhs: in signed(31 downto 0);
rhs: in signed(31 downto 0);
en: in std_logic;
m: out signed(31 downto 0);
y: out signed(31 downto 0);
valid: out std_logic; -- Multiplication valid
comp: out std_logic -- Computing
);
end component;
component shifter is
port (
a: in unsigned(31 downto 0);
b: in unsigned(4 downto 0);
o: out unsigned(31 downto 0);
left: in std_logic;
arith:in std_logic
);
end component;
signal mult_en: std_logic;
signal mult_a: signed(31 downto 0);
signal mult_b: signed(31 downto 0);
signal mult_r: signed(31 downto 0);
signal mult_y: signed(31 downto 0);
signal mult_busy: std_logic;
signal mult_valid: std_logic;
signal shift_arith: std_logic;
signal shift_out: unsigned(31 downto 0);
signal shift_left: std_logic;
begin
mulen: if MULT_ENABLED generate
valid <= mult_valid;
multiplier: mult
port map (
clk => clk,
rst => rst,
lhs => mult_a,
rhs => mult_b,
en => mult_en,
m => mult_r,
y => mult_y,
valid => mult_valid,
comp => mult_busy
);
end generate;
muldis: if not MULT_ENABLED generate
mult_r <= (others => 'X');
mult_y <= (others => 'X');
mult_valid <= '0';
mult_busy <= '0';
end generate;
shifter_inst: shifter
port map (
a => alu_a(31 downto 0),
b => alu_b(4 downto 0),
o => shift_out,
left => shift_left,
arith => shift_arith
);
busy <= mult_busy;
alu_a <= '0' & a;
alu_b <= '0' & b;
mult_a <= signed(a);
mult_b <= signed(b);
carryext(32 downto 1) <= (others => '0');
carryext(0) <= ci when cen='1' else '0';--op=ALU_ADDC or op=ALU_SUBB else '0';
alu_add_r <= alu_a + alu_b + carryext;
alu_sub_r <= alu_a - alu_b - carryext;
mult_en <= '1' when op=ALU_MUL and en='1' else '0';
process(alu_add_r, carryext, alu_a, alu_b, alu_sub_r, op, mult_valid, mult_r,shift_out,mult_y)
begin
shift_left <= 'X';
shift_arith <= 'X';
case op is
when ALU_ADD => -- | ALU_ADDRI |ALU_ADDC =>
alu_r <= alu_add_r;
when ALU_SUB => --| ALU_CMP | ALU_SUBB =>
alu_r <= alu_sub_r;
when ALU_AND => alu_r <= alu_a and alu_b;
when ALU_OR => alu_r <= alu_a or alu_b;
--when ALU_NOT => alu_r <= not alu_a;
when ALU_XOR => alu_r <= alu_a xor alu_b;
when ALU_SEXTB => alu_r(7 downto 0) <= alu_a(7 downto 0);
alu_r(32 downto 8) <= (others => alu_a(7));
when ALU_SEXTS => alu_r(15 downto 0) <= alu_a(15 downto 0);
alu_r(32 downto 16) <= (others => alu_a(15));
when ALU_SHL =>
shift_arith<='X';
shift_left<='1';
alu_r <= 'X' & shift_out;
when ALU_SRA =>
shift_arith<='1';
shift_left<='0';
alu_r <= 'X' & shift_out;
when ALU_SRL =>
shift_arith<='0';
shift_left<='0';
alu_r <= 'X' & shift_out;
when ALU_MUL =>
alu_r <= mult_y(31) & unsigned(mult_r);
when others => alu_r <= (others =>'X');
end case;
-- if mult_valid='1' then
-- alu_r <= mult_y(31) & unsigned(mult_r);
-- end if;
end process;
y <= unsigned(mult_y);
o <= alu_r(31 downto 0);
co <= alu_sub_r(32);
sign <= alu_sub_r(31);
zero <= '1' when alu_sub_r(31 downto 0)=x"00000000" else '0';
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity topo is
port ( SW : in std_logic_vector (17 downto 0);
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7: out std_logic_vector(6 downto 0);
LEDR : out std_logic_vector (17 downto 0);
LEDG : out std_logic_vector (7 downto 0);
KEY: in std_logic_vector(3 downto 0);
clock_50: in std_logic
);
end topo;
architecture topo_stru of topo is
component contador_pontos is
port (compara, user, cont_match, clock, reset: in std_logic;
ledred, ledgrn: out std_logic_vector(7 downto 0)
);
end component;
component decod is
port (C: in std_logic_vector(3 downto 0);
S: out std_logic_vector(6 downto 0)
);
end component;
component vector_to_bcd is port(
input: in std_logic_vector(7 downto 0);
to_decod1, to_decod0: out std_logic_vector(3 downto 0)
);
end component;
component comparador is
port (compara, player, clock: in std_logic;
tiro: in std_logic_vector(13 downto 0);
address: in std_logic_vector(1 downto 0);
match: out std_logic
);
end component;
component fsm
port (dif: in std_logic_vector(1 downto 0);
clock, init, fire, reset: in std_logic;
memaddr: in std_logic_vector(1 downto 0);
linha: in std_logic_vector(13 downto 0);
displaycont: out std_logic_vector(7 downto 0);
displayaddr: out std_logic_vector(1 downto 0);
displaylinha: out std_logic_vector(13 downto 0);
user, compara: out std_logic;
difout: out std_logic_vector(1 downto 0)
);
end component;
signal jogador, comparar, tiro_match: std_logic;
signal dificuldade, addr_to_hex, jog_to_hex: std_logic_vector(1 downto 0);
signal to_contador: std_logic_vector(7 downto 0);
signal to_dec1, to_dec0, linha_to_decod: std_logic_vector(3 downto 0);
signal linha_to_number: std_logic_vector(13 downto 0);
begin
-- cria a fsm e designa os parametros. entradas: dificuldade, clock, init, fire, endereco de memoria, tiro
-- saidas: contador, endereco de memoria para o hex e comparador, linha de tiro para hex e comparador, jogador atual, enable do comparador e dificuldade
machine: fsm port map (SW(17 downto 16), clock_50, KEY(2), KEY(3), KEY(0), SW(15 downto 14), SW(13 downto 0), to_contador, addr_to_hex, linha_to_number, jogador, comparar, dificuldade);
-- entrega um vetor de 8 bits com o tempo restante para o conversor que transforma em 2 vetores de 4 bits com o mesmo valor em bcd
vector_bcd: vector_to_bcd port map (to_contador, to_dec1, to_dec0);
-- cria o comparador e liga ele aos seus parametros. entradas: enable, jogador atual, clock, linha de tiro e endereco de memoria
-- saidas: match
comp: comparador port map (comparar, jogador, clock_50, linha_to_number, addr_to_hex, tiro_match);
-- cria o contador de pontos e liga ele aos seus parametros. entradas: enable (caso esteja 1, ele "escuta" o que entra no match), jogador atual, match, clock e reset
-- saidas: ledr e ledg
pontuacao: contador_pontos port map (comparar, jogador, tiro_match, clock_50, KEY(0), LEDR(7 downto 0), LEDG(7 downto 0));
-- digito da unidade do contador para 7 segmentos
decod_hex0: decod port map(to_dec0, HEX0);
-- digito da dezena do contador para 7 segmentos
decod_hex1: decod port map(to_dec1, HEX1);
-- digito da dificuldade para 7 segmentos
decod_hex2: decod port map (("00"&dificuldade)+"1", HEX2);
-- "L"
HEX3 <= "1000111";
process(jogador) -- decodifica o std_logic que guarda o numero do jogado para 7 segmentos
begin
if jogador = '0' then
jog_to_hex <= "01";
else
jog_to_hex <= "10";
end if;
end process;
decod_hex4: decod port map ("00"&jog_to_hex, HEX4);
-- "U"
HEX5 <= "1000001";
process(linha_to_number) -- percorre os swiches 13 ao 0 para descobrir qual esta ativo, entao decodifica seu numero para 7 segmentos
variable i: integer;
variable position: integer;
begin
position := 0;
for i in 0 to 13 loop
if linha_to_number(i) = '1' then
position := i;
end if;
end loop;
linha_to_decod <= std_logic_vector(to_unsigned(position, linha_to_decod'length));
end process;
-- numero da coluna gerado pelo process acima
decod_hex6: decod port map (linha_to_decod, HEX6);
-- numero da linha da matriz escolhido pelos switches 15 e 14
decod_hex7: decod port map ("00"&addr_to_hex, HEX7);
end topo_stru; |
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: debug_ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 17.0.0 Build 595 04/25/2017 SJ Standard Edition
-- ************************************************************
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY debug_ram IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END debug_ram;
ARCHITECTURE SYN OF debug_ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=dbg",
lpm_type => "altsyncram",
numwords_a => 32,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 5,
width_a => 32,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "dbg"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=dbg"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL debug_ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL debug_ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL debug_ram.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL debug_ram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL debug_ram_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity alu is
port(
func : in std_logic_vector(3 downto 0);
busA : in std_logic_vector(15 downto 0);
busB : in std_logic_vector(15 downto 0);
inZ : in std_logic;
inS : in std_logic;
inO : in std_logic;
outZ : out std_logic;
outS : out std_logic;
outO : out std_logic;
busC : out std_logic_vector(15 downto 0)
);
end alu;
architecture BEHAVIOR of alu is
-- Definitions --
signal ans : std_logic_vector(15 downto 0);
signal atop : std_logic;
signal btop : std_logic;
signal ftop : std_logic;
signal shift_ov : std_logic;
-- Main --
begin
busC <= ans;
-- Calculate Process --
process(func, busA, busB) begin
case func is
when "0000" => -- select busA (not only HALT) --
ans <= busA;
when "0001" => -- select busB (not only LD1) --
ans <= busB;
when "0101" => -- ADD --
ans <= busA + busB;
when "0110" => -- SUB --
ans <= busA - busB;
when "0111" => -- SL --
if(busB = "0000000000010000") then
shift_ov <= busA(0); ans <= "0000000000000000";
elsif(busB > "0000000000010000") then
shift_ov <= '0'; ans <= "0000000000000000";
else
case busB(3 downto 0) is
when "0000" => shift_ov <= '0'; ans <= busA;
when "0001" => shift_ov <= busA(15); ans <= busA(14 downto 0) & '0';
when "0010" => shift_ov <= busA(14); ans <= busA(13 downto 0) & "00";
when "0011" => shift_ov <= busA(13); ans <= busA(12 downto 0) & "000";
when "0100" => shift_ov <= busA(12); ans <= busA(11 downto 0) & "0000";
when "0101" => shift_ov <= busA(11); ans <= busA(10 downto 0) & "00000";
when "0110" => shift_ov <= busA(10); ans <= busA( 9 downto 0) & "000000";
when "0111" => shift_ov <= busA( 9); ans <= busA( 8 downto 0) & "0000000";
when "1000" => shift_ov <= busA( 8); ans <= busA( 7 downto 0) & "00000000";
when "1001" => shift_ov <= busA( 7); ans <= busA( 6 downto 0) & "000000000";
when "1010" => shift_ov <= busA( 6); ans <= busA( 5 downto 0) & "0000000000";
when "1011" => shift_ov <= busA( 5); ans <= busA( 4 downto 0) & "00000000000";
when "1100" => shift_ov <= busA( 4); ans <= busA( 3 downto 0) & "000000000000";
when "1101" => shift_ov <= busA( 3); ans <= busA( 2 downto 0) & "0000000000000";
when "1110" => shift_ov <= busA( 2); ans <= busA( 1 downto 0) & "00000000000000";
when "1111" => shift_ov <= busA( 1); ans <= busA(0) & "000000000000000";
when others => shift_ov <= '0'; ans <= busA;
end case;
end if;
when "1000" => -- SR --
if(busB = "0000000000010000") then
shift_ov <= busA(15); ans <= "0000000000000000";
elsif(busB > "0000000000010000") then
shift_ov <= '0'; ans <= "0000000000000000";
else
case busB(3 downto 0) is
when "0000" => shift_ov <= '0'; ans <= busA;
when "0001" => shift_ov <= busA( 0); ans <= '0' & busA(15 downto 1);
when "0010" => shift_ov <= busA( 1); ans <= "00" & busA(15 downto 2);
when "0011" => shift_ov <= busA( 2); ans <= "000" & busA(15 downto 3);
when "0100" => shift_ov <= busA( 3); ans <= "0000" & busA(15 downto 4);
when "0101" => shift_ov <= busA( 4); ans <= "00000" & busA(15 downto 5);
when "0110" => shift_ov <= busA( 5); ans <= "000000" & busA(15 downto 6);
when "0111" => shift_ov <= busA( 6); ans <= "0000000" & busA(15 downto 7);
when "1000" => shift_ov <= busA( 7); ans <= "00000000" & busA(15 downto 8);
when "1001" => shift_ov <= busA( 8); ans <= "000000000" & busA(15 downto 9);
when "1010" => shift_ov <= busA( 9); ans <= "0000000000" & busA(15 downto 10);
when "1011" => shift_ov <= busA(10); ans <= "00000000000" & busA(15 downto 11);
when "1100" => shift_ov <= busA(11); ans <= "000000000000" & busA(15 downto 12);
when "1101" => shift_ov <= busA(12); ans <= "0000000000000" & busA(15 downto 13);
when "1110" => shift_ov <= busA(13); ans <= "00000000000000" & busA(15 downto 14);
when "1111" => shift_ov <= busA(14); ans <= "000000000000000" & busA(15);
when others => shift_ov <= '0'; ans <= busA;
end case;
end if;
when "1001" => -- NAND --
ans <= busA nand busB;
when "1010" => -- JMP --
ans <= busA; --------------------------- effective address
when "1011" => -- JZE --
if(inZ = '1') then
ans <= busA; ----------------------- effective address
else
ans <= busB + "0000000000000001"; -- program register
end if;
when "1100" => -- JMI --
if(inS = '1') then
ans <= busA; ----------------------- effective address
else
ans <= busB + "0000000000000001"; -- program register
end if;
when "1101" => -- JOV --
if(inO = '1') then
ans <= busA; ----------------------- effective address
else
ans <= busB + "0000000000000001"; -- program register
end if;
when "1110" => -- RJMP --
ans <= busA; --------------------------- general register
when "1111" => -- DISP --
ans <= "000000000000" & busA(3 downto 0);
when others =>
ans <= "XXXXXXXXXXXXXXXX";
end case;
end process;
-- GetTop Process --
process(busA, busB, ans) begin
atop <= busA(15);
btop <= busB(15);
ftop <= ans(15);
if(ans = "0000000000000000") then
outZ <= '1';
else
outZ <= '0';
end if;
end process;
-- Flag Process --
process(func, atop, btop, ftop) begin
case func is
when "0101" =>
if(((atop and btop) or (atop and not ftop) or (btop and not ftop)) = '1') then
outO <= '1';
else
outO <= '0';
end if;
when "0110" =>
if(((not atop and (btop or ftop)) or (btop and ftop)) = '1') then
outO <= '1';
else
outO <= '0';
end if;
when "0111" =>
outO <= shift_ov;
when "1000" =>
outO <= shift_ov;
when others =>
outO <= '0';
end case;
outS <= ftop;
end process;
end BEHAVIOR;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity alu is
port(
func : in std_logic_vector(3 downto 0);
busA : in std_logic_vector(15 downto 0);
busB : in std_logic_vector(15 downto 0);
inZ : in std_logic;
inS : in std_logic;
inO : in std_logic;
outZ : out std_logic;
outS : out std_logic;
outO : out std_logic;
busC : out std_logic_vector(15 downto 0)
);
end alu;
architecture BEHAVIOR of alu is
-- Definitions --
signal ans : std_logic_vector(15 downto 0);
signal atop : std_logic;
signal btop : std_logic;
signal ftop : std_logic;
signal shift_ov : std_logic;
-- Main --
begin
busC <= ans;
-- Calculate Process --
process(func, busA, busB) begin
case func is
when "0000" => -- select busA (not only HALT) --
ans <= busA;
when "0001" => -- select busB (not only LD1) --
ans <= busB;
when "0101" => -- ADD --
ans <= busA + busB;
when "0110" => -- SUB --
ans <= busA - busB;
when "0111" => -- SL --
if(busB = "0000000000010000") then
shift_ov <= busA(0); ans <= "0000000000000000";
elsif(busB > "0000000000010000") then
shift_ov <= '0'; ans <= "0000000000000000";
else
case busB(3 downto 0) is
when "0000" => shift_ov <= '0'; ans <= busA;
when "0001" => shift_ov <= busA(15); ans <= busA(14 downto 0) & '0';
when "0010" => shift_ov <= busA(14); ans <= busA(13 downto 0) & "00";
when "0011" => shift_ov <= busA(13); ans <= busA(12 downto 0) & "000";
when "0100" => shift_ov <= busA(12); ans <= busA(11 downto 0) & "0000";
when "0101" => shift_ov <= busA(11); ans <= busA(10 downto 0) & "00000";
when "0110" => shift_ov <= busA(10); ans <= busA( 9 downto 0) & "000000";
when "0111" => shift_ov <= busA( 9); ans <= busA( 8 downto 0) & "0000000";
when "1000" => shift_ov <= busA( 8); ans <= busA( 7 downto 0) & "00000000";
when "1001" => shift_ov <= busA( 7); ans <= busA( 6 downto 0) & "000000000";
when "1010" => shift_ov <= busA( 6); ans <= busA( 5 downto 0) & "0000000000";
when "1011" => shift_ov <= busA( 5); ans <= busA( 4 downto 0) & "00000000000";
when "1100" => shift_ov <= busA( 4); ans <= busA( 3 downto 0) & "000000000000";
when "1101" => shift_ov <= busA( 3); ans <= busA( 2 downto 0) & "0000000000000";
when "1110" => shift_ov <= busA( 2); ans <= busA( 1 downto 0) & "00000000000000";
when "1111" => shift_ov <= busA( 1); ans <= busA(0) & "000000000000000";
when others => shift_ov <= '0'; ans <= busA;
end case;
end if;
when "1000" => -- SR --
if(busB = "0000000000010000") then
shift_ov <= busA(15); ans <= "0000000000000000";
elsif(busB > "0000000000010000") then
shift_ov <= '0'; ans <= "0000000000000000";
else
case busB(3 downto 0) is
when "0000" => shift_ov <= '0'; ans <= busA;
when "0001" => shift_ov <= busA( 0); ans <= '0' & busA(15 downto 1);
when "0010" => shift_ov <= busA( 1); ans <= "00" & busA(15 downto 2);
when "0011" => shift_ov <= busA( 2); ans <= "000" & busA(15 downto 3);
when "0100" => shift_ov <= busA( 3); ans <= "0000" & busA(15 downto 4);
when "0101" => shift_ov <= busA( 4); ans <= "00000" & busA(15 downto 5);
when "0110" => shift_ov <= busA( 5); ans <= "000000" & busA(15 downto 6);
when "0111" => shift_ov <= busA( 6); ans <= "0000000" & busA(15 downto 7);
when "1000" => shift_ov <= busA( 7); ans <= "00000000" & busA(15 downto 8);
when "1001" => shift_ov <= busA( 8); ans <= "000000000" & busA(15 downto 9);
when "1010" => shift_ov <= busA( 9); ans <= "0000000000" & busA(15 downto 10);
when "1011" => shift_ov <= busA(10); ans <= "00000000000" & busA(15 downto 11);
when "1100" => shift_ov <= busA(11); ans <= "000000000000" & busA(15 downto 12);
when "1101" => shift_ov <= busA(12); ans <= "0000000000000" & busA(15 downto 13);
when "1110" => shift_ov <= busA(13); ans <= "00000000000000" & busA(15 downto 14);
when "1111" => shift_ov <= busA(14); ans <= "000000000000000" & busA(15);
when others => shift_ov <= '0'; ans <= busA;
end case;
end if;
when "1001" => -- NAND --
ans <= busA nand busB;
when "1010" => -- JMP --
ans <= busA; --------------------------- effective address
when "1011" => -- JZE --
if(inZ = '1') then
ans <= busA; ----------------------- effective address
else
ans <= busB + "0000000000000001"; -- program register
end if;
when "1100" => -- JMI --
if(inS = '1') then
ans <= busA; ----------------------- effective address
else
ans <= busB + "0000000000000001"; -- program register
end if;
when "1101" => -- JOV --
if(inO = '1') then
ans <= busA; ----------------------- effective address
else
ans <= busB + "0000000000000001"; -- program register
end if;
when "1110" => -- RJMP --
ans <= busA; --------------------------- general register
when "1111" => -- DISP --
ans <= "000000000000" & busA(3 downto 0);
when others =>
ans <= "XXXXXXXXXXXXXXXX";
end case;
end process;
-- GetTop Process --
process(busA, busB, ans) begin
atop <= busA(15);
btop <= busB(15);
ftop <= ans(15);
if(ans = "0000000000000000") then
outZ <= '1';
else
outZ <= '0';
end if;
end process;
-- Flag Process --
process(func, atop, btop, ftop) begin
case func is
when "0101" =>
if(((atop and btop) or (atop and not ftop) or (btop and not ftop)) = '1') then
outO <= '1';
else
outO <= '0';
end if;
when "0110" =>
if(((not atop and (btop or ftop)) or (btop and ftop)) = '1') then
outO <= '1';
else
outO <= '0';
end if;
when "0111" =>
outO <= shift_ov;
when "1000" =>
outO <= shift_ov;
when others =>
outO <= '0';
end case;
outS <= ftop;
end process;
end BEHAVIOR;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_hessian:1.0
-- IP Revision: 41
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_hessian_1_0 IS
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_hessian_1_0;
ARCHITECTURE system_vga_hessian_1_0_arch OF system_vga_hessian_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_hessian_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_hessian IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_hessian;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_hessian
GENERIC MAP (
ROW_WIDTH => 10
)
PORT MAP (
clk_x16 => clk_x16,
active => active,
rst => rst,
x_addr => x_addr,
y_addr => y_addr,
g_in => g_in,
hessian_out => hessian_out
);
END system_vga_hessian_1_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_hessian:1.0
-- IP Revision: 41
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_hessian_1_0 IS
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_hessian_1_0;
ARCHITECTURE system_vga_hessian_1_0_arch OF system_vga_hessian_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_hessian_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_hessian IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_hessian;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_hessian
GENERIC MAP (
ROW_WIDTH => 10
)
PORT MAP (
clk_x16 => clk_x16,
active => active,
rst => rst,
x_addr => x_addr,
y_addr => y_addr,
g_in => g_in,
hessian_out => hessian_out
);
END system_vga_hessian_1_0_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity DIVIDER_32b_4x_fast is
generic(SIZE: INTEGER := 32);
port(
reset : in STD_LOGIC;
start : in STD_LOGIC;
clk : in STD_LOGIC;
INPUT_1 : in STD_LOGIC_VECTOR((SIZE - 1) downto 0);
INPUT_2 : in STD_LOGIC_VECTOR((SIZE - 1) downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR((SIZE - 1) downto 0);
OUTPUT_2 : out STD_LOGIC_VECTOR((SIZE - 1) downto 0);
ready : out STD_LOGIC
);
end DIVIDER_32b_4x_fast;
ARCHITECTURE behav of DIVIDER_32b_4x_fast IS
signal buf : STD_LOGIC_VECTOR((2 * SIZE - 1) downto 0);
signal dbuf : STD_LOGIC_VECTOR((SIZE - 1) downto 0);
signal sm : INTEGER range 0 to (SIZE/4);
alias buf1 is buf((2 * SIZE - 1) downto SIZE);
alias buf2 is buf((SIZE - 1) downto 0);
begin
process(reset, start, clk)
variable tbuf2 : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf1v : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf1f : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf2vv : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf2vf : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf2fv : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf2ff : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf3v : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf3f : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf4vv : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf4vf : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf4fv : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable tbuf4ff : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
begin
if reset = '1' then
OUTPUT_1 <= (others => '0');
OUTPUT_2 <= (others => '0');
sm <= 0;
ready <= '0';
elsif rising_edge(clk) then
case sm is
when 0 =>
OUTPUT_1 <= buf2;
OUTPUT_2 <= buf1;
ready <= '0';
buf2 <= (others => 'X');
dbuf <= INPUT_2;
buf1 <= (others => 'X');
if start = '1' then
buf1 <= (others => '0');
buf2 <= INPUT_1;
sm <= sm + 1;
else
sm <= sm;
end if;
when others =>
-- PREMIERE ITERATION DEROULEE DE LA DIVISION
tbuf1v((2 * SIZE - 1) downto SIZE) := '0' & (buf((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf1v((SIZE - 1) downto 0) := buf2((SIZE - 2) downto 0) & '1'; -- ON POUSSE LE RESULTAT
tbuf1f := buf((2 * SIZE - 2) downto 0) & '0';
-- QUATRIEME ITERATION DEROULEE DE LA DIVISION
tbuf2vv((2 * SIZE - 1) downto SIZE) := '0' & (tbuf1v((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf2vv((SIZE - 1) downto 0) := tbuf1v((SIZE - 2) downto 0) & '1';
tbuf2vf := tbuf1v((2 * SIZE - 2) downto 0) & '0';
tbuf2fv((2 * SIZE - 1) downto SIZE) := '0' & (tbuf1f((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf2fv((SIZE - 1) downto 0) := tbuf1f((SIZE - 2) downto 0) & '1';
tbuf2ff := tbuf1f((2 * SIZE - 2) downto 0) & '0';
if buf((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
if tbuf1v((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
tbuf2 := tbuf2vv;
else
tbuf2 := tbuf2vf;
end if;
else
if tbuf1v((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
tbuf2 := tbuf2fv;
else
tbuf2 := tbuf2ff;
end if;
end if;
-- TROISIEME ITERATION DEROULEE DE LA DIVISION
tbuf3v((2 * SIZE - 1) downto SIZE) := '0' & (tbuf2((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf3v((SIZE - 1) downto 0) := tbuf2((SIZE - 2) downto 0) & '1';
tbuf3f := tbuf2((2 * SIZE - 2) downto 0) & '0';
-- QUATRIEME ITERATION DEROULEE DE LA DIVISION
tbuf4vv((2 * SIZE - 1) downto SIZE) := '0' & (tbuf3v((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf4vv((SIZE - 1) downto 0) := tbuf3v((SIZE - 2) downto 0) & '1';
tbuf4vf := tbuf3v((2 * SIZE - 2) downto 0) & '0';
tbuf4fv((2 * SIZE - 1) downto SIZE) := '0' & (tbuf3f((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf4fv((SIZE - 1) downto 0) := tbuf3f((SIZE - 2) downto 0) & '1';
tbuf4ff := tbuf3f((2 * SIZE - 2) downto 0) & '0';
if tbuf2((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
if tbuf3v((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
buf <= tbuf4vv;
else
buf <= tbuf4vf;
end if;
else
if tbuf3f((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
buf <= tbuf4fv;
else
buf <= tbuf4ff;
end if;
end if;
-- QUEL VA ETRE NOTRE PROCHAIN ETAT ?
if sm /= (SIZE/4) then
sm <= sm + 1;
ready <= '0';
else
sm <= 0;
ready <= '1';
end if;
end case;
end if;
end process;
end behav;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 17:57:15 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_8/mul8_8_stub.vhdl
-- Design : mul8_8
-- Purpose : Stub declaration of top-level module interface
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mul8_8 is
Port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end mul8_8;
architecture stub of mul8_8 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,A[7:0],B[7:0],P[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "mult_gen_v12_0_12,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 17:57:15 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_8/mul8_8_stub.vhdl
-- Design : mul8_8
-- Purpose : Stub declaration of top-level module interface
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mul8_8 is
Port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end mul8_8;
architecture stub of mul8_8 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,A[7:0],B[7:0],P[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "mult_gen_v12_0_12,Vivado 2016.4";
begin
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity sub is
port (
clk : out std_logic;
cnt : inout integer := 0);
end entity;
architecture test of sub is
signal clk_i : bit := '0';
signal clk_std : std_logic;
begin
clk_i <= not clk_i after 1 ns;
clk_std <= to_stdulogic(clk_i);
clk <= clk_std;
process (clk_std) is
begin
if rising_edge(clk_std) then
cnt <= cnt + 1;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
entity ieee2 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of ieee2 is
signal cnt : integer := 0;
signal clk : std_logic;
begin
sub_i: entity work.sub port map ( clk, cnt );
process (clk) is
begin
if rising_edge(clk) then
report "clock!";
end if;
end process;
process is
begin
wait for 10 ns;
report integer'image(cnt);
assert cnt = 5;
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
use work.all;
use work.util.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.math_real.ALL;
use work.testbench_mm_master_pkg.all;
entity stream_to_avalon_tb is
end entity;
architecture sim of stream_to_avalon_tb is
signal stream_valid : std_logic ;
signal stream_ready : std_logic ;
signal stream_data : std_logic_vector(15 downto 0);
signal ctl_write: std_logic;
signal ctl_read: std_logic;
signal ctl_address: std_logic_vector(31 downto 0);
signal ctl_writedata: std_logic_vector(31 downto 0);
signal ctl_readdata: std_logic_vector(31 downto 0);
signal ctl_waitrequest: std_logic;
signal ctl_readdatavalid: std_logic;
signal writer_write: std_logic;
signal writer_waitrequest: std_logic;
signal writer_address: std_logic_vector(31 downto 0);
signal writer_burstcount: std_logic_vector(9 downto 0);
signal writer_writedata: std_logic_vector(127 downto 0);
signal clk, rst: std_logic;
signal rnd: real;
begin
clock: entity work.clock_gen
port map
(
clk => clk ,
rst => rst ,
rnd => rnd
);
source: entity work.random_stream_source
generic map (speed => 0.1, bw => 16, incrementing => true)
port map
(
clk => clk ,
rst => rst ,
out_valid => stream_valid ,
out_ready => stream_ready ,
out_data => stream_data
);
writer_waitrequest <= '1' when rnd > 0.01 else '0';
dut: entity work.stream_to_avalon
port map
(
stream_clk => clk ,
stream_rst => rst ,
stream_data => stream_data ,
stream_valid => stream_valid ,
stream_ready => stream_ready ,
clk => clk,
rst => rst,
ctl_write => ctl_write ,
ctl_read => ctl_read ,
ctl_address => ctl_address(3 downto 0) ,
ctl_writedata => ctl_writedata ,
ctl_readdata => ctl_readdata ,
ctl_waitrequest => ctl_waitrequest ,
ctl_readdatavalid => ctl_readdatavalid ,
writer_write => writer_write ,
writer_waitrequest => writer_waitrequest ,
writer_address => writer_address ,
writer_burstcount => writer_burstcount ,
writer_writedata => writer_writedata
);
tb_sm: entity work.testbench_mm_master generic map (instructions => (
(do_write, 1, 1024),
(do_write, 2, 8192),
(do_write, 0, 1),
(do_write, 0, 2),
(do_write, 0, 0),
(do_idle, 0, 0)
)) port map
(
clk => clk,
rst => rst,
mm_write => ctl_write ,
mm_waitrequest => ctl_waitrequest ,
mm_address => ctl_address ,
mm_writedata => ctl_writedata
);
ctl_read <= '0';
end architecture;
|
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <[email protected]>
--
-- Description:
-- Send data to MAX5541 DAC.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.lfsr_pkg.all;
entity max5541_interface is
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
data_i : in std_ulogic_vector(15 downto 0);
data_en_i : in std_ulogic;
busy_o : out std_ulogic;
done_o : out std_ulogic;
-- MAX5541 signals
cs_o : out std_ulogic;
sclk_o : out std_ulogic;
din_o : out std_ulogic);
end entity max5541_interface;
architecture rtl of max5541_interface is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- LFSR counter bit length
constant len_c : natural := lfsr_length(data_i'length);
-- LFSR counter initial value
constant seed_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_seed(len_c);
-- LFSR counter maximum value
constant max_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_shift(seed_c, data_i'length - 1);
-- FSM states
type state_t is (IDLE, CLK_HIGH, CLK_LOW);
-- FSM registers
type reg_t is record
state : state_t;
lfsr : std_ulogic_vector(len_c - 1 downto 0);
count : std_ulogic;
data : std_ulogic_vector(15 downto 0);
clk : std_ulogic;
done : std_ulogic;
end record reg_t;
-- FSM initial state
constant init_c : reg_t := (
state => IDLE,
lfsr => seed_c,
count => '0',
data => (others => '0'),
clk => '0',
done => '0');
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal reg : reg_t;
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal next_reg : reg_t;
signal busy : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
busy_o <= busy;
done_o <= reg.done;
cs_o <= not busy;
sclk_o <= reg.clk;
din_o <= reg.data(reg.data'high);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
-- FSM registering
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= next_reg;
end if;
end if;
end process regs;
------------------------------------------------------------------------------
-- Combinatorics
------------------------------------------------------------------------------
-- FSM combinatorics
comb : process(reg, data_i, data_en_i) is
begin -- process comb
-- Defaults
next_reg <= reg;
busy <= '1';
next_reg.done <= init_c.done;
case reg.state is
when IDLE =>
busy <= '0';
if data_en_i = '1' then
next_reg.data <= data_i;
next_reg.state <= CLK_HIGH;
end if;
when CLK_HIGH =>
if reg.count = '1' then
next_reg.clk <= '1';
next_reg.count <= '0';
next_reg.state <= CLK_LOW;
else
next_reg.count <= '1';
end if;
when CLK_LOW =>
if reg.count = '1' then
if reg.lfsr = max_c then
next_reg <= init_c;
next_reg.done <= '1';
else
next_reg.clk <= '0';
next_reg.count <= '0';
next_reg.state <= CLK_HIGH;
next_reg.data <= reg.data(reg.data'high - 1 downto reg.data'low) & '0';
next_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
else
next_reg.count <= '1';
end if;
end case;
end process comb;
end architecture rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: MMU
-- File: mmu.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: Leon3 MMU top level entity
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmu is
generic (
tech : integer range 0 to NTECH := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
mmudci : in mmudc_in_type;
mmudco : out mmudc_out_type;
mmuici : in mmuic_in_type;
mmuico : out mmuic_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type;
ramcclk : in std_ulogic := '0';
ramcin : in std_logic_vector(2*ramcbits-1 downto 0) := (others => '0');
ramcout : out std_logic_vector(2*ramcbits-1 downto 0)
);
end mmu;
architecture rtl of mmu is
constant MMUCTX_BITS : integer := M_CTX_SZ;
constant M_TLB_TYPE : integer range 0 to 1 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(1,2)); -- eather split or combined
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
constant M_ENT_I : integer range 2 to 64 := itlbnum; -- icache tlb entries: number
constant M_ENT_ILOG : integer := log2(M_ENT_I); -- icache tlb entries: address bits
constant M_ENT_D : integer range 2 to 64 := dtlbnum; -- dcache tlb entries: number
constant M_ENT_DLOG : integer := log2(M_ENT_D); -- dcache tlb entries: address bits
constant M_ENT_C : integer range 2 to 64 := M_ENT_I; -- i/dcache tlb entries: number
constant M_ENT_CLOG : integer := M_ENT_ILOG; -- i/dcache tlb entries: address bits
type mmu_op is record
trans_op : std_logic;
flush_op : std_logic;
diag_op : std_logic;
end record;
constant mmu_op_none : mmu_op := ('0', '0', '0');
type mmu_cmbpctrl is record
tlbowner : mmu_idcache;
tlbactive : std_logic;
op : mmu_op;
end record;
constant mmu_cmbpctrl_none : mmu_cmbpctrl := (id_icache, '0', mmu_op_none);
type mmu_rtype is record
cmb_s1 : mmu_cmbpctrl;
cmb_s2 : mmu_cmbpctrl;
splt_is1 : mmu_cmbpctrl;
splt_is2 : mmu_cmbpctrl;
splt_ds1 : mmu_cmbpctrl;
splt_ds2 : mmu_cmbpctrl;
twactive : std_logic; -- split tlb
twowner : mmu_idcache; -- split tlb
flush : std_logic;
mmctrl2 : mmctrl_type2;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : mmu_rtype := (
cmb_s1 => mmu_cmbpctrl_none,
cmb_s2 => mmu_cmbpctrl_none,
splt_is1 => mmu_cmbpctrl_none,
splt_is2 => mmu_cmbpctrl_none,
splt_ds1 => mmu_cmbpctrl_none,
splt_ds2 => mmu_cmbpctrl_none,
twactive => '0',
twowner => id_icache,
flush => '0',
mmctrl2 => mmctrl2_zero);
signal r, c : mmu_rtype;
-- tlb
component mmutlb
generic (
tech : integer range 0 to NTECH := 0;
entries : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
tlbi : in mmutlb_in_type;
tlbo : out mmutlb_out_type;
two : in mmutw_out_type;
twi : out mmutw_in_type;
ramcclk: in std_ulogic;
ramcin : in std_logic_vector(ramcbits-1 downto 0);
ramcout: out std_logic_vector(ramcbits-1 downto 0)
);
end component;
signal tlbi_a0 : mmutlb_in_type;
signal tlbi_a1 : mmutlb_in_type;
signal tlbo_a0 : mmutlb_out_type;
signal tlbo_a1 : mmutlb_out_type;
signal twi_a : mmutwi_a(1 downto 0);
signal two_a : mmutwo_a(1 downto 0);
-- table walk
component mmutw
generic (
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mmctrl1 : in mmctrl_type1;
twi : in mmutw_in_type;
two : out mmutw_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type
);
end component;
signal twi : mmutw_in_type;
signal two : mmutw_out_type;
signal mmctrl1 : mmctrl_type1;
begin
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
p0: process (rst, r, mmudci, mmuici, mcmmo, tlbo_a0, tlbo_a1, tlbi_a0, tlbi_a1, two_a, twi_a, two)
variable cmbtlbin : mmuidc_data_in_type;
variable cmbtlbout : mmutlb_out_type;
variable spltitlbin : mmuidc_data_in_type;
variable spltdtlbin : mmuidc_data_in_type;
variable spltitlbout : mmutlb_out_type;
variable spltdtlbout : mmutlb_out_type;
variable mmuico_transdata : mmuidc_data_out_type;
variable mmudco_transdata : mmuidc_data_out_type;
variable mmuico_grant : std_logic;
variable mmudco_grant : std_logic;
variable v : mmu_rtype;
variable twiv : mmutw_in_type;
variable twod, twoi : mmutw_out_type;
variable fault : mmutlbfault_out_type;
variable wbtransdata : mmuidc_data_out_type;
variable fs : mmctrl_fs_type;
variable fa : std_logic_vector(VA_I_SZ-1 downto 0);
begin
v := r;
wbtransdata.finish := '0';
wbtransdata.data := (others => '0');
wbtransdata.cache := '0';
wbtransdata.accexc := '0';
if (M_TLB_TYPE = 0) and (M_TLB_FASTWRITE /= 0) then
wbtransdata := tlbo_a1.wbtransdata;
end if;
cmbtlbin.data := (others => '0');
cmbtlbin.su := '0';
cmbtlbin.read := '0';
cmbtlbin.isid := id_dcache;
cmbtlbout.transdata.finish := '0';
cmbtlbout.transdata.data := (others => '0');
cmbtlbout.transdata.cache := '0';
cmbtlbout.transdata.accexc := '0';
cmbtlbout.fault.fault_pro := '0';
cmbtlbout.fault.fault_pri := '0';
cmbtlbout.fault.fault_access := '0';
cmbtlbout.fault.fault_mexc := '0';
cmbtlbout.fault.fault_trans := '0';
cmbtlbout.fault.fault_inv := '0';
cmbtlbout.fault.fault_lvl := (others => '0');
cmbtlbout.fault.fault_su := '0';
cmbtlbout.fault.fault_read := '0';
cmbtlbout.fault.fault_isid := id_dcache;
cmbtlbout.fault.fault_addr := (others => '0');
cmbtlbout.nexttrans := '0';
cmbtlbout.s1finished := '0';
mmuico_transdata.finish := '0';
mmuico_transdata.data := (others => '0');
mmuico_transdata.cache := '0';
mmuico_transdata.accexc := '0';
mmudco_transdata.finish := '0';
mmudco_transdata.data := (others => '0');
mmudco_transdata.cache := '0';
mmudco_transdata.accexc := '0';
mmuico_grant := '0';
mmudco_grant := '0';
twiv.walk_op_ur := '0';
twiv.areq_ur := '0';
twiv.data := (others => '0');
twiv.adata := (others => '0');
twiv.aaddr := (others => '0');
twod.finish := '0';
twod.data := (others => '0');
twod.addr := (others => '0');
twod.lvl := (others => '0');
twod.fault_mexc := '0';
twod.fault_trans := '0';
twod.fault_inv := '0';
twod.fault_lvl := (others => '0');
twoi.finish := '0';
twoi.data := (others => '0');
twoi.addr := (others => '0');
twoi.lvl := (others => '0');
twoi.fault_mexc := '0';
twoi.fault_trans := '0';
twoi.fault_inv := '0';
twoi.fault_lvl := (others => '0');
fault.fault_pro := '0';
fault.fault_pri := '0';
fault.fault_access := '0';
fault.fault_mexc := '0';
fault.fault_trans := '0';
fault.fault_inv := '0';
fault.fault_lvl := (others => '0');
fault.fault_su := '0';
fault.fault_read := '0';
fault.fault_isid := id_dcache;
fault.fault_addr := (others => '0');
fs.ow := '0';
fs.fav := '0';
fs.ft := (others => '0');
fs.at_ls := '0';
fs.at_id := '0';
fs.at_su := '0';
fs.l := (others => '0');
fs.ebe := (others => '0');
fa := (others => '0');
if M_TLB_TYPE = 0 then
spltitlbout := tlbo_a0;
spltdtlbout := tlbo_a1;
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
spltdtlbin := mmudci.transdata;
spltitlbin := mmuici.transdata;
mmudco_transdata := spltdtlbout.transdata;
mmuico_transdata := spltitlbout.transdata;
-- d-tlb
if ((not r.splt_ds1.tlbactive) or spltdtlbout.s1finished) = '1' then
v.splt_ds1.tlbactive := '0';
v.splt_ds1.op.trans_op := '0';
v.splt_ds1.op.flush_op := '0';
if mmudci.trans_op = '1' then
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
v.flush := '1';
mmudco_grant := '1';
v.splt_ds1.tlbactive := '1';
v.splt_ds1.op.flush_op := '1';
end if;
end if;
-- i-tlb
if ((not r.splt_is1.tlbactive) or spltitlbout.s1finished) = '1' then
v.splt_is1.tlbactive := '0';
v.splt_is1.op.trans_op := '0';
v.splt_is1.op.flush_op := '0';
if v.flush = '1' then
v.flush := '0';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.flush_op := '1';
elsif mmuici.trans_op = '1' then
mmuico_grant := '1';
v.splt_is1.tlbactive := '1';
v.splt_is1.op.trans_op := '1';
end if;
end if;
if spltitlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
fault := spltitlbout.fault;
end if;
if spltdtlbout.transdata.finish = '1' and (r.splt_is2.op.flush_op = '0') then
if (spltdtlbout.fault.fault_mexc or
spltdtlbout.fault.fault_trans or
spltdtlbout.fault.fault_inv or
spltdtlbout.fault.fault_pro or
spltdtlbout.fault.fault_pri or
spltdtlbout.fault.fault_access) = '1' then
fault := spltdtlbout.fault; -- overwrite icache fault
end if;
end if;
if spltitlbout.s1finished = '1' then
v.splt_is2 := r.splt_is1;
end if;
if spltdtlbout.s1finished = '1' then
v.splt_ds2 := r.splt_ds1;
end if;
if ( r.splt_is2.op.flush_op ) = '1' then
mmuico_transdata.finish := '0';
end if;
-- share tw
if two.finish = '1' then
v.twactive := '0';
end if;
if r.twowner = id_icache then
twiv := twi_a(0);
twoi.finish := two.finish;
else
twiv := twi_a(1);
twod.finish := two.finish;
end if;
if (v.twactive) = '0' then
if (twi_a(1).areq_ur or twi_a(1).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_dcache;
elsif (twi_a(0).areq_ur or twi_a(0).walk_op_ur) = '1' then
v.twactive := '1';
v.twowner := id_icache;
end if;
end if;
else
--# combined i/d cache: 1 tlb, 1 tw
-- share one tlb among i and d cache
cmbtlbout := tlbo_a0;
mmuico_grant := '0'; mmudco_grant := '0';
mmuico_transdata.finish := '0'; mmudco_transdata.finish := '0';
twiv := twi_a(0);
twod := two; twoi := two;
twod.finish := '0'; twoi.finish := '0';
-- twod.finish := two.finish;
twoi.finish := two.finish;
if ((not v.cmb_s1.tlbactive) or cmbtlbout.s1finished) = '1' then
v.cmb_s1.tlbactive := '0';
v.cmb_s1.op.trans_op := '0';
v.cmb_s1.op.flush_op := '0';
if (mmudci.trans_op or mmudci.flush_op or mmuici.trans_op) = '1' then
v.cmb_s1.tlbactive := '1';
end if;
if mmuici.trans_op = '1' then
mmuico_grant := '1';
v.cmb_s1.tlbowner := id_icache;
v.cmb_s1.op.trans_op := '1';
elsif mmudci.trans_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.trans_op := '1';
elsif mmudci.flush_op = '1' then
mmudco_grant := '1';
v.cmb_s1.tlbowner := id_dcache;
v.cmb_s1.op.flush_op := '1';
end if;
end if;
if (r.cmb_s1.tlbactive and not r.cmb_s2.tlbactive) = '1' then
end if;
if cmbtlbout.s1finished = '1' then
v.cmb_s2 := r.cmb_s1;
end if;
if r.cmb_s1.tlbowner = id_dcache then
cmbtlbin := mmudci.transdata;
else
cmbtlbin := mmuici.transdata;
end if;
if r.cmb_s2.tlbowner = id_dcache then
mmudco_transdata := cmbtlbout.transdata;
else
mmuico_transdata := cmbtlbout.transdata;
end if;
if cmbtlbout.transdata.finish = '1' and (r.cmb_s2.op.flush_op = '0') then
fault := cmbtlbout.fault;
end if;
end if;
-- # fault status register
if (mmudci.fsread) = '1' then
v.mmctrl2.valid := '0'; v.mmctrl2.fs.fav := '0';
end if;
if (fault.fault_mexc) = '1' then
fs.ft := FS_FT_TRANS;
elsif (fault.fault_trans) = '1' then
fs.ft := FS_FT_INV;
elsif (fault.fault_inv) = '1' then
fs.ft := FS_FT_INV;
elsif (fault.fault_pri) = '1' then
fs.ft := FS_FT_PRI;
elsif (fault.fault_pro) = '1' then
fs.ft := FS_FT_PRO;
elsif (fault.fault_access) = '1' then
fs.ft := FS_FT_BUS;
else
fs.ft := FS_FT_NONE;
end if;
fs.ow := '0';
fs.l := fault.fault_lvl;
if fault.fault_isid = id_dcache then
fs.at_id := '0';
else
fs.at_id := '1';
end if;
fs.at_su := fault.fault_su;
fs.at_ls := not fault.fault_read;
fs.fav := '1';
fs.ebe := (others => '0');
fa := fault.fault_addr(VA_I_U downto VA_I_D);
if (fault.fault_mexc or
fault.fault_trans or
fault.fault_inv or
fault.fault_pro or
fault.fault_pri or
fault.fault_access) = '1' then
--# priority
if v.mmctrl2.valid = '1'then
if (fault.fault_mexc) = '1' then
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
if (r.mmctrl2.fs.ft /= FS_FT_INV) then
if fault.fault_isid = id_dcache then
-- dcache
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
else
-- icache
if (not r.mmctrl2.fs.at_id) = '0' then
fs.ow := '1';
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
end if;
end if;
end if;
end if;
else
v.mmctrl2.fs := fs;
v.mmctrl2.fa := fa;
v.mmctrl2.valid := '1';
end if;
if (fault.fault_isid) = id_dcache then
mmudco_transdata.accexc := '1';
else
mmuico_transdata.accexc := '1';
end if;
end if;
-- # reset
if ( not RESET_ALL ) and ( rst = '0' ) then
if M_TLB_TYPE = 0 then
v.splt_is1.tlbactive := RRES.splt_is1.tlbactive;
v.splt_is2.tlbactive := RRES.splt_is2.tlbactive;
v.splt_ds1.tlbactive := RRES.splt_ds1.tlbactive;
v.splt_ds2.tlbactive := RRES.splt_ds2.tlbactive;
v.splt_is1.op.trans_op := RRES.splt_is1.op.trans_op;
v.splt_is2.op.trans_op := RRES.splt_is2.op.trans_op;
v.splt_ds1.op.trans_op := RRES.splt_ds1.op.trans_op;
v.splt_ds2.op.trans_op := RRES.splt_ds2.op.trans_op;
v.splt_is1.op.flush_op := RRES.splt_is1.op.flush_op;
v.splt_is2.op.flush_op := RRES.splt_is2.op.flush_op;
v.splt_ds1.op.flush_op := RRES.splt_ds1.op.flush_op;
v.splt_ds2.op.flush_op := RRES.splt_ds2.op.flush_op;
else
v.cmb_s1.tlbactive := RRES.cmb_s1.tlbactive;
v.cmb_s2.tlbactive := RRES.cmb_s2.tlbactive;
v.cmb_s1.op.trans_op := RRES.cmb_s1.op.trans_op;
v.cmb_s2.op.trans_op := RRES.cmb_s2.op.trans_op;
v.cmb_s1.op.flush_op := RRES.cmb_s1.op.flush_op;
v.cmb_s2.op.flush_op := RRES.cmb_s2.op.flush_op;
end if;
v.flush := RRES.flush;
v.mmctrl2.valid := RRES.mmctrl2.valid;
v.twactive := RRES.twactive;
v.twowner := RRES.twowner;
end if;
-- drive signals
if M_TLB_TYPE = 0 then
tlbi_a0.trans_op <= r.splt_is1.op.trans_op;
tlbi_a0.flush_op <= r.splt_is1.op.flush_op;
tlbi_a0.transdata <= spltitlbin;
tlbi_a0.s2valid <= r.splt_is2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
tlbi_a1.trans_op <= r.splt_ds1.op.trans_op;
tlbi_a1.flush_op <= r.splt_ds1.op.flush_op;
tlbi_a1.transdata <= spltdtlbin;
tlbi_a1.s2valid <= r.splt_ds2.tlbactive;
tlbi_a1.mmctrl1 <= mmudci.mmctrl1;
tlbi_a1.wb_op <= mmudci.wb_op;
else
tlbi_a0.trans_op <= r.cmb_s1.op.trans_op;
tlbi_a0.flush_op <= r.cmb_s1.op.flush_op;
tlbi_a0.transdata <= cmbtlbin;
tlbi_a0.s2valid <= r.cmb_s2.tlbactive;
tlbi_a0.mmctrl1 <= mmudci.mmctrl1;
tlbi_a0.wb_op <= '0';
end if;
tlbi_a0.testin <= mmudci.testin;
tlbi_a1.testin <= mmudci.testin;
mmudco.transdata <= mmudco_transdata;
mmuico.transdata <= mmuico_transdata;
mmudco.grant <= mmudco_grant;
mmuico.grant <= mmuico_grant;
mmuico.tlbmiss <= twi_a(0).tlbmiss;
mmudco.mmctrl2 <= r.mmctrl2;
mmudco.wbtransdata <= wbtransdata;
twi <= twiv;
two_a(0) <= twoi;
two_a(1) <= twod;
mmctrl1 <= mmudci.mmctrl1;
c <= v;
end process p0;
tlbcomb0: if M_TLB_TYPE = 1 generate
-- i/d tlb
ctlb0 : mmutlb
generic map ( tech, M_ENT_C, 0, tlb_rep, mmupgsz, ramcbits )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0),
ramcclk, ramcin(ramcbits-1 downto 0), ramcout(ramcbits-1 downto 0));
mmudco.tlbmiss <= twi_a(0).tlbmiss;
ramcout(2*ramcbits-1 downto ramcbits) <= (others => '0');
end generate tlbcomb0;
tlbsplit0: if M_TLB_TYPE = 0 generate
-- i tlb
itlb0 : mmutlb
generic map ( tech, M_ENT_I, 0, tlb_rep, mmupgsz, ramcbits )
port map (rst, clk, tlbi_a0, tlbo_a0, two_a(0), twi_a(0),
ramcclk, ramcin(ramcbits-1 downto 0), ramcout(ramcbits-1 downto 0));
-- d tlb
dtlb0 : mmutlb
generic map ( tech, M_ENT_D, tlb_type, tlb_rep, mmupgsz, ramcbits )
port map (rst, clk, tlbi_a1, tlbo_a1, two_a(1), twi_a(1),
ramcclk, ramcin(2*ramcbits-1 downto ramcbits), ramcout(2*ramcbits-1 downto ramcbits));
mmudco.tlbmiss <= twi_a(1).tlbmiss;
end generate tlbsplit0;
-- table walk component
tw0 : mmutw
generic map ( mmupgsz )
port map (rst, clk, mmctrl1, twi, two, mcmmo, mcmmi);
-- pragma translate_off
chk : process
begin
assert not ((M_TLB_TYPE = 1) and (M_TLB_FASTWRITE /= 0)) report
"Fast writebuffer only supported for combined cache"
severity failure;
wait;
end process;
-- pragma translate_on
end rtl;
|
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_hdmi is
port(
clk_125 : in std_logic;
clk_25 : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
active : in std_logic;
rgb : in std_logic_vector(23 downto 0);
tmds : out std_logic_vector(3 downto 0);
tmdsb : out std_logic_vector(3 downto 0);
hdmi_cec : in std_logic;
hdmi_hpd : in std_logic;
hdmi_out_en : out std_logic
);
end zybo_hdmi;
architecture Structural of zybo_hdmi is
signal clk_dvi : std_logic := '0';
signal clk_dvin : std_logic := '0';
signal clk_vga : std_logic := '0';
signal red : std_logic_vector(7 downto 0) := (others => '0');
signal green : std_logic_vector(7 downto 0) := (others => '0');
signal blue : std_logic_vector(7 downto 0) := (others => '0');
signal red_s : std_logic;
signal green_s : std_logic;
signal blue_s : std_logic;
signal clock_s : std_logic;
begin
-- Enable HDMI enable out signal, as stated in reference
hdmi_out_en <= '1';
-- Map rgb in to the separate channels
red <= rgb(23 downto 16);
green <= rgb(15 downto 8);
blue <= rgb(7 downto 0);
-- DVI-D module
DVID : entity work.dvid(Behavioral)
port map(
clk => clk_dvi,
clk_n => clk_dvin,
clk_pixel => clk_vga,
red_p => red,
green_p => green,
blue_p => blue,
video_on => active,
hsync => hsync,
vsync => vsync,
-- outputs to TMDS drivers
red_serial => red_s,
green_serial => green_s,
blue_serial => blue_s,
clock_serial => clock_s
);
OBUFDS_blue : OBUFDS PORT MAP ( O => TMDS(0), OB => TMDSB(0), I => blue_s );
OBUFDS_red : OBUFDS PORT MAP ( O => TMDS(1), OB => TMDSB(1), I => green_s );
OBUFDS_green : OBUFDS PORT MAP ( O => TMDS(2), OB => TMDSB(2), I => red_s );
OBUFDS_clock : OBUFDS PORT MAP ( O => TMDS(3), OB => TMDSB(3), I => clock_s );
clk_dvi <= clk_125; -- DVI clk (pos)
clk_dvin <= not clk_125; -- DVI clk (neg)
clk_vga <= clk_25; -- VGA clk
end Structural; |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_hdmi is
port(
clk_125 : in std_logic;
clk_25 : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
active : in std_logic;
rgb : in std_logic_vector(23 downto 0);
tmds : out std_logic_vector(3 downto 0);
tmdsb : out std_logic_vector(3 downto 0);
hdmi_cec : in std_logic;
hdmi_hpd : in std_logic;
hdmi_out_en : out std_logic
);
end zybo_hdmi;
architecture Structural of zybo_hdmi is
signal clk_dvi : std_logic := '0';
signal clk_dvin : std_logic := '0';
signal clk_vga : std_logic := '0';
signal red : std_logic_vector(7 downto 0) := (others => '0');
signal green : std_logic_vector(7 downto 0) := (others => '0');
signal blue : std_logic_vector(7 downto 0) := (others => '0');
signal red_s : std_logic;
signal green_s : std_logic;
signal blue_s : std_logic;
signal clock_s : std_logic;
begin
-- Enable HDMI enable out signal, as stated in reference
hdmi_out_en <= '1';
-- Map rgb in to the separate channels
red <= rgb(23 downto 16);
green <= rgb(15 downto 8);
blue <= rgb(7 downto 0);
-- DVI-D module
DVID : entity work.dvid(Behavioral)
port map(
clk => clk_dvi,
clk_n => clk_dvin,
clk_pixel => clk_vga,
red_p => red,
green_p => green,
blue_p => blue,
video_on => active,
hsync => hsync,
vsync => vsync,
-- outputs to TMDS drivers
red_serial => red_s,
green_serial => green_s,
blue_serial => blue_s,
clock_serial => clock_s
);
OBUFDS_blue : OBUFDS PORT MAP ( O => TMDS(0), OB => TMDSB(0), I => blue_s );
OBUFDS_red : OBUFDS PORT MAP ( O => TMDS(1), OB => TMDSB(1), I => green_s );
OBUFDS_green : OBUFDS PORT MAP ( O => TMDS(2), OB => TMDSB(2), I => red_s );
OBUFDS_clock : OBUFDS PORT MAP ( O => TMDS(3), OB => TMDSB(3), I => clock_s );
clk_dvi <= clk_125; -- DVI clk (pos)
clk_dvin <= not clk_125; -- DVI clk (neg)
clk_vga <= clk_25; -- VGA clk
end Structural; |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_hdmi is
port(
clk_125 : in std_logic;
clk_25 : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
active : in std_logic;
rgb : in std_logic_vector(23 downto 0);
tmds : out std_logic_vector(3 downto 0);
tmdsb : out std_logic_vector(3 downto 0);
hdmi_cec : in std_logic;
hdmi_hpd : in std_logic;
hdmi_out_en : out std_logic
);
end zybo_hdmi;
architecture Structural of zybo_hdmi is
signal clk_dvi : std_logic := '0';
signal clk_dvin : std_logic := '0';
signal clk_vga : std_logic := '0';
signal red : std_logic_vector(7 downto 0) := (others => '0');
signal green : std_logic_vector(7 downto 0) := (others => '0');
signal blue : std_logic_vector(7 downto 0) := (others => '0');
signal red_s : std_logic;
signal green_s : std_logic;
signal blue_s : std_logic;
signal clock_s : std_logic;
begin
-- Enable HDMI enable out signal, as stated in reference
hdmi_out_en <= '1';
-- Map rgb in to the separate channels
red <= rgb(23 downto 16);
green <= rgb(15 downto 8);
blue <= rgb(7 downto 0);
-- DVI-D module
DVID : entity work.dvid(Behavioral)
port map(
clk => clk_dvi,
clk_n => clk_dvin,
clk_pixel => clk_vga,
red_p => red,
green_p => green,
blue_p => blue,
video_on => active,
hsync => hsync,
vsync => vsync,
-- outputs to TMDS drivers
red_serial => red_s,
green_serial => green_s,
blue_serial => blue_s,
clock_serial => clock_s
);
OBUFDS_blue : OBUFDS PORT MAP ( O => TMDS(0), OB => TMDSB(0), I => blue_s );
OBUFDS_red : OBUFDS PORT MAP ( O => TMDS(1), OB => TMDSB(1), I => green_s );
OBUFDS_green : OBUFDS PORT MAP ( O => TMDS(2), OB => TMDSB(2), I => red_s );
OBUFDS_clock : OBUFDS PORT MAP ( O => TMDS(3), OB => TMDSB(3), I => clock_s );
clk_dvi <= clk_125; -- DVI clk (pos)
clk_dvin <= not clk_125; -- DVI clk (neg)
clk_vga <= clk_25; -- VGA clk
end Structural; |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_hdmi is
port(
clk_125 : in std_logic;
clk_25 : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
active : in std_logic;
rgb : in std_logic_vector(23 downto 0);
tmds : out std_logic_vector(3 downto 0);
tmdsb : out std_logic_vector(3 downto 0);
hdmi_cec : in std_logic;
hdmi_hpd : in std_logic;
hdmi_out_en : out std_logic
);
end zybo_hdmi;
architecture Structural of zybo_hdmi is
signal clk_dvi : std_logic := '0';
signal clk_dvin : std_logic := '0';
signal clk_vga : std_logic := '0';
signal red : std_logic_vector(7 downto 0) := (others => '0');
signal green : std_logic_vector(7 downto 0) := (others => '0');
signal blue : std_logic_vector(7 downto 0) := (others => '0');
signal red_s : std_logic;
signal green_s : std_logic;
signal blue_s : std_logic;
signal clock_s : std_logic;
begin
-- Enable HDMI enable out signal, as stated in reference
hdmi_out_en <= '1';
-- Map rgb in to the separate channels
red <= rgb(23 downto 16);
green <= rgb(15 downto 8);
blue <= rgb(7 downto 0);
-- DVI-D module
DVID : entity work.dvid(Behavioral)
port map(
clk => clk_dvi,
clk_n => clk_dvin,
clk_pixel => clk_vga,
red_p => red,
green_p => green,
blue_p => blue,
video_on => active,
hsync => hsync,
vsync => vsync,
-- outputs to TMDS drivers
red_serial => red_s,
green_serial => green_s,
blue_serial => blue_s,
clock_serial => clock_s
);
OBUFDS_blue : OBUFDS PORT MAP ( O => TMDS(0), OB => TMDSB(0), I => blue_s );
OBUFDS_red : OBUFDS PORT MAP ( O => TMDS(1), OB => TMDSB(1), I => green_s );
OBUFDS_green : OBUFDS PORT MAP ( O => TMDS(2), OB => TMDSB(2), I => red_s );
OBUFDS_clock : OBUFDS PORT MAP ( O => TMDS(3), OB => TMDSB(3), I => clock_s );
clk_dvi <= clk_125; -- DVI clk (pos)
clk_dvin <= not clk_125; -- DVI clk (neg)
clk_vga <= clk_25; -- VGA clk
end Structural; |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_hdmi is
port(
clk_125 : in std_logic;
clk_25 : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
active : in std_logic;
rgb : in std_logic_vector(23 downto 0);
tmds : out std_logic_vector(3 downto 0);
tmdsb : out std_logic_vector(3 downto 0);
hdmi_cec : in std_logic;
hdmi_hpd : in std_logic;
hdmi_out_en : out std_logic
);
end zybo_hdmi;
architecture Structural of zybo_hdmi is
signal clk_dvi : std_logic := '0';
signal clk_dvin : std_logic := '0';
signal clk_vga : std_logic := '0';
signal red : std_logic_vector(7 downto 0) := (others => '0');
signal green : std_logic_vector(7 downto 0) := (others => '0');
signal blue : std_logic_vector(7 downto 0) := (others => '0');
signal red_s : std_logic;
signal green_s : std_logic;
signal blue_s : std_logic;
signal clock_s : std_logic;
begin
-- Enable HDMI enable out signal, as stated in reference
hdmi_out_en <= '1';
-- Map rgb in to the separate channels
red <= rgb(23 downto 16);
green <= rgb(15 downto 8);
blue <= rgb(7 downto 0);
-- DVI-D module
DVID : entity work.dvid(Behavioral)
port map(
clk => clk_dvi,
clk_n => clk_dvin,
clk_pixel => clk_vga,
red_p => red,
green_p => green,
blue_p => blue,
video_on => active,
hsync => hsync,
vsync => vsync,
-- outputs to TMDS drivers
red_serial => red_s,
green_serial => green_s,
blue_serial => blue_s,
clock_serial => clock_s
);
OBUFDS_blue : OBUFDS PORT MAP ( O => TMDS(0), OB => TMDSB(0), I => blue_s );
OBUFDS_red : OBUFDS PORT MAP ( O => TMDS(1), OB => TMDSB(1), I => green_s );
OBUFDS_green : OBUFDS PORT MAP ( O => TMDS(2), OB => TMDSB(2), I => red_s );
OBUFDS_clock : OBUFDS PORT MAP ( O => TMDS(3), OB => TMDSB(3), I => clock_s );
clk_dvi <= clk_125; -- DVI clk (pos)
clk_dvin <= not clk_125; -- DVI clk (neg)
clk_vga <= clk_25; -- VGA clk
end Structural; |
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.VCOMPONENTS.ALL;
entity zybo_hdmi is
port(
clk_125 : in std_logic;
clk_25 : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
active : in std_logic;
rgb : in std_logic_vector(23 downto 0);
tmds : out std_logic_vector(3 downto 0);
tmdsb : out std_logic_vector(3 downto 0);
hdmi_cec : in std_logic;
hdmi_hpd : in std_logic;
hdmi_out_en : out std_logic
);
end zybo_hdmi;
architecture Structural of zybo_hdmi is
signal clk_dvi : std_logic := '0';
signal clk_dvin : std_logic := '0';
signal clk_vga : std_logic := '0';
signal red : std_logic_vector(7 downto 0) := (others => '0');
signal green : std_logic_vector(7 downto 0) := (others => '0');
signal blue : std_logic_vector(7 downto 0) := (others => '0');
signal red_s : std_logic;
signal green_s : std_logic;
signal blue_s : std_logic;
signal clock_s : std_logic;
begin
-- Enable HDMI enable out signal, as stated in reference
hdmi_out_en <= '1';
-- Map rgb in to the separate channels
red <= rgb(23 downto 16);
green <= rgb(15 downto 8);
blue <= rgb(7 downto 0);
-- DVI-D module
DVID : entity work.dvid(Behavioral)
port map(
clk => clk_dvi,
clk_n => clk_dvin,
clk_pixel => clk_vga,
red_p => red,
green_p => green,
blue_p => blue,
video_on => active,
hsync => hsync,
vsync => vsync,
-- outputs to TMDS drivers
red_serial => red_s,
green_serial => green_s,
blue_serial => blue_s,
clock_serial => clock_s
);
OBUFDS_blue : OBUFDS PORT MAP ( O => TMDS(0), OB => TMDSB(0), I => blue_s );
OBUFDS_red : OBUFDS PORT MAP ( O => TMDS(1), OB => TMDSB(1), I => green_s );
OBUFDS_green : OBUFDS PORT MAP ( O => TMDS(2), OB => TMDSB(2), I => red_s );
OBUFDS_clock : OBUFDS PORT MAP ( O => TMDS(3), OB => TMDSB(3), I => clock_s );
clk_dvi <= clk_125; -- DVI clk (pos)
clk_dvin <= not clk_125; -- DVI clk (neg)
clk_vga <= clk_25; -- VGA clk
end Structural; |
-------------------------------------------------------------------------------
--! @file alteraOpenmacTop-rtl-ea.vhd
--
--! @brief OpenMAC toplevel for Altera
--
--! @details This is the openMAC toplevel for Altera platform.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
--! use openmac package
use work.openmacPkg.all;
entity alteraOpenmacTop is
generic (
-----------------------------------------------------------------------
-- Phy configuration
-----------------------------------------------------------------------
--! Number of Phy ports
gPhyPortCount : natural := 2;
--! Phy port interface type (Rmii or Mii)
gPhyPortType : natural := cPhyPortRmii;
--! Number of SMI phy ports
gSmiPortCount : natural := 1;
-----------------------------------------------------------------------
-- General configuration
-----------------------------------------------------------------------
--! Endianness ("little" or "big")
gEndianness : string := "little";
--! Enable packet activity generator (e.g. connect to LED)
gEnableActivity : natural := cFalse;
--! Enable DMA observer circuit
gEnableDmaObserver : natural := cFalse;
-----------------------------------------------------------------------
-- DMA configuration
-----------------------------------------------------------------------
--! DMA address width (byte-addressing)
gDmaAddrWidth : natural := 32;
--! DMA data width
gDmaDataWidth : natural := 16;
--! DMA burst count width
gDmaBurstCountWidth : natural := 4;
--! DMA write burst length (Rx packets) [words]
gDmaWriteBurstLength : natural := 16;
--! DMA read burst length (Tx packets) [words]
gDmaReadBurstLength : natural := 16;
--! DMA write FIFO length (Rx packets) [words]
gDmaWriteFifoLength : natural := 16;
--! DMA read FIFO length (Tx packets) [words]
gDmaReadFifoLength : natural := 16;
-----------------------------------------------------------------------
-- Packet buffer configuration
-----------------------------------------------------------------------
--! Packet buffer location for Tx packets
gPacketBufferLocTx : natural := cPktBufLocal;
--! Packet buffer location for Rx packets
gPacketBufferLocRx : natural := cPktBufLocal;
--! Packet buffer log2(size) [log2(bytes)]
gPacketBufferLog2Size : natural := 10;
-----------------------------------------------------------------------
-- MAC timer configuration
-----------------------------------------------------------------------
--! Number of timers
gTimerCount : natural := 2;
--! Enable timer pulse width control
gTimerEnablePulseWidth : natural := cFalse;
--! Timer pulse width register width
gTimerPulseRegWidth : natural := 10
);
port (
-----------------------------------------------------------------------
-- Clock and reset signal pairs
-----------------------------------------------------------------------
--! Main clock used for openMAC, openHUB and openFILTER (freq = 50 MHz)
csi_mainClk_clock : in std_logic;
--! Main reset used for openMAC, openHUB and openFILTER
rsi_mainRst_reset : in std_logic;
--! DMA master clock
csi_dmaClk_clock : in std_logic;
--! DMA master reset
rsi_dmaRst_reset : in std_logic;
--! Packet buffer clock
csi_pktClk_clock : in std_logic;
--! Packet buffer reset
rsi_pktRst_reset : in std_logic;
--! Twice main clock used for Rmii Tx path
csi_mainClkx2_clock : in std_logic;
-----------------------------------------------------------------------
-- MAC REG memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC REGISTER chipselect
avs_macReg_chipselect : in std_logic;
--! MM slave MAC REGISTER write
avs_macReg_write : in std_logic;
--! MM slave MAC REGISTER read
avs_macReg_read : in std_logic;
--! MM slave MAC REGISTER waitrequest
avs_macReg_waitrequest : out std_logic;
--! MM slave MAC REGISTER byteenable
avs_macReg_byteenable : in std_logic_vector(cMacRegDataWidth/cByteLength-1 downto 0);
--! MM slave MAC REGISTER address
avs_macReg_address : in std_logic_vector(cMacRegAddrWidth-1 downto 1);
--! MM slave MAC REGISTER writedata
avs_macReg_writedata : in std_logic_vector(cMacRegDataWidth-1 downto 0);
--! MM slave MAC REGISTER readdata
avs_macReg_readdata : out std_logic_vector(cMacRegDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC TIMER memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC TIMER chipselect
avs_macTimer_chipselect : in std_logic;
--! MM slave MAC TIMER write
avs_macTimer_write : in std_logic;
--! MM slave MAC TIMER read
avs_macTimer_read : in std_logic;
--! MM slave MAC TIMER waitrequest
avs_macTimer_waitrequest : out std_logic;
--! MM slave MAC TIMER address
avs_macTimer_address : in std_logic_vector(cMacTimerAddrWidth-1 downto 2);
--! MM slave MAC TIMER writedata
avs_macTimer_writedata : in std_logic_vector(cMacTimerDataWidth-1 downto 0);
--! MM slave MAC TIMER readdata
avs_macTimer_readdata : out std_logic_vector(cMacTimerDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC PACKET BUFFER memory mapped slave
-----------------------------------------------------------------------
--! MM slave MAC PACKET BUFFER chipselect
avs_pktBuf_chipselect : in std_logic;
--! MM slave MAC PACKET BUFFER write
avs_pktBuf_write : in std_logic;
--! MM slave MAC PACKET BUFFER read
avs_pktBuf_read : in std_logic;
--! MM slave MAC PACKET BUFFER waitrequest
avs_pktBuf_waitrequest : out std_logic;
--! MM slave MAC PACKET BUFFER byteenable
avs_pktBuf_byteenable : in std_logic_vector(cPktBufDataWidth/8-1 downto 0);
--! MM slave MAC PACKET BUFFER address (width given by gPacketBufferLog2Size)
avs_pktBuf_address : in std_logic_vector(gPacketBufferLog2Size-1 downto 2);
--! MM slave MAC PACKET BUFFER writedata
avs_pktBuf_writedata : in std_logic_vector(cPktBufDataWidth-1 downto 0);
--! MM slave MAC PACKET BUFFER readdata
avs_pktBuf_readdata : out std_logic_vector(cPktBufDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- MAC DMA memory mapped master
-----------------------------------------------------------------------
--! MM master MAC DMA write
avm_dma_write : out std_logic;
--! MM master MAC DMA read
avm_dma_read : out std_logic;
--! MM master MAC DMA waitrequest
avm_dma_waitrequest : in std_logic;
--! MM master MAC DMA readdatavalid
avm_dma_readdatavalid : in std_logic;
--! MM master MAC DMA byteenable
avm_dma_byteenable : out std_logic_vector(gDmaDataWidth/8-1 downto 0);
--! MM master MAC DMA address
avm_dma_address : out std_logic_vector(gDmaAddrWidth-1 downto 0);
--! MM master MAC DMA burstcount
avm_dma_burstcount : out std_logic_vector(gDmaBurstCountWidth-1 downto 0);
--! MM master MAC DMA writedata
avm_dma_writedata : out std_logic_vector(gDmaDataWidth-1 downto 0);
--! MM master MAC DMA readdata
avm_dma_readdata : in std_logic_vector(gDmaDataWidth-1 downto 0);
-----------------------------------------------------------------------
-- Interrupts
-----------------------------------------------------------------------
--! MAC TIMER interrupt
ins_timerIrq_irq : out std_logic;
--! MAC interrupt
ins_macIrq_irq : out std_logic;
-----------------------------------------------------------------------
-- Rmii Phy ports
-----------------------------------------------------------------------
--! Rmii Rx data valid ports
coe_rmii_rxDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Rx data ports
coe_rmii_rxData : in std_logic_vector(gPhyPortCount*2-1 downto 0);
--! Rmii Rx error ports
coe_rmii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx enable ports
coe_rmii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Rmii Tx data ports
coe_rmii_txData : out std_logic_vector(gPhyPortCount*2-1 downto 0);
-----------------------------------------------------------------------
-- Mii Phy ports
-----------------------------------------------------------------------
--! Mii Rx data valid ports
coe_mii_rxDataValid : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx data ports
coe_mii_rxData : in std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Rx error ports
coe_mii_rxError : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Rx Clocks
coe_mii_rxClk : in std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx enable ports
coe_mii_txEnable : out std_logic_vector(gPhyPortCount-1 downto 0);
--! Mii Tx data ports
coe_mii_txData : out std_logic_vector(gPhyPortCount*4-1 downto 0);
--! Mii Tx Clocks
coe_mii_txClk : in std_logic_vector(gPhyPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Phy management interface
-----------------------------------------------------------------------
--! Phy reset (low-active)
coe_smi_nPhyRst : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI clock
coe_smi_clk : out std_logic_vector(gSmiPortCount-1 downto 0);
--! SMI data I/OI (tri-state buffer)
coe_smi_dio : inout std_logic_vector(gSmiPortCount-1 downto 0);
-----------------------------------------------------------------------
-- Other ports
-----------------------------------------------------------------------
--! Packet activity (enabled with gEnableActivity)
coe_pktActivity : out std_logic;
--! MAC TIMER outputs
coe_macTimerOut : out std_logic_vector(gTimerCount-1 downto 0)
);
end alteraOpenmacTop;
architecture rtl of alteraOpenmacTop is
--! Byte address of macReg
signal macReg_address : std_logic_vector(avs_macReg_address'left downto 0);
--! Byte address of macTimer
signal macTimer_address : std_logic_vector(avs_macTimer_address'left downto 0);
--! Byte address of pktBuf
signal pktBuf_address : std_logic_vector(avs_pktBuf_address'left downto 0);
--! Mac Tx interrupt
signal macTx_interrupt : std_logic;
--! Mac Rx interrupt
signal macRx_interrupt : std_logic;
--! Rmii Tx path
signal rmiiTx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Rmii Rx path
signal rmiiRx : tRmiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Tx path
signal miiTx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Mii Rx path
signal miiRx : tMiiPathArray(gPhyPortCount-1 downto 0);
--! Smi tri-state-buffer input
signal smi_data_in : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output
signal smi_data_out : std_logic_vector(gSmiPortCount-1 downto 0);
--! Smi tri-state-buffer output enable
signal smi_data_outEnable : std_logic;
begin
---------------------------------------------------------------------------
-- Map outputs
---------------------------------------------------------------------------
-- Mac interrupts are or'd to single line.
ins_macIrq_irq <= macTx_interrupt or macRx_interrupt;
-- Phy Tx path
rmiiPathArrayToStdLogicVector(
iVector => rmiiTx,
oEnable => coe_rmii_txEnable,
oData => coe_rmii_txData
);
miiPathArrayToStdLogicVector(
iVector => miiTx,
oEnable => coe_mii_txEnable,
oData => coe_mii_txData
);
---------------------------------------------------------------------------
-- Map inputs
---------------------------------------------------------------------------
-- Assign byte addresses.
macReg_address <= avs_macReg_address & "0"; --word to byte
macTimer_address <= avs_macTimer_address & "00"; --dword to byte
pktBuf_address <= avs_pktBuf_address & "00"; --dword to byte
-- Phy Rx path
stdLogicVectorToRmiiPathArray(
iEnable => coe_rmii_rxDataValid,
iData => coe_rmii_rxData,
oVector => rmiiRx
);
stdLogicVectorToMiiPathArray(
iEnable => coe_mii_rxDataValid,
iData => coe_mii_rxData,
oVector => miiRx
);
---------------------------------------------------------------------------
-- Map IOs
---------------------------------------------------------------------------
-- Assign SMI IO buffers
coe_smi_dio <= smi_data_out when smi_data_outEnable = cActivated else
(others => 'Z');
-- Simply assign the input vector.
smi_data_in <= coe_smi_dio;
--! This is the openMAC toplevel instantiation.
THEOPENMACTOP : entity work.openmacTop
generic map (
gPhyPortCount => gPhyPortCount,
gPhyPortType => gPhyPortType,
gSmiPortCount => gSmiPortCount,
gEndianness => gEndianness,
gEnableActivity => gEnableActivity,
gEnableDmaObserver => gEnableDmaObserver,
gDmaAddrWidth => gDmaAddrWidth,
gDmaDataWidth => gDmaDataWidth,
gDmaBurstCountWidth => gDmaBurstCountWidth,
gDmaWriteBurstLength => gDmaWriteBurstLength,
gDmaReadBurstLength => gDmaReadBurstLength,
gDmaWriteFifoLength => gDmaWriteFifoLength,
gDmaReadFifoLength => gDmaReadFifoLength,
gPacketBufferLocTx => gPacketBufferLocTx,
gPacketBufferLocRx => gPacketBufferLocRx,
gPacketBufferLog2Size => gPacketBufferLog2Size,
gTimerCount => gTimerCount,
gTimerEnablePulseWidth => gTimerEnablePulseWidth,
gTimerPulseRegWidth => gTimerPulseRegWidth
)
port map (
iClk => csi_mainClk_clock,
iRst => rsi_mainRst_reset,
iDmaClk => csi_dmaClk_clock,
iDmaRst => rsi_dmaRst_reset,
iPktBufClk => csi_pktClk_clock,
iPktBufRst => rsi_pktRst_reset,
iClk2x => csi_mainClkx2_clock,
iMacReg_chipselect => avs_macReg_chipselect,
iMacReg_write => avs_macReg_write,
iMacReg_read => avs_macReg_read,
oMacReg_waitrequest => avs_macReg_waitrequest,
iMacReg_byteenable => avs_macReg_byteenable,
iMacReg_address => macReg_address,
iMacReg_writedata => avs_macReg_writedata,
oMacReg_readdata => avs_macReg_readdata,
iMacTimer_chipselect => avs_macTimer_chipselect,
iMacTimer_write => avs_macTimer_write,
iMacTimer_read => avs_macTimer_read,
oMacTimer_waitrequest => avs_macTimer_waitrequest,
iMacTimer_address => macTimer_address,
iMacTimer_writedata => avs_macTimer_writedata,
oMacTimer_readdata => avs_macTimer_readdata,
iPktBuf_chipselect => avs_pktBuf_chipselect,
iPktBuf_write => avs_pktBuf_write,
iPktBuf_read => avs_pktBuf_read,
oPktBuf_waitrequest => avs_pktBuf_waitrequest,
iPktBuf_byteenable => avs_pktBuf_byteenable,
iPktBuf_address => pktBuf_address,
iPktBuf_writedata => avs_pktBuf_writedata,
oPktBuf_readdata => avs_pktBuf_readdata,
oDma_write => avm_dma_write,
oDma_read => avm_dma_read,
iDma_waitrequest => avm_dma_waitrequest,
iDma_readdatavalid => avm_dma_readdatavalid,
oDma_byteenable => avm_dma_byteenable,
oDma_address => avm_dma_address,
oDma_burstcount => avm_dma_burstcount,
oDma_burstcounter => open, --current burst counter state unused
oDma_writedata => avm_dma_writedata,
iDma_readdata => avm_dma_readdata,
oMacTimer_interrupt => ins_timerIrq_irq,
oMacTx_interrupt => macTx_interrupt,
oMacRx_interrupt => macRx_interrupt,
iRmii_Rx => rmiiRx,
iRmii_RxError => coe_rmii_rxError,
oRmii_Tx => rmiiTx,
iMii_Rx => miiRx,
iMii_RxError => coe_mii_rxError,
iMii_RxClk => coe_mii_rxClk,
oMii_Tx => miiTx,
iMii_TxClk => coe_mii_txClk,
onPhy_reset => coe_smi_nPhyRst,
oSmi_clk => coe_smi_clk,
oSmi_data_outEnable => smi_data_outEnable,
oSmi_data_out => smi_data_out,
iSmi_data_in => smi_data_in,
oActivity => coe_pktActivity,
oMacTimer => coe_macTimerOut
);
end rtl;
|
architecture rtl of fifo is
begin
x <= a AND b OR c NAND d NOR e XOR f XNOR g;
x <= a AND b OR c NAND d NOR e XOR f XNOR g;
end architecture;
|
------------------------------------------------------------------------------------------------------------------------
-- Model Title: Hall sensor
-- Entity Name: hall_sensor
-- Author: <[email protected]>
-- Created:
-- Last update: 2020/07/08 Schaeftlarn
--
------------------------------------------------------------------------------------------------------------------------
-- Description: small signal model of Hall sensor: Vh == Binput*Rh*Ic/d
-- simulated with systemvision.com
--
-- SMD HS-420 Datasheet:
-- Magnetic sensitivity: VH=100…330 mV/kG at Ic=5mA => -(2...6.6) mV/T/mA
-- input resistance: Rin=240...550 Ohm
-- output resistance: Rout=240...550 Ohm
-- control current: Ic max=20 mA / Ic nom=5 mA
-- operating temperature range: -40...110 degC
-- meaning of temperature coefficient of resistance (0...40 degC): -1.8
-- meaning of temperature coefficient of VH (0...40 degC): -1.8
--
-- Indium Antimonide:
-- Rh= -7.2e-4 m3/C; d=0.4 mm => Magnetic sensitivity: VH=Rh*Ic/d= -1.8 mV/T/mA
--
------------------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.electrical_systems.all;
use IEEE.energy_systems.all;
entity hall_sensor is
generic (key : real := 1.0); -- key [no units]
port (quantity Binput: in real;
terminal e_ic1, e_ic2: electrical;
terminal e_vh1, e_vh2: electrical);
end entity hall_sensor;
architecture basic of hall_sensor is
quantity vc across ic through e_ic1 to e_ic2;
quantity vh across ih through e_vh1 to e_vh2;
-------
-- model parameters
constant Rin:real:= 400.0; -- input resistance: Rin, Ohm
constant Rh:real:= -7.2e-4; -- Indium Antimonide Rh
constant d:real:= 0.4e-3; -- thickness, d
begin
vc == Rin*ic;
vh == Binput*Rh*ic/d;
--- for information only
--VH == Rh*ic/d; -- magnetic sensitivity
end architecture basic;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity idctbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(8 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(8 downto 0);
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end idctbuff;
architecture augh of idctbuff is
-- Embedded RAM
type ram_type is array (0 to 383) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra1_data <= ram( to_integer(ra1_addr) ) when to_integer(ra1_addr) < 384 else (others => '-');
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 384 else (others => '-');
ra2_data <= ram( to_integer(ra2_addr) ) when to_integer(ra2_addr) < 384 else (others => '-');
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity idctbuff is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(8 downto 0);
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(8 downto 0);
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end idctbuff;
architecture augh of idctbuff is
-- Embedded RAM
type ram_type is array (0 to 383) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra1_data <= ram( to_integer(ra1_addr) ) when to_integer(ra1_addr) < 384 else (others => '-');
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 384 else (others => '-');
ra2_data <= ram( to_integer(ra2_addr) ) when to_integer(ra2_addr) < 384 else (others => '-');
end architecture;
|
--
-- Taken from rtl/commonlib/types_util.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Package for common testbenches implementation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
package types_util is
function strlen(s: in string) return integer;
function StringToUVector(inStr: string) return std_ulogic_vector;
function StringToSVector(inStr: string) return std_logic_vector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector) return std_logic_vector;
function SignalFromString(inStr: string; ind : integer ) return std_logic;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector;
function tost(v:std_logic_vector) return string;
function tost(v:std_logic) return string;
function tost(i : integer) return string;
procedure print(s : string);
end;
package body types_util is
function strlen(s: in string) return integer is
variable n: integer:=0; variable sj: integer:=s'left;
begin
loop
if sj>s'right then exit;
elsif s(sj)=NUL then exit; --sequential if protects sj > length
else sj:=sj+1; n:=n+1;
end if;
end loop;
return n;
end strlen;
function SignalFromString(inStr: string; ind : integer ) return std_logic is
variable temp: std_logic := 'X';
begin
if(inStr(inStr'high-ind)='1') then temp := '1';
elsif(inStr(inStr'high-ind)='0') then temp := '0';
end if;
return temp;
end function SignalFromString;
function StringToUVector(inStr: string) return std_ulogic_vector is
variable temp: std_ulogic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToUVector;
-- conversion function
function StringToSVector(inStr: string) return std_logic_vector is
variable temp: std_logic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToSVector;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector is
constant ss: string(1 to inStr'length) := inStr;
variable c : integer;
variable temp: std_logic_vector(7 downto 0) := (others => 'X');
begin
c := character'pos(ss(idx+1));
for i in 0 to 7 loop --
temp(i) := to_unsigned(c,8)(i);
end loop;
return temp;
end function SymbolToSVector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector)
return std_logic_vector is
variable temp: std_logic_vector(inUnsigned'length-1 downto 0) := (others => 'X');
variable i: integer:=0;
begin
while i < inUnsigned'length loop
if(inUnsigned(i)='1') then temp(i) := '1';
elsif(inUnsigned(i)='0') then temp(i) := '0';
end if;
i := i+1;
end loop;
return temp;
end function UnsignedToSigned;
subtype nibble is std_logic_vector(3 downto 0);
function todec(i:integer) return character is
begin
case i is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when others => return('0');
end case;
end;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
function tost(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(0 to slen*4-1) := (others => '0');
variable s : string(1 to slen);
variable nz : boolean := false;
variable index : integer := -1;
variable vector : bit_vector(0 TO 7);
alias reverse_vector : bit_vector
( vector'length DOWNTO 1 )
IS vector ;
begin
vv(slen*4-vlen to slen*4-1) := v;
for i in 0 to slen-1 loop
if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then
index := i;
else
nz := false;
s(i+1) := tohex(vv(i*4 to i*4+3));
end if;
end loop;
if ((index +2) = slen) then return(s(slen to slen));
else return(string'("0x") & s(index+2 to slen)); end if; --'
end;
function tost(v:std_logic) return string is
begin
if to_x01(v) = '1' then return("1"); else return("0"); end if;
end;
function tost(i : integer) return string is
variable L : line;
variable s, x : string(1 to 128);
variable n, tmp : integer := 0;
begin
tmp := i;
if i < 0 then tmp := -i; end if;
loop
s(128-n) := todec(tmp mod 10);
tmp := tmp / 10;
n := n+1;
if tmp = 0 then exit; end if;
end loop;
x(1 to n) := s(129-n to 128);
if i < 0 then return "-" & x(1 to n); end if;
return(x(1 to n));
end;
procedure print(s : string) is
variable L : line;
begin
L := new string'(s); writeline(output, L);
end;
end;
|
--
-- Taken from rtl/commonlib/types_util.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Package for common testbenches implementation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
package types_util is
function strlen(s: in string) return integer;
function StringToUVector(inStr: string) return std_ulogic_vector;
function StringToSVector(inStr: string) return std_logic_vector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector) return std_logic_vector;
function SignalFromString(inStr: string; ind : integer ) return std_logic;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector;
function tost(v:std_logic_vector) return string;
function tost(v:std_logic) return string;
function tost(i : integer) return string;
procedure print(s : string);
end;
package body types_util is
function strlen(s: in string) return integer is
variable n: integer:=0; variable sj: integer:=s'left;
begin
loop
if sj>s'right then exit;
elsif s(sj)=NUL then exit; --sequential if protects sj > length
else sj:=sj+1; n:=n+1;
end if;
end loop;
return n;
end strlen;
function SignalFromString(inStr: string; ind : integer ) return std_logic is
variable temp: std_logic := 'X';
begin
if(inStr(inStr'high-ind)='1') then temp := '1';
elsif(inStr(inStr'high-ind)='0') then temp := '0';
end if;
return temp;
end function SignalFromString;
function StringToUVector(inStr: string) return std_ulogic_vector is
variable temp: std_ulogic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToUVector;
-- conversion function
function StringToSVector(inStr: string) return std_logic_vector is
variable temp: std_logic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToSVector;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector is
constant ss: string(1 to inStr'length) := inStr;
variable c : integer;
variable temp: std_logic_vector(7 downto 0) := (others => 'X');
begin
c := character'pos(ss(idx+1));
for i in 0 to 7 loop --
temp(i) := to_unsigned(c,8)(i);
end loop;
return temp;
end function SymbolToSVector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector)
return std_logic_vector is
variable temp: std_logic_vector(inUnsigned'length-1 downto 0) := (others => 'X');
variable i: integer:=0;
begin
while i < inUnsigned'length loop
if(inUnsigned(i)='1') then temp(i) := '1';
elsif(inUnsigned(i)='0') then temp(i) := '0';
end if;
i := i+1;
end loop;
return temp;
end function UnsignedToSigned;
subtype nibble is std_logic_vector(3 downto 0);
function todec(i:integer) return character is
begin
case i is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when others => return('0');
end case;
end;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
function tost(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(0 to slen*4-1) := (others => '0');
variable s : string(1 to slen);
variable nz : boolean := false;
variable index : integer := -1;
variable vector : bit_vector(0 TO 7);
alias reverse_vector : bit_vector
( vector'length DOWNTO 1 )
IS vector ;
begin
vv(slen*4-vlen to slen*4-1) := v;
for i in 0 to slen-1 loop
if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then
index := i;
else
nz := false;
s(i+1) := tohex(vv(i*4 to i*4+3));
end if;
end loop;
if ((index +2) = slen) then return(s(slen to slen));
else return(string'("0x") & s(index+2 to slen)); end if; --'
end;
function tost(v:std_logic) return string is
begin
if to_x01(v) = '1' then return("1"); else return("0"); end if;
end;
function tost(i : integer) return string is
variable L : line;
variable s, x : string(1 to 128);
variable n, tmp : integer := 0;
begin
tmp := i;
if i < 0 then tmp := -i; end if;
loop
s(128-n) := todec(tmp mod 10);
tmp := tmp / 10;
n := n+1;
if tmp = 0 then exit; end if;
end loop;
x(1 to n) := s(129-n to 128);
if i < 0 then return "-" & x(1 to n); end if;
return(x(1 to n));
end;
procedure print(s : string) is
variable L : line;
begin
L := new string'(s); writeline(output, L);
end;
end;
|
--
-- Taken from rtl/commonlib/types_util.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Package for common testbenches implementation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
package types_util is
function strlen(s: in string) return integer;
function StringToUVector(inStr: string) return std_ulogic_vector;
function StringToSVector(inStr: string) return std_logic_vector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector) return std_logic_vector;
function SignalFromString(inStr: string; ind : integer ) return std_logic;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector;
function tost(v:std_logic_vector) return string;
function tost(v:std_logic) return string;
function tost(i : integer) return string;
procedure print(s : string);
end;
package body types_util is
function strlen(s: in string) return integer is
variable n: integer:=0; variable sj: integer:=s'left;
begin
loop
if sj>s'right then exit;
elsif s(sj)=NUL then exit; --sequential if protects sj > length
else sj:=sj+1; n:=n+1;
end if;
end loop;
return n;
end strlen;
function SignalFromString(inStr: string; ind : integer ) return std_logic is
variable temp: std_logic := 'X';
begin
if(inStr(inStr'high-ind)='1') then temp := '1';
elsif(inStr(inStr'high-ind)='0') then temp := '0';
end if;
return temp;
end function SignalFromString;
function StringToUVector(inStr: string) return std_ulogic_vector is
variable temp: std_ulogic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToUVector;
-- conversion function
function StringToSVector(inStr: string) return std_logic_vector is
variable temp: std_logic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToSVector;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector is
constant ss: string(1 to inStr'length) := inStr;
variable c : integer;
variable temp: std_logic_vector(7 downto 0) := (others => 'X');
begin
c := character'pos(ss(idx+1));
for i in 0 to 7 loop --
temp(i) := to_unsigned(c,8)(i);
end loop;
return temp;
end function SymbolToSVector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector)
return std_logic_vector is
variable temp: std_logic_vector(inUnsigned'length-1 downto 0) := (others => 'X');
variable i: integer:=0;
begin
while i < inUnsigned'length loop
if(inUnsigned(i)='1') then temp(i) := '1';
elsif(inUnsigned(i)='0') then temp(i) := '0';
end if;
i := i+1;
end loop;
return temp;
end function UnsignedToSigned;
subtype nibble is std_logic_vector(3 downto 0);
function todec(i:integer) return character is
begin
case i is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when others => return('0');
end case;
end;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
function tost(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(0 to slen*4-1) := (others => '0');
variable s : string(1 to slen);
variable nz : boolean := false;
variable index : integer := -1;
variable vector : bit_vector(0 TO 7);
alias reverse_vector : bit_vector
( vector'length DOWNTO 1 )
IS vector ;
begin
vv(slen*4-vlen to slen*4-1) := v;
for i in 0 to slen-1 loop
if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then
index := i;
else
nz := false;
s(i+1) := tohex(vv(i*4 to i*4+3));
end if;
end loop;
if ((index +2) = slen) then return(s(slen to slen));
else return(string'("0x") & s(index+2 to slen)); end if; --'
end;
function tost(v:std_logic) return string is
begin
if to_x01(v) = '1' then return("1"); else return("0"); end if;
end;
function tost(i : integer) return string is
variable L : line;
variable s, x : string(1 to 128);
variable n, tmp : integer := 0;
begin
tmp := i;
if i < 0 then tmp := -i; end if;
loop
s(128-n) := todec(tmp mod 10);
tmp := tmp / 10;
n := n+1;
if tmp = 0 then exit; end if;
end loop;
x(1 to n) := s(129-n to 128);
if i < 0 then return "-" & x(1 to n); end if;
return(x(1 to n));
end;
procedure print(s : string) is
variable L : line;
begin
L := new string'(s); writeline(output, L);
end;
end;
|
--
-- Taken from rtl/commonlib/types_util.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Package for common testbenches implementation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
package types_util is
function strlen(s: in string) return integer;
function StringToUVector(inStr: string) return std_ulogic_vector;
function StringToSVector(inStr: string) return std_logic_vector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector) return std_logic_vector;
function SignalFromString(inStr: string; ind : integer ) return std_logic;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector;
function tost(v:std_logic_vector) return string;
function tost(v:std_logic) return string;
function tost(i : integer) return string;
procedure print(s : string);
end;
package body types_util is
function strlen(s: in string) return integer is
variable n: integer:=0; variable sj: integer:=s'left;
begin
loop
if sj>s'right then exit;
elsif s(sj)=NUL then exit; --sequential if protects sj > length
else sj:=sj+1; n:=n+1;
end if;
end loop;
return n;
end strlen;
function SignalFromString(inStr: string; ind : integer ) return std_logic is
variable temp: std_logic := 'X';
begin
if(inStr(inStr'high-ind)='1') then temp := '1';
elsif(inStr(inStr'high-ind)='0') then temp := '0';
end if;
return temp;
end function SignalFromString;
function StringToUVector(inStr: string) return std_ulogic_vector is
variable temp: std_ulogic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToUVector;
-- conversion function
function StringToSVector(inStr: string) return std_logic_vector is
variable temp: std_logic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToSVector;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector is
constant ss: string(1 to inStr'length) := inStr;
variable c : integer;
variable temp: std_logic_vector(7 downto 0) := (others => 'X');
begin
c := character'pos(ss(idx+1));
for i in 0 to 7 loop --
temp(i) := to_unsigned(c,8)(i);
end loop;
return temp;
end function SymbolToSVector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector)
return std_logic_vector is
variable temp: std_logic_vector(inUnsigned'length-1 downto 0) := (others => 'X');
variable i: integer:=0;
begin
while i < inUnsigned'length loop
if(inUnsigned(i)='1') then temp(i) := '1';
elsif(inUnsigned(i)='0') then temp(i) := '0';
end if;
i := i+1;
end loop;
return temp;
end function UnsignedToSigned;
subtype nibble is std_logic_vector(3 downto 0);
function todec(i:integer) return character is
begin
case i is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when others => return('0');
end case;
end;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
function tost(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(0 to slen*4-1) := (others => '0');
variable s : string(1 to slen);
variable nz : boolean := false;
variable index : integer := -1;
variable vector : bit_vector(0 TO 7);
alias reverse_vector : bit_vector
( vector'length DOWNTO 1 )
IS vector ;
begin
vv(slen*4-vlen to slen*4-1) := v;
for i in 0 to slen-1 loop
if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then
index := i;
else
nz := false;
s(i+1) := tohex(vv(i*4 to i*4+3));
end if;
end loop;
if ((index +2) = slen) then return(s(slen to slen));
else return(string'("0x") & s(index+2 to slen)); end if; --'
end;
function tost(v:std_logic) return string is
begin
if to_x01(v) = '1' then return("1"); else return("0"); end if;
end;
function tost(i : integer) return string is
variable L : line;
variable s, x : string(1 to 128);
variable n, tmp : integer := 0;
begin
tmp := i;
if i < 0 then tmp := -i; end if;
loop
s(128-n) := todec(tmp mod 10);
tmp := tmp / 10;
n := n+1;
if tmp = 0 then exit; end if;
end loop;
x(1 to n) := s(129-n to 128);
if i < 0 then return "-" & x(1 to n); end if;
return(x(1 to n));
end;
procedure print(s : string) is
variable L : line;
begin
L := new string'(s); writeline(output, L);
end;
end;
|
--
-- Taken from rtl/commonlib/types_util.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Package for common testbenches implementation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
package types_util is
function strlen(s: in string) return integer;
function StringToUVector(inStr: string) return std_ulogic_vector;
function StringToSVector(inStr: string) return std_logic_vector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector) return std_logic_vector;
function SignalFromString(inStr: string; ind : integer ) return std_logic;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector;
function tost(v:std_logic_vector) return string;
function tost(v:std_logic) return string;
function tost(i : integer) return string;
procedure print(s : string);
end;
package body types_util is
function strlen(s: in string) return integer is
variable n: integer:=0; variable sj: integer:=s'left;
begin
loop
if sj>s'right then exit;
elsif s(sj)=NUL then exit; --sequential if protects sj > length
else sj:=sj+1; n:=n+1;
end if;
end loop;
return n;
end strlen;
function SignalFromString(inStr: string; ind : integer ) return std_logic is
variable temp: std_logic := 'X';
begin
if(inStr(inStr'high-ind)='1') then temp := '1';
elsif(inStr(inStr'high-ind)='0') then temp := '0';
end if;
return temp;
end function SignalFromString;
function StringToUVector(inStr: string) return std_ulogic_vector is
variable temp: std_ulogic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToUVector;
-- conversion function
function StringToSVector(inStr: string) return std_logic_vector is
variable temp: std_logic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToSVector;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector is
constant ss: string(1 to inStr'length) := inStr;
variable c : integer;
variable temp: std_logic_vector(7 downto 0) := (others => 'X');
begin
c := character'pos(ss(idx+1));
for i in 0 to 7 loop --
temp(i) := to_unsigned(c,8)(i);
end loop;
return temp;
end function SymbolToSVector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector)
return std_logic_vector is
variable temp: std_logic_vector(inUnsigned'length-1 downto 0) := (others => 'X');
variable i: integer:=0;
begin
while i < inUnsigned'length loop
if(inUnsigned(i)='1') then temp(i) := '1';
elsif(inUnsigned(i)='0') then temp(i) := '0';
end if;
i := i+1;
end loop;
return temp;
end function UnsignedToSigned;
subtype nibble is std_logic_vector(3 downto 0);
function todec(i:integer) return character is
begin
case i is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when others => return('0');
end case;
end;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
function tost(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(0 to slen*4-1) := (others => '0');
variable s : string(1 to slen);
variable nz : boolean := false;
variable index : integer := -1;
variable vector : bit_vector(0 TO 7);
alias reverse_vector : bit_vector
( vector'length DOWNTO 1 )
IS vector ;
begin
vv(slen*4-vlen to slen*4-1) := v;
for i in 0 to slen-1 loop
if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then
index := i;
else
nz := false;
s(i+1) := tohex(vv(i*4 to i*4+3));
end if;
end loop;
if ((index +2) = slen) then return(s(slen to slen));
else return(string'("0x") & s(index+2 to slen)); end if; --'
end;
function tost(v:std_logic) return string is
begin
if to_x01(v) = '1' then return("1"); else return("0"); end if;
end;
function tost(i : integer) return string is
variable L : line;
variable s, x : string(1 to 128);
variable n, tmp : integer := 0;
begin
tmp := i;
if i < 0 then tmp := -i; end if;
loop
s(128-n) := todec(tmp mod 10);
tmp := tmp / 10;
n := n+1;
if tmp = 0 then exit; end if;
end loop;
x(1 to n) := s(129-n to 128);
if i < 0 then return "-" & x(1 to n); end if;
return(x(1 to n));
end;
procedure print(s : string) is
variable L : line;
begin
L := new string'(s); writeline(output, L);
end;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
use work.pkg_6502_opcodes.all;
use work.file_io_pkg.all;
library std;
use std.textio.all;
entity tb_decode is
end tb_decode;
architecture tb of tb_decode is
signal i_reg : std_logic_vector(7 downto 0);
signal s_is_absolute : boolean;
signal s_is_abs_jump : boolean;
signal s_is_immediate : boolean;
signal s_is_implied : boolean;
signal s_is_stack : boolean;
signal s_is_push : boolean;
signal s_is_zeropage : boolean;
signal s_is_indirect : boolean;
signal s_is_relative : boolean;
signal s_is_load : boolean;
signal s_is_store : boolean;
signal s_is_shift : boolean;
signal s_is_alu : boolean;
signal s_is_rmw : boolean;
signal s_is_jump : boolean;
signal s_is_postindexed : boolean;
signal s_is_illegal : boolean;
signal s_select_index_y : boolean;
signal s_store_a_from_alu : boolean;
-- signal s_load_a : boolean;
signal s_load_x : boolean;
signal s_load_y : boolean;
signal clock : std_logic := '0';
signal reset : std_logic := '0';
type t_state is (fetch, decode, absolute, abs_hi, abs_fix, branch, branch_fix,
indir1, indir2, jump_sub, jump, retrn, rmw1, rmw2, vector, startup,
zp, zp_idx, zp_indir, push1, push2, push3, pull1, pull2, pull3 );
signal state : t_state;
signal state_idx : integer range 0 to 31;
signal opcode : string(1 to 13);
signal sync : std_logic;
signal dummy_cycle : std_logic;
signal latch_dreg : std_logic;
signal copy_d2p : std_logic;
signal reg_update : std_logic;
signal rwn : std_logic;
signal vect_addr : std_logic_vector(3 downto 0);
signal a16 : std_logic;
signal a_mux : t_amux := c_amux_pc;
signal dout_mux : t_dout_mux;
signal pc_oper : t_pc_oper;
signal s_oper : t_sp_oper;
signal adl_oper : t_adl_oper;
signal adh_oper : t_adh_oper;
signal stop_clock : boolean := false;
begin
s_is_absolute <= is_absolute(i_reg);
s_is_abs_jump <= is_abs_jump(i_reg);
s_is_immediate <= is_immediate(i_reg);
s_is_implied <= is_implied(i_reg);
s_is_stack <= is_stack(i_reg);
s_is_push <= is_push(i_reg);
s_is_zeropage <= is_zeropage(i_reg);
s_is_indirect <= is_indirect(i_reg);
s_is_relative <= is_relative(i_reg);
s_is_load <= is_load(i_reg);
s_is_store <= is_store(i_reg);
s_is_shift <= is_shift(i_reg);
s_is_alu <= is_alu(i_reg);
s_is_rmw <= is_rmw(i_reg);
s_is_jump <= is_jump(i_reg);
s_is_postindexed <= is_postindexed(i_reg);
s_is_illegal <= is_illegal(i_reg);
s_select_index_y <= select_index_y(i_reg);
s_store_a_from_alu <= store_a_from_alu(i_reg);
--s_load_a <= load_a(i_reg);
s_load_x <= load_x(i_reg);
s_load_y <= load_y(i_reg);
test: process
variable ireg : std_logic_vector(7 downto 0);
variable v_opcode : string(1 to 13);
begin
for i in 0 to 255 loop
ireg := std_logic_vector(to_unsigned(i, 8));
v_opcode := opcode_array(i);
assert not (v_opcode(4)=' ' and is_illegal(ireg)) report "Function says it's illegal, opcode does not." & v_opcode severity error;
assert not (v_opcode(4)='*' and not is_illegal(ireg)) report "Opcode says it's illegal, function says it's not." & v_opcode severity error;
end loop;
wait;
end process;
dump: process
variable inst : std_logic_vector(7 downto 0);
variable bool : boolean;
variable L : line;
type t_bool_array is array(natural range <>) of boolean;
type t_sel_array is array(natural range <>) of std_logic_vector(1 downto 0);
variable b_is_absolute : t_bool_array(0 to 255);
variable b_is_abs_jump : t_bool_array(0 to 255);
variable b_is_immediate : t_bool_array(0 to 255);
variable b_is_implied : t_bool_array(0 to 255);
variable b_is_stack : t_bool_array(0 to 255);
variable b_is_push : t_bool_array(0 to 255);
variable b_is_zeropage : t_bool_array(0 to 255);
variable b_is_indirect : t_bool_array(0 to 255);
variable b_is_relative : t_bool_array(0 to 255);
variable b_is_load : t_bool_array(0 to 255);
variable b_is_store : t_bool_array(0 to 255);
variable b_is_shift : t_bool_array(0 to 255);
variable b_is_alu : t_bool_array(0 to 255);
variable b_is_rmw : t_bool_array(0 to 255);
variable b_is_jump : t_bool_array(0 to 255);
variable b_is_postindexed : t_bool_array(0 to 255);
variable b_select_index_y : t_bool_array(0 to 255);
variable b_store_a_from_alu : t_bool_array(0 to 255);
variable b_shift_sel : t_sel_array(0 to 255);
procedure write_str(variable L : inout line; s : string) is
begin
write(L, s);
end procedure;
procedure output_bool(bool : boolean) is
begin
if bool then
write_str(L, " (*) ");
else
write_str(L, " . ");
end if;
end procedure;
procedure output_shift_sel(bool : boolean; sel: std_logic_vector(1 downto 0)) is
type t_string_array is array(natural range <>) of string(1 to 5);
constant c_shift_sel_str : t_string_array(0 to 3) := ( "0xFF ", "data ", "accu ", " A&D " );
begin
if bool then
write_str(L, c_shift_sel_str(to_integer(unsigned(sel))));
else
write_str(L, " . ");
end if;
end procedure;
procedure print_table(b : t_bool_array; title: string) is
begin
write(L, title);
writeline(output, L);
writeline(output, L);
write_str(L, " ");
for x in 0 to 7 loop
inst := std_logic_vector(to_unsigned(x*32, 8));
write(L, VecToHex(inst, 2));
write_str(L, " ");
end loop;
writeline(output, L);
for y in 0 to 31 loop
inst := std_logic_vector(to_unsigned(y, 8));
write(L, VecToHex(inst, 2));
write(L, ' ');
for x in 0 to 7 loop
output_bool(b(y + x*32));
end loop;
writeline(output, L);
end loop;
writeline(output, L);
writeline(output, L);
end procedure;
procedure print_sel_table(title: string) is
begin
write(L, title);
writeline(output, L);
writeline(output, L);
write_str(L, " ");
for x in 0 to 7 loop
inst := std_logic_vector(to_unsigned(x*32, 8));
write(L, VecToHex(inst, 2));
write_str(L, " ");
end loop;
writeline(output, L);
for y in 0 to 31 loop
inst := std_logic_vector(to_unsigned(y, 8));
write(L, VecToHex(inst, 2));
write(L, ' ');
for x in 0 to 7 loop
output_shift_sel(b_is_shift(y + x*32), b_shift_sel(y + x*32));
end loop;
writeline(output, L);
end loop;
writeline(output, L);
writeline(output, L);
end procedure;
procedure write_bool(variable L : inout line; b : boolean; t : string; f : string := "") is
begin
write(L, ";");
if b then
write(L, t);
else
write(L, f);
end if;
end procedure;
procedure write_signals(variable L : inout line) is
begin
write_bool(L, latch_dreg='1', "LatchDREG");
write_bool(L, reg_update='1', "RegUpdate");
write_bool(L, copy_d2p='1', "Load P");
write_bool(L, rwn='0', "Write");
write_bool(L, a16='1', "Inst", "Data");
write(L, ";ADDR:" & t_amux'image(a_mux));
write(L, ";DOUT:" & t_dout_mux'image(dout_mux));
write(L, ";PC:" & t_pc_oper'image(pc_oper));
write(L, ";SP:" & t_sp_oper'image(s_oper));
write(L, ";ADL:" & t_adl_oper'image(adl_oper));
write(L, ";ADH:" & t_adh_oper'image(adh_oper));
end procedure;
file fout : text;
type t_string_array is array(natural range <>) of string(1 to 3);
constant alu_strings : t_string_array(0 to 7) := ("OR ", "AND", "EOR", "ADC", "---", "LD ", "CMP", "SBC" );
constant shift_strings : t_string_array(0 to 7) := ("ASL", "ROL", "LSR", "ROR", "---", "LD ", "DEC", "INC" );
variable j : integer;
begin
for i in 0 to 255 loop
inst := std_logic_vector(to_unsigned(i, 8));
b_is_absolute(i) := is_absolute(inst);
b_is_abs_jump(i) := is_abs_jump(inst);
b_is_immediate(i) := is_immediate(inst);
b_is_implied(i) := is_implied(inst);
b_is_stack(i) := is_stack(inst);
b_is_push(i) := is_push(inst);
b_is_zeropage(i) := is_zeropage(inst);
b_is_indirect(i) := is_indirect(inst);
b_is_relative(i) := is_relative(inst);
b_is_load(i) := is_load(inst);
b_is_store(i) := is_store(inst);
b_is_shift(i) := is_shift(inst);
b_is_alu(i) := is_alu(inst);
b_is_rmw(i) := is_rmw(inst);
b_is_jump(i) := is_jump(inst);
b_is_postindexed(i) := is_postindexed(inst);
b_select_index_y(i) := select_index_y(inst);
b_store_a_from_alu(i) := store_a_from_alu(inst);
b_shift_sel(i) := shifter_in_select(inst);
end loop;
print_table(b_is_absolute , "is_absolute");
print_table(b_is_abs_jump , "is_abs_jump");
print_table(b_is_immediate , "is_immediate");
print_table(b_is_implied , "is_implied");
print_table(b_is_stack , "is_stack");
print_table(b_is_push , "is_push");
print_table(b_is_zeropage , "is_zeropage");
print_table(b_is_indirect , "is_indirect");
print_table(b_is_relative , "is_relative");
print_table(b_is_load , "is_load");
print_table(b_is_store , "is_store");
print_table(b_is_shift , "is_shift");
print_table(b_is_alu , "is_alu");
print_table(b_is_rmw , "is_rmw");
print_table(b_is_jump , "is_jump");
print_table(b_is_postindexed , "is_postindexed");
print_table(b_select_index_y , "Select index Y");
print_table(b_store_a_from_alu , "Store A from ALU");
print_sel_table("Shifter Input");
reset <= '1';
wait until clock = '1';
wait until clock = '1';
reset <= '0';
file_open(fout, "opcodes.csv", WRITE_MODE);
write(L, "Code;Opcode;State;IMM#;IMPL;ABS;REL;RMW;ZP;INDIR;INDEXED;X/Y;AJMP;JUMP;STACK;PUSH;LOAD;STORE;SHIFT;ALU;ALU->A;->SH" );
writeline(fout, L);
for i in 0 to 256 loop
j := i mod 256;
while sync /= '1' loop
write(L, ";;" & t_state'image(state));
write(L, ";;;;;;;;;;;;;;;;;;;");
write_signals(L);
writeline(fout,L);
wait until clock = '1';
end loop;
i_reg <= std_logic_vector(to_unsigned(j, 8));
write(L, VecToHex(std_logic_vector(to_unsigned(j, 8)), 2));
write(L, ";" & opcode_array(j));
write(L, ";" & t_state'image(state));
write_bool(L, b_is_immediate(j) , "IMM#");
write_bool(L, b_is_implied(j) , "IMPL");
write_bool(L, b_is_absolute(j) , "ABS");
write_bool(L, b_is_relative(j) , "REL");
write_bool(L, b_is_rmw(j) , "RMW");
write_bool(L, b_is_zeropage(j) , "ZP");
write_bool(L, b_is_indirect(j) , "INDIR");
write_bool(L, b_is_postindexed(j), "INDEXED");
write_bool(L, b_select_index_y(j), "Y", "X" );
write_bool(L, b_is_abs_jump(j) , "AJMP");
write_bool(L, b_is_jump(j) , "JUMP");
write_bool(L, b_is_stack(j) , "STACK");
write_bool(L, b_is_push(j) and b_is_stack(j), "PUSH");
write_bool(L, b_is_load(j) , "LOAD");
write_bool(L, b_is_store(j) , "STORE");
write_bool(L, b_is_shift(j) , "SHIFT:" & shift_strings(to_integer(unsigned(i_reg(7 downto 5)))));
write_bool(L, b_is_alu(j) , "ALU:" & alu_strings(to_integer(unsigned(i_reg(7 downto 5)))));
write_bool(L, b_store_a_from_alu(j), "ALU->A");
write(L, ";");
output_shift_sel(b_is_shift(j), b_shift_sel(j));
write_signals(L);
writeline(fout,L);
wait until clock = '1';
end loop;
stop_clock <= true;
file_close(fout);
wait;
end process;
clock <= not clock after 0.5 us when not stop_clock;
i_proc: entity work.proc_control
generic map (true)
port map (
clock => clock,
clock_en => '1',
ready => '1',
reset => reset,
interrupt => '0',
i_reg => i_reg,
index_carry => '0',
pc_carry => '0',
branch_taken => true,
sync => sync,
dummy_cycle => open,
state_idx => state_idx,
latch_dreg => latch_dreg,
copy_d2p => copy_d2p,
reg_update => reg_update,
rwn => rwn,
-- set_i_flag => set_i_flag,
-- nmi_done => nmi_done,
vect_sel => "00",
vect_addr => vect_addr,
a16 => a16,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper
);
state <= t_state'val(state_idx);
opcode <= opcode_array(to_integer(unsigned(i_reg)));
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
entity conv01 is
port (i : std_logic_vector (19 downto 0);
o : out std_logic_vector (31 downto 0));
end conv01;
architecture behav of conv01 is
begin
process (i)
variable v : std_logic_vector (31 downto 0);
begin
v := (i'left downto 0 => i, others => '0');
o <= v;
end process;
end behav;
|
entity FIFO is
END entity;
entity FIFO is
END entity;
entity FIFO is
END entity;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grtestmod
-- File: grtestmod.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Modified: Jan Andersson, Aeroflex Gaisler
-- Contact: [email protected]
-- Description: Test report module
--
-- See also the gaiser.sim.ahbrep module for a module connected via AHB for
-- for use internally on SoC.
--
-- This module supports a 16- or 32-bit interface as selected via the 'width'
-- generic.
--
-- In 32-bit mode the module has the following memory map:
--
-- 0x00 : sets and prints vendor id from data[31:24] and
-- device id from data[23:12]
-- 0x04 : asserts error number data[15:0]
-- 0x08 : calls subtest data[7:0]
-- 0x10 : prints *** GRLIB system test starting ***
-- 0x14 : prints Test passed / errors detected
-- 0x18 : prints Checkpoint data[15:0] with time stamp
--
-- In 16-bit mode the module has the following memory map:
--
-- 0x00 : sets vendor id from data[15:8] and MSbs of device id from data[7:0]
-- 0x04 : asserts error number data[15:0]
-- 0x08 : calls subtest data[7:0]
-- 0x0C : sets LSbs of device id from data[15:12], prints vendor and device id
-- 0x10 : prints *** GRLIB system test starting ***
-- 0x14 : prints Test passed / errors detected
-- 0x18 : prints Checkpoint data[15:0] with time stamp
--
-- The width is defined for the systest software via GRLIB_REPORTDEV_WIDTH
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
use std.textio.all;
entity grtestmod is
generic (
halt : integer := 0;
width : integer := 32);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : in std_ulogic;
address : in std_logic_vector(21 downto 2);
data : inout std_logic_vector(width-1 downto 0);
iosn : in std_ulogic;
oen : in std_ulogic;
writen : in std_ulogic;
brdyn : out std_ulogic := '1';
bexcn : out std_ulogic := '1';
state : out std_logic_vector(1 downto 0);
testdev : out std_logic_vector(19 downto 0);
subtest : out std_logic_vector(7 downto 0)
);
end;
architecture sim of grtestmod is
subtype msgtype is string(1 to 40);
constant ntests : integer := 2;
type msgarr is array (0 to ntests) of msgtype;
constant msg : msgarr := (
"*** Starting GRLIB system test *** ", -- 0
"Test completed OK, halting simulation ", -- 1
"Test FAILED " -- 2
);
signal ior, iow : std_ulogic;
signal addr : std_logic_vector(21 downto 2);
signal ldata : std_logic_vector(width-1 downto 0);
begin
ior <= iosn or oen;
iow <= iosn or writen;
data <= (others => 'Z');
addr <= to_X01(address) after 1 ns;
ldata <= to_X01(data) after 1 ns;
log : process(ior, iow) --, clk)
variable errno, errcnt, lsubtest, vendorid, deviceid : integer;
variable lstate: std_logic_vector(1 downto 0) := "00";
--variable addr : std_logic_vector(21 downto 2);
--variable ldata : std_logic_vector(width-1 downto 0);
begin
--if rising_edge(clk) then
-- addr := to_X01(address);
-- ldata := to_X01(data);
--end if;
if falling_edge (ior) then
brdyn <= '1', '0' after 100 ns;
if addr(15) = '1' then bexcn <= '1', '0' after 100 ns; end if;
elsif rising_edge (ior) then
brdyn <= '1'; bexcn <= '1';
elsif falling_edge(iow) then
brdyn <= '1', '0' after 100 ns;
if addr(15) = '1' then bexcn <= '1', '0' after 100 ns; end if;
elsif rising_edge(iow) then
brdyn <= '1'; bexcn <= '1';
-- addr := to_X01(address);
case addr(7 downto 2) is
when "000000" =>
if width = 32 then
vendorid := conv_integer(ldata(31*(width/32) downto 24*(width/32)));
deviceid := conv_integer(ldata(23*(width/32) downto 12*(width/32)));
print(iptable(vendorid).device_table(deviceid));
testdev <= conv_std_logic_vector(vendorid*256+deviceid,20);
else
vendorid := conv_integer(ldata(15 downto 8));
deviceid := 2**4*conv_integer(ldata(7 downto 0));
end if;
when "000001" =>
errno := conv_integer(ldata(15 downto 0));
if (halt = 0) then
assert false
report "test failed, error (" & tost(errno) & ")"
severity failure;
else
assert false
report "test failed, error (" & tost(errno) & ")"
severity warning;
end if;
lstate := "11";
when "000010" =>
lsubtest := conv_integer(ldata(7 downto 0));
call_subtest(vendorid, deviceid, lsubtest);
subtest <= conv_std_logic_vector(lsubtest,8);
when "000011" =>
if width = 16 then
deviceid := deviceid + conv_integer(ldata(15 downto 12));
print(iptable(vendorid).device_table(deviceid));
testdev <= conv_std_logic_vector(vendorid*256+deviceid,20);
end if;
when "000100" =>
print ("");
print ("**** GRLIB system test starting ****");
errcnt := 0;
if lstate="00" then lstate := "01"; end if;
when "000101" =>
if errcnt = 0 then
print ("Test passed, halting with IU error mode");
if lstate="01" then lstate := "10"; end if;
elsif errcnt = 1 then
print ("1 error detected, halting with IU error mode");
else
print (tost(errcnt) & " errors detected, halting with IU error mode");
end if;
print ("");
when "000110" =>
grlib.testlib.print("Checkpoint " & tost(conv_integer(ldata(15 downto 0))));
when "000111" =>
vendorid := 0; deviceid := 0;
print ("Basic memory test");
when others =>
end case;
end if;
state <= lstate;
end process;
end;
-- pragma translate_on
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNAUBM7IRL is
Begin
output <= a & b;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNAUBM7IRL is
Begin
output <= a & b;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNAUBM7IRL is
Begin
output <= a & b;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNAUBM7IRL is
Begin
output <= a & b;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNAUBM7IRL is
Begin
output <= a & b;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNAUBM7IRL is
Begin
output <= a & b;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNAUBM7IRL is
Begin
output <= a & b;
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNAUBM7IRL is
Begin
output <= a & b;
end architecture; |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Module Name: adau1761_configuraiton_data - Behavioral
-- Description: A script for the I3C2, which sends out I2c transactions to configure
-- the ADAU1761 codec.
--
-- See i3c2program for original source for script
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adau1761_configuraiton_data is
Port ( clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (9 downto 0);
data : out STD_LOGIC_VECTOR (8 downto 0));
end adau1761_configuraiton_data;
architecture Behavioral of adau1761_configuraiton_data is
begin
process(clk)
begin
if rising_edge(clk) then
case address is
when "0000000000" => data <= "011101111";
when "0000000001" => data <= "101110110";
when "0000000010" => data <= "101000000";
when "0000000011" => data <= "100000000";
when "0000000100" => data <= "100001110";
when "0000000101" => data <= "011111111";
when "0000000110" => data <= "101110110";
when "0000000111" => data <= "101000000";
when "0000001000" => data <= "100000010";
when "0000001001" => data <= "100000000";
when "0000001010" => data <= "101111101";
when "0000001011" => data <= "100000000";
when "0000001100" => data <= "100001100";
when "0000001101" => data <= "100100011";
when "0000001110" => data <= "100000001";
when "0000001111" => data <= "011111111";
when "0000010000" => data <= "011101111";
when "0000010001" => data <= "101110110";
when "0000010010" => data <= "101000000";
when "0000010011" => data <= "100000000";
when "0000010100" => data <= "100001111";
when "0000010101" => data <= "011111111";
when "0000010110" => data <= "011101111";
when "0000010111" => data <= "101110110";
when "0000011000" => data <= "101000000";
when "0000011001" => data <= "100010101";
when "0000011010" => data <= "100000001";
when "0000011011" => data <= "011111111";
when "0000011100" => data <= "101110110";
when "0000011101" => data <= "101000000";
when "0000011110" => data <= "100001010";
when "0000011111" => data <= "100000001";
when "0000100000" => data <= "011111111";
when "0000100001" => data <= "101110110";
when "0000100010" => data <= "101000000";
when "0000100011" => data <= "100001011";
when "0000100100" => data <= "100000101";
when "0000100101" => data <= "011111111";
when "0000100110" => data <= "101110110";
when "0000100111" => data <= "101000000";
when "0000101000" => data <= "100001100";
when "0000101001" => data <= "100000001";
when "0000101010" => data <= "011111111";
when "0000101011" => data <= "101110110";
when "0000101100" => data <= "101000000";
when "0000101101" => data <= "100001101";
when "0000101110" => data <= "100000101";
when "0000101111" => data <= "011111111";
when "0000110000" => data <= "101110110";
when "0000110001" => data <= "101000000";
when "0000110010" => data <= "100011100";
when "0000110011" => data <= "100100001";
when "0000110100" => data <= "011111111";
when "0000110101" => data <= "101110110";
when "0000110110" => data <= "101000000";
when "0000110111" => data <= "100011110";
when "0000111000" => data <= "101000001";
when "0000111001" => data <= "011111111";
when "0000111010" => data <= "101110110";
when "0000111011" => data <= "101000000";
when "0000111100" => data <= "100100011";
when "0000111101" => data <= "111100111";
when "0000111110" => data <= "011111111";
when "0000111111" => data <= "101110110";
when "0001000000" => data <= "101000000";
when "0001000001" => data <= "100100100";
when "0001000010" => data <= "111100111";
when "0001000011" => data <= "011111111";
when "0001000100" => data <= "101110110";
when "0001000101" => data <= "101000000";
when "0001000110" => data <= "100100101";
when "0001000111" => data <= "111100111";
when "0001001000" => data <= "011111111";
when "0001001001" => data <= "101110110";
when "0001001010" => data <= "101000000";
when "0001001011" => data <= "100100110";
when "0001001100" => data <= "111100111";
when "0001001101" => data <= "011111111";
when "0001001110" => data <= "101110110";
when "0001001111" => data <= "101000000";
when "0001010000" => data <= "100011001";
when "0001010001" => data <= "100000011";
when "0001010010" => data <= "011111111";
when "0001010011" => data <= "101110110";
when "0001010100" => data <= "101000000";
when "0001010101" => data <= "100101001";
when "0001010110" => data <= "100000011";
when "0001010111" => data <= "011111111";
when "0001011000" => data <= "101110110";
when "0001011001" => data <= "101000000";
when "0001011010" => data <= "100101010";
when "0001011011" => data <= "100000011";
when "0001011100" => data <= "011111111";
when "0001011101" => data <= "101110110";
when "0001011110" => data <= "101000000";
when "0001011111" => data <= "111110010";
when "0001100000" => data <= "100000001";
when "0001100001" => data <= "011111111";
when "0001100010" => data <= "101110110";
when "0001100011" => data <= "101000000";
when "0001100100" => data <= "111110011";
when "0001100101" => data <= "100000001";
when "0001100110" => data <= "011111111";
when "0001100111" => data <= "101110110";
when "0001101000" => data <= "101000000";
when "0001101001" => data <= "111111001";
when "0001101010" => data <= "101111111";
when "0001101011" => data <= "011111111";
when "0001101100" => data <= "101110110";
when "0001101101" => data <= "101000000";
when "0001101110" => data <= "111111010";
when "0001101111" => data <= "100000011";
when "0001110000" => data <= "011111111";
when "0001110001" => data <= "000010011";
when "0001110010" => data <= "011111110";
when "0001110011" => data <= "011111110";
when "0001110100" => data <= "011111110";
when "0001110101" => data <= "011111110";
when "0001110110" => data <= "011111110";
when "0001110111" => data <= "011111110";
when "0001111000" => data <= "101110110";
when "0001111001" => data <= "101000000";
when "0001111010" => data <= "100011100";
when "0001111011" => data <= "100100000";
when "0001111100" => data <= "011111111";
when "0001111101" => data <= "101110110";
when "0001111110" => data <= "101000000";
when "0001111111" => data <= "100011110";
when "0010000000" => data <= "101000000";
when "0010000001" => data <= "011111111";
when "0010000010" => data <= "011101111";
when "0010000011" => data <= "011101111";
when "0010000100" => data <= "011101111";
when "0010000101" => data <= "011101111";
when "0010000110" => data <= "010100000";
when "0010000111" => data <= "010100001";
when "0010001000" => data <= "011101111";
when "0010001001" => data <= "011101111";
when "0010001010" => data <= "101110110";
when "0010001011" => data <= "101000000";
when "0010001100" => data <= "100011100";
when "0010001101" => data <= "100100001";
when "0010001110" => data <= "011111111";
when "0010001111" => data <= "101110110";
when "0010010000" => data <= "101000000";
when "0010010001" => data <= "100011110";
when "0010010010" => data <= "101000001";
when "0010010011" => data <= "011111111";
when "0010010100" => data <= "011111110";
when "0010010101" => data <= "011111110";
when "0010010110" => data <= "011111110";
when "0010010111" => data <= "011111110";
when "0010011000" => data <= "010000000";
when "0010011001" => data <= "000010100";
when "0010011010" => data <= "010000001";
when "0010011011" => data <= "000011001";
when "0010011100" => data <= "000010011";
when "0010011101" => data <= "011111110";
when "0010011110" => data <= "011111110";
when "0010011111" => data <= "011111110";
when "0010100000" => data <= "101110110";
when "0010100001" => data <= "101000000";
when "0010100010" => data <= "100011100";
when "0010100011" => data <= "100100000";
when "0010100100" => data <= "011111111";
when "0010100101" => data <= "101110110";
when "0010100110" => data <= "101000000";
when "0010100111" => data <= "100011110";
when "0010101000" => data <= "101000000";
when "0010101001" => data <= "011111111";
when "0010101010" => data <= "011101111";
when "0010101011" => data <= "011101111";
when "0010101100" => data <= "011101111";
when "0010101101" => data <= "011101111";
when "0010101110" => data <= "010110000";
when "0010101111" => data <= "010100001";
when "0010110000" => data <= "011101111";
when "0010110001" => data <= "011101111";
when "0010110010" => data <= "101110110";
when "0010110011" => data <= "101000000";
when "0010110100" => data <= "100011100";
when "0010110101" => data <= "100100001";
when "0010110110" => data <= "011111111";
when "0010110111" => data <= "101110110";
when "0010111000" => data <= "101000000";
when "0010111001" => data <= "100011110";
when "0010111010" => data <= "101000001";
when "0010111011" => data <= "011111111";
when "0010111100" => data <= "011111110";
when "0010111101" => data <= "011111110";
when "0010111110" => data <= "011111110";
when "0010111111" => data <= "011111110";
when "0011000000" => data <= "010010000";
when "0011000001" => data <= "000001111";
when "0011000010" => data <= "010000001";
when "0011000011" => data <= "000011110";
when "0011000100" => data <= "000011000";
when "0011000101" => data <= "011111110";
when "0011000110" => data <= "011111110";
when "0011000111" => data <= "011111110";
when "0011001000" => data <= "101110110";
when "0011001001" => data <= "101000000";
when "0011001010" => data <= "100011100";
when "0011001011" => data <= "100100000";
when "0011001100" => data <= "011111111";
when "0011001101" => data <= "101110110";
when "0011001110" => data <= "101000000";
when "0011001111" => data <= "100011110";
when "0011010000" => data <= "101000000";
when "0011010001" => data <= "011111111";
when "0011010010" => data <= "011101111";
when "0011010011" => data <= "011101111";
when "0011010100" => data <= "011101111";
when "0011010101" => data <= "011101111";
when "0011010110" => data <= "010100000";
when "0011010111" => data <= "010110001";
when "0011011000" => data <= "011101111";
when "0011011001" => data <= "011101111";
when "0011011010" => data <= "101110110";
when "0011011011" => data <= "101000000";
when "0011011100" => data <= "100011100";
when "0011011101" => data <= "100100001";
when "0011011110" => data <= "011111111";
when "0011011111" => data <= "101110110";
when "0011100000" => data <= "101000000";
when "0011100001" => data <= "100011110";
when "0011100010" => data <= "101000001";
when "0011100011" => data <= "011111111";
when "0011100100" => data <= "011111110";
when "0011100101" => data <= "011111110";
when "0011100110" => data <= "011111110";
when "0011100111" => data <= "011111110";
when "0011101000" => data <= "010000000";
when "0011101001" => data <= "000000000";
when "0011101010" => data <= "010010001";
when "0011101011" => data <= "000001111";
when "0011101100" => data <= "000011101";
when "0011101101" => data <= "011111110";
when "0011101110" => data <= "011111110";
when "0011101111" => data <= "011111110";
when "0011110000" => data <= "101110110";
when "0011110001" => data <= "101000000";
when "0011110010" => data <= "100011100";
when "0011110011" => data <= "100100000";
when "0011110100" => data <= "011111111";
when "0011110101" => data <= "101110110";
when "0011110110" => data <= "101000000";
when "0011110111" => data <= "100011110";
when "0011111000" => data <= "101000000";
when "0011111001" => data <= "011111111";
when "0011111010" => data <= "011101111";
when "0011111011" => data <= "011101111";
when "0011111100" => data <= "011101111";
when "0011111101" => data <= "011101111";
when "0011111110" => data <= "010110000";
when "0011111111" => data <= "010110001";
when "0100000000" => data <= "011101111";
when "0100000001" => data <= "011101111";
when "0100000010" => data <= "101110110";
when "0100000011" => data <= "101000000";
when "0100000100" => data <= "100011100";
when "0100000101" => data <= "100100001";
when "0100000110" => data <= "011111111";
when "0100000111" => data <= "101110110";
when "0100001000" => data <= "101000000";
when "0100001001" => data <= "100011110";
when "0100001010" => data <= "101000001";
when "0100001011" => data <= "011111111";
when "0100001100" => data <= "011111110";
when "0100001101" => data <= "011111110";
when "0100001110" => data <= "011111110";
when "0100001111" => data <= "011111110";
when "0100010000" => data <= "010010000";
when "0100010001" => data <= "000011001";
when "0100010010" => data <= "010010001";
when "0100010011" => data <= "000010100";
when "0100010100" => data <= "000100010";
when others => data <= (others =>'0');
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Module Name: adau1761_configuraiton_data - Behavioral
-- Description: A script for the I3C2, which sends out I2c transactions to configure
-- the ADAU1761 codec.
--
-- See i3c2program for original source for script
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity adau1761_configuraiton_data is
Port ( clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (9 downto 0);
data : out STD_LOGIC_VECTOR (8 downto 0));
end adau1761_configuraiton_data;
architecture Behavioral of adau1761_configuraiton_data is
begin
process(clk)
begin
if rising_edge(clk) then
case address is
when "0000000000" => data <= "011101111";
when "0000000001" => data <= "101110110";
when "0000000010" => data <= "101000000";
when "0000000011" => data <= "100000000";
when "0000000100" => data <= "100001110";
when "0000000101" => data <= "011111111";
when "0000000110" => data <= "101110110";
when "0000000111" => data <= "101000000";
when "0000001000" => data <= "100000010";
when "0000001001" => data <= "100000000";
when "0000001010" => data <= "101111101";
when "0000001011" => data <= "100000000";
when "0000001100" => data <= "100001100";
when "0000001101" => data <= "100100011";
when "0000001110" => data <= "100000001";
when "0000001111" => data <= "011111111";
when "0000010000" => data <= "011101111";
when "0000010001" => data <= "101110110";
when "0000010010" => data <= "101000000";
when "0000010011" => data <= "100000000";
when "0000010100" => data <= "100001111";
when "0000010101" => data <= "011111111";
when "0000010110" => data <= "011101111";
when "0000010111" => data <= "101110110";
when "0000011000" => data <= "101000000";
when "0000011001" => data <= "100010101";
when "0000011010" => data <= "100000001";
when "0000011011" => data <= "011111111";
when "0000011100" => data <= "101110110";
when "0000011101" => data <= "101000000";
when "0000011110" => data <= "100001010";
when "0000011111" => data <= "100000001";
when "0000100000" => data <= "011111111";
when "0000100001" => data <= "101110110";
when "0000100010" => data <= "101000000";
when "0000100011" => data <= "100001011";
when "0000100100" => data <= "100000101";
when "0000100101" => data <= "011111111";
when "0000100110" => data <= "101110110";
when "0000100111" => data <= "101000000";
when "0000101000" => data <= "100001100";
when "0000101001" => data <= "100000001";
when "0000101010" => data <= "011111111";
when "0000101011" => data <= "101110110";
when "0000101100" => data <= "101000000";
when "0000101101" => data <= "100001101";
when "0000101110" => data <= "100000101";
when "0000101111" => data <= "011111111";
when "0000110000" => data <= "101110110";
when "0000110001" => data <= "101000000";
when "0000110010" => data <= "100011100";
when "0000110011" => data <= "100100001";
when "0000110100" => data <= "011111111";
when "0000110101" => data <= "101110110";
when "0000110110" => data <= "101000000";
when "0000110111" => data <= "100011110";
when "0000111000" => data <= "101000001";
when "0000111001" => data <= "011111111";
when "0000111010" => data <= "101110110";
when "0000111011" => data <= "101000000";
when "0000111100" => data <= "100100011";
when "0000111101" => data <= "111100111";
when "0000111110" => data <= "011111111";
when "0000111111" => data <= "101110110";
when "0001000000" => data <= "101000000";
when "0001000001" => data <= "100100100";
when "0001000010" => data <= "111100111";
when "0001000011" => data <= "011111111";
when "0001000100" => data <= "101110110";
when "0001000101" => data <= "101000000";
when "0001000110" => data <= "100100101";
when "0001000111" => data <= "111100111";
when "0001001000" => data <= "011111111";
when "0001001001" => data <= "101110110";
when "0001001010" => data <= "101000000";
when "0001001011" => data <= "100100110";
when "0001001100" => data <= "111100111";
when "0001001101" => data <= "011111111";
when "0001001110" => data <= "101110110";
when "0001001111" => data <= "101000000";
when "0001010000" => data <= "100011001";
when "0001010001" => data <= "100000011";
when "0001010010" => data <= "011111111";
when "0001010011" => data <= "101110110";
when "0001010100" => data <= "101000000";
when "0001010101" => data <= "100101001";
when "0001010110" => data <= "100000011";
when "0001010111" => data <= "011111111";
when "0001011000" => data <= "101110110";
when "0001011001" => data <= "101000000";
when "0001011010" => data <= "100101010";
when "0001011011" => data <= "100000011";
when "0001011100" => data <= "011111111";
when "0001011101" => data <= "101110110";
when "0001011110" => data <= "101000000";
when "0001011111" => data <= "111110010";
when "0001100000" => data <= "100000001";
when "0001100001" => data <= "011111111";
when "0001100010" => data <= "101110110";
when "0001100011" => data <= "101000000";
when "0001100100" => data <= "111110011";
when "0001100101" => data <= "100000001";
when "0001100110" => data <= "011111111";
when "0001100111" => data <= "101110110";
when "0001101000" => data <= "101000000";
when "0001101001" => data <= "111111001";
when "0001101010" => data <= "101111111";
when "0001101011" => data <= "011111111";
when "0001101100" => data <= "101110110";
when "0001101101" => data <= "101000000";
when "0001101110" => data <= "111111010";
when "0001101111" => data <= "100000011";
when "0001110000" => data <= "011111111";
when "0001110001" => data <= "000010011";
when "0001110010" => data <= "011111110";
when "0001110011" => data <= "011111110";
when "0001110100" => data <= "011111110";
when "0001110101" => data <= "011111110";
when "0001110110" => data <= "011111110";
when "0001110111" => data <= "011111110";
when "0001111000" => data <= "101110110";
when "0001111001" => data <= "101000000";
when "0001111010" => data <= "100011100";
when "0001111011" => data <= "100100000";
when "0001111100" => data <= "011111111";
when "0001111101" => data <= "101110110";
when "0001111110" => data <= "101000000";
when "0001111111" => data <= "100011110";
when "0010000000" => data <= "101000000";
when "0010000001" => data <= "011111111";
when "0010000010" => data <= "011101111";
when "0010000011" => data <= "011101111";
when "0010000100" => data <= "011101111";
when "0010000101" => data <= "011101111";
when "0010000110" => data <= "010100000";
when "0010000111" => data <= "010100001";
when "0010001000" => data <= "011101111";
when "0010001001" => data <= "011101111";
when "0010001010" => data <= "101110110";
when "0010001011" => data <= "101000000";
when "0010001100" => data <= "100011100";
when "0010001101" => data <= "100100001";
when "0010001110" => data <= "011111111";
when "0010001111" => data <= "101110110";
when "0010010000" => data <= "101000000";
when "0010010001" => data <= "100011110";
when "0010010010" => data <= "101000001";
when "0010010011" => data <= "011111111";
when "0010010100" => data <= "011111110";
when "0010010101" => data <= "011111110";
when "0010010110" => data <= "011111110";
when "0010010111" => data <= "011111110";
when "0010011000" => data <= "010000000";
when "0010011001" => data <= "000010100";
when "0010011010" => data <= "010000001";
when "0010011011" => data <= "000011001";
when "0010011100" => data <= "000010011";
when "0010011101" => data <= "011111110";
when "0010011110" => data <= "011111110";
when "0010011111" => data <= "011111110";
when "0010100000" => data <= "101110110";
when "0010100001" => data <= "101000000";
when "0010100010" => data <= "100011100";
when "0010100011" => data <= "100100000";
when "0010100100" => data <= "011111111";
when "0010100101" => data <= "101110110";
when "0010100110" => data <= "101000000";
when "0010100111" => data <= "100011110";
when "0010101000" => data <= "101000000";
when "0010101001" => data <= "011111111";
when "0010101010" => data <= "011101111";
when "0010101011" => data <= "011101111";
when "0010101100" => data <= "011101111";
when "0010101101" => data <= "011101111";
when "0010101110" => data <= "010110000";
when "0010101111" => data <= "010100001";
when "0010110000" => data <= "011101111";
when "0010110001" => data <= "011101111";
when "0010110010" => data <= "101110110";
when "0010110011" => data <= "101000000";
when "0010110100" => data <= "100011100";
when "0010110101" => data <= "100100001";
when "0010110110" => data <= "011111111";
when "0010110111" => data <= "101110110";
when "0010111000" => data <= "101000000";
when "0010111001" => data <= "100011110";
when "0010111010" => data <= "101000001";
when "0010111011" => data <= "011111111";
when "0010111100" => data <= "011111110";
when "0010111101" => data <= "011111110";
when "0010111110" => data <= "011111110";
when "0010111111" => data <= "011111110";
when "0011000000" => data <= "010010000";
when "0011000001" => data <= "000001111";
when "0011000010" => data <= "010000001";
when "0011000011" => data <= "000011110";
when "0011000100" => data <= "000011000";
when "0011000101" => data <= "011111110";
when "0011000110" => data <= "011111110";
when "0011000111" => data <= "011111110";
when "0011001000" => data <= "101110110";
when "0011001001" => data <= "101000000";
when "0011001010" => data <= "100011100";
when "0011001011" => data <= "100100000";
when "0011001100" => data <= "011111111";
when "0011001101" => data <= "101110110";
when "0011001110" => data <= "101000000";
when "0011001111" => data <= "100011110";
when "0011010000" => data <= "101000000";
when "0011010001" => data <= "011111111";
when "0011010010" => data <= "011101111";
when "0011010011" => data <= "011101111";
when "0011010100" => data <= "011101111";
when "0011010101" => data <= "011101111";
when "0011010110" => data <= "010100000";
when "0011010111" => data <= "010110001";
when "0011011000" => data <= "011101111";
when "0011011001" => data <= "011101111";
when "0011011010" => data <= "101110110";
when "0011011011" => data <= "101000000";
when "0011011100" => data <= "100011100";
when "0011011101" => data <= "100100001";
when "0011011110" => data <= "011111111";
when "0011011111" => data <= "101110110";
when "0011100000" => data <= "101000000";
when "0011100001" => data <= "100011110";
when "0011100010" => data <= "101000001";
when "0011100011" => data <= "011111111";
when "0011100100" => data <= "011111110";
when "0011100101" => data <= "011111110";
when "0011100110" => data <= "011111110";
when "0011100111" => data <= "011111110";
when "0011101000" => data <= "010000000";
when "0011101001" => data <= "000000000";
when "0011101010" => data <= "010010001";
when "0011101011" => data <= "000001111";
when "0011101100" => data <= "000011101";
when "0011101101" => data <= "011111110";
when "0011101110" => data <= "011111110";
when "0011101111" => data <= "011111110";
when "0011110000" => data <= "101110110";
when "0011110001" => data <= "101000000";
when "0011110010" => data <= "100011100";
when "0011110011" => data <= "100100000";
when "0011110100" => data <= "011111111";
when "0011110101" => data <= "101110110";
when "0011110110" => data <= "101000000";
when "0011110111" => data <= "100011110";
when "0011111000" => data <= "101000000";
when "0011111001" => data <= "011111111";
when "0011111010" => data <= "011101111";
when "0011111011" => data <= "011101111";
when "0011111100" => data <= "011101111";
when "0011111101" => data <= "011101111";
when "0011111110" => data <= "010110000";
when "0011111111" => data <= "010110001";
when "0100000000" => data <= "011101111";
when "0100000001" => data <= "011101111";
when "0100000010" => data <= "101110110";
when "0100000011" => data <= "101000000";
when "0100000100" => data <= "100011100";
when "0100000101" => data <= "100100001";
when "0100000110" => data <= "011111111";
when "0100000111" => data <= "101110110";
when "0100001000" => data <= "101000000";
when "0100001001" => data <= "100011110";
when "0100001010" => data <= "101000001";
when "0100001011" => data <= "011111111";
when "0100001100" => data <= "011111110";
when "0100001101" => data <= "011111110";
when "0100001110" => data <= "011111110";
when "0100001111" => data <= "011111110";
when "0100010000" => data <= "010010000";
when "0100010001" => data <= "000011001";
when "0100010010" => data <= "010010001";
when "0100010011" => data <= "000010100";
when "0100010100" => data <= "000100010";
when others => data <= (others =>'0');
end case;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_861 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_861;
architecture augh of cmp_861 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_861 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_861;
architecture augh of cmp_861 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
-- implementation of the HDB1 encoder.
entity hdb1_enc is
port (
clr_bar,
clk : in bit; -- clock input.
e : in bit; -- input.
s0, s1 : out bit -- output.
);
end hdb1_enc;
architecture behaviour of hdb1_enc is
signal q0, q1, q2 : bit; -- 3 flipflops for 6 states.
begin
process (clk, clr_bar) begin
if clr_bar = '0' then
q0 <= '0';
q1 <= '0';
q2 <= '0';
s0 <= '0';
s1 <= '0';
elsif clk'event and clk = '1' then
q0 <= (e and (not q1))
or ((not e) and (not q0) and q1 and q2 )
or ((not e) and q0 and q1 and (not q2) );
q1 <= (e and (not q1))
or ((not q1) and q2)
or ((not e) and q1 and (not q2));
q2 <= (not e) and (not q2);
s0 <= ((not q1) and (not q2))
or ((not e)and q1 and q2);
s1 <= (q1 and (not q2))
or ((not e) and (not q1) and q2);
end if;
end process;
end behaviour;
|
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`protect end_protected
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_2_block.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_2_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_3 : IN std_logic; -- ufix1
dout_3_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_3_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_11_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_11_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_3_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_4_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_4_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block IS
-- Signals
SIGNAL dout_3_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din1_re : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_3_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din1_im : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_11_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din2_re : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_11_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din2_im : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_3_re_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_3_im_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_4_re_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_4_im_tmp : signed(18 DOWNTO 0); -- sfix19
BEGIN
dout_3_re_signed <= signed(dout_3_re);
din1_re <= resize(dout_3_re_signed, 19);
dout_3_im_signed <= signed(dout_3_im);
din1_im <= resize(dout_3_im_signed, 19);
dout_11_re_signed <= signed(dout_11_re);
din2_re <= resize(dout_11_re_signed, 19);
dout_11_im_signed <= signed(dout_11_im);
din2_im <= resize(dout_11_im_signed, 19);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_3)
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_3 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 20) + resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 20) - resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 20) + resize(din2_re, 20);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 20) - resize(din2_re, 20);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 20) + resize(din2_re, 20);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 20) - resize(din2_re, 20);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 20) + resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 20) - resize(din2_im, 20);
END IF;
dout_3_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(18 DOWNTO 0);
dout_3_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(18 DOWNTO 0);
dout_4_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(18 DOWNTO 0);
dout_4_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(18 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_4_re <= std_logic_vector(dout_4_re_tmp);
dout_4_im <= std_logic_vector(dout_4_im_tmp);
dout_3_re_1 <= std_logic_vector(dout_3_re_tmp);
dout_3_im_1 <= std_logic_vector(dout_3_im_tmp);
END rtl;
|
-- A dual-port 2KiB RAM described as recommended by Xilinx
-- (C) Copyright 2011 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity dpram2k is
port(clka : in std_logic;
clkb : in std_logic;
ena : in std_logic;
enb : in std_logic;
wea : in std_logic;
web : in std_logic;
addra : in std_logic_vector(10 downto 0);
addrb : in std_logic_vector(10 downto 0);
dia : in std_logic_vector(7 downto 0);
dib : in std_logic_vector(7 downto 0);
doa : out std_logic_vector(7 downto 0);
dob : out std_logic_vector(7 downto 0));
end dpram2k;
architecture syn of dpram2k is
type ram_type is array (0 to 2047) of std_logic_vector(7 downto 0);
shared variable RAM : ram_type;
begin
process (CLKA)
begin
if CLKA'event and CLKA = '1' then
if ENA = '1' then
if WEA = '1' then
RAM(conv_integer(ADDRA)) := DIA;
end if;
DOA <= RAM(conv_integer(ADDRA));
end if;
end if;
end process;
process (CLKB)
begin
if CLKB'event and CLKB = '1' then
if ENB = '1' then
if WEB = '1' then
RAM(conv_integer(ADDRB)) := DIB;
end if;
DOB <= RAM(conv_integer(ADDRB));
end if;
end if;
end process;
end syn;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: atcpads_gen
-- File: atcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Atmel ATC18 pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package atcpads is
-- input pad
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
-- input pad with pull-up
component pc33d00uz port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad
component pc33d20z port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad with pull-up
component pt33d20uz port (pad : inout std_logic; cin : out std_logic); end component;
-- output pads
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
-- tri-state output pads
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
-- tri-state output pads with pull-up
component pt33t01uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08uz port (i, oen : in std_logic; pad : out std_logic); end component;
-- bidirectional pads
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
-- bidirectional pads with pull-up
component pt33b01uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
--PCI pads
component pp33o01z
port (i : in std_logic; pad : out std_logic);
end component;
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pc33d00z;
-- pragma translate_on
entity atc18_inpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_inpad is
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
begin
pci0 : if level = pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33b01z;
use atc18.pt33b01z;
use atc18.pt33b02z;
use atc18.pt33b08z;
use atc18.pt33b04z;
-- pragma translate_on
entity atc18_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of atc18_iopad is
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
begin
pci0 : if level = pci33 generate
op : pp33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
f1 : if (strength <= 4) generate
op : pt33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f2 : if (strength > 4) and (strength <= 8) generate
op : pt33b02z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f3 : if (strength > 8) and (strength <= 16) generate
op : pt33b04z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f4 : if (strength > 16) generate
op : pt33b08z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33o01z;
use atc18.pt33o02z;
use atc18.pt33o04z;
use atc18.pt33o08z;
-- pragma translate_on
entity atc18_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of atc18_outpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
signal gnd : std_logic;
begin
gnd <= '0';
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => gnd, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33o01z port map (i => i, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33o02z port map (i => i, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33o04z port map (i => i, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33o08z port map (i => i, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33t01z;
use atc18.pt33t02z;
use atc18.pt33t04z;
use atc18.pt33t08z;
-- pragma translate_on
entity atc18_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of atc18_toutpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
begin
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => en, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33t01z port map (i => i, oen => en, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33t02z port map (i => i, oen => en, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33t04z port map (i => i, oen => en, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33t08z port map (i => i, oen => en, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity atc18_clkpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_clkpad is
begin
o <= pad;
end;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_get_offset is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of sample_iterator_get_offset is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it12 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it13 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it14 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it15 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it16 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it17 : STD_LOGIC := '0';
signal i_sample_read_reg_130 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_130_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal indices_begin_addr_reg_135 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3 : STD_LOGIC_VECTOR (31 downto 0);
signal indices_stride_addr_read_reg_147 : STD_LOGIC_VECTOR (7 downto 0);
signal indices_begin_addr_read_reg_162 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_116_p2 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_8_reg_167 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_fu_93_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_116_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_116_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_125_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_125_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_116_ce : STD_LOGIC;
signal grp_fu_125_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_125_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
signal grp_fu_116_p00 : STD_LOGIC_VECTOR (23 downto 0);
signal grp_fu_116_p10 : STD_LOGIC_VECTOR (23 downto 0);
component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (23 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4_U0 : component nfa_accept_samples_generic_hw_mul_16ns_8ns_24_4
generic map (
ID => 0,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 8,
dout_WIDTH => 24)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_116_p0,
din1 => grp_fu_116_p1,
ce => grp_fu_116_ce,
dout => grp_fu_116_p2);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U1 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_125_p0,
din1 => grp_fu_125_p1,
ce => grp_fu_125_ce,
dout => grp_fu_125_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it12 assign process. --
ap_reg_ppiten_pp0_it12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it13 assign process. --
ap_reg_ppiten_pp0_it13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it14 assign process. --
ap_reg_ppiten_pp0_it14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it15 assign process. --
ap_reg_ppiten_pp0_it15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it16 assign process. --
ap_reg_ppiten_pp0_it16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it17 assign process. --
ap_reg_ppiten_pp0_it17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_sample_read_reg_130_pp0_it1 <= i_sample_read_reg_130;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it1;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it2;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it3;
ap_reg_ppstg_i_sample_read_reg_130_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_130_pp0_it4;
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(0) <= indices_begin_addr_reg_135(0);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(1) <= indices_begin_addr_reg_135(1);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(2) <= indices_begin_addr_reg_135(2);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(3) <= indices_begin_addr_reg_135(3);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(4) <= indices_begin_addr_reg_135(4);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(5) <= indices_begin_addr_reg_135(5);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(6) <= indices_begin_addr_reg_135(6);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(7) <= indices_begin_addr_reg_135(7);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(8) <= indices_begin_addr_reg_135(8);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(9) <= indices_begin_addr_reg_135(9);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(10) <= indices_begin_addr_reg_135(10);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(11) <= indices_begin_addr_reg_135(11);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(12) <= indices_begin_addr_reg_135(12);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(13) <= indices_begin_addr_reg_135(13);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(14) <= indices_begin_addr_reg_135(14);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(15) <= indices_begin_addr_reg_135(15);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(0) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(0);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(1) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(1);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(2) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(2);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(3) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(3);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(4) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(4);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(5) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(5);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(6) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(6);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(7) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(7);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(8) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(8);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(9) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(9);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(10) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(10);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(11) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(11);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(12) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(12);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(13) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(13);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(14) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(14);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(15) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(15);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(0) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(0);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(1) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(1);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(2) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(2);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(3) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(3);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(4) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(4);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(5) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(5);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(6) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(6);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(7) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(7);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(8) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(8);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(9) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(9);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(10) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(10);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(11) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(11);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(12) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(12);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(13) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(13);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(14) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(14);
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(15) <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_sample_read_reg_130 <= i_sample;
indices_begin_addr_reg_135(0) <= tmp_fu_93_p1(32 - 1 downto 0)(0);
indices_begin_addr_reg_135(1) <= tmp_fu_93_p1(32 - 1 downto 0)(1);
indices_begin_addr_reg_135(2) <= tmp_fu_93_p1(32 - 1 downto 0)(2);
indices_begin_addr_reg_135(3) <= tmp_fu_93_p1(32 - 1 downto 0)(3);
indices_begin_addr_reg_135(4) <= tmp_fu_93_p1(32 - 1 downto 0)(4);
indices_begin_addr_reg_135(5) <= tmp_fu_93_p1(32 - 1 downto 0)(5);
indices_begin_addr_reg_135(6) <= tmp_fu_93_p1(32 - 1 downto 0)(6);
indices_begin_addr_reg_135(7) <= tmp_fu_93_p1(32 - 1 downto 0)(7);
indices_begin_addr_reg_135(8) <= tmp_fu_93_p1(32 - 1 downto 0)(8);
indices_begin_addr_reg_135(9) <= tmp_fu_93_p1(32 - 1 downto 0)(9);
indices_begin_addr_reg_135(10) <= tmp_fu_93_p1(32 - 1 downto 0)(10);
indices_begin_addr_reg_135(11) <= tmp_fu_93_p1(32 - 1 downto 0)(11);
indices_begin_addr_reg_135(12) <= tmp_fu_93_p1(32 - 1 downto 0)(12);
indices_begin_addr_reg_135(13) <= tmp_fu_93_p1(32 - 1 downto 0)(13);
indices_begin_addr_reg_135(14) <= tmp_fu_93_p1(32 - 1 downto 0)(14);
indices_begin_addr_reg_135(15) <= tmp_fu_93_p1(32 - 1 downto 0)(15);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_addr_read_reg_162 <= indices_begin_datain;
tmp_8_reg_167 <= grp_fu_116_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_addr_read_reg_147 <= indices_stride_datain;
end if;
end if;
end process;
indices_begin_addr_reg_135(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it1(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it2(31 downto 16) <= "0000000000000000";
ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3(31 downto 16) <= "0000000000000000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it5 , ap_reg_ppiten_pp0_it9 , indices_stride_rsp_empty_n , indices_begin_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it17, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it17) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13, ap_reg_ppiten_pp0_it14, ap_reg_ppiten_pp0_it15, ap_reg_ppiten_pp0_it16, ap_reg_ppiten_pp0_it17)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it14) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it15) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it16) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it17))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return <= grp_fu_125_p2;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11, ap_reg_ppiten_pp0_it12, ap_reg_ppiten_pp0_it13, ap_reg_ppiten_pp0_it14, ap_reg_ppiten_pp0_it15, ap_reg_ppiten_pp0_it16)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it12) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it13) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it14) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it15) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it16) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- grp_fu_116_ce assign process. --
grp_fu_116_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_116_ce <= ap_const_logic_1;
else
grp_fu_116_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_116_p0 <= grp_fu_116_p00(16 - 1 downto 0);
grp_fu_116_p00 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_130_pp0_it5),24));
grp_fu_116_p1 <= grp_fu_116_p10(8 - 1 downto 0);
grp_fu_116_p10 <= std_logic_vector(resize(unsigned(indices_stride_addr_read_reg_147),24));
-- grp_fu_125_ce assign process. --
grp_fu_125_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_125_ce <= ap_const_logic_1;
else
grp_fu_125_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_125_p0 <= std_logic_vector(resize(unsigned(tmp_8_reg_167),32));
grp_fu_125_p1 <= indices_begin_addr_read_reg_162;
indices_begin_address <= ap_reg_ppstg_indices_begin_addr_reg_135_pp0_it3;
indices_begin_dataout <= ap_const_lv32_0;
indices_begin_req_din <= ap_const_logic_0;
-- indices_begin_req_write assign process. --
indices_begin_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it4) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_req_write <= ap_const_logic_1;
else
indices_begin_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_begin_rsp_read assign process. --
indices_begin_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_begin_rsp_read <= ap_const_logic_1;
else
indices_begin_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_begin_size <= ap_const_lv32_1;
indices_samples_address <= ap_const_lv32_0;
indices_samples_dataout <= ap_const_lv16_0;
indices_samples_req_din <= ap_const_logic_0;
indices_samples_req_write <= ap_const_logic_0;
indices_samples_rsp_read <= ap_const_logic_0;
indices_samples_size <= ap_const_lv32_0;
indices_stride_address <= tmp_fu_93_p1(32 - 1 downto 0);
indices_stride_dataout <= ap_const_lv8_0;
indices_stride_req_din <= ap_const_logic_0;
-- indices_stride_req_write assign process. --
indices_stride_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_req_write <= ap_const_logic_1;
else
indices_stride_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_stride_rsp_read assign process. --
indices_stride_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it9, indices_stride_rsp_empty_n, indices_begin_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_stride_rsp_empty_n = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and (indices_begin_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_stride_rsp_read <= ap_const_logic_1;
else
indices_stride_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_stride_size <= ap_const_lv32_1;
tmp_fu_93_p1 <= std_logic_vector(resize(unsigned(i_index),64));
end behav;
|
entity repro5 is
end repro5;
architecture behav of repro5 is
type my_rec is record
a : bit;
w : bit_vector (1 to 2);
end record;
procedure check (signal v : my_rec) is
begin
assert v.a = '0' and v.w = "01";
end check;
procedure pack (signal a : bit; signal w : bit_vector) is
begin
check (v.a => a,
v.w => w);
end pack;
signal sa : bit;
signal sw : bit_vector (1 to 2);
begin
process
begin
sa <= '0';
sw <= "01";
wait for 0 ns;
pack (sa, sw);
wait;
end process;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2634.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02634ent IS
END c13s03b01x00p02n01i02634ent;
ARCHITECTURE c13s03b01x00p02n01i02634arch OF c13s03b01x00p02n01i02634ent IS
BEGIN
TESTING: PROCESS
variable k/k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02634 - Identifier can not contain '/'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02634arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2634.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02634ent IS
END c13s03b01x00p02n01i02634ent;
ARCHITECTURE c13s03b01x00p02n01i02634arch OF c13s03b01x00p02n01i02634ent IS
BEGIN
TESTING: PROCESS
variable k/k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02634 - Identifier can not contain '/'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02634arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2634.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02634ent IS
END c13s03b01x00p02n01i02634ent;
ARCHITECTURE c13s03b01x00p02n01i02634arch OF c13s03b01x00p02n01i02634ent IS
BEGIN
TESTING: PROCESS
variable k/k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02634 - Identifier can not contain '/'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02634arch;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ab
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:20 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ab-rtl-a.vhd,v 1.3 2005/07/15 16:20:04 wig Exp $
-- $Date: 2005/07/15 16:20:04 $
-- $Log: ent_ab-rtl-a.vhd,v $
-- Revision 1.3 2005/07/15 16:20:04 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_ab
--
architecture rtl of ent_ab is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:03:00 05/17/2016
-- Design Name:
-- Module Name: pUe11 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pUe11 is
Port ( ax : in STD_LOGIC_VECTOR (2 downto 1);
ay : in STD_LOGIC_VECTOR (2 downto 1);
Xa : in STD_LOGIC_VECTOR (4 downto 1);
Ye : out STD_LOGIC_VECTOR (4 downto 1));
end pUe11;
architecture Behavioral of pUe11 is
signal V : STD_LOGIC;
begin
with ax select
V <= Xa(1) when "00",
Xa(2) when "01",
Xa(3) when "10",
Xa(4) when others;
with ay select
Ye <= "000" & V when "00",
"00" & V & "0" when "01",
"0" & V & "00" when "10",
V & "000" when others;
end Behavioral;
|
-- $Id: tb_nx_cram_memctl.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nx_cram_memctl - sim
-- Description: Test bench for nx_cram_memctl
--
-- Dependencies: vlib/simlib/simclk
-- vlib/simlib/simclkcnt
-- bplib/micron/mt45w8mw16b
-- tbd_nx_cram_memctl [UUT, abstact]
--
-- To test: nx_cram_memctl_as (via tbd_nx_cram_memctl_as)
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.4 use new simclk/simclkcnt
-- 2011-11-26 433 1.3 renamed from tb_n2_cram_memctl
-- 2011-11-21 432 1.2 now numeric_std clean; update O_FLA_CE_N usage
-- 2010-05-30 297 1.1 use abstact uut tbd_nx_cram_memctl
-- 2010-05-23 293 1.0 Initial version (derived from tb_s3_sram_memctl)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_nx_cram_memctl is
end tb_nx_cram_memctl;
architecture sim of tb_nx_cram_memctl is
component tbd_nx_cram_memctl is -- CRAM driver (abstract) [tb design]
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv22; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end component;
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal REQ : slbit := '0';
signal WE : slbit := '0';
signal BUSY : slbit := '0';
signal ACK_R : slbit := '0';
signal ACK_W : slbit := '0';
signal ACT_R : slbit := '0';
signal ACT_W : slbit := '0';
signal ADDR : slv22 := (others=>'0');
signal BE : slv4 := (others=>'0');
signal DI : slv32 := (others=>'0');
signal DO : slv32 := (others=>'0');
signal O_MEM_CE_N : slbit := '0';
signal O_MEM_BE_N : slv2 := (others=>'0');
signal O_MEM_WE_N : slbit := '0';
signal O_MEM_OE_N : slbit := '0';
signal O_MEM_ADV_N : slbit := '0';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'0');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal R_MEMON : slbit := '0';
signal N_CHK_DATA : slbit := '0';
signal N_REF_DATA : slv32 := (others=>'0');
signal N_REF_ADDR : slv22 := (others=>'0');
signal R_CHK_DATA_AL : slbit := '0';
signal R_REF_DATA_AL : slv32 := (others=>'0');
signal R_REF_ADDR_AL : slv22 := (others=>'0');
signal R_CHK_DATA_DL : slbit := '0';
signal R_REF_DATA_DL : slv32 := (others=>'0');
signal R_REF_ADDR_DL : slv22 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 7.5 ns; -- compatible ucf for
constant c2out_time : time := 12.0 ns; -- tbd_nx_cram_memctl_as
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
UUT : tbd_nx_cram_memctl
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
proc_stim: process
file fstim : text open read_mode is "tb_nx_cram_memctl_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable iaddr : slv22 := (others=>'0');
variable idata : slv32 := (others=>'0');
variable ibe : slv4 := (others=>'0');
variable ival : slbit := '0';
variable nbusy : integer := 0;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".memon" => -- .memon
read_ea(iline, ival);
R_MEMON <= ival;
wait for 2*clock_period;
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when "read " => -- read
readgen_ea(iline, iaddr, 16);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
REQ <= '1';
WE <= '0';
writetimestamp(oline, CLK_CYCLE, ": stim read ");
writegen(oline, iaddr, right, 7, 16);
write(oline, string'(" "));
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY='1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
N_CHK_DATA <= '1', '0' after clock_period;
N_REF_DATA <= idata;
N_REF_ADDR <= iaddr;
wait for clock_period;
REQ <= '0';
when "write " => -- write
readgen_ea(iline, iaddr, 16);
read_ea(iline, ibe);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
BE <= ibe;
DI <= idata;
REQ <= '1';
WE <= '1';
writetimestamp(oline, CLK_CYCLE, ": stim write");
writegen(oline, iaddr, right, 7, 16);
writegen(oline, ibe , right, 5, 2);
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
wait for clock_period;
REQ <= '0';
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file fstim
wait for 10*clock_period;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if ACK_R = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
writegen(oline, DO, right, 9, 16);
if R_CHK_DATA_DL = '1' then
write(oline, string'(" CHECK"));
if R_REF_DATA_DL = DO then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
writegen(oline, R_REF_DATA_DL, right, 9, 16);
write(oline, string'(" for a="));
writegen(oline, R_REF_ADDR_DL, right, 5, 16);
end if;
R_CHK_DATA_DL <= '0';
end if;
writeline(output, oline);
end if;
if R_CHK_DATA_AL = '1' then
R_CHK_DATA_DL <= R_CHK_DATA_AL;
R_REF_DATA_DL <= R_REF_DATA_AL;
R_REF_ADDR_DL <= R_REF_ADDR_AL;
R_CHK_DATA_AL <= '0';
end if;
if N_CHK_DATA = '1' then
R_CHK_DATA_AL <= N_CHK_DATA;
R_REF_DATA_AL <= N_REF_DATA;
R_REF_ADDR_AL <= N_REF_ADDR;
end if;
end loop;
end process proc_moni;
proc_memon: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MEMON = '1' then
writetimestamp(oline, CLK_CYCLE, ": mem ");
write(oline, string'(" ce="));
write(oline, not O_MEM_CE_N, right, 2);
write(oline, string'(" be="));
write(oline, not O_MEM_BE_N, right, 4);
write(oline, string'(" we="));
write(oline, not O_MEM_WE_N, right);
write(oline, string'(" oe="));
write(oline, not O_MEM_OE_N, right);
write(oline, string'(" a="));
writegen(oline, O_MEM_ADDR, right, 6, 16);
write(oline, string'(" d="));
writegen(oline, IO_MEM_DATA, right, 4, 16);
writeline(output, oline);
end if;
end loop;
end process proc_memon;
end sim;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2158.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02158ent IS
END c07s02b04x00p21n01i02158ent;
ARCHITECTURE c07s02b04x00p21n01i02158arch OF c07s02b04x00p21n01i02158ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_1 is severity_level_v (1 to 1);
SUBTYPE severity_level_null is severity_level_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : severity_level_1;
variable l_operand : severity_level := NOTE ;
variable r_operand : severity_level_null;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result(1)=NOTE)
report "***PASSED TEST: c07s02b04x00p21n01i02158"
severity NOTE;
assert (result(1)=NOTE)
report "***FAILED TEST: c07s02b04x00p21n01i02158 - Concatenation of null and SEVERITY_LEVEL element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02158arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2158.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02158ent IS
END c07s02b04x00p21n01i02158ent;
ARCHITECTURE c07s02b04x00p21n01i02158arch OF c07s02b04x00p21n01i02158ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_1 is severity_level_v (1 to 1);
SUBTYPE severity_level_null is severity_level_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : severity_level_1;
variable l_operand : severity_level := NOTE ;
variable r_operand : severity_level_null;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result(1)=NOTE)
report "***PASSED TEST: c07s02b04x00p21n01i02158"
severity NOTE;
assert (result(1)=NOTE)
report "***FAILED TEST: c07s02b04x00p21n01i02158 - Concatenation of null and SEVERITY_LEVEL element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02158arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2158.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02158ent IS
END c07s02b04x00p21n01i02158ent;
ARCHITECTURE c07s02b04x00p21n01i02158arch OF c07s02b04x00p21n01i02158ent IS
TYPE severity_level_v is array (integer range <>) of severity_level;
SUBTYPE severity_level_1 is severity_level_v (1 to 1);
SUBTYPE severity_level_null is severity_level_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : severity_level_1;
variable l_operand : severity_level := NOTE ;
variable r_operand : severity_level_null;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result(1)=NOTE)
report "***PASSED TEST: c07s02b04x00p21n01i02158"
severity NOTE;
assert (result(1)=NOTE)
report "***FAILED TEST: c07s02b04x00p21n01i02158 - Concatenation of null and SEVERITY_LEVEL element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02158arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2781.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ATTRIBUTE is
end ATTRIBUTE;
ENTITY c13s09b00x00p99n01i02781ent IS
END c13s09b00x00p99n01i02781ent;
ARCHITECTURE c13s09b00x00p99n01i02781arch OF c13s09b00x00p99n01i02781ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02781 - Reserved word ATTRIBUTE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02781arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2781.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ATTRIBUTE is
end ATTRIBUTE;
ENTITY c13s09b00x00p99n01i02781ent IS
END c13s09b00x00p99n01i02781ent;
ARCHITECTURE c13s09b00x00p99n01i02781arch OF c13s09b00x00p99n01i02781ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02781 - Reserved word ATTRIBUTE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02781arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2781.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ATTRIBUTE is
end ATTRIBUTE;
ENTITY c13s09b00x00p99n01i02781ent IS
END c13s09b00x00p99n01i02781ent;
ARCHITECTURE c13s09b00x00p99n01i02781arch OF c13s09b00x00p99n01i02781ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02781 - Reserved word ATTRIBUTE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02781arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 26.08.2016 16:22:30
-- Design Name:
-- Module Name: control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library SlowWorm;
use SlowWorm.SlowWorm.ALL;
entity control is
Port (
clk : in std_ulogic;
-- Instruction memory.
inst_mem_data : in data_t;
inst_mem_addr : out addr_t;
-- Data memory.
data_mem_data_read : in data_t;
data_mem_data_write : out data_t;
data_mem_addr : out addr_t;
data_mem_we : out std_ulogic;
-- Data stack.
dstack_data_read : in data_t;
dstack_data_write : out data_t;
dstack_push : out std_ulogic;
dstack_pop : out std_ulogic;
-- Return stack.
rstack_data_read : in data_t;
rstack_data_write : out data_t;
rstack_push : out std_ulogic;
rstack_pop : out std_ulogic
);
end control;
architecture Behavioral of control is
type state_t is (Reset, Fetch, Decode, Execute, Halt);
subtype instr_type_t is std_ulogic_vector(2 downto 0);
signal state : state_t := Reset;
signal data_addr, pc : addr_t;
signal instruction : data_t;
constant INSTR_TYPE_IMM_VAL : instr_type_t := "001";
constant INSTR_TYPE_LOGIC : instr_type_t := "011";
constant INSTR_TYPE_CONTROL : instr_type_t := "101";
constant INSTR_TYPE_UCODE : instr_type_t := "111";
begin
main: process (clk) is
-- General stuff used in decode state.
alias call_bit : std_ulogic is instruction(0);
alias instr_type : instr_type_t is instruction(2 downto 0);
variable call_address : addr_t;
variable is_call : boolean;
-- Used for Immediate Value instructions.
alias imm_stack : std_ulogic is instruction(3);
constant DATA_STACK : std_ulogic := '0';
alias imm_val : std_ulogic_vector(11 downto 0) is instruction(15 downto 4);
alias imm_sign_bit : std_ulogic is instruction(instruction'left);
variable imm_val_extended : data_t;
begin
if rising_edge(clk) then
-- Clear any control signals that cause a change of state in other modules.
dstack_push <= '0';
dstack_pop <= '0';
rstack_push <= '0';
rstack_pop <= '0';
data_mem_we <= '0';
case state is
when Reset =>
pc <= TO_UNSIGNED(0, pc'length);
inst_mem_addr <= TO_UNSIGNED(0, inst_mem_addr'length);
state <= Fetch;
-- Preconditions:
-- `inst_mem_addr` is loaded with the correct instruction memory address.
-- Postconditions:
-- `instruction` contains the next instruction to decode.
when Fetch =>
instruction <= inst_mem_data;
pc <= pc + 1;
state <= Decode;
when Decode =>
call_address := DATA_TO_ADDR(instruction(15 downto 0));
is_call := (call_bit = '0');
if is_call then
rstack_push <= '1';
rstack_data_write <= ADDR_TO_DATA(pc);
pc <= call_address;
inst_mem_addr <= call_address;
state <= Fetch;
else
case instr_type is
when INSTR_TYPE_IMM_VAL =>
imm_val_extended(imm_val'range) := imm_val;
imm_val_extended(imm_val_extended'left downto (imm_val'left + 1)) := (imm_val_extended'left downto (imm_val'left + 1) => imm_sign_bit);
if imm_stack = DATA_STACK then
dstack_push <= '1';
dstack_data_write <= imm_val_extended;
else
rstack_push <= '1';
rstack_data_write <= imm_val_extended;
end if;
inst_mem_addr <= pc;
state <= Fetch;
when INSTR_TYPE_LOGIC =>
--TODO. For now this is basically a no-op.
state <= Execute;
when INSTR_TYPE_CONTROL =>
--TODO. For now this is basically a no-op.
state <= Execute;
when INSTR_TYPE_UCODE =>
--TODO.
state <= Halt;
when others =>
-- something fucky has happened.
state <= Halt;
end case;
end if;
when Execute =>
inst_mem_addr <= pc;
state <= Fetch;
null; --TODO
when Halt =>
null;
end case;
end if;
end process;
end Behavioral;
|
-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_12;
USE proc_sys_reset_v5_0_12.proc_sys_reset;
ENTITY gcd_zynq_snick_rst_ps7_0_49M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END gcd_zynq_snick_rst_ps7_0_49M_0;
ARCHITECTURE gcd_zynq_snick_rst_ps7_0_49M_0_arch OF gcd_zynq_snick_rst_ps7_0_49M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF gcd_zynq_snick_rst_ps7_0_49M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END gcd_zynq_snick_rst_ps7_0_49M_0_arch;
|
-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_12;
USE proc_sys_reset_v5_0_12.proc_sys_reset;
ENTITY gcd_zynq_snick_rst_ps7_0_49M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END gcd_zynq_snick_rst_ps7_0_49M_0;
ARCHITECTURE gcd_zynq_snick_rst_ps7_0_49M_0_arch OF gcd_zynq_snick_rst_ps7_0_49M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF gcd_zynq_snick_rst_ps7_0_49M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END gcd_zynq_snick_rst_ps7_0_49M_0_arch;
|
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
|
--
-- General-purpose FIFO for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end entity fifo;
architecture behave of fifo is
type mem_t is array (0 to ((2**bits)-1)) of std_logic_vector(7 downto 0);
signal memory: mem_t;
signal wraddr: unsigned(bits-1 downto 0);
signal rdaddr: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
read <= memory( conv_integer(std_logic_vector(rdaddr)) );
end if;
end process;
process(clk,rdaddr,wraddr,rst)
variable full_v: std_logic;
variable empty_v: std_logic;
begin
if rdaddr=wraddr then
empty_v:='1';
else
empty_v:='0';
end if;
if wraddr=rdaddr-1 then
full_v:='1';
else
full_v:='0';
end if;
if rising_edge(clk) then
if rst='1' then
wraddr <= (others => '0');
rdaddr <= (others => '0');
else
if wr='1' and full_v='0' then
memory(conv_integer(std_logic_vector(wraddr) ) ) <= write;
wraddr <= wraddr+1;
end if;
if rd='1' and empty_v='0' then
rdaddr <= rdaddr+1;
end if;
end if;
full <= full_v;
empty <= empty_v;
end if;
end process;
end behave;
|
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