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-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_cache is
end entity tb_cache;
architecture test of tb_cache is
signal halt : bit := '0';
begin
dut : entity work.cache(instrumented)
generic map ( cache_size => 128*1024, block_size => 16,
associativity => 2, benchmark_name => "dhrystone " )
port map ( halt => halt );
halt <= '1' after 10 ns;
end architecture test;
entity tb_cache_read_data is
end entity tb_cache_read_data;
architecture reader of tb_cache_read_data is
begin
process is
type measurement_record is
record
cache_size, block_size, associativity : positive;
benchmark_name : string(1 to 10);
miss_rate : real;
ave_access_time : delay_length;
end record;
type measurement_file is file of measurement_record;
file measurements : measurement_file open read_mode is "cache-measurements";
variable measurement : measurement_record;
use std.textio.all;
variable L : line;
begin
while not endfile(measurements) loop
read(measurements, measurement);
write(L, measurement.cache_size);
write(L, ' ');
write(L, measurement.block_size);
write(L, ' ');
write(L, measurement.associativity);
write(L, ' ');
write(L, measurement.benchmark_name);
write(L, ' ');
write(L, measurement.miss_rate);
write(L, ' ');
write(L, measurement.ave_access_time);
writeline(output, L);
end loop;
wait;
end process;
end architecture reader;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_cache is
end entity tb_cache;
architecture test of tb_cache is
signal halt : bit := '0';
begin
dut : entity work.cache(instrumented)
generic map ( cache_size => 128*1024, block_size => 16,
associativity => 2, benchmark_name => "dhrystone " )
port map ( halt => halt );
halt <= '1' after 10 ns;
end architecture test;
entity tb_cache_read_data is
end entity tb_cache_read_data;
architecture reader of tb_cache_read_data is
begin
process is
type measurement_record is
record
cache_size, block_size, associativity : positive;
benchmark_name : string(1 to 10);
miss_rate : real;
ave_access_time : delay_length;
end record;
type measurement_file is file of measurement_record;
file measurements : measurement_file open read_mode is "cache-measurements";
variable measurement : measurement_record;
use std.textio.all;
variable L : line;
begin
while not endfile(measurements) loop
read(measurements, measurement);
write(L, measurement.cache_size);
write(L, ' ');
write(L, measurement.block_size);
write(L, ' ');
write(L, measurement.associativity);
write(L, ' ');
write(L, measurement.benchmark_name);
write(L, ' ');
write(L, measurement.miss_rate);
write(L, ' ');
write(L, measurement.ave_access_time);
writeline(output, L);
end loop;
wait;
end process;
end architecture reader;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_cache is
end entity tb_cache;
architecture test of tb_cache is
signal halt : bit := '0';
begin
dut : entity work.cache(instrumented)
generic map ( cache_size => 128*1024, block_size => 16,
associativity => 2, benchmark_name => "dhrystone " )
port map ( halt => halt );
halt <= '1' after 10 ns;
end architecture test;
entity tb_cache_read_data is
end entity tb_cache_read_data;
architecture reader of tb_cache_read_data is
begin
process is
type measurement_record is
record
cache_size, block_size, associativity : positive;
benchmark_name : string(1 to 10);
miss_rate : real;
ave_access_time : delay_length;
end record;
type measurement_file is file of measurement_record;
file measurements : measurement_file open read_mode is "cache-measurements";
variable measurement : measurement_record;
use std.textio.all;
variable L : line;
begin
while not endfile(measurements) loop
read(measurements, measurement);
write(L, measurement.cache_size);
write(L, ' ');
write(L, measurement.block_size);
write(L, ' ');
write(L, measurement.associativity);
write(L, ' ');
write(L, measurement.benchmark_name);
write(L, ' ');
write(L, measurement.miss_rate);
write(L, ' ');
write(L, measurement.ave_access_time);
writeline(output, L);
end loop;
wait;
end process;
end architecture reader;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/Complex3Multiply_block2.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block2
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block2 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din2_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din2_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
di2_vld_dly3 : IN std_logic;
twdl_3_6_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_6_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_6_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_6_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin2_vld : OUT std_logic
);
END Complex3Multiply_block2;
ARCHITECTURE rtl OF Complex3Multiply_block2 IS
-- Signals
SIGNAL din2_re_dly3_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly3_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL din_sum : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdl_3_6_re_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_re_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_6_im_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_im_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL adder_add_cast : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL adder_add_cast_1 : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL twdl_sum : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL prodOfRe : signed(33 DOWNTO 0); -- sfix34_En15
SIGNAL prodOfIm : signed(33 DOWNTO 0); -- sfix34_En15
SIGNAL prodOfSum : signed(35 DOWNTO 0); -- sfix36_En15
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_multRes_re_reg1 : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_multRes_re_reg2 : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_multRes_im_reg : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_tmpResult_reg_next : signed(35 DOWNTO 0); -- sfix36_En15
SIGNAL Complex3Add_multRes_re_reg1_next : signed(34 DOWNTO 0); -- sfix35_En15
SIGNAL Complex3Add_multRes_re_reg2_next : signed(34 DOWNTO 0); -- sfix35_En15
SIGNAL Complex3Add_multRes_im_reg_next : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(35 DOWNTO 0); -- sfix36_En15
SIGNAL multResFP_re : signed(34 DOWNTO 0); -- sfix35_En15
SIGNAL multResFP_im : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL twdlXdin_6_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_6_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
din2_re_dly3_signed <= signed(din2_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 17);
ELSE
din_re_reg <= din2_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din2_im_dly3_signed <= signed(din2_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 17);
ELSE
din_im_reg <= din2_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
din_sum <= resize(din_re_reg, 18) + resize(din_im_reg, 18);
twdl_3_6_re_signed <= signed(twdl_3_6_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSE
twdl_re_reg <= twdl_3_6_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_6_im_signed <= signed(twdl_3_6_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSE
twdl_im_reg <= twdl_3_6_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast <= resize(twdl_re_reg, 18);
adder_add_cast_1 <= resize(twdl_im_reg, 18);
twdl_sum <= adder_add_cast + adder_add_cast_1;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly1 <= di2_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 36);
Complex3Add_tmpResult_reg <= to_signed(0, 36);
Complex3Add_multRes_re_reg1 <= to_signed(0, 35);
Complex3Add_multRes_re_reg2 <= to_signed(0, 35);
Complex3Add_multRes_im_reg <= to_signed(0, 37);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(34 DOWNTO 0);
VARIABLE sub_cast_0 : signed(34 DOWNTO 0);
VARIABLE sub_cast_1 : signed(36 DOWNTO 0);
VARIABLE sub_cast_2 : signed(36 DOWNTO 0);
VARIABLE add_cast : signed(34 DOWNTO 0);
VARIABLE add_cast_0 : signed(34 DOWNTO 0);
VARIABLE add_temp : signed(34 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 35);
sub_cast_0 := resize(prodOfIm, 35);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 37);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 37);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 35);
add_cast_0 := resize(prodOfIm, 35);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 36);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin2_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_6_re_tmp <= multResFP_re(31 DOWNTO 15);
twdlXdin_6_re <= std_logic_vector(twdlXdin_6_re_tmp);
twdlXdin_6_im_tmp <= multResFP_im(31 DOWNTO 15);
twdlXdin_6_im <= std_logic_vector(twdlXdin_6_im_tmp);
END rtl;
|
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.myDeclare.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_async_com_control IS
END TB_async_com_control;
ARCHITECTURE behavior OF TB_async_com_control IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT async_com_control
PORT(
bus_clk : IN std_logic;
reset : IN std_logic;
conf_ack : IN std_logic;
conf_nack : IN std_logic;
conf_done : IN std_logic;
async_fifo_wr_enb : out std_logic;
async_fifo_wr_data : out std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal bus_clk : std_logic := '0';
signal reset : std_logic := '0';
signal hs_start : std_logic := '0';
signal conf_ack : std_logic := '0';
signal conf_nack : std_logic := '0';
signal conf_done : std_logic := '0';
signal async_fifo_wr_enb : std_logic;
signal async_fifo_wr_data : std_logic_vector(7 downto 0);
-- Clock period definitions
constant bus_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: async_com_control PORT MAP (
bus_clk => bus_clk,
reset => reset,
hs_start => hs_start,
conf_ack => conf_ack,
conf_nack => conf_nack,
conf_done => conf_done,
async_fifo_wr_enb => async_fifo_wr_enb,
async_fifo_wr_data => async_fifo_wr_data
);
-- Clock process definitions
bus_clk_process :process
begin
bus_clk <= '0';
wait for bus_clk_period/2;
bus_clk <= '1';
wait for bus_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for bus_clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- fifo_out_8b_sync_1.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fifo_out_8b_sync_1 is
port (
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_slave_0.address
in_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
wr_en : in std_logic := '0'; -- .write
out_data : out std_logic_vector(31 downto 0); -- .readdata
wait_req : out std_logic; -- .waitrequest
byte_en : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
st_data : out std_logic_vector(7 downto 0); -- avalon_streaming_source.data
st_ready : in std_logic := '0'; -- .ready
st_valid : out std_logic; -- .valid
irq : out std_logic -- conduit_end.export
);
end entity fifo_out_8b_sync_1;
architecture rtl of fifo_out_8b_sync_1 is
component fifo_out_8b_sync is
generic (
FIFO_DEPTH : integer := 16;
BUS_WIDTH : integer := 32
);
port (
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
wr_en : in std_logic := 'X'; -- write
out_data : out std_logic_vector(31 downto 0); -- readdata
wait_req : out std_logic; -- waitrequest
byte_en : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
st_data : out std_logic_vector(7 downto 0); -- data
st_ready : in std_logic := 'X'; -- ready
st_valid : out std_logic; -- valid
irq : out std_logic -- export
);
end component fifo_out_8b_sync;
begin
fifo_out_8b_sync_1 : component fifo_out_8b_sync
generic map (
FIFO_DEPTH => 16,
BUS_WIDTH => 32
)
port map (
addr => addr, -- avalon_slave_0.address
in_data => in_data, -- .writedata
wr_en => wr_en, -- .write
out_data => out_data, -- .readdata
wait_req => wait_req, -- .waitrequest
byte_en => byte_en, -- .byteenable
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
st_data => st_data, -- avalon_streaming_source.data
st_ready => st_ready, -- .ready
st_valid => st_valid, -- .valid
irq => irq -- conduit_end.export
);
end architecture rtl; -- of fifo_out_8b_sync_1
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
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-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
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--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(13-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 32,
C_DOUT_WIDTH => 256,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 32,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 32,
C_WR_PNTR_WIDTH => 14,
C_RD_PNTR_WIDTH => 11,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : read_data_fifo_0_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity U232C_SEND is
generic (
WTIME : std_logic_vector(15 downto 0) := x"1ADB");
port (
CLK : in std_logic;
GO : in std_logic;
DATA : in std_logic_vector (7 downto 0);
TX : out std_logic;
SENT : out std_logic);
end U232C_SEND;
architecture blackbox of U232C_SEND is
signal countdown : std_logic_vector(15 downto 0) := WTIME;
signal sendbuf : std_logic_vector(8 downto 0) := (others => '1');
signal state : integer range 0 to 10 := 10;
signal sig_sent : std_logic := '1';
begin
SENT <= sig_sent;
TX <= sendbuf(0);
statemachine : process(CLK)
begin
if rising_edge(CLK) then
case state is
when 10 =>
if GO = '1' then
sendbuf <= DATA&"0";
sig_sent <= '0';
countdown <= WTIME;
state <= state-1;
end if;
when 0 =>
if countdown = 0 then
sig_sent <= '1';
state <= 10;
else
countdown <= countdown-1;
end if;
when others =>
if countdown = 0 then
sendbuf <= "1"&sendbuf(8 downto 1);
countdown <= WTIME;
state <= state-1;
else
countdown <= countdown-1;
end if;
end case;
end if;
end process;
end blackbox;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-09 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_06500_bad.vhd
-- File Creation date : 2015-04-09
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Counters end of counting: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_06500_bad is
port (
i_Clock : in std_logic; -- Main clock signal
i_Reset_n : in std_logic; -- Main reset signal
i_Enable : in std_logic; -- Enables the counter
i_Length : in std_logic_vector(3 downto 0); -- Unsigned Value for Counter Period
o_Count : out std_logic_vector(3 downto 0) -- Counter (unsigned value)
);
end STD_06500_bad;
--CODE
architecture Behavioral of STD_06500_bad is
signal Count : unsigned(3 downto 0); -- Counter output signal (unsigned converted)
signal Count_Length : unsigned(3 downto 0); -- Length input signal (unsigned converted)
begin
Count_Length <= unsigned(i_Length);
-- Will count undefinitely from 0 to i_Length while i_Enable is asserted
P_Count : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Count <= (others => '0');
elsif (rising_edge(i_Clock)) then
if (Count = Count_Length) then -- Counter restarts from 0
Count <= (others => '0');
elsif (i_Enable = '1') then -- Increment counter value
Count <= Count + 1;
end if;
end if;
end process;
o_Count <= std_logic_vector(Count);
end Behavioral;
--CODE
|
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- This file describes the implementation of a generic equalizer. This --
-- equaliser is made up out of three second order, direct IIR-filters with --
-- multipliers between. --
-- --
-- --
-- Generic: --
-- DATA_WIDTH - The width of the input data, output data as well --
-- as the data signals between the IIR-filters and --
-- multipliers --
-- DATA_FRACT - The factrional width of above data --
-- --
-- SCALE_WIDTH_1 - Data width of the first scaling factor --
-- SCALE_FRACT_1 - Fractional width of the first scaling factor --
-- SCALE_WIDTH_2 - Data width of the second scaling factor --
-- SCALE_FRACT_2 - Fractional width of the second scaling factor --
-- SCALE_WIDTH_3 - Data width of the third scaling factor --
-- SCALE_FRACT_3 - Fractional width of the third scaling factor --
-- SCALE_WIDTH_4 - Data width of the fourth scaling factor --
-- SCALE_FRACT_4 - Fractional width of the fourth scaling factor --
-- --
-- INTERNAL_IIR_WIDTH_1 - Width of the internal calculations within the --
-- first IIR-filter --
-- INTERNAL_IIR_FRACT_1 - Fractional width of the internal calculations --
-- within the first IIR-filter --
-- INTERNAL_IIR_WIDTH_2 - Width of the internal calculations within the --
-- second IIR-filter --
-- INTERNAL_IIR_FRACT_2 - Fractional width of the internal calculations --
-- within the second IIR-filter --
-- INTERNAL_IIR_WIDTH_3 - Width of the internal calculations within the --
-- third IIR-filter --
-- INTERNAL_IIR_FRACT_3 - Fractional width of the internal calculations --
-- within the third IIR-filter --
-- --
-- COEFF_WIDTH_1 - Width of the coefficients used in the first --
-- IIR-filter --
-- COEFF_FRACT_1 - Fractional width of the coefficients used in the --
-- first IIR-filter --
-- COEFF_WIDTH_2 - Width of the coefficients used in the second --
-- IIR-filter --
-- COEFF_FRACT_2 - Fractional width of the coefficients used in the --
-- second IIR-filter --
-- COEFF_WIDTH_3 - Width of the coefficients used in the third --
-- IIR-filter --
-- COEFF_FRACT_3 - Fractional width of the coefficients used in the --
-- third IIR-filter --
-- --
-- --
-- Input/Output: --
-- clk - System clock --
-- reset - Resets component when high --
-- write_mode - Write new coefficients when high --
-- x - Input --
-- --
-- scale_1 - First scaling factor --
-- scale_2 - Second scaling factor --
-- scale_3 - Third scaling factor --
-- scale_4 - Fourth scaling factor --
-- --
-- b0_1 - B coefficient of the first IIR filter --
-- b1_1 - B coefficient of the first IIR filter --
-- b2_1 - B coefficient of the first IIR filter --
-- a1_1 - A coefficient of the first IIR filter --
-- a2_1 - A coefficient of the first IIR filter --
-- --
-- b0_2 - B coefficient of the second IIR filter --
-- b1_2 - B coefficient of the second IIR filter --
-- b2_2 - B coefficient of the second IIR filter --
-- a1_2 - A coefficient of the second IIR filter --
-- a2_2 - A coefficient of the second IIR filter --
-- --
-- b0_3 - B coefficient of the third IIR filter --
-- b1_3 - B coefficient of the third IIR filter --
-- b2_3 - B coefficient of the third IIR filter --
-- a1_3 - A coefficient of the third IIR filter --
-- a2_3 - A coefficient of the third IIR filter --
-- --
-- y - Output --
-- --
-- --
-- Internal Constants: --
-- N - Number of coefficients, this number is three for a --
-- second order filter and should not be changed. The --
-- constant is mearly there to simplify creation of --
-- higher order filters. Note that for this to be done --
-- successfully, you have to increase the number of --
-- coefficients as well. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Equalizer is
generic (DATA_WIDTH : natural := 8;
DATA_FRACT : natural := 6;
SCALE_WIDTH_1 : natural := 8;
SCALE_FRACT_1 : natural := 6;
SCALE_WIDTH_2 : natural := 8;
SCALE_FRACT_2 : natural := 6;
SCALE_WIDTH_3 : natural := 8;
SCALE_FRACT_3 : natural := 6;
SCALE_WIDTH_4 : natural := 8;
SCALE_FRACT_4 : natural := 6;
INTERNAL_IIR_WIDTH_1 : natural := 12;
INTERNAL_IIR_FRACT_1 : natural := 8;
INTERNAL_IIR_WIDTH_2 : natural := 12;
INTERNAL_IIR_FRACT_2 : natural := 8;
INTERNAL_IIR_WIDTH_3 : natural := 12;
INTERNAL_IIR_FRACT_3 : natural := 8;
COEFF_WIDTH_1 : natural := 8;
COEFF_FRACT_1 : natural := 6;
COEFF_WIDTH_2 : natural := 8;
COEFF_FRACT_2 : natural := 6;
COEFF_WIDTH_3 : natural := 8;
COEFF_FRACT_3 : natural := 6);
port(clk : in std_logic;
reset : in std_logic;
x : in std_logic_vector(DATA_WIDTH-1 downto 0);
scale_1 : in std_logic_vector(SCALE_WIDTH_1-1 downto 0);
scale_2 : in std_logic_vector(SCALE_WIDTH_2-1 downto 0);
scale_3 : in std_logic_vector(SCALE_WIDTH_3-1 downto 0);
scale_4 : in std_logic_vector(SCALE_WIDTH_4-1 downto 0);
b0_1 : in std_logic_vector(COEFF_WIDTH_1-1 downto 0);
b1_1 : in std_logic_vector(COEFF_WIDTH_1-1 downto 0);
b2_1 : in std_logic_vector(COEFF_WIDTH_1-1 downto 0);
a1_1 : in std_logic_vector(COEFF_WIDTH_1-1 downto 0);
a2_1 : in std_logic_vector(COEFF_WIDTH_1-1 downto 0);
b0_2 : in std_logic_vector(COEFF_WIDTH_2-1 downto 0);
b1_2 : in std_logic_vector(COEFF_WIDTH_2-1 downto 0);
b2_2 : in std_logic_vector(COEFF_WIDTH_2-1 downto 0);
a1_2 : in std_logic_vector(COEFF_WIDTH_2-1 downto 0);
a2_2 : in std_logic_vector(COEFF_WIDTH_2-1 downto 0);
b0_3 : in std_logic_vector(COEFF_WIDTH_3-1 downto 0);
b1_3 : in std_logic_vector(COEFF_WIDTH_3-1 downto 0);
b2_3 : in std_logic_vector(COEFF_WIDTH_3-1 downto 0);
a1_3 : in std_logic_vector(COEFF_WIDTH_3-1 downto 0);
a2_3 : in std_logic_vector(COEFF_WIDTH_3-1 downto 0);
y : out std_logic_vector(DATA_WIDTH-1 downto 0));
end Equalizer;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Equalizer is
-- Signals ---------------------------------------------------------------------
signal s_scale_1 : std_logic_vector(SCALE_WIDTH_1-1 downto 0);
signal s_scale_2 : std_logic_vector(SCALE_WIDTH_2-1 downto 0);
signal s_scale_3 : std_logic_vector(SCALE_WIDTH_3-1 downto 0);
signal s_scale_4 : std_logic_vector(SCALE_WIDTH_4-1 downto 0);
signal s_b0_1 : std_logic_vector(COEFF_WIDTH_1-1 downto 0);
signal s_b1_1 : std_logic_vector(COEFF_WIDTH_1-1 downto 0);
signal s_b2_1 : std_logic_vector(COEFF_WIDTH_1-1 downto 0);
signal s_a1_1 : std_logic_vector(COEFF_WIDTH_1-1 downto 0);
signal s_a2_1 : std_logic_vector(COEFF_WIDTH_1-1 downto 0);
signal s_b0_2 : std_logic_vector(COEFF_WIDTH_2-1 downto 0);
signal s_b1_2 : std_logic_vector(COEFF_WIDTH_2-1 downto 0);
signal s_b2_2 : std_logic_vector(COEFF_WIDTH_2-1 downto 0);
signal s_a1_2 : std_logic_vector(COEFF_WIDTH_2-1 downto 0);
signal s_a2_2 : std_logic_vector(COEFF_WIDTH_2-1 downto 0);
signal s_b0_3 : std_logic_vector(COEFF_WIDTH_3-1 downto 0);
signal s_b1_3 : std_logic_vector(COEFF_WIDTH_3-1 downto 0);
signal s_b2_3 : std_logic_vector(COEFF_WIDTH_3-1 downto 0);
signal s_a1_3 : std_logic_vector(COEFF_WIDTH_3-1 downto 0);
signal s_a2_3 : std_logic_vector(COEFF_WIDTH_3-1 downto 0);
signal iir_input_1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal iir_input_2 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal iir_input_3 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal iir_output_1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal iir_output_2 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal iir_output_3 : std_logic_vector(DATA_WIDTH-1 downto 0);
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
begin
-- Set coefficients
s_scale_1 <= scale_1;
s_scale_2 <= scale_2;
s_scale_3 <= scale_3;
s_scale_4 <= scale_4;
s_b0_1 <= b0_1;
s_b1_1 <= b1_1;
s_b2_1 <= b2_1;
s_a1_1 <= a1_1;
s_a2_1 <= a2_1;
s_b0_2 <= b0_2;
s_b1_2 <= b1_2;
s_b2_2 <= b2_2;
s_a1_2 <= a1_2;
s_a2_2 <= a2_2;
s_b0_3 <= b0_3;
s_b1_3 <= b1_3;
s_b2_3 <= b2_3;
s_a1_3 <= a1_3;
s_a2_3 <= a2_3;
-- Stage 1 -------------------------------------------------------------------
Multiplier_1 : entity work.Multiplier
generic map(X_WIDTH => DATA_WIDTH,
X_FRACTION => DATA_FRACT,
Y_WIDTH => SCALE_WIDTH_1,
Y_FRACTION => SCALE_FRACT_1,
S_WIDTH => DATA_WIDTH,
S_FRACTION => DATA_FRACT)
port map(x => x,
y => s_scale_1,
s => iir_input_1);
Generic_IIR_SO_1 : entity work.Generic_IIR_SO
generic map(IN_WIDTH => DATA_WIDTH,
IN_FRACT => DATA_FRACT,
COEFFICIENT_WIDTH => COEFF_WIDTH_1,
COEFFICIENT_FRACT => COEFF_FRACT_1,
INTERNAL_WIDTH => INTERNAL_IIR_WIDTH_1,
INTERNAL_FRACT => INTERNAL_IIR_FRACT_1,
OUT_WIDTH => DATA_WIDTH,
OUT_FRACT => DATA_FRACT)
port map(clk => clk,
reset => reset,
x => iir_input_1,
B0 => s_b0_1,
B1 => s_b1_1,
B2 => s_b2_1,
A1 => s_a1_1,
A2 => s_a2_1,
y => iir_output_1);
-- Stage 2 -------------------------------------------------------------------
Multiplier_2 : entity work.Multiplier
generic map(X_WIDTH => DATA_WIDTH,
X_FRACTION => DATA_FRACT,
Y_WIDTH => SCALE_WIDTH_2,
Y_FRACTION => SCALE_FRACT_2,
S_WIDTH => DATA_WIDTH,
S_FRACTION => DATA_FRACT)
port map(x => iir_output_1,
y => s_scale_2,
s => iir_input_2);
Generic_IIR_SO_2 : entity work.Generic_IIR_SO
generic map(IN_WIDTH => DATA_WIDTH,
IN_FRACT => DATA_FRACT,
COEFFICIENT_WIDTH => COEFF_WIDTH_2,
COEFFICIENT_FRACT => COEFF_FRACT_2,
INTERNAL_WIDTH => INTERNAL_IIR_WIDTH_2,
INTERNAL_FRACT => INTERNAL_IIR_FRACT_2,
OUT_WIDTH => DATA_WIDTH,
OUT_FRACT => DATA_FRACT)
port map(clk => clk,
reset => reset,
x => iir_input_2,
B0 => s_b0_2,
B1 => s_b1_2,
B2 => s_b2_2,
A1 => s_a1_2,
A2 => s_a2_2,
y => iir_output_2);
-- Stage 3 -------------------------------------------------------------------
Multiplier_3 : entity work.Multiplier
generic map(X_WIDTH => DATA_WIDTH,
X_FRACTION => DATA_FRACT,
Y_WIDTH => SCALE_WIDTH_3,
Y_FRACTION => SCALE_FRACT_3,
S_WIDTH => DATA_WIDTH,
S_FRACTION => DATA_FRACT)
port map(x => iir_output_2,
y => s_scale_3,
s => iir_input_3);
Generic_IIR_SO_3 : entity work.Generic_IIR_SO
generic map(IN_WIDTH => DATA_WIDTH,
IN_FRACT => DATA_FRACT,
COEFFICIENT_WIDTH => COEFF_WIDTH_3,
COEFFICIENT_FRACT => COEFF_FRACT_3,
INTERNAL_WIDTH => INTERNAL_IIR_WIDTH_3,
INTERNAL_FRACT => INTERNAL_IIR_FRACT_3,
OUT_WIDTH => DATA_WIDTH,
OUT_FRACT => DATA_FRACT)
port map(clk => clk,
reset => reset,
x => iir_input_3,
B0 => s_b0_3,
B1 => s_b1_3,
B2 => s_b2_3,
A1 => s_a1_3,
A2 => s_a2_3,
y => iir_output_3);
-- Stage 4 -------------------------------------------------------------------
Multiplier_4 : entity work.Multiplier
generic map(X_WIDTH => DATA_WIDTH,
X_FRACTION => DATA_FRACT,
Y_WIDTH => SCALE_WIDTH_4,
Y_FRACTION => SCALE_FRACT_4,
S_WIDTH => DATA_WIDTH,
S_FRACTION => DATA_FRACT)
port map(x => iir_output_3,
y => s_scale_4,
s => y);
end architecture; |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:13:47 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_rst_ps7_0_100M_0/system_rst_ps7_0_100M_0_stub.vhdl
-- Design : system_rst_ps7_0_100M_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rst_ps7_0_100M_0 is
Port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_rst_ps7_0_100M_0;
architecture stub of system_rst_ps7_0_100M_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2016.4";
begin
end;
|
--
-- Test READ for real types
--
entity textio7 is
end entity;
use std.textio.all;
architecture test of textio7 is
procedure check(value, expect : real) is
variable l : line;
begin
assert abs(value - expect) < 0.0001
report "value=" & real'image(value) & " expect=" & real'image(expect)
severity failure;
write(l, value);
writeline(output, l);
deallocate(l);
end procedure;
begin
main: process is
variable r : real;
variable l : line;
begin
l := new string'("1.23");
read(l, r);
check(r, 1.23);
deallocate(l);
l := new string'("+4");
read(l, r);
check(r, 4.0);
deallocate(l);
l := new string'("-0.001");
read(l, r);
check(r, -0.001);
deallocate(l);
l := new string'("1.23e2");
read(l, r);
check(r, 123.0);
deallocate(l);
l := new string'("1.994500e+03");
read(l, r);
check(r, 1994.5);
deallocate(l);
l := new string'(" 1.994500e+03");
read(l, r);
check(r, 1994.5);
deallocate(l);
wait;
end process;
end architecture;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 22:04:02 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_0_stub.vhdl
-- Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awid[11:0],s_axi_awaddr[12:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock,s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[12:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock,s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[12:0],bram_wrdata_a[31:0],bram_rddata_a[31:0],bram_rst_b,bram_clk_b,bram_en_b,bram_we_b[3:0],bram_addr_b[12:0],bram_wrdata_b[31:0],bram_rddata_b[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_bram_ctrl,Vivado 2017.2.1";
begin
end;
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32 -- Comment
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32); -- Comment should stay
PORT (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1');
end entity FIFO;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
ENTITY IFID_register_tb IS
END IFID_register_tb;
ARCHITECTURE behavior OF IFID_register_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IFID_register
port
(Clk, reset : in std_logic;
instruction_i, pc_i: in std_logic_vector(31 downto 0);
instruction_o, pc_o : out std_logic_vector(31 downto 0));
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal instruction_i, pc_i : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal instruction_o, pc_o : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IFID_register PORT MAP (
clk => clk,
reset => reset,
instruction_i => instruction_i,
instruction_o => instruction_o,
pc_i => pc_i,
pc_o => pc_o
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
-- write some data
wait for clk_period/2;
pc_i <= x"1000_1000";
instruction_i <= x"0101_0101";
wait for clk_period;
pc_i <= x"FEDC_BA98";
instruction_i <= x"F00F_F00F";
wait for clk_period*2;
assert false report "end of simulation" severity failure;
wait;
end process;
END; |
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity bin_to_gray is
generic (N: natural := 3);
port (
bin: in std_logic_vector(N-1 downto 0);
gray: out std_logic_vector(N-1 downto 0));
end entity bin_to_gray;
--------------------------------------
architecture circuit of bin_to_gray is
--signals and declarations
begin
gray(N-1) <= bin(N-1);
gen: for i in 1 to N-1 generate
gray(N-1 - i) <= bin(N-1) xor bin(N-1 - i);
end generate gen;
end architecture circuit;
--------------------------------------
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
-------------------------------------------------------------------------------
--
-- File: SyncAsyncReset.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a reset-bridge. It takes a reset signal asynchronous to the
-- target clock domain (OutClk) and provides a safe asynchronous or synchronous
-- reset for the OutClk domain (oRst). The signal oRst is asserted immediately
-- as aRst arrives, but is de-asserted synchronously with the OutClk rising
-- edge. This means it can be used to safely reset any FF in the OutClk domain,
-- respecting recovery time specs for FFs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ResetBridge is
Generic (
kPolarity : std_logic := '1');
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
oRst : out STD_LOGIC);
end ResetBridge;
architecture Behavioral of ResetBridge is
signal aRst_int : std_logic;
attribute KEEP : string;
attribute KEEP of aRst_int: signal is "TRUE";
begin
aRst_int <= kPolarity xnor aRst; --SyncAsync uses active-high reset
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kPolarity,
kStages => 2) --use double FF synchronizer
port map (
aReset => aRst_int,
aIn => not kPolarity,
OutClk => OutClk,
oOut => oRst);
end Behavioral;
|
library ieee;
library ieee;
-- Some comment
library ieee;
library ieee;
library ieee;
|
--This should pass
context con1 is
end context;
context con2 is
end context;
--This should fail
context con3 is
end;
context con4 is
end
;
-- Split declaration across lines
context
con5
is
end
context
;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Top-Module: FanControl example design for a ML605 board
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library PoC;
use PoC.physical.all;
entity top_FanControl_ML605 is
port (
ML605_SystemClock_200MHz_p : in STD_LOGIC;
ML605_SystemClock_200MHz_n : in STD_LOGIC;
ML605_GPIO_LED : out STD_LOGIC_VECTOR(7 downto 0);
ML605_FanControl_PWM : out STD_LOGIC;
ML605_FanControl_Tacho : in STD_LOGIC
);
end entity;
architecture top of top_FanControl_ML605 is
attribute KEEP : BOOLEAN;
-- ===========================================================================
-- configurations
-- ===========================================================================
-- common configuration
constant DEBUG : BOOLEAN := TRUE;
constant SYS_CLOCK_FREQ : FREQ := 200 MHz;
-- ClockNetwork configuration
-- ===========================================================================
constant SYSTEM_CLOCK_FREQ : FREQ := SYS_CLOCK_FREQ / 2;
-- ===========================================================================
-- signal declarations
-- ===========================================================================
-- clock and reset signals
signal System_RefClock_200MHz : STD_LOGIC;
signal ClkNet_Reset : STD_LOGIC;
signal ClkNet_ResetDone : STD_LOGIC;
signal SystemClock_200MHz : STD_LOGIC;
signal SystemClock_100MHz : STD_LOGIC;
signal SystemClock_Stable_200MHz : STD_LOGIC;
signal SystemClock_Stable_100MHz : STD_LOGIC;
signal System_Clock : STD_LOGIC;
signal System_Reset : STD_LOGIC;
attribute KEEP of System_Clock : signal is TRUE;
attribute KEEP of System_Reset : signal is TRUE;
begin
-- ===========================================================================
-- assert statements
-- ===========================================================================
assert FALSE report "FanControl configuration:" severity NOTE;
assert FALSE report " SYS_CLOCK_FREQ: " & to_string(SYS_CLOCK_FREQ, 3) severity note;
-- ===========================================================================
-- Input/output buffers
-- ===========================================================================
IBUFGDS_SystemClock : IBUFGDS
port map (
I => ML605_SystemClock_200MHz_p,
IB => ML605_SystemClock_200MHz_n,
O => System_RefClock_200MHz
);
-- ==========================================================================================================================================================
-- ClockNetwork
-- ==========================================================================================================================================================
ClkNet_Reset <= '0';
ClkNet : entity PoC.clknet_ClockNetwork_ML605
generic map (
CLOCK_IN_FREQ => SYS_CLOCK_FREQ
)
port map (
ClockIn_200MHz => System_RefClock_200MHz,
ClockNetwork_Reset => ClkNet_Reset,
ClockNetwork_ResetDone => ClkNet_ResetDone,
Control_Clock_200MHz => open,
Clock_250MHz => open,
Clock_200MHz => SystemClock_200MHz,
Clock_125MHz => open,
Clock_100MHz => SystemClock_100MHz,
Clock_10MHz => open,
Clock_Stable_250MHz => open,
Clock_Stable_200MHz => SystemClock_Stable_200MHz,
Clock_Stable_125MHz => open,
Clock_Stable_100MHz => SystemClock_Stable_100MHz,
Clock_Stable_10MHz => open
);
-- system signals
System_Clock <= SystemClock_100MHz;
System_Reset <= not SystemClock_Stable_100MHz;
-- ==========================================================================================================================================================
-- General Purpose I/O
-- ==========================================================================================================================================================
blkGPIO : block
signal GPIO_LED : STD_LOGIC_VECTOR(7 downto 0);
signal GPIO_LED_d : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
GPIO_LED <= "0000000" & ClkNet_ResetDone;
GPIO_LED_d <= GPIO_LED when rising_edge(System_Clock);
ML605_GPIO_LED <= GPIO_LED_d;
end block;
-- ==========================================================================================================================================================
-- Fan Control
-- ==========================================================================================================================================================
blkFanControl : block
signal FanControl_PWM : STD_LOGIC;
signal FanControl_PWM_d : STD_LOGIC := '0';
signal FanControl_Tacho_async : STD_LOGIC;
signal FanControl_Tacho_sync : STD_LOGIC;
begin
FanControl_Tacho_async <= ML605_FanControl_Tacho;
sync : entity PoC.sync_Bits
port map (
Clock => System_Clock, -- Clock to be synchronized to
Input(0) => FanControl_Tacho_async, -- Data to be synchronized
Output(0) => FanControl_Tacho_sync -- synchronized data
);
Fan : entity PoC.io_FanControl
generic map (
CLOCK_FREQ => SYSTEM_CLOCK_FREQ -- 100 MHz
)
port map (
Clock => System_Clock,
Reset => System_Reset,
Fan_PWM => FanControl_PWM,
Fan_Tacho => FanControl_Tacho_sync,
TachoFrequency => open
);
-- IOB-FF
FanControl_PWM_d <= FanControl_PWM when rising_edge(System_Clock);
ML605_FanControl_PWM <= FanControl_PWM_d;
end block;
end architecture;
|
--------------------------------
-- Copyright 1992-2001 Future Parallel
-- VLSI Design Lab
-- Library: VFP
-- Designer: Tim Pagden
-- Opened: 02.06.2001
-- Updated: 12.06.2001
-- DNH: T:/author/dnh/integer_class.dnh
--------------------------------
entity integer_class_tb is
--
-- tests for integer_class package
--
end integer_class_tb;
use std.textio.all;
library vfp;
use vfp.std_verification.all;
use vfp.integer_class.all;
architecture tb0 of integer_class_tb is
begin
process
--variable num_chars : integer;
variable j : integer;
variable k : integer;
variable tfi : boolean;
--variable bit_width : integer;
variable log_line : line;
file log_file : text open write_mode is "intclass.log";
begin
debug("Starting tests...");
log(log_file, "======== Start of integer_class tests ========");
debug(3);
debug("int is ", 3);
log(log_file, 3);
log(log_file, "int is ", 3);
--tb_log(log_file, "==== strlen tests...");
--for i in 0 to 9 loop
-- log(log_file, string_length(10 ** i));
-- log(log_file, string_length(-(10 ** i)));
--end loop;
log(log_file, "==== binary_wordlength tests...");
for i in 0 to 31 loop
log(log_file, binary_wordlength(2 ** i));
log(log_file, binary_wordlength(-(2 ** i)));
--write(log_line, (2 ** i)); -- it's OK 2**31 -> -(2**31) automatically,
-- presumably simulator does a shift operation internally!
end loop;
log(log_file, "==== integer string length tests ...");
for i in 0 to 9 loop
log(log_file, (integer'IMAGE(10 ** i)))'LENGTH;
log(log_file, (integer'IMAGE(-(10 ** i))))'LENGTH;
end loop;
log(log_file, "==== next_greater_binary_power_minus_1 tests ...");
for i in 0 to 31 loop
log(log_file, next_greater_binary_power_minus_1(2 ** i));
log(log_file, next_greater_binary_power_minus_1(-(2 ** i)));
end loop;
--tb_log(log_file, "==== is_factor_of_32 tests ...");
--for i in 0 to 32 loop
-- tfi := is_factor_of_32(i);
-- if tfi then
-- write(log_line, i);
-- write(log_line, string'(" is a factor"));
-- -- sprintf("i,s", +integer, string)
-- -- unary + takes any operand and returns a string
-- -- sprintf("i,s", integer, string)
-- writeline(log_file, log_line);
-- else
-- write(log_line, i);
-- write(log_line, string'("..."));
-- writeline(log_file, log_line);
-- end if;
--end loop;
write(log_line, string'("==== is_power_of_2 tests ..."));
writeline(log_file, log_line);
for i in 0 to 31 loop
k := 2 ** i;
tfi := is_power_of_2(k);
if tfi then
write(log_line, string'("Correct, "));
write(log_line, k);
write(log_line, string'(" is a power of 2"));
writeline(log_file, log_line);
else
write(log_line, k);
write(log_line, string'(" has not been captured as a power of 2 - it should be!"));
writeline(log_file, log_line);
end if;
end loop;
write(log_line, string'("==== log_2 tests ..."));
writeline(log_file, log_line);
for i in 0 to 31 loop
k := (2 ** i)-1;
j := log_2(k);
write(log_line, k);
write(log_line, string'(" , "));
write(log_line, j);
writeline(log_file, log_line);
k := 2 ** i;
j := log_2(k);
write(log_line, k);
write(log_line, string'(" , "));
write(log_line, j);
writeline(log_file, log_line);
k := (2 ** i)+1;
j := log_2(k);
write(log_line, k);
write(log_line, string'(" , "));
write(log_line, j);
writeline(log_file, log_line);
end loop;
log(log_file, "======== End of integer_class tests ========");
debug("Tests finished.");
wait;
end process;
end tb0;
configuration integer_class_tb_cfg_0 of integer_class_tb is
for tb0
end for;
end integer_class_tb_cfg_0;
|
--------------------------------
-- Copyright 1992-2001 Future Parallel
-- VLSI Design Lab
-- Library: VFP
-- Designer: Tim Pagden
-- Opened: 02.06.2001
-- Updated: 12.06.2001
-- DNH: T:/author/dnh/integer_class.dnh
--------------------------------
entity integer_class_tb is
--
-- tests for integer_class package
--
end integer_class_tb;
use std.textio.all;
library vfp;
use vfp.std_verification.all;
use vfp.integer_class.all;
architecture tb0 of integer_class_tb is
begin
process
--variable num_chars : integer;
variable j : integer;
variable k : integer;
variable tfi : boolean;
--variable bit_width : integer;
variable log_line : line;
file log_file : text open write_mode is "intclass.log";
begin
debug("Starting tests...");
log(log_file, "======== Start of integer_class tests ========");
debug(3);
debug("int is ", 3);
log(log_file, 3);
log(log_file, "int is ", 3);
--tb_log(log_file, "==== strlen tests...");
--for i in 0 to 9 loop
-- log(log_file, string_length(10 ** i));
-- log(log_file, string_length(-(10 ** i)));
--end loop;
log(log_file, "==== binary_wordlength tests...");
for i in 0 to 31 loop
log(log_file, binary_wordlength(2 ** i));
log(log_file, binary_wordlength(-(2 ** i)));
--write(log_line, (2 ** i)); -- it's OK 2**31 -> -(2**31) automatically,
-- presumably simulator does a shift operation internally!
end loop;
log(log_file, "==== integer string length tests ...");
for i in 0 to 9 loop
log(log_file, (integer'IMAGE(10 ** i)))'LENGTH;
log(log_file, (integer'IMAGE(-(10 ** i))))'LENGTH;
end loop;
log(log_file, "==== next_greater_binary_power_minus_1 tests ...");
for i in 0 to 31 loop
log(log_file, next_greater_binary_power_minus_1(2 ** i));
log(log_file, next_greater_binary_power_minus_1(-(2 ** i)));
end loop;
--tb_log(log_file, "==== is_factor_of_32 tests ...");
--for i in 0 to 32 loop
-- tfi := is_factor_of_32(i);
-- if tfi then
-- write(log_line, i);
-- write(log_line, string'(" is a factor"));
-- -- sprintf("i,s", +integer, string)
-- -- unary + takes any operand and returns a string
-- -- sprintf("i,s", integer, string)
-- writeline(log_file, log_line);
-- else
-- write(log_line, i);
-- write(log_line, string'("..."));
-- writeline(log_file, log_line);
-- end if;
--end loop;
write(log_line, string'("==== is_power_of_2 tests ..."));
writeline(log_file, log_line);
for i in 0 to 31 loop
k := 2 ** i;
tfi := is_power_of_2(k);
if tfi then
write(log_line, string'("Correct, "));
write(log_line, k);
write(log_line, string'(" is a power of 2"));
writeline(log_file, log_line);
else
write(log_line, k);
write(log_line, string'(" has not been captured as a power of 2 - it should be!"));
writeline(log_file, log_line);
end if;
end loop;
write(log_line, string'("==== log_2 tests ..."));
writeline(log_file, log_line);
for i in 0 to 31 loop
k := (2 ** i)-1;
j := log_2(k);
write(log_line, k);
write(log_line, string'(" , "));
write(log_line, j);
writeline(log_file, log_line);
k := 2 ** i;
j := log_2(k);
write(log_line, k);
write(log_line, string'(" , "));
write(log_line, j);
writeline(log_file, log_line);
k := (2 ** i)+1;
j := log_2(k);
write(log_line, k);
write(log_line, string'(" , "));
write(log_line, j);
writeline(log_file, log_line);
end loop;
log(log_file, "======== End of integer_class tests ========");
debug("Tests finished.");
wait;
end process;
end tb0;
configuration integer_class_tb_cfg_0 of integer_class_tb is
for tb0
end for;
end integer_class_tb_cfg_0;
|
--------------------------------
-- Copyright 1992-2001 Future Parallel
-- VLSI Design Lab
-- Library: VFP
-- Designer: Tim Pagden
-- Opened: 02.06.2001
-- Updated: 12.06.2001
-- DNH: T:/author/dnh/integer_class.dnh
--------------------------------
entity integer_class_tb is
--
-- tests for integer_class package
--
end integer_class_tb;
use std.textio.all;
library vfp;
use vfp.std_verification.all;
use vfp.integer_class.all;
architecture tb0 of integer_class_tb is
begin
process
--variable num_chars : integer;
variable j : integer;
variable k : integer;
variable tfi : boolean;
--variable bit_width : integer;
variable log_line : line;
file log_file : text open write_mode is "intclass.log";
begin
debug("Starting tests...");
log(log_file, "======== Start of integer_class tests ========");
debug(3);
debug("int is ", 3);
log(log_file, 3);
log(log_file, "int is ", 3);
--tb_log(log_file, "==== strlen tests...");
--for i in 0 to 9 loop
-- log(log_file, string_length(10 ** i));
-- log(log_file, string_length(-(10 ** i)));
--end loop;
log(log_file, "==== binary_wordlength tests...");
for i in 0 to 31 loop
log(log_file, binary_wordlength(2 ** i));
log(log_file, binary_wordlength(-(2 ** i)));
--write(log_line, (2 ** i)); -- it's OK 2**31 -> -(2**31) automatically,
-- presumably simulator does a shift operation internally!
end loop;
log(log_file, "==== integer string length tests ...");
for i in 0 to 9 loop
log(log_file, (integer'IMAGE(10 ** i)))'LENGTH;
log(log_file, (integer'IMAGE(-(10 ** i))))'LENGTH;
end loop;
log(log_file, "==== next_greater_binary_power_minus_1 tests ...");
for i in 0 to 31 loop
log(log_file, next_greater_binary_power_minus_1(2 ** i));
log(log_file, next_greater_binary_power_minus_1(-(2 ** i)));
end loop;
--tb_log(log_file, "==== is_factor_of_32 tests ...");
--for i in 0 to 32 loop
-- tfi := is_factor_of_32(i);
-- if tfi then
-- write(log_line, i);
-- write(log_line, string'(" is a factor"));
-- -- sprintf("i,s", +integer, string)
-- -- unary + takes any operand and returns a string
-- -- sprintf("i,s", integer, string)
-- writeline(log_file, log_line);
-- else
-- write(log_line, i);
-- write(log_line, string'("..."));
-- writeline(log_file, log_line);
-- end if;
--end loop;
write(log_line, string'("==== is_power_of_2 tests ..."));
writeline(log_file, log_line);
for i in 0 to 31 loop
k := 2 ** i;
tfi := is_power_of_2(k);
if tfi then
write(log_line, string'("Correct, "));
write(log_line, k);
write(log_line, string'(" is a power of 2"));
writeline(log_file, log_line);
else
write(log_line, k);
write(log_line, string'(" has not been captured as a power of 2 - it should be!"));
writeline(log_file, log_line);
end if;
end loop;
write(log_line, string'("==== log_2 tests ..."));
writeline(log_file, log_line);
for i in 0 to 31 loop
k := (2 ** i)-1;
j := log_2(k);
write(log_line, k);
write(log_line, string'(" , "));
write(log_line, j);
writeline(log_file, log_line);
k := 2 ** i;
j := log_2(k);
write(log_line, k);
write(log_line, string'(" , "));
write(log_line, j);
writeline(log_file, log_line);
k := (2 ** i)+1;
j := log_2(k);
write(log_line, k);
write(log_line, string'(" , "));
write(log_line, j);
writeline(log_file, log_line);
end loop;
log(log_file, "======== End of integer_class tests ========");
debug("Tests finished.");
wait;
end process;
end tb0;
configuration integer_class_tb_cfg_0 of integer_class_tb is
for tb0
end for;
end integer_class_tb_cfg_0;
|
entity test is
package a is new b generic map(c => foo'bar);
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SimpleRegister is
generic(
WIDTH : integer := 16
);
Port(
inval : in std_ulogic_vector(WIDTH - 1 downto 0);
outval : out std_ulogic_vector(WIDTH - 1 downto 0);
set : in std_ulogic;
reset : in std_ulogic;
clock : in std_ulogic
);
end SimpleRegister;
architecture Behavioral of SimpleRegister is
begin
process(clock, set)
begin
if reset = '1' then
outval <= (others => '0');
else
if set = '1' and rising_edge(clock) then
outval <= inval;
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ps_converter is
port (
clk : in std_logic;
rst : in std_logic;
clk_en : in std_logic;
start : in std_logic;
d : in std_logic_vector(7 downto 0);
q : out std_logic
);
end ps_converter;
architecture rtl of ps_converter is
signal reg : std_logic_vector(7 downto 0) := (others => '0');
signal cnt : unsigned(2 downto 0) := to_unsigned(0, 3);
begin
process
begin
wait until rising_edge(clk);
if rst = '1' then
reg <= (others => '0');
elsif clk_en = '1' then
if start = '1' then
reg <= d;
q <= d(7);
cnt <= to_unsigned(6, 3);
else
q <= d(to_integer(cnt));
cnt <= cnt - to_unsigned(1, 3);
end if;
end if;
end process;
end rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_pk_test.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package stimulus_generators is
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length );
end package stimulus_generators;
package body stimulus_generators is
type digit_table is array ( natural range 0 to 1 ) of bit;
constant digit : digit_table := ( '0', '1' );
function natural_to_bv ( nat : in natural;
length : in natural ) return bit_vector is
variable temp : natural := nat;
variable result : bit_vector(0 to length - 1);
begin
for index in result'reverse_range loop
result(index) := digit( temp rem 2 );
temp := temp / 2;
end loop;
return result;
end function natural_to_bv;
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length ) is
begin
bv <= natural_to_bv(0, bv'length);
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= natural_to_bv(value, bv'length);
end loop;
end procedure all_possible_values;
end package body stimulus_generators;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_pk_test.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package stimulus_generators is
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length );
end package stimulus_generators;
package body stimulus_generators is
type digit_table is array ( natural range 0 to 1 ) of bit;
constant digit : digit_table := ( '0', '1' );
function natural_to_bv ( nat : in natural;
length : in natural ) return bit_vector is
variable temp : natural := nat;
variable result : bit_vector(0 to length - 1);
begin
for index in result'reverse_range loop
result(index) := digit( temp rem 2 );
temp := temp / 2;
end loop;
return result;
end function natural_to_bv;
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length ) is
begin
bv <= natural_to_bv(0, bv'length);
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= natural_to_bv(value, bv'length);
end loop;
end procedure all_possible_values;
end package body stimulus_generators;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_pk_test.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package stimulus_generators is
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length );
end package stimulus_generators;
package body stimulus_generators is
type digit_table is array ( natural range 0 to 1 ) of bit;
constant digit : digit_table := ( '0', '1' );
function natural_to_bv ( nat : in natural;
length : in natural ) return bit_vector is
variable temp : natural := nat;
variable result : bit_vector(0 to length - 1);
begin
for index in result'reverse_range loop
result(index) := digit( temp rem 2 );
temp := temp / 2;
end loop;
return result;
end function natural_to_bv;
procedure all_possible_values ( signal bv : out bit_vector;
delay_between_values : in delay_length ) is
begin
bv <= natural_to_bv(0, bv'length);
for value in 1 to 2**bv'length - 1 loop
wait for delay_between_values;
bv <= natural_to_bv(value, bv'length);
end loop;
end procedure all_possible_values;
end package body stimulus_generators;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY instantiate IS
PORT (
SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
LEDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
LEDG : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END;
ARCHITECTURE behavioural OF instantiate IS
SIGNAL done : std_logic;
SIGNAL not_key : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL read_addr : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL func : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL flag : std_logic;
SIGNAL reg0_out : std_logic_vector(15 DOWNTO 0);
SIGNAL reg1_out : std_logic_vector(15 DOWNTO 0);
SIGNAL c_state : INTEGER;
COMPONENT binaryto4hex IS
PORT (
binary : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
output0, output1, output2, output3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT;
COMPONENT ram_16bit IS
PORT (
clock : IN STD_LOGIC;
done : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
write_addr : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
read_addr : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
write_enable : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
COMPONENT my_little_processor IS
PORT (
clock, reset : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
flag_out, done_out : OUT STD_LOGIC;
read_addr, reg0_out, reg1_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
c_state : OUT INTEGER
);
END COMPONENT;
BEGIN
ram : ram_16bit
PORT MAP(
clock => not_key(2),
done => done,
data => "0000000000000000",
write_addr => "0000000000000000",
read_addr => read_addr,
write_enable => '0',
q => func
);
processor : my_little_processor
PORT MAP(
clock => not_key(2),
reset => not_key(1),
data_in => func,
flag_out => flag,
done_out => done,
read_addr => read_addr,
reg0_out => reg0_out,
reg1_out => reg1_out,
c_state => c_state
);
bintohex0 : binaryto4hex
PORT MAP(
binary => reg1_out,
output0 => HEX0,
output1 => HEX1,
output2 => HEX2,
output3 => HEX3
);
bintohex1 : binaryto4hex
PORT MAP(
binary => reg0_out,
output0 => HEX4,
output1 => HEX5,
output2 => HEX6,
output3 => HEX7
);
-- Negate key state (not_key[0] = 1 when KEY0 is pressed)
not_key <= NOT KEY;
-- Assign LEDG's above KEYs to current state
LEDG(7 DOWNTO 0) <= std_logic_vector(to_unsigned(c_state, 8));
LEDG(8) <= not_key(2);
--Assign current instruction to 16 LEDs
LEDR(15 DOWNTO 0) <= func;
-- Assign the flag
LEDR(17) <= flag;
LEDR(16) <= flag;
END behavioural; |
-- $Id: tb_tst_rlink_b3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_b3
-- Description: Configuration for tb_tst_rlink_b3 for tb_basys3
--
-- Dependencies: sys_tst_rlink_b3
--
-- To test: sys_tst_rlink_b3
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-18 648 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_rlink_b3 of tb_basys3 is
for sim
for all : basys3_aif
use entity work.sys_tst_rlink_b3;
end for;
end for;
end tb_tst_rlink_b3;
|
-------------------------------------------------------------------------------
-- $Id: sync_fifo.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
-------------------------------------------------------------------------------
-- sync_fifo.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Author: satish
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2010/10/28 11:17:56 $
--
-- History:
-- satish 2004-03-24 New Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.numeric_std.all;
library fsl_v20_v2_11_f;
use fsl_v20_v2_11_f.all;
entity Sync_FIFO is
generic (
C_IMPL_STYLE : integer := 0;
WordSize : integer := 8;
MemSize : integer := 16
);
port (
Reset : in std_logic;
Clk : in std_logic;
WE : in std_logic;
DataIn : in std_logic_vector(WordSize-1 downto 0);
Full : out std_logic;
RD : in std_logic;
DataOut : out std_logic_vector(WordSize-1 downto 0);
Exists : out std_logic
);
end Sync_FIFO;
architecture VHDL_RTL of Sync_FIFO is
function log2(x : natural) return integer is
variable i : integer := 0;
begin
-- coverage off
if x = 0 then return 0;
-- coverage on
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
constant AddrWidth : integer := log2(MemSize);
signal Read_Address : std_logic_vector(0 to AddrWidth-1);
signal Write_Address : std_logic_vector(0 to AddrWidth-1);
component SRL_FIFO is
generic (
C_DATA_BITS : integer;
C_DEPTH : integer);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
-- FIFO_Half_Full : out std_logic;
-- FIFO_Half_Empty : out std_logic;
Data_Exists : out std_logic);
end component SRL_FIFO;
component Sync_DPRAM is
generic (
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 16
);
port (
clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(C_AWIDTH-1 downto 0);
dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
di : in std_logic_vector(C_DWIDTH-1 downto 0);
dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end component;
component Sync_BRAM is
generic (
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 16
);
port (
clk : in std_logic;
-- Write port
we : in std_logic;
a : in std_logic_vector(C_AWIDTH-1 downto 0);
di : in std_logic_vector(C_DWIDTH-1 downto 0);
-- Read port
dpra_en : in std_logic;
dpra : in std_logic_vector(C_AWIDTH-1 downto 0);
dpo : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end component;
signal read_bram_enable : std_logic;
signal DataOut_BRAM : std_logic_vector(WordSize-1 downto 0);
begin
FSL_Flag_Handle : if ((MemSize > 16) or (C_IMPL_STYLE /= 0)) generate
signal read_addr_ptr : natural range 0 to 2 ** AddrWidth-1;
signal write_addr_ptr : natural range 0 to 2 ** AddrWidth-1;
signal full_i : std_logic;
signal exists_i : std_logic;
signal read_addr_incr : std_logic;
signal first_write_on_empty_fifo : std_logic;
signal last_word : std_logic;
signal fifo_length : natural range 0 to MemSize;
begin
-- FIFO length handling
Fifo_Length_Handle : process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
fifo_length <= 0;
else
-- write and no read => increment length
-- don't increment length when FULL
if (WE = '1' and RD = '0' and full_i = '0') then
fifo_length <= fifo_length + 1;
-- read and no write => decrement length
-- don't decrement length when EMPTY
elsif (WE = '0' and RD = '1' and exists_i = '1') then
fifo_length <= fifo_length - 1;
end if;
end if;
end if;
end process Fifo_Length_Handle;
---------------------------------------------------------------------------
-- Need special handling for BRAM based fifo since there is one extra delay
-- reading out data from it.
-- We are pipelining the reading by making read_addr be one read ahead and
-- are holding the data on the BRAM output by enabling/disabling the BRAM
-- enable signal
---------------------------------------------------------------------------
Rd_Delay_For_Bram : if (C_IMPL_STYLE /= 0) generate
signal fall_through_data : std_logic_vector(WordSize-1 downto 0);
signal use_fall_through : std_logic;
begin
-------------------------------------------------------------------------
-- Need to detect when writing into an empty FIFO,
-------------------------------------------------------------------------
First_Write : process (Clk) is
begin -- process First_Write
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
first_write_on_empty_fifo <= '0';
else
first_write_on_empty_fifo <= WE and not exists_i;
end if;
end if;
end process First_Write;
-------------------------------------------------------------------------
-- Read out BRAM contents on the first word written in an empty FIFO and
-- all other FIFO read except when the last word is read since the "real"
-- FIFO is actually empty at this time since the last word is on the
-- output of the BRAM
-------------------------------------------------------------------------
last_word <= '1' when (fifo_length = 1) else '0';
read_bram_enable <= first_write_on_empty_fifo or (RD and (not last_word or WE));
read_addr_incr <= read_bram_enable;
-------------------------------------------------------------------------
-- The exists flag is now if the BRAM output has valid data and not the
-- content of the FIFO
-------------------------------------------------------------------------
FIFO_Exists_DFF : process (Clk) is
begin -- process FIFO_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
Exists <= '0';
else
if (first_write_on_empty_fifo = '1') then
Exists <= '1';
elsif ((RD = '1') and (WE = '0') and (last_word = '1')) then
Exists <= '0';
end if;
end if;
end if;
end process FIFO_Exists_DFF;
-------------------------------------------------------------------------
-- Data output with fallthrough
-------------------------------------------------------------------------
use_fall_through_DFF : process (Clk) is
begin -- process FIFO_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if ((RD and (not WE)) = '1') or (Reset = '1') then -- synchronous reset (active high)
use_fall_through <= '0';
elsif (RD and not last_word) = '1' then
use_fall_through <= '0';
elsif (RD = '1') then
-- The equation (RD and WE and last_word) = '1' can be reduced to (RD = '1')
use_fall_through <= '1';
end if;
end if;
end process use_fall_through_DFF;
fall_through_data_DFF : process (Clk) is
begin -- process FIFO_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (RD and WE and last_word) = '1' then
fall_through_data <= DataIn;
end if;
end if;
end process fall_through_data_DFF;
DataOut <= fall_through_data when (use_fall_through = '1') else DataOut_BRAM;
end generate Rd_Delay_For_Bram;
Rd_No_Delay : if (C_IMPL_STYLE = 0) generate
read_addr_incr <= RD;
Exists <= exists_i;
end generate Rd_No_Delay;
-- Set Full and empty flags
full_i <= '1' when (fifo_length = MemSize) else '0';
exists_i <= '1' when (fifo_length /= 0) else '0';
Full <= full_i;
-- Increment Read Address Pointer
Read_Addr_Handle : process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
read_addr_ptr <= 0;
elsif (read_addr_incr = '1') then
read_addr_ptr <= (read_addr_ptr + 1) mod (2 ** AddrWidth);
end if;
end if;
end process Read_Addr_Handle;
-- Increment Write Address Pointer
Write_Addr_Handle : process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
write_addr_ptr <= 0;
elsif (WE = '1') then
write_addr_ptr <= (write_addr_ptr + 1) mod (2 ** AddrWidth);
end if;
end if;
end process Write_Addr_Handle;
Write_Address <= std_logic_vector(to_unsigned(write_addr_ptr, AddrWidth));
Read_Address <= std_logic_vector(to_unsigned(read_addr_ptr, AddrWidth));
end generate FSL_Flag_Handle;
Sync_FIFO_I : if (C_IMPL_STYLE = 0) generate
srl_fifo_i : if (MemSize <= 16) generate
FSL_FIFO : SRL_FIFO
generic map (
C_DATA_BITS => WordSize,
C_DEPTH => MemSize)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => WE, -- Master Write Signal
Data_In => DataIn, -- Master Data
FIFO_Read => RD, -- Slave Read Signal
Data_Out => DataOut, -- Slave Data
FIFO_Full => Full, -- FIFO full signal
-- FIFO_Half_Full => open,
-- FIFO_Half_Empty => open,
Data_Exists => Exists); -- Slave Data exists
end generate srl_fifo_i;
dpram_fifo_i : if (MemSize > 16) generate
DPRAM_FIFO : SYNC_DPRAM
generic map (
C_DWIDTH => WordSize,
C_AWIDTH => AddrWidth)
port map (
clk => Clk,
we => WE,
a => Write_Address,
dpra => Read_Address,
di => DataIn,
dpo => DataOut);
end generate dpram_fifo_i;
end generate Sync_FIFO_I;
Sync_BRAM_FIFO : if (C_IMPL_STYLE /= 0) generate
Sync_BRAM_I1 : Sync_BRAM
generic map (
C_DWIDTH => WordSize, -- [integer]
C_AWIDTH => AddrWidth) -- [integer]
port map (
clk => Clk, -- [in std_logic]
-- Write port
we => WE, -- [in std_logic]
a => Write_Address, -- [in std_logic_vector(C_AWIDTH-1 downto 0)]
di => DataIn, -- [in std_logic_vector(C_DWIDTH-1 downto 0)]
-- Read port
dpra_en => read_bram_enable, -- [in std_logic]
dpra => Read_Address, -- [in std_logic_vector(C_AWIDTH-1 downto 0)]
dpo => DataOut_BRAM); -- [out std_logic_vector(C_DWIDTH-1 downto 0)]
end generate Sync_BRAM_FIFO;
end VHDL_RTL;
|
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: Register - Behavioral
-- Create Date: 16:15:54 12/26/2009
-- Description: the status register of a CPU.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity status_reg is
port ( I_CLK : in std_logic;
I_COND : in std_logic_vector ( 3 downto 0);
I_DIN : in std_logic_vector ( 7 downto 0);
I_FLAGS : in std_logic_vector ( 7 downto 0);
I_WE_F : in std_logic;
I_WE_SR : in std_logic;
Q : out std_logic_vector ( 7 downto 0);
Q_CC : out std_logic);
end status_reg;
architecture Behavioral of status_reg is
signal L : std_logic_vector ( 7 downto 0);
begin
process(I_CLK)
begin
if (rising_edge(I_CLK)) then
if (I_WE_F = '1') then -- write flags (from ALU)
L <= I_FLAGS;
elsif (I_WE_SR = '1') then -- write I/O
L <= I_DIN;
end if;
end if;
end process;
cond: process(I_COND, L)
begin
case I_COND(2 downto 0) is
when "000" => Q_CC <= L(0) xor I_COND(3);
when "001" => Q_CC <= L(1) xor I_COND(3);
when "010" => Q_CC <= L(2) xor I_COND(3);
when "011" => Q_CC <= L(3) xor I_COND(3);
when "100" => Q_CC <= L(4) xor I_COND(3);
when "101" => Q_CC <= L(5) xor I_COND(3);
when "110" => Q_CC <= L(6) xor I_COND(3);
when others => Q_CC <= L(7) xor I_COND(3);
end case;
end process;
Q <= L;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: Register - Behavioral
-- Create Date: 16:15:54 12/26/2009
-- Description: the status register of a CPU.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity status_reg is
port ( I_CLK : in std_logic;
I_COND : in std_logic_vector ( 3 downto 0);
I_DIN : in std_logic_vector ( 7 downto 0);
I_FLAGS : in std_logic_vector ( 7 downto 0);
I_WE_F : in std_logic;
I_WE_SR : in std_logic;
Q : out std_logic_vector ( 7 downto 0);
Q_CC : out std_logic);
end status_reg;
architecture Behavioral of status_reg is
signal L : std_logic_vector ( 7 downto 0);
begin
process(I_CLK)
begin
if (rising_edge(I_CLK)) then
if (I_WE_F = '1') then -- write flags (from ALU)
L <= I_FLAGS;
elsif (I_WE_SR = '1') then -- write I/O
L <= I_DIN;
end if;
end if;
end process;
cond: process(I_COND, L)
begin
case I_COND(2 downto 0) is
when "000" => Q_CC <= L(0) xor I_COND(3);
when "001" => Q_CC <= L(1) xor I_COND(3);
when "010" => Q_CC <= L(2) xor I_COND(3);
when "011" => Q_CC <= L(3) xor I_COND(3);
when "100" => Q_CC <= L(4) xor I_COND(3);
when "101" => Q_CC <= L(5) xor I_COND(3);
when "110" => Q_CC <= L(6) xor I_COND(3);
when others => Q_CC <= L(7) xor I_COND(3);
end case;
end process;
Q <= L;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: Register - Behavioral
-- Create Date: 16:15:54 12/26/2009
-- Description: the status register of a CPU.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity status_reg is
port ( I_CLK : in std_logic;
I_COND : in std_logic_vector ( 3 downto 0);
I_DIN : in std_logic_vector ( 7 downto 0);
I_FLAGS : in std_logic_vector ( 7 downto 0);
I_WE_F : in std_logic;
I_WE_SR : in std_logic;
Q : out std_logic_vector ( 7 downto 0);
Q_CC : out std_logic);
end status_reg;
architecture Behavioral of status_reg is
signal L : std_logic_vector ( 7 downto 0);
begin
process(I_CLK)
begin
if (rising_edge(I_CLK)) then
if (I_WE_F = '1') then -- write flags (from ALU)
L <= I_FLAGS;
elsif (I_WE_SR = '1') then -- write I/O
L <= I_DIN;
end if;
end if;
end process;
cond: process(I_COND, L)
begin
case I_COND(2 downto 0) is
when "000" => Q_CC <= L(0) xor I_COND(3);
when "001" => Q_CC <= L(1) xor I_COND(3);
when "010" => Q_CC <= L(2) xor I_COND(3);
when "011" => Q_CC <= L(3) xor I_COND(3);
when "100" => Q_CC <= L(4) xor I_COND(3);
when "101" => Q_CC <= L(5) xor I_COND(3);
when "110" => Q_CC <= L(6) xor I_COND(3);
when others => Q_CC <= L(7) xor I_COND(3);
end case;
end process;
Q <= L;
end Behavioral;
|
-- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
-- Implement some hand-holding for dumb synthesis tools
entity opa_prim_ternary is
generic(
g_wide : natural);
port(
a_i : in unsigned(g_wide-1 downto 0);
b_i : in unsigned(g_wide-1 downto 0);
c_i : in unsigned(g_wide-1 downto 0);
x_o : out unsigned(g_wide-1 downto 0));
end opa_prim_ternary;
architecture rtl of opa_prim_ternary is
begin
x_o <= a_i + b_i + c_i;
end rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: image_selector_fifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.image_selector_fifo_pkg.ALL;
ENTITY image_selector_fifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF image_selector_fifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:image_selector_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: image_selector_fifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.image_selector_fifo_pkg.ALL;
ENTITY image_selector_fifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF image_selector_fifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:image_selector_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: image_selector_fifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.image_selector_fifo_pkg.ALL;
ENTITY image_selector_fifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF image_selector_fifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:image_selector_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-07 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03800_good.vhd
-- File Creation date : 2015-04-07
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Synchronous elements initialization: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_03800_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic; -- D Flip-Flop output signal
o_Q_n : out std_logic -- D Flip-Flop output signal, inverted
);
end STD_03800_good;
--CODE
architecture Behavioral of STD_03800_good is
signal Q : std_logic; -- D Flip-Flop output
signal Q_n : std_logic; -- Same as Q, inverted
begin
-- D FlipFlop process
P_FlipFlop : process(i_Clock, i_Reset_n)
begin
if (i_Reset_n = '0') then
Q <= '0';
Q_n <= '1';
elsif (rising_edge(i_Clock)) then
Q <= i_D;
Q_n <= not i_D;
end if;
end process;
o_Q <= Q;
o_Q_n <= Q_n;
end Behavioral;
--CODE
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library isa;
use isa.or1k_pkg.all;
library sys;
use sys.sys_pkg.all;
use work.cpu_or1knd_i5_pkg.all;
entity cpu_or1knd_i5_core is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
sys_slave_ctrl_out : in sys_slave_ctrl_out_type;
sys_slave_dp_out : in sys_slave_dp_out_type;
sys_master_ctrl_out : out sys_master_ctrl_out_type;
sys_master_dp_out : out sys_master_dp_out_type
);
end;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_mm2s_basic_wrap;
use axi_sg_v4_1.axi_sg_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_sg_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0) ;
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_MM2S_ADDR_WIDTH+40)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+40)-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_sg_datamover;
architecture implementation of axi_sg_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
-- coverage off
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
-- coverage on
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
-- coverage off
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
-- coverage on
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
-- coverage off
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
-- coverage on
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
-- coverage off
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
-- coverage on
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
-- coverage off
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
-- coverage on
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
-- coverage off
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
-- coverage on
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_sg_v4_1.axi_sg_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
sg_ctl => sg_ctl ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_sg_v4_1.axi_sg_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
sg_ctl => sg_ctl ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
end implementation;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:00:58 03/11/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Part1/programCounter_tb.vhd
-- Project Name: Part1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: programCounter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY programCounter_tb IS
END programCounter_tb;
ARCHITECTURE behavior OF programCounter_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT programCounter
PORT(
CLK : IN std_logic;
EN : IN std_logic;
RST : IN std_logic;
INSADR : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal EN : std_logic := '0';
signal RST : std_logic := '0';
--Outputs
signal INSADR : std_logic_vector(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: programCounter PORT MAP (
CLK => CLK,
EN => EN,
RST => RST,
INSADR => INSADR
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
EN <= '1';
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- https://github.com/ghdl/ghdl/issues/1842
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
package signal_pkg is
type t_sigs is array (natural range <>) of std_logic_vector(7 downto 0);
type t_signals is record
dta: t_sigs(0 to 7);
end record;
end signal_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signal_pkg.all;
entity source is
generic (
instance_number : integer := 0);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
outs : out t_signals
);
end entity source;
architecture sim of source is
signal toggle : std_logic := '0';
begin -- architecture rtl
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
outs.dta(instance_number) <= (others => '0');
else
toggle <= not toggle;
if toggle='0' then
outs.dta(instance_number) <= (others => '0');
end if;
outs.dta(instance_number) <= std_logic_vector(to_unsigned(instance_number + 2, 8));
end if;
end if;
end process;
end architecture sim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signal_pkg.all;
entity elab26 is
end elab26;
architecture beh1 of elab26 is
signal clk : std_logic := '0';
signal rst_n : std_logic := '0';
signal test : t_signals;
begin -- beh1
clk <= not clk after 10 ns when now < 50 ns;
process
begin
rst_n <= '0';
wait for 30 ns;
rst_n <= '1';
wait;
end process;
g1: for i in 0 to 7 generate
source_1: entity work.source
generic map (
instance_number => i)
port map (
rst_n_i => rst_n,
clk_i => clk,
outs => test);
end generate g1;
check_p: process is
begin
wait for 50 ns;
for i in 0 to 7 loop
assert test.dta(i) = (0 to 7 => 'U');
end loop;
wait;
end process;
end beh1;
|
------------------------------------------------------------
-- Copyright (c) 2019 by Paul Scherrer Institute, Switzerland
-- All rights reserved.
------------------------------------------------------------
------------------------------------------------------------
-- Testbench generated by TbGen.py
------------------------------------------------------------
-- see Library/Python/TbGenerator
------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_i2c_master_pkg.all;
library work;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
use work.psi_tb_txt_util.all;
use work.psi_tb_i2c_pkg.all;
------------------------------------------------------------
-- Entity Declaration
------------------------------------------------------------
entity psi_common_i2c_master_tb is
generic (
InternalTriState_g : boolean := true
);
end entity;
------------------------------------------------------------
-- Architecture
------------------------------------------------------------
architecture sim of psi_common_i2c_master_tb is
-- *** Fixed Generics ***
constant ClockFrequency_g : real := 125.0e6;
constant I2cFrequency_g : real := 1.0e6;
constant BusBusyTimeout_g : real := 50.0e-6;
constant CmdTimeout_g : real := 10.0e-6;
-- *** Not Assigned Generics (default values) ***
-- *** TB Control ***
signal TbRunning : boolean := True;
signal NextCase : integer := -1;
signal ProcessDone : std_logic_vector(0 to 1) := (others => '0');
constant AllProcessesDone_c : std_logic_vector(0 to 1) := (others => '1');
constant TbProcNr_stim_c : integer := 0;
constant TbProcNr_i2c_c : integer := 1;
signal StimCase : integer := -1;
signal I2cCase : integer := -1;
-- *** DUT Signals ***
signal Clk : std_logic := '1';
signal Rst : std_logic := '1';
signal CmdRdy : std_logic := '0';
signal CmdVld : std_logic := '0';
signal CmdType : std_logic_vector(2 downto 0) := (others => '0');
signal CmdData : std_logic_vector(7 downto 0) := (others => '0');
signal CmdAck : std_logic := '0';
signal RspVld : std_logic := '0';
signal RspData : std_logic_vector(7 downto 0) := (others => '0');
signal RspType : std_logic_vector(2 downto 0) := (others => '0');
signal RspArbLost : std_logic := '0';
signal RspAck : std_logic := '0';
signal RspSeq : std_logic := '0';
signal BusBusy : std_logic := '0';
signal TimeoutCmd : std_logic := '0';
signal I2cScl : std_logic := '0';
signal I2cSda : std_logic := '0';
signal I2cScl_I : std_logic := '0';
signal I2cScl_O : std_logic := '0';
signal I2cScl_T : std_logic := '0';
signal I2cSda_I : std_logic := '0';
signal I2cSda_O : std_logic := '0';
signal I2cSda_T : std_logic := '0';
-- *** Helper Functions ***
procedure WaitForCase( signal TestCase : in integer;
Value : in integer) is
begin
if TestCase /= Value then
wait until TestCase = Value;
end if;
end procedure;
procedure ApplyCmd( Command : in std_logic_vector(2 downto 0);
Data : in std_logic_vector(7 downto 0);
Ack : in std_logic;
signal CmdVld : out std_logic;
signal CmdRdy : in std_logic;
signal CmdType : out std_logic_vector(2 downto 0);
signal CmdData : out std_logic_vector(7 downto 0);
signal CmdAck : out std_logic) is
begin
wait until rising_edge(Clk);
CmdVld <= '1';
CmdType <= Command;
CmdData <= Data;
CmdAck <= Ack;
wait until rising_edge(Clk) and CmdRdy = '1';
CmdVld <= '0';
CmdType <= (others => '0');
CmdData <= (others => '0');
CmdAck <= '0';
end procedure;
procedure CheckRsp( Command : in std_logic_vector(2 downto 0);
Data : in std_logic_vector;
Ack : in std_logic;
ArbLost : in std_logic;
signal RspVld : in std_logic;
signal RspData : in std_logic_vector(7 downto 0);
signal RspType : in std_logic_vector(2 downto 0);
signal RspArbLost : in std_logic;
signal RspAck : in std_logic;
signal RspSeq : in std_logic;
Msg : in string := "No Msg";
Err : in std_logic := '0') is
begin
wait until rising_edge(Clk) and RspVld = '1';
StdlvCompareStdlv(Command, RspType, "Response: Wrong Type - " & Msg);
if Data /= "X" then
StdlvCompareStdlv(Data, RspData, "Response: Wrong Data - " & Msg);
end if;
if Ack /= 'X' then
StdlCompare(choose(Ack = '1', 1, 0), RspAck, "Response: Wrong Ack - " & Msg);
end if;
if ArbLost /= 'X' then
StdlCompare(choose(ArbLost = '1', 1, 0), RspArbLost, "Response: Wrong ArbLost - " & Msg);
end if;
StdlCompare(choose(Err = '1', 1, 0), RspSeq, "Response: Wrong Err - " & Msg);
end procedure;
begin
------------------------------------------------------------
-- DUT Instantiation
------------------------------------------------------------
i_dut : entity work.psi_common_i2c_master
generic map (
ClockFrequency_g => ClockFrequency_g,
I2cFrequency_g => I2cFrequency_g,
BusBusyTimeout_g => BusBusyTimeout_g,
CmdTimeout_g => CmdTimeout_g,
InternalTriState_g => InternalTriState_g,
DisableAsserts_g => true
)
port map (
Clk => Clk,
Rst => Rst,
CmdRdy => CmdRdy,
CmdVld => CmdVld,
CmdType => CmdType,
CmdData => CmdData,
CmdAck => CmdAck,
RspVld => RspVld,
RspType => RspType,
RspArbLost => RspArbLost,
RspData => RspData,
RspAck => RspAck,
RspSeq => RspSeq,
BusBusy => BusBusy,
TimeoutCmd => TimeoutCmd,
I2cScl => I2cScl,
I2cSda => I2cSda,
I2cScl_I => I2cScl_I,
I2cScl_O => I2cScl_O,
I2cScl_T => I2cScl_T,
I2cSda_I => I2cSda_I,
I2cSda_O => I2cSda_O,
I2cSda_T => I2cSda_T
);
------------------------------------------------------------
-- I2C Emulation
------------------------------------------------------------
I2cPullup(I2cScl, I2cSda);
g_triState : if not InternalTriState_g generate
I2cScl <= 'Z' when I2cScl_T = '1' else I2cScl_O;
I2cScl_I <= To01X(I2cScl);
I2cSda <= 'Z' when I2cSda_T = '1' else I2cSda_O;
I2cSda_I <= To01X(I2cSda);
end generate;
------------------------------------------------------------
-- Testbench Control !DO NOT EDIT!
------------------------------------------------------------
p_tb_control : process
begin
wait until Rst = '0';
wait until ProcessDone = AllProcessesDone_c;
TbRunning <= false;
wait;
end process;
------------------------------------------------------------
-- Clocks !DO NOT EDIT!
------------------------------------------------------------
p_clock_Clk : process
constant Frequency_c : real := real(125e6);
begin
while TbRunning loop
wait for 0.5*(1 sec)/Frequency_c;
Clk <= not Clk;
end loop;
wait;
end process;
------------------------------------------------------------
-- Resets
------------------------------------------------------------
p_rst_Rst : process
begin
wait for 1 us;
-- Wait for two clk edges to ensure reset is active for at least one edge
wait until rising_edge(Clk);
wait until rising_edge(Clk);
Rst <= '0';
wait;
end process;
------------------------------------------------------------
-- Processes
------------------------------------------------------------
-- *** stim ***
p_stim : process
begin
I2cSetFrequency(I2cFrequency_g);
-- start of process !DO NOT EDIT
wait until Rst = '0';
wait until rising_edge(Clk);
-- *** Test Bus Busy ***
print(">> Test Bus Busy");
StimCase <= 0;
wait until rising_edge(Clk);
WaitForCase(I2cCase, 0);
wait for 10 us;
-- *** Test Start / Repeated-Start / Stop ***
print(">> Test Start / Repeated-Start / Stop");
StimCase <= 1;
wait until rising_edge(Clk);
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start");
ApplyCmd(CMD_REPSTART, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REPSTART, "X", 'X', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop");
WaitForCase(I2cCase, 1);
wait for 10 us;
-- *** Test Write ***
print(">> Test Write");
StimCase <= 2;
wait until rising_edge(Clk);
-- 1Byte ACK
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 1b ACK");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 1b ACK");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop 1b ACK");
-- 2Byte ACK, then NACK
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b ACK -> NACK");
ApplyCmd(CMD_SEND, X"12", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b ACK -> NACK 1");
ApplyCmd(CMD_SEND, X"34", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '0', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b ACK -> NACK 2");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop 2b ACK -> NACK");
WaitForCase(I2cCase, 2);
wait for 10 us;
-- *** Test Read ***
print(">> Test Read");
StimCase <= 3;
wait until rising_edge(Clk);
-- 1Byte ACK
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 1b ACK");
ApplyCmd(CMD_REC, X"00", '1', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REC, X"67", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 1b ACK");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop 1b ACK");
-- 2Byte ACK, then NACK
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b ACK -> NACK");
ApplyCmd(CMD_REC, X"00", '1', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REC, X"34", 'X', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b ACK -> NACK 1");
ApplyCmd(CMD_REC, X"00", '0', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REC, X"56", 'X', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b ACK -> NACK 2");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop 2b ACK -> NACK");
WaitForCase(I2cCase, 3);
wait for 10 us;
-- *** Test Clock Stretching ***
print(">> Test Clock Stretching");
StimCase <= 4;
wait until rising_edge(Clk);
-- 1Byte Read ACK
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Read 1b ACK");
ApplyCmd(CMD_REC, X"00", '1', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REC, X"67", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Read 1b ACK");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop Read 1b ACK");
-- 2Byte ACK, then NACK
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b Write ACK -> NACK");
ApplyCmd(CMD_SEND, X"12", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b Write ACK -> NACK 1");
ApplyCmd(CMD_SEND, X"34", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '0', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b Write ACK -> NACK 2");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop 2b Write ACK -> NACK");
-- Write / Read
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b W->R");
ApplyCmd(CMD_SEND, X"12", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Write 2b W->R");
ApplyCmd(CMD_REPSTART, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REPSTART, "X", 'X', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "RepStart 2b W->R");
ApplyCmd(CMD_REC, X"00", '1', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REC, X"67", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Read 2b W->R");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop 2b W->R");
WaitForCase(I2cCase, 4);
wait for 10 us;
-- *** Test Delayed Command *** (clock is held low until command available)
print(">> Test Delayed Command");
StimCase <= 5;
wait until rising_edge(Clk);
-- 1Byte Read ACK, delay shorter than timeout
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Read 1b ACK");
wait for CmdTimeout_g/2.0*(1 sec);
wait until rising_edge(Clk);
ApplyCmd(CMD_REC, X"00", '1', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REC, X"67", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Read 1b ACK");
wait for CmdTimeout_g/2.0*(1 sec);
wait until rising_edge(Clk);
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop Read 1b ACK");
-- Command Timeout (Timeout after start, other commands ignored)
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Read 1b ACK");
wait for CmdTimeout_g*2.0*(1 sec);
wait until rising_edge(Clk);
ApplyCmd(CMD_REC, X"00", '1', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REC, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Read 1b ACK", Err => '1');
wait for CmdTimeout_g*2.0*(1 sec);
wait until rising_edge(Clk);
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop Read 1b ACK", Err => '1');
WaitForCase(I2cCase, 5);
wait for 10 us;
-- *** Test Arbitration ***
print(">> Test Arbitration");
StimCase <= 6;
wait until rising_edge(Clk);
-- Multi Master, Same Write
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 1b ACK");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 1b ACK");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop 1b ACK");
-- Arbitration Lost during Write
wait for 10 us;
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost Write");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '0', '1', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost Write");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Lost Write", Err => '1');
-- Arbitration Lost during STOP (other master continues writing)
wait for 10 us;
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost Stop");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost Stop");
ApplyCmd(CMD_STOP, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_STOP, "X", 'X', '1', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop Lost Stop");
-- Arbitration Lost during repeated start (other master continues writing)
wait for 20 us;
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost RepStartA");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost RepStartA");
ApplyCmd(CMD_REPSTART, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REPSTART, "X", 'X', '1', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Repstart Lost RepStartA");
-- Arbitration Lost during repeated start (other master stops)
wait for 20 us;
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost RepStartB");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost RepStartB");
ApplyCmd(CMD_REPSTART, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_REPSTART, "X", 'X', '1', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Repstart Lost RepStartB");
-- Arbitration lost due to stop (during first bit of data)
wait for 10 us;
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost DueStop");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost DueStop 1");
ApplyCmd(CMD_SEND, X"F0", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '0', '1', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost DueStop 2");
-- Arbitration lost due to rep-start (during first bit of data)
wait for 10 us;
ApplyCmd(CMD_START, X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_START, "X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost DueRepStart");
ApplyCmd(CMD_SEND, X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost DueRepStart 1");
ApplyCmd(CMD_SEND, X"F0", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
CheckRsp(CMD_SEND, "X", '0', '1', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start Lost DueRepStart 2");
WaitForCase(I2cCase, 6);
wait for 10 us;
-- end of process !DO NOT EDIT!
wait for 1 us;
ProcessDone(TbProcNr_stim_c) <= '1';
wait;
end process;
-- *** i2c slave ***
p_i2c_slave : process
begin
I2cBusFree(I2cScl, I2cSda);
-- start of process !DO NOT EDIT
wait until Rst = '0';
wait until rising_edge(Clk);
-- *** Test Bus Busy ***
WaitForCase(StimCase, 0);
-- Not busy
wait for 1 us;
StdlCompare(0, BusBusy, "Busy 0");
-- A transfer is goiong on
I2cScl <= '0';
wait for 1 us;
StdlCompare(1, BusBusy, "Busy 1");
-- busy is kept
I2cScl <= 'Z';
wait for 10 us;
StdlCompare(1, BusBusy, "Busy 2");
-- released after timeout
wait for BusBusyTimeout_g*(1 sec);
StdlCompare(0, BusBusy, "Busy 3");
-- Asserted on start
I2cMasterSendStart(I2cScl, I2cSda, "Assert Start");
wait for 1 us;
StdlCompare(1, BusBusy, "Busy 4");
-- Released on stop
I2cMasterSendStop(I2cScl, I2cSda, "Assert Start");
wait for 1 us;
StdlCompare(0, BusBusy, "Busy 4");
I2cCase <= 0;
-- *** Test Start / Stop ***
WaitForCase(StimCase, 1);
I2cSlaveWaitStart(I2cScl, I2cSda, "Start");
I2cSlaveWaitRepeatedStart(I2cScl, I2cSda, "RepStart");
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop");
I2cCase <= 1;
-- *** Test Write ***
WaitForCase(StimCase, 2);
-- 1 Byte Ack
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 1b Ack");
I2cSlaveExpectByte(16#A3#, I2cScl, I2cSda, "Data 1b Ack", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop");
-- 2 Byte Ack, then NACK
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 2b ACK -> NACK");
I2cSlaveExpectByte(16#12#, I2cScl, I2cSda, "Data 2b ACK -> NACK 1", '0');
I2cSlaveExpectByte(16#34#, I2cScl, I2cSda, "Data 2b ACK -> NACK 2", '1');
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop");
I2cCase <= 2;
-- *** Test Read ***
WaitForCase(StimCase, 3);
-- 1 Byte Ack
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 1b Ack");
I2cSlaveSendByte(16#67#, I2cScl, I2cSda, "Data 1b Ack", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop");
-- 2 Byte Ack, then NACK
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 2b ACK -> NACK");
I2cSlaveSendByte(16#34#, I2cScl, I2cSda, "Data 2b ACK -> NACK 1", '0');
I2cSlaveSendByte(16#56#, I2cScl, I2cSda, "Data 2b ACK -> NACK 2", '1');
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop");
I2cCase <= 3;
-- *** Test Clock Stretching ***
WaitForCase(StimCase, 4);
-- 1 Byte Read Ack
I2cSlaveWaitStart(I2cScl, I2cSda, "Start Read 1b Ack");
I2cSlaveSendByte(16#67#, I2cScl, I2cSda, "Data Write 1b Ack", '0', ClkStretch => 1 us);
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop", ClkStretch => 1 us);
-- 2 Byte Write Ack, then NACK
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 2b Write ACK -> NACK");
I2cSlaveExpectByte(16#12#, I2cScl, I2cSda, "Data 2b Write ACK -> NACK 1", '0', ClkStretch => 1 us);
I2cSlaveExpectByte(16#34#, I2cScl, I2cSda, "Data 2b Write ACK -> NACK 2", '1', ClkStretch => 1 us);
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop", ClkStretch => 1 us);
-- Write / Read
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 2b W->R");
I2cSlaveExpectByte(16#12#, I2cScl, I2cSda, "Write 2b W->R", '0', ClkStretch => 1 us);
I2cSlaveWaitRepeatedStart(I2cScl, I2cSda, "RepStart 2b W->R", ClkStretch => 1 us);
I2cSlaveSendByte(16#67#, I2cScl, I2cSda, "Read 2b W->R", '0', ClkStretch => 1 us);
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop 2b W->R", ClkStretch => 1 us);
I2cCase <= 4;
-- *** Test Delayed Command ***
WaitForCase(StimCase, 5);
-- 1 Byte Ack, delay shorter than timeout
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 1b Ack");
I2cSlaveSendByte(16#67#, I2cScl, I2cSda, "Data 1b Ack", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop");
-- Command Timeout (Timeout after start, stop generated internally)
I2cSlaveWaitStart(I2cScl, I2cSda, "Start 1b Ack");
I2cSlaveWaitStop(I2cScl, I2cSda, "Stop");
I2cCase <= 5;
-- *** Test Arbitration ***
WaitForCase(StimCase, 6);
-- Multi Master, Same Write
I2cSlaveWaitStart(I2cScl, I2cSda, "S: Start 1b Ack");
I2cSlaveExpectByte(16#A3#, I2cScl, I2cSda, "S: Data 1b Ack", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "S: Stop");
-- Arbitration Lost during Write
I2cSlaveWaitStart(I2cScl, I2cSda, "S: Start Lost Write");
I2cSlaveExpectByte(16#87#, I2cScl, I2cSda, "S: Stop Lost Write", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "S: Lost Write Stop");
-- Arbitration Lost STOP (other master continues writing)
I2cSlaveWaitStart(I2cScl, I2cSda, "S: Start Lost Stop");
I2cSlaveExpectByte(16#A3#, I2cScl, I2cSda, "S: Data Lost Stop 1", '0');
I2cSlaveExpectByte(16#12#, I2cScl, I2cSda, "S: Data Lost Stop 2", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "S: Stop Lost Stop");
-- Arbitration Lost during repeated start (other master continues writing)
I2cSlaveWaitStart(I2cScl, I2cSda, "S: Start Lost RepStartA");
I2cSlaveExpectByte(16#A3#, I2cScl, I2cSda, "S: Data Lost RepStartA 1", '0');
I2cSlaveExpectByte(16#12#, I2cScl, I2cSda, "S: Data Lost RepStartA 2", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "S: Stop Lost RepStartA");
-- Arbitration Lost during repeated start (other master stops)
I2cSlaveWaitStart(I2cScl, I2cSda, "S: Start Lost RepStartB");
I2cSlaveExpectByte(16#A3#, I2cScl, I2cSda, "S: Data Lost RepStartB 1", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "S: Stop Lost RepStartB");
-- Arbitration lost due to stop (during first bit of data)
I2cSlaveWaitStart(I2cScl, I2cSda, "S: Start Lost DueStop");
I2cSlaveExpectByte(16#A3#, I2cScl, I2cSda, "S: Data Lost DueStop 1", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "S: Stop Lost DueStop");
-- Arbitration lost due to rep-start (during first bit of data)
I2cSlaveWaitStart(I2cScl, I2cSda, "S: Start Lost RepStart");
I2cSlaveExpectByte(16#A3#, I2cScl, I2cSda, "S: Write Lost RepStart 1", '0');
I2cSlaveWaitRepeatedStart(I2cScl, I2cSda, "S: Lost RepStart RepStart");
I2cSlaveSendByte(16#34#, I2cScl, I2cSda, "S: Read Lost RepStart RepStart", '0');
I2cSlaveWaitStop(I2cScl, I2cSda, "S: Stop Lost RepStart");
I2cCase <= 6;
-- end of process !DO NOT EDIT!
ProcessDone(TbProcNr_i2c_c) <= '1';
wait;
end process;
-- *** i2c master ***
p_i2c_master : process
begin
I2cBusFree(I2cScl, I2cSda);
-- *** Test Arbitration ***
WaitForCase(StimCase, 6);
-- Multi Master, Same Write
I2cSlaveWaitStart(I2cScl, I2cSda, "M: Start 1b Ack");
-- small delay
I2cScl <= '0';
wait for 100 ns;
-- continue
I2cMasterSendByte(16#A3#, I2cScl, I2cSda, "M: Data 1b Ack");
I2cMasterSendStop(I2cScl, I2cSda, "M: Stop");
-- Arbitration Lost during Write
I2cSlaveWaitStart(I2cScl, I2cSda, "M: Start Lost Write");
I2cMasterSendByte(16#87#, I2cScl, I2cSda, "M: Data Lost Write");
I2cMasterSendStop(I2cScl, I2cSda, "M: Stop Loast Read");
-- Arbitration Lost STOP (other master continues writing)
I2cSlaveWaitStart(I2cScl, I2cSda, "M: Start Lost Stop");
I2cMasterSendByte(16#A3#, I2cScl, I2cSda, "M: Data Lost Stop 1");
I2cMasterSendByte(16#12#, I2cScl, I2cSda, "M: Data Lost Stop 2");
I2cMasterSendStop(I2cScl, I2cSda, "M: Stop Lost Stop");
-- Arbitration Lost during repeated start (other master continues writing)
I2cSlaveWaitStart(I2cScl, I2cSda, "M: Start Lost RepStartA");
I2cMasterSendByte(16#A3#, I2cScl, I2cSda, "M: Data Lost RepStartA 1");
I2cMasterSendByte(16#12#, I2cScl, I2cSda, "M: Data Lost RepStartA 2");
I2cMasterSendStop(I2cScl, I2cSda, "M: Stop Lost RepStartA");
-- Arbitration Lost during repeated start (other master stops)
I2cSlaveWaitStart(I2cScl, I2cSda, "M: Start Lost RepStartB");
I2cMasterSendByte(16#A3#, I2cScl, I2cSda, "M: Data Lost RepStartB 1");
I2cMasterSendStop(I2cScl, I2cSda, "M: Stop Lost RepStartB");
-- Arbitration lost due to stop (during first bit of data)
I2cSlaveWaitStart(I2cScl, I2cSda, "M: Start Lost DueStop");
I2cMasterSendByte(16#A3#, I2cScl, I2cSda, "M: Data Lost DueStop 1");
I2cMasterSendStop(I2cScl, I2cSda, "M: Stop Lost DueStop");
-- Arbitration lost due to rep-start (during first bit of data)
I2cSlaveWaitStart(I2cScl, I2cSda, "M: Start Lost DueRepstart");
I2cMasterSendByte(16#A3#, I2cScl, I2cSda, "M: write Lost DueRepstart 1");
I2cMasterSendRepeatedStart(I2cScl, I2cSda, "M: Stop Lost DueRepstart");
I2cMasterExpectByte(16#34#, I2cScl, I2cSda, "M: read Lost DueRepstart 1");
I2cMasterSendStop(I2cScl, I2cSda, "M: Stop Lost DueRepstart");
wait;
end process;
end;
|
-- Greg Stitt
-- University of Florida
-- Description:
-- This file implements a fifo entity. The fifo has a configurable depth
-- and width, and can use bram, distributed ram, or LUTs/FFs to implement
-- the buffer. The fifo also has a configurable output delay of either 0 or 1
-- cycles.
--
-- This entity does not implement the behavior of the fifo and instead
-- instantiates fifo_core architectures depending on the configuration of
-- generics. The fifo and fifo_core could potentially be combined, but having
-- recursive instantiations causes problems with some simulators, which this
-- implementation tries to avoid.
-- Notes:
-- The fifo protects against invalid writes (i.e. when full) and invalid reads
-- (i.e. when empty)
--
-- (use_bram = true and same_cycle_output = true) is not supported by
-- all FPGAs.
--
-- When using BRAM, the FIFO depth is rounded up to the nearest power of two.
--
-- The actual choice of RAM depends on the specific synthesis tool and FPGA.
-- This entity does not guarantee the correct type.
-- Used entities:
-- fifo_core
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.math_custom.all;
-------------------------------------------------------------------------------
-- Generics Description
-- width : the width of the FIFO in bits (required)
-- depth : the depth of the FIFO in words (required)
-- almost_full_count : the count at which almost_full is asserted (default = 0)
-- use_bram : uses bram when true, uses LUTs/FFs when false
-- (default = true)
-- use_distribted_ram : uses distributed ram when true. If use_bram is also
-- true, use_distributed_ram is ignore. If both are false,
-- use LUTS/FFs. (default = false)
-- same_cycle_output : when true, output appears in same cycle as read. when
-- false, output appears one cycle after read.
-- (default = false)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description: (all control inputs are active high)
-- clk : clock
-- rst : reset (asynchronous)
-- rd : read enable
-- wr : write enable
-- empty : asserted when the FIFO is empty
-- full : asserted when the FIFO is full
-- almost_full : asserted when count >= almost_full_count
-- input : Input to write into the FIFO
-- output : Output read from the FIFO
-------------------------------------------------------------------------------
entity fifo is
generic(width : positive;
depth : positive;
almost_full_count : natural := 0;
use_bram : boolean := true;
use_distributed_ram : boolean := false;
same_cycle_output : boolean := false);
port(clk : in std_logic;
rst : in std_logic;
rd : in std_logic;
wr : in std_logic;
empty : out std_logic;
full : out std_logic;
almost_full : out std_logic;
count : out std_logic_vector(bitsNeeded(depth)-1 downto 0);
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0));
end fifo;
architecture DEFAULT of fifo is
begin
-- if the user doesn't want any type of ram, use the flip-flop architecture
FF : if use_bram = false and use_distributed_ram = false generate
U_FIFO_FF : entity work.fifo_core(FF)
generic map (width => width,
depth => depth,
almost_full_count => almost_full_count,
use_bram => false,
same_cycle_output => same_cycle_output)
port map (clk => clk,
rst => rst,
rd => rd,
wr => wr,
empty => empty,
full => full,
almost_full => almost_full,
count => count,
input => input,
output => output);
end generate FF;
-- for any type of memory, use the MEMORY architecture where the use_bram
-- option will specify the type of memory
MEMORY : if use_bram = true or use_distributed_ram = true generate
U_FIFO_RAM : entity work.fifo_core(MEMORY)
generic map (width => width,
depth => depth,
almost_full_count => almost_full_count,
use_bram => use_bram,
same_cycle_output => same_cycle_output)
port map (clk => clk,
rst => rst,
rd => rd,
wr => wr,
empty => empty,
full => full,
almost_full => almost_full,
count => count,
input => input,
output => output);
end generate MEMORY;
end DEFAULT;
|
--Helpful resource:
--ftp://www.cs.uregina.ca/pub/class/301/multiplexer/lecture.html
library IEEE;
use IEEE.std_logic_1164.all;
entity mux8 is
port(
bus0 : in std_logic_vector(3 downto 0) := (others => '-');
bus1 : in std_logic_vector(3 downto 0) := (others => '-');
bus2 : in std_logic_vector(3 downto 0) := (others => '-');
bus3 : in std_logic_vector(3 downto 0) := (others => '-');
bus4 : in std_logic_vector(3 downto 0) := (others => '-');
bus5 : in std_logic_vector(3 downto 0) := (others => '-');
bus6 : in std_logic_vector(3 downto 0) := (others => '-');
bus7 : in std_logic_vector(3 downto 0) := (others => '-');
S : in std_logic_vector(2 downto 0);
R : out std_logic_vector(3 downto 0)
);
end mux8;
architecture Behavioural of mux8 is
begin
with S select
R <= bus0 when "000",
bus1 when "001",
bus2 when "010",
bus3 when "011",
bus4 when "100",
bus5 when "101",
bus6 when "110",
bus7 when others;
end Behavioural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1881.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01881ent IS
END c07s01b00x00p08n01i01881ent;
ARCHITECTURE c07s01b00x00p08n01i01881arch OF c07s01b00x00p08n01i01881ent IS
type small_int is range 0 to 7;
BEGIN
TESTING : PROCESS
variable tmp : small_int;
BEGIN
case TESTING is -- process labels illegal here
when 0 => tmp := 0;
when others => tmp := 1;
end case;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01881 - Process labels are not permitted as primaries in a case expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01881arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1881.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01881ent IS
END c07s01b00x00p08n01i01881ent;
ARCHITECTURE c07s01b00x00p08n01i01881arch OF c07s01b00x00p08n01i01881ent IS
type small_int is range 0 to 7;
BEGIN
TESTING : PROCESS
variable tmp : small_int;
BEGIN
case TESTING is -- process labels illegal here
when 0 => tmp := 0;
when others => tmp := 1;
end case;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01881 - Process labels are not permitted as primaries in a case expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01881arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1881.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01881ent IS
END c07s01b00x00p08n01i01881ent;
ARCHITECTURE c07s01b00x00p08n01i01881arch OF c07s01b00x00p08n01i01881ent IS
type small_int is range 0 to 7;
BEGIN
TESTING : PROCESS
variable tmp : small_int;
BEGIN
case TESTING is -- process labels illegal here
when 0 => tmp := 0;
when others => tmp := 1;
end case;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01881 - Process labels are not permitted as primaries in a case expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01881arch;
|
--------------------------------------------------------------------------------
--
-- tbmsgs.vhdl
--
-- Testbench messages
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tbmsgs is
procedure testcase(
constant desc : in string;
constant count : in natural);
procedure check(
constant good : in boolean;
constant desc : in string);
procedure tested(
constant desc : in string);
procedure testcase_complete;
end;
package body tbmsgs is
shared variable total_tests : natural := 0;
shared variable total_errors : integer := 0;
shared variable completed_tests : natural := 0;
procedure testcase(
constant desc : in string;
constant count : in natural) is
begin
report "|tbmsgs| *** running test case: " & desc;
total_tests := count;
end procedure;
procedure check(
constant good : in boolean;
constant desc : in string) is
begin
if not good then
report "|tbmsgs| ERROR: " & desc;
total_errors := total_errors + 1;
end if;
end procedure;
procedure tested(
constant desc : in string) is
begin
report "|tbmsgs| tested: " & desc;
completed_tests := completed_tests + 1;
end procedure;
procedure testcase_complete is
begin
report "|tbmsgs| tests run: " & integer'image(completed_tests) &
"/" & integer'image(total_tests) & ", errors: " &
integer'image(total_errors);
end procedure;
end;
|
--------------------------------------------------------------------------------
--
-- tbmsgs.vhdl
--
-- Testbench messages
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tbmsgs is
procedure testcase(
constant desc : in string;
constant count : in natural);
procedure check(
constant good : in boolean;
constant desc : in string);
procedure tested(
constant desc : in string);
procedure testcase_complete;
end;
package body tbmsgs is
shared variable total_tests : natural := 0;
shared variable total_errors : integer := 0;
shared variable completed_tests : natural := 0;
procedure testcase(
constant desc : in string;
constant count : in natural) is
begin
report "|tbmsgs| *** running test case: " & desc;
total_tests := count;
end procedure;
procedure check(
constant good : in boolean;
constant desc : in string) is
begin
if not good then
report "|tbmsgs| ERROR: " & desc;
total_errors := total_errors + 1;
end if;
end procedure;
procedure tested(
constant desc : in string) is
begin
report "|tbmsgs| tested: " & desc;
completed_tests := completed_tests + 1;
end procedure;
procedure testcase_complete is
begin
report "|tbmsgs| tests run: " & integer'image(completed_tests) &
"/" & integer'image(total_tests) & ", errors: " &
integer'image(total_errors);
end procedure;
end;
|
--This should pass
context c1 is
end context c1;
--These should fail
context c1 is
end context c1;
context c1 is
end context c1;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:06:40 02/19/2017
-- Design Name:
-- Module Name: sumpleto - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sumpleto is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
s : out STD_LOGIC);
end sumpleto;
architecture Behavioral of sumpleto is
-- VHDL Instantiation Created from source file sumador_medio.vhd -- 20:10:20 02/19/2017
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
COMPONENT sumador_medio
PORT(
a : IN std_logic;
b : IN std_logic;
cout : OUT std_logic;
s : OUT std_logic
);
END COMPONENT;
signal out0 : STD_LOGIC := '0';
signal c0 : STD_LOGIC := '0';
signal out1 : STD_LOGIC := '0';
begin
Inst_sumador_medio_1: sumador_medio PORT MAP(
a => a,
b => b,
cout => out0,
s => c0
);
Inst_sumador_medio_2: sumador_medio PORT MAP(
a => c0,
b => cin,
cout => out1,
s => s
);
Inst_sumador_medio_3: sumador_medio PORT MAP(
a => out0,
b => out1,
--cout => ,
s => cout
);
end Behavioral;
|
-- NEED RESULT: ARCH00082.P1: Multi transport transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00082.P2: Multi transport transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00082.P3: Multi transport transactions occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00082: One transport transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00082: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00082: One transport transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00082: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00082: One transport transaction occurred on signal asg with indexed name on LHS passed
-- NEED RESULT: ARCH00082: Old transactions were removed on signal asg with indexed name on LHS passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00082
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00082(ARCH00082)
-- ENT00082_Test_Bench(ARCH00082_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00082 is
port (
s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_st_arr1 : inout st_arr1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr1 : out chk_sig_type
)
is
begin
case counter is
when 0 =>
s_st_arr1 (st_arr1'Left) <= transport
c_st_arr1_2 (st_arr1'Right) after 10 ns,
c_st_arr1_1 (st_arr1'Right) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_2 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00082.P1" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr1 (st_arr1'Left) <= transport
c_st_arr1_2 (st_arr1'Right) after 10 ns,
c_st_arr1_1 (st_arr1'Right) after 20 ns,
c_st_arr1_2 (st_arr1'Right) after 30 ns,
c_st_arr1_1 (st_arr1'Right) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr1 (st_arr1'Left) =
c_st_arr1_2 (st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1 (st_arr1'Left) <= transport
c_st_arr1_1 (st_arr1'Right) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr1 (st_arr1'Left) =
c_st_arr1_1 (st_arr1'Right) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00082" ,
"One transport transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
test_report ( "ARCH00082" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00082" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_arr2 : inout st_arr2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr2 : out chk_sig_type
)
is
begin
case counter is
when 0 =>
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00082.P2" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_2 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr2 (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_1 (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00082" ,
"One transport transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
test_report ( "ARCH00082" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00082" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_arr3 : inout st_arr3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr3 : out chk_sig_type
)
is
begin
case counter is
when 0 =>
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00082.P3" ,
"Multi transport transactions occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_2 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr3 (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_1 (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00082" ,
"One transport transaction occurred on signal " &
"asg with indexed name on LHS",
correct ) ;
test_report ( "ARCH00082" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00082" ,
"Old transactions were removed on signal " &
"asg with indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00082 ;
--
architecture ARCH00082 of ENT00082 is
begin
PGEN_CHKP_1 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_arr1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_arr1 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_arr1,
counter,
correct,
savtime,
chk_st_arr1
) ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_arr2 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_arr2,
counter,
correct,
savtime,
chk_st_arr2
) ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_arr3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_arr3 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_arr3,
counter,
correct,
savtime,
chk_st_arr3
) ;
end process P3 ;
--
--
end ARCH00082 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00082_Test_Bench is
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
end ENT00082_Test_Bench ;
--
architecture ARCH00082_Test_Bench of ENT00082_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00082 ( ARCH00082 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1
, s_st_arr2
, s_st_arr3
) ;
end block L1 ;
end ARCH00082_Test_Bench ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3040.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY vests29 IS
END vests29;
ARCHITECTURE c12s02b02x00p01n02i03040arch OF vests29 IS
type c_a is array(integer range <>) of integer;
type c_r is
record
i : integer;
r : real;
b : bit;
end record;
BEGIN
-- test for no associations
bl1 : block
generic(i:c_a(1 to 3):=(10,10,10); r:c_r:=(10,3.4,'1'));
begin
assert ((i(1)=10) and (i(2)=10) and (i(3)=10))
report "Default value for array generic not correct"
severity failure;
assert ((r.i=10) and (r.r=3.4) and (r.b='1'))
report "Default value for record generic not correct"
severity failure;
assert NOT((i(1)=10) and (i(2)=10) and (i(3)=10) and (r.i=10) and (r.r=3.4) and (r.b='1'))
report "***PASSED TEST: c12s02b02x00p01n02i03040"
severity NOTE;
assert ((i(1)=10) and (i(2)=10) and (i(3)=10) and (r.i=10) and (r.r=3.4) and (r.b='1'))
report "***FAILED TEST: c12s02b02x00p01n02i03040 - The actual part of an implicit association element is the default expression test failed."
severity ERROR;
end block;
END c12s02b02x00p01n02i03040arch;
|
-------------------------------------------------------------------------------
-- Copyright Institut Pascal Equipe Dream (19-10-2016)
-- Francois Berry, El Mehdi Abdali, Maxime Pelcat
-- This software is a computer program whose purpose is to manage dynamic
-- partial reconfiguration.
-- This software is governed by the CeCILL-C license under French law and
-- abiding by the rules of distribution of free software. You can use,
-- modify and/ or redistribute the software under the terms of the CeCILL-C
-- license as circulated by CEA, CNRS and INRIA at the following URL
-- "http://www.cecill.info".
-- As a counterpart to the access to the source code and rights to copy,
-- modify and redistribute granted by the license, users are provided only
-- with a limited warranty and the software's author, the holder of the
-- economic rights, and the successive licensors have only limited
-- liability.
-- In this respect, the user's attention is drawn to the risks associated
-- with loading, using, modifying and/or developing or reproducing the
-- software by the user in light of its specific status of free software,
-- that may mean that it is complicated to manipulate, and that also
-- therefore means that it is reserved for developers and experienced
-- professionals having in-depth computer knowledge. Users are therefore
-- encouraged to load and test the software's suitability as regards their
-- requirements in conditions enabling the security of their systems and/or
-- data to be ensured and, more generally, to use and operate it in the
-- same conditions as regards security.
-- The fact that you are presently reading this means that you have had
-- knowledge of the CeCILL-C license and that you accept its terms.
-------------------------------------------------------------------------------
-- Doxygen Comments -----------------------------------------------------------
--! @file d5m_controller.vhd
--
--! @brief D5M CMOS Image sensor controller
--! @author Francois Berry, El Mehdi Abdali, Maxime Pelcat
--! @board SoCKit from Arrow and Terasic
--! @version 1.0
--! @date 16/11/2016
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity d5m_controller is
generic
(
pixel_address_width : integer
);
port
(
-----
-- Board I/Os
clk : in std_logic; -- Input clock for processing and sent to CCD_XCLKIN
reset_n : in std_logic;
ccd_trigger : out std_logic; -- Enable
ccd_reset : out std_logic; -- Reset sensor
ccd_xclkin : out std_logic;
ccd_data : in std_logic_vector(11 downto 0);
ccd_fval : in std_logic;
ccd_lval : in std_logic;
ccd_pixclk : in std_logic;
i_exposure_adj : in std_logic; -- Adjusting exposure
i2c_sclk : out std_logic;
i2c_sdata : inout std_logic;
-----
-- Unused I/Os (for future extensions)
pix_address : out std_logic_vector(pixel_address_width-1 downto 0);
oRed : out std_logic_vector(7 downto 0);
oGreen : out std_logic_vector(7 downto 0);
oBlue : out std_logic_vector(7 downto 0);
-----
-- GPStudio i/os
data : out std_logic_vector(7 downto 0); -- gray data output
dv : out std_logic; -- data valid
fv : out std_logic -- flow valid
);
end d5m_controller;
architecture arch of d5m_controller is
component CCD_Capture
port
(
oDATA : out std_logic_vector(11 downto 0);
oDVAL : out std_logic;
oX_Cont : out std_logic_vector(15 downto 0);
oY_Cont : out std_logic_vector(15 downto 0);
oFrame_Cont : out std_logic_vector(31 downto 0);
iDATA : in std_logic_vector(11 downto 0);
iFVAL : in std_logic;
iLVAL : in std_logic;
iSTART : in std_logic;
iEND : in std_logic;
iCLK : in std_logic;
iRST : in std_logic;
oADDRESS : out std_logic_vector(23 downto 0);
oLVAL : out std_logic
);
end component CCD_Capture;
component I2C_CCD_Config
port
(
iCLK : in std_logic;
iRST_N : in std_logic;
iZOOM_MODE_SW : in std_logic;
iEXPOSURE_ADJ : in std_logic;
iEXPOSURE_DEC_p : in std_logic;
I2C_SCLK : out std_logic;
I2C_SDAT : inout std_logic
);
end component I2C_CCD_Config;
component RAW2RGB
port
(
iCLK : in std_logic;
iRST : in std_logic;
iDATA : in std_logic_vector(11 downto 0);
iDVAL : in std_logic;
oRed : out std_logic_vector(11 downto 0);
oGreen : out std_logic_vector(11 downto 0);
oBlue : out std_logic_vector(11 downto 0);
oDVAL : out std_logic;
iX_Cont : in std_logic_vector(15 downto 0);
iY_Cont : in std_logic_vector(15 downto 0)
);
end component RAW2RGB;
component RGB2GRY
port
(
clk : in std_logic;
reset : in std_logic;
src_CCD_R : in std_logic_vector(11 downto 0);
src_CCD_G : in std_logic_vector(11 downto 0);
src_CCD_B : in std_logic_vector(11 downto 0);
oCCD_GRY : out std_logic_vector(7 downto 0)
);
end component RGB2GRY;
component VideoSampler
generic(
DATA_WIDTH : integer;
PIXEL_WIDTH : integer;
FIFO_DEPTH : integer;
DEFAULT_SCR : integer;
DEFAULT_FLOWLENGHT : integer;
HREF_POLARITY : string;
VSYNC_POLARITY : string
);
port(
-- input from CLOCK50 domain
clk_i : in std_logic;
reset_n_i : in std_logic;
-- inputs from camera
pclk_i : in std_logic;
href_i : in std_logic;
vsync_i : in std_logic;
pixel_i : in std_logic_vector(7 downto 0);
-- params from slave
enable_i : in std_logic;
flowlength_i : in std_logic_vector(31 downto 0);
-- Stream interface
data_o : out std_logic_vector(7 downto 0);
dv_o : out std_logic;
fv_o : out std_logic
);
end component;
signal sCCD_R, sCCD_G, sCCD_B, mCCD_DATA : std_logic_vector(11 downto 0);
signal mCCD_DVAL, sCCD_DVAL : std_logic;
signal X_Cont, Y_Cont : std_logic_vector(15 downto 0);
signal frame_count : std_logic_vector(31 downto 0);
signal temp_pix_address : std_logic_vector(23 downto 0);
signal sig_LVAL : std_logic;
signal m_DATA : std_logic_vector(7 downto 0);
constant DEFAULT_FLOWLENGTH : std_logic_vector(31 downto 0) := x"00140000"; -- 1280*1024
begin
-- Preparing debayering
CCD_Capture_inst : CCD_Capture
port map
(
iDATA => ccd_data,
iFVAL => ccd_fval,
iLVAL => ccd_lval,
iSTART => '1', -- always activating
iEND => '0',
iCLK => ccd_pixclk,
iRST => reset_n,
oDATA => mCCD_DATA,
oDVAL => mCCD_DVAL,
oX_Cont => X_Cont,
oY_Cont => Y_Cont,
oFrame_Cont => frame_count,
oADDRESS => temp_pix_address,
oLVAL => sig_LVAL
);
-- Debayering
RAW2RGB_inst : RAW2RGB
port map
(
iCLK => ccd_pixclk,
iRST => reset_n,
iDATA => mCCD_DATA,
iDVAL => mCCD_DVAL,
oRed => sCCD_R,
oGreen => sCCD_G,
oBlue => sCCD_B,
oDVAL => sCCD_DVAL,
iX_Cont => X_Cont,
iY_Cont => Y_Cont
);
-- Converting to grayscale
RGB2GRY_int : RGB2GRY
port map
(
clk => clk,
reset => not(reset_n),
src_CCD_R => sCCD_R(11 downto 0),
src_CCD_G => sCCD_G(11 downto 0),
src_CCD_B => sCCD_B(11 downto 0),
oCCD_GRY => m_DATA
);
I2C_CCD_Config_inst : I2C_CCD_Config
port map
(
iCLK => clk,
iRST_N => reset_n,
iZOOM_MODE_SW => '0',
iEXPOSURE_ADJ => i_exposure_adj,
iEXPOSURE_DEC_p => '0',
I2C_SCLK => i2c_sclk,
I2C_SDAT => i2c_sdata
);
-- Resampling
VideoSampler_inst : VideoSampler
generic map (
PIXEL_WIDTH => 8,
DATA_WIDTH => 32,
FIFO_DEPTH => 4096*4,
DEFAULT_SCR => 0,
DEFAULT_FLOWLENGHT => 1280*1024,
HREF_POLARITY => "high",
VSYNC_POLARITY => "high"
)
port map (
reset_n_i => reset_n,
clk_i => clk,
pclk_i => ccd_pixclk,
href_i => ccd_lval,
vsync_i => ccd_fval,
pixel_i => m_DATA,
enable_i => '1',
flowlength_i => DEFAULT_FLOWLENGTH,
data_o => data,
dv_o => dv,
fv_o => fv
);
oRed <= sCCD_R(11 downto 4);
oGreen <= sCCD_G(11 downto 4);
oBlue <= sCCD_B(11 downto 4);
ccd_xclkin <= clk;
ccd_trigger <= '1';
ccd_reset <= '1';
pix_address <= temp_pix_address(pixel_address_width-1 downto 0);
end arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_DM is
Port ( PC : in STD_LOGIC_VECTOR (4 downto 0);
RFsource : in std_logic_vector (1 downto 0);
DataToMem : in STD_LOGIC_VECTOR (31 downto 0);
ALUResult : in STD_LOGIC_VECTOR (31 downto 0);
DataToReg : out STD_LOGIC_VECTOR (31 downto 0)
);
end MUX_DM;
architecture Behavioral of MUX_DM is
begin
process(PC, RFsource, DataToMem, ALUResult) begin
if(RFsource = "00") then
DataToReg <= DataToMem;
elsif(RFsource = "01") then
DataToReg <= ALUResult;
else
DataToReg(4 downto 0) <= PC;
DataToReg(31 downto 5) <= (others => '0');
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:08:51 06/04/2016
-- Design Name:
-- Module Name: Mux4to1_8bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Mux4to1_1bit is
port(A, B, C, D : in std_logic;
sel : in std_logic_vector(1 downto 0);
S : out std_logic);
end Mux4to1_1bit;
architecture Behavioral of Mux4to1_1bit is
begin
with sel select
s <= A when "00",
B when "01",
C when "10",
D when "11",
'X' when others;
end Behavioral;
|
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the testbench for simulating the
--! Plasma-SoC.
-------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.plasoc_gpio_pack.all;
use work.boot_pack.all;
entity testbench_vivado_0 is
generic ( gpio_width : integer := 16; input_delay : time := 0 ns );
end testbench_vivado_0;
architecture Behavioral of testbench_vivado_0 is
component axiplasma_wrapper is
generic (
lower_app : string := "boot";
upper_app : string := "main";
upper_ext : boolean := false);
port(
raw_clock : in std_logic; -- 100 MHz on the Nexys 4.
raw_nreset : in std_logic;
gpio_output : out std_logic_vector(default_data_out_width-1 downto 0);
gpio_input : in std_logic_vector(default_data_in_width-1 downto 0);
uart_tx : out std_logic;
uart_rx : in std_logic;
DDR2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
DDR2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR2_cas_n : out STD_LOGIC;
DDR2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR2_ras_n : out STD_LOGIC;
DDR2_we_n : out STD_LOGIC);
end component;
constant clock_period : time := 10 ns;
constant uart_period : time := 104167 ns;
constant time_out_threshold : integer := 2**30;
subtype gpio_type is std_logic_vector(gpio_width-1 downto 0);
signal raw_clock : std_logic := '1';
signal raw_nreset : std_logic := '0';
signal gpio_output : gpio_type;
signal gpio_input : gpio_type := (others=>'0');
signal uart_tx : std_logic;
signal uart_clock : std_logic := '1';
signal uart_tx_data_avail : std_logic := '0';
signal uart_tx_data_ack : std_logic := '0';
signal uart_tx_started : boolean := false;
signal uart_tx_counter : integer range 0 to 8 := 0;
signal uart_tx_buffer : std_logic_vector(7 downto 0) := (others=>'0');
signal uart_tx_data : std_logic_vector(7 downto 0) := (others=>'0');
signal uart_rx : std_logic;
signal uart_rx_enable : std_logic := '0';
signal uart_rx_done : std_logic := '0';
signal uart_rx_data : std_logic_vector(7 downto 0) := (others=>'0');
signal uart_rx_counter : integer range 0 to 9 := 0;
signal boot_checksum : std_logic_vector(7 downto 0) := (others=>'0');
begin
axiplasma_wrapper_inst : axiplasma_wrapper
port map (
raw_clock => raw_clock,
raw_nreset => raw_nreset,
gpio_output => gpio_output,
gpio_input => gpio_input,
uart_tx => uart_tx,
uart_rx => uart_rx,
DDR2_addr => open,
DDR2_ba => open,
DDR2_cas_n => open,
DDR2_ck_n => open,
DDR2_ck_p => open,
DDR2_cke => open,
DDR2_cs_n => open,
DDR2_dm => open,
DDR2_dq => open,
DDR2_dqs_n => open,
DDR2_dqs_p => open,
DDR2_odt => open,
DDR2_ras_n => open,
DDR2_we_n => open);
raw_clock <= not raw_clock after clock_period/2;
raw_nreset <= '1' after 10*clock_period+input_delay;
-- Get uart_tx
uart_clock <= not uart_clock after uart_period/2;
process (uart_clock)
begin
if rising_edge(uart_clock) then
if uart_tx_started then
uart_tx_counter <= uart_tx_counter+1;
if uart_tx_counter=8 then
uart_tx_data <= uart_tx_buffer;
uart_tx_started <= false;
else
uart_tx_buffer(uart_tx_counter) <= uart_tx;
end if;
elsif uart_tx='0' then
uart_tx_started <= true;
uart_tx_counter <= 0;
end if;
if uart_tx_data_ack='1' then
uart_tx_data_avail <= '0';
elsif uart_tx_started and uart_tx_counter=8 then
uart_tx_data_avail <= '1';
end if;
end if;
end process;
-- Set uart_rx
uart_rx_done <= '1' when uart_rx_counter=9 else '0';
process (uart_clock)
begin
if rising_edge(uart_clock) then
if uart_rx_enable='1' then
if uart_rx_counter/=9 then
uart_rx_counter <= uart_rx_counter+1;
if uart_rx_counter=0 then
uart_rx <= '0';
elsif uart_rx_counter<= 8 then
uart_rx <= uart_rx_data(uart_rx_counter-1);
end if;
else
uart_rx <= '1';
end if;
else
uart_rx_counter <= 0;
uart_rx <= '1';
end if;
end if;
end process;
process
constant word_width : integer := 32;
subtype byte_type is std_logic_vector(7 downto 0);
subtype word_type is std_logic_vector(word_width-1 downto 0);
constant BOOT_LOADER_START_WORD : word_type := x"f0f0f0f0";
constant BOOT_LOADER_ACK_SUCCESS_BYTE : byte_type := x"01";
constant BOOT_LOADER_ACK_FAILURE_BYTE : byte_type := x"02";
constant BOOT_LOADER_STATUS_MORE : byte_type := x"01";
constant BOOT_LOADER_STATUS_DONE : byte_type := x"02";
constant BOOT_LOADER_CHECKSUM_DIVISOR : integer := 230;
variable word : word_type;
variable byte : byte_type;
variable app_data : ram_type := load_hex;
variable app_ptr : integer := 0;
procedure set_uart_rx( byte : in byte_type ) is
begin
uart_rx_data <= byte;
uart_rx_enable <= '1';
wait until uart_rx_done='1';
wait for uart_period;
uart_rx_enable <= '0';
wait for uart_period;
end;
procedure set_uart_word ( word : in word_type ) is
begin
for each_byte in 0 to word_width/8-1 loop
set_uart_rx(word(7+each_byte*8 downto each_byte*8));
end loop;
end;
procedure get_uart_tx is
begin
wait until uart_tx_data_avail='1';
wait for uart_period;
byte := uart_tx_data;
uart_tx_data_ack <= '1';
wait for uart_period;
uart_tx_data_ack <= '0';
wait for uart_period;
end;
begin
-- wait until raw_nreset='1';
-- wait until gpio_output=X"0001";
-- wait for 2 ms;
-- set_uart_word(BOOT_LOADER_START_WORD);
-- get_uart_tx;
-- if byte=BOOT_LOADER_ACK_SUCCESS_BYTE then
-- report "Success ACK";
-- elsif byte=BOOT_LOADER_ACK_FAILURE_BYTE then
-- report "Failed ACK";
-- wait;
-- else
-- report "???";
-- wait;
-- end if;
-- while true loop
-- -- instruction
-- word := app_data(app_ptr);
-- set_uart_word(word);
-- -- checksum
-- word := std_logic_vector(unsigned(word) mod BOOT_LOADER_CHECKSUM_DIVISOR);
-- boot_checksum <= word(7 downto 0);
-- set_uart_rx(word(7 downto 0));
-- -- status
-- app_ptr := app_ptr+1;
-- --if app_ptr=ram_size then
-- if app_ptr=13 then
-- set_uart_rx(BOOT_LOADER_STATUS_DONE);
-- exit;
-- else
-- set_uart_rx(BOOT_LOADER_STATUS_MORE);
-- end if;
-- -- ack
-- get_uart_tx;
-- if byte=BOOT_LOADER_ACK_SUCCESS_BYTE then
-- report "Success ACK";
-- elsif byte=BOOT_LOADER_ACK_FAILURE_BYTE then
-- report "Failed ACK";
-- wait;
-- else
-- report "???";
-- wait;
-- end if;
-- end loop;
wait;
end process;
-- Run testbench application.
process
-- This procedure should force the simulation to stop if a
-- problem becomes apparent.
procedure assert_procedure( state : boolean; mesg : string ) is
variable breaksimulation : std_logic_vector(0 downto 0);
begin
if not state then
assert False report mesg severity error;
breaksimulation(1) := '1';
end if;
end;
-- The procedure sets a single specified bit of the gpio input interface.
procedure set_gpio_input( gpio_index : integer ) is
variable gpio_input_buff : gpio_type := (others=>'0');
begin
gpio_input_buff(gpio_index) := '1';
gpio_input <= gpio_input_buff;
wait for clock_period;
end;
-- Waits for the corresponding output response. If it takes too long,
-- it is assumed there is an error and the simulation should end as a result.
procedure wait_for_gpio_output is
variable assert_counter : integer := 0;
begin
while gpio_output/=gpio_input loop
assert_procedure( state => assert_counter/=time_out_threshold, mesg => "Timeout occurred." );
assert_counter := assert_counter+1;
wait for clock_period;
end loop;
wait for clock_period;
end;
begin
wait until raw_nreset='1';
wait until gpio_output=X"0001";
wait for 500 us;
gpio_input <= X"0003" after input_delay;
wait for 2 ms;
gpio_input <= X"00f3" after input_delay;
wait for 2 ms;
while True loop
gpio_input <= X"00f1" after input_delay;
wait for 50 us;
gpio_input <= X"00f0" after input_delay;
wait for 50 us;
gpio_input <= X"00f5" after input_delay;
wait for 50 us;
gpio_input <= X"00ff" after input_delay;
wait for 50 us;
gpio_input <= X"05f7" after input_delay;
wait for 50 us;
gpio_input <= X"10f0" after input_delay;
wait for 50 us;
end loop;
wait;
end process;
end Behavioral;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 8.5e-07,
W => Wdiff_0,
Wdiff_0init => 7.6e-06,
scope => private
)
port map(
D => net2,
G => net1,
S => net3
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 8.5e-07,
W => Wdiff_0,
Wdiff_0init => 7.6e-06,
scope => private
)
port map(
D => out1,
G => out1,
S => net3
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => W_0,
W_0init => 5.89e-05
)
port map(
D => net3,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.55e-06,
W => Wcm_1,
Wcm_1init => 8.5e-07,
scope => private
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.55e-06,
W => Wcmout_1,
Wcmout_1init => 6.28e-05,
scope => private
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net2
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.5e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.5e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => vbias2,
G => vbias3,
S => net4
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net5,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net5,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net5,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
--------------------------------------------------------------------------------------------------
-- Multi-channel FIR Tap
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package multichannel_fir_tap_pkg is
--FIR tap component declaration
component multichannel_fir_tap is
port( clk : in std_logic;
rst : in std_logic;
coef : in coefficient;
sig_in : in sig;
sig_out : out sig;
sum_in : in fir_sig;
sum_out : out fir_sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
--This entity represents a single tap in a FIR filter. The taps are designed to implement a
--cascade adder allowing for chaining an indefinite (tho definitely finite) number of taps.
entity multichannel_fir_tap is
port( clk : in std_logic;
rst : in std_logic;
coef : in coefficient;
sig_in : in sig;
sig_out : out sig;
sum_in : in fir_sig;
sum_out : out fir_sig);
end multichannel_fir_tap;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE (behavioral)
--------------------------------------------------------------------------------------------------
architecture behave of multichannel_fir_tap is
signal sig_delay : sig_array(1 to 4) := (others => (others => '0'));
signal coef_reg : coefficient := (others => '0');
signal product : fir_sig := (others => '0');
begin
--delay the input signal
delay_sig : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sig_delay <= (others => (others => '0'));
else
sig_delay(1) <= sig_in;
sig_delay(2) <= sig_delay(1);
sig_delay(3) <= sig_delay(2);
sig_delay(4) <= sig_delay(3);
end if;
end if;
end process;
sig_out <= sig_delay(3);
--register the coefficient
reg_coef : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
coef_reg <= (others => '0');
else
coef_reg <= coef;
end if;
end if;
end process;
--multiply the signal to the tap coefficient
multiply : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
product <= (others => '0');
else
product <= resize(sig_delay(4) * coef_reg, NUM_FIR_BITS);
end if;
end if;
end process;
--update the sum
update_sum : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sum_out <= (others => '0');
else
sum_out <= sum_in + product;
end if;
end if;
end process;
end behave;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2018.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02018ent IS
END c07s02b04x00p01n01i02018ent;
ARCHITECTURE c07s02b04x00p01n01i02018arch OF c07s02b04x00p01n01i02018ent IS
BEGIN
TESTING: PROCESS
variable y : bit;
BEGIN
y := bit'('1') + 3; -- Failure_here
-- + operator predefined only for numeric
-- types.
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02018 - The adding operators are predefined only for numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02018arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2018.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02018ent IS
END c07s02b04x00p01n01i02018ent;
ARCHITECTURE c07s02b04x00p01n01i02018arch OF c07s02b04x00p01n01i02018ent IS
BEGIN
TESTING: PROCESS
variable y : bit;
BEGIN
y := bit'('1') + 3; -- Failure_here
-- + operator predefined only for numeric
-- types.
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02018 - The adding operators are predefined only for numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02018arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2018.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02018ent IS
END c07s02b04x00p01n01i02018ent;
ARCHITECTURE c07s02b04x00p01n01i02018arch OF c07s02b04x00p01n01i02018ent IS
BEGIN
TESTING: PROCESS
variable y : bit;
BEGIN
y := bit'('1') + 3; -- Failure_here
-- + operator predefined only for numeric
-- types.
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02018 - The adding operators are predefined only for numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02018arch;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file addsb_11_0_26986301a9f671cd.vhd when simulating
-- the core, addsb_11_0_26986301a9f671cd. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY addsb_11_0_26986301a9f671cd IS
PORT (
a : IN STD_LOGIC_VECTOR(24 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(24 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(24 DOWNTO 0)
);
END addsb_11_0_26986301a9f671cd;
ARCHITECTURE addsb_11_0_26986301a9f671cd_a OF addsb_11_0_26986301a9f671cd IS
-- synthesis translate_off
COMPONENT wrapped_addsb_11_0_26986301a9f671cd
PORT (
a : IN STD_LOGIC_VECTOR(24 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(24 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(24 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_addsb_11_0_26986301a9f671cd USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 25,
c_add_mode => 0,
c_ainit_val => "0",
c_b_constant => 0,
c_b_type => 0,
c_b_value => "0000000000000000000000000",
c_b_width => 25,
c_borrow_low => 1,
c_bypass_low => 0,
c_ce_overrides_bypass => 1,
c_ce_overrides_sclr => 0,
c_has_bypass => 0,
c_has_c_in => 0,
c_has_c_out => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_implementation => 0,
c_latency => 0,
c_out_width => 25,
c_sclr_overrides_sset => 0,
c_sinit_val => "0",
c_verbosity => 0,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_addsb_11_0_26986301a9f671cd
PORT MAP (
a => a,
b => b,
s => s
);
-- synthesis translate_on
END addsb_11_0_26986301a9f671cd_a;
|
library ieee;
use ieee.std_logic_1164.all;
use work.utilities.all;
package arith_dsp48e is
------------------------------------------------------------------------------------------
-- Fixed-point divider using DSP48E slice
------------------------------------------------------------------------------------------
-- Performs the operation "n_i" (numerator) divided by "d_i" (denominator), both
-- containing "G_DATAIN_WIDTH" bits, and presents the result in "q_o" (quotient) and
-- "r_o" (remainder) after "G_PRECISION"+2 clock cycles. "q_o" contains "G_PRECISION"+1
-- bits (msb is the sign bit, 2's complement) and "r_o" contains the same number of bits
-- as "n_i" and "d_i". Both division results (quotient and remainder) has the decimal
-- point shifted "G_PRECISION" bits to the left in relation to the operands' (numerator
-- and denominator) decimal points, which must be in the same position.
--
-- "trg" and "rdy" are one-clock-cycle controls to request new division calculation and
-- indicate its completion, respectively.
--
-- "err_o" is asserted when a trigger comes before a division completion. A new trigger
-- is only allowed after "G_PRECISION"+1 clock cycles after the valid trigger.
--
-- Known limitations:
-- - The denominator must be greater than the numerator.
-- - The denominator must be positive.
------------------------------------------------------------------------------------------
component div_fixedpoint is
generic
(
G_DATAIN_WIDTH : integer range 2 to 48;
G_PRECISION : integer range 1 to 47
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
n_i : in std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
d_i : in std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
q_o : out std_logic_vector(G_PRECISION downto 0);
r_o : out std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
trg_i : in std_logic;
rdy_o : out std_logic;
err_o : out std_logic
);
end component;
------------------------------------------------------------------------------------------
-- Floating-point divider using DSP48E slice
------------------------------------------------------------------------------------------
-- Performs the operation "n_i" (numerator) divided by "d_i" (denominator), both
-- containing "G_DATA_WIDTH" bits, and presents the result in "q_o" (quotient) and
-- "r_o" (remainder) after "G_DATA_WIDTH"+4 clock cycles. "q_o" and "r_o" contain the
-- same number of bits as "n_i" and "d_i" (msb is the sign bit, 2's complement). The
-- decimal point of "n_i" or the decimal point of "d_i" is shifted to the left before
-- performing a fixed-point division. With the left shift, the "n_i" arithmetic msb is
-- put one position below the "d_i" arithmetic msb. The shift amplitude is presented in
-- the "shift_o" output.
--
-- The final division result (quotient and remainder) has the decimal point shifted by
-- "G_DATA_WIDTH" - 1 + shift_o.
--
-- "trg" and "rdy" are one-clock-cycle flags to request new division calculation and
-- indicate its completion, respectively.
--
-- "err_o" is asserted when a trigger comes before a division completion. A new trigger
-- is only allowed after "G_DATA_WIDTH"+5 clock cycles after the valid trigger.
--
-- Known limitations:
-- - The denominator must be positive.
-- - It is not possible to trigger a new calculation during the clock cycle that data
-- ready is asserted.
-- - The position of the most significant bit of the numerator must not exceed
-- "G_DATA_WIDTH"-3.
------------------------------------------------------------------------------------------
component div_floatingpoint is
generic
(
G_DATA_WIDTH : integer range 2 to 48
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
n_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
d_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
q_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
r_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
shift_o : out std_logic_vector(log2(G_DATA_WIDTH) downto 0);
trg_i : in std_logic;
rdy_o : out std_logic;
err_o : out std_logic
);
end component;
------------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
component div_ieee754_single is
generic
(
G_DATA_WIDTH : integer range 2 to 48
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
n_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
d_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
q_o : out std_logic_vector(31 downto 0);
trg_i : in std_logic;
rdy_o : out std_logic;
err_o : out std_logic
);
end component;
end arith_dsp48e;
----------------------------------------------------------------------------------------------
-- div_fixedpoint
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity div_fixedpoint is
generic
(
G_DATAIN_WIDTH : integer range 2 to 48 := 48;
G_PRECISION : integer range 1 to 47 := 47
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
n_i : in std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
d_i : in std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
q_o : out std_logic_vector(G_PRECISION downto 0);
r_o : out std_logic_vector(G_DATAIN_WIDTH-1 downto 0);
trg_i : in std_logic;
rdy_o : out std_logic;
err_o : out std_logic
);
end div_fixedpoint;
architecture rtl of div_fixedpoint is
-- Division initialization and operands hold
signal slv_n_hold : std_logic_vector(G_DATAIN_WIDTH-1 downto 0) := (others => '0');
signal slv_d_hold : std_logic_vector(G_DATAIN_WIDTH-1 downto 0) := (others => '0');
signal slv_alumode_init : std_logic_vector(3 downto 0) := (others => '0');
-- Start/stop divison signals
signal sl_init : std_logic := '1';
signal sl_finished : std_logic;
-- Iteration counter
signal uv_count : unsigned(5 downto 0) :=(others => '0');
constant C_MAX_COUNT : unsigned(5 downto 0) := to_unsigned(G_PRECISION+1, 6);
-- Entity outputs (auxiliary signals)
signal slv_q : std_logic_vector(G_PRECISION downto 0) := (others => '0');
signal slv_r : std_logic_vector(G_DATAIN_WIDTH-1 downto 0) := (others => '0');
signal sl_err : std_logic := '0';
-- DSP48E inputs
signal slv_r_extended : std_logic_vector(47 downto 0);
signal slv_d_hold_extended : std_logic_vector(47 downto 0);
signal slv_alumode : std_logic_vector(3 downto 0);
-- DSP48E outputs
signal slv_r_fb : std_logic_vector(47 downto 0);
signal slv_carryout : std_logic_vector(3 downto 0);
begin
DSP48E_inst : DSP48E
generic map
(
ALUMODEREG => 0,
AREG => 0,
ACASCREG => 0,
A_INPUT => "DIRECT",
BREG => 0,
BCASCREG => 0,
B_INPUT => "DIRECT",
CREG => 0,
MREG => 0,
OPMODEREG => 0,
PREG => 1,
USE_MULT => "NONE"
)
port map
(
CARRYOUT => slv_carryout,
P => slv_r_fb,
A => slv_d_hold_extended(47 downto 18),
ACIN => (others => '0'),
ALUMODE => slv_alumode,
B => slv_d_hold_extended(17 downto 0),
BCIN => (others => '0'),
C => slv_r_extended,
CARRYCASCIN => '0',
CARRYIN => '0',
CARRYINSEL => "000",
CEA1 => '0',
CEA2 => ce_i,
CEALUMODE => ce_i,
CEB1 => '0',
CEB2 => ce_i,
CEC => '0',
CECARRYIN => ce_i,
CECTRL => '0',
CEM => '0',
CEMULTCARRYIN => '0',
CEP => ce_i,
CLK => clk_i,
MULTSIGNIN => '0',
OPMODE => "0110011",
PCIN => (others => '0'),
RSTA => rst_i,
RSTALLCARRYIN => rst_i,
RSTALUMODE => rst_i,
RSTB => rst_i,
RSTC => rst_i,
RSTCTRL => rst_i,
RSTM => rst_i,
RSTP => rst_i
);
-- Holds numerator, denominator and add/subtract operation for division initalization
prc_hold_operands : process(clk_i)
begin
if rising_edge(clk_i) then
if ce_i = '1' then
if trg_i = '1' then
slv_n_hold <= n_i;
slv_d_hold <= d_i;
slv_alumode_init <= "00" & not(n_i(G_DATAIN_WIDTH-1)) & not(n_i(G_DATAIN_WIDTH-1));
end if;
end if;
end if;
end process;
-- Iteration counter and start/stop division control
prc_control : process(rst_i, clk_i)
begin
if rst_i = '1' then
sl_init <= '1';
uv_count <= (others => '0');
rdy_o <= '0';
sl_err <= '0';
elsif rising_edge(clk_i) then
if ce_i = '1' then
if uv_count = 0 then
-- Assert data ready ("rdy_o") for one clock cycle if no error has occured
if sl_err = '0' then
if sl_finished = '0' then
rdy_o <= '1';
else
rdy_o <= '0';
end if;
end if;
if trg_i = '1' then
uv_count <= C_MAX_COUNT;
sl_init <= '1';
sl_finished <= '0';
sl_err <= '0';
else
sl_finished <= '1';
end if;
else
uv_count <= uv_count - 1;
sl_init <= '0';
rdy_o <= '0';
-- If a new trigger comes before completion of current division processing,
-- asserts error output high until a new trigger comes in a legal time instant
if trg_i = '1' then
sl_err <= '1';
end if;
end if;
end if;
end if;
end process;
-- Builds quotient bit vector
prc_quotient : process(clk_i)
begin
if rising_edge(clk_i) then
if ce_i = '1' then
slv_q <= slv_q(G_PRECISION-1 downto 0) & slv_carryout(3);
end if;
end if;
end process;
-- Assigns internal signals to output
q_o <= slv_q;
r_o <= slv_r;
err_o <= sl_err;
-- Sets next remainder (current remainder shifted to the left by 2) (or initialization)
slv_r <= slv_n_hold when sl_init = '1' else
slv_r_fb(G_DATAIN_WIDTH-2 downto 0) & '0';
-- Sets next operation (add or subtract) based on carry bit (or initialization)
slv_alumode <= slv_alumode_init when sl_init = '1' else
"00" & slv_carryout(3) & slv_carryout(3);
-- Sign extension for DSP48E input signals
slv_d_hold_extended(G_DATAIN_WIDTH-1 downto 0) <= slv_d_hold;
slv_d_hold_extended(47 downto G_DATAIN_WIDTH) <= (others => slv_d_hold(G_DATAIN_WIDTH-1));
slv_r_extended(G_DATAIN_WIDTH-1 downto 0) <= slv_r;
slv_r_extended(47 downto G_DATAIN_WIDTH) <= (others => slv_r(G_DATAIN_WIDTH-1));
end rtl;
----------------------------------------------------------------------------------------------
-- div_floatingpoint
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arith_dsp48e.all;
use work.utilities.all;
library unisim;
use unisim.vcomponents.all;
entity div_floatingpoint is
generic
(
G_DATA_WIDTH : integer range 2 to 48 := 48
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
n_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
d_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
q_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
r_o : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
shift_o : out std_logic_vector(log2(G_DATA_WIDTH) downto 0);
trg_i : in std_logic;
rdy_o : out std_logic;
err_o : out std_logic
);
end div_floatingpoint;
architecture rtl of div_floatingpoint is
-- FSM states
type state_type is (IDLE, CALCULATE_SHIFT, SHIFT, DIVIDE);
signal state : state_type;
-- Division initialization and operands hold
signal slv_n_hold : std_logic_vector(G_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_d_hold : std_logic_vector(G_DATA_WIDTH-1 downto 0) := (others => '0');
-- Entity outputs (auxiliary signals)
signal sl_rdy : std_logic;
signal sl_err : std_logic;
-- Start/stop divison signals
signal sl_init : std_logic;
-- Number of bits to shift for increasing division precision
signal sv_shift : signed(log2(G_DATA_WIDTH) downto 0) := (others => '0');
begin
div_fixedpoint_inst : div_fixedpoint
generic map
(
G_DATAIN_WIDTH => G_DATA_WIDTH,
G_PRECISION => G_DATA_WIDTH-1
)
port map
(
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_i,
n_i => slv_n_hold,
d_i => slv_d_hold,
q_o => q_o,
r_o => r_o,
trg_i => sl_init,
rdy_o => sl_rdy,
err_o => open
);
-- Assigns internal signals to output
shift_o <= std_logic_vector(sv_shift);
err_o <= sl_err;
-- Only asserts ready output if fixed-point division has finished and there was no bad trigger.
rdy_o <= sl_rdy and not(sl_err);
-- Finite state-machine which sequences the operations: wait for trigger (idle), calculate shift, shift and divide.
prc_fsm : process(rst_i, clk_i)
variable v_sv_msb_n, v_sv_msb_d : signed(log2(G_DATA_WIDTH) downto 0);
variable v_sv_n_hold, v_sv_d_hold : signed(G_DATA_WIDTH-1 downto 0);
variable v_i_shift : integer range 0 to G_DATA_WIDTH-1;
begin
if rst_i = '1' then
state <= IDLE;
sl_init <= '0';
elsif rising_edge(clk_i) then
if ce_i = '1' then
case state is
when IDLE =>
if trg_i = '1' then
state <= CALCULATE_SHIFT;
end if;
slv_n_hold <= n_i;
slv_d_hold <= d_i;
when CALCULATE_SHIFT =>
state <= SHIFT;
v_sv_msb_n := signed(find_msb(slv_n_hold, slv_n_hold(slv_n_hold'left)));
v_sv_msb_d := signed(find_msb(slv_d_hold, slv_d_hold(slv_d_hold'left)));
sv_shift <= v_sv_msb_d - v_sv_msb_n - 1;
sl_init <= '0';
when SHIFT =>
state <= DIVIDE;
v_i_shift := to_integer(abs(sv_shift));
if sv_shift > 0 then
v_sv_n_hold := signed(slv_n_hold);
slv_n_hold <= std_logic_vector(v_sv_n_hold sll v_i_shift);
else
v_sv_d_hold := signed(slv_d_hold);
slv_d_hold <= std_logic_vector(v_sv_d_hold sll v_i_shift);
end if;
sl_init <= '1';
when DIVIDE =>
if sl_rdy = '1' and trg_i = '1' then
state <= CALCULATE_SHIFT;
elsif sl_rdy = '1' then
state <= IDLE;
end if;
sl_init <= '0';
when others =>
state <= IDLE;
end case;
end if;
end if;
end process;
-- Asserts error when trigger comes before end of division.
prc_error : process(rst_i, clk_i)
begin
if rst_i = '1' then
sl_err <= '0';
elsif rising_edge(clk_i) then
if ce_i = '1' then
if state = IDLE and trg_i = '1' then
sl_err <= '0';
elsif state = DIVIDE and trg_i = '1' and sl_rdy = '1' then
sl_err <= '0';
elsif trg_i = '1' then
sl_err <= '1';
end if;
end if;
end if;
end process;
end rtl;
----------------------------------------------------------------------------------------------
-- div_ieee754_single
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arith_dsp48e.all;
use work.utilities.all;
library unisim;
use unisim.vcomponents.all;
entity div_ieee754_single is
generic
(
G_DATA_WIDTH : integer range 2 to 48 := 48
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
n_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
d_i : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
q_o : out std_logic_vector(31 downto 0);
trg_i : in std_logic;
rdy_o : out std_logic;
err_o : out std_logic
);
end div_ieee754_single;
architecture rtl of div_ieee754_single is
-- FSM states
type state_type is (IDLE, CHECK_SIGNAL, CALCULATE_SHIFT, SHIFT, CHECK_ADDITIONAL_SHIFT, DIVIDE);
signal state : state_type := IDLE;
-- Division initialization and operands hold
signal slv_n_hold : std_logic_vector(G_DATA_WIDTH-1 downto 0) := (others => '0');
signal slv_d_hold : std_logic_vector(G_DATA_WIDTH-1 downto 0) := (others => '0');
-- Entity outputs (auxiliary signals)
signal sl_rdy : std_logic;
signal sl_err : std_logic;
-- Start/stop divison signals
signal sl_init : std_logic := '0';
-- Sections of 32-bit single precision binary
signal slv_signed_mantissa : std_logic_vector(24 downto 0);
signal sv_exponent : signed(7 downto 0);
signal sl_result_signal : std_logic;
-- Number of bits to shift for increasing division precision
signal sv_shift : signed(log2(G_DATA_WIDTH) downto 0) := (others => '0');
begin
div_fixedpoint_inst : div_fixedpoint
generic map
(
G_DATAIN_WIDTH => G_DATA_WIDTH,
G_PRECISION => 24
)
port map
(
clk_i => clk_i,
rst_i => rst_i,
ce_i => ce_i,
n_i => slv_n_hold,
d_i => slv_d_hold,
q_o => slv_signed_mantissa,
r_o => open,
trg_i => sl_init,
rdy_o => sl_rdy,
err_o => open
);
-- Assigns internal signals to output
-- Note: additional shift for making 1 <= mantissa < 2 (instead of .5 <= mantissa < 1 result of integer division)
-- The msb (always equals to 1 (positive number) or 0 (negative number)) is discarded since the IEEE 754 already considers it implicitly)
q_o <= sl_result_signal & std_logic_vector(sv_exponent) & slv_signed_mantissa(22 downto 0);
err_o <= sl_err;
-- Only asserts ready output if fixed-point division has finished and there was no bad trigger.
rdy_o <= sl_rdy and not(sl_err);
-- Finite state-machine which sequences the operations: wait for trigger (idle), calculate shift, shift and divide.
prc_fsm : process(rst_i, clk_i)
variable v_sv_msb_n, v_sv_msb_d : signed(log2(G_DATA_WIDTH) downto 0);
variable v_sv_n_hold, v_sv_d_hold : signed(G_DATA_WIDTH-1 downto 0);
variable v_i_shift : integer range 0 to G_DATA_WIDTH-1;
begin
if rst_i = '1' then
state <= IDLE;
sl_init <= '0';
elsif rising_edge(clk_i) then
if ce_i = '1' then
case state is
when IDLE =>
if trg_i = '1' then
state <= CALCULATE_SHIFT;
sl_result_signal <= n_i(n_i'left);
slv_n_hold <= std_logic_vector(abs(signed(n_i)));
slv_d_hold <= d_i;
end if;
when CALCULATE_SHIFT =>
state <= SHIFT;
v_sv_msb_n := signed(find_msb(slv_n_hold, slv_n_hold(slv_n_hold'left)));
v_sv_msb_d := signed(find_msb(slv_d_hold, slv_d_hold(slv_d_hold'left)));
sv_shift <= v_sv_msb_d - v_sv_msb_n;
sl_init <= '0';
when SHIFT =>
state <= CHECK_ADDITIONAL_SHIFT;
v_i_shift := to_integer(abs(sv_shift));
if sv_shift > 0 then
v_sv_n_hold := signed(slv_n_hold);
slv_n_hold <= std_logic_vector(v_sv_n_hold sll v_i_shift);
else
v_sv_d_hold := signed(slv_d_hold);
slv_d_hold <= std_logic_vector(v_sv_d_hold sll v_i_shift);
end if;
sl_init <= '0';
when CHECK_ADDITIONAL_SHIFT =>
state <= DIVIDE;
v_sv_n_hold := signed(slv_n_hold);
v_sv_d_hold := signed(slv_d_hold);
if (v_sv_n_hold > v_sv_d_hold) then
v_sv_n_hold := signed(slv_n_hold);
slv_n_hold <= std_logic_vector(v_sv_n_hold srl 1);
sv_shift <= sv_shift - 1;
end if;
sl_init <= '1';
when DIVIDE =>
-- Add 127 offset to exponent and subtract 1 due to additional shift for making 1 <= mantissa < 2
sv_exponent <= to_signed(126, 8) - resize(sv_shift, 8);
if sl_rdy = '1' and trg_i = '1' then
state <= CALCULATE_SHIFT;
elsif sl_rdy = '1' then
state <= IDLE;
end if;
sl_init <= '0';
when others =>
state <= IDLE;
end case;
end if;
end if;
end process;
-- Asserts error when trigger comes before end of division.
prc_error : process(rst_i, clk_i)
begin
if rst_i = '1' then
sl_err <= '0';
elsif rising_edge(clk_i) then
if ce_i = '1' then
if state = IDLE and trg_i = '1' then
sl_err <= '0';
elsif state = DIVIDE and trg_i = '1' and sl_rdy = '1' then
sl_err <= '0';
elsif trg_i = '1' then
sl_err <= '1';
end if;
end if;
end if;
end process;
end rtl;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:21:59 06/16/2015
-- Design Name:
-- Module Name: C:/project10/ROM_tb.vhd
-- Project Name: project10
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ROM
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ROM_tb IS
END ROM_tb;
ARCHITECTURE behavior OF ROM_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ROM
PORT(
add : IN std_logic_vector(4 downto 0);
data_out : OUT std_logic_vector(0 to 23)
);
END COMPONENT;
--Inputs
signal add : std_logic_vector(4 downto 0) := (others => '0');
--Outputs
signal data_out : std_logic_vector(0 to 23);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ROM PORT MAP (
add => add,
data_out => data_out
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
add<="00000";
wait for 20 ns;
add<="00001";
wait for 20 ns;
add<="00010";
wait for 20 ns;
add<="00100";
wait for 20 ns;
add<="00110";
wait for 20 ns;
add<="01000";
wait for 20 ns;
add<="01010";
wait for 20 ns;
add<="01100";
wait for 20 ns;
add<="01110";
-- insert stimulus here
wait;
end process;
END;
|
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_2;
end architecture ARCH;
|
-------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--!
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_ABLK_SIZE : integer := 128; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 1; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding style
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_CTR_AD_SIZE : integer := 16; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 16; --! Maximum size for the counter that keeps track of data
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_REVERSE_DBLK : integer := 0 --! Reverse block order (for message only)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! =================
--! Crypto Core Signals
--! =================
--! Data signals
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag data
--! Info signals
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! Control signals
key_ready : out std_logic; --! Indicates that the key is ready
key_needs_update : out std_logic; --! Indicates that the key needs update and should be acknowledge by the core via key_updated signal
key_updated : in std_logic; --! Key has been updated
rdkey_ready : out std_logic; --! (Optional) Round key ready
rdkey_read : in std_logic := '0'; --! (Optional) Round key read
npub_ready : out std_logic; --! (Optional) Npub ready
npub_read : in std_logic; --! (Optional) Npub read
nsec_ready : out std_logic; --! (Optional) Nsec ready
nsec_read : in std_logic := '0'; --! (Optional) Nsec read
bdi_ready : out std_logic; --! Block ready
bdi_proc : out std_logic; --! Block processing
bdi_ad : out std_logic; --! Input block is an authenticated data
bdi_nsec : out std_logic; --! Input block is a secret message number
bdi_decrypt : out std_logic; --! Decryption operation
bdi_pad : out std_logic; --! Last block of segment type contain padding
bdi_eot : out std_logic; --! Last block of segment type (end-of-type)
bdi_eoi : out std_logic; --! Last block of message (end-of-message)
bdi_nodata : out std_logic; --! Control signal indicating that there's no plain-text or authenticated data. The unit should generate a tag right away.
bdi_read : in std_logic; --! Handshake signal indicating that the data block has been read
bdi_size : out std_logic_vector(G_BS_BYTES -1 downto 0); --! Block size signal. Note: 0 = Full block.
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! PAD location
exp_tag_ready : out std_logic; --! Expected tag is ready
msg_auth_done : in std_logic; --! Message authentication completion signal
--! FIFO
bypass_fifo_full : in std_logic; --! An input signal indicating that the bypass FIFO is full
bypass_fifo_wr : out std_logic --! An output signal for writing data to bypass FIFO
);
end PreProcessor;
architecture structure of PreProcessor is
function isNPUBdisabled (a : integer ) return integer is
begin
if (a = 1 or a = 2) then
return 1;
else
return 0;
end if;
end function isNPUBdisabled;
function isKeyak (blksize: integer) return integer is
begin
if (G_DBLK_SIZE = 1344) then
return 1;
else
return 0;
end if;
end function isKeyak;
constant NPUB_DISABLE : integer := isNPUBdisabled(G_PLAINTEXT_MODE);
constant IS_KEYAK : integer := isKeyak(G_DBLK_SIZE);
signal en_data : std_logic;
signal en_npub : std_logic;
signal en_nsec : std_logic;
signal en_key : std_logic;
signal en_rdkey : std_logic;
signal sel_blank_pdi : std_logic;
signal clr_len : std_logic;
signal en_len_a_r : std_logic;
signal en_len_d_r : std_logic;
signal en_len_last_r : std_logic;
signal en_len_a : std_logic;
signal en_len_d : std_logic;
signal pad_enable : std_logic;
signal en_pad_loc : std_logic;
signal pad_eot : std_logic;
signal pad_eoi : std_logic;
signal pad_type_ad : std_logic;
signal pad_shift : std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
signal size_dword : std_logic_vector(log2_ceil(G_W/8) downto 0);
signal en_exp_tag : std_logic;
signal sel_input : std_logic_vector(2 downto 0);
signal en_last_word : std_logic;
signal key_updated_sel : std_logic;
signal key_updated_int : std_logic;
begin
uDP: entity work.PreProcessor_Datapath(dataflow)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_KEYAK => IS_KEYAK ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_PAD => G_PAD ,
G_PAD_STYLE => G_PAD_STYLE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
sdi => sdi ,
--! =================
--! Crypto Core Signals
--! =================
key_updated => key_updated_sel ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
npub => npub ,
nsec => nsec ,
len_a => len_a ,
len_d => len_d ,
exp_tag => exp_tag ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
sel_input => sel_input
);
uCtrl: entity work.PreProcessor_Control(behavior)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE ,
G_PLAINTEXT_MODE => G_PLAINTEXT_MODE ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_KEY_SIZE => G_KEY_SIZE ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_PAD => G_PAD ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D ,
G_TAG_SIZE => G_TAG_SIZE ,
G_KEYAK => IS_KEYAK
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi => sdi ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
error => open ,
--! =================
--! Crypto Core Signals
--! =================
--! control signals
key_ready => key_ready ,
key_needs_update => key_needs_update ,
key_updated => key_updated_sel ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_read => nsec_read ,
nsec_ready => nsec_ready ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_decrypt => bdi_decrypt ,
bdi_pad => bdi_pad ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_nodata => bdi_nodata ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bypass_fifo_full => bypass_fifo_full ,
bypass_fifo_wr => bypass_fifo_wr ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
key_updated_int => key_updated_int , --! Only used for Keyak
sel_input => sel_input
);
gKeyak1: if (IS_KEYAK = 1) generate
key_updated_sel <= key_updated_int;
end generate;
gKeyak0: if (IS_KEYAK = 0) generate
key_updated_sel <= key_updated;
end generate;
end structure;
|
-------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--!
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_ABLK_SIZE : integer := 128; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 1; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding style
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_CTR_AD_SIZE : integer := 16; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 16; --! Maximum size for the counter that keeps track of data
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_REVERSE_DBLK : integer := 0 --! Reverse block order (for message only)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! =================
--! Crypto Core Signals
--! =================
--! Data signals
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag data
--! Info signals
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! Control signals
key_ready : out std_logic; --! Indicates that the key is ready
key_needs_update : out std_logic; --! Indicates that the key needs update and should be acknowledge by the core via key_updated signal
key_updated : in std_logic; --! Key has been updated
rdkey_ready : out std_logic; --! (Optional) Round key ready
rdkey_read : in std_logic := '0'; --! (Optional) Round key read
npub_ready : out std_logic; --! (Optional) Npub ready
npub_read : in std_logic; --! (Optional) Npub read
nsec_ready : out std_logic; --! (Optional) Nsec ready
nsec_read : in std_logic := '0'; --! (Optional) Nsec read
bdi_ready : out std_logic; --! Block ready
bdi_proc : out std_logic; --! Block processing
bdi_ad : out std_logic; --! Input block is an authenticated data
bdi_nsec : out std_logic; --! Input block is a secret message number
bdi_decrypt : out std_logic; --! Decryption operation
bdi_pad : out std_logic; --! Last block of segment type contain padding
bdi_eot : out std_logic; --! Last block of segment type (end-of-type)
bdi_eoi : out std_logic; --! Last block of message (end-of-message)
bdi_nodata : out std_logic; --! Control signal indicating that there's no plain-text or authenticated data. The unit should generate a tag right away.
bdi_read : in std_logic; --! Handshake signal indicating that the data block has been read
bdi_size : out std_logic_vector(G_BS_BYTES -1 downto 0); --! Block size signal. Note: 0 = Full block.
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! PAD location
exp_tag_ready : out std_logic; --! Expected tag is ready
msg_auth_done : in std_logic; --! Message authentication completion signal
--! FIFO
bypass_fifo_full : in std_logic; --! An input signal indicating that the bypass FIFO is full
bypass_fifo_wr : out std_logic --! An output signal for writing data to bypass FIFO
);
end PreProcessor;
architecture structure of PreProcessor is
function isNPUBdisabled (a : integer ) return integer is
begin
if (a = 1 or a = 2) then
return 1;
else
return 0;
end if;
end function isNPUBdisabled;
function isKeyak (blksize: integer) return integer is
begin
if (G_DBLK_SIZE = 1344) then
return 1;
else
return 0;
end if;
end function isKeyak;
constant NPUB_DISABLE : integer := isNPUBdisabled(G_PLAINTEXT_MODE);
constant IS_KEYAK : integer := isKeyak(G_DBLK_SIZE);
signal en_data : std_logic;
signal en_npub : std_logic;
signal en_nsec : std_logic;
signal en_key : std_logic;
signal en_rdkey : std_logic;
signal sel_blank_pdi : std_logic;
signal clr_len : std_logic;
signal en_len_a_r : std_logic;
signal en_len_d_r : std_logic;
signal en_len_last_r : std_logic;
signal en_len_a : std_logic;
signal en_len_d : std_logic;
signal pad_enable : std_logic;
signal en_pad_loc : std_logic;
signal pad_eot : std_logic;
signal pad_eoi : std_logic;
signal pad_type_ad : std_logic;
signal pad_shift : std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
signal size_dword : std_logic_vector(log2_ceil(G_W/8) downto 0);
signal en_exp_tag : std_logic;
signal sel_input : std_logic_vector(2 downto 0);
signal en_last_word : std_logic;
signal key_updated_sel : std_logic;
signal key_updated_int : std_logic;
begin
uDP: entity work.PreProcessor_Datapath(dataflow)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_KEYAK => IS_KEYAK ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_PAD => G_PAD ,
G_PAD_STYLE => G_PAD_STYLE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
sdi => sdi ,
--! =================
--! Crypto Core Signals
--! =================
key_updated => key_updated_sel ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
npub => npub ,
nsec => nsec ,
len_a => len_a ,
len_d => len_d ,
exp_tag => exp_tag ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
sel_input => sel_input
);
uCtrl: entity work.PreProcessor_Control(behavior)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE ,
G_PLAINTEXT_MODE => G_PLAINTEXT_MODE ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_KEY_SIZE => G_KEY_SIZE ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_PAD => G_PAD ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D ,
G_TAG_SIZE => G_TAG_SIZE ,
G_KEYAK => IS_KEYAK
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi => sdi ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
error => open ,
--! =================
--! Crypto Core Signals
--! =================
--! control signals
key_ready => key_ready ,
key_needs_update => key_needs_update ,
key_updated => key_updated_sel ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_read => nsec_read ,
nsec_ready => nsec_ready ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_decrypt => bdi_decrypt ,
bdi_pad => bdi_pad ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_nodata => bdi_nodata ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bypass_fifo_full => bypass_fifo_full ,
bypass_fifo_wr => bypass_fifo_wr ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
key_updated_int => key_updated_int , --! Only used for Keyak
sel_input => sel_input
);
gKeyak1: if (IS_KEYAK = 1) generate
key_updated_sel <= key_updated_int;
end generate;
gKeyak0: if (IS_KEYAK = 0) generate
key_updated_sel <= key_updated;
end generate;
end structure;
|
-------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--!
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_ABLK_SIZE : integer := 128; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 1; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding style
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_CTR_AD_SIZE : integer := 16; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 16; --! Maximum size for the counter that keeps track of data
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_REVERSE_DBLK : integer := 0 --! Reverse block order (for message only)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! =================
--! Crypto Core Signals
--! =================
--! Data signals
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag data
--! Info signals
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! Control signals
key_ready : out std_logic; --! Indicates that the key is ready
key_needs_update : out std_logic; --! Indicates that the key needs update and should be acknowledge by the core via key_updated signal
key_updated : in std_logic; --! Key has been updated
rdkey_ready : out std_logic; --! (Optional) Round key ready
rdkey_read : in std_logic := '0'; --! (Optional) Round key read
npub_ready : out std_logic; --! (Optional) Npub ready
npub_read : in std_logic; --! (Optional) Npub read
nsec_ready : out std_logic; --! (Optional) Nsec ready
nsec_read : in std_logic := '0'; --! (Optional) Nsec read
bdi_ready : out std_logic; --! Block ready
bdi_proc : out std_logic; --! Block processing
bdi_ad : out std_logic; --! Input block is an authenticated data
bdi_nsec : out std_logic; --! Input block is a secret message number
bdi_decrypt : out std_logic; --! Decryption operation
bdi_pad : out std_logic; --! Last block of segment type contain padding
bdi_eot : out std_logic; --! Last block of segment type (end-of-type)
bdi_eoi : out std_logic; --! Last block of message (end-of-message)
bdi_nodata : out std_logic; --! Control signal indicating that there's no plain-text or authenticated data. The unit should generate a tag right away.
bdi_read : in std_logic; --! Handshake signal indicating that the data block has been read
bdi_size : out std_logic_vector(G_BS_BYTES -1 downto 0); --! Block size signal. Note: 0 = Full block.
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! PAD location
exp_tag_ready : out std_logic; --! Expected tag is ready
msg_auth_done : in std_logic; --! Message authentication completion signal
--! FIFO
bypass_fifo_full : in std_logic; --! An input signal indicating that the bypass FIFO is full
bypass_fifo_wr : out std_logic --! An output signal for writing data to bypass FIFO
);
end PreProcessor;
architecture structure of PreProcessor is
function isNPUBdisabled (a : integer ) return integer is
begin
if (a = 1 or a = 2) then
return 1;
else
return 0;
end if;
end function isNPUBdisabled;
function isKeyak (blksize: integer) return integer is
begin
if (G_DBLK_SIZE = 1344) then
return 1;
else
return 0;
end if;
end function isKeyak;
constant NPUB_DISABLE : integer := isNPUBdisabled(G_PLAINTEXT_MODE);
constant IS_KEYAK : integer := isKeyak(G_DBLK_SIZE);
signal en_data : std_logic;
signal en_npub : std_logic;
signal en_nsec : std_logic;
signal en_key : std_logic;
signal en_rdkey : std_logic;
signal sel_blank_pdi : std_logic;
signal clr_len : std_logic;
signal en_len_a_r : std_logic;
signal en_len_d_r : std_logic;
signal en_len_last_r : std_logic;
signal en_len_a : std_logic;
signal en_len_d : std_logic;
signal pad_enable : std_logic;
signal en_pad_loc : std_logic;
signal pad_eot : std_logic;
signal pad_eoi : std_logic;
signal pad_type_ad : std_logic;
signal pad_shift : std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
signal size_dword : std_logic_vector(log2_ceil(G_W/8) downto 0);
signal en_exp_tag : std_logic;
signal sel_input : std_logic_vector(2 downto 0);
signal en_last_word : std_logic;
signal key_updated_sel : std_logic;
signal key_updated_int : std_logic;
begin
uDP: entity work.PreProcessor_Datapath(dataflow)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_KEYAK => IS_KEYAK ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_PAD => G_PAD ,
G_PAD_STYLE => G_PAD_STYLE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
sdi => sdi ,
--! =================
--! Crypto Core Signals
--! =================
key_updated => key_updated_sel ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
npub => npub ,
nsec => nsec ,
len_a => len_a ,
len_d => len_d ,
exp_tag => exp_tag ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
sel_input => sel_input
);
uCtrl: entity work.PreProcessor_Control(behavior)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE ,
G_PLAINTEXT_MODE => G_PLAINTEXT_MODE ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_KEY_SIZE => G_KEY_SIZE ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_PAD => G_PAD ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D ,
G_TAG_SIZE => G_TAG_SIZE ,
G_KEYAK => IS_KEYAK
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi => sdi ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
error => open ,
--! =================
--! Crypto Core Signals
--! =================
--! control signals
key_ready => key_ready ,
key_needs_update => key_needs_update ,
key_updated => key_updated_sel ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_read => nsec_read ,
nsec_ready => nsec_ready ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_decrypt => bdi_decrypt ,
bdi_pad => bdi_pad ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_nodata => bdi_nodata ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bypass_fifo_full => bypass_fifo_full ,
bypass_fifo_wr => bypass_fifo_wr ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
key_updated_int => key_updated_int , --! Only used for Keyak
sel_input => sel_input
);
gKeyak1: if (IS_KEYAK = 1) generate
key_updated_sel <= key_updated_int;
end generate;
gKeyak0: if (IS_KEYAK = 0) generate
key_updated_sel <= key_updated;
end generate;
end structure;
|
-------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--!
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_ABLK_SIZE : integer := 128; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 1; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding style
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_CTR_AD_SIZE : integer := 16; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 16; --! Maximum size for the counter that keeps track of data
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_REVERSE_DBLK : integer := 0 --! Reverse block order (for message only)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! =================
--! Crypto Core Signals
--! =================
--! Data signals
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag data
--! Info signals
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! Control signals
key_ready : out std_logic; --! Indicates that the key is ready
key_needs_update : out std_logic; --! Indicates that the key needs update and should be acknowledge by the core via key_updated signal
key_updated : in std_logic; --! Key has been updated
rdkey_ready : out std_logic; --! (Optional) Round key ready
rdkey_read : in std_logic := '0'; --! (Optional) Round key read
npub_ready : out std_logic; --! (Optional) Npub ready
npub_read : in std_logic; --! (Optional) Npub read
nsec_ready : out std_logic; --! (Optional) Nsec ready
nsec_read : in std_logic := '0'; --! (Optional) Nsec read
bdi_ready : out std_logic; --! Block ready
bdi_proc : out std_logic; --! Block processing
bdi_ad : out std_logic; --! Input block is an authenticated data
bdi_nsec : out std_logic; --! Input block is a secret message number
bdi_decrypt : out std_logic; --! Decryption operation
bdi_pad : out std_logic; --! Last block of segment type contain padding
bdi_eot : out std_logic; --! Last block of segment type (end-of-type)
bdi_eoi : out std_logic; --! Last block of message (end-of-message)
bdi_nodata : out std_logic; --! Control signal indicating that there's no plain-text or authenticated data. The unit should generate a tag right away.
bdi_read : in std_logic; --! Handshake signal indicating that the data block has been read
bdi_size : out std_logic_vector(G_BS_BYTES -1 downto 0); --! Block size signal. Note: 0 = Full block.
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! PAD location
exp_tag_ready : out std_logic; --! Expected tag is ready
msg_auth_done : in std_logic; --! Message authentication completion signal
--! FIFO
bypass_fifo_full : in std_logic; --! An input signal indicating that the bypass FIFO is full
bypass_fifo_wr : out std_logic --! An output signal for writing data to bypass FIFO
);
end PreProcessor;
architecture structure of PreProcessor is
function isNPUBdisabled (a : integer ) return integer is
begin
if (a = 1 or a = 2) then
return 1;
else
return 0;
end if;
end function isNPUBdisabled;
function isKeyak (blksize: integer) return integer is
begin
if (G_DBLK_SIZE = 1344) then
return 1;
else
return 0;
end if;
end function isKeyak;
constant NPUB_DISABLE : integer := isNPUBdisabled(G_PLAINTEXT_MODE);
constant IS_KEYAK : integer := isKeyak(G_DBLK_SIZE);
signal en_data : std_logic;
signal en_npub : std_logic;
signal en_nsec : std_logic;
signal en_key : std_logic;
signal en_rdkey : std_logic;
signal sel_blank_pdi : std_logic;
signal clr_len : std_logic;
signal en_len_a_r : std_logic;
signal en_len_d_r : std_logic;
signal en_len_last_r : std_logic;
signal en_len_a : std_logic;
signal en_len_d : std_logic;
signal pad_enable : std_logic;
signal en_pad_loc : std_logic;
signal pad_eot : std_logic;
signal pad_eoi : std_logic;
signal pad_type_ad : std_logic;
signal pad_shift : std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
signal size_dword : std_logic_vector(log2_ceil(G_W/8) downto 0);
signal en_exp_tag : std_logic;
signal sel_input : std_logic_vector(2 downto 0);
signal en_last_word : std_logic;
signal key_updated_sel : std_logic;
signal key_updated_int : std_logic;
begin
uDP: entity work.PreProcessor_Datapath(dataflow)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_KEYAK => IS_KEYAK ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_PAD => G_PAD ,
G_PAD_STYLE => G_PAD_STYLE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
sdi => sdi ,
--! =================
--! Crypto Core Signals
--! =================
key_updated => key_updated_sel ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
npub => npub ,
nsec => nsec ,
len_a => len_a ,
len_d => len_d ,
exp_tag => exp_tag ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
sel_input => sel_input
);
uCtrl: entity work.PreProcessor_Control(behavior)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE ,
G_PLAINTEXT_MODE => G_PLAINTEXT_MODE ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_KEY_SIZE => G_KEY_SIZE ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_PAD => G_PAD ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D ,
G_TAG_SIZE => G_TAG_SIZE ,
G_KEYAK => IS_KEYAK
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi => sdi ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
error => open ,
--! =================
--! Crypto Core Signals
--! =================
--! control signals
key_ready => key_ready ,
key_needs_update => key_needs_update ,
key_updated => key_updated_sel ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_read => nsec_read ,
nsec_ready => nsec_ready ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_decrypt => bdi_decrypt ,
bdi_pad => bdi_pad ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_nodata => bdi_nodata ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bypass_fifo_full => bypass_fifo_full ,
bypass_fifo_wr => bypass_fifo_wr ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
key_updated_int => key_updated_int , --! Only used for Keyak
sel_input => sel_input
);
gKeyak1: if (IS_KEYAK = 1) generate
key_updated_sel <= key_updated_int;
end generate;
gKeyak0: if (IS_KEYAK = 0) generate
key_updated_sel <= key_updated;
end generate;
end structure;
|
-------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--!
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_ABLK_SIZE : integer := 128; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 1; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding style
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_CTR_AD_SIZE : integer := 16; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 16; --! Maximum size for the counter that keeps track of data
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_REVERSE_DBLK : integer := 0 --! Reverse block order (for message only)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! =================
--! Crypto Core Signals
--! =================
--! Data signals
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag data
--! Info signals
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! Control signals
key_ready : out std_logic; --! Indicates that the key is ready
key_needs_update : out std_logic; --! Indicates that the key needs update and should be acknowledge by the core via key_updated signal
key_updated : in std_logic; --! Key has been updated
rdkey_ready : out std_logic; --! (Optional) Round key ready
rdkey_read : in std_logic := '0'; --! (Optional) Round key read
npub_ready : out std_logic; --! (Optional) Npub ready
npub_read : in std_logic; --! (Optional) Npub read
nsec_ready : out std_logic; --! (Optional) Nsec ready
nsec_read : in std_logic := '0'; --! (Optional) Nsec read
bdi_ready : out std_logic; --! Block ready
bdi_proc : out std_logic; --! Block processing
bdi_ad : out std_logic; --! Input block is an authenticated data
bdi_nsec : out std_logic; --! Input block is a secret message number
bdi_decrypt : out std_logic; --! Decryption operation
bdi_pad : out std_logic; --! Last block of segment type contain padding
bdi_eot : out std_logic; --! Last block of segment type (end-of-type)
bdi_eoi : out std_logic; --! Last block of message (end-of-message)
bdi_nodata : out std_logic; --! Control signal indicating that there's no plain-text or authenticated data. The unit should generate a tag right away.
bdi_read : in std_logic; --! Handshake signal indicating that the data block has been read
bdi_size : out std_logic_vector(G_BS_BYTES -1 downto 0); --! Block size signal. Note: 0 = Full block.
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! PAD location
exp_tag_ready : out std_logic; --! Expected tag is ready
msg_auth_done : in std_logic; --! Message authentication completion signal
--! FIFO
bypass_fifo_full : in std_logic; --! An input signal indicating that the bypass FIFO is full
bypass_fifo_wr : out std_logic --! An output signal for writing data to bypass FIFO
);
end PreProcessor;
architecture structure of PreProcessor is
function isNPUBdisabled (a : integer ) return integer is
begin
if (a = 1 or a = 2) then
return 1;
else
return 0;
end if;
end function isNPUBdisabled;
function isKeyak (blksize: integer) return integer is
begin
if (G_DBLK_SIZE = 1344) then
return 1;
else
return 0;
end if;
end function isKeyak;
constant NPUB_DISABLE : integer := isNPUBdisabled(G_PLAINTEXT_MODE);
constant IS_KEYAK : integer := isKeyak(G_DBLK_SIZE);
signal en_data : std_logic;
signal en_npub : std_logic;
signal en_nsec : std_logic;
signal en_key : std_logic;
signal en_rdkey : std_logic;
signal sel_blank_pdi : std_logic;
signal clr_len : std_logic;
signal en_len_a_r : std_logic;
signal en_len_d_r : std_logic;
signal en_len_last_r : std_logic;
signal en_len_a : std_logic;
signal en_len_d : std_logic;
signal pad_enable : std_logic;
signal en_pad_loc : std_logic;
signal pad_eot : std_logic;
signal pad_eoi : std_logic;
signal pad_type_ad : std_logic;
signal pad_shift : std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
signal size_dword : std_logic_vector(log2_ceil(G_W/8) downto 0);
signal en_exp_tag : std_logic;
signal sel_input : std_logic_vector(2 downto 0);
signal en_last_word : std_logic;
signal key_updated_sel : std_logic;
signal key_updated_int : std_logic;
begin
uDP: entity work.PreProcessor_Datapath(dataflow)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_KEYAK => IS_KEYAK ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_PAD => G_PAD ,
G_PAD_STYLE => G_PAD_STYLE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
sdi => sdi ,
--! =================
--! Crypto Core Signals
--! =================
key_updated => key_updated_sel ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
npub => npub ,
nsec => nsec ,
len_a => len_a ,
len_d => len_d ,
exp_tag => exp_tag ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
sel_input => sel_input
);
uCtrl: entity work.PreProcessor_Control(behavior)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE ,
G_PLAINTEXT_MODE => G_PLAINTEXT_MODE ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_KEY_SIZE => G_KEY_SIZE ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_PAD => G_PAD ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D ,
G_TAG_SIZE => G_TAG_SIZE ,
G_KEYAK => IS_KEYAK
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi => sdi ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
error => open ,
--! =================
--! Crypto Core Signals
--! =================
--! control signals
key_ready => key_ready ,
key_needs_update => key_needs_update ,
key_updated => key_updated_sel ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_read => nsec_read ,
nsec_ready => nsec_ready ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_decrypt => bdi_decrypt ,
bdi_pad => bdi_pad ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_nodata => bdi_nodata ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bypass_fifo_full => bypass_fifo_full ,
bypass_fifo_wr => bypass_fifo_wr ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
key_updated_int => key_updated_int , --! Only used for Keyak
sel_input => sel_input
);
gKeyak1: if (IS_KEYAK = 1) generate
key_updated_sel <= key_updated_int;
end generate;
gKeyak0: if (IS_KEYAK = 0) generate
key_updated_sel <= key_updated;
end generate;
end structure;
|
-------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--!
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_ABLK_SIZE : integer := 128; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 1; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding style
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_CTR_AD_SIZE : integer := 16; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 16; --! Maximum size for the counter that keeps track of data
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_REVERSE_DBLK : integer := 0 --! Reverse block order (for message only)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! =================
--! Crypto Core Signals
--! =================
--! Data signals
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag data
--! Info signals
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! Control signals
key_ready : out std_logic; --! Indicates that the key is ready
key_needs_update : out std_logic; --! Indicates that the key needs update and should be acknowledge by the core via key_updated signal
key_updated : in std_logic; --! Key has been updated
rdkey_ready : out std_logic; --! (Optional) Round key ready
rdkey_read : in std_logic := '0'; --! (Optional) Round key read
npub_ready : out std_logic; --! (Optional) Npub ready
npub_read : in std_logic; --! (Optional) Npub read
nsec_ready : out std_logic; --! (Optional) Nsec ready
nsec_read : in std_logic := '0'; --! (Optional) Nsec read
bdi_ready : out std_logic; --! Block ready
bdi_proc : out std_logic; --! Block processing
bdi_ad : out std_logic; --! Input block is an authenticated data
bdi_nsec : out std_logic; --! Input block is a secret message number
bdi_decrypt : out std_logic; --! Decryption operation
bdi_pad : out std_logic; --! Last block of segment type contain padding
bdi_eot : out std_logic; --! Last block of segment type (end-of-type)
bdi_eoi : out std_logic; --! Last block of message (end-of-message)
bdi_nodata : out std_logic; --! Control signal indicating that there's no plain-text or authenticated data. The unit should generate a tag right away.
bdi_read : in std_logic; --! Handshake signal indicating that the data block has been read
bdi_size : out std_logic_vector(G_BS_BYTES -1 downto 0); --! Block size signal. Note: 0 = Full block.
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! PAD location
exp_tag_ready : out std_logic; --! Expected tag is ready
msg_auth_done : in std_logic; --! Message authentication completion signal
--! FIFO
bypass_fifo_full : in std_logic; --! An input signal indicating that the bypass FIFO is full
bypass_fifo_wr : out std_logic --! An output signal for writing data to bypass FIFO
);
end PreProcessor;
architecture structure of PreProcessor is
function isNPUBdisabled (a : integer ) return integer is
begin
if (a = 1 or a = 2) then
return 1;
else
return 0;
end if;
end function isNPUBdisabled;
function isKeyak (blksize: integer) return integer is
begin
if (G_DBLK_SIZE = 1344) then
return 1;
else
return 0;
end if;
end function isKeyak;
constant NPUB_DISABLE : integer := isNPUBdisabled(G_PLAINTEXT_MODE);
constant IS_KEYAK : integer := isKeyak(G_DBLK_SIZE);
signal en_data : std_logic;
signal en_npub : std_logic;
signal en_nsec : std_logic;
signal en_key : std_logic;
signal en_rdkey : std_logic;
signal sel_blank_pdi : std_logic;
signal clr_len : std_logic;
signal en_len_a_r : std_logic;
signal en_len_d_r : std_logic;
signal en_len_last_r : std_logic;
signal en_len_a : std_logic;
signal en_len_d : std_logic;
signal pad_enable : std_logic;
signal en_pad_loc : std_logic;
signal pad_eot : std_logic;
signal pad_eoi : std_logic;
signal pad_type_ad : std_logic;
signal pad_shift : std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
signal size_dword : std_logic_vector(log2_ceil(G_W/8) downto 0);
signal en_exp_tag : std_logic;
signal sel_input : std_logic_vector(2 downto 0);
signal en_last_word : std_logic;
signal key_updated_sel : std_logic;
signal key_updated_int : std_logic;
begin
uDP: entity work.PreProcessor_Datapath(dataflow)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_KEYAK => IS_KEYAK ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_PAD => G_PAD ,
G_PAD_STYLE => G_PAD_STYLE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
sdi => sdi ,
--! =================
--! Crypto Core Signals
--! =================
key_updated => key_updated_sel ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
npub => npub ,
nsec => nsec ,
len_a => len_a ,
len_d => len_d ,
exp_tag => exp_tag ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
sel_input => sel_input
);
uCtrl: entity work.PreProcessor_Control(behavior)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE ,
G_PLAINTEXT_MODE => G_PLAINTEXT_MODE ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_KEY_SIZE => G_KEY_SIZE ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_PAD => G_PAD ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D ,
G_TAG_SIZE => G_TAG_SIZE ,
G_KEYAK => IS_KEYAK
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi => sdi ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
error => open ,
--! =================
--! Crypto Core Signals
--! =================
--! control signals
key_ready => key_ready ,
key_needs_update => key_needs_update ,
key_updated => key_updated_sel ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_read => nsec_read ,
nsec_ready => nsec_ready ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_decrypt => bdi_decrypt ,
bdi_pad => bdi_pad ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_nodata => bdi_nodata ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bypass_fifo_full => bypass_fifo_full ,
bypass_fifo_wr => bypass_fifo_wr ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
key_updated_int => key_updated_int , --! Only used for Keyak
sel_input => sel_input
);
gKeyak1: if (IS_KEYAK = 1) generate
key_updated_sel <= key_updated_int;
end generate;
gKeyak0: if (IS_KEYAK = 0) generate
key_updated_sel <= key_updated;
end generate;
end structure;
|
-------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--!
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_ABLK_SIZE : integer := 128; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 1; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding style
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_CTR_AD_SIZE : integer := 16; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 16; --! Maximum size for the counter that keeps track of data
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_REVERSE_DBLK : integer := 0 --! Reverse block order (for message only)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! =================
--! Crypto Core Signals
--! =================
--! Data signals
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag data
--! Info signals
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! Control signals
key_ready : out std_logic; --! Indicates that the key is ready
key_needs_update : out std_logic; --! Indicates that the key needs update and should be acknowledge by the core via key_updated signal
key_updated : in std_logic; --! Key has been updated
rdkey_ready : out std_logic; --! (Optional) Round key ready
rdkey_read : in std_logic := '0'; --! (Optional) Round key read
npub_ready : out std_logic; --! (Optional) Npub ready
npub_read : in std_logic; --! (Optional) Npub read
nsec_ready : out std_logic; --! (Optional) Nsec ready
nsec_read : in std_logic := '0'; --! (Optional) Nsec read
bdi_ready : out std_logic; --! Block ready
bdi_proc : out std_logic; --! Block processing
bdi_ad : out std_logic; --! Input block is an authenticated data
bdi_nsec : out std_logic; --! Input block is a secret message number
bdi_decrypt : out std_logic; --! Decryption operation
bdi_pad : out std_logic; --! Last block of segment type contain padding
bdi_eot : out std_logic; --! Last block of segment type (end-of-type)
bdi_eoi : out std_logic; --! Last block of message (end-of-message)
bdi_nodata : out std_logic; --! Control signal indicating that there's no plain-text or authenticated data. The unit should generate a tag right away.
bdi_read : in std_logic; --! Handshake signal indicating that the data block has been read
bdi_size : out std_logic_vector(G_BS_BYTES -1 downto 0); --! Block size signal. Note: 0 = Full block.
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! PAD location
exp_tag_ready : out std_logic; --! Expected tag is ready
msg_auth_done : in std_logic; --! Message authentication completion signal
--! FIFO
bypass_fifo_full : in std_logic; --! An input signal indicating that the bypass FIFO is full
bypass_fifo_wr : out std_logic --! An output signal for writing data to bypass FIFO
);
end PreProcessor;
architecture structure of PreProcessor is
function isNPUBdisabled (a : integer ) return integer is
begin
if (a = 1 or a = 2) then
return 1;
else
return 0;
end if;
end function isNPUBdisabled;
function isKeyak (blksize: integer) return integer is
begin
if (G_DBLK_SIZE = 1344) then
return 1;
else
return 0;
end if;
end function isKeyak;
constant NPUB_DISABLE : integer := isNPUBdisabled(G_PLAINTEXT_MODE);
constant IS_KEYAK : integer := isKeyak(G_DBLK_SIZE);
signal en_data : std_logic;
signal en_npub : std_logic;
signal en_nsec : std_logic;
signal en_key : std_logic;
signal en_rdkey : std_logic;
signal sel_blank_pdi : std_logic;
signal clr_len : std_logic;
signal en_len_a_r : std_logic;
signal en_len_d_r : std_logic;
signal en_len_last_r : std_logic;
signal en_len_a : std_logic;
signal en_len_d : std_logic;
signal pad_enable : std_logic;
signal en_pad_loc : std_logic;
signal pad_eot : std_logic;
signal pad_eoi : std_logic;
signal pad_type_ad : std_logic;
signal pad_shift : std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
signal size_dword : std_logic_vector(log2_ceil(G_W/8) downto 0);
signal en_exp_tag : std_logic;
signal sel_input : std_logic_vector(2 downto 0);
signal en_last_word : std_logic;
signal key_updated_sel : std_logic;
signal key_updated_int : std_logic;
begin
uDP: entity work.PreProcessor_Datapath(dataflow)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_KEYAK => IS_KEYAK ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_PAD => G_PAD ,
G_PAD_STYLE => G_PAD_STYLE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
sdi => sdi ,
--! =================
--! Crypto Core Signals
--! =================
key_updated => key_updated_sel ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
npub => npub ,
nsec => nsec ,
len_a => len_a ,
len_d => len_d ,
exp_tag => exp_tag ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
sel_input => sel_input
);
uCtrl: entity work.PreProcessor_Control(behavior)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE ,
G_PLAINTEXT_MODE => G_PLAINTEXT_MODE ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_KEY_SIZE => G_KEY_SIZE ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_PAD => G_PAD ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D ,
G_TAG_SIZE => G_TAG_SIZE ,
G_KEYAK => IS_KEYAK
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi => sdi ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
error => open ,
--! =================
--! Crypto Core Signals
--! =================
--! control signals
key_ready => key_ready ,
key_needs_update => key_needs_update ,
key_updated => key_updated_sel ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_read => nsec_read ,
nsec_ready => nsec_ready ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_decrypt => bdi_decrypt ,
bdi_pad => bdi_pad ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_nodata => bdi_nodata ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bypass_fifo_full => bypass_fifo_full ,
bypass_fifo_wr => bypass_fifo_wr ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
key_updated_int => key_updated_int , --! Only used for Keyak
sel_input => sel_input
);
gKeyak1: if (IS_KEYAK = 1) generate
key_updated_sel <= key_updated_int;
end generate;
gKeyak0: if (IS_KEYAK = 0) generate
key_updated_sel <= key_updated;
end generate;
end structure;
|
-------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--!
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_ABLK_SIZE : integer := 128; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 1; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding style
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_CTR_AD_SIZE : integer := 16; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 16; --! Maximum size for the counter that keeps track of data
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_REVERSE_DBLK : integer := 0 --! Reverse block order (for message only)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! =================
--! Crypto Core Signals
--! =================
--! Data signals
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag data
--! Info signals
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! Control signals
key_ready : out std_logic; --! Indicates that the key is ready
key_needs_update : out std_logic; --! Indicates that the key needs update and should be acknowledge by the core via key_updated signal
key_updated : in std_logic; --! Key has been updated
rdkey_ready : out std_logic; --! (Optional) Round key ready
rdkey_read : in std_logic := '0'; --! (Optional) Round key read
npub_ready : out std_logic; --! (Optional) Npub ready
npub_read : in std_logic; --! (Optional) Npub read
nsec_ready : out std_logic; --! (Optional) Nsec ready
nsec_read : in std_logic := '0'; --! (Optional) Nsec read
bdi_ready : out std_logic; --! Block ready
bdi_proc : out std_logic; --! Block processing
bdi_ad : out std_logic; --! Input block is an authenticated data
bdi_nsec : out std_logic; --! Input block is a secret message number
bdi_decrypt : out std_logic; --! Decryption operation
bdi_pad : out std_logic; --! Last block of segment type contain padding
bdi_eot : out std_logic; --! Last block of segment type (end-of-type)
bdi_eoi : out std_logic; --! Last block of message (end-of-message)
bdi_nodata : out std_logic; --! Control signal indicating that there's no plain-text or authenticated data. The unit should generate a tag right away.
bdi_read : in std_logic; --! Handshake signal indicating that the data block has been read
bdi_size : out std_logic_vector(G_BS_BYTES -1 downto 0); --! Block size signal. Note: 0 = Full block.
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! PAD location
exp_tag_ready : out std_logic; --! Expected tag is ready
msg_auth_done : in std_logic; --! Message authentication completion signal
--! FIFO
bypass_fifo_full : in std_logic; --! An input signal indicating that the bypass FIFO is full
bypass_fifo_wr : out std_logic --! An output signal for writing data to bypass FIFO
);
end PreProcessor;
architecture structure of PreProcessor is
function isNPUBdisabled (a : integer ) return integer is
begin
if (a = 1 or a = 2) then
return 1;
else
return 0;
end if;
end function isNPUBdisabled;
function isKeyak (blksize: integer) return integer is
begin
if (G_DBLK_SIZE = 1344) then
return 1;
else
return 0;
end if;
end function isKeyak;
constant NPUB_DISABLE : integer := isNPUBdisabled(G_PLAINTEXT_MODE);
constant IS_KEYAK : integer := isKeyak(G_DBLK_SIZE);
signal en_data : std_logic;
signal en_npub : std_logic;
signal en_nsec : std_logic;
signal en_key : std_logic;
signal en_rdkey : std_logic;
signal sel_blank_pdi : std_logic;
signal clr_len : std_logic;
signal en_len_a_r : std_logic;
signal en_len_d_r : std_logic;
signal en_len_last_r : std_logic;
signal en_len_a : std_logic;
signal en_len_d : std_logic;
signal pad_enable : std_logic;
signal en_pad_loc : std_logic;
signal pad_eot : std_logic;
signal pad_eoi : std_logic;
signal pad_type_ad : std_logic;
signal pad_shift : std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
signal size_dword : std_logic_vector(log2_ceil(G_W/8) downto 0);
signal en_exp_tag : std_logic;
signal sel_input : std_logic_vector(2 downto 0);
signal en_last_word : std_logic;
signal key_updated_sel : std_logic;
signal key_updated_int : std_logic;
begin
uDP: entity work.PreProcessor_Datapath(dataflow)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_KEYAK => IS_KEYAK ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_PAD => G_PAD ,
G_PAD_STYLE => G_PAD_STYLE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
sdi => sdi ,
--! =================
--! Crypto Core Signals
--! =================
key_updated => key_updated_sel ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
npub => npub ,
nsec => nsec ,
len_a => len_a ,
len_d => len_d ,
exp_tag => exp_tag ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
sel_input => sel_input
);
uCtrl: entity work.PreProcessor_Control(behavior)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE ,
G_PLAINTEXT_MODE => G_PLAINTEXT_MODE ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_KEY_SIZE => G_KEY_SIZE ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_PAD => G_PAD ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D ,
G_TAG_SIZE => G_TAG_SIZE ,
G_KEYAK => IS_KEYAK
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi => sdi ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
error => open ,
--! =================
--! Crypto Core Signals
--! =================
--! control signals
key_ready => key_ready ,
key_needs_update => key_needs_update ,
key_updated => key_updated_sel ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_read => nsec_read ,
nsec_ready => nsec_ready ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_decrypt => bdi_decrypt ,
bdi_pad => bdi_pad ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_nodata => bdi_nodata ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bypass_fifo_full => bypass_fifo_full ,
bypass_fifo_wr => bypass_fifo_wr ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
key_updated_int => key_updated_int , --! Only used for Keyak
sel_input => sel_input
);
gKeyak1: if (IS_KEYAK = 1) generate
key_updated_sel <= key_updated_int;
end generate;
gKeyak0: if (IS_KEYAK = 0) generate
key_updated_sel <= key_updated;
end generate;
end structure;
|
-------------------------------------------------------------------------------
--! @file PreProcessor.vhd
--! @brief Pre-processing unit for an authenticated encryption module.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
--!
--! SIPO used within this unit follows the following convention:
--! > Order in the test vector file (left to right): A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO input (time 0 to time N-1) : A(0) A(1) A(2) … A(N-1)
--! > Order at the SIPO output (left to right) : A(0) A(1) A(2) … A(N-1)
--! where A is a single I/O word.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.AEAD_pkg.all;
entity PreProcessor is
generic (
G_W : integer := 32; --! Public data width (bits)
G_SW : integer := 32; --! Secret data width (bits)
G_NPUB_SIZE : integer := 128; --! Npub width (bits)
G_NSEC_ENABLE : integer := 0; --! Enable NSEC port
G_NSEC_SIZE : integer := 128; --! Nsec width (bits)
G_ABLK_SIZE : integer := 128; --! Authenticated Data Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data Block size (bits)
G_KEY_SIZE : integer := 128; --! Key size (bits)
G_RDKEY_ENABLE : integer := 0; --! Enable rdkey port (also disables key port)
G_RDKEY_SIZE : integer := 128; --! Roundkey size (bits)
G_TAG_SIZE : integer := 128; --! Tag size (bits)
G_BS_BYTES : integer := 4; --! The number of bits required to hold block size expressed in bytes = log2_ceil(max(G_ABLK_SIZE,G_DBLK_SIZE)/8)
G_LOADLEN_ENABLE : integer := 0; --! Enable load length section
G_PAD : integer := 1; --! Enable padding
G_PAD_STYLE : integer := 1; --! Padding style
G_PAD_AD : integer := 1; --! (G_PAD's sub option) Enable AD Padding
G_PAD_D : integer := 1; --! (G_PAD's sub option) Enable Data padding
G_CTR_AD_SIZE : integer := 16; --! Maximum size for the counter that keeps track of authenticated data
G_CTR_D_SIZE : integer := 16; --! Maximum size for the counter that keeps track of data
G_PLAINTEXT_MODE : integer := 0; --! Plaintext Mode
G_CIPHERTEXT_MODE : integer := 0; --! Ciphertext mode
G_REVERSE_DBLK : integer := 0 --! Reverse block order (for message only)
);
port (
--! =================
--! External Signals
--! =================
--! Global signals
clk : in std_logic;
rst : in std_logic;
--! Data in signals
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Key signals
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! =================
--! Crypto Core Signals
--! =================
--! Data signals
key : out std_logic_vector(G_KEY_SIZE -1 downto 0); --! Key data
rdkey : out std_logic_vector(G_RDKEY_SIZE -1 downto 0); --! Round key data
bdi : out std_logic_vector(G_DBLK_SIZE -1 downto 0); --! Block data
npub : out std_logic_vector(G_NPUB_SIZE -1 downto 0); --! Npub data
nsec : out std_logic_vector(G_NSEC_SIZE -1 downto 0); --! Nsec data
exp_tag : out std_logic_vector(G_TAG_SIZE -1 downto 0); --! Tag data
--! Info signals
len_a : out std_logic_vector(G_CTR_AD_SIZE -1 downto 0); --! Len of authenticated data in bytes (used for some algorithm)
len_d : out std_logic_vector(G_CTR_D_SIZE -1 downto 0); --! Len of data in bytes (used for some algorithm)
--! Control signals
key_ready : out std_logic; --! Indicates that the key is ready
key_needs_update : out std_logic; --! Indicates that the key needs update and should be acknowledge by the core via key_updated signal
key_updated : in std_logic; --! Key has been updated
rdkey_ready : out std_logic; --! (Optional) Round key ready
rdkey_read : in std_logic := '0'; --! (Optional) Round key read
npub_ready : out std_logic; --! (Optional) Npub ready
npub_read : in std_logic; --! (Optional) Npub read
nsec_ready : out std_logic; --! (Optional) Nsec ready
nsec_read : in std_logic := '0'; --! (Optional) Nsec read
bdi_ready : out std_logic; --! Block ready
bdi_proc : out std_logic; --! Block processing
bdi_ad : out std_logic; --! Input block is an authenticated data
bdi_nsec : out std_logic; --! Input block is a secret message number
bdi_decrypt : out std_logic; --! Decryption operation
bdi_pad : out std_logic; --! Last block of segment type contain padding
bdi_eot : out std_logic; --! Last block of segment type (end-of-type)
bdi_eoi : out std_logic; --! Last block of message (end-of-message)
bdi_nodata : out std_logic; --! Control signal indicating that there's no plain-text or authenticated data. The unit should generate a tag right away.
bdi_read : in std_logic; --! Handshake signal indicating that the data block has been read
bdi_size : out std_logic_vector(G_BS_BYTES -1 downto 0); --! Block size signal. Note: 0 = Full block.
bdi_valid_bytes : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! Valid bytes
bdi_pad_loc : out std_logic_vector(G_DBLK_SIZE/8 -1 downto 0); --! PAD location
exp_tag_ready : out std_logic; --! Expected tag is ready
msg_auth_done : in std_logic; --! Message authentication completion signal
--! FIFO
bypass_fifo_full : in std_logic; --! An input signal indicating that the bypass FIFO is full
bypass_fifo_wr : out std_logic --! An output signal for writing data to bypass FIFO
);
end PreProcessor;
architecture structure of PreProcessor is
function isNPUBdisabled (a : integer ) return integer is
begin
if (a = 1 or a = 2) then
return 1;
else
return 0;
end if;
end function isNPUBdisabled;
function isKeyak (blksize: integer) return integer is
begin
if (G_DBLK_SIZE = 1344) then
return 1;
else
return 0;
end if;
end function isKeyak;
constant NPUB_DISABLE : integer := isNPUBdisabled(G_PLAINTEXT_MODE);
constant IS_KEYAK : integer := isKeyak(G_DBLK_SIZE);
signal en_data : std_logic;
signal en_npub : std_logic;
signal en_nsec : std_logic;
signal en_key : std_logic;
signal en_rdkey : std_logic;
signal sel_blank_pdi : std_logic;
signal clr_len : std_logic;
signal en_len_a_r : std_logic;
signal en_len_d_r : std_logic;
signal en_len_last_r : std_logic;
signal en_len_a : std_logic;
signal en_len_d : std_logic;
signal pad_enable : std_logic;
signal en_pad_loc : std_logic;
signal pad_eot : std_logic;
signal pad_eoi : std_logic;
signal pad_type_ad : std_logic;
signal pad_shift : std_logic_vector(log2_ceil(G_W/8) -1 downto 0);
signal size_dword : std_logic_vector(log2_ceil(G_W/8) downto 0);
signal en_exp_tag : std_logic;
signal sel_input : std_logic_vector(2 downto 0);
signal en_last_word : std_logic;
signal key_updated_sel : std_logic;
signal key_updated_int : std_logic;
begin
uDP: entity work.PreProcessor_Datapath(dataflow)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_KEY_SIZE => G_KEY_SIZE ,
G_KEYAK => IS_KEYAK ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_PAD => G_PAD ,
G_PAD_STYLE => G_PAD_STYLE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_TAG_SIZE => G_TAG_SIZE
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
sdi => sdi ,
--! =================
--! Crypto Core Signals
--! =================
key_updated => key_updated_sel ,
key => key ,
rdkey => rdkey ,
bdi => bdi ,
npub => npub ,
nsec => nsec ,
len_a => len_a ,
len_d => len_d ,
exp_tag => exp_tag ,
bdi_valid_bytes => bdi_valid_bytes ,
bdi_pad_loc => bdi_pad_loc ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
sel_input => sel_input
);
uCtrl: entity work.PreProcessor_Control(behavior)
generic map (
G_W => G_W ,
G_SW => G_SW ,
G_CIPHERTEXT_MODE => G_CIPHERTEXT_MODE ,
G_PLAINTEXT_MODE => G_PLAINTEXT_MODE ,
G_ABLK_SIZE => G_ABLK_SIZE ,
G_DBLK_SIZE => G_DBLK_SIZE ,
G_BS_BYTES => G_BS_BYTES ,
G_KEY_SIZE => G_KEY_SIZE ,
G_NPUB_DISABLE => NPUB_DISABLE ,
G_NPUB_SIZE => G_NPUB_SIZE ,
G_NSEC_ENABLE => G_NSEC_ENABLE ,
G_NSEC_SIZE => G_NSEC_SIZE ,
G_RDKEY_ENABLE => G_RDKEY_ENABLE ,
G_RDKEY_SIZE => G_RDKEY_SIZE ,
G_REVERSE_DBLK => G_REVERSE_DBLK ,
G_LOADLEN_ENABLE => G_LOADLEN_ENABLE ,
G_CTR_AD_SIZE => G_CTR_AD_SIZE ,
G_CTR_D_SIZE => G_CTR_D_SIZE ,
G_PAD => G_PAD ,
G_PAD_AD => G_PAD_AD ,
G_PAD_D => G_PAD_D ,
G_TAG_SIZE => G_TAG_SIZE ,
G_KEYAK => IS_KEYAK
)
port map (
--! =================
--! External Signals
--! =================
--! Global signals
clk => clk ,
rst => rst ,
pdi => pdi ,
pdi_valid => pdi_valid ,
pdi_ready => pdi_ready ,
sdi => sdi ,
sdi_valid => sdi_valid ,
sdi_ready => sdi_ready ,
error => open ,
--! =================
--! Crypto Core Signals
--! =================
--! control signals
key_ready => key_ready ,
key_needs_update => key_needs_update ,
key_updated => key_updated_sel ,
rdkey_ready => rdkey_ready ,
rdkey_read => rdkey_read ,
npub_ready => npub_ready ,
npub_read => npub_read ,
nsec_read => nsec_read ,
nsec_ready => nsec_ready ,
bdi_ready => bdi_ready ,
bdi_proc => bdi_proc ,
bdi_ad => bdi_ad ,
bdi_nsec => bdi_nsec ,
bdi_decrypt => bdi_decrypt ,
bdi_pad => bdi_pad ,
bdi_eot => bdi_eot ,
bdi_eoi => bdi_eoi ,
bdi_nodata => bdi_nodata ,
bdi_read => bdi_read ,
bdi_size => bdi_size ,
bypass_fifo_full => bypass_fifo_full ,
bypass_fifo_wr => bypass_fifo_wr ,
exp_tag_ready => exp_tag_ready ,
msg_auth_done => msg_auth_done ,
--! =================
--! Internal Signals
--! =================
pad_shift => pad_shift ,
en_data => en_data ,
en_npub => en_npub ,
en_nsec => en_nsec ,
en_key => en_key ,
en_rdkey => en_rdkey ,
sel_blank_pdi => sel_blank_pdi ,
clr_len => clr_len ,
en_len_a_r => en_len_a_r ,
en_len_d_r => en_len_d_r ,
en_len_last_r => en_len_last_r ,
en_len_a => en_len_a ,
en_len_d => en_len_d ,
en_exp_tag => en_exp_tag ,
size_dword => size_dword ,
en_last_word => en_last_word ,
--! Pad related control
pad_eot => pad_eot ,
pad_eoi => pad_eoi ,
pad_type_ad => pad_type_ad ,
pad_enable => pad_enable ,
en_pad_loc => en_pad_loc ,
--! Supplmental control
key_updated_int => key_updated_int , --! Only used for Keyak
sel_input => sel_input
);
gKeyak1: if (IS_KEYAK = 1) generate
key_updated_sel <= key_updated_int;
end generate;
gKeyak0: if (IS_KEYAK = 0) generate
key_updated_sel <= key_updated;
end generate;
end structure;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library accum;
use accum.OneHotAccum.all;
entity MRAM is
port (
CLK: in std_logic;
RW: in std_logic;
ADDR: in mem_addr;
DIN: in operand;
DOUT: out operand
);
end MRAM;
architecture Beh of MRAM is
type tRAM is array (0 to 31) of operand;
signal RAM: tRAM:= (
-- | BIN | ADR BIN
"0000000000000000", -- | 00000 |
"0000000000000000", -- | 00001 |
"0000000000000000", -- | 00010 |
"0000000000000000", -- | 00011 |
"0000000000000000", -- | 00100 |
"0000000000000000", -- | 00101 |
"0000000000000000", -- | 00110 |
"0000000000000000", -- | 00111 |
"0000000000000000", -- | 01000 |
"0000000000000000", -- | 01001 |
"0000000000000000", -- | 01010 |
"0000000000000000", -- | 01011 |
"0000000000000000", -- | 01100 |
"0000000000000000", -- | 01101 |
"0000000000000000", -- | 01110 |
"0000000000000000", -- | 01111 |
"0000000000001000", -- | 10000 |
"0000000000000000", -- | 10001 |
"0000000000000000", -- | 10010 |
"0000000000000001", -- | 10011 |
"0000000000000000", -- | 10100 |
"0000000000000001", -- | 10101 |
others => "0000000000000000"
);
signal data_in: operand;
signal data_out: operand;
Begin
data_in <= Din;
WRITE: process (CLK, RW, ADDR, data_in)
begin
if (RW = '0') then
if (rising_edge(CLK)) then
RAM(conv_integer(ADDR)) <= data_in;
end if;
end if;
end process;
data_out <= RAM (conv_integer(ADDR));
RDP: process (RW, RAM, data_out)
begin
if (RW = '1') then
DOUT <= data_out;
else
DOUT <= (others => 'Z');
end if;
end process;
end Beh; |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:08:56 01/16/2014
-- Design Name:
-- Module Name: /home/tejainece/learnings/xilinx/BoothPartProdGen/BoothPartProdGen_tb.vhd
-- Project Name: BoothPartProdGen
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: BoothPartProdGen
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY BoothPartProdGen_tb IS
END BoothPartProdGen_tb;
ARCHITECTURE behavior OF BoothPartProdGen_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT BoothPartProdGen
PORT(
bin3 : IN std_logic_vector(2 downto 0);
a : IN std_logic_vector(15 downto 0);
product : OUT std_logic_vector(16 downto 0)
);
END COMPONENT;
--Inputs
signal bin3 : std_logic_vector(2 downto 0) := (others => '0');
signal a : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal product : std_logic_vector(16 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: BoothPartProdGen PORT MAP (
bin3 => bin3,
a => a,
product => product
);
stim_proc: process
begin
a <= "0000000000000101";
bin3 <= "000";
wait for 10 ns;
bin3 <= "001";
wait for 10 ns;
bin3 <= "010";
wait for 10 ns;
bin3 <= "011";
wait for 10 ns;
bin3 <= "100";
wait for 10 ns;
bin3 <= "101";
wait for 10 ns;
bin3 <= "110";
wait for 10 ns;
bin3 <= "111";
wait for 10 ns;
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2497.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p04n02i02497ent IS
END c07s03b03x00p04n02i02497ent;
ARCHITECTURE c07s03b03x00p04n02i02497arch OF c07s03b03x00p04n02i02497ent IS
BEGIN
TESTING: PROCESS
function func1 (a1 : real; b1 : integer:= 12) return integer is
begin
return 5;
end;
variable x: real := 1.2;
variable y: integer ;
BEGIN
y := func1 (y,x);
assert FALSE
report "***FAILED TEST: c07s03b03x00p04n02i02497 - The actual parameter can be specified explicitly by an association element in the association list."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p04n02i02497arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2497.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p04n02i02497ent IS
END c07s03b03x00p04n02i02497ent;
ARCHITECTURE c07s03b03x00p04n02i02497arch OF c07s03b03x00p04n02i02497ent IS
BEGIN
TESTING: PROCESS
function func1 (a1 : real; b1 : integer:= 12) return integer is
begin
return 5;
end;
variable x: real := 1.2;
variable y: integer ;
BEGIN
y := func1 (y,x);
assert FALSE
report "***FAILED TEST: c07s03b03x00p04n02i02497 - The actual parameter can be specified explicitly by an association element in the association list."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p04n02i02497arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2497.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p04n02i02497ent IS
END c07s03b03x00p04n02i02497ent;
ARCHITECTURE c07s03b03x00p04n02i02497arch OF c07s03b03x00p04n02i02497ent IS
BEGIN
TESTING: PROCESS
function func1 (a1 : real; b1 : integer:= 12) return integer is
begin
return 5;
end;
variable x: real := 1.2;
variable y: integer ;
BEGIN
y := func1 (y,x);
assert FALSE
report "***FAILED TEST: c07s03b03x00p04n02i02497 - The actual parameter can be specified explicitly by an association element in the association list."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p04n02i02497arch;
|
-------------------------------------------------------------------------------
--
-- File: ULPI.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module handles ULPI transmissions (NOPID, PID, EXTW, REGW, EXTR, REGR)
-- and reception
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ULPI is
Port (
Ulpi_Clk : in STD_LOGIC; --ULPI input clock. Generated by the USB PHY
reset : in STD_LOGIC; -- Reset siganl from upper layers. Resets all logic in this module
--ULPI Bus
u_Ulpi_Data : inout STD_LOGIC_VECTOR(7 downto 0);
u_Ulpi_Dir : in STD_LOGIC;
u_Ulpi_Nxt : in STD_LOGIC;
u_Ulpi_Stp : out STD_LOGIC;
u_Ulpi_Reset : out STD_LOGIC;
--Command signals for ULPI State machine
u_Send_NOOP_CMD : in STD_LOGIC;
u_Send_NOPID_CMD : in STD_LOGIC;
u_Send_PID_CMD : in STD_LOGIC;
u_Send_EXTW_CMD : in STD_LOGIC;
u_Send_REGW_CMD : in STD_LOGIC;
u_Send_EXTR_CMD : in STD_LOGIC;
u_Send_REGR_CMD : in STD_LOGIC;
u_Send_STP_CMD : in STD_LOGIC;
u_Send_Last : in STD_LOGIC;
u_Send_Err : in STD_LOGIC;
u_USB_Mode : in STD_LOGIC;
--Interface with upper layers
u_Tx_Data : in STD_LOGIC_VECTOR (7 downto 0); -- packet data to be transmitted
u_Tx_Data_En : out STD_LOGIC; -- data strobe; indicates to the upper layers when to place valid data on tx_data
u_Tx_Pid : in STD_LOGIC_VECTOR (3 downto 0); -- PID field associated with transmit packet (PID) commands
u_Tx_Regw_Data : in STD_LOGIC_VECTOR (7 downto 0); --Register data associated with the REGW, EXTW commands
u_Tx_Reg_Addr : in STD_LOGIC_VECTOR (7 downto 0); --Immediate address associated with the REGW, EXTW commands
u_Tx_Cmd_Done : out STD_LOGIC; --NOPID, NOOP, PID, EXTW, REGW, REGR, EXTR command completed, ready for next command
u_Tx_Pid_Phase_Done : out STD_LOGIC;
u_CRC16_En : out STD_LOGIC; --indicates to upper layers to consider the current byte as part of the sequence on which CRC16 is computed
u_Ulpi_Dir_Out : out STD_LOGIC;
u_Rx_Data : out STD_LOGIC_VECTOR (7 downto 0); --data received on the ULPI bus
u_Rx_Packet_Received : out STD_LOGIC; --indicates if u_Rx_Data is packet data
u_Rx_Cmd_Received : out STD_LOGIC; --indicates if u_Rx_Data is packet data
u_Rx_Register_Data : out STD_LOGIC_VECTOR (7 downto 0); --Data received in turn of REGR_CMD or EXTW_CMD
u_Rx_Register_Data_Received : out STD_LOGIC; -- indicates if u_Rx_Register_Data is valid
--UTMI+ signals
u_LineState : out STD_LOGIC_VECTOR (1 downto 0);
u_Vbus : out STD_LOGIC_VECTOR (1 downto 0);
u_RxEvent : out STD_LOGIC_VECTOR (1 downto 0);
u_RxActive : out STD_LOGIC;
u_ID : out STD_LOGIC;
u_Alt_Int : out STD_LOGIC;
state_ind : out STD_LOGIC_VECTOR(5 downto 0) --for debug purposes
);
end ULPI;
architecture Behavioral of ULPI is
constant TXCMD_NOOP : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant TXCMD_NOPID : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant TXCMD_PID : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant TXCMD_REGR : STD_LOGIC_VECTOR (7 downto 0) := "11101110";
constant TXCMD_REGW : STD_LOGIC_VECTOR (7 downto 0) := "10101110";
constant TXCMD_EXTR : STD_LOGIC_VECTOR (7 downto 0) := "11101111";
constant TXCMD_EXTW : STD_LOGIC_VECTOR (7 downto 0) := "10101111";
type state_type is (IDLE, SEND_STP, REGR_END, FSM_ERROR, ABORT, RECEIVE, PID_CMD, PID_DATA, PID_DATA_LAST, PID_STP, PID_DATA_ERR, PID_WAIT_J1, PID_WAIT_J2, PID_WAIT_FSEOP1, PID_WAIT_FSEOP2, PID_WAIT_HSEOP1, PID_WAIT_HSEOP2, PID_WAIT_EOP, NOPID_CMD, NOPID_DATA, NOPID_DATA_LAST, NOPID_STP, REGR_CMD1, REGR_CMD2, REGR_TURN, REGR_DATA, REGW_CMD, REGW_DATA, REGW_STP, EXTW_CMD, EXTW_ADDR, EXTW_DATA, EXTW_STP, EXTR_CMD1, EXTR_CMD2, EXTR_ADDR, EXTR_TURN, EXTR_DATA, EXTR_STP);
signal u_Ulpi_State, u_Ulpi_Next_State : state_type;
signal u_Ulpi_Dir_q : STD_LOGIC;
signal u_Ulpi_Dir_qq : STD_LOGIC;
signal u_Ulpi_Stp_Fsm : STD_LOGIC;
signal u_Txmux_Out_Data : STD_LOGIC_VECTOR (7 downto 0);
signal u_Txmux_Out_Data_q : STD_LOGIC_VECTOR (7 downto 0);
signal t_data_debug : STD_LOGIC_VECTOR (7 downto 0);
signal u_Txcmd_Code : STD_LOGIC_VECTOR (7 downto 0);
signal u_Txmux_Ctrl_8b_Commands : STD_LOGIC; --used to select TX_CMDs made up of 8 constant bits : NOPID, EXTW, EXTR on ULPI bus
signal u_Txmux_Ctrl_Extreg_Addr : STD_LOGIC; --used to select the extended register address on the ULPI bus
signal u_Txmux_Ctrl_Register_Commands : STD_LOGIC; --used to select REGW and REGR commands on the ULPI bus
signal u_Txmux_Ctrl_Data : STD_LOGIC; --used to select data bytes on ULPI bus
signal u_Txmux_Ctrl_Reg_Data : STD_LOGIC; --used to select the register data to be written on the ULPI bus
signal u_Txmux_Ctrl_PID_Command : STD_LOGIC; --used to select PID commands : 4 constant bits (0100) + 4PID bits on ULPI bus
--signal idle_state : STD_LOGIC;
signal u_Receive_Data : STD_LOGIC_VECTOR (7 downto 0);
signal u_Rx_CMD : STD_LOGIC;
signal u_Rx_CMD_Fsm : STD_LOGIC;
signal u_Reg_Data_Latch: STD_LOGIC;
signal u_Packet_Received: STD_LOGIC;
signal u_Rxdemux_Register_Data : STD_LOGIC_VECTOR (7 downto 0);
signal u_Receive_Data_q : STD_LOGIC_VECTOR (7 downto 0);
signal u_Rxdemux_LineState : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_Vbus : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_RxEvent : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_RxEvent_q : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_ID : STD_LOGIC;
signal u_Rxdemux_Alt_Int : STD_LOGIC;
signal state_ind_fsm : STD_LOGIC_VECTOR(5 downto 0);
signal debug_clk : STD_LOGIC := '0';
--attribute mark_debug : string;
--attribute keep : string;
--attribute mark_debug of state_ind : signal is "true";
--attribute keep of state_ind : signal is "true";
--attribute mark_debug of u_Ulpi_Dir : signal is "true";
--attribute keep of u_Ulpi_Dir : signal is "true";
--attribute mark_debug of u_Ulpi_Nxt : signal is "true";
--attribute keep of u_Ulpi_Nxt : signal is "true";
--attribute mark_debug of u_Ulpi_Stp : signal is "true";
--attribute keep of u_Ulpi_Stp : signal is "true";
--attribute mark_debug of u_Receive_Data_q : signal is "true";
--attribute keep of u_Receive_Data_q : signal is "true";
--attribute mark_debug of u_Txmux_Out_Data_q : signal is "true";
--attribute keep of u_Txmux_Out_Data_q : signal is "true";
--attribute mark_debug of u_Ulpi_Stp_Fsm : signal is "true";
--attribute keep of u_Ulpi_Stp_Fsm : signal is "true";
--attribute mark_debug of debug_clk : signal is "true";
--attribute keep of debug_clk : signal is "true";
begin
u_Ulpi_Reset <= reset;
u_Ulpi_Dir_Out <= u_Ulpi_Dir_q;
u_Rx_Register_Data_Received <= u_Reg_Data_Latch;
u_Rx_Data <= u_Receive_Data_q;
u_Rx_Register_Data <= u_Rxdemux_Register_Data;
--rx_en <= rx_data_en;
u_Rxdemux_LineState <= u_Receive_Data(1 downto 0);
u_Rxdemux_Vbus <= u_Receive_Data(3 downto 2);
u_Rxdemux_RxEvent <= u_Receive_Data(5 downto 4);
u_RxEvent <= u_Rxdemux_RxEvent_q;
u_Rxdemux_ID <= u_Receive_Data(6);
u_Rxdemux_Alt_Int <= u_Receive_Data(7);
bidirbuf: for i in 0 to 7 generate
IOBUF_inst : IOBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => u_Receive_Data(i), -- Buffer output
IO => u_Ulpi_Data(i), -- Buffer inout port (connect directly to top-level port)
I => u_Txmux_Out_Data_q(i), -- Buffer input
T => u_Ulpi_Dir_q -- 3-state enable input, high=input, low=output
);
end generate;
--decide if rx_data carries data/RXCMD
u_Packet_Received <= u_Ulpi_Dir and u_Ulpi_Nxt;
u_Rx_CMD <= (u_Ulpi_Dir_q and u_Ulpi_Dir) and (not u_Ulpi_Nxt);
RXACTIVE_PROC: process (Ulpi_Clk, u_Packet_Received, u_Rxdemux_RxEvent_q, u_Ulpi_Dir_q)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0' or u_Ulpi_Dir = '0') then
u_RxActive <= '0';
elsif (u_Ulpi_Dir_q = '1' and u_Packet_Received = '1') then
u_RxActive <= '1';
end if;
end if;
end process;
STATE_CHANGE: process (Ulpi_Clk) --For debug purposes
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
debug_clk <= not debug_clk;
end if;
end process;
--ULPI output signals are registered
DATA_STP_Q_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Txmux_Out_Data_q <= (others => '0');
u_Ulpi_Stp <= '0';
else
u_Ulpi_Stp <= u_Ulpi_Stp_Fsm;
u_Txmux_Out_Data_q <= u_Txmux_Out_Data;
end if;
end if;
end process;
--register receive data/control signals (outputs to upper layers)
RX_Q_PROC: process(Ulpi_Clk)
begin
if(Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Rx_Cmd_Received <= '0';
u_Ulpi_Dir_q <= '0';
u_Ulpi_Dir_qq <= '0';
u_Rx_Packet_Received <= '0';
u_Receive_Data_q <= (others => '0');
u_LineState <= (others => '0');
u_Vbus <= (others => '0');
u_Rxdemux_RxEvent_q <= (others => '0');
u_ID <= '0';
u_Alt_Int <= '0';
u_Rxdemux_Register_Data <= (others => '0');
t_data_debug <= (others => '0');
else
t_data_debug <= u_Txmux_Out_Data;
u_Rx_Cmd_Received <= u_Rx_CMD;
u_Ulpi_Dir_q <= u_Ulpi_Dir;
u_Ulpi_Dir_qq <= u_Ulpi_Dir_q;
u_Rx_Packet_Received <= u_Packet_Received;
u_Receive_Data_q <= u_Receive_Data;
if((u_Rx_CMD = '1') and (u_Rx_CMD_Fsm = '1')) then
u_LineState <= u_Rxdemux_LineState;
u_Vbus <= u_Rxdemux_Vbus;
u_Rxdemux_RxEvent_q <= u_Rxdemux_RxEvent;
u_ID <= u_Rxdemux_ID;
u_Alt_Int <= u_Rxdemux_Alt_Int;
elsif ( u_Reg_Data_Latch = '1') then
u_Rxdemux_Register_Data <= u_Receive_Data;
end if;
end if;
end if;
end process;
--Combinational process that selects the byte to be placed on the ULPI data bus
--It can be a TX Command, Packet Data, PID, Register Address, Register Data
TXMUX_PROC: process(Ulpi_Clk, u_Txmux_Ctrl_Data, u_Txmux_Ctrl_Extreg_Addr, u_Txmux_Ctrl_PID_Command, u_Txmux_Ctrl_8b_Commands, u_Txmux_Ctrl_Register_Commands, u_Tx_Data, u_Tx_Pid, u_Txcmd_Code, u_Tx_Reg_Addr, u_Txmux_Ctrl_Reg_Data, u_Tx_Regw_Data)
begin
if(u_Txmux_Ctrl_Data = '1') then
u_Txmux_Out_Data <= u_Tx_Data;
elsif (u_Txmux_Ctrl_PID_Command = '1') then
u_Txmux_Out_Data(3 downto 0) <= u_Tx_Pid;
u_Txmux_Out_Data(7 downto 4) <= TXCMD_PID;
elsif (u_Txmux_Ctrl_8b_Commands = '1') then
u_Txmux_Out_Data <= u_Txcmd_Code;
elsif (u_Txmux_Ctrl_Register_Commands = '1') then
u_Txmux_Out_Data(7 downto 6) <= u_Txcmd_Code(7 downto 6);
u_Txmux_Out_Data(5 downto 0) <= u_Tx_Reg_Addr(5 downto 0);
elsif (u_Txmux_Ctrl_Extreg_Addr = '1') then
u_Txmux_Out_Data <= u_Tx_Reg_Addr;
elsif (u_Txmux_Ctrl_Reg_Data = '1') then
u_Txmux_Out_Data <= u_Tx_Regw_Data;
else
u_Txmux_Out_Data <= (others => '0');
end if;
end process;
-- ULPI State Machine. Implements the framework required for transmit commands( NOPID,
-- PID, EXTW, REGW, EXTR, REGR) and decodes received data
SYNC_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Ulpi_State <= IDLE;
state_ind <= (others => '0');
else
u_Ulpi_State <= u_Ulpi_Next_State;
state_ind <= state_ind_fsm;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (u_Ulpi_State, u_Ulpi_Dir_q, u_Receive_Data_q ,u_Rx_CMD, u_Send_Last, u_Send_Err, u_Ulpi_Dir, u_Ulpi_Dir_qq, u_USB_Mode, u_Receive_Data, u_Ulpi_Nxt, u_Send_NOPID_CMD, u_Send_PID_CMD,u_Send_REGW_CMD,u_Send_EXTW_CMD,u_Send_REGR_CMD,u_Send_EXTR_CMD,u_Send_NOOP_CMD, u_Send_STP_CMD)
begin
--declare default state for next_state to avoid latches
u_Ulpi_Next_State <= u_Ulpi_State;
state_ind_fsm <= "000000";
u_Ulpi_Stp_Fsm <= '0';
u_Txmux_Ctrl_Data <= '0';
u_Txmux_Ctrl_Reg_Data <= '0';
u_Txmux_Ctrl_8b_Commands <= '0';
u_Txmux_Ctrl_Register_Commands <= '0';
u_Tx_Data_En <= '0';
u_Txmux_Ctrl_PID_Command <= '0';
u_Txcmd_Code <= (others => '0');
u_Rx_CMD_Fsm <= '0';
u_Tx_Cmd_Done <= '0';
u_CRC16_En <= '0';
u_Txmux_Ctrl_Extreg_Addr <= '0';
u_Reg_Data_Latch <= '0';
u_Tx_Pid_Phase_Done <= '0';
case (u_Ulpi_State) is
when IDLE =>
state_ind_fsm <= "000000";
u_Txmux_Ctrl_8b_Commands <= '1';
u_Txcmd_Code <= (others => '0');
if ( u_Ulpi_Dir = '0') then
if(u_Send_NOPID_CMD = '1') then
u_Ulpi_Next_State <= NOPID_CMD;
elsif (u_Send_PID_CMD = '1') then
u_Ulpi_Next_State <= PID_CMD;
elsif (u_Send_REGW_CMD = '1') then
u_Ulpi_Next_State <= REGW_CMD;
elsif (u_Send_EXTW_CMD = '1') then
u_Ulpi_Next_State <= EXTW_CMD;
elsif (u_Send_REGR_CMD = '1') then
u_Ulpi_Next_State <= REGR_CMD1;
elsif (u_Send_EXTR_CMD = '1') then
u_Ulpi_Next_State <= EXTR_CMD1;
elsif (u_Send_NOOP_CMD = '1') then
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= IDLE;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
--SEND PID_CMD -- No support for packet abort
when PID_CMD =>
state_ind_fsm <= "000001";
u_Txmux_Ctrl_PID_Command <= '1';
if (u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_PID_Command <= '0';
u_Txmux_Ctrl_Data <= '1';
u_Tx_Data_En <= '1';
u_CRC16_En <= '1';
if (u_Send_Last = '1') then
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= PID_STP;
else
u_Tx_Pid_Phase_Done <= '1';
u_Ulpi_Next_State <= PID_DATA;
end if;
end if;
when PID_DATA =>
state_ind_fsm <= "000010";
u_Txmux_Ctrl_Data <= '1';
if(u_Ulpi_Nxt = '1') then
u_CRC16_En <= '1';
u_Tx_Data_En <= '1';
if (u_Send_Last = '1') then
if (u_Send_Err = '0') then
u_Ulpi_Next_State <= PID_DATA_LAST;
else
u_Ulpi_Next_State <= PID_DATA_ERR;
end if;
end if;
else
u_Tx_Data_En <= '0';
end if;
when PID_DATA_LAST =>
state_ind_fsm <= "000011";
u_Txmux_Ctrl_Data <= '1';
if(u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_Data <= '0';
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= PID_STP;
end if;
when PID_STP =>
state_ind_fsm <= "000100";
u_Ulpi_Next_State <= PID_WAIT_EOP;
when PID_WAIT_EOP =>
state_ind_fsm <= "000101";
--if(ulpi_dir = '1') then
if(u_USB_Mode = '1') then
u_Ulpi_Next_State <= PID_WAIT_HSEOP1;
else
u_Ulpi_Next_State <= PID_WAIT_FSEOP1;
end if;
--end if;
when PID_WAIT_HSEOP1 =>
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= PID_WAIT_HSEOP2;
end if;
when PID_WAIT_HSEOP2 =>
state_ind_fsm <= "000110";
if(u_Ulpi_Dir = '1') then
u_Rx_CMD_Fsm <= '1';
if(u_Receive_Data(1 downto 0) = "00") then
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= PID_WAIT_HSEOP1;
end if;
end if;
when PID_WAIT_FSEOP1 =>
state_ind_fsm <= "000111";
if(u_Ulpi_Dir = '1') then
u_Rx_CMD_Fsm <= '1';
u_Ulpi_Next_State <= PID_WAIT_FSEOP2;
end if;
when PID_WAIT_FSEOP2 =>
state_ind_fsm <= "001000";
if(u_Ulpi_Dir_qq = '1') then
u_Rx_CMD_Fsm <= '1';
if(u_Receive_Data_q(1 downto 0) = "00") then
u_Ulpi_Next_State <= PID_WAIT_J1;
else
u_Ulpi_Next_State <= FSM_ERROR;
end if;
end if;
when PID_WAIT_J1 =>
state_ind_fsm <= "001001";
if (u_Ulpi_Dir = '1') then
u_Rx_CMD_Fsm <= '1';
u_Ulpi_Next_State <= PID_WAIT_J2;
end if;
when PID_WAIT_J2 =>
state_ind_fsm <= "001010";
if(u_Receive_Data_q(1 downto 0) = "01") then
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= FSM_ERROR;
end if;
when PID_DATA_ERR =>
state_ind_fsm <= "001011";
u_Tx_Cmd_Done <= '1';
u_Ulpi_Stp_Fsm <= '1';
u_Txcmd_Code <= (others => '1');
u_Txmux_Ctrl_8b_Commands <= '1';
u_Ulpi_Next_State <= IDLE; --The link must wait for an RX_CMD indicating a SE0 to J transition before transmitting another packet : Not implemented
--SEND NOPID
when NOPID_CMD =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001100";
u_Txcmd_Code <= TXCMD_NOPID;
u_Txmux_Ctrl_8b_Commands <= '1';
if (u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_8b_Commands <= '0';
u_Txmux_Ctrl_Data <= '1';
u_Ulpi_Next_State <= NOPID_DATA;
end if;
else
u_Ulpi_Next_State <= IDLE;
end if;
when NOPID_DATA =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001101";
u_Txmux_Ctrl_Data <= '1';
if (u_Ulpi_Nxt = '1') then
if (u_Send_Last = '1') then
u_Ulpi_Next_State <= NOPID_DATA_LAST;
end if;
end if;
else
u_Ulpi_Next_State <= ABORT;
end if;
when NOPID_DATA_LAST =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001110";
u_Txmux_Ctrl_Data <= '1';
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= NOPID_STP;
else
u_Ulpi_Next_State <= ABORT;
end if;
when NOPID_STP =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001111";
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= ABORT;
end if;
--SEND REGW
when REGW_CMD =>
state_ind_fsm <= "010000";
u_Txcmd_Code <= TXCMD_REGW;
u_Txmux_Ctrl_Register_Commands <= '1';
if (u_Ulpi_Dir = '0') then
if (u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_Register_Commands <= '0';
u_Txmux_Ctrl_Reg_Data <= '1';
u_Ulpi_Next_State <= REGW_DATA;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGW_DATA =>
state_ind_fsm <= "010001";
if (u_Ulpi_Dir = '0') then
if (u_Ulpi_Nxt = '1') then
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= REGW_STP;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGW_STP =>
state_ind_fsm <= "010010";
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
--SEND EXTW Not Working!
when EXTW_CMD =>
state_ind_fsm <= "010011";
u_Txcmd_Code <= TXCMD_EXTW;
u_Txmux_Ctrl_8b_Commands <= '1';
if (u_Ulpi_Dir = '0') then
if(u_Ulpi_Nxt = '1') then
u_Ulpi_Next_State <= EXTW_ADDR;
end if;
else
u_Ulpi_Next_State <= ABORT;
end if;
when EXTW_ADDR =>
state_ind_fsm <= "010100";
u_Txmux_Ctrl_Extreg_Addr <= '1';
if (u_Ulpi_Dir = '0') then
u_Ulpi_Next_State <= EXTW_DATA;
else
u_Ulpi_Next_State <= ABORT;
end if;
when EXTW_DATA =>
state_ind_fsm <= "010101";
if (u_Ulpi_Dir = '0') then
u_Txmux_Ctrl_Reg_Data <= '1';
u_Ulpi_Next_State <= EXTW_STP;
else
u_Ulpi_Next_State <= ABORT;
end if;
when EXTW_STP =>
state_ind_fsm <= "010110";
if (u_Ulpi_Dir = '0') then
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
u_Ulpi_Stp_Fsm <= '1';
else
u_Ulpi_Next_State <= ABORT;
end if;
--SEND REGR
when REGR_CMD1 =>
state_ind_fsm <= "010111";
u_Txcmd_Code <= TXCMD_REGR;
u_Txmux_Ctrl_Register_Commands <= '1';
if (u_Ulpi_Dir = '0') then
if(u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_Register_Commands <= '0';
u_Ulpi_Next_State <= REGR_TURN;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGR_TURN =>
state_ind_fsm <= "011000";
if(u_Ulpi_Dir = '1') then
if(u_Ulpi_Nxt = '0') then
u_Reg_Data_Latch <= '1';
u_Ulpi_Next_State <= REGR_DATA;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
end if;
when REGR_DATA =>
state_ind_fsm <= "011010";
if(u_Ulpi_Dir = '0') then
u_Ulpi_Next_State <= REGR_END;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGR_END =>
u_Tx_Cmd_Done <= '1';
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= RECEIVE;
else
u_Ulpi_Next_State <= IDLE;
end if;
--SEND EXTR Not Working!
when EXTR_CMD1 =>
state_ind_fsm <= "011011";
u_Txmux_Ctrl_8b_Commands <= '1';
u_Txcmd_Code <= TXCMD_EXTR;
if (u_Ulpi_Dir = '0') then
if(u_Ulpi_Nxt = '1') then
u_Ulpi_Next_State <= EXTR_ADDR;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when EXTR_ADDR =>
state_ind_fsm <= "011101";
u_Txmux_Ctrl_Extreg_Addr <= '1';
if (u_Ulpi_Dir = '0') then
u_Ulpi_Next_State <= EXTR_TURN;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when EXTR_TURN =>
state_ind_fsm <= "011110";
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= EXTR_DATA;
end if;
when EXTR_DATA =>
state_ind_fsm <= "011111";
u_Tx_Cmd_Done <= '1';
u_Reg_Data_Latch <= '1';
if (u_Ulpi_Nxt = '0') then
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= RECEIVE;
else
u_Ulpi_Next_State <= IDLE;
end if;
end if;
--ABORT
when ABORT =>
state_ind_fsm <= "100000";
u_Ulpi_Next_State <= IDLE;
when SEND_STP =>
state_ind_fsm <= "100010";
u_Ulpi_Stp_Fsm <= '1';
if (u_Ulpi_Dir_q = '0') then
u_Ulpi_Next_State <= IDLE;
end if;
--RECEIVE
when RECEIVE =>
state_ind_fsm <= "100001";
if(u_Ulpi_Dir = '1') then
if (u_Send_STP_CMD = '1') then
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= SEND_STP;
elsif(u_Rx_CMD = '1') then
u_Rx_CMD_Fsm <= '1';
end if;
else
u_Ulpi_Next_State <= IDLE;
end if;
when others =>
u_Ulpi_Next_State <= IDLE;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: ULPI.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module handles ULPI transmissions (NOPID, PID, EXTW, REGW, EXTR, REGR)
-- and reception
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ULPI is
Port (
Ulpi_Clk : in STD_LOGIC; --ULPI input clock. Generated by the USB PHY
reset : in STD_LOGIC; -- Reset siganl from upper layers. Resets all logic in this module
--ULPI Bus
u_Ulpi_Data : inout STD_LOGIC_VECTOR(7 downto 0);
u_Ulpi_Dir : in STD_LOGIC;
u_Ulpi_Nxt : in STD_LOGIC;
u_Ulpi_Stp : out STD_LOGIC;
u_Ulpi_Reset : out STD_LOGIC;
--Command signals for ULPI State machine
u_Send_NOOP_CMD : in STD_LOGIC;
u_Send_NOPID_CMD : in STD_LOGIC;
u_Send_PID_CMD : in STD_LOGIC;
u_Send_EXTW_CMD : in STD_LOGIC;
u_Send_REGW_CMD : in STD_LOGIC;
u_Send_EXTR_CMD : in STD_LOGIC;
u_Send_REGR_CMD : in STD_LOGIC;
u_Send_STP_CMD : in STD_LOGIC;
u_Send_Last : in STD_LOGIC;
u_Send_Err : in STD_LOGIC;
u_USB_Mode : in STD_LOGIC;
--Interface with upper layers
u_Tx_Data : in STD_LOGIC_VECTOR (7 downto 0); -- packet data to be transmitted
u_Tx_Data_En : out STD_LOGIC; -- data strobe; indicates to the upper layers when to place valid data on tx_data
u_Tx_Pid : in STD_LOGIC_VECTOR (3 downto 0); -- PID field associated with transmit packet (PID) commands
u_Tx_Regw_Data : in STD_LOGIC_VECTOR (7 downto 0); --Register data associated with the REGW, EXTW commands
u_Tx_Reg_Addr : in STD_LOGIC_VECTOR (7 downto 0); --Immediate address associated with the REGW, EXTW commands
u_Tx_Cmd_Done : out STD_LOGIC; --NOPID, NOOP, PID, EXTW, REGW, REGR, EXTR command completed, ready for next command
u_Tx_Pid_Phase_Done : out STD_LOGIC;
u_CRC16_En : out STD_LOGIC; --indicates to upper layers to consider the current byte as part of the sequence on which CRC16 is computed
u_Ulpi_Dir_Out : out STD_LOGIC;
u_Rx_Data : out STD_LOGIC_VECTOR (7 downto 0); --data received on the ULPI bus
u_Rx_Packet_Received : out STD_LOGIC; --indicates if u_Rx_Data is packet data
u_Rx_Cmd_Received : out STD_LOGIC; --indicates if u_Rx_Data is packet data
u_Rx_Register_Data : out STD_LOGIC_VECTOR (7 downto 0); --Data received in turn of REGR_CMD or EXTW_CMD
u_Rx_Register_Data_Received : out STD_LOGIC; -- indicates if u_Rx_Register_Data is valid
--UTMI+ signals
u_LineState : out STD_LOGIC_VECTOR (1 downto 0);
u_Vbus : out STD_LOGIC_VECTOR (1 downto 0);
u_RxEvent : out STD_LOGIC_VECTOR (1 downto 0);
u_RxActive : out STD_LOGIC;
u_ID : out STD_LOGIC;
u_Alt_Int : out STD_LOGIC;
state_ind : out STD_LOGIC_VECTOR(5 downto 0) --for debug purposes
);
end ULPI;
architecture Behavioral of ULPI is
constant TXCMD_NOOP : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant TXCMD_NOPID : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant TXCMD_PID : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant TXCMD_REGR : STD_LOGIC_VECTOR (7 downto 0) := "11101110";
constant TXCMD_REGW : STD_LOGIC_VECTOR (7 downto 0) := "10101110";
constant TXCMD_EXTR : STD_LOGIC_VECTOR (7 downto 0) := "11101111";
constant TXCMD_EXTW : STD_LOGIC_VECTOR (7 downto 0) := "10101111";
type state_type is (IDLE, SEND_STP, REGR_END, FSM_ERROR, ABORT, RECEIVE, PID_CMD, PID_DATA, PID_DATA_LAST, PID_STP, PID_DATA_ERR, PID_WAIT_J1, PID_WAIT_J2, PID_WAIT_FSEOP1, PID_WAIT_FSEOP2, PID_WAIT_HSEOP1, PID_WAIT_HSEOP2, PID_WAIT_EOP, NOPID_CMD, NOPID_DATA, NOPID_DATA_LAST, NOPID_STP, REGR_CMD1, REGR_CMD2, REGR_TURN, REGR_DATA, REGW_CMD, REGW_DATA, REGW_STP, EXTW_CMD, EXTW_ADDR, EXTW_DATA, EXTW_STP, EXTR_CMD1, EXTR_CMD2, EXTR_ADDR, EXTR_TURN, EXTR_DATA, EXTR_STP);
signal u_Ulpi_State, u_Ulpi_Next_State : state_type;
signal u_Ulpi_Dir_q : STD_LOGIC;
signal u_Ulpi_Dir_qq : STD_LOGIC;
signal u_Ulpi_Stp_Fsm : STD_LOGIC;
signal u_Txmux_Out_Data : STD_LOGIC_VECTOR (7 downto 0);
signal u_Txmux_Out_Data_q : STD_LOGIC_VECTOR (7 downto 0);
signal t_data_debug : STD_LOGIC_VECTOR (7 downto 0);
signal u_Txcmd_Code : STD_LOGIC_VECTOR (7 downto 0);
signal u_Txmux_Ctrl_8b_Commands : STD_LOGIC; --used to select TX_CMDs made up of 8 constant bits : NOPID, EXTW, EXTR on ULPI bus
signal u_Txmux_Ctrl_Extreg_Addr : STD_LOGIC; --used to select the extended register address on the ULPI bus
signal u_Txmux_Ctrl_Register_Commands : STD_LOGIC; --used to select REGW and REGR commands on the ULPI bus
signal u_Txmux_Ctrl_Data : STD_LOGIC; --used to select data bytes on ULPI bus
signal u_Txmux_Ctrl_Reg_Data : STD_LOGIC; --used to select the register data to be written on the ULPI bus
signal u_Txmux_Ctrl_PID_Command : STD_LOGIC; --used to select PID commands : 4 constant bits (0100) + 4PID bits on ULPI bus
--signal idle_state : STD_LOGIC;
signal u_Receive_Data : STD_LOGIC_VECTOR (7 downto 0);
signal u_Rx_CMD : STD_LOGIC;
signal u_Rx_CMD_Fsm : STD_LOGIC;
signal u_Reg_Data_Latch: STD_LOGIC;
signal u_Packet_Received: STD_LOGIC;
signal u_Rxdemux_Register_Data : STD_LOGIC_VECTOR (7 downto 0);
signal u_Receive_Data_q : STD_LOGIC_VECTOR (7 downto 0);
signal u_Rxdemux_LineState : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_Vbus : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_RxEvent : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_RxEvent_q : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_ID : STD_LOGIC;
signal u_Rxdemux_Alt_Int : STD_LOGIC;
signal state_ind_fsm : STD_LOGIC_VECTOR(5 downto 0);
signal debug_clk : STD_LOGIC := '0';
--attribute mark_debug : string;
--attribute keep : string;
--attribute mark_debug of state_ind : signal is "true";
--attribute keep of state_ind : signal is "true";
--attribute mark_debug of u_Ulpi_Dir : signal is "true";
--attribute keep of u_Ulpi_Dir : signal is "true";
--attribute mark_debug of u_Ulpi_Nxt : signal is "true";
--attribute keep of u_Ulpi_Nxt : signal is "true";
--attribute mark_debug of u_Ulpi_Stp : signal is "true";
--attribute keep of u_Ulpi_Stp : signal is "true";
--attribute mark_debug of u_Receive_Data_q : signal is "true";
--attribute keep of u_Receive_Data_q : signal is "true";
--attribute mark_debug of u_Txmux_Out_Data_q : signal is "true";
--attribute keep of u_Txmux_Out_Data_q : signal is "true";
--attribute mark_debug of u_Ulpi_Stp_Fsm : signal is "true";
--attribute keep of u_Ulpi_Stp_Fsm : signal is "true";
--attribute mark_debug of debug_clk : signal is "true";
--attribute keep of debug_clk : signal is "true";
begin
u_Ulpi_Reset <= reset;
u_Ulpi_Dir_Out <= u_Ulpi_Dir_q;
u_Rx_Register_Data_Received <= u_Reg_Data_Latch;
u_Rx_Data <= u_Receive_Data_q;
u_Rx_Register_Data <= u_Rxdemux_Register_Data;
--rx_en <= rx_data_en;
u_Rxdemux_LineState <= u_Receive_Data(1 downto 0);
u_Rxdemux_Vbus <= u_Receive_Data(3 downto 2);
u_Rxdemux_RxEvent <= u_Receive_Data(5 downto 4);
u_RxEvent <= u_Rxdemux_RxEvent_q;
u_Rxdemux_ID <= u_Receive_Data(6);
u_Rxdemux_Alt_Int <= u_Receive_Data(7);
bidirbuf: for i in 0 to 7 generate
IOBUF_inst : IOBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => u_Receive_Data(i), -- Buffer output
IO => u_Ulpi_Data(i), -- Buffer inout port (connect directly to top-level port)
I => u_Txmux_Out_Data_q(i), -- Buffer input
T => u_Ulpi_Dir_q -- 3-state enable input, high=input, low=output
);
end generate;
--decide if rx_data carries data/RXCMD
u_Packet_Received <= u_Ulpi_Dir and u_Ulpi_Nxt;
u_Rx_CMD <= (u_Ulpi_Dir_q and u_Ulpi_Dir) and (not u_Ulpi_Nxt);
RXACTIVE_PROC: process (Ulpi_Clk, u_Packet_Received, u_Rxdemux_RxEvent_q, u_Ulpi_Dir_q)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0' or u_Ulpi_Dir = '0') then
u_RxActive <= '0';
elsif (u_Ulpi_Dir_q = '1' and u_Packet_Received = '1') then
u_RxActive <= '1';
end if;
end if;
end process;
STATE_CHANGE: process (Ulpi_Clk) --For debug purposes
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
debug_clk <= not debug_clk;
end if;
end process;
--ULPI output signals are registered
DATA_STP_Q_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Txmux_Out_Data_q <= (others => '0');
u_Ulpi_Stp <= '0';
else
u_Ulpi_Stp <= u_Ulpi_Stp_Fsm;
u_Txmux_Out_Data_q <= u_Txmux_Out_Data;
end if;
end if;
end process;
--register receive data/control signals (outputs to upper layers)
RX_Q_PROC: process(Ulpi_Clk)
begin
if(Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Rx_Cmd_Received <= '0';
u_Ulpi_Dir_q <= '0';
u_Ulpi_Dir_qq <= '0';
u_Rx_Packet_Received <= '0';
u_Receive_Data_q <= (others => '0');
u_LineState <= (others => '0');
u_Vbus <= (others => '0');
u_Rxdemux_RxEvent_q <= (others => '0');
u_ID <= '0';
u_Alt_Int <= '0';
u_Rxdemux_Register_Data <= (others => '0');
t_data_debug <= (others => '0');
else
t_data_debug <= u_Txmux_Out_Data;
u_Rx_Cmd_Received <= u_Rx_CMD;
u_Ulpi_Dir_q <= u_Ulpi_Dir;
u_Ulpi_Dir_qq <= u_Ulpi_Dir_q;
u_Rx_Packet_Received <= u_Packet_Received;
u_Receive_Data_q <= u_Receive_Data;
if((u_Rx_CMD = '1') and (u_Rx_CMD_Fsm = '1')) then
u_LineState <= u_Rxdemux_LineState;
u_Vbus <= u_Rxdemux_Vbus;
u_Rxdemux_RxEvent_q <= u_Rxdemux_RxEvent;
u_ID <= u_Rxdemux_ID;
u_Alt_Int <= u_Rxdemux_Alt_Int;
elsif ( u_Reg_Data_Latch = '1') then
u_Rxdemux_Register_Data <= u_Receive_Data;
end if;
end if;
end if;
end process;
--Combinational process that selects the byte to be placed on the ULPI data bus
--It can be a TX Command, Packet Data, PID, Register Address, Register Data
TXMUX_PROC: process(Ulpi_Clk, u_Txmux_Ctrl_Data, u_Txmux_Ctrl_Extreg_Addr, u_Txmux_Ctrl_PID_Command, u_Txmux_Ctrl_8b_Commands, u_Txmux_Ctrl_Register_Commands, u_Tx_Data, u_Tx_Pid, u_Txcmd_Code, u_Tx_Reg_Addr, u_Txmux_Ctrl_Reg_Data, u_Tx_Regw_Data)
begin
if(u_Txmux_Ctrl_Data = '1') then
u_Txmux_Out_Data <= u_Tx_Data;
elsif (u_Txmux_Ctrl_PID_Command = '1') then
u_Txmux_Out_Data(3 downto 0) <= u_Tx_Pid;
u_Txmux_Out_Data(7 downto 4) <= TXCMD_PID;
elsif (u_Txmux_Ctrl_8b_Commands = '1') then
u_Txmux_Out_Data <= u_Txcmd_Code;
elsif (u_Txmux_Ctrl_Register_Commands = '1') then
u_Txmux_Out_Data(7 downto 6) <= u_Txcmd_Code(7 downto 6);
u_Txmux_Out_Data(5 downto 0) <= u_Tx_Reg_Addr(5 downto 0);
elsif (u_Txmux_Ctrl_Extreg_Addr = '1') then
u_Txmux_Out_Data <= u_Tx_Reg_Addr;
elsif (u_Txmux_Ctrl_Reg_Data = '1') then
u_Txmux_Out_Data <= u_Tx_Regw_Data;
else
u_Txmux_Out_Data <= (others => '0');
end if;
end process;
-- ULPI State Machine. Implements the framework required for transmit commands( NOPID,
-- PID, EXTW, REGW, EXTR, REGR) and decodes received data
SYNC_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Ulpi_State <= IDLE;
state_ind <= (others => '0');
else
u_Ulpi_State <= u_Ulpi_Next_State;
state_ind <= state_ind_fsm;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (u_Ulpi_State, u_Ulpi_Dir_q, u_Receive_Data_q ,u_Rx_CMD, u_Send_Last, u_Send_Err, u_Ulpi_Dir, u_Ulpi_Dir_qq, u_USB_Mode, u_Receive_Data, u_Ulpi_Nxt, u_Send_NOPID_CMD, u_Send_PID_CMD,u_Send_REGW_CMD,u_Send_EXTW_CMD,u_Send_REGR_CMD,u_Send_EXTR_CMD,u_Send_NOOP_CMD, u_Send_STP_CMD)
begin
--declare default state for next_state to avoid latches
u_Ulpi_Next_State <= u_Ulpi_State;
state_ind_fsm <= "000000";
u_Ulpi_Stp_Fsm <= '0';
u_Txmux_Ctrl_Data <= '0';
u_Txmux_Ctrl_Reg_Data <= '0';
u_Txmux_Ctrl_8b_Commands <= '0';
u_Txmux_Ctrl_Register_Commands <= '0';
u_Tx_Data_En <= '0';
u_Txmux_Ctrl_PID_Command <= '0';
u_Txcmd_Code <= (others => '0');
u_Rx_CMD_Fsm <= '0';
u_Tx_Cmd_Done <= '0';
u_CRC16_En <= '0';
u_Txmux_Ctrl_Extreg_Addr <= '0';
u_Reg_Data_Latch <= '0';
u_Tx_Pid_Phase_Done <= '0';
case (u_Ulpi_State) is
when IDLE =>
state_ind_fsm <= "000000";
u_Txmux_Ctrl_8b_Commands <= '1';
u_Txcmd_Code <= (others => '0');
if ( u_Ulpi_Dir = '0') then
if(u_Send_NOPID_CMD = '1') then
u_Ulpi_Next_State <= NOPID_CMD;
elsif (u_Send_PID_CMD = '1') then
u_Ulpi_Next_State <= PID_CMD;
elsif (u_Send_REGW_CMD = '1') then
u_Ulpi_Next_State <= REGW_CMD;
elsif (u_Send_EXTW_CMD = '1') then
u_Ulpi_Next_State <= EXTW_CMD;
elsif (u_Send_REGR_CMD = '1') then
u_Ulpi_Next_State <= REGR_CMD1;
elsif (u_Send_EXTR_CMD = '1') then
u_Ulpi_Next_State <= EXTR_CMD1;
elsif (u_Send_NOOP_CMD = '1') then
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= IDLE;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
--SEND PID_CMD -- No support for packet abort
when PID_CMD =>
state_ind_fsm <= "000001";
u_Txmux_Ctrl_PID_Command <= '1';
if (u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_PID_Command <= '0';
u_Txmux_Ctrl_Data <= '1';
u_Tx_Data_En <= '1';
u_CRC16_En <= '1';
if (u_Send_Last = '1') then
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= PID_STP;
else
u_Tx_Pid_Phase_Done <= '1';
u_Ulpi_Next_State <= PID_DATA;
end if;
end if;
when PID_DATA =>
state_ind_fsm <= "000010";
u_Txmux_Ctrl_Data <= '1';
if(u_Ulpi_Nxt = '1') then
u_CRC16_En <= '1';
u_Tx_Data_En <= '1';
if (u_Send_Last = '1') then
if (u_Send_Err = '0') then
u_Ulpi_Next_State <= PID_DATA_LAST;
else
u_Ulpi_Next_State <= PID_DATA_ERR;
end if;
end if;
else
u_Tx_Data_En <= '0';
end if;
when PID_DATA_LAST =>
state_ind_fsm <= "000011";
u_Txmux_Ctrl_Data <= '1';
if(u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_Data <= '0';
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= PID_STP;
end if;
when PID_STP =>
state_ind_fsm <= "000100";
u_Ulpi_Next_State <= PID_WAIT_EOP;
when PID_WAIT_EOP =>
state_ind_fsm <= "000101";
--if(ulpi_dir = '1') then
if(u_USB_Mode = '1') then
u_Ulpi_Next_State <= PID_WAIT_HSEOP1;
else
u_Ulpi_Next_State <= PID_WAIT_FSEOP1;
end if;
--end if;
when PID_WAIT_HSEOP1 =>
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= PID_WAIT_HSEOP2;
end if;
when PID_WAIT_HSEOP2 =>
state_ind_fsm <= "000110";
if(u_Ulpi_Dir = '1') then
u_Rx_CMD_Fsm <= '1';
if(u_Receive_Data(1 downto 0) = "00") then
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= PID_WAIT_HSEOP1;
end if;
end if;
when PID_WAIT_FSEOP1 =>
state_ind_fsm <= "000111";
if(u_Ulpi_Dir = '1') then
u_Rx_CMD_Fsm <= '1';
u_Ulpi_Next_State <= PID_WAIT_FSEOP2;
end if;
when PID_WAIT_FSEOP2 =>
state_ind_fsm <= "001000";
if(u_Ulpi_Dir_qq = '1') then
u_Rx_CMD_Fsm <= '1';
if(u_Receive_Data_q(1 downto 0) = "00") then
u_Ulpi_Next_State <= PID_WAIT_J1;
else
u_Ulpi_Next_State <= FSM_ERROR;
end if;
end if;
when PID_WAIT_J1 =>
state_ind_fsm <= "001001";
if (u_Ulpi_Dir = '1') then
u_Rx_CMD_Fsm <= '1';
u_Ulpi_Next_State <= PID_WAIT_J2;
end if;
when PID_WAIT_J2 =>
state_ind_fsm <= "001010";
if(u_Receive_Data_q(1 downto 0) = "01") then
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= FSM_ERROR;
end if;
when PID_DATA_ERR =>
state_ind_fsm <= "001011";
u_Tx_Cmd_Done <= '1';
u_Ulpi_Stp_Fsm <= '1';
u_Txcmd_Code <= (others => '1');
u_Txmux_Ctrl_8b_Commands <= '1';
u_Ulpi_Next_State <= IDLE; --The link must wait for an RX_CMD indicating a SE0 to J transition before transmitting another packet : Not implemented
--SEND NOPID
when NOPID_CMD =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001100";
u_Txcmd_Code <= TXCMD_NOPID;
u_Txmux_Ctrl_8b_Commands <= '1';
if (u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_8b_Commands <= '0';
u_Txmux_Ctrl_Data <= '1';
u_Ulpi_Next_State <= NOPID_DATA;
end if;
else
u_Ulpi_Next_State <= IDLE;
end if;
when NOPID_DATA =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001101";
u_Txmux_Ctrl_Data <= '1';
if (u_Ulpi_Nxt = '1') then
if (u_Send_Last = '1') then
u_Ulpi_Next_State <= NOPID_DATA_LAST;
end if;
end if;
else
u_Ulpi_Next_State <= ABORT;
end if;
when NOPID_DATA_LAST =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001110";
u_Txmux_Ctrl_Data <= '1';
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= NOPID_STP;
else
u_Ulpi_Next_State <= ABORT;
end if;
when NOPID_STP =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001111";
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= ABORT;
end if;
--SEND REGW
when REGW_CMD =>
state_ind_fsm <= "010000";
u_Txcmd_Code <= TXCMD_REGW;
u_Txmux_Ctrl_Register_Commands <= '1';
if (u_Ulpi_Dir = '0') then
if (u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_Register_Commands <= '0';
u_Txmux_Ctrl_Reg_Data <= '1';
u_Ulpi_Next_State <= REGW_DATA;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGW_DATA =>
state_ind_fsm <= "010001";
if (u_Ulpi_Dir = '0') then
if (u_Ulpi_Nxt = '1') then
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= REGW_STP;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGW_STP =>
state_ind_fsm <= "010010";
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
--SEND EXTW Not Working!
when EXTW_CMD =>
state_ind_fsm <= "010011";
u_Txcmd_Code <= TXCMD_EXTW;
u_Txmux_Ctrl_8b_Commands <= '1';
if (u_Ulpi_Dir = '0') then
if(u_Ulpi_Nxt = '1') then
u_Ulpi_Next_State <= EXTW_ADDR;
end if;
else
u_Ulpi_Next_State <= ABORT;
end if;
when EXTW_ADDR =>
state_ind_fsm <= "010100";
u_Txmux_Ctrl_Extreg_Addr <= '1';
if (u_Ulpi_Dir = '0') then
u_Ulpi_Next_State <= EXTW_DATA;
else
u_Ulpi_Next_State <= ABORT;
end if;
when EXTW_DATA =>
state_ind_fsm <= "010101";
if (u_Ulpi_Dir = '0') then
u_Txmux_Ctrl_Reg_Data <= '1';
u_Ulpi_Next_State <= EXTW_STP;
else
u_Ulpi_Next_State <= ABORT;
end if;
when EXTW_STP =>
state_ind_fsm <= "010110";
if (u_Ulpi_Dir = '0') then
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
u_Ulpi_Stp_Fsm <= '1';
else
u_Ulpi_Next_State <= ABORT;
end if;
--SEND REGR
when REGR_CMD1 =>
state_ind_fsm <= "010111";
u_Txcmd_Code <= TXCMD_REGR;
u_Txmux_Ctrl_Register_Commands <= '1';
if (u_Ulpi_Dir = '0') then
if(u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_Register_Commands <= '0';
u_Ulpi_Next_State <= REGR_TURN;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGR_TURN =>
state_ind_fsm <= "011000";
if(u_Ulpi_Dir = '1') then
if(u_Ulpi_Nxt = '0') then
u_Reg_Data_Latch <= '1';
u_Ulpi_Next_State <= REGR_DATA;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
end if;
when REGR_DATA =>
state_ind_fsm <= "011010";
if(u_Ulpi_Dir = '0') then
u_Ulpi_Next_State <= REGR_END;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGR_END =>
u_Tx_Cmd_Done <= '1';
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= RECEIVE;
else
u_Ulpi_Next_State <= IDLE;
end if;
--SEND EXTR Not Working!
when EXTR_CMD1 =>
state_ind_fsm <= "011011";
u_Txmux_Ctrl_8b_Commands <= '1';
u_Txcmd_Code <= TXCMD_EXTR;
if (u_Ulpi_Dir = '0') then
if(u_Ulpi_Nxt = '1') then
u_Ulpi_Next_State <= EXTR_ADDR;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when EXTR_ADDR =>
state_ind_fsm <= "011101";
u_Txmux_Ctrl_Extreg_Addr <= '1';
if (u_Ulpi_Dir = '0') then
u_Ulpi_Next_State <= EXTR_TURN;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when EXTR_TURN =>
state_ind_fsm <= "011110";
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= EXTR_DATA;
end if;
when EXTR_DATA =>
state_ind_fsm <= "011111";
u_Tx_Cmd_Done <= '1';
u_Reg_Data_Latch <= '1';
if (u_Ulpi_Nxt = '0') then
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= RECEIVE;
else
u_Ulpi_Next_State <= IDLE;
end if;
end if;
--ABORT
when ABORT =>
state_ind_fsm <= "100000";
u_Ulpi_Next_State <= IDLE;
when SEND_STP =>
state_ind_fsm <= "100010";
u_Ulpi_Stp_Fsm <= '1';
if (u_Ulpi_Dir_q = '0') then
u_Ulpi_Next_State <= IDLE;
end if;
--RECEIVE
when RECEIVE =>
state_ind_fsm <= "100001";
if(u_Ulpi_Dir = '1') then
if (u_Send_STP_CMD = '1') then
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= SEND_STP;
elsif(u_Rx_CMD = '1') then
u_Rx_CMD_Fsm <= '1';
end if;
else
u_Ulpi_Next_State <= IDLE;
end if;
when others =>
u_Ulpi_Next_State <= IDLE;
end case;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity psl_test_error is
end entity psl_test_error;
architecture test of psl_test_error is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 100 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING PSL_TEST_ERROR test case";
report "================================";
s_write <= '0';
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait;
end process TestP;
-- -psl statements
-- psl default clock is rising_edge(s_clk);
-- this don't work (error while analyse)
-- psl assert always (s_write -> not(s_read)) report "ERROR: s_write and s_read active @ same time!";
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity psl_test_error is
end entity psl_test_error;
architecture test of psl_test_error is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 100 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING PSL_TEST_ERROR test case";
report "================================";
s_write <= '0';
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait;
end process TestP;
-- -psl statements
-- psl default clock is rising_edge(s_clk);
-- this don't work (error while analyse)
-- psl assert always (s_write -> not(s_read)) report "ERROR: s_write and s_read active @ same time!";
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity psl_test_error is
end entity psl_test_error;
architecture test of psl_test_error is
signal s_rst_n : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
begin
s_rst_n <= '1' after 100 ns;
s_clk <= not s_clk after 10 ns;
TestP : process is
begin
report "RUNNING PSL_TEST_ERROR test case";
report "================================";
s_write <= '0';
s_read <= '0';
wait until s_rst_n = '1' and rising_edge(s_clk);
s_write <= '1'; -- cover should hit
wait until rising_edge(s_clk);
s_read <= '1'; -- assertion should hit
wait until rising_edge(s_clk);
s_write <= '0';
s_read <= '0';
wait;
end process TestP;
-- -psl statements
-- psl default clock is rising_edge(s_clk);
-- this don't work (error while analyse)
-- psl assert always (s_write -> not(s_read)) report "ERROR: s_write and s_read active @ same time!";
end architecture test;
|
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file box_counter.vhd
--! @brief counts the number of boxes grouped over the occurence number
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2013-03-10
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
--! Use numeric std
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.types.all;
use work.utils.all;
entity box_counter is
generic(
--! Number of max boxes
G_MAX_BOXES : NATURAL := C_MAX_BOXES;
G_CNT_SIZE : NATURAL := C_CNT_SIZE
);
port(
--! Clock input
clk_in : in STD_LOGIC;
--! Reset input
rst_in : in STD_LOGIC;
--! Restart comparation
restart_in : in STD_LOGIC;
--! last box input
last_box_in : in STD_LOGIC;
--! REV Box valid
box2_valid_in : in STD_LOGIC;
count_out : out unsigned(G_MAX_BOXES*G_CNT_SIZE-1 downto 0)
);
end entity box_counter;
architecture box_counter_arc of box_counter is
TYPE T_CNT is array (0 to G_MAX_BOXES - 1) of unsigned(G_CNT_SIZE-1 downto 0);
signal cnt_s : T_CNT;
signal last_cnt_s : unsigned(G_CNT_SIZE-1 downto 0);
begin
gen_output : for i in cnt_s'range generate
count_out(G_CNT_SIZE*(i+1)-1 downto G_CNT_SIZE*i) <= cnt_s(i);
end generate gen_output;
p_cnt : process (clk_in, rst_in) is
begin
if rst_in = '1' then
cnt_s <= (others => (others => '0'));
last_cnt_s <= (others => '0');
else
if rising_edge(clk_in) then
if last_box_in = '1' then
if box2_valid_in = '1' then
cnt_s(to_integer(last_cnt_s)) <= cnt_s(to_integer(last_cnt_s)) + 1;
else
cnt_s(to_integer(last_cnt_s-1)) <= cnt_s(to_integer(last_cnt_s-1)) + 1;
end if;
last_cnt_s <= (others => '0');
elsif box2_valid_in = '1' then
last_cnt_s <= last_cnt_s + 1;
end if;
end if; -- clk
end if; -- rst
end process p_cnt;
end architecture box_counter_arc;
|
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the 68000 software compatible Kernal of TG68 --
-- --
-- Copyright (c) 2007-2010 Tobias Gubener <[email protected]> --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.08 2010/06/14
-- Bugfix Movem with regmask==xFFFF
-- Add missing Illegal $4AFC
--
-- Revision 1.07 2009/10/02
-- Bugfix Movem with regmask==x0000
--
-- Revision 1.06 2009/02/10
-- Bugfix shift and rotations opcodes when the bitcount and the data are in the same register:
-- Example lsr.l D2,D2
-- Thanks to Peter Graf for report
--
-- Revision 1.05 2009/01/26
-- Implement missing RTR
-- Thanks to Peter Graf for report
--
-- Revision 1.04 2007/12/29
-- size improvement
-- change signal "microaddr" to one hot state machine
--
-- Revision 1.03 2007/12/21
-- Thanks to Andreas Ehliar
-- Split regfile to use blockram for registers
-- insert "WHEN OTHERS => null;" on END CASE;
--
-- Revision 1.02 2007/12/17
-- Bugfix jsr nn.w
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FC Output
-- add odd Address test
-- add TRACE
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TG68_fast is
port(clk : in std_logic;
reset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
test_IPL : in std_logic:='0'; --only for debugging
address : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
state_out : out std_logic_vector(1 downto 0);
LDS, UDS : out std_logic;
decodeOPC : buffer std_logic;
wr : out std_logic
);
end TG68_fast;
architecture logic of TG68_fast is
signal state : std_logic_vector(1 downto 0);
signal clkena : std_logic;
signal TG68_PC : std_logic_vector(31 downto 0);
signal TG68_PC_add : std_logic_vector(31 downto 0);
signal memaddr : std_logic_vector(31 downto 0);
signal memaddr_in : std_logic_vector(31 downto 0);
signal ea_data : std_logic_vector(31 downto 0);
signal ea_data_OP1 : std_logic;
signal setaddrlong : std_logic;
signal OP1out, OP2out : std_logic_vector(31 downto 0);
signal OP1outbrief : std_logic_vector(15 downto 0);
signal OP1in : std_logic_vector(31 downto 0);
signal data_write_tmp : std_logic_vector(31 downto 0);
signal Xtmp : std_logic_vector(31 downto 0);
signal PC_dataa, PC_datab, PC_result : std_logic_vector(31 downto 0);
signal setregstore : std_logic;
signal datatype : std_logic_vector(1 downto 0);
signal longread : std_logic;
signal longreaddirect : std_logic;
signal long_done : std_logic;
signal nextpass : std_logic;
signal setnextpass : std_logic;
signal setdispbyte : std_logic;
signal setdisp : std_logic;
signal setdispbrief : std_logic;
signal regdirectsource : std_logic;
signal endOPC : std_logic;
signal postadd : std_logic;
signal presub : std_logic;
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal addsub_q : std_logic_vector(31 downto 0);
signal briefext : std_logic_vector(31 downto 0);
signal setbriefext : std_logic;
signal addsub : std_logic;
signal c_in : std_logic_vector(3 downto 0);
signal c_out : std_logic_vector(2 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal last_data_read : std_logic_vector(15 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal registerin : std_logic_vector(31 downto 0);
signal reg_QA : std_logic_vector(31 downto 0);
signal reg_QB : std_logic_vector(31 downto 0);
signal Hwrena,Lwrena : std_logic;
signal Regwrena : std_logic;
signal rf_dest_addr : std_logic_vector(6 downto 0);
signal rf_source_addr : std_logic_vector(6 downto 0);
signal rf_dest_addr_tmp : std_logic_vector(6 downto 0);
signal rf_source_addr_tmp : std_logic_vector(6 downto 0);
signal opcode : std_logic_vector(15 downto 0);
signal laststate : std_logic_vector(1 downto 0);
signal setstate : std_logic_vector(1 downto 0);
signal mem_address : std_logic_vector(31 downto 0);
signal memaddr_a : std_logic_vector(31 downto 0);
signal mem_data_read : std_logic_vector(31 downto 0);
signal mem_data_write : std_logic_vector(31 downto 0);
signal set_mem_rega : std_logic;
signal data_read_ram : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal counter_reg : std_logic_vector(31 downto 0);
signal TG68_PC_br8 : std_logic;
signal TG68_PC_brw : std_logic;
signal TG68_PC_nop : std_logic;
signal setgetbrief : std_logic;
signal getbrief : std_logic;
signal brief : std_logic_vector(15 downto 0);
signal dest_areg : std_logic;
signal source_areg : std_logic;
signal data_is_source : std_logic;
signal set_store_in_tmp : std_logic;
signal store_in_tmp : std_logic;
signal write_back : std_logic;
signal setaddsub : std_logic;
signal setstackaddr : std_logic;
signal writePC : std_logic;
signal writePC_add : std_logic;
signal set_TG68_PC_dec: std_logic;
signal TG68_PC_dec : std_logic_vector(1 downto 0);
signal directPC : std_logic;
signal set_directPC : std_logic;
signal execOPC : std_logic;
signal fetchOPC : std_logic;
signal Flags : std_logic_vector(15 downto 0); --T.S..III ...XNZVC
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal exec_ADD : std_logic;
signal exec_OR : std_logic;
signal exec_AND : std_logic;
signal exec_EOR : std_logic;
signal exec_MOVE : std_logic;
signal exec_MOVEQ : std_logic;
signal exec_MOVESR : std_logic;
signal exec_DIRECT : std_logic;
signal exec_ADDQ : std_logic;
signal exec_CMP : std_logic;
signal exec_ROT : std_logic;
signal exec_exg : std_logic;
signal exec_swap : std_logic;
signal exec_write_back: std_logic;
signal exec_tas : std_logic;
signal exec_EXT : std_logic;
signal exec_ABCD : std_logic;
signal exec_SBCD : std_logic;
signal exec_MULU : std_logic;
signal exec_DIVU : std_logic;
signal exec_Scc : std_logic;
signal exec_CPMAW : std_logic;
signal set_exec_ADD : std_logic;
signal set_exec_OR : std_logic;
signal set_exec_AND : std_logic;
signal set_exec_EOR : std_logic;
signal set_exec_MOVE : std_logic;
signal set_exec_MOVEQ : std_logic;
signal set_exec_MOVESR: std_logic;
signal set_exec_ADDQ : std_logic;
signal set_exec_CMP : std_logic;
signal set_exec_ROT : std_logic;
signal set_exec_tas : std_logic;
signal set_exec_EXT : std_logic;
signal set_exec_ABCD : std_logic;
signal set_exec_SBCD : std_logic;
signal set_exec_MULU : std_logic;
signal set_exec_DIVU : std_logic;
signal set_exec_Scc : std_logic;
signal set_exec_CPMAW : std_logic;
signal condition : std_logic;
signal OP2out_one : std_logic;
signal OP1out_zero : std_logic;
signal ea_to_pc : std_logic;
signal ea_build : std_logic;
signal ea_only : std_logic;
signal get_ea_now : std_logic;
signal source_lowbits : std_logic;
signal dest_hbits : std_logic;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_XC : std_logic;
signal set_rot_nop : std_logic;
signal rot_nop : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal rot_bits : std_logic_vector(1 downto 0);
signal rot_cnt : std_logic_vector(5 downto 0);
signal set_rot_cnt : std_logic_vector(5 downto 0);
signal movem_busy : std_logic;
signal set_movem_busy : std_logic;
signal movem_addr : std_logic;
signal movem_regaddr : std_logic_vector(3 downto 0);
signal movem_mask : std_logic_vector(15 downto 0);
signal set_get_movem_mask : std_logic;
signal get_movem_mask : std_logic;
signal maskzero : std_logic;
signal test_maskzero : std_logic;
signal movem_muxa : std_logic_vector(7 downto 0);
signal movem_muxb : std_logic_vector(3 downto 0);
signal movem_muxc : std_logic_vector(1 downto 0);
signal movem_presub : std_logic;
signal save_memaddr : std_logic;
signal movem_bits : std_logic_vector(4 downto 0);
signal ea_calc_b : std_logic_vector(31 downto 0);
signal set_mem_addsub : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number_reg : std_logic_vector(4 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal exec_Bits : std_logic;
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal one_bit_out : std_logic;
signal set_get_bitnumber : std_logic;
signal get_bitnumber : std_logic;
signal mem_byte : std_logic;
signal wait_mem_byte : std_logic;
signal movepl : std_logic;
signal movepw : std_logic;
signal set_movepl : std_logic;
signal set_movepw : std_logic;
signal set_direct_data: std_logic;
signal use_direct_data: std_logic;
signal direct_data : std_logic;
signal set_get_extendedOPC : std_logic;
signal get_extendedOPC: std_logic;
signal setstate_delay : std_logic_vector(1 downto 0);
signal setstate_mux : std_logic_vector(1 downto 0);
signal use_XZFlag : std_logic;
signal use_XFlag : std_logic;
signal dummy_a : std_logic_vector(8 downto 0);
signal niba_l : std_logic_vector(5 downto 0);
signal niba_h : std_logic_vector(5 downto 0);
signal niba_lc : std_logic;
signal niba_hc : std_logic;
signal bcda_lc : std_logic;
signal bcda_hc : std_logic;
signal dummy_s : std_logic_vector(8 downto 0);
signal nibs_l : std_logic_vector(5 downto 0);
signal nibs_h : std_logic_vector(5 downto 0);
signal nibs_lc : std_logic;
signal nibs_hc : std_logic;
signal dummy_mulu : std_logic_vector(31 downto 0);
signal dummy_div : std_logic_vector(31 downto 0);
signal dummy_div_sub : std_logic_vector(16 downto 0);
signal dummy_div_over : std_logic_vector(16 downto 0);
signal set_V_Flag : std_logic;
signal OP1sign : std_logic;
signal set_sign : std_logic;
signal sign : std_logic;
signal sign2 : std_logic;
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(31 downto 0);
signal div_sign : std_logic;
signal div_quot : std_logic_vector(31 downto 0);
signal div_ovl : std_logic;
signal pre_V_Flag : std_logic;
signal set_vectoraddr : std_logic;
signal writeSR : std_logic;
signal trap_illegal : std_logic;
signal trap_priv : std_logic;
signal trap_1010 : std_logic;
signal trap_1111 : std_logic;
signal trap_trap : std_logic;
signal trap_trapv : std_logic;
signal trap_interrupt : std_logic;
signal trapmake : std_logic;
signal trapd : std_logic;
-- signal trap_PC : std_logic_vector(31 downto 0);
signal trap_SR : std_logic_vector(15 downto 0);
signal set_directSR : std_logic;
signal directSR : std_logic;
signal set_directCCR : std_logic;
signal directCCR : std_logic;
signal set_stop : std_logic;
signal stop : std_logic;
signal trap_vector : std_logic_vector(31 downto 0);
signal to_USP : std_logic;
signal from_USP : std_logic;
signal to_SR : std_logic;
signal from_SR : std_logic;
signal illegal_write_mode : std_logic;
signal illegal_read_mode : std_logic;
signal illegal_byteaddr : std_logic;
signal use_SP : std_logic;
signal no_Flags : std_logic;
signal IPL_nr : std_logic_vector(2 downto 0);
signal rIPL_nr : std_logic_vector(2 downto 0);
signal interrupt : std_logic;
signal SVmode : std_logic;
signal trap_chk : std_logic;
signal test_delay : std_logic_vector(2 downto 0);
signal set_PCmarker : std_logic;
signal PCmarker : std_logic;
signal set_Z_error : std_logic;
signal Z_error : std_logic;
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_dAn2, ld_AnXn1, ld_AnXn2, ld_AnXn3, st_dAn1, st_dAn2,
st_AnXn1, st_AnXn2, st_AnXn3, bra1, bra2, bsr1, bsr2, dbcc1, dbcc2,
movem, andi, op_AxAy, cmpm, link, int1, int2, int3, int4, rte, trap1, trap2, trap3,
movep1, movep2, movep3, movep4, movep5, init1, init2,
mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12, mul13, mul14, mul15,
div1, div2, div3, div4, div5, div6, div7, div8, div9, div10, div11, div12, div13, div14, div15 );
signal micro_state : micro_states;
signal next_micro_state : micro_states;
type regfile_t is array(0 to 16) of std_logic_vector(15 downto 0);
signal regfile_low : regfile_t;
signal regfile_high : regfile_t;
signal RWindex_A : integer range 0 to 16;
signal RWindex_B : integer range 0 to 16;
BEGIN
-----------------------------------------------------------------------------
-- Registerfile
-----------------------------------------------------------------------------
RWindex_A <= conv_integer(rf_dest_addr(4)&(rf_dest_addr(3 downto 0) XOR "1111"));
RWindex_B <= conv_integer(rf_source_addr(4)&(rf_source_addr(3 downto 0) XOR "1111"));
PROCESS (clk)
BEGIN
IF falling_edge(clk) THEN
IF clkena='1' THEN
reg_QA <= regfile_high(RWindex_A) & regfile_low(RWindex_A);
reg_QB <= regfile_high(RWindex_B) & regfile_low(RWindex_B);
END IF;
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF Lwrena='1' THEN
regfile_low(RWindex_A) <= registerin(15 downto 0);
END IF;
IF Hwrena='1' THEN
regfile_high(RWindex_A) <= registerin(31 downto 16);
END IF;
END IF;
END IF;
END PROCESS;
address <= TG68_PC when state="00" else X"ffffffff" when state="01" else memaddr;
LDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='1') AND state/="01" ELSE '1';
UDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='0') AND state/="01" ELSE '1';
state_out <= state;
wr <= '0' WHEN state="11" ELSE '1';
IPL_nr <= NOT IPL;
-----------------------------------------------------------------------------
-- "ALU"
-----------------------------------------------------------------------------
PROCESS (addsub_a, addsub_b, addsub, add_result, c_in)
BEGIN
IF addsub='1' THEN --ADD
add_result <= (('0'&addsub_a&c_in(0))+('0'&addsub_b&c_in(0)));
ELSE --SUB
add_result <= (('0'&addsub_a&'0')-('0'&addsub_b&c_in(0)));
END IF;
addsub_q <= add_result(32 downto 1);
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
c_in(3) <= add_result(33);
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
c_out <= c_in(3 downto 1);
END PROCESS;
-----------------------------------------------------------------------------
-- MEM_IO
-----------------------------------------------------------------------------
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, memaddr, memaddr_a, set_mem_addsub, movem_presub,
movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
data_write_tmp, addsub_q, set_vectoraddr, trap_vector, interrupt)
BEGIN
clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC;
IF rising_edge(clk) THEN
IF clkena='1' THEN
trap_vector(31 downto 8) <= (others => '0');
-- IF trap_addr_fault='1' THEN
-- trap_vector(7 downto 0) <= X"08";
-- END IF;
-- IF trap_addr_error='1' THEN
-- trap_vector(7 downto 0) <= X"0C";
-- END IF;
IF trap_illegal='1' THEN
trap_vector(7 downto 0) <= X"10";
END IF;
IF z_error='1' THEN
trap_vector(7 downto 0) <= X"14";
END IF;
-- IF trap_chk='1' THEN
-- trap_vector(7 downto 0) <= X"18";
-- END IF;
IF trap_trapv='1' THEN
trap_vector(7 downto 0) <= X"1C";
END IF;
IF trap_priv='1' THEN
trap_vector(7 downto 0) <= X"20";
END IF;
-- IF trap_trace='1' THEN
-- trap_vector(7 downto 0) <= X"24";
-- END IF;
IF trap_1010='1' THEN
trap_vector(7 downto 0) <= X"28";
END IF;
IF trap_1111='1' THEN
trap_vector(7 downto 0) <= X"2C";
END IF;
IF trap_trap='1' THEN
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
END IF;
IF interrupt='1' THEN
trap_vector(7 downto 2) <= "011"&rIPL_nr;
END IF;
END IF;
END IF;
memaddr_a(3 downto 0) <= "0000";
memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3));
memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15));
IF movem_presub='1' THEN
IF movem_busy='1' OR longread='1' THEN
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF state(1)='1' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr_a(1) <= '1';
ELSIF execOPC='1' THEN
IF datatype="10" THEN
memaddr_a(3 downto 0) <= "1100";
ELSE
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF setdisp='1' THEN
IF setdispbrief='1' THEN
memaddr_a <= briefext;
ELSIF setdispbyte='1' THEN
memaddr_a(7 downto 0) <= brief(7 downto 0);
ELSE
memaddr_a(15 downto 0) <= brief;
END IF;
END IF;
memaddr_in <= memaddr+memaddr_a;
IF longread='0' THEN
IF set_mem_addsub='1' THEN
memaddr_in <= addsub_q;
ELSIF set_vectoraddr='1' THEN
memaddr_in <= trap_vector;
ELSIF interrupt='1' THEN
memaddr_in <= "1111111111111111111111111111"&rIPL_nr&'0';
ELSIF set_mem_rega='1' THEN
memaddr_in <= reg_QA;
ELSIF setaddrlong='1' AND longread='0' THEN
memaddr_in <= data_read;
ELSIF decodeOPC='1' THEN
memaddr_in <= TG68_PC;
END IF;
END IF;
data_read(15 downto 0) <= data_in;
data_read(31 downto 16) <= (OTHERS=>data_in(15));
IF long_done='1' THEN
data_read(31 downto 16) <= last_data_read;
END IF;
IF mem_byte='1' AND memaddr(0)='0' THEN
data_read(7 downto 0) <= data_in(15 downto 8);
END IF;
IF longread='1' THEN
data_write <= data_write_tmp(31 downto 16);
ELSE
data_write(7 downto 0) <= data_write_tmp(7 downto 0);
IF mem_byte='1' THEN
data_write(15 downto 8) <= data_write_tmp(7 downto 0);
ELSE
data_write(15 downto 8) <= data_write_tmp(15 downto 8);
IF datatype="00" THEN
data_write(7 downto 0) <= data_write_tmp(15 downto 8);
END IF;
END IF;
END IF;
IF reset='0' THEN
longread <= '0';
long_done <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' THEN
last_data_read <= data_in;
long_done <= longread;
IF get_extendedOPC='0' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr <= memaddr_in;
END IF;
IF get_extendedOPC='0' THEN
IF ((setstate_mux(1)='1' AND datatype="10") OR longreaddirect='1') AND longread='0' AND interrupt='0' THEN
longread <= '1';
ELSE
longread <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- brief
-----------------------------------------------------------------------------
process (clk, brief, OP1out)
begin
IF brief(11)='1' THEN
OP1outbrief <= OP1out(31 downto 16);
ELSE
OP1outbrief <= (OTHERS=>OP1out(15));
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
briefext <= OP1outbrief&OP1out(15 downto 0);
-- CASE brief(10 downto 9) IS
-- WHEN "00" => briefext <= OP1outbrief&OP1out(15 downto 0);
-- WHEN "01" => briefext <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
-- WHEN "10" => briefext <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
-- WHEN "11" => briefext <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000";
-- END CASE;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- PC Calc + fetch opcode
-----------------------------------------------------------------------------
process (clk, reset, opcode, TG68_PC, TG68_PC_dec, TG68_PC_br8, TG68_PC_brw, PC_dataa, PC_datab, execOPC, last_data_read, get_extendedOPC,
setstate_delay, setstate)
begin
PC_dataa <= TG68_PC;
PC_datab(2 downto 0) <= "010";
PC_datab(7 downto 3) <= (others => PC_datab(2));
PC_datab(15 downto 8) <= (others => PC_datab(7));
PC_datab(31 downto 16) <= (others => PC_datab(15));
IF execOPC='0' THEN
IF TG68_PC_br8='1' THEN
PC_datab(7 downto 0) <= opcode(7 downto 0);
END IF;
IF TG68_PC_dec(1)='1' THEN
PC_datab(2) <= '1';
END IF;
IF TG68_PC_brw = '1' THEN
PC_datab(15 downto 0) <= last_data_read(15 downto 0);
END IF;
END IF;
TG68_PC_add <= PC_dataa+PC_datab;
IF get_extendedOPC='1' THEN
setstate_mux <= setstate_delay;
ELSE
setstate_mux <= setstate;
END IF;
IF reset = '0' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
TG68_PC <= (others =>'0');
state <= "01";
decodeOPC <= '0';
fetchOPC <= '0';
endOPC <= '0';
interrupt <= '0';
trap_interrupt <= '1';
execOPC <= '0';
getbrief <= '0';
TG68_PC_dec <= "00";
directPC <= '0';
directSR <= '0';
directCCR <= '0';
stop <= '0';
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_EXT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
exec_MULU <= '0';
exec_DIVU <= '0';
exec_Scc <= '0';
exec_CPMAW <= '0';
mem_byte <= '0';
rot_cnt <="000001";
rot_nop <= '0';
get_extendedOPC <= '0';
get_bitnumber <= '0';
get_movem_mask <= '0';
test_maskzero <= '0';
movepl <= '0';
movepw <= '0';
test_delay <= "000";
PCmarker <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' THEN
get_extendedOPC <= set_get_extendedOPC;
get_bitnumber <= set_get_bitnumber;
get_movem_mask <= set_get_movem_mask;
test_maskzero <= get_movem_mask;
setstate_delay <= setstate;
TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec;
IF directPC='1' AND clkena='1' THEN
TG68_PC <= data_read;
ELSIF ea_to_pc='1' AND longread='0' THEN
TG68_PC <= memaddr_in;
ELSIF (state ="00" AND TG68_PC_nop='0') OR TG68_PC_br8='1' OR TG68_PC_brw='1' OR TG68_PC_dec(1)='1' THEN
TG68_PC <= TG68_PC_add;
END IF;
IF get_bitnumber='1' THEN
bit_number_reg <= data_read(4 downto 0);
END IF;
IF clkena='1' OR get_extendedOPC='1' THEN
IF set_get_extendedOPC='1' THEN
state <= "00";
ELSIF get_extendedOPC='1' THEN
state <= setstate_mux;
ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN
state <= "01"; --decode cycle, execute cycle
ELSE
state <= setstate_mux;
END IF;
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' AND wait_mem_byte='0' THEN
mem_byte <= '1';
ELSE
mem_byte <= '0';
END IF;
END IF;
END IF;
IF clkena='1' THEN
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
fetchOPC <= '0';
exec_CPMAW <= '0';
endOPC <= '0';
interrupt <= '0';
execOPC <= '0';
exec_EXT <= '0';
exec_Scc <= '0';
rot_nop <= '0';
decodeOPC <= fetchOPC;
directPC <= set_directPC;
directSR <= set_directSR;
directCCR <= set_directCCR;
exec_MULU <= set_exec_MULU;
exec_DIVU <= set_exec_DIVU;
movepl <= '0';
movepw <= '0';
stop <= set_stop OR (stop AND NOT interrupt);
IF set_PCmarker='1' THEN
PCmarker <= '1';
ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN
PCmarker <= '0';
END IF;
IF (decodeOPC OR execOPC)='1' THEN
rot_cnt <= set_rot_cnt;
END IF;
IF next_micro_state=idle AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
nextpass <= '0';
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
endOPC <= '1';
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
interrupt <= '1';
rIPL_nr <= IPL_nr;
ELSE
IF stop='0' THEN
fetchOPC <= '1';
END IF;
END IF;
END IF;
IF exec_write_back='0' OR state/="11" THEN
IF stop='0' THEN
execOPC <= '1';
END IF;
exec_ADD <= set_exec_ADD;
exec_OR <= set_exec_OR;
exec_AND <= set_exec_AND;
exec_EOR <= set_exec_EOR;
exec_MOVE <= set_exec_MOVE;
exec_MOVEQ <= set_exec_MOVEQ;
exec_MOVESR <= set_exec_MOVESR;
exec_ADDQ <= set_exec_ADDQ;
exec_CMP <= set_exec_CMP;
exec_ROT <= set_exec_ROT;
exec_tas <= set_exec_tas;
exec_EXT <= set_exec_EXT;
exec_ABCD <= set_exec_ABCD;
exec_SBCD <= set_exec_SBCD;
exec_Scc <= set_exec_Scc;
exec_CPMAW <= set_exec_CPMAW;
rot_nop <= set_rot_nop;
END IF;
ELSE
IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
nextpass <= '1';
END IF;
END IF;
IF interrupt='1' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
-- trap_PC <= TG68_PC;
trap_interrupt <= '1';
END IF;
IF fetchOPC='1' THEN
trap_interrupt <= '0';
IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' THEN
-- IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' OR opcode(15 downto 6)="0100111011" THEN --nur für Validator
opcode <= X"60FE";
IF to_SR='0' THEN
test_delay <= "001";
END IF;
ELSE
opcode <= data_read(15 downto 0);
END IF;
getbrief <= '0';
-- trap_PC <= TG68_PC;
ELSE
test_delay <= test_delay(1 downto 0)&'0';
getbrief <= setgetbrief;
movepl <= set_movepl;
movepw <= set_movepw;
END IF;
IF decodeOPC='1' OR interrupt='1' THEN
trap_SR <= Flags;
END IF;
IF getbrief='1' THEN
brief <= data_read(15 downto 0);
END IF;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- handle EA_data, data_write_tmp
-----------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset = '0' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
direct_data <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
direct_data <= '0';
IF endOPC='1' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSE
IF set_Z_error='1' THEN
Z_error <= '1';
END IF;
exec_DIRECT <= set_exec_MOVE;
IF setstate_mux="10" AND write_back='1' THEN
exec_write_back <= '1';
END IF;
END IF;
IF set_direct_data='1' THEN
direct_data <= '1';
use_direct_data <= '1';
END IF;
IF set_exec_MOVE='1' AND state="11" THEN
use_direct_data <= '1';
END IF;
IF (exec_DIRECT='1' AND state="00" AND getbrief='0' AND endOPC='0') OR state="10" THEN
set_store_in_tmp <= '1';
ea_data <= data_read;
END IF;
IF writePC_add='1' THEN
data_write_tmp <= TG68_PC_add;
ELSIF writePC='1' OR fetchOPC='1' OR interrupt='1' OR (trap_trap='1' AND decodeOPC='1') THEN --fetchOPC für Trap
data_write_tmp <= TG68_PC;
ELSIF execOPC='1' OR (get_ea_now='1' AND ea_only='1') THEN --get_ea_now='1' AND ea_only='1' ist für pea
data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)®isterin(6 downto 0);
ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
data_write_tmp <= data_read;
IF movepl='1' THEN
data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
END IF;
ELSIF (movem_busy='1' AND datatype="10" AND movem_presub='1') OR movepl='1' THEN
data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
ELSIF (NOT trapmake AND decodeOPC)='1' OR movem_busy='1' OR movepw='1' THEN
data_write_tmp <= OP2out;
ELSIF writeSR='1'THEN
data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set dest regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trapmake, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
BEGIN
rf_dest_addr <= rf_dest_addr_tmp;
IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
rf_dest_addr(4) <= Flags(13) OR trapmake;
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_dest_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_dest_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF setbriefext='1' THEN
rf_dest_addr_tmp <= ("000"&brief(15 downto 12));
ELSIF setstackaddr='1' THEN
rf_dest_addr_tmp <= "0001111";
ELSIF dest_hbits='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(11 downto 9);
ELSE
IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(2 downto 0);
ELSE
rf_dest_addr_tmp <= "0001"&opcode(2 downto 0);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP1
-----------------------------------------------------------------------------
PROCESS (reg_QA, OP1out_zero, from_SR, Flags, ea_data_OP1, set_store_in_tmp, ea_data)
BEGIN
OP1out <= reg_QA;
IF OP1out_zero='1' THEN
OP1out <= (OTHERS => '0');
ELSIF from_SR='1' THEN
OP1out(15 downto 0) <= Flags;
ELSIF ea_data_OP1='1' AND set_store_in_tmp='1' THEN
OP1out <= ea_data;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set source regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, Flags, movem_addr, movem_presub, movem_regaddr, source_lowbits, source_areg, from_USP, rf_source_addr_tmp)
BEGIN
rf_source_addr <= rf_source_addr_tmp;
IF rf_source_addr_tmp(3 downto 0)="1111" AND from_USP='0' THEN
rf_source_addr(4) <= Flags(13);
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_source_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_source_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF from_USP='1' THEN
rf_source_addr_tmp <= "0001111";
ELSIF source_lowbits='1' THEN
rf_source_addr_tmp <= "000"&source_areg&opcode(2 downto 0);
ELSE
rf_source_addr_tmp <= "000"&source_areg&opcode(11 downto 9);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP2
-----------------------------------------------------------------------------
PROCESS (OP2out, reg_QB, opcode, datatype, OP2out_one, exec_EXT, exec_MOVEQ, EXEC_ADDQ, use_direct_data, data_write_tmp,
ea_data_OP1, set_store_in_tmp, ea_data, movepl)
BEGIN
OP2out(15 downto 0) <= reg_QB(15 downto 0);
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
IF OP2out_one='1' THEN
OP2out(15 downto 0) <= "1111111111111111";
ELSIF exec_EXT='1' THEN
IF opcode(6)='0' THEN --ext.w
OP2out(15 downto 8) <= (OTHERS => OP2out(7));
END IF;
ELSIF use_direct_data='1' THEN
OP2out <= data_write_tmp;
ELSIF ea_data_OP1='0' AND set_store_in_tmp='1' THEN
OP2out <= ea_data;
ELSIF exec_MOVEQ='1' THEN
OP2out(7 downto 0) <= opcode(7 downto 0);
OP2out(15 downto 8) <= (OTHERS => opcode(7));
ELSIF exec_ADDQ='1' THEN
OP2out(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
OP2out(3) <='1';
ELSE
OP2out(3) <='0';
END IF;
OP2out(15 downto 4) <= (OTHERS => '0');
ELSIF datatype="10" OR movepl='1' THEN
OP2out(31 downto 16) <= reg_QB(31 downto 16);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- addsub
-----------------------------------------------------------------------------
PROCESS (OP1out, OP2out, presub, postadd, execOPC, OP2out_one, datatype, use_SP, use_XZFlag, use_XFlag, Flags, setaddsub)
BEGIN
addsub_a <= OP1out;
addsub_b <= OP2out;
addsub <= NOT presub;
c_in(0) <='0';
IF execOPC='0' AND OP2out_one='0' THEN
IF datatype="00" AND use_SP='0' THEN
addsub_b <= "00000000000000000000000000000001";
ELSIF datatype="10" AND (presub OR postadd)='1' THEN
addsub_b <= "00000000000000000000000000000100";
ELSE
addsub_b <= "00000000000000000000000000000010";
END IF;
ELSE
IF (use_XZFlag='1' OR use_XFlag='1') AND Flags(4)='1' THEN
c_in(0) <= '1';
END IF;
addsub <= setaddsub;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Write Reg
-----------------------------------------------------------------------------
PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA, maskzero)
BEGIN
Lwrena <= '0';
Hwrena <= '0';
registerin <= OP1in;
IF (presub='1' OR postadd='1') AND endOPC='0' THEN -- -(An)+
Hwrena <= '1';
Lwrena <= '1';
ELSIF Regwrena='1' AND maskzero='0' THEN --read (mem)
Lwrena <= '1';
CASE datatype IS
WHEN "00" => --BYTE
registerin(15 downto 8) <= reg_QA(15 downto 8);
WHEN "01" => --WORD
IF rf_dest_addr(3)='1' OR movem_addr='1' THEN
Hwrena <='1';
END IF;
WHEN OTHERS => --LONG
Hwrena <= '1';
END CASE;
END IF;
END PROCESS;
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
PROCESS (opcode, OP1in, OP1out, OP2out, datatype, c_out, exec_ABCD, exec_SBCD, exec_CPMAW, exec_MOVESR, bits_out, Flags, flag_z, use_XZFlag, addsub_ofl,
dummy_s, dummy_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, addsub_q, movem_addr, data_read, exec_MULU, exec_DIVU, exec_OR,
exec_AND, exec_Scc, exec_EOR, exec_MOVE, exec_exg, exec_ROT, execOPC, exec_swap, exec_Bits, rot_out, dummy_mulu, dummy_div, save_memaddr, memaddr,
memaddr_in, ea_only, get_ea_now)
BEGIN
--BCD_ARITH-------------------------------------------------------------------
--ADC
dummy_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
--SBC
dummy_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
nibs_lc <= nibs_l(5);
nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
nibs_hc <= nibs_h(5);
------------------------------------------------------------------------------
flag_z <= "000";
OP1in <= addsub_q;
IF movem_addr='1' THEN
OP1in <= data_read;
ELSIF exec_ABCD='1' THEN
OP1in(7 downto 0) <= dummy_a(7 downto 0);
ELSIF exec_SBCD='1' THEN
OP1in(7 downto 0) <= dummy_s(7 downto 0);
ELSIF exec_MULU='1' THEN
OP1in <= dummy_mulu;
ELSIF exec_DIVU='1' AND execOPC='1' THEN
OP1in <= dummy_div;
ELSIF exec_OR='1' THEN
OP1in <= OP2out OR OP1out;
ELSIF exec_AND='1' OR exec_Scc='1' THEN
OP1in <= OP2out AND OP1out;
ELSIF exec_EOR='1' THEN
OP1in <= OP2out XOR OP1out;
ELSIF exec_MOVE='1' OR exec_exg='1' THEN
OP1in <= OP2out;
ELSIF exec_ROT='1' THEN
OP1in <= rot_out;
ELSIF save_memaddr='1' THEN
OP1in <= memaddr;
ELSIF get_ea_now='1' AND ea_only='1' THEN
OP1in <= memaddr_in;
ELSIF exec_swap='1' THEN
OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
ELSIF exec_bits='1' THEN
OP1in <= bits_out;
ELSIF exec_MOVESR='1' THEN
OP1in(15 downto 0) <= Flags;
END IF;
IF use_XZFlag='1' AND flags(2)='0' THEN
flag_z <= "000";
ELSIF OP1in(7 downto 0)="00000000" THEN
flag_z(0) <= '1';
IF OP1in(15 downto 8)="00000000" THEN
flag_z(1) <= '1';
IF OP1in(31 downto 16)="0000000000000000" THEN
flag_z(2) <= '1';
END IF;
END IF;
END IF;
-- --Flags NZVC
IF datatype="00" THEN --Byte
set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
IF exec_ABCD='1' THEN
set_flags(0) <= dummy_a(8);
ELSIF exec_SBCD='1' THEN
set_flags(0) <= dummy_s(8);
END IF;
ELSIF datatype="10" OR exec_CPMAW='1' THEN --Long
set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
ELSE --Word
set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
END IF;
END PROCESS;
------------------------------------------------------------------------------
--Flags
------------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset='0' THEN
Flags(13) <= '1';
SVmode <= '1';
Flags(10 downto 8) <= "111";
ELSIF rising_edge(clk) THEN
IF clkena = '1' THEN
IF directSR='1' THEN
Flags <= data_read(15 downto 0);
END IF;
IF directCCR='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
IF interrupt='1' THEN
Flags(10 downto 8) <=rIPL_nr;
SVmode <= '1';
END IF;
IF writeSR='1' OR interrupt='1' THEN
Flags(13) <='1';
END IF;
IF endOPC='1' AND to_SR='0' THEN
SVmode <= Flags(13);
END IF;
IF execOPC='1' AND to_SR='1' THEN
Flags(7 downto 0) <= OP1in(7 downto 0); --CCR
IF datatype="01" AND (opcode(14)='0' OR opcode(9)='1') THEN --move to CCR wird als word gespeichert
Flags(15 downto 8) <= OP1in(15 downto 8); --SR
SVmode <= OP1in(13);
END IF;
ELSIF Z_error='1' THEN
IF opcode(8)='0' THEN
Flags(3 downto 0) <= "1000";
ELSE
Flags(3 downto 0) <= "0100";
END IF;
ELSIF no_Flags='0' AND trapmake='0' THEN
IF exec_ADD='1' THEN
Flags(4) <= set_flags(0);
ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
Flags(4) <= rot_XC;
END IF;
IF (exec_ADD OR exec_CMP)='1' THEN
Flags(3 downto 0) <= set_flags;
ELSIF decodeOPC='1' and set_exec_ROT='1' THEN
Flags(1) <= '0';
ELSIF exec_DIVU='1' THEN
IF set_V_Flag='1' THEN
Flags(3 downto 0) <= "1010";
ELSE
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
END IF;
ELSIF exec_OR='1' OR exec_AND='1' OR exec_EOR='1' OR exec_MOVE='1' OR exec_swap='1' OR exec_MULU='1' THEN
Flags(3 downto 0) <= set_flags(3 downto 2)&"00";
ELSIF exec_ROT='1' THEN
Flags(3 downto 2) <= set_flags(3 downto 2);
Flags(0) <= rot_XC;
IF rot_bits="00" THEN --ASL/ASR
Flags(1) <= ((set_flags(3) XOR rot_rot) OR Flags(1));
END IF;
ELSIF exec_bits='1' THEN
Flags(2) <= NOT one_bit_in;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- execute opcode
-----------------------------------------------------------------------------
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt, rot_nop,
Z_error, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out, micro_state)
BEGIN
TG68_PC_br8 <= '0';
TG68_PC_brw <= '0';
TG68_PC_nop <= '0';
setstate <= "00";
Regwrena <= '0';
postadd <= '0';
presub <= '0';
movem_presub <= '0';
setaddsub <= '1';
setaddrlong <= '0';
setnextpass <= '0';
regdirectsource <= '0';
setdisp <= '0';
setdispbyte <= '0';
setdispbrief <= '0';
setbriefext <= '0';
setgetbrief <= '0';
longreaddirect <= '0';
dest_areg <= '0';
source_areg <= '0';
data_is_source <= '0';
write_back <= '0';
setstackaddr <= '0';
writePC <= '0';
writePC_add <= '0';
set_TG68_PC_dec <= '0';
set_directPC <= '0';
set_exec_ADD <= '0';
set_exec_OR <= '0';
set_exec_AND <= '0';
set_exec_EOR <= '0';
set_exec_MOVE <= '0';
set_exec_MOVEQ <= '0';
set_exec_MOVESR <= '0';
set_exec_ADDQ <= '0';
set_exec_CMP <= '0';
set_exec_ROT <= '0';
set_exec_EXT <= '0';
set_exec_CPMAW <= '0';
OP2out_one <= '0';
ea_to_pc <= '0';
ea_build <= '0';
get_ea_now <= '0';
rot_bits <= "XX";
set_rot_nop <= '0';
set_rot_cnt <= "000001";
set_movem_busy <= '0';
set_get_movem_mask <= '0';
save_memaddr <= '0';
set_mem_addsub <= '0';
exec_exg <= '0';
exec_swap <= '0';
exec_Bits <= '0';
set_get_bitnumber <= '0';
dest_hbits <= '0';
source_lowbits <= '0';
set_mem_rega <= '0';
ea_data_OP1 <= '0';
ea_only <= '0';
set_direct_data <= '0';
set_get_extendedOPC <= '0';
set_exec_tas <= '0';
OP1out_zero <= '0';
use_XZFlag <= '0';
use_XFlag <= '0';
set_exec_ABCD <= '0';
set_exec_SBCD <= '0';
set_exec_MULU <= '0';
set_exec_DIVU <= '0';
set_exec_Scc <= '0';
trap_illegal <='0';
trap_priv <='0';
trap_1010 <='0';
trap_1111 <='0';
trap_trap <='0';
trap_trapv <= '0';
trapmake <='0';
set_vectoraddr <='0';
writeSR <= '0';
set_directSR <= '0';
set_directCCR <= '0';
set_stop <= '0';
from_SR <= '0';
to_SR <= '0';
from_USP <= '0';
to_USP <= '0';
illegal_write_mode <= '0';
illegal_read_mode <= '0';
illegal_byteaddr <= '0';
no_Flags <= '0';
set_PCmarker <= '0';
use_SP <= '0';
set_Z_error <= '0';
wait_mem_byte <= '0';
set_movepl <= '0';
set_movepw <= '0';
trap_chk <= '0';
next_micro_state <= idle;
------------------------------------------------------------------------------
--Sourcepass
------------------------------------------------------------------------------
IF ea_only='0' AND get_ea_now='1' THEN
setstate <= "10";
END IF;
IF ea_build='1' THEN
CASE opcode(5 downto 3) IS --source
WHEN "010"|"011"|"100" => -- -(An)+
get_ea_now <='1';
setnextpass <= '1';
IF opcode(4)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(3)='1' THEN --(An)+
postadd <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(5)='1' THEN -- -(An)
presub <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(4 downto 3)/="10" THEN
regwrena <= '1';
END IF;
WHEN "101" => --(d16,An)
next_micro_state <= ld_dAn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "111" =>
CASE opcode(2 downto 0) IS
WHEN "000" => --(xxxx).w
next_micro_state <= ld_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= ld_nn;
WHEN "010" => --(d16,PC)
next_micro_state <= ld_dAn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "011" => --(d8,PC,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "100" => --#data
setnextpass <= '1';
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
------------------------------------------------------------------------------
--prepere opcode
------------------------------------------------------------------------------
CASE opcode(7 downto 6) IS
WHEN "00" => datatype <= "00"; --Byte
WHEN "01" => datatype <= "01"; --Word
WHEN OTHERS => datatype <= "10"; --Long
END CASE;
IF execOPC='1' AND endOPC='0' AND exec_write_back='1' THEN
setstate <="11";
END IF;
------------------------------------------------------------------------------
--test illegal mode
------------------------------------------------------------------------------
IF (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_write_mode <= '1';
END IF;
IF (opcode(5 downto 2)="1111" AND opcode(1 downto 0)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_read_mode <= '1';
END IF;
IF opcode(5 downto 3)="001" AND datatype="00" THEN
illegal_byteaddr <= '1';
END IF;
CASE opcode(15 downto 12) IS
-- 0000 ----------------------------------------------------------------------------
WHEN "0000" =>
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
datatype <= "00"; --Byte
use_SP <= '1';
no_Flags <='1';
IF opcode(7)='0' THEN
set_exec_move <= '1';
set_movepl <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7)='0' THEN
set_direct_data <= '1';
END IF;
next_micro_state <= movep1;
setgetbrief <='1';
set_mem_regA <= '1';
END IF;
IF opcode(7)='0' AND endOPC='1' THEN
IF opcode(6)='1' THEN
datatype <= "10"; --Long
ELSE
datatype <= "01"; --Word
END IF;
dest_hbits <='1';
regwrena <= '1';
END IF;
ELSE
IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits
IF execOPC='1' AND get_extendedOPC='0' THEN
IF opcode(7 downto 6)/="00" AND endOPC='1' THEN
regwrena <= '1';
END IF;
exec_Bits <= '1';
ea_data_OP1 <= '1';
END IF;
-- IF get_extendedOPC='1' THEN
-- datatype <= "01"; --Word
-- ELS
IF opcode(5 downto 4)="00" THEN
datatype <= "10"; --Long
ELSE
datatype <= "00"; --Byte
IF opcode(7 downto 6)/="00" THEN
write_back <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
IF opcode(8)='0' THEN
IF opcode(5 downto 4)/="00" THEN --Dn, An
set_get_extendedOPC <= '1';
END IF;
set_get_bitnumber <= '1';
END IF;
END IF;
ELSE --andi, ...xxxi
IF opcode(11 downto 8)="0000" THEN --ORI
set_exec_OR <= '1';
END IF;
IF opcode(11 downto 8)="0010" THEN --ANDI
set_exec_AND <= '1';
END IF;
IF opcode(11 downto 8)="0100" OR opcode(11 downto 8)="0110" THEN --SUBI, ADDI
set_exec_ADD <= '1';
END IF;
IF opcode(11 downto 8)="1010" THEN --EORI
set_exec_EOR <= '1';
END IF;
IF opcode(11 downto 8)="1100" THEN --CMPI
set_exec_CMP <= '1';
ELSIF trapmake='0' THEN
write_back <= '1';
END IF;
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR
-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR
IF SVmode='0' AND opcode(6)='1' THEN --SR
trap_priv <= '1';
trapmake <= '1';
ELSE
from_SR <= '1';
to_SR <= '1';
IF decodeOPC='1' THEN
setnextpass <= '1';
set_direct_data <= '1';
END IF;
END IF;
ELSE
IF decodeOPC='1' THEN
IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100" --ANDI, ORI, SUBI
OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN --ADDI, EORI, CMPI
-- IF (set_exec_AND OR set_exec_OR OR set_exec_ADD --ANDI, ORI, SUBI
-- OR set_exec_EOR OR set_exec_CMP)='1' THEN --ADDI, EORI, CMPI
next_micro_state <= andi;
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF opcode(11 downto 8)/="1100" THEN --CMPI
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
IF opcode(11 downto 8)="1100" OR opcode(11 downto 8)="0100" THEN --CMPI, SUBI
setaddsub <= '0';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 0001, 0010, 0011 -----------------------------------------------------------------
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
set_exec_MOVE <= '1';
IF opcode(8 downto 6)="001" THEN
no_Flags <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
CASE opcode(13 downto 12) IS
WHEN "01" => datatype <= "00"; --Byte
WHEN "10" => datatype <= "10"; --Long
WHEN OTHERS => datatype <= "01"; --Word
END CASE;
source_lowbits <= '1'; -- Dn=> An=>
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF getbrief='1' AND nextpass='1' THEN -- =>(d16,An) =>(d8,An,Xn)
set_mem_rega <= '1';
END IF;
IF execOPC='1' AND opcode(8 downto 7)="00" THEN
Regwrena <= '1';
END IF;
IF nextpass='1' OR execOPC='1' OR opcode(5 downto 4)="00" THEN
dest_hbits <= '1';
IF opcode(8 downto 6)/="000" THEN
dest_areg <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
CASE opcode(8 downto 6) IS --destination
-- WHEN "000" => --Dn
-- WHEN "001" => --An
WHEN "010"|"011"|"100" => --destination -(an)+
IF opcode(7)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(6)='1' THEN --(An)+
postadd <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(8)='1' THEN -- -(An)
presub <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(7 downto 6)/="10" THEN
regwrena <= '1';
END IF;
setstate <= "11";
next_micro_state <= nop;
WHEN "101" => --(d16,An)
next_micro_state <= st_dAn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= st_AnXn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "111" =>
CASE opcode(11 downto 9) IS
WHEN "000" => --(xxxx).w
next_micro_state <= st_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= st_nn;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
-- 0100 ----------------------------------------------------------------------------
WHEN "0100" => --rts_group
IF opcode(8)='1' THEN --lea
IF opcode(6)='1' THEN --lea
IF opcode(7)='1' THEN
ea_only <= '1';
IF opcode(5 downto 3)="010" THEN --lea (Am),An
set_exec_move <='1';
no_Flags <='1';
dest_areg <= '1';
dest_hbits <= '1';
source_lowbits <= '1';
source_areg <= '1';
IF execOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
dest_areg <= '1';
dest_hbits <= '1';
regwrena <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --chk
IF opcode(7)='1' THEN
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
datatype <= "01"; --Word
IF execOPC='1' THEN
setaddsub <= '0';
--first alternative
ea_data_OP1 <= '1';
IF c_out(1)='1' OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- trap_chk <= '1'; --first I must change the Trap System
-- trapmake <= '1';
END IF;
--second alternative
-- IF (c_out(1)='0' AND flag_z(1)='0') OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- -- trap_chk <= '1'; --first I must change the Trap System
-- -- trapmake <= '1';
-- END IF;
-- dest_hbits <= '1';
-- source_lowbits <='1';
END IF;
ELSE
trap_illegal <= '1'; -- chk long for 68020
trapmake <= '1';
END IF;
END IF;
ELSE
CASE opcode(11 downto 9) IS
WHEN "000"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move from SR
set_exec_MOVESR <= '1';
datatype <= "01";
write_back <='1'; -- im 68000 wird auch erst gelesen
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --negx
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "001"=>
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
trap_illegal <= '1';
trapmake <= '1';
ELSE --clr
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_AND <= '1';
IF execOPC='1' THEN
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "010"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move to CCR
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE --neg
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "011"=> --not, move toSR
IF opcode(7 downto 6)="11" THEN --move to SR
IF SVmode='1' THEN
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
ELSE --not
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_EOR <= '1';
IF execOPC='1' THEN
OP2out_one <= '1';
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "100"|"110"=>
IF opcode(7)='1' THEN --movem, ext
IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
source_lowbits <= '1';
IF decodeOPC='1' THEN
set_exec_EXT <= '1';
set_exec_move <= '1';
END IF;
IF opcode(6)='0' THEN
datatype <= "01"; --WORD
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE --movem
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
ea_only <= '1';
IF decodeOPC='1' THEN
datatype <= "01"; --Word
set_get_movem_mask <='1';
set_get_extendedOPC <='1';
IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
set_mem_rega <= '1';
setstate <= "01";
IF opcode(10)='0' THEN
set_movem_busy <='1';
ELSE
next_micro_state <= movem;
END IF;
ELSE
ea_build <= '1';
END IF;
ELSE
IF opcode(6)='0' THEN
datatype <= "01"; --Word
END IF;
END IF;
IF execOPC='1' THEN
IF opcode(5 downto 3)="100" OR opcode(5 downto 3)="011" THEN
regwrena <= '1';
save_memaddr <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
set_movem_busy <= '1';
IF opcode(10)='0' THEN
setstate <="01";
ELSE
setstate <="10";
END IF;
END IF;
IF opcode(5 downto 3)="100" THEN
movem_presub <= '1';
END IF;
IF movem_addr='1' THEN
IF opcode(10)='1' THEN
regwrena <= '1';
END IF;
END IF;
IF movem_busy='1' THEN
IF opcode(10)='0' THEN
setstate <="11";
ELSE
setstate <="10";
END IF;
END IF;
END IF;
ELSE
IF opcode(10)='1' THEN --MUL, DIV 68020
trap_illegal <= '1';
trapmake <= '1';
ELSE --pea, swap
IF opcode(6)='1' THEN
datatype <= "10";
IF opcode(5 downto 3)="000" THEN --swap
IF execOPC='1' THEN
exec_swap <= '1';
regwrena <= '1';
END IF;
ELSIF opcode(5 downto 3)="001" THEN --bkpt
ELSE --pea
ea_only <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF get_ea_now='1' THEN
setstate <="01";
END IF;
END IF;
ELSE --nbcd
IF decodeOPC='1' THEN --nbcd
ea_build <= '1';
END IF;
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
WHEN "101"=> --tst, tas
IF opcode(7 downto 2)="111111" THEN --4AFC illegal
trap_illegal <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
dest_hbits <= '1'; --for Flags
source_lowbits <= '1';
-- IF opcode(3)='1' THEN --MC68020...
-- source_areg <= '1';
-- END IF;
END IF;
set_exec_MOVE <= '1';
IF opcode(7 downto 6)="11" THEN --tas
set_exec_tas <= '1';
write_back <= '1';
datatype <= "00"; --Byte
IF execOPC='1' AND endOPC='1' THEN
regwrena <= '1';
END IF;
END IF;
END IF;
-- WHEN "110"=>
WHEN "111"=> --4EXX
IF opcode(7)='1' THEN --jsr, jmp
datatype <= "10";
ea_only <= '1';
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF get_ea_now='1' THEN --jsr
IF opcode(6)='0' THEN
setstate <="01";
END IF;
ea_to_pc <= '1';
IF opcode(5 downto 1)="11100" THEN
writePC_add <= '1';
ELSE
writePC <= '1';
END IF;
END IF;
ELSE --
CASE opcode(6 downto 0) IS
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
trap_trap <='1';
trapmake <= '1';
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
datatype <= "10";
IF decodeOPC='1' THEN
next_micro_state <= link;
set_exec_MOVE <= '1'; --für displacement
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
source_lowbits <= '1';
source_areg <= '1';
END IF;
IF execOPC='1' THEN
setstackaddr <='1';
regwrena <= '1';
END IF;
WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" => --unlink
datatype <= "10";
IF decodeOPC='1' THEN
setstate <= "10";
set_mem_rega <= '1';
ELSIF execOPC='1' THEN
regwrena <= '1';
exec_exg <= '1';
ELSE
setstackaddr <='1';
regwrena <= '1';
get_ea_now <= '1';
ea_only <= '1';
END IF;
WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" => --move An,USP
IF SVmode='1' THEN
no_Flags <= '1';
to_USP <= '1';
setstackaddr <= '1';
source_lowbits <= '1';
source_areg <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
IF SVmode='1' THEN
no_Flags <= '1';
from_USP <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110000" => --reset
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110001" => --nop
WHEN "1110010" => --stop
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
setnextpass <= '1';
set_directSR <= '1';
set_stop <= '1';
END IF;
END IF;
WHEN "1110011" => --rte
IF SVmode='1' THEN
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directSR <= '1';
next_micro_state <= rte;
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110101" => --rts
IF decodeOPC='1' THEN
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
END IF;
WHEN "1110110" => --trapv
IF Flags(1)='1' THEN
trap_trapv <= '1';
trapmake <= '1';
END IF;
WHEN "1110111" => --rtr
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directCCR <= '1';
next_micro_state <= rte;
END IF;
WHEN OTHERS =>
trap_illegal <= '1';
trapmake <= '1';
END CASE;
END IF;
WHEN OTHERS => null;
END CASE;
END IF;
-- 0101 ----------------------------------------------------------------------------
WHEN "0101" => --subq, addq
IF opcode(7 downto 6)="11" THEN --dbcc
IF opcode(5 downto 3)="001" THEN --dbcc
datatype <= "01"; --Word
IF decodeOPC='1' THEN
next_micro_state <= nop;
OP2out_one <= '1';
IF condition='0' THEN
Regwrena <= '1';
IF c_in(2)='1' THEN
next_micro_state <= dbcc1;
END IF;
END IF;
data_is_source <= '1';
END IF;
ELSE --Scc
datatype <= "00"; --Byte
write_back <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF condition='0' THEN
set_exec_Scc <= '1';
END IF;
IF execOPC='1' THEN
IF condition='1' THEN
OP2out_one <= '1';
exec_EXG <= '1';
ELSE
OP1out_zero <= '1';
END IF;
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
ELSE --addq, subq
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(5 downto 3)="001" THEN
no_Flags <= '1';
END IF;
write_back <= '1';
set_exec_ADDQ <= '1';
set_exec_ADD <= '1';
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 0110 ----------------------------------------------------------------------------
WHEN "0110" => --bra,bsr,bcc
datatype <= "10";
IF micro_state=idle THEN
IF opcode(11 downto 8)="0001" THEN --bsr
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bsr1;
ELSE
next_micro_state <= bsr2;
setstate <= "01";
END IF;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
ELSE --bra
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bra1;
END IF;
IF condition='1' THEN
TG68_PC_br8 <= '1';
END IF;
END IF;
END IF;
-- 0111 ----------------------------------------------------------------------------
WHEN "0111" => --moveq
IF opcode(8)='0' THEN
IF trap_interrupt='0' THEN
datatype <= "10"; --Long
Regwrena <= '1';
set_exec_MOVEQ <= '1';
set_exec_MOVE <= '1';
dest_hbits <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
-- 1000 ----------------------------------------------------------------------------
WHEN "1000" => --or
IF opcode(7 downto 6)="11" THEN --divu, divs
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
IF opcode(7 downto 6)="00" THEN --sbcd
use_XZFlag <= '1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --pack, unpack
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --or
set_exec_OR <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1001, 1101 -----------------------------------------------------------------------
WHEN "1001"|"1101" => --sub, add
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --adda.w, suba.w
datatype <= "01"; --Word
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(14)='0' THEN
setaddsub <= '0';
END IF;
END IF;
IF opcode(8)='1' AND opcode(5 downto 4)="00" AND opcode(7 downto 6)/="11" THEN --addx, subx
use_XZFlag <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN
write_back <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(7 downto 6)="11" THEN --adda, suba
no_Flags <= '1';
dest_areg <='1';
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
ELSE
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 1010 ----------------------------------------------------------------------------
WHEN "1010" => --Trap 1010
trap_1010 <= '1';
trapmake <= '1';
-- 1011 ----------------------------------------------------------------------------
WHEN "1011" => --eor, cmp
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --cmpa.w
datatype <= "01"; --Word
set_exec_CPMAW <= '1';
END IF;
IF opcode(8)='1' AND opcode(5 downto 3)="001" AND opcode(7 downto 6)/="11" THEN --cmpm
set_exec_CMP <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_rega <= '1';
postadd <= '1';
next_micro_state <= cmpm;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
setaddsub <= '0';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
set_exec_EOR <= '1';
write_back <= '1';
ELSE --cmp
set_exec_CMP <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE --cmp
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --cmpa
dest_areg <='1';
END IF;
dest_hbits <= '1';
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 1100 ----------------------------------------------------------------------------
WHEN "1100" => --and, exg
IF opcode(7 downto 6)="11" THEN --mulu, muls
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
IF opcode(7 downto 6)="00" THEN --abcd
use_XZFlag <= '1';
-- datatype <= "00"; --ist schon default
set_exec_ADD <= '1';
set_exec_ABCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --exg
datatype <= "10";
regwrena <= '1';
IF opcode(6)='1' AND opcode(3)='1' THEN
dest_areg <= '1';
source_areg <= '1';
END IF;
IF decodeOPC='1' THEN
set_mem_rega <= '1';
exec_exg <= '1';
ELSE
save_memaddr <= '1';
dest_hbits <= '1';
END IF;
END IF;
ELSE --and
set_exec_AND <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1110 ----------------------------------------------------------------------------
WHEN "1110" => --rotation
set_exec_ROT <= '1';
IF opcode(7 downto 6)="11" THEN
datatype <= "01";
rot_bits <= opcode(10 downto 9);
ea_data_OP1 <= '1';
write_back <= '1';
ELSE
rot_bits <= opcode(4 downto 3);
data_is_source <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7 downto 6)="11" THEN
ea_build <= '1';
ELSE
IF opcode(5)='1' THEN
IF OP2out(5 downto 0)/="000000" THEN
set_rot_cnt <= OP2out(5 downto 0);
ELSE
set_rot_nop <= '1';
END IF;
ELSE
set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
set_rot_cnt(3) <='1';
ELSE
set_rot_cnt(3) <='0';
END IF;
END IF;
END IF;
END IF;
IF opcode(7 downto 6)/="11" THEN
IF execOPC='1' AND rot_nop='0' THEN
Regwrena <= '1';
set_rot_cnt <= rot_cnt-1;
END IF;
END IF;
-- ----------------------------------------------------------------------------
WHEN OTHERS =>
trap_1111 <= '1';
trapmake <= '1';
END CASE;
-- END PROCESS;
-----------------------------------------------------------------------------
-- execute microcode
-----------------------------------------------------------------------------
--PROCESS (micro_state)
-- BEGIN
IF Z_error='1' THEN -- divu by zero
trapmake <= '1'; --wichtig für USP
IF trapd='0' THEN
writePC <= '1';
END IF;
END IF;
IF trapmake='1' AND trapd='0' THEN
next_micro_state <= trap1;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
END IF;
IF interrupt='1' THEN
next_micro_state <= int1;
setstate <= "10";
-- datatype <= "01"; --wirkt sich auf Flags aus
END IF;
IF reset='0' THEN
micro_state <= init1;
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
trapd <= trapmake;
IF fetchOPC='1' THEN
micro_state <= idle;
ELSE
micro_state <= next_micro_state;
END IF;
END IF;
END IF;
CASE micro_state IS
WHEN ld_nn => -- (nnnn).w/l=>
get_ea_now <='1';
setnextpass <= '1';
setaddrlong <= '1';
WHEN st_nn => -- =>(nnnn).w/l
setstate <= "11";
setaddrlong <= '1';
next_micro_state <= nop;
WHEN ld_dAn1 => -- d(An)=>, --d(PC)=>
setstate <= "01";
next_micro_state <= ld_dAn2;
WHEN ld_dAn2 => -- d(An)=>, --d(PC)=>
get_ea_now <='1';
setdisp <= '1'; --word
setnextpass <= '1';
WHEN ld_AnXn1 => -- d(An,Xn)=>, --d(PC,Xn)=>
setstate <= "01";
next_micro_state <= ld_AnXn2;
WHEN ld_AnXn2 => -- d(An,Xn)=>, --d(PC,Xn)=>
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= ld_AnXn3;
WHEN ld_AnXn3 =>
get_ea_now <='1';
setdisp <= '1'; --brief
setdispbrief <= '1';
setnextpass <= '1';
WHEN st_dAn1 => -- =>d(An)
setstate <= "01";
next_micro_state <= st_dAn2;
WHEN st_dAn2 => -- =>d(An)
setstate <= "11";
setdisp <= '1'; --word
next_micro_state <= nop;
WHEN st_AnXn1 => -- =>d(An,Xn)
setstate <= "01";
next_micro_state <= st_AnXn2;
WHEN st_AnXn2 => -- =>d(An,Xn)
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= st_AnXn3;
WHEN st_AnXn3 =>
setstate <= "11";
setdisp <= '1'; --brief
setdispbrief <= '1';
next_micro_state <= nop;
WHEN bra1 => --bra
IF condition='1' THEN
TG68_PC_br8 <= '1'; --pc+0000
setstate <= "01";
next_micro_state <= bra2;
END IF;
WHEN bra2 => --bra
TG68_PC_brw <= '1';
WHEN bsr1 => --bsr
set_TG68_PC_dec <= '1'; --in 2 Takten -2
setstate <= "01";
next_micro_state <= bsr2;
WHEN bsr2 => --bsr
IF TG68_PC_dec(0)='1' THEN
TG68_PC_brw <= '1';
ELSE
TG68_PC_br8 <= '1';
END IF;
writePC <= '1';
setstate <= "11";
next_micro_state <= nop;
WHEN dbcc1 => --dbcc
TG68_PC_nop <= '1';
setstate <= "01";
next_micro_state <= dbcc2;
WHEN dbcc2 => --dbcc
TG68_PC_brw <= '1';
WHEN movem => --movem
set_movem_busy <='1';
setstate <= "10";
WHEN andi => --andi
IF opcode(5 downto 4)/="00" THEN
ea_build <= '1';
setnextpass <= '1';
END IF;
WHEN op_AxAy => -- op -(Ax),-(Ay)
presub <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_addsub <= '1';
setstate <= "10";
WHEN cmpm => -- cmpm (Ay)+,(Ax)+
postadd <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_rega <= '1';
setstate <= "10";
WHEN link => -- link
setstate <="11";
save_memaddr <= '1';
regwrena <= '1';
WHEN int1 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
next_micro_state <= int2;
WHEN int2 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= int3;
WHEN int3 => -- interrupt
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
setstate <= "10";
next_micro_state <= int4;
WHEN int4 => -- interrupt
datatype <= "10";
WHEN rte => -- RTE
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
WHEN trap1 => -- TRAP
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= trap2;
WHEN trap2 => -- TRAP
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
-- longreaddirect <= '1';
setstate <= "10";
next_micro_state <= trap3;
WHEN trap3 => -- TRAP
datatype <= "10";
WHEN movep1 => -- MOVEP d(An)
setstate <= "01";
IF opcode(6)='1' THEN
set_movepl <= '1';
END IF;
next_micro_state <= movep2;
WHEN movep2 =>
setdisp <= '1';
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
wait_mem_byte <= '1';
END IF;
next_micro_state <= movep3;
WHEN movep3 =>
IF opcode(6)='1' THEN
set_movepw <= '1';
next_micro_state <= movep4;
END IF;
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN movep4 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
wait_mem_byte <= '1';
setstate <= "11";
END IF;
next_micro_state <= movep5;
WHEN movep5 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN init1 => -- init SP
longreaddirect <= '1';
next_micro_state <= init2;
WHEN init2 => -- init PC
get_ea_now <='1'; --\
ea_only <= '1'; --- OP1in <= memaddr_in
setaddrlong <= '1'; -- memaddr_in <= data_read
regwrena <= '1';
setstackaddr <='1'; -- dest_addr <= SP
set_directPC <= '1';
longreaddirect <= '1';
next_micro_state <= nop;
WHEN mul1 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul2;
WHEN mul2 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul3;
WHEN mul3 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul4;
WHEN mul4 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul5;
WHEN mul5 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul6;
WHEN mul6 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul7;
WHEN mul7 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul8;
WHEN mul8 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul9;
WHEN mul9 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul10;
WHEN mul10 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul11;
WHEN mul11 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul12;
WHEN mul12 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul13;
WHEN mul13 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul14;
WHEN mul14 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul15;
WHEN mul15 => -- mulu
set_exec_MULU <= '1';
WHEN div1 => -- divu
IF OP2out(15 downto 0)=x"0000" THEN --div zero
set_Z_error <= '1';
ELSE
set_exec_DIVU <= '1';
next_micro_state <= div2;
END IF;
setstate <="01";
WHEN div2 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div3;
WHEN div3 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div4;
WHEN div4 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div5;
WHEN div5 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div6;
WHEN div6 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div7;
WHEN div7 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div8;
WHEN div8 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div9;
WHEN div9 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div10;
WHEN div10 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div11;
WHEN div11 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div12;
WHEN div12 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div13;
WHEN div13 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div14;
WHEN div14 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div15;
WHEN div15 => -- divu
set_exec_DIVU <= '1';
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Conditions
-----------------------------------------------------------------------------
PROCESS (opcode, Flags)
BEGIN
CASE opcode(11 downto 8) IS
WHEN X"0" => condition <= '1';
WHEN X"1" => condition <= '0';
WHEN X"2" => condition <= NOT Flags(0) AND NOT Flags(2);
WHEN X"3" => condition <= Flags(0) OR Flags(2);
WHEN X"4" => condition <= NOT Flags(0);
WHEN X"5" => condition <= Flags(0);
WHEN X"6" => condition <= NOT Flags(2);
WHEN X"7" => condition <= Flags(2);
WHEN X"8" => condition <= NOT Flags(1);
WHEN X"9" => condition <= Flags(1);
WHEN X"a" => condition <= NOT Flags(3);
WHEN X"b" => condition <= Flags(3);
WHEN X"c" => condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1));
WHEN X"d" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1));
WHEN X"e" => condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2));
WHEN X"f" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2);
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Bits
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, OP2out, one_bit_in, one_bit_out, bit_Number, bit_number_reg)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --btst
one_bit_out <= one_bit_in;
WHEN "01" => --bchg
one_bit_out <= NOT one_bit_in;
WHEN "10" => --bclr
one_bit_out <= '0';
WHEN "11" => --bset
one_bit_out <= '1';
WHEN OTHERS => null;
END CASE;
IF opcode(8)='0' THEN
IF opcode(5 downto 4)="00" THEN
bit_number <= bit_number_reg(4 downto 0);
ELSE
bit_number <= "00"&bit_number_reg(2 downto 0);
END IF;
ELSE
IF opcode(5 downto 4)="00" THEN
bit_number <= OP2out(4 downto 0);
ELSE
bit_number <= "00"&OP2out(2 downto 0);
END IF;
END IF;
bits_out <= OP1out;
CASE bit_Number IS
WHEN "00000" => one_bit_in <= OP1out(0);
bits_out(0) <= one_bit_out;
WHEN "00001" => one_bit_in <= OP1out(1);
bits_out(1) <= one_bit_out;
WHEN "00010" => one_bit_in <= OP1out(2);
bits_out(2) <= one_bit_out;
WHEN "00011" => one_bit_in <= OP1out(3);
bits_out(3) <= one_bit_out;
WHEN "00100" => one_bit_in <= OP1out(4);
bits_out(4) <= one_bit_out;
WHEN "00101" => one_bit_in <= OP1out(5);
bits_out(5) <= one_bit_out;
WHEN "00110" => one_bit_in <= OP1out(6);
bits_out(6) <= one_bit_out;
WHEN "00111" => one_bit_in <= OP1out(7);
bits_out(7) <= one_bit_out;
WHEN "01000" => one_bit_in <= OP1out(8);
bits_out(8) <= one_bit_out;
WHEN "01001" => one_bit_in <= OP1out(9);
bits_out(9) <= one_bit_out;
WHEN "01010" => one_bit_in <= OP1out(10);
bits_out(10) <= one_bit_out;
WHEN "01011" => one_bit_in <= OP1out(11);
bits_out(11) <= one_bit_out;
WHEN "01100" => one_bit_in <= OP1out(12);
bits_out(12) <= one_bit_out;
WHEN "01101" => one_bit_in <= OP1out(13);
bits_out(13) <= one_bit_out;
WHEN "01110" => one_bit_in <= OP1out(14);
bits_out(14) <= one_bit_out;
WHEN "01111" => one_bit_in <= OP1out(15);
bits_out(15) <= one_bit_out;
WHEN "10000" => one_bit_in <= OP1out(16);
bits_out(16) <= one_bit_out;
WHEN "10001" => one_bit_in <= OP1out(17);
bits_out(17) <= one_bit_out;
WHEN "10010" => one_bit_in <= OP1out(18);
bits_out(18) <= one_bit_out;
WHEN "10011" => one_bit_in <= OP1out(19);
bits_out(19) <= one_bit_out;
WHEN "10100" => one_bit_in <= OP1out(20);
bits_out(20) <= one_bit_out;
WHEN "10101" => one_bit_in <= OP1out(21);
bits_out(21) <= one_bit_out;
WHEN "10110" => one_bit_in <= OP1out(22);
bits_out(22) <= one_bit_out;
WHEN "10111" => one_bit_in <= OP1out(23);
bits_out(23) <= one_bit_out;
WHEN "11000" => one_bit_in <= OP1out(24);
bits_out(24) <= one_bit_out;
WHEN "11001" => one_bit_in <= OP1out(25);
bits_out(25) <= one_bit_out;
WHEN "11010" => one_bit_in <= OP1out(26);
bits_out(26) <= one_bit_out;
WHEN "11011" => one_bit_in <= OP1out(27);
bits_out(27) <= one_bit_out;
WHEN "11100" => one_bit_in <= OP1out(28);
bits_out(28) <= one_bit_out;
WHEN "11101" => one_bit_in <= OP1out(29);
bits_out(29) <= one_bit_out;
WHEN "11110" => one_bit_in <= OP1out(30);
bits_out(30) <= one_bit_out;
WHEN "11111" => one_bit_in <= OP1out(31);
bits_out(31) <= one_bit_out;
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Rotation
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, rot_nop)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_rot <= OP1out(7);
WHEN "01"|"11" => --Word
rot_rot <= OP1out(15);
WHEN "10" => --Long
rot_rot <= OP1out(31);
WHEN OTHERS => null;
END CASE;
CASE rot_bits IS
WHEN "00" => --ASL, ASR
rot_lsb <= '0';
rot_msb <= rot_rot;
WHEN "01" => --LSL, LSR
rot_lsb <= '0';
rot_msb <= '0';
WHEN "10" => --ROXL, ROXR
rot_lsb <= Flags(4);
rot_msb <= Flags(4);
WHEN "11" => --ROL, ROR
rot_lsb <= rot_rot;
rot_msb <= OP1out(0);
WHEN OTHERS => null;
END CASE;
IF rot_nop='1' THEN
rot_out <= OP1out;
rot_XC <= Flags(0);
ELSE
IF opcode(8)='1' THEN --left
rot_out <= OP1out(30 downto 0)&rot_lsb;
rot_XC <= rot_rot;
ELSE --right
rot_XC <= OP1out(0);
rot_out <= rot_msb&OP1out(31 downto 1);
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_out(7) <= rot_msb;
WHEN "01"|"11" => --Word
rot_out(15) <= rot_msb;
WHEN OTHERS =>
END CASE;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- MULU/MULS
-----------------------------------------------------------------------------
PROCESS (clk, opcode, OP2out, muls_msb, mulu_reg, OP1sign, sign2)
BEGIN
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(15)='1' THEN --MULS Neg faktor
OP1sign <= '1';
mulu_reg <= "0000000000000000"&(0-reg_QB(15 downto 0));
ELSE
OP1sign <= '0';
mulu_reg <= "0000000000000000"®_QB(15 downto 0);
END IF;
ELSIF exec_MULU='1' THEN
mulu_reg <= dummy_mulu;
END IF;
END IF;
END IF;
IF (opcode(8)='1' AND OP2out(15)='1') OR OP1sign='1' THEN
muls_msb <= mulu_reg(31);
ELSE
muls_msb <= '0';
END IF;
IF opcode(8)='1' AND OP2out(15)='1' THEN
sign2 <= '1';
ELSE
sign2 <= '0';
END IF;
IF mulu_reg(0)='1' THEN
IF OP1sign='1' THEN
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))-(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
ELSE
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))+(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
END IF;
ELSE
dummy_mulu <= muls_msb&mulu_reg(31 downto 1);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- DIVU
-----------------------------------------------------------------------------
PROCESS (clk, execOPC, opcode, OP1out, OP2out, div_reg, dummy_div_sub, div_quot, div_sign, dummy_div_over, dummy_div)
BEGIN
set_V_Flag <= '0';
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(31)='1' THEN -- Neg divisor
div_sign <= '1';
div_reg <= 0-reg_QB;
ELSE
div_sign <= '0';
div_reg <= reg_QB;
END IF;
ELSIF exec_DIVU='1' THEN
div_reg <= div_quot;
END IF;
END IF;
END IF;
dummy_div_over <= ('0'&OP1out(31 downto 16))-('0'&OP2out(15 downto 0));
IF opcode(8)='1' AND OP2out(15) ='1' THEN
dummy_div_sub <= (div_reg(31 downto 15))+('1'&OP2out(15 downto 0));
ELSE
dummy_div_sub <= (div_reg(31 downto 15))-('0'&OP2out(15 downto 0));
END IF;
IF (dummy_div_sub(16))='1' THEN
div_quot(31 downto 16) <= div_reg(30 downto 15);
ELSE
div_quot(31 downto 16) <= dummy_div_sub(15 downto 0);
END IF;
div_quot(15 downto 0) <= div_reg(14 downto 0)&NOT dummy_div_sub(16);
IF execOPC='1' AND opcode(8)='1' AND (OP2out(15) XOR div_sign)='1' THEN
dummy_div(15 downto 0) <= 0-div_quot(15 downto 0);
ELSE
dummy_div(15 downto 0) <= div_quot(15 downto 0);
END IF;
IF div_sign='1' THEN
dummy_div(31 downto 16) <= 0-div_quot(31 downto 16);
ELSE
dummy_div(31 downto 16) <= div_quot(31 downto 16);
END IF;
IF (opcode(8)='1' AND (OP2out(15) XOR div_sign XOR dummy_div(15))='1' AND dummy_div(15 downto 0)/=X"0000") --Overflow DIVS
OR (opcode(8)='0' AND dummy_div_over(16)='0') THEN --Overflow DIVU
set_V_Flag <= '1';
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Movem
-----------------------------------------------------------------------------
PROCESS (reset, clk, movem_mask, movem_muxa ,movem_muxb, movem_muxc)
BEGIN
IF movem_mask(7 downto 0)="00000000" THEN
movem_muxa <= movem_mask(15 downto 8);
movem_regaddr(3) <= '1';
ELSE
movem_muxa <= movem_mask(7 downto 0);
movem_regaddr(3) <= '0';
END IF;
IF movem_muxa(3 downto 0)="0000" THEN
movem_muxb <= movem_muxa(7 downto 4);
movem_regaddr(2) <= '1';
ELSE
movem_muxb <= movem_muxa(3 downto 0);
movem_regaddr(2) <= '0';
END IF;
IF movem_muxb(1 downto 0)="00" THEN
movem_muxc <= movem_muxb(3 downto 2);
movem_regaddr(1) <= '1';
ELSE
movem_muxc <= movem_muxb(1 downto 0);
movem_regaddr(1) <= '0';
END IF;
IF movem_muxc(0)='0' THEN
movem_regaddr(0) <= '1';
ELSE
movem_regaddr(0) <= '0';
END IF;
movem_bits <= ("0000"&movem_mask(0))+("0000"&movem_mask(1))+("0000"&movem_mask(2))+("0000"&movem_mask(3))+
("0000"&movem_mask(4))+("0000"&movem_mask(5))+("0000"&movem_mask(6))+("0000"&movem_mask(7))+
("0000"&movem_mask(8))+("0000"&movem_mask(9))+("0000"&movem_mask(10))+("0000"&movem_mask(11))+
("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15));
IF reset = '0' THEN
movem_busy <= '0';
movem_addr <= '0';
maskzero <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND get_movem_mask='1' THEN
movem_mask <= data_read(15 downto 0);
END IF;
IF clkena_in='1' AND test_maskzero='1' THEN
IF movem_mask=X"0000" THEN
maskzero <= '1';
END IF;
END IF;
IF clkena_in='1' AND endOPC='1' THEN
maskzero <= '0';
END IF;
IF clkena='1' THEN
IF set_movem_busy='1' THEN
IF movem_bits(4 downto 1) /= "0000" OR opcode(10)='0' THEN
movem_busy <= '1';
END IF;
movem_addr <= '1';
END IF;
IF movem_addr='1' THEN
CASE movem_regaddr IS
WHEN "0000" => movem_mask(0) <= '0';
WHEN "0001" => movem_mask(1) <= '0';
WHEN "0010" => movem_mask(2) <= '0';
WHEN "0011" => movem_mask(3) <= '0';
WHEN "0100" => movem_mask(4) <= '0';
WHEN "0101" => movem_mask(5) <= '0';
WHEN "0110" => movem_mask(6) <= '0';
WHEN "0111" => movem_mask(7) <= '0';
WHEN "1000" => movem_mask(8) <= '0';
WHEN "1001" => movem_mask(9) <= '0';
WHEN "1010" => movem_mask(10) <= '0';
WHEN "1011" => movem_mask(11) <= '0';
WHEN "1100" => movem_mask(12) <= '0';
WHEN "1101" => movem_mask(13) <= '0';
WHEN "1110" => movem_mask(14) <= '0';
WHEN "1111" => movem_mask(15) <= '0';
WHEN OTHERS => null;
END CASE;
IF opcode(10)='1' THEN
IF movem_bits="00010" OR movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
END IF;
END IF;
IF movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
movem_addr <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1021.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n01i01021ent IS
END c06s03b00x00p10n01i01021ent;
ARCHITECTURE c06s03b00x00p10n01i01021arch OF c06s03b00x00p10n01i01021ent IS
BEGIN
B1:Block
signal s1 : BIT;
begin
TESTING: PROCESS
BEGIN
wait for 1 ns;
END PROCESS TESTING;
B2:Block
signal s2 : BIT;
begin
TEST : PROCESS
BEGIN
s2 <= B1.s1;
wait for 2 ns;
assert NOT(s2='0')
report "***PASSED TEST: c06s03b00x00p10n01i01021"
severity NOTE;
assert (s2='0')
report "***FAILED TEST: c06s03b00x00p10n01i01021 - Entity declaration does not occur in construct specifed by the prefix."
severity ERROR;
END PROCESS TEST;
end block B2;
end block B1;
END c06s03b00x00p10n01i01021arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1021.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n01i01021ent IS
END c06s03b00x00p10n01i01021ent;
ARCHITECTURE c06s03b00x00p10n01i01021arch OF c06s03b00x00p10n01i01021ent IS
BEGIN
B1:Block
signal s1 : BIT;
begin
TESTING: PROCESS
BEGIN
wait for 1 ns;
END PROCESS TESTING;
B2:Block
signal s2 : BIT;
begin
TEST : PROCESS
BEGIN
s2 <= B1.s1;
wait for 2 ns;
assert NOT(s2='0')
report "***PASSED TEST: c06s03b00x00p10n01i01021"
severity NOTE;
assert (s2='0')
report "***FAILED TEST: c06s03b00x00p10n01i01021 - Entity declaration does not occur in construct specifed by the prefix."
severity ERROR;
END PROCESS TEST;
end block B2;
end block B1;
END c06s03b00x00p10n01i01021arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1021.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p10n01i01021ent IS
END c06s03b00x00p10n01i01021ent;
ARCHITECTURE c06s03b00x00p10n01i01021arch OF c06s03b00x00p10n01i01021ent IS
BEGIN
B1:Block
signal s1 : BIT;
begin
TESTING: PROCESS
BEGIN
wait for 1 ns;
END PROCESS TESTING;
B2:Block
signal s2 : BIT;
begin
TEST : PROCESS
BEGIN
s2 <= B1.s1;
wait for 2 ns;
assert NOT(s2='0')
report "***PASSED TEST: c06s03b00x00p10n01i01021"
severity NOTE;
assert (s2='0')
report "***FAILED TEST: c06s03b00x00p10n01i01021 - Entity declaration does not occur in construct specifed by the prefix."
severity ERROR;
END PROCESS TEST;
end block B2;
end block B1;
END c06s03b00x00p10n01i01021arch;
|
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`protect end_protected
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57632)
`protect data_block
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`protect end_protected
|
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